VLSI Circuit Design Process

(Module-II, VLSI Design)

Dr. Kumar Gaurav

Dept. of Electronics & Communication Engineering, NIT Patna
Email: [email protected]
Contact No: +91-8470077459
Office: Faculty Room, 5th Floor, Nano Building, NIT Patna, Bihar
Module-II

VLSI Circuit Design Processes: Basic CMOS Technology, n-well CMOS process, p-
well CMOS process, Twin tub process, Silicon on insulator; CMOS process
enhancement-Interconnect; circuit elements,

Stick Diagrams, Design Rules and Layouts, Lambda based design rules, Contact
cuts, CMOS Lambda and Micron based design rules, Layout Diagrams for logic
gates, Transistor structures, wires and vias,

Scaling of MOS circuits- Scaling models, scaling factors, scaling factors for device
parameters, Limitations of Scaling

2
Integrated Circuits (IC)

❖ IC or chip, an assembly of electronic components, fabricated as a single unit, in which miniaturized

active devices (e.g., transistors and diodes) and passive devices (e.g., capacitors and resistors)
and their interconnections are built up on a thin substrate of semiconductor material (typically silicon).

❖ Wafer: 1-inch, t < 250µm; 2-inch, t: 275 µm; 3-inch, t: 375 µm; 4-inch, t: 525 µm; 4.9 inch, t: 625 µm;
5.9 inch, t: 675 µm; 7.9 inch, t: 725 µm; 11.8 inch, t: 775 µm; 17.7 inch (proposed)

❖ Die: The die or processor die is a rectangular pattern on a wafer that contains
circuitry to perform a specific function.

❖ Chip: When single die is packaged, it is called chip.

Silicon Wafer

Die Chip 3
Integrated Circuits (IC)
❖ Types of ICs:

Based on the method or techniques used in manufacturing them, types of ICs can be divided into three
classes:
▪ Thin and thick film ICs
▪ Monolithic ICs
▪ Hybrid or multichip ICs

Based on the working (I/O):

▪ Digital Integrated Circuits
▪ Analog Integrated Circuits
▪ Mixed Signal ICs

Based on the size: SSI/MSI/LSI/VLSI/ULSI

4
Integrated Circuits (IC)
Based on the method or techniques used in manufacturing them:

❑ Thin and thick film ICs:

In thin or thick film ICs, passive components such as resistors, capacitors are
integrated but the diodes and transistors are connected as separate components to form a
single and a complete circuit.
Thin and thick ICs that are produced commercially are merely the combination
of integrated and discrete (separate) components.

❑ Monolithic ICs:

In monolithic ICs, the discrete components, the active and the passive and also the
interconnections between then are formed on a silicon chip. The word monolithic is
actually derived from two Greek words “mono” meaning one or single and Lithos
meaning stone.
Thus, monolithic circuit is a circuit that is built into a single crystal.

Monolithic ICs
5
Integrated Circuits (IC)
Monolithic ICs: (Contd…)

▪ Monolithic ICs are the most common types ICs in use today.
▪ Its cost of production is cheap and is reliable.
▪ Commercially manufactured ICs are used as amplifiers, voltage regulators, in AM receivers,
and in computer circuits.
▪ The insulation between the components of monolithic ICs is poor.
▪ It also have low power rating, fabrication of insulators is not that possible and so many other
factors.

❑ Hybrid or Multi chip ICs:

As the name implies, “Multi”, more than one individual chips are interconnected. The active
components that are contained in this kind of ICs are diffused transistors or diodes.
The passive components are the diffused resistors or capacitors on a single chip.

Its performance is better than that of monolithic ICs.

6
Hybrid ICs
Integrated Circuits (IC)

Based on the working (I/O):

❑ Digital Integrated Circuits:

These types of ICs work on the basic digital system i.e. two defined level which is 0’s and
1’s (in other words, Low and High or ON and OFF respectively). Microprocessor and Micro
controller is the example of Digital ICs which contains of million of flip flops and logic gates.

❑ Analog Integrated Circuits:

Analog ICs work by processing continuous signals i.e. analog signal. OP-AMP
(Operational Amplifier), NE 555 Timers and Sensors are the example of Analog ICs. These
types of ICs are used for amplification, filtering, modulation, demodulation etc.

❑ Mixed Signal ICs:

Mixed Signal Integrated Circuit is a kind of ICs where both Digital and Analog ICs are
combine on a single chip.

Based on the size: (already discussed)

7
Si Wafer Preparation

Silicon Wafer Preparation

▪ The most commonly available natural sources of silicon are silica and silicates. At present, silicon-
made devices constitute over 95% of all semiconductor devices.

▪ The starting material for Si wafer manufacture is called Electronic grade Si (EGS).

▪ This is an ingot of Si that can be shaped and cut into the final wafers.

▪ EGS should have impurity levels of the order of ppb.

▪ To get EGS, the starting material is called Metallurgical grade Si (MGS).

▪ The first step is the synthesis of MGS from the ore.

8
 Si Wafer Preparation

▪ The starting material for Si manufacture is quartzite (SiO2) or sand. The ore is
reduced to Si by mixing with coke and heating in a submerged electrode arc furnace.

SiC (s) + SiO2 (s)→Si (l) + SiO (g) + CO (g)

▪ The Si (l) formed is removed from the bottom of the furnace.

▪ This is the MGS and is around 98% pure.

▪ Further purification is needed to make EGS since the impurity concentration must be reduced to ppb
levels.

▪ One of the techniques for converting MGS to EGS is called the Seimens process.

▪ The final material obtained is the EGS. This is a polycrystalline form of Si, like MGS, but has much
smaller impurity levels, closer to what is desired in the final single crystal wafer.

9
Si Wafer Preparation

▪ EGS is still polycrystalline and needs to be converted into a single crystal Si ingot for producing
the wafers.

▪ There are two main techniques for converting polycrystalline EGS into a single crystal ingot,
which are used to obtain the final wafers.

Czochralski technique (CZ):

• This is the dominant technique for manufacturing single crystals.
• It is especially suited for the large wafers that are currently used in IC fabrication.

Float zone technique:

• This is mainly used for small sized wafers.
• The float zone technique is used for producing specialty wafers that have low oxygen impurity
concentration.

10
Si Wafer Preparation

▪ After the single crystal is obtained, this needs to be further processed to produce the wafers.
For this, the wafers need to be shaped and cut.

▪ Usually, industrial grade diamond tipped saws are used for this process.

▪ The shaping operations consist of two steps:

• The seed and tang ends of the ingot are removed.
• The surface of the ingot is ground to get an uniform diameter across the length of the ingot.

▪ After the orientation and resistivity checks, one or more flats are ground along the length of the ingot.

▪ There are two types of flats.

✓ Primary flat: this is ground relative to a specific crystal direction. This acts as a
visual reference to the orientation of the wafer.

✓ Secondary flat: this used for identification of the wafer, dopant type and orientation.

11
nMOS Transistor Fabrication

❖ There are a large number and variety of basic fabrication steps used in the production of modern MOS
ICs.
The same process can be used for the designed of nMOS or pMOS or CMOS devices.

❖ The gate material could be either metal or poly-silicon.

Fabrication Steps: (nMOS Transistor Fabrication)

Step 1:

▪ Processing is carried on single crystal silicon of high purity on which required p-type impurities are
introduced as crystal is grown.

▪ Such wafers are vary in diameter and they are doped with say boron to impurity concentration
of 1015/cm3 to 1016 /cm3.

Si Substrate

12
nMOS Fabrication
Step 2: Oxidation

▪ A layer of SiO2 typically 1 micrometer thick is grown all over the surface of the wafer to protect
the surface, acts as a barrier to the dopant during processing, and provide a generally
insulating substrate on to which other layers may be deposited and patterned.

SiO2

Si Substrate

The role of SiO2 in IC fabrication is as below :

▪ It acts as a diffusion mask permitting selective diffusions into silicon wafer through the window
etched into oxide.

▪ It is used for surface passivation which is nothing but creating protective SiO2 layer on the
wafer surface. It protects the junction from moisture and other atmospheric
contaminants.

▪ It serves as an insulator on the wafer surface. Its high relative dielectric constant, which enables
metal line to pass over the active silicon regions.
▪ SiO2 acts as the active gate electrode in MOS device structure.
▪ It is used to isolate one device from another.
▪ It provides electrical isolation of multilevel metallization used in VLSI. 13
nMOS Fabrication
Dry oxidation: The oxidation takes place under pure oxygen atmosphere. The silicon and
oxide react to form silicon dioxide:
Si + O2→SiO2

This process is done at 1000 to 1200 °C actually. To create a very thin and stable oxide the
process can be done at even lower temperatures of about 800 °C.

Characteristic of the dry oxidation:

✓ slow growth of oxide
✓ high density
✓ high breakdown voltage

Wet oxidation: In wet thermal oxidation, the oxygen is led through a bubbler vessel filled with
heated water (about 95 °C), so that in addition to oxygen water is present in the quartz tube as
steam. The oxidation is given by:

Si + 2H2O→SiO2 + 2H2

This process is done by 900 to 1000°C.

Characteristics o f t h e wet oxidation:

✓ fast growth even on low temperatures
✓ less quality than dry oxides
14
nMOS Fabrication
Step 3: Masking and Photolithography

Photolithography is a patterning process in which a photosensitive polymer is selectively exposed to

light through a mask, leaving a latent image in the polymer that can then be selectively dissolved to
provide patterned access to an underlying substrate.

Steps:

✓ Uniformly covers of the substrate with photoresist

✓ Selectively exposes with a mask

✓ Develops the photoresist to define the desirable patterns

✓ Suitable for pattern definition with small feature sizes

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nMOS Fabrication
Step 3: Masking and Photolithography (Contd…)

The exterior (surface) is now enclosed with the photo oppose which is deposit onto the wafer
and spun to an even distribution of the necessary thickness.

Photoresist
SiO2

Si Substrate

✓ The photoresist coating is then uncovered to ultraviolet (UV) light through masking
which describes those areas into which transmission is to take place as one with transistor channels.

✓ Suppose, for example, that those areas uncovered to UV radiations are polymerized, but that the
areas necessary for diffusion are protected by the cover and remain unchanged.

✓ These regions are consequently readily fixed away together with the original silicon dioxide so that
the surface of the wafer is uncovered in the window defined by the mask.

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nMOS Fabrication
There are two types of photoresist: positive and negative

Positive tone resists:

✓ The resist is exposed with UV light where the underlying material is to be removed.
✓ In these resists, exposure to the UV light changes the chemical structure of the resist so that it
becomes more soluble in the developer.
✓ The exposed resist is then washed away by the developer solution, leaving windows of the bare
underlying material.
✓ The mask, therefore, contains an exact copy of the pattern which is to remain on the wafer,
as a stencil for subsequent processing.
✓ Example: PMMA Series

Negative tone resists:

✓ Negative tone resists behave in the opposite manner.

✓ When exposed to the UV light, the negative resist becomes crosslinked/polymerized, and more
difficult to dissolve in developer.
✓ Therefore, the negative resist remains on the surface of the substrate where it is exposed, and the
developer solution removes only the unexposed areas.
✓ Masks used for negative photoresists, therefore, contain the inverse or photographic
"negative" of the pattern to be transferred. The figure above shows the pattern differences generated
from the use of a positive and negative resist.
✓ Example: SU-8 Series

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nMOS Fabrication
Step 3: Masking and Photolithography (Contd…)

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nMOS Fabrication
Step 3: Masking and Photolithography (Contd…)
✓ The photo resist layer is then exposed to ultraviolet light through masking which defines those
regions into which diffusion is to take place together with transistor channels.

✓ The opaque region at the mask allow the ultraviolet light to hit the surface of the photoresist at
the substrate and making it dissolve.

UV light exposed to the substrate

Photoresist surface that hit by the UV light dissolve The uncovered dissolve while the covered region 19
remain
nMOS Fabrication
Step 4: Etching

Etching is the process of selective removal of regions of a semiconductor, metal, or silicon dioxide.

Classified as dry and wet etch.

✓ In wet etching, the wafers are immersed in a chemical solution at a predetermined

temperature. In this process, the material to be etched is removed equally in all directions so
that some material is etched from regions where it is to be left. This becomes a serious problem
when dealing with small dimensions.

✓ In dry (or plasma) etching, the wafers are immersed in a gaseous plasma created by a
radio-frequency electric field applied to a gas such as argon. The wafer to be etched is
placed on an electrode and is subjected to the bombardment of its surface by gas ions. As a
result, atoms at or near the surface to be etched are removed by the transfer of momentum from
the ions to the atoms.

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nMOS Fabrication

Step 4: Etching (Contd…)

The substrate now is ready to be etched to remove the remaining photoresist at the substrate
and to create an opening at the substrate.

In this process, Hydrofluoric acid is used as its etch acid.

Hydrofluoric acid used as etch acid The remaining photoresist removed and an opening to
the substrate created.

21
nMOS Fabrication
Step 5:

A layer of the thin oxide is form SiO2 (0.1 micrometer typical) is grown over the entire chip
surface at high temperature.

A layer of thin oxide grown at the surface of the substrate

Step 6:

The polysilicon layer consists of heavily doped polysilicon deposited at the surface of the substrate by
chemical vapor deposition (CVD).

Polysilicon is deposited at the surface of the substrate.

22
nMOS Fabrication

Step 7:

Photoresist is done for the second time at the surface of the substrate.

Substrate is coated with photoresist

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nMOS Fabrication
Step 8:

The photolithography process also done for the second time.

The process is done to create a new pattern to make a polysilicon gate at the center of the
substrate.

Photo-mask is in Photoresist surface that hit

position for patterning by the UV light dissolve

The uncovered dissolve while

UV light exposed to the covered region remain
the substrate
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nMOS Fabrication

Step 9:

The substrate is now etch with hydrofluoric acid to remove the remaining photoresist and polysilicon. As
a result, a polysilicon gate is formed at the center of the substrate.

Polysilicon gate created

Hydrofluoric acid used as etch acid

25
nMOS Fabrication

Step 10: Ion Implantation

This is a process of introducing dopants into selected areas of the surface of the wafer by
bombarding the surface with high-energy ions of the particular dopant.

✓ In this process, Substrate is bombarded by an amount of arsenic or phosphorus electron to create

N region to form drain and source.

Arsenic or phosphorus ion bombarded at N region formed at the substrate representing

the substrate. source and drain

26
nMOS Fabrication

Step 11: Annealing

Annealing is a heat treatment that alters the physical and sometimes chemical properties of a
material to increase its ductility and reduce its hardness, making it more workable.

✓ After the ion implantation done, the annealing process is conducted to repair the single crystal
structure of the substrate and active the dopant.

The annealing process done to repair the single

crystal structure

27
nMOS Fabrication
Step 12:

Oxidation process is conducted once more to grow an insulating oxide at the substrate.

The growth of insulating oxide

Step 13:

Photoresist is conducted once more at the surface of the substrate.

28
Photoresist coated the substrate
nMOS Fabrication
Step 14:

Another photolithography is done to create an opening to metallization process.

Masking process UV light exposed to the substrate

Photoresist surface that hit by the UV The uncovered dissolve while the
light dissolve covered region remain
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nMOS Fabrication
Step 15:

The substrate is now etched remove the remaining photoresist. As a result creating
an opening for metallization process.

Etching process to remove photoresist An opening created through etching

and create an opening

30
nMOS Fabrication

Step 16: Metallization and interconnections

After all semiconductor fabrication steps of a device or of an integrated circuit are completed, it
becomes necessary to provide metallic interconnections for the integrated circuit and for
external connections to both the device and to the IC.

✓ The substrate then has metal (aluminum) deposited over its surface to a thickness typically of 1
micrometer. Aluminum evaporated to cover surface. This metal layer is then masked and etched to
form the required interconnection pattern.

Aluminum evaporated to cover the surface of Aluminum etched to form Metal

the surface contact

31
nMOS Fabrication

Step 17:

Then passivation layer is created with an oxide layer to protect against contamination and
increase electrical stability at the substrate.

The substrate then coated by the

passivation layer

NOTE: Similar process flow can be considered of pMOS fabrication.

32
CMOS Fabrication

▪ CMOS fabrication methods:

▪ n-well or p-well process

▪ Twin-Tub Process

▪ Silicon On Insulator process

I. n-well or p-well process

By this process, CMOS can be obtained by integrating both nMOS and pMOS transistors over the same
silicon wafer.

▪ n-well: The pMOS transistors are placed in the n-well and the nMOS transistors are created on
the substrate.

▪ p-well: The nMOS transistors are placed in the p-well and the pMOS transistors are created on
the substrate.

▪ The CMOS fabrication process flow is conducted using basic fabrication steps
while manufactured using n-well/p-well technology.
33
 CMOS Fabrication

Ref: CMOS digital integrated

circuits analysis and design,
Sung-Mo Kang (Author), Yusuf
Leblebici (Author)

Simplified process sequence for the fabrication of the n-well CMOS integrated 34
circuit with a single polysilicon layer, showing only major fabrication steps
CMOS Fabrication

Using n-well

Step 1: First we choose a substrate as a base for fabrication. For n-well, a p-type silicon substrate is
selected.

Step 2: Oxidation

35
CMOS Fabrication

Step 3: Growing of Photoresist: At this stage to permit the selective etching, the SiO2 layer is
subjected to the photolithography process. In this process, the wafer is coated with a
uniform film of a photosensitive emulsion.

Step 4: Masking: This step is the continuation of the photolithography process. In this step, a
desired pattern of openness is made using a mask, over the photoresist. The substrate is now
exposed to UV rays the photoresist present under the exposed regions of mask gets soluble.

36
CMOS Fabrication
Step 5: Removal of Unexposed Photoresist: The mask is removed and the unexposed region of
photoresist is dissolved by developer solution.

Step 6: Etching: The wafer is immersed in an etching solution i.e., hydrofluoric acid, which
removes the oxide from the areas through which dopants are to be diffused or ion implanted.

37
CMOS Fabrication

Step 7: Removal of Whole Photoresist Layer: During the etching process, those portions of SiO2 which
are protected by the photoresist layer are not affected. The photoresist mask is now stripped off with a
chemical solvent (hot H2SO4).

38
CMOS Fabrication

Step 8: Formation of n-well: The n-type impurities are diffused by diffusion or ion implantation
into the p-type substrate through the exposed region, thus forming an n- well.

Step 9: Removal of SiO2: The layer of SiO2 is now removed by using hydrofluoric acid.

39
CMOS Fabrication

Step 10: Deposition of Polysilicon: The misalignment of the gate of a CMOS transistor would
lead to the unwanted capacitance which could harm circuit. So to prevent this “Self- aligned gate
process” is preferred where gate regions are formed before the formation of source and drain
using ion implantation.

✓ Polysilicon is deposited by using Chemical Deposition Process over a thin layer of gate oxide.
✓ This thin gate oxide under the Polysilicon layer prevents further doping under the gate region.

40
CMOS Fabrication

Step 11: Formation of Gate Region: Except the two regions required for formation of the gate for
nMOS and pMOS transistors the remaining portion of Polysilicon is stripped off.

Step 12: Oxidation Process: An oxidation layer is deposited over the wafer which acts as a shield for
further diffusion and metallization processes.

41
CMOS Fabrication

Step 13: Masking and Diffusion: For making regions for diffusion of n-type impurities
using masking process small gaps are made.

✓ Using diffusion process three n+ regions are developed for the formation of terminals of nMOS.

42
CMOS Fabrication

Step 14: Removal of Oxide: The oxide layer is stripped off.

Step 15: P-type Diffusion: Similar to the n-type diffusion for forming the terminals of pMOS, three p+ type
diffusion are carried out.

43
CMOS Fabrication
Step 16: Laying of Thick Field oxide: Before forming the metal terminals a thick field oxide is
laid out to form a protective layer for the regions of the wafer where no terminals are required.

Step 17: Metallization: This step is used for the formation of metal terminals which can provide
interconnections. Aluminum is spread on the whole wafer.

✓ Al is sputtered over the entire area filling contact cuts too.

✓ Metal is patterned with the metal mask.

44
CMOS Fabrication
Step 18: Removal of Excess Metal: The excess metal is removed from the wafer.

Step 19: Formation of Terminals and naming them: In the gaps formed after removal of excess metal
terminals are formed for the interconnections and the names are assigned to the terminals.

Using p-well

The p-well process is similar to n-well process except that here n-type substrate is used and p-type
diffusions are carried out for well. For simplicity usually, n-well process is preferred. 45
 CMOS Fabrication
Using n-well; Inverter cross-section
Step 17:
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Step 17: Substrate must be tied to GND, n-well to VDD Use heavily doped well and substrate contacts/taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

46
CMOS Fabrication
Detailed Mask Views
✓ Transistors and wires are defined by masks.

❖ Six masks
– n-well
n well

– Polysilicon
– n+ diffusion
– p+ diffusion Po l ysil ic o n

– Contact
– Metal n + D if f u sio n

p + D if f u sio n

Contact

Me t a l

47
CMOS Fabrication
Detailed Mask Views.

❖ Six masks

n-well
p substrate

Polysilicon

Polysilicon
Polysilicon
Thin gate oxide

n well
p substrate

48
CMOS Fabrication

n+ Diffusion

n+ diffusion

n well
p substrate

p+ Diffusion

p+ diffusion
p+ n+ n+ p+ p+ n+

n well
p substrate

49
CMOS Fabrication

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
Contact n well
p substrate

Metal

Metal Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate 50
CMOS Inverter

Ref: CMOS digital integrated

circuits: analysis and design,
Sung-Mo Kang (Author), Yusuf
Leblebici (Author)

The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and
one pMOS transistor (in the n-well), and the polysilicon and metal interconnections.
51
The final step is to deposit the passivation layer (for protection) over the chip, except over wire-bonding
pad areas. After Atlas of IC Technologies, by W. Maly.
CMOS Inverter

Inverter Mask Set:

✓ Transistors and wires are defined by masks
✓ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

52
CMOS Fabrication

II. Twin-tub/well process

Twin Tub/well Fabrication of CMOS:

✓ Twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-type
transistors.

✓ Doping of substrate and diffusion regions can be controlled in an independent manner. This helps in
overcoming latch-up.

✓ One can optimize independently for threshold voltage, body effect, and the gain associated with n-
and p-devices.

✓ Epitaxy: Epitaxy refers to the deposition of a crystalline overlayer on a crystalline substrate. The
overlayer is called an epitaxial film or epitaxial layer. The term epitaxy comes from the Greek roots
epi, meaning "above", and taxis, meaning "an ordered manner".

53
CMOS Fabrication
Twin-Tub/well Fabrication of CMOS:

Various steps involved in the fabrication of CMOS using Twin-tub method are as follows:

✓ A lightly doped n or p-type substrate is taken and the epitaxial layer is used. Epitaxial layer
protects the latch-up problem in the chip.

✓ The starting material for this process is p+ substrate with epitaxial grown p-layer which is also called
as epilayer.

✓ The high purity silicon layers with measured thickness and exact dopant concentration are grown.

✓ Formation of tubes for p and n well.

✓ Thin oxide construction for protection from contamination during diffusion processes.

✓ Source and drain are formed using ion implantation methods.

✓ Cuts are made for making portions for metal contacts.

✓ Metallization is done for drawing metal contacts

54
Twin-tub CMOS process

Selection of Substrate: The twin-tub CMOS process starts with a high resistive n-type silicon substrate.

Generally, the starting material is a high resistivity n+ or p+ substrate with lightly doped epitaxial or epi
layer on the top to protect latch up. This epitaxial layer acts the actual substrate on which the n-well and
the p-well are formed.

Deposition of Epitaxial Layer : n-type silicon substrate is cleaned and an epitaxial layer is deposited over
the same.

55
Developing thick oxide layer (1µm) using oxidation

Lithography (MASK1) for defining window for n-well.

56
Removal of soluable photo resist using organic solvents

Etching of uncovered thick oxide using HF (Hydrofluoric acid)

57
Removal of hardened photo resist by oxide cleaning and PR etching

Formation of N-well using ion implantation

58
Formation of P-well using ion implantation

Oxide cleaning and developing thin oxide

59
Deposition of Polysilicon layer

Lithography (MASK2) to pattern polysilicon

60
61
Lithography(MASK3)

Use n+ MASK (MASK 3) to define area for n-region

62
Formation of n+ regions by ion implantation

Lithography p+ MASK (MASK4) for PMOS

Similar steps (MASK 4) are used to create p+ regions by ion implantation

63
Thick Oxide Deposition
Cover the entire surface with thick oxide layer

Lithography (MASK 5) for Oxide Patterning

Oxide layer is masked with photoresist and etched to expose selected areas where contact cuts are
to be made

64
Metallization and MASK 6 for Metal Patterning

Connections are made to drain, source and gate terminals.

65
CMOS Fabrication
III. Silicon On Insulator process

Silicon on insulator (SOI) technology refers to the use of a layered silicon–insulator–silicon

substrate in place of conventional silicon in semiconductor Manufacturing.

66
CMOS Fabrication

Why SOI? Or
Need for SOI Technology

As MOSFET’s are scaled down to near and sub-micrometer dimensions, small geometry effects alter
their device characteristics (Parasitic Effects are pronounced).

• The SOI CMOS technology allows the creation of independent, completely isolated nMOS and
pMOS transistors virtually side-by-side on an insulating substrate.

• The main advantages of this technology are the higher integration density (because of the
absence of well regions), complete avoidance of the latch-up problem, and lower parasitic
capacitances compared to the conventional p & n-well or twin- tub CMOS processes.

• Compatible with existing fabrication process without any special equipment or retooling of an
existing factory

67
CMOS Fabrication
SOI Technology

SOI-based devices differ from conventional silicon built devices in that the silicon junction is above an
electrical insulator, typically silicon dioxide or sapphire

In a Silicon On Insulator (SOI) Fabrication technology , Transistors are encapsulated in SiO2 on all
sides. 68
CMOS Fabrication

The choice of insulator depends largely on intended application:

• Sapphire is used for high performance radio frequency (RF) and radiation-sensitive applications.

• Silicon dioxide is used for diminished short channel effects in microelectronics devices.

BOX: Buried Oxide

69
CMOS Fabrication
Bulk silicon and Silicon on Insulator (SOI) MOSFET

70
CMOS Fabrication
SIMOX (Separation by IMplanted OXygen)

There are two essential stages of the process:

ion implantation and annealing.

In the implantation stage, oxygen ions are

implanted in the silicon wafer and react with the
silicon to form silicon dioxide precipitates.
However, the implantation causes considerable
damage to the wafer and the layer of silicon
dioxide precipitates is not continuous.

Thus, high-temperature annealing helps repair

the damage and form the oxide precipitates into a
continuous layer. Now, the silicon's quality is
restored and the buried oxide (BOX) layer can
act as a highly effective insulator

71
• Latchup refers to short circuit/low impedance
path formed between power and ground rails
in an IC leading to high current and damage
to the IC.

• It occurs due to interaction between parasitic

pnp and npn transistors.

72
• The structure formed by these resembles a Silicon Controlled
rectifier (SCR).

• These form a positive feedback loop, by short circuiting the

power rail and ground rail, which eventually causes excessive
current, and can even permanently damage the device.

73
CMOS Process Enhancement
CMOS process enhancement

• In the Analog, Digital or RF CMOS integrated circuits along with transistors other elements such as
interconnects, resistors, capacitors are to be integrated on chip.

• In order to achieve this, enhancements in CMOS process technology is required.

• The main goals of adding CMOS enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.

(3) To provide routing of interconnects.

• These enhancements in CMOS technology includes:

• Multilevel metal layers

• Multilevel poly layers

• Combination of both. 74
CMOS Process Enhancement

Transistors

▪ Multiple threshold voltages and oxide thicknesses

• Processes offer multiple threshold voltages

• Low threshold devices: faster, higher leakage. High threshold devices: opposite
• Thin oxides: provide high ON currents but cannot handle high voltages (e.g. I/Os)
• Thicker oxides provided for I/O devices

▪ Silicon on Insulator

• As the name suggests transistors are fabricated on an insulator (SiO2 or sapphire).

• Insulating substrate eliminates capacitance between the source/drain and body, higher speed
devices and low leakage currents.

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CMOS Process Enhancement
▪ High-k gate dielectrics

• Transistors need high gate capacitance to attract charge to the channel.

• Thin gates and therefore high gate leakages
• Thicker gates that leak less can be made with high-k materials. E.g. Hafnium Oxide (k=20),
Zirconium Oxide (k=23), Silicon Nitride (k=6.5-7.5)

▪ Low leakage transistors

• Scaling transistors causes exponential increase in subthreshold leakages.

• Can be improved using gate structure where gates is placed on more than one side of the
channel.

These devices are generically

called finFETs.

▪ Higher mobility
▪ Plastic transistors
▪ High-voltage transistors
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CMOS Process Enhancement
Interconnects

• The most important enhancement in CMOS processes is the additions of signal and power supply
routing layers. The advantage of this type of routing is it improves power and clock distribution to
the different modules inside the chip.

• The interconnect layers involved in process are :

(1) Metal interconnect

(2) Polysilicon interconnect

(3) Local interconnect.

• The second layer of metal interconnect (Metal 2) is required for digital Integrated circuits. The
connection between first metal layer (Metal 1) and second metal layer (Metal 2) is established with
the help of via. For high speed chips third metal layer (Metal 3) is also required.

• Polysilicon Interconnect layers are used in ICs because of its high melting points as compare to
Al. But the major problem with polysilicon interconnect is it has high sheet resistance because of
this for long distance interconnects this provides significant delay.

• If silicide is used as a interconnect layer for connecting different cells then it is called as local
interconnect. The important advantage of local interconnect is it allows direct connection between
polysilicon and diffusion regions due to this metal contacts are eliminated which reduces the chip
area. 77
CMOS Process Enhancement

Circuit Elements

Resistor

Capacitor

78
Design Rules & Layout

Introduction:

▪ Design rules are a set of geometrical specifications that dictate the design of the layout.

▪ Layout is top view of a chip.

▪ Design process are aided by stick diagram and layout.

▪ Stick diagram gives the placement of different components and their connection details but the

dimensions of devices are not mentioned.

▪ Circuit design with all dimensions is Layout.

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Design Rules & Layout

▪ Fabrication process needs different masks, these masks are prepared from layout.

▪ Layout is an Interface between circuit designer and fabrication engineer.

▪ Layout is made using a set of design rules.

▪ Design rules allow translation of circuit (usually in stick diagram or symbolic form) into actual
geometry in silicon wafer.

▪ These rules usually specify the minimum allowable line widths for physical objects on- chip.

▪ Example: metal, polysilicon, interconnects, diffusion areas, minimum feature dimensions, and
minimum allowable separations between two such features.

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Design Rules & Layout

Need for Design Rules:

▪ Better area efficiency
▪ Better yield
▪ Better reliability
▪ Increase the probability of fabricating a successful product on Si wafer.

If design rules are not followed:

✓ Functional or non-functional circuit.
✓ Design consuming larger Si area.
✓ The device can fail during or after simulation.

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Design Rules & Layout

Stick Diagrams

▪ A stick diagram is a symbolic representation of a layout.

▪ In stick diagram, each conductive layer is represented by a line of distinct color.

▪ Width of line is not important, as stick diagrams just give only wiring and routing information.

▪ Does show all components/vias, relative placement.

▪ Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries. (Demerits)

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Design Rules & Layout
Colour Codes:

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Design Rules & Layout
Stick Diagrams: Basic Rules

▪ Poly crosses diffusion forms transistor

✓ Red (poly) over Green/yellow(Active), gives a FET.

✓ Aspect Ratio or Transistor size ratio (L:W)

▪ Blue may cross over red or green, without connection.

▪ Connection between layers is specified with X.
▪ Metal lines on different layer can cross one another, connections are done using via.

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Design Rules & Layout

Stick Diagrams: Basic Steps

▪ Normally, the first step is to draw two parallel metal (blue) VDD and GND rails.

▪ There should be enough space between them for other circuit elements.

▪ Next, Active (Green/yellow) paths must be drawn for required transistors.

▪ Do not forget to mark contacts as X, wherever required.

▪ Remember, Poly (Red) crosses Active (Green/yellow), where transistor is required.

▪ For depletion mode FET, draw required implants (yellow). *

▪ Label each transistor with L:W ratio. *

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Design Rules & Layout
Stick Diagrams: Examples

Inverter:

NMOS Inverter: Enhancement load

86
Design Rules & Layout

NMOS Inverter: Depletion load

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Design Rules & Layout

NMOS 2 I/P NAND Gate

88
Design Rules & Layout

NMOS 2 I/P NOR Gate

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Design Rules & Layout
Stick Diagrams: CMOS Inverter

Stick Diagrams: CMOS

Wells

• The various N and P diffusions must be

reverse biased to ensure that those wells are
insulated from each other.
• This requires that the N- wells are connected to
the most positive voltage, VDD.
• The P substrate must be connected to the most
negative voltage, ground.
• This assumes that all other nets are at a voltage
90
between 0V and VDD.
Design Rules & Layout

Stick Diagrams: CMOS-NAND Gate

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Design Rules & Layout

Stick Diagrams: CMOS-NOR Gate

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Design Rules & Layout

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Design Rules & Layout

• Draw the stick diagrams of the following functions:

• Y=AB
• Y=A+B
• Y=(ABC)’
• Y=(A+B+C)’
• Y=AB+BC+CD

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Design Rules & Layout
Types of Layout Design Rules:

▪ λ Based Design Rules

▪ Industry Standard: Micron Rules

λ Based Design Rules

It specify the layout constraints in terms of a single parameter and thus allow linear/
proportional scaling of all geometrical constraints

Industry Standard: Micron Rules

▪ All device dimensions are expressed in terms of absolute dimension (μm/nm).
▪ These rules will not support proportional scaling (i.e., multiples of λ).
▪ Can result in 50% reduction in area over λ based rules
▪ Standard in industry.

Manufacturing Issues and related rules:

▪ Antenna Rules, Layer Density Rules, Resolution Enhancement Rules 95
Design Rules & Layout

Design Rule Entities

1. Layer Representations

• Substrates and/or Wells

• Diffusion Regions (Active areas)
• Select regions: For contacts to substrate or well
• Polysilicon Layers
• Metal Interconnects
• Contact: Metal to active
• Via: Metal to metal

2. Intralayer Constraints

3. Interlayer Constraints

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Design Rules & Layout

Typical design flow for the

production of a mask layout. 97
Design Rules & Layout

Layout Rules of a Minimum-Size MOSFET

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© CMOS Digital Integrated Circuits – 3rd Edition
Design Rules & Layout

Layout Rules of a CMOS

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© CMOS Digital Integrated Circuits – 3rd Edition
Design Rules & Layout

λ Based Design Rules:

▪ Developed by Mead and Conway.

▪ All device dimensions are expresses in terms of a scalable parameter λ.
▪ λ = L/2; L = The minimum feature size of transistor
▪ L= 2 λ
▪ These rules support proportional scaling.
▪ They should be applied carefully in sub-micron CMOS process.
▪ Design rules govern the layout of individual components: transistors, wires,
contacts, vias.
▪ How small can the gates be, and how small can the wires be made?

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Design Rules & Layout

λ Based Design Rules: (contd…)

• In MOS, the minimum feature size of Tr is:

(L/W)n = 1/1 = 2 λ/2 λ

Active area = L*W = 4 λ2

• In CMOS, the minimum feature size of Tr is:

(L/W)n = 1/1.5 = 2 λ/3 λ

Active area = L*W = 6 λ2

• Mentor Graphics/Cadence IC tool has built-in design rule checker (DRC).

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Design Rules & Layout

λ Based Design Rules: (contd…)

• Minimum length or width of a feature on a layer is 2λ.

▪ To allow for shape contraction

• Minimum separation of features on a layer is 2λ.

▪ To ensure adequate continuity of the intervening materials

• Two Features on different mask layers can be misaligned by a maximum of 2λ on the

wafer.

• If the overlap of these two different mask layers can be catastrophic to the design, they
must be separated by at least 2λ.

• If the overlap is just undesirable, they must be separated by at least λ.

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Design Rules (NMOS)

λ Based Design Rules: (contd…)

▪ Minimum width of PolySi and diffusion line 2λ

▪ Minimum width of Metal line 3λ

▪ as metal lines run over a more uneven surface than other conducting layers to
ensure their continuity.

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Design Rules (NMOS)
λ Based Design Rules: (contd…)

▪ PolySi - PolySi spacing 2λ

▪ Metal - Metal spacing 3λ

▪ Diffusion-Diffusion spacing 3λ

To avoid the possibility of their associated regions overlapping and conducting current

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Design Rules (NMOS)

λ Based Design Rules: (contd…)

▪ Diffusion-PolySi spacing λ: To prevent the lines overlapping to form unwanted

capacitor.

▪ Metal lines can pass over both diffusion and polySi without electrical effect. Where
no separation is specified, metal lines can overlap or cross.

105
Design Rules (NMOS)
λ Based Design Rules: (contd…)

▪ It is recommended practice to leave λ between a metal edge and a polySi or diffusion line
to which it is not electrically connected

106
Design Rules (Contact Cut)
λ Based Design Rules: (contd…)

▪ Metal connects to polySi/diffusion by contact cut.

▪ Contact area: 2λ x 2λ

▪ Metal and polySi or diffusion must overlap this contact area by λ so that the two
desired conductors encompass the contact area despite any misalignment
between conducting layers and the contact hole.

107
Design Rules (Contact Cut)
λ Based Design Rules: (contd…)

▪ Contact cut–Contact cut: 2λ apart

▪ Why? To prevent holes from merging.

Interlayer Contacts:

Interconnection between poly and diffusion is done by contacts.

• Metal contact
• Butting contact
• Buried contact 108
Layout
(Butting Contact)
▪ The gate and diffusion of NMOS device can be connected by a butting contact.

▪ Here, metal makes contact to both the diffusion forming the drain of the transistor
and to the polySi forming this device’s gate.

▪ Requires a metal cap

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 Layout
(Butting Contact)

▪ Metallization is required only over the butting

contact holes which are 2 λ x 4λ in size.

▪ A border of width λ around all four sides is

added to ensure proper contact.

▪ This brings the metallization size to 4λ x6λ.

110
 Layout
(Buried Contact)

▪ The buried contact window defines the area where oxide is to be removed so that polySi
connects directly to diffusion.

▪ Contact Area must be a min. of 2 λ x 2λ to ensure adequate contact area.

111
Layout
(Buried Contact)

112
Layout
(Buried Contact)

▪ The buried contact window surrounds this contact by λ in all directions to

avoid any part of this area forming a transistor.

▪ Separated from its related transistor gate by 2λ to prevent gate area from being
reduced.

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λ Based Design Rules:
(Summarized)

▪ Minimum diff width 2λ ▪ Contact size 2λ * 2λ

▪ Minimum poly width 2λ ▪ Contact diff/poly/metal overlap 1λ
▪ Minimum metal width 3λ ▪ Contact to contact spacing 2λ
▪ poly-poly spacing 2λ ▪ Contact to poly/diff spacing 2λ
▪ diff-diff spacing 3λ ▪ Buried contact to active device spacing 2λ
▪ metal-metal spacing 3λ ▪ Buried contact overlap in diff direction 2λ
▪ diff-poly spacing λ ▪ Buried contact overlap in poly direction 1λ
▪ Poly gate extend beyond diff by 2λ ▪ Implant gate overlap 2λ
▪ Diff extend beyond poly by 2λ

114
Design Rules (NMOS)

115
Layout
(NMOS INVERTER- Enhancement load)

116
Layout
(NMOS INVERTER- Enhancement load)

117
Layout
(NMOS INVERTER- Enhancement load)

118
Layout
(NMOS INVERTER Depletion load)

119
Layout
(NMOS INVERTER Depletion load)

120
Layout
(NMOS NAND)

121
Layout
(NMOS NAND)

122
Layout
(NMOS NOR)

123
Layout
(NMOS NOR)

124
Layout
(CMOS Inverter)

125
126