Introduction To Electronics

P2508 Lecture Notes

Instructor:
Naleli J. Matjelo, PhD

National University of Lesotho

Department of Physics & Electronics
P. O. Roma 180
Lesotho
Southern Africa

Office Number: SCI 239

Email Address: [email protected]
Telephone Number: +26652213290
Contents

1 Introduction to Semiconductors 1

1.1 Classification of Solids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Amorphous Solids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.2 Crystalline Solids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Band Structure of Solids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.1 Insulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.2 Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.3 Conductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Semiconductor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.1 Intrinsic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.2 Extrinsic Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Hall Effect in Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 PN Junction Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.2 Forward-Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.5.3 Reverse-Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.6 Semiconductor Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.1 Common Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.6.2 Common Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

i
CONTENTS ii

2 Diodes and Applications 14

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 The Physics of Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Ideal Diode Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.2 Current-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.3 Diode Breakdown Regimes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.3.1 I-V Characteristics In Breakdown Regimes . . . . . . . . . . . . . . . 16

2.2.3.2 Zener Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.3.3 Avalanche Breakdown . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 Basic Diode Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.1 Diode Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.2 The Load Line Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.3 Simple Diode Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.4 Rectifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.5 RF Mixer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.6 Voltage Multiplier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4 Zener Diode Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.1 Zener Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.2 Equivalent Circuit Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.4.3 Voltage Regulation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.4.4 Voltage Clipper Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.5 Voltage Shifter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

CONTENTS iii

3 Bipolar Junction Transistor 25

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.1 Symbols and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.1.2 The Band Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2 BJT Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.1 I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.2 Cutoff Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.3 Saturation Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.4 Active Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3 Common Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.1 Common Base Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.3.2 Common Emitter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3.3 Common Collector Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 Common Circuit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4.1 BJT Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4.2 BJT NAND Gate Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5 BJT vs Other Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.1 Advantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.2 Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 Field Effect Transistors 38

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.1 Some Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1.2 FET Family Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2 Junction Field Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.1 JFET Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.2 JFET I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

CONTENTS iv

4.2.2.1 Ohmic Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2.2 Cut-off Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2.3 Saturation or Active Region . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2.4 Breakdown Region . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.3 JFET As Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.4 JFET NOT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2.5 JFET Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.3 Metal-Oxide Semiconductor Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . 45

4.3.1 Depletion Mode MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.2 Enhancement Mode MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.3 MOSFET Amplifier Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3.3.1 Cut-off Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3.3.2 Ohmic (Linear) Region . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3.3.3 Saturation Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3.4 MOSFET NOT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.3.5 MOSFET Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 Common FET Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.4.1 Common Source Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.4.2 Common Drain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.4.3 Common Gate Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5 Logic Families and Binary Representation 54

5.1 Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.2 Common Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.2.1 TTL Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.1.2.2 ECL Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

CONTENTS v

5.1.2.3 CMOS Logic Family . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1.3 Further Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1.3.1 Types of Logic Family . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1.3.2 Bipolar Logic Family . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.1.3.3 Unipolar Logic Family . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.1.3.4 Classification of Logic Family . . . . . . . . . . . . . . . . . . . . . 57

5.1.3.5 Features of Some Logic Families . . . . . . . . . . . . . . . . . . . . 58

5.1.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.1.5 Comparison and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.2 Binary Number Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.2.1 Number Base Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.2.1.1 Decimal To Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.2.1.2 Binary To Decimal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2.2 Unsigned Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.2.2.2 Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2.3 Signed Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2.3.2 Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2.3.3 Addition Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.2.3.4 Subtraction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2.4 Reflected Binary (or Gray) Code . . . . . . . . . . . . . . . . . . . . . . . . . . 66

CONTENTS vi

6 Logic Gates and Boolean Logic 68

6.1 Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.1.1 Basic Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.1.2 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1.3 AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.4 NOT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.5 NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.1.6 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1.7 XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1.8 XNOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2.1 Boolean Expressions Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2.1.1 Sum of Products (SOP) . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2.1.2 Product of Sums (POS) . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2.1.3 Canonical Form (CF) . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.2 Boolean Algebraic Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.2.1 Annulment Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.2.2.2 Identity Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.2.2.3 Idempotent Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2.4 Complement Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2.5 Commutative Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2.6 Double Negation Law . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2.7 de Morgan´s Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2.2.8 Boolean Postulates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.2.9 Distributive Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.2.10 Absorptive Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

CONTENTS vii

6.2.2.11 Associative Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.3 Boolean Algebra Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2.4 Boolean Logic Laws Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.3 Karnaugh Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.1 Filling Karnaugh Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.1.1 Two-Variable Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.3.1.2 Three-Variable Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.1.3 Four-Variable Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.2 Simplification Using K-map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.2.1 Steps To Follow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6.3.2.2 Grouping Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.3.2.3 An Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7 Latches and Flip-Flops 86

8 Counters and Feedback Circuits 87

Lecture 1

Introduction to Semiconductors

1.1 Classification of Solids

In general solids are classified into two categories with different characteristics:

• Amorphous solids

• Crystalline solids

1.1.1 Amorphous Solids

An amorphous solid is a solid whose constituents are randomly arranged. Some examples of amorphous
solids are glass and plastics. Although amorphous solids consist of microcrystalline structures, their
orderly arrangement is restricted to very short distances of the same order of magnitude as the interatomic
distances.

1.1.2 Crystalline Solids

A crystalline solid is a solid whose constituents manifest an orderly arrangement geometrically. Some
examples of crystalline solids are sodium chloride, sugar and diamond. The main characteristics of
crystalline substances are:

(a). Orderly arrangement: The constituent units of crystalline solids are arranged in an orderly fashion
which repeats itself over very long distances as compared to interatomic distances. The arrange-
ment of bricks in a wall can be considered as an example. The arrangement is so well defined that
the entire pattern can be repeated provided the arrangement of a few atoms is known.

(b). Crystals are always bounded by plane faces.

1
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 2

(c). The faces of crystals always meet at some fixed angles: For any particular solid the angle between
corresponding pair of faces is always the same in all crystals. Figure 1.1 below illustrates this
point.

Fig. 1.1: Crystal face angles.

(d). Different crystals of the same substance may sometimes appear to be different from outside, (either
due to different rate of growth by different faces or due to some damage to the corners or edges) but
the interfacial angle is always the same. For example, sodium chloride grows from water solution
as cubes but from 15% aqueous urea as an octahedron. In Figure 1.2 below Sodium ions are blue,
chloride ions are green.

Fig. 1.2: Sodium Chloride crystal habits.

Two crystals of a single substance with the same lattice but different shapes are said to be of
different habit. On habit modification the relative areas of different faces change but the angles
between such faces remain constant.

(e). Crystalline solids exhibit anisotropy in many of their properties. That includes all those properties
which depend upon direction or angular orientation of crystals. These show different behavior in
non-parallel directions. One such consequence of anisotropy is the phenomenon of cleavage. In
crystals the splitting is easier in some directions than others. For example, in a crystal of sodium
chloride cleavage can only be achieved along planes parallel to cube faces. Any attempt to cleave
such a crystal along any arbitrary plane will shatter it. Figure 1.3 below illustrate this phenomenon
of cleavage.
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 3

Fig. 1.3: Crystal cleavage.

(f). The transition from the solid to liquid (i.e. melting point) for crystalline solids is sharp and distinct.
An amorphous substance, on the other hand, has no sharp melting point. The transition from solid
to liquid in an amorphous solid does not take place at a defined point but extends over a long range.
The absence of sharp melting point suggests that most of amorphous solids may be best thought
of as liquids.

(g). Crystalline solids exhibit definite heats of fusion.

1.2 Band Structure of Solids

Solids can also be categorized on the basis of their band structures. More specifically, the size of the
bandgap will determine whether a material is a conductor, an insulator or a semiconductor. Figure 1.4
below shows the band structure of insulators (a), semiconductors (b) and conductors (c) respectively.

Fig. 1.4: Band structure of insulators (a), semiconductors (b) and conductors (c).

1.2.1 Insulators

Material with bandgap around 5eV or more will typically be classified as an insulator. It takes a lot of
energy (> 5eV hence not cheap) to excite an electron from the valence band, across the bandgap, all the
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 4

way to the conduction band where it can move freely and conduct electricity. This requires photons with
energies or frequencies in the regime of x-rays and gamma rays to excite across such a large bandgap.
Examples of insulators include glass, wood, rubber, oil, ceramic, quartz and bone.

1.2.2 Semiconductors

In the case of a semiconductor, the band gap is relatively small thus an electron from the valence band
can be excited to the conduction band using photons with energies or frequencies in the range from
infra-red to ultraviolet. This is one of the reasons why the sun (in the visible range 400nm to 700nm) is
able to excite the electrons in solar panels to produce electricity. The bandgap for a semiconductor can
be made even smaller by introducing impurities into the semiconductor’s crystalline structure and this is
the basis for the process called doping. Indium Antimonide (InSb) is one of the semiconductors with the
smallest bandgap of about 0.18eV to 0.20eV. Examples of semiconductors include Silicon, Germanium,
Selenium, Tellurium and Gallium Arsenide.

1.2.3 Conductors

In conductors, the conduction and valance bands are so close to one another that they actually overlap.
That means in this case, the electrons are readily available (for conducting electricity given a small
pushing electric field) in the conduction band. Examples of conductors include Silver, Copper, Gold,
Aluminium, Zinc, Nickel, Brass and Bronze.

1.3 Semiconductor Types

1.3.1 Intrinsic Semiconductors

In a pure insulator or semiconductor, when we excite electrons from the valence band to the conduction
band, the density of electrons in the conduction band (typically denoted n for “negative” charges) is
equal to the density of holes in the valence band (denoted p for “positive” charges). Without impurities,
a semiconductor is known as intrinsic. Where impurities are added the semiconductor is sometimes
called extrinsic. Imagine that we have an intrinsic semiconductor and the valence band is completely
full, the conduction band is completely empty and we are at 0K temperature. This means the Fermi level
is exactly in the middle of the bandgap as shown in Figure 1.5 below.
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 5

Fig. 1.5: Semiconductor band structure and energy state occupation probability.

From Fermi-Dirac statistics we know that the probability fe (ε) of an electron to occupy energy state ε
(or any state between ε and ε + dε) is given by,

1
fe (ε) =
exp(β (ε − µ)) + 1
with β = (kB T )−1 . For β (ε − µ)  1 we have,

fe (ε) ≈ exp(−β (ε − µ))

Near conduction band (CB) edge we can make a quadratic approximation in momentum h̄~k and write,

h̄2 ~
ε~k = Ec +~k · ·k
2me
which is quadratic close to the bottom of the conduction band. The electron density of states De (ε)
(which is the number of eigenstates at energy ε) is given by,

1 2me 3/2 √
De (ε) = ( ) ε − Ec
2π 2 h̄2

which tells us how many eigenstates there are at each energy level (i.e. degeneracy). The carrier concen-
tration n can be obtained as follows,

´∞
n = Ec De (ε) f e (ε)dε

1 2me 3/2
´∞√
= 2π 2 ( h̄ 2 ) exp(β µ) Ec ε − Ec exp(−β ε)dε

= 2( 2πmh̄e2 β )3/2 exp(−β (Ec − µ))

LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 6

Recall that for finite nonzero temperature the transition across the Fermi level become relaxed and this
makes it possible for electron excitation by means of thermal energy kB T if the bandgap is small enough.
Figure 1.6 below shows the variation of carrier concentration n with temperature T for two different
bandgaps Eg (i.e. Eg = 0.66eV for Ge and Eg = 1.11eV for Si).

Fig. 1.6: Electron concentration as a function temperature for Ge and Si.

1
Let’s do the same analysis for the valence band. Since fe (ε) = exp(β (ε−µ))+1 for electrons, it is obvious
that for holes we have,

exp(β (ε − µ)) 1
fh (ε) = 1 − fe (ε) = =
exp(β (ε − µ)) + 1 exp(β (µ − ε)) + 1

For β (µ − ε)  1 we have,

fh (ε) ≈ exp(−β (µ − ε))

Near valence band (VB) edge we can write,

h̄2 ~
ε~k = Ev −~k · ·k
2mh
which is quadratic close to the bottom of the valence band. The holes density of states Dh (ε) is given by,

1 2mh 3/2 p
Dh (ε) = ( ) Eh − ε
2π 2 h̄2

The carrier concentration p can be obtained as follows,

´ Ev
p = −∞ Dh (ε) f h (ε)dε

= 2( 2πmh̄h2 β )3/2 exp(−β (µ − Ev ))

LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 7

Combining the two carrier concentrations n and p we get,

1
np = 4( 2
)3 (me mh )3/2 exp(−β Eg )
2π h̄ β
This is independent of doping and it is called the Law of Mass Action. The np values at 300K for Si, Ge
and GaAs are shown in the table below,

Si Ge GaAs
2.1 × 1019 cm−6 2.89 × 1026 cm−6 6.55 × 1012 cm−6

Intrinsic carrier concentration is given by,

1
ni = pi = 2( )3/2 (me mh )3/4 exp(−β Eg /2)
2π h̄2 β

1.3.2 Extrinsic Semiconductors

Consider silicon, a semiconductor with a bandgap of 1.1eV . Replacing one atom with phosphorus:

• Compared with Silicon, Phosphorus has one extra proton and one extra electron.

• As the valence band is filled, this electron must go into the conduction band.

• This is known as a donor (or electron donor) or n−dopant, as n is the symbol for the density of
electrons in the conduction band.

Replacing one atom with Aluminium:

• This provides one fewer electron than Silicon, so there will be one electron missing from the
valence band, thus leaving a hole.

• This is known as an electron acceptor, or a p−dopant.

Figure 1.7 below shows the crystal structure after introducing an N-dopant (Phosphorus) and also after
introducing a P-dopant (Boron).

Fig. 1.7: Silicon doping with Phosphorus (n-doping) and Boron (p-doping).
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 8

In practice, electrons are bound to n−dopants, but the states are weakly bound, just below the conduc-
tion. At low temperatures, we have carrier freeze-out and the material will not conduct electricity. But
temperature can excite electrons to the conduction band. Similarly, p−dopants provide states for elec-
trons just above the valence band and can be thermally populated with electrons, leaving holes in the
valence band. These two scenarios are summarized in Figure 1.8 below.

Fig. 1.8: Band structure modification due to doping.

In the absence of impurities, the Fermi energy is in the middle of the bandgap. Adding dopants shifts the
Fermi energy so that it is between the donor or acceptor states and the nearest band as shown in Figure
1.9 below.

Fig. 1.9: Shift in Fermi energy level due doping.

Shown in Figure 1.10 are the bandgaps for some selected semiconductors.

Fig. 1.10: Bandgap energies for some common semiconductors.

Shown in Figure 1.11 are the ionization energies for selected donors and acceptors in silicon.
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 9

Fig. 1.11: Ionization energies for some common semiconductors.

1.4 Hall Effect in Semiconductors

Imagine that we apply a magnetic field perpendicular to the direction of flow of charge carriers, in a
semiconductor material as shown in Figure 1.12 below.

Fig. 1.12: Hall Voltage measurement.

The charge carriers will experience an electric force perpendicular to the directions of both the applied
magnetic field and the carrier flow. This effect is called the Hall effect and is used widely in magnetic
field sensing. Hall effect can also be used to identify whether the underlying semiconductor is n−type
or p−type. The measured Hall voltage VH will be either positive or negative depending on whether the
semiconductor is p−type or n−type based on the following relation,

IBz
VH =
qnd

where I, B, q, n and d denote current flowing through the semiconductor, the magnetic field, charge of
one carrier particle, number of mobile charge carriers and the thickness of the semiconductor material
respectively.
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 10

1.5 PN Junction Basics

1.5.1 Introduction

Simply put, a PN junction is a piece of an extrinsic semiconductor with one end being P-type material
and the other end being an N-type material as shown in Figure 1.13 below. The PN junction can be
formed by doping one end of a N-type semiconductor (i.e. Silicon or Germanium) with a P-type dopant
(i.e. Boron). A semiconductor with P-type material at one end and N-type material at the other has some
unique properties. The P-type material has positive majority charge carriers, called holes, which are free
to move about the semiconductor crystal structure. On the other hand, the N-type material has mobile
negative majority carriers, called electrons, which are also free to move about the crystal structure.

Fig. 1.13: PN Junction schematic.

Near the junction, the N-type material electrons diffuse across the junction, combining with holes in P-
type material. The region of the P-type material near the junction takes on a net negative charge because
of the electrons attracted. Since electrons departed the N-type region, it takes on a localized positive
charge. The thin layer of the crystal lattice between these charges has been depleted of majority carriers,
thus, is known as the depletion region. It becomes non-conductive intrinsic semiconductor material. In
effect, we have nearly an insulator separating the conductive P and N doped regions.

1.5.2 Forward-Biasing

Forward-biasing of the PN junction can be achieved by applying positive voltage to the P-type end of
the PN junction as shown in Figure 1.14 below.
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 11

Fig. 1.14: Forward-biasing the PN junction.

Electrons in the N-type end are pushed by the battery towards the junction where they diffuse through.
On the other hand the holes in the P-type end are pushed by the battery towards the junction where
they also diffuse through. Given a battery voltage higher than threshold voltage of the PN junction
(i.e 0.2V for Ge and 0.6V for Si), the N-type electrons and P-holes will recombine at the junction thus
annihilating each other as currents of N-type and P-type majority carriers flow toward the junction. The
recombination at the junction allows battery current to flow through the PN junction and the junction is
said to be forward-biased.

1.5.3 Reverse-Biasing

Reverse-biasing of the PN junction can be achieved by applying positive voltage to the N-type side of the
PN junction as shown in Figure 1.15 below. In this setup, the positive battery terminal pulls electrons,
in the N-type end, away from the junction. This leaves behind a nonconducting depletion region of net
positive charge on immovable lattice points close to the PN junction.

Fig. 1.15: Reverse-biasing the PN junction.

In a similar fashion the negative terminal pulls holes, in the P-type end, away from the junction. This
leaves behind a nonconducting depletion region of net negative charge on immovable lattice points close
to the PN junction. As the battery voltage is increased, the thickness of the nonconducting depletion
region at the junction also increases thus creating a more stronger battery-like source of electric field
LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 12

across the junction which opposes or acts in reverse of the actual battery, hence the name reverse-biasing.
Since there is no recombination of majority carriers at the junction, there will be no conduction across
the PN junction.

1.6 Semiconductor Devices

Most semiconductor devices make use of a PN junction to control the flow of signal or excitation fre-
quency depending on the application of device. While there are less common semiconductor devices
like thyrister, Hall effect sensor and photocoupler, the most common of these devices are the diode and
the transistor.

1.6.1 Common Diodes

A diode act as a one way valve allowing current to flow easily in one direction but not the other direction.
Below are some examples of common diodes. Below is the list of common diodes,

(a). Signal Diode

(b). Zener Diode

(c). Light Emitting Diode

(d). Schotty Diode

(e). Tunnel Diode

(f). Varactor Diode

(g). Laser Diode

(h). Peltier Diode

(i). Crystal Diode

(j). Avalanche Diode

(k). Vacuum Diode

(l). PIN Diode

(m). Gunn Diode

Find out the function of each one of these diodes.

LECTURE 1. INTRODUCTION TO SEMICONDUCTORS 13

1.6.2 Common Transistors

Below is the list of some commonly used transistors,

(a). Bipolar Junction Transistor

(b). Darlington Transistor

(c). Insulated-gate Bipolar Transistor (IGBT)

(d). Field Effect Transistors

Find out the function of each one of these transistors.

Lecture 2

Diodes and Applications

2.1 Introduction

Diodes are the basic building blocks for most semiconductor devices. A diode is basically a PN junction
that we discussed in the previous lecture. That is, a diode consists of a junction of two semiconductor
materials, one doped with an electron deficient P-type material while the other is doped with an electron
abundant N-type material. This makes a diode to be part of the bipolar device family which functions as
a one-way signal valve in electronic circuits.

Fig. 2.1: Various diode symbols.

Figure 2.1 above shows various symbols used to represent or denote different types of diodes. In all
symbols, the arrow always pointing away from anode (P-type) toward cathode (N-type). Forward-biasing

14
LECTURE 2. DIODES AND APPLICATIONS 15

would mean connecting the positive terminal of the battery to the anode or P-type side of the diode while
the other battery terminal is connected to the cathode or N-type side of the diode. Reverse-biasing is
the exact opposite or reversal of the forward-biasing connection. In the next section we study the basic
characteristics and the Physics of diode operation.

2.2 The Physics of Diodes

2.2.1 Ideal Diode Equation

An ideal diode equation (also called Shockley ideal diode equation or the diode law) is an equation
relating applied voltage v and diode current i for an ideal diode can be written as follows,

 
v
i(v) = IS exp( )−1 (2.1)
ηVT

where IS is the reverse saturation current, VT = T /11, 586 is the volt equivalent of temperature and η is
the emission coefficient, which is 1 for germanium devices and 2 for silicon devices. In reverse bias, the
applied voltage v is negative and the resulting diode current i(v) will also be negative. The ideal diode
equation (2.1) above is only valid if the applied voltage v is greater than the Zener breakdown voltage
VZ of the diode (i.e. v > VZ ). A real diode approaches the ideal diode equation, hence the ideal diode
equation is a good model for a real diode.

2.2.2 Current-Voltage Characteristics

The characteristics of a diode can be summarized with a curve showing the current and voltage relation-
ship as shown in Figure 2.2 below.

Fig. 2.2: Ideal diode I-V Curve.

LECTURE 2. DIODES AND APPLICATIONS 16

From the I −V characteristic curve we can see that the current is exactly zero when the applied voltage
v is zero. For negative applied voltages between the Zener voltage and zero (i.e.VZ and 0V ) the diode
current seems to be relatively flat (or unchanging) and this is because the diode is in reverse bias and
hence not conducting. However, if the applied voltage goes below the Zener voltage, the diode gets in
the breakdown regime as will be explained in the next section.

2.2.3 Diode Breakdown Regimes

2.2.3.1 I-V Characteristics In Breakdown Regimes

If the applied voltage goes just below the Zener voltage, the diode goes in mode called the Zener break-
down mode and the ideal diode equation above does not hold anymore. In this Zener regime, the current-
voltage gradient is so steep that the diode can be used as voltage regulator. That is, the current changes
dramatically while the voltage is almost unchanging and it is this feature which allows the diode (used
as a voltage regulator) to handle a wide range of current loading while keeping the voltage constant. We
will get back to this feature when talking about Zener diode in later sections.

Fig. 2.3: Zener vs Avalanche Breakdown.

The I-V characteristic curve in Figure 2.3 shows the two breakdown regimes encountered by a diode in
reverse bias. If the applied voltage pushed further below the Zener breakdown voltage, the diode will
enter into another break down regime called the avalanche breakdown regime. The characteristics of the
two breakdown regimes are listed in the subsections below.

2.2.3.2 Zener Breakdown

1. This occurs at junctions which being heavily doped have narrow depletion layers .

2. This breakdown voltage sets a very strong electric field across this narrow layer.
LECTURE 2. DIODES AND APPLICATIONS 17

3. Here electric field is very strong to rupture the covalent bonds thereby generating electron-hole pairs.
So even a small increase in reverse voltage is capable of producing large number of current carriers (i.e.
why the junction has a very low resistance). This leads to Zener breakdown.

2.2.3.3 Avalanche Breakdown

1. This occurs at junctions which being lightly doped have wide depletion layers.

2. Here electric field is not strong enough to produce Zener breakdown.

3. Here minority carriers collide with semi conductor atoms in the depletion region, which breaks the
covalent bonds and electron-hole pairs are generated. Newly generated charge carriers are accelerated
by the electric field which results in more collision and generates avalanche of charge Carriers. This
results in avalanche breakdown.

2.3 Basic Diode Circuits

2.3.1 Diode Equivalent Circuit

The basic diode (i.e. signal diode) is used as one way current valve to allow current flow in one direction
and block it in the opposite direction. That is, the basic diode is used as a unidirectional switch as shown
by the equivalent circuits in Figure 2.4 below.

Fig. 2.4: Equivalent circuit for basic diode.

The 0.7V battery in the equivalent circuit represents the electric field (and hence electric potential/voltage)
created by opposite charges across the PN junction in the depletion region.

2.3.2 The Load Line Analysis

This is an analysis method for nonlinear electronic circuits whereby a straight line (called a load line) is
drawn on the characteristic curve of the nonlinear device to obtain its operating point. It can be done for
LECTURE 2. DIODES AND APPLICATIONS 18

direct currents as well as for alternating currents. The Figure 2.5 below shows the series connection of a
resistor R and a diode as well as the corresponding characteristic curve.

Fig. 2.5: Diode load line analysis.

The characteristic curve shows the current vs voltage relationship of the diode. The load line is a straight
line drawn with a gradient 1/R, current intercept VDD /R and voltage intercept VDD . That is, the load line
equation is given by,

1 VDD
ID = − VD + (2.2)
R R

The current I goes through all circuit components, hence the current through the resistor is the same as
the current through diode. This allows us to equate the current for resistor (described by the load line)
above to the diode current stated in equation (2.1) and rearrange terms as shown below,

VD 1 VDD
IS exp( ) + VD = IS + (2.3)
ηVT R R

with the general solution  

VDD
VD = ηVT ln 1 + k (2.4)
IS R
for some dimensional parameter 0 < k < 1. The operating point is the point where characteristic curve
intersects with the load line. This is also where equation (2.3) holds and the coordinates at that point are
given by,

VDD
(VD , ID ) = ((1 − k)VDD , k ) (2.5)
R

Notice that the power dissipated on the diode is given by,

2
VDD
PD = VD ID = k(1 − k) (2.6)
R
LECTURE 2. DIODES AND APPLICATIONS 19

and it is maximum when k = 1/2. Designing for maximum power dissipation into the diode could
be important as a way to avoid back-reflected power which can harm the power supply in a long run.
Selecting k = 1/2 for maximum power dissipation simply translates to choosing the resistor value R
such that IR = VD = VDD /2. Arbitrarily choosing the value of k is equivalent to choosing an arbitrary
operating point on the characteristic curve of the diode.

2.3.3 Simple Diode Circuits

Figure 2.6 below shows some simple diode circuits with some labeled voltages at different nodes.

Fig. 2.6: Simple diode circuits.

Determine the values of the voltages corresponding to the labeled nodes given that the diodes are silicon-
based with 0.7V threshold.

2.3.4 Rectifier Circuit

A rectifier circuit is essentially a converter circuit used to convert alternating current to direct current as
shown in the Figure 2.7 below. The ring of four diodes separate the polarities of the alternating current
supply and direct each polarity on a unique wire. For example, at the junction between D1 and D4 , the
negative polarity is only allowed to take the path down through D4 .

Fig. 2.7: Full wave rectifier.

LECTURE 2. DIODES AND APPLICATIONS 20

Also at the junction between D2 and D3 , the negative polarity is allowed to take the path up through D2 .
Therefore the terminal between D2 and D4 carries the negative polarity contributed through both D4 and
D2 to the load. On the other hand the positive polarities are allowed to take the path down through D1
and the path up through D3 to the junction where the wire between D1 and D3 takes this positive polarity
further to the load.

2.3.5 RF Mixer Circuit

An RF ring mixer shown in the Figure 2.8 below uses a combination of inductors or transformers together
with a ring connection of diodes to multiply the local oscillator (or carrier) signal (i.e. LO) with a
radiofrequency (or baseband) signal (i.e. RF) and produces an intermediate (or mixed or modulated)
output signal (i.e. IF).

D4 D1
T1 T2

LO RF

D3 D2

IF

Fig. 2.8: RF Mixer circuit.

The diodes in this setup are used to switch on and off the upper and lower part of the center-tapped
transformers. This kind of circuit will be dealt in more details in later electronics engineering courses.

2.3.6 Voltage Multiplier Circuit

A voltage multiplier is an electrical circuit that converts AC electrical power from a lower voltage to a
higher DC voltage, typically using a network of capacitors and diodes. Voltage multipliers can be used
to generate a few volts for electronic appliances, to millions of volts for purposes such as high-energy
physics experiments and lightning safety testing.

Fig. 2.9: Villard cascade voltage multiplier circuit.

LECTURE 2. DIODES AND APPLICATIONS 21

The most common type of voltage multiplier is the half-wave series multiplier, also called the Villard
cascade as shown in the Figure 2.9 above. The C1 capacitor is charged through diode D1 to Us , then
potential of C1 adds with that of the AC source, thus charging C2 to 2Us through D2 . This same logic
carries on through the cascades to the DC output

2.4 Zener Diode Circuits

2.4.1 Zener Diode Characteristics

The Zener diode is used in reverse bias or reverse breakdown mode (i.e. the diodes anode connects to
the negative supply).

Fig. 2.10: Zener diode I-V curve.

From the I-V characteristics curve in Figure 2.10 above, we can see that the Zener diode has a region in
its reverse bias characteristics of almost a constant negative voltage regardless of the value of the current
flowing through the diode and remains nearly constant even with large changes in current as long as the
Zener diodes current remains between the breakdown current IZ(min) and the maximum current rating
IZ(max) .

2.4.2 Equivalent Circuit Model

An equivalent circuit for the Zener diode can be represented as a battery VZ in series with a Zener
resistance rZ as shown in the Figure 2.11 below.
LECTURE 2. DIODES AND APPLICATIONS 22

Fig. 2.11: Equivalent circuit for Zener diode.

This equivalent circuit representation makes it easier and a lot more convenient when analyzing complex
circuits involving Zener diodes along with other electronic components in one circuit. The next section
discusses the example of Zener diode application as a voltage regulator.

2.4.3 Voltage Regulation Circuit

Voltage regulator is an electronic circuit designed to convert some unstable voltage supply into a stable
voltage supply. A Zener diode connected in reverse bias can be used to stabilize an unstable supply
voltage as shown in Figure 2.12 below.

Fig. 2.12: Zener diode in a voltage regulator circuit.

A voltage regulator is used in many electronics circuit where one would normally use a potential divider
circuit. The reason for preferring a voltage regulator over a potential divider is that a potential divider
is ineffective and unstable in applications where the load is varying. Consider a scenario in which an
unstable power supply outputs a voltage in the range from 80V to 120V as depicted in the Figure 2.13
below.

Fig. 2.13: Voltage regulator circuit example.

LECTURE 2. DIODES AND APPLICATIONS 23

If a 50V Zener diode is able to supply a 10kΩ load with a stable voltage of 50V for any supply voltage
in the given range of 80V to 120V , then find the minimum and maximum Zener diode current IZ . To
answer this question we need to first realize that maximum current flows through the Zener diode when
the supply voltage is maximum (i.e. 120V ). In this case we will have the current I through the 5kΩ
resistor as,

120V − 50V
I= = 14mA (2.7)
5kΩ

The load current IL will be given by,

50V
IL = = 5mA (2.8)
10kΩ

This leaves the maximum current through the Zener diode as,

IZmax = I − IL = 14mA − 5mA = 9mA (2.9)

The minimum current through the Zener diode can be obtained in a similar fashion but using the mini-
mum supply voltage of 80V . This would give the current I through the 5kΩ resistor as,

80V − 50V
I= = 6mA (2.10)
5kΩ

The load current IL will still be given by,

50V
IL = = 5mA (2.11)
10kΩ

This leaves the minimum current through the Zener diode as,

IZmin = I − IL = 6mA − 5mA = 1mA (2.12)

This means that the operation current range for this Zener diode should cover the range 1mA to 9mA
otherwise the Zener diode will fail to supply a stable 50V to a load. Notice that in the extreme supply
voltages (i.e. 80V and 120V ) the load voltage and current remain the same at 50V and 5mA respectively.
This is the essence of voltage regulation.

2.4.4 Voltage Clipper Circuit

There are cases whereby a device has to limit the voltage amplitude as way to protect itself against
damage or perhaps as a way to limit out-of-range signal fro display purposes. In such cases, two opposing
Zener diodes in series can be connected in parallel with the load as shown in the Figure 2.14 below.
LECTURE 2. DIODES AND APPLICATIONS 24

Fig. 2.14: Zener diode in a voltage clipper circuit.

For positive input voltage Vin the first Zener diode is in forward bias hence will just operated like a basic
diode allowing current to flow through it. However, the second Zener diode will be in reverse bias and
will start to regulate (i.e. flattens the voltage) the incoming voltage as soon as it reaches VZener2 . The
same is true about the first Zener diode at VZener1 for negative input supply voltages Vin .

2.4.5 Voltage Shifter Circuit

Suppose that the input voltage Vin is increased steadily in time from zero, in the circuit shown in the
Figure 2.15 below. While the input voltage is between zero and Vzener , the reverse-biased Zener diode is
not conducting any current through to the resistor side.

Fig. 2.15: Zener diode in a voltage shifter circuit.

However, once the supply voltage goes beyond the Zener voltage, the diode starts to conduct and result-
ing output voltage Vout becomes directly proportional to the supply voltage. The region or set of input
voltage values (i.e. 0V to VZener ) for which the output voltage Vout values remained unchanged is called
the deadband (or dead zone or neutral zone) of the Zener diode.
Lecture 3

Bipolar Junction Transistor

3.1 Introduction

A bipolar junction transistor (BJT) is a type of transistor that uses both electrons and electron holes as
charge carriers. Much like a relay (which allows a small current signal to control a much larger current
signal), a bipolar transistor allows a small current injected at one of its terminals (usually the base) to
control a much larger current flowing between two other terminals (usually collector to emitter current)
thus making the device capable of amplification as well as switching. The bipolar junction transistor
is composed of two junctions made by the P-type and N-type semiconductors as will be shown in the
next section. Bipolar transistors are called bipolar because the main flow of electrons through them takes
place in two types of semiconductor material (i.e. P-type and N-type), as the main current goes from
emitter to collector (or vice versa). That is, there are two types of charge carriers (i.e. electrons and
holes) which comprise this main current through the transistor.

3.1.1 Symbols and Structure

Figure 3.1 below shows the symbol and and junction structure for an NPN bipolar junction transistor,
with C, B and E being the terminals for collector, base and emitter respectively. The letters IC , IB and IE
are the currents for collector, base and emitter terminals respectively.

Fig. 3.1: Symbol and Junction structure for NPN bipolar junction transistor.

25
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 26

For a PNP bipolar junction transistor, the symbol arrow is reversed (i.e point inward from emitter to
base) and P is swapped with N everywhere in the junction structure.

3.1.2 The Band Structure

Just as a reminder of band structures, Figure 3.2 below shows the band structure of an NPN bipolar
junction transistor. The first diagram shows the band structure of an NPN transistor in equilibrium. This
looks exactly like two diodes sharing the same P-type semiconductor material. The Fermi energy level
in relation to the conduction and valance bands in various regions should serve as reminder about what
we said in the first lecture when explaining the effects of impurities (or doping) on the Fermi energy
level.

Fig. 3.2: Band structure of NPN BJT in equilibrium and also in active mode.

The second diagram show the band structure of the same transistor while biased in active mode with
electrons injected at the emitter and overshooting into the collector through the base. One way to inject
electrons through the emitter is as shown in Figure 3.3 below which illustrates the flow of carriers in the
NPN bipolar junction transistor. It can be seen that the controlling (or base) current and the controlled
(or collector) current always mesh together through the emitter wire, and their electrons always flow
against the direction of the transistor’s arrow.

Fig. 3.3: Carrier flow in the NPN BJT.

LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 27

Absence of current through the base of the transistor will shut the transistor off like an open switch and
prevent current through the collector. The presence of base current turns the transistor on like a closed
switch and allows a proportional amount of current through the collector. Collector current is primarily
limited by the base current, regardless of the amount of voltage available to push it. The next section
will explore in more detail the use of bipolar transistors as switching elements.

3.2 BJT Operation Modes

3.2.1 I-V Characteristics

Figure 3.4 below shows the I-V curve and load line for biasing a transistor. There are three regions shown
in the I-V characteristic curve. The two shaded regions (i.e. saturation or point A and cutoff regions or
point B) are used for switching purposes. That is, in those two regions the transistor either fully off or
fully on, thus acts like a voltage controlled switch. Acting as switch means a transistor can be used to
build logic gates like NAND gate as will be demonstrated in sections that follow. The unshaded middle
region labeled as active region is commonly used for amplification of signal input at the base terminal. In
this active mode, a relatively small signal injected at the base terminal can be amplified by the transistor
and come out as a larger signal at the collector or emitter terminal.

Fig. 3.4: Transistor I-V curves and biasing.

3.2.2 Cutoff Mode Operation

Figure 3.5below show the circuit for biasing the transistor to operate in cutoff mode. In this mode, both
collector-base junction and emitter-base junction are reverse biased. This in turn not allows the current
to flow from collector to emitter when the base-emitter voltage is low. In this mode device is completely
switched off as the result the current flowing through the device is zero.
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 28

Fig. 3.5: NPN transistor biased for cutoff mode.

This is equivalent to applying input voltage of zero (i.e. Vin = 0V ) and removing the wire shorting Vin to
emitter connector. Notice that the output voltage Vout is the same as the supply voltage Vcc as a result of
having IC = 0A. This means that in applications where a transistor is used as a switch, the output voltage
would be high in this mode. This make a transistor to behave like an inverting device since it gives out
high voltage at the collector when a low input voltage is applied at the base.

3.2.3 Saturation Mode Operation

Figure 3.6 below shows the dotted line which separates the saturated and active region of a transistor.

Fig. 3.6: Separation between the saturation and active region of a bipolar junction transistor.

In this mode of operation, both the emitter base and collector base junctions are forward biased. Current
flows freely from collector to emitter when the base-emitter voltage is high. In this mode device is fully
switched ON. Figure 3.7 below show the circuit for biasing the transistor to operate in saturation mode.
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 29

Fig. 3.7: NPN transistor biased for saturation mode.

In this mode, the collector current has reached saturation value (i.e. IC = ISat ).

Similarly, in the saturation region, a transistor is biased in such a way that maximum base current is
applied that results maximum collector current and minimum collector-emitter voltage. This causes the
depletion layer to become small and to allow maximum current flow through the transistor. Therefore,
the transistor is fully in ON condition.

Hence, from the above discussion, we can say that transistors can be made to work as ON/OFF solid
state switch by operating transistor in cutoff and saturation regions. This type of switching application
is used for controlling motors, lamp loads, solenoids, etc.

3.2.4 Active Mode Operation

Biasing in this mode simply translates to moving the quiescent operating point (i.e. Q-point) along the
load line. Placing the Q-point in the center has the advantage of allowing full swings of AC signals
without clipping on one side before the other. Figure 3.8 below shows the example of signal clipping
due to no biasing.

Fig. 3.8: Signal clipping due to no biasing.

LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 30

It can be seen that the output voltage can Vout waveform is clipped such that all the negative components
(that were present in the in input voltage Vin waveform) are now missing. One way to move the operation
point along the load line is by using a potential divider biasing as shown in Figure 3.9below.

Fig. 3.9: NPN transistor biased for active mode.

The resistors R1 and R2 make a potential divider that feed a fraction of Vcc into the transistor base
terminal. This type of network has the effect of offsetting the input signal. Instead of swinging around
0V , the signal then swings along a positive DC offset voltage. The resistors R1 and R2 determine this
offset voltage. Due to the biasing voltage at the base junction of the transistor, the transistor will always
conduct slightly and consequently there will be a current Ic flowing even when there is no signal at the
base. This current, known as zero-signal collector current, represents the proper offset required to push
the signal into the positive half of the transistors operation. In order to calculate the values of R1 and R2
one must first find the value of Ve , Re , Ic , and the Q-point.

For maximum output performance, amplifiers are usually midpoint biased. This simply means the tran-
sistor Q-point is chosen at the coordinates (Vce , Ic ) = (Vcc /2, Ic(max) /2) where Ic(max) is the maximum
collector current rating of the transistor. When the transistor operates on this Q-point, the output signal
will swing around Vcc /2, thus avoiding clipping. The DC load line shown in red helps to find this mid-
point operation. With this information and some extra information including Vbe ≈ 0.7V (for Si) and
Ie ≈ Ic = β Ib , we can straight-forwardly determine (in terms of other variables) the values of the two
resistors R1 and R2 with the help of Kirchhoff’s law. This will be left as an exercise for students.
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 31

3.3 Common Configurations

3.3.1 Common Base Configuration

As its name suggests, in the Common Base or grounded base configuration, the base connection is
common to both the input signal and the output signal. The input signal is applied between the transistors
base and the emitter terminals, while the corresponding output signal is taken from between the base and
the collector terminals as shown in Figure 3.10 below. The base terminal is grounded or can be connected
to some fixed reference voltage point.

Fig. 3.10: Common base configuration.

The input current flowing into the emitter is quite large as its the sum of both the base current and
collector current respectively therefore, the collector current output is less than the emitter current input
resulting in a current gain for this type of circuit of unity or less, in other words the common base
configuration attenuates the input current signal. Its input characteristics represent that of a forward
biased diode while the output characteristics represent that of an illuminated photo-diode.

Also this type of bipolar transistor configuration has a high ratio of output to input resistance. Then the
voltage gain ( Av ) for a common base configuration is therefore given as,

Vout I3 R3 R3
Gain = = =α (3.1)
Vin I4 R4 R4

with α ≈ 1 as the ratio between collector and emitter currents. This type of transistor arrangement
is not very common due to its unusually high voltage gain characteristics. The common base circuit is
generally only used in single stage amplifier circuits such as microphone pre-amplifier or radio frequency
(RF) amplifiers due to its very good high frequency response. This type of amplifier configuration is a
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 32

non-inverting voltage amplifier circuit, in that the signal voltages Vin and Vout are in-phase. Summary
characteristics of common base configuration:

• High voltage gain.

• Low current gain.

• Low power gain.

• Input and output phase relation is 0o .

• It has low input impedance.

• It has high output impedance.

Some common applications include:

• It is used in moving coil microphones pre-amplifier.

• It is used in UHF and VHF RF amplifiers.

3.3.2 Common Emitter Configuration

In the Common Emitter or grounded emitter configuration, the input signal is applied between the base
and the emitter, while the output is taken from between the collector and the emitter as shown in Figure
3.9. This type of configuration is the most commonly used circuit for transistor based amplifiers and
which represents the normal method of bipolar transistor connection. In this type of configuration, the
current flowing out of the transistor must be equal to the currents flowing into the transistor as the emitter
current is given as
Ie = Ic + Ib . (3.2)

The common emitter amplifier configuration produces the highest current and power gain of all the three
bipolar transistor configurations. This is mainly because the input impedance is low as it is connected
to a forward biased PN-junction, while the output impedance is high as it is taken from a reverse biased
PN-junction. As the load resistance is connected in series with the collector, the current gain of the
common emitter transistor configuration is quite large as it is given by the ratio,

Ic
β= . (3.3)
Ib

Then, small changes in current flowing in the base will thus control the current in the emitter-collector
circuit. For most general purposes transistors β ranges between the values 20 and 200. This configuration
has a much lower voltage gain than the common base configuration. However, it has a much higher
current and power gain than the common base configuration. The common emitter configuration is an
inverting amplifier circuit. This means that the resulting output signal has a 180o phase-shift with regards
to the input voltage signal. The advantages of a common emitter amplifier include the following:
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 33

• The common emitter amplifier has a low input impedance and it is an inverting amplifier.

• The output impedance of this amplifier is high.

• This amplifier has the highest power gain when combined with medium voltage and current gain.

• The current gain of the common emitter amplifier is high.

The disadvantages of a common emitter amplifier include the following:

• In the high frequencies, the common emitter amplifier does not respond.

• The voltage gain of this amplifier is unstable.

• The output resistance is very high in these amplifiers.

• In these amplifiers, there is a high thermal instability High output resistance

The applications of a common emitter amplifier include the following:

• The common emitter amplifiers are used in the low-frequency voltage amplifiers.

• These amplifiers are used typically in the RF circuits.

• In general, the amplifiers are used in the Low noise amplifiers

• The common emitter circuit is popular because it’s well-suited for voltage amplification, especially
at low frequencies.

• Common-emitter amplifiers are also used in radio frequency transceiver circuits.

• Common emitter configuration commonly used in low-noise amplifiers.

3.3.3 Common Collector Configuration

In the Common Collector or grounded collector configuration, the collector is connected to ground
through the supply, thus the collector terminal is common to both the input and the output. The input
signal is connected directly to the base terminal, while the output signal is taken from across the emit-
ter load resistor as shown in Figure 3.11. This type of configuration is commonly known as a Voltage
Follower or Emitter Follower circuit.
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 34

Fig. 3.11: Common collector configuration.

The common collector, or emitter follower configuration is very useful for impedance matching appli-
cations because of its very high input impedance, in the region of hundreds of thousands of Ohms while
having a relatively low output impedance. This configuration has a current gain approximately equal to
the β value of the transistor itself. However, in the common collector configuration, the load resistance
is connected in series with the emitter terminal so its current is equal to that of the emitter current. As
the emitter current is the combination of the collector and the base current combined, the load resistance
in this type of transistor configuration also has both the collector current and the input current of the base
flowing through it. Then the current gain of the circuit is given as,

Ie
= β +1 (3.4)
Ib

Characteristics of common collector configuration include:

• Voltage gain of zero.

• High current gain.

• Medium power gain.

• Input and output are in-phase (i.e. 0o ).

• Input resistance is high.

• Output resistance is low.

Some common applications include,

• This amplifier is used as an impedance matching circuit.

• It is used as a switching circuit.

• The high current gain combined with near-unity voltage gain makes this circuit a great voltage
buffer.

• It is also used for circuit isolation.

LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 35

3.4 Common Circuit Applications

There mainly two applications of a bipolar junction transistor, which are amplification and switching.
They are the building blocks of most of the electronic circuits, especially where audio, current or voltage
amplification is required. Below we give one example of each application.

3.4.1 BJT Amplifier Circuit

In many cases, NPN transistors are preferred over PNP transistors for amplification purpose because
conduction carried out through mobility of electrons is better than conduction through mobility of holes.
In Figure 3.12 below two NPN bipolar junction transistors are used in cascode connection to stably
amplify the signal at the base terminal.

Fig. 3.12: BJT-based cascode amplifier circuit.

This is one of the most stable and robust amplifier configurations since its design takes into account the
internal parasitic effects (i.e. Miller capacitance among others) of a BJT. The capacitances CC1 and CC2
are called coupling capacitances since they capacitively couple in and out the RF signals while blocking
the DC signals. The capacitor CE is called the by-pass capacitor since it re-route RF signals away from
the resistor RE on their way to ground. More details on this kind of circuit will be covered in the 3rd
year Electronics course on Analog Circuit Design.

3.4.2 BJT NAND Gate Circuit

A NAND gate is a universal logic gate in the sense that all other logic gates can be built out of a NAND
gate. That means if we can construct a NAND gate, then we can construct all other gates. Figure 3.13
LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 36

below show the NAND gate circuit built out of a BJT biased in a switching mode.

Fig. 3.13: BJT-based NAND gate circuit.

As we can recall from earlier example in transistor modes that a BJT in switching mode is inverting
in the sense that, when the input is low, the output is high and vice versa. In that sense it behaves very
much like a logic gate called a NOT gate. In the Figure above we have two inputs A and B and one output
labeled as OUT or Q. When the input/output voltage is around 4.5V to 5.5V we say the input/output is
high or it 1 and if it the voltage is close to 0V we say the input/output is low or it is 0. In short 0V means
binary 0 and 5V means binary 1.

Any two distinct voltage values can be used instead of 0V and 5V but these two are very common in
digital circuits. Notice that when A and B are high, both transistors (i.e. T1 and T2 ) are fully switched on
and conducting thus the resistor takes up all of Vcc leaving close to 0V below it. This means the output
will be 0V which is a binary 0 as shown in the truth table in Figure 3.13 above. However, if any (or both)
of the inputs (i.e. A or B or both) has voltage 0V (or binary 0) the the switch will be open and current
can’t flow from the supply down to ground. In this case the output voltage will remain as Vcc = 5V or
binary output 1 as shown in the truth table. This truth table is identical to that of a NAND gate, thus the
circuit above is BJT-based NAND gate circuit.

3.5 BJT vs Other Transistors

3.5.1 Advantages

Below we outline the advantages of BJTs in relation to other transistor types:

• Bipolar junction transistor comes with a large amplification factor.

• This type of transistor provides a better voltage gain.

LECTURE 3. BIPOLAR JUNCTION TRANSISTOR 37

• This transistor comes with a capability of operating in four regions i.e active region, reverse mode,
saturation and cut-off region.

• BJT provides a better response at higher frequencies.

• BJTs also act as a switch.

3.5.2 Disadvantages

Below we list the disadvantages of BJTs in relation to other transistor types:

• BJT is very sensitive to heat and produces noise is some cases.

• The switching power of BJTs is very low as compared to unipolar transistors like FETs.
Lecture 4

Field Effect Transistors

4.1 Introduction

4.1.1 Some Background

In the previous lecture we discussed the circuit applications of bipolar junction transistors (BJTs), in
which both holes and electrons take part in conduction. The presence of two carrier types is the reason
why these transistors are said to be "bipolar". Such transistors have two main drawbacks which are (a)
low input impedance because of forward biased emitter junction and (b) considerable noise level. Both
of these drawbacks have been overcome, to a great extent in the field effect transistor (FET), which is an
electric field (or voltage) controlled device. FETs have all the advantages that vacuum tubes and ordinary
BJTs have thus they are replacing both the vacuum tubes and BJTs in many applications.

Fig. 4.1: N-channel and P-channel FET Symbols.

As shown in Figure 4.1 above, a field-effect transistor (FET) is a three terminal (namely drain, source
and gate) semiconductor device in which current conduction is by only one type of majority carriers
(electrons in case of an N-channel FET or holes in a P-channel FET). It is also sometimes called the
uni-polar transistor. Unlike a BJT, a FET requires virtually no input (bias signal) current and gives an
extremely high input resistance, which is the most important advantage over a BJT. Either BJT or FET
devices can be used to operate in amplifier circuits or other similar electronic circuits, with different bias
considerations.

38
LECTURE 4. FIELD EFFECT TRANSISTORS 39

4.1.2 FET Family Tree

There are two categories of FET namely; Junction Field-Effect Transistor (JFET) and Insulated-Gate
Field-Effect Transistor (IGFET) or Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET).

Field Effect
Transistors

Junction Insulated
Gate

Depletion Enhancement

P-channel N-channel P-channel N-channel

Depletion

P-channel N-channel

Fig. 4.2: JFET Family tree.

Figure 4.2 above shows a family tree of the FET. The next two sections cover these two categories of the
FET.

4.2 Junction Field Effect Transistor

4.2.1 JFET Basic Operation

In a junction field-effect transistor or JFET, the controlled current passes from source to drain. The
controlling voltage is applied at the gate. Unlike in BJT, the current does not have to pass through a
PN junction on its way between source and drain. Rather the current travels through the path (called a
channel) which is either a P-type (for a P channel JFET) or an N-type (for an N channel JFET) material.
Figure 4.3 shows the PN structure and pin layout for both N channel JFET and P channel JFET.

Fig. 4.3: N Channel JFET and P Channel JFET.

LECTURE 4. FIELD EFFECT TRANSISTORS 40

With no voltage applied between gate and source, the channel is a wide-open path for current to flow.
However, if a voltage is applied between gate and source in such a way that it reverse-biases the PN
junction, the flow between source and drain connections becomes limited or regulated, just as it was for
bipolar transistors with a set amount of base current. Maximum gate-source voltage “pinches off” all
current through source and drain, thus forcing the JFET into cutoff mode.

Fig. 4.4: N Channel JFET ad P Channel JFET biased.

As seen from Figure 4.4 above, this behavior is due to the depletion region of the PN junction expanding
under the influence of a reverse-bias voltage, eventually occupying the entire width of the channel if the
voltage is great enough. This action may be compared to reducing the flow of a liquid through a flexible
hose by squeezing it as shown in Figure 4.5 below.

Fig. 4.5: JFET Compared to a squeezed hose pipe.

With enough force, the hose will be constricted enough to completely block the flow. By changing
the gate terminal voltage, the width of the depletion layer increases thus extending into the channel
and reducing the opening of the channel which inturn limits the current through the channel. We can,
therefore conclude that by controlling gate voltage we can control the drain current. For added clarity,
Figure 4.6 below makes this channel pinch-off phenomena more obvious. With no external Gate voltage
(VG = 0), and a small voltage (VDS ) applied between the Drain and the Source, maximum saturation
current (IDSS ) will flow through the channel from the Drain to the Source restricted only by the small
depletion region around the junctions.
LECTURE 4. FIELD EFFECT TRANSISTORS 41

Fig. 4.6: Formation of channel pinch-off.

If a small negative voltage (i.e. −VGS ) is now applied to the Gate the size of the depletion region begins
to increase hence reducing the overall effective area of the channel and thus reducing the current flowing
through it, a sort of “squeezing” effect takes place. So by applying a reverse bias voltage increases the
width of the depletion region which in turn reduces the conduction of the channel. Since the PN-junction
is reverse biased, little current will flow into the gate connection. As the Gate voltage (i.e. −VGS ) is made
more negative, the width of the channel decreases until no more current flows between the Drain and the
Source and the FET is said to be “pinched-off” (similar to the cut-off region for a BJT). The voltage at
which the channel closes is called the pinch-off voltage,VP .

In the second diagram of Figure 4.6 above, the pinch-off voltage VP for this transistor is shown as the
voltage above which the channel is completely closed and no conduction between source and drain
happens. In this pinch-off region the Gate voltage, VGS controls the channel current and VDS has little or
no effect. The result is that the FET acts more like a voltage controlled resistor which has zero resistance
when VGS = 0 and maximum “ON” resistance (i.e. RDS ) when the Gate voltage is very negative. Under
normal operating conditions, the JFET gate is always negatively biased relative to the source. It is
essential that the Gate voltage is never positive since if it is all the channel current will flow to the Gate
and not to the Source, the result is damage to the JFET.This voltage-control property of the JFET allows
it to be used for many different electronic applications such as in amplification and switching. Then to
close the channel:

• No Gate Voltage (VGS ) and VDS is increased from zero.

• No VDS and Gate control is decreased negatively from zero.

• VDS and VGS varying.

The P-channel Junction Field Effect Transistor operates exactly the same as the N-channel above, with
the following exceptions:

(a). Channel current is positive due to holes.

(b). The polarity of the biasing voltage needs to be reversed.

LECTURE 4. FIELD EFFECT TRANSISTORS 42

4.2.2 JFET I-V Characteristics

Figure 4.7 below shows the output characteristics of an N-channel JFET with the gate short-circuited to
the source. The voltage VGS applied to the Gate controls the current flowing between the Drain and the
Source terminals. VGS refers to the voltage applied between the Gate and the Source while VDS refers to
the voltage applied between the Drain and the Source. Because a JFET is a voltage controlled device,
there is no current flowing into the gate hence the Source current IS flowing out of the device equals the
Drain current ID flowing into it. That is,

ID = IS (4.1)

Fig. 4.7: JFET I-V characteristics.

The characteristics curves for a P-channel junction field effect transistor are the same as those above,
except that the Drain current ID decreases with an increasing positive Gate-Source voltage, VGS . The
Drain current is zero when VGS = VP . For normal operation, VGS is biased to be somewhere between VP
and 0. Then we can calculate the Drain current, ID for any given bias point in the saturation or active
region as follows,

VGS 2
 
ID = IDSS 1 − (4.2)
VP

Note that the value of the Drain current will be between zero (pinch-off) and IDSS (maximum current).
By knowing the Drain current ID and the Drain-Source voltage VDS the resistance of the channel (RDS )
is given as,

4VDS 1
RDS = = (4.3)
4ID gm

with gm as the transconductance gain which represents the rate of change of the Drain current with
respect to the change in Gate-Source voltage. The characteristics curves example in Figure 4.7 above
shows the four different regions of operation for a JFET and these are described briefly below.
LECTURE 4. FIELD EFFECT TRANSISTORS 43

4.2.2.1 Ohmic Region

When VGS = 0 the depletion layer of the channel is very small and the JFET acts like a voltage controlled
resistor.

4.2.2.2 Cut-off Region

This is also known as the pinch-off region were the Gate voltage, VGS is sufficient to cause the JFET to
act as an open circuit as the channel resistance is at maximum.

4.2.2.3 Saturation or Active Region

The JFET becomes a good conductor and is controlled by the Gate-Source voltage, (VGS ) while the
Drain-Source voltage, (VDS ) has little or no effect.

4.2.2.4 Breakdown Region

The voltage between the Drain and the Source, (VDS ) is high enough to causes the JFET’s resistive
channel to break down and pass uncontrolled maximum current.

4.2.3 JFET As Amplifier

Just like the BJT, the JFET can be used to make an amplifier circuit with the JFET connected in common
source thus having characteristics much similar to the BJT common emitter circuit. The main advantage
JFET amplifiers have over BJT amplifiers is their high input impedance which is controlled by the Gate
biasing resistive network formed by R1 and R2 connected in potential divider configuration as shown in
Figure 4.8 below.

Fig. 4.8: JFET Amplifier biasing.

LECTURE 4. FIELD EFFECT TRANSISTORS 44

This common Source amplifier circuit is biased by the voltage divider network formed by resistors R1
and R2 . The voltage across the Source resistor RS is generally set to be about one quarter of VDD . That
is,

VDD
VS = ID RS = VG −VGS ≈ (4.4)
4

The required Gate voltage can then be calculated from this RS value. Since the Gate current is zero, (i.e
IG = 0) we can set the required DC quiescent voltage by the proper selection of resistors R1 and R2 . We
can also describe the Gate voltage in relation to the potential divider network as follows,

R2
VG = VDD (4.5)
R1 + R2

The control of the Drain current by a negative Gate potential makes the JFET useful as a switch and it is
essential that the Gate voltage is never positive for an N-channel JFET as the channel current will flow to
the Gate and not the Drain resulting in damage to the JFET. The principals of operation for a P-channel
JFET are the same as for the N-channel JFET, except that the polarity of the voltages need to be reversed.

4.2.4 JFET NOT Gate

Fig. 4.9: JFET NOT Gate.

When A is positive, it turns off the high gate, disconnecting Q from positive voltage (Vdd ); and turns
on the low gate, connecting Q to the negative voltage (Vss ): A positive makes Q negative. When A is
negative, it turns on the high gate and off the low gate, connecting Q to positive voltage and disconnecting
negative voltage; A negative makes Q positive.

4.2.5 JFET Properties

This is a voltage control device since the current through the channel gets controlled by gate voltage.
LECTURE 4. FIELD EFFECT TRANSISTORS 45

In other words, the electric field across the junction effects the operation of the transistor and that is why
it is named as junction field effect transistor.

As in normal operating condition, the junction between input gate region and channel remains to reverse
biased, the input impedance of the transistor is high.

Ideally, there will be no gate current in JFET.

Majority carriers only contribute the current through the channel in the device, i.e., free electrons in n
channel and holes in p channel and these are the reason why a transistor is called unipolar device.

4.3 Metal-Oxide Semiconductor Field-Effect Transistor

The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is one type of FET transistor. In
these transistors the gate terminal is electrically insulated from the current carrying channel so that it is
also called as Insulated Gate Field Effect Transistor (IGFET). Due to the insulation between gate and
source terminals the input resistance of MOSFET may be very high such as in megaohms (MΩ). Like
JFET the MOSFET also acts as a voltage controlled resistor when no current flows into the gate terminal.
The small voltage at the gate terminal controls the current flow through the channel between the source
and drain terminals. In present days, the MOSFET transistors are mostly used in the electronic circuit
applications instead of the JFET. Like JFET, the MOSFET transistors also have three terminals, such
as Drain (D), Source (S) and Gate (G) and also one more terminal called substrate or Body (B) is used
in the circuit connections. The MOSFETs are also available in both types, N-channel (NMOS) and P-
channel (PMOS). The MOSFETs are basically classified in to two forms they are Depletion type and
Enhancement type transistors.

Fig. 4.10: MOSFET Channel construction.

Figure 4.10 above shows the channel structure of a P-channel and N-channel MOSFET. The basic struc-
ture of the MOSFET is shown in the above figure. The construction of the MOSFET is very different as
compared to the construction of the JFET. In both enhancement and depletion modes of MOSFETs an
LECTURE 4. FIELD EFFECT TRANSISTORS 46

electric field is produced by gate voltage which changes the flow charge carriers, such as electrons for N-
channel and holes for P-channel. Here we observed that the gate terminal is injected into the thin metal
oxide insulated layer at the top and two N-type regions are used below the drain and source terminals.

Fig. 4.11: Basic structure of a MOSFET.

In the above MOSFET structure the channel between drain and source is an N-type which is formed
opposite to the P-type substrate. It is easy to bias the MOSFET gate terminal for the polarities of either
positive (+ve) or negative (-ve). If there is no bias at the gate terminal, then the MOSFET is generally
in non-conducting state so that these MOSFETs are used to make switches and logic gates. Both the
depletion and enhancement modes of MOSFETs are available in N-channel and P-channel types.

4.3.1 Depletion Mode MOSFET

The depletion type MOSFET transistor is equivalent to a “normally closed” switch. The depletion type
of transistors requires gate-source voltage (VGS ) to switch OFF the device. The symbols for depletion
mode of MOSFETs in both N-channel and P-channel types are shown above. In the above symbols we
can observe that the fourth terminal substrate is connected to the ground, but in discrete MOSFETs it is
connected to source terminal. The continuous thick line connected between the drain and source terminal
represents the depletion type. The arrow symbol indicates the type of channel, such as N-channel or P-
channel. In this type of MOSFETs a thin layer of silicon is deposited below the gate terminal.
LECTURE 4. FIELD EFFECT TRANSISTORS 47

Fig. 4.12: Symbols for Depletion Mode MOSFET.

The depletion mode MOSFET transistors are generally ON at zero gate-source voltage (VGS ). The con-
ductivity of the channel in depletion MOSFETs is less compared to the enhancement type of MOSFETs.
The depletion mode MOSFETs are generally known as ‘Switched ON’ devices, because these transistors
are generally closed when there is no bias voltage at the gate terminal. If the gate voltage increases in
positive, then the channel width increases in depletion mode. As a result the drain current ID through
the channel increases. If the applied gate voltage more negative, then the channel width is very less
and MOSFET may enter into the cutoff region. The depletion mode MOSFET is rarely used type of
transistor in the electronic circuits.

Fig. 4.13: I-V Characteristic curve.

The V-I characteristics of the depletion mode MOSFET transistor are given above. This characteristic
mainly gives the relationship between drain- source voltage (VDS ) and drain current (ID ). The small
voltage at the gate controls the current flow through the channel. The channel between drain and source
acts as a good conductor with zero bias voltage at gate terminal. The channel width and drain current
increases if the gate voltage is positive and these two (channel width and drain current) decreases if the
gate voltage is negative.
LECTURE 4. FIELD EFFECT TRANSISTORS 48

4.3.2 Enhancement Mode MOSFET

The Enhancement mode MOSFET is equivalent to “Normally Open” switch and these types of transistors
require gate-source voltage to switch ON the device. The symbols of both N-channel and P-channel
enhancement mode MOSFET transistors are shown below. Here we can observe that the broken line is
connected between the source and drain which represents the enhancement mode type. In enhancement
mode MOSFETs the conductivity increases by increasing the oxide layer which adds the carriers to the
channel. Generally, this oxide layer is called as ‘Inversion layer’. The channel is formed between the
drain and source in the opposite type to the substrate, such as N-channel is made with a P-type substrate
and P-channel is made with an N-type substrate.

Fig. 4.14: Symbols for Enhancement Mode MOSFET.

The conductivity of the channel due to electrons or holes depends on N-type or P-type channel respec-
tively. The Enhancement mode MOSFET is commonly used type of transistor. This type of MOSFET is
equivalent to normally-open switch because it does not conduct when the gate voltage is zero. If the pos-
itive voltage (+VGS ) is applied to the N-channel gate terminal, then the channel conducts and the drain
current flows through the channel. If this bias voltage increases to more positive then channel width and
drain current through the channel increases to some more. But if the bias voltage is zero or negative
(−VGS ) then the transistor may switch OFF and the channel is in non-conductive state. So now we can
say that the gate voltage of enhancement mode MOSFET enhances the channel.

Fig. 4.15: Enhancement Mode MOSFET I-V Characteristic curve.

LECTURE 4. FIELD EFFECT TRANSISTORS 49

Enhancement mode MOSFET transistors are mostly used as switches in electronic circuits because of
their low ON resistance and high OFF resistance and also because of their high gate resistance. These
transistors are used to make logic gates and in power switching circuits, such as CMOS gates, which have
both NMOS and PMOS Transistors. The V-I characteristics of enhancement mode MOSFET are shown
above which gives the relationship between the drain current (ID ) and the drain-source voltage (VDS ).
From the above figure we observed the behavior of an enhancement MOSFET in different regions, such
as ohmic, saturation and cut-off regions. MOSFET transistors are made with different semiconductor
materials. These MOSFETs have the ability to operate in both conductive and non-conductive modes
depending on the bias voltage at the input. This ability of MOSFET makes it to use in switching and
amplification.

4.3.3 MOSFET Amplifier Circuit

Like JFETs, the MOSFETs are also used to make single-stage amplifier circuits. The N-channel en-
hancement mode MOSFET with common source configuration is the mainly used type of amplifier
circuit than others. The depletion mode MOSFET amplifiers are very similar to the JFET amplifiers.
The input resistance of the MOSFET is controlled by the gate bias resistance which is generated by the
input resistors. The output signal of this amplifier circuit is inverted because when the gate voltage (VG )
is high the transistor is switched ON and when the voltage (VG ) is low then the transistor is switched
OFF.

Fig. 4.16: N-Channel MOSFET Amplifier.

The general MOSFET amplifier with common source configuration is shown above. This is an amplifier
of class A mode. Here the voltage divider network is formed by the input resistors R1 and R2 and the
input resistance for the AC signal is given as Rin = RG = 1MΩ. The equations to calculate the gate
voltage and drain current for the above amplifier circuit are given below.

R2
VG = VDD (4.6)
R1 + R2

and for Drain current we have,

LECTURE 4. FIELD EFFECT TRANSISTORS 50

VS
ID = (4.7)
RS

with VG as gate voltage, VS as input source voltage, VDD as supply voltage at drain, RS as source resis-
tance, and R1 & R2 as two input resistors. The different regions in which the MOSFET operates in their
total operation are discussed below.

4.3.3.1 Cut-off Region

If the gate-source voltage is less than the threshold voltage then we say that the transistor is operating in
the cut-off region (i.e. fully OFF). In this region drain current is zero (i.e. IDS = 0)and the transistor acts
as an open circuit.

VGS < VT H (4.8)

4.3.3.2 Ohmic (Linear) Region

If the gate voltage is greater than threshold voltage and the drain-source voltage lies between VT H and
(VGS –VT H ) then we say that the transistor is in linear region and at this state the transistor acts as a
variable resistor.

VGS > VT H (4.9)

and
VT H < VDS < VGS –VT H (4.10)

implies MOSFET acts as a variable resistor.

4.3.3.3 Saturation Region

In this region the gate voltage is much greater than threshold voltage and the drain current is at its
maximum value and the transistor is in fully ON state. In this region the transistor acts as a closed
circuit.

VGS >> VT H (4.11)

and
(VGS –VT H ) < VDS < 2(VGS –VT H ) (4.12)
LECTURE 4. FIELD EFFECT TRANSISTORS 51

implies IDS is maximum. The gate voltage at which the transistor ON and starts the current flow through
the channel is called threshold voltage. This threshold voltage value range for N-channel devices is in
between 0.5V to 0.7V and for P-channel devices is in between −0.5V to −0.8V .

4.3.4 MOSFET NOT Gate

Much like in the case of JFET, a NOT gate can also be constructed using MOSFET as shown in Figure
4.17 below.

Fig. 4.17: MOSFET NOT Gate.

4.3.5 MOSFET Summary

The behavior of a MOSFET transistor in depletion and enhancement modes depending on the gate volt-
age is summarized as follows.

Table 4.1: MOSFET Summary Table.

MOSFET Type VG > 0 VG = 0 VG < 0
P-Channel Enhancement OFF OFF ON
P-Channel Depletion OFF ON ON
N-Channel ENhancement ON OFF OFF
N-Channel Depletion ON ON OFF

MOSFET Applications include the following:

• MOSFETs are used in digital integrated circuits, such as microprocessors.

• Used in calculators.

• Used in memories and in logic CMOS gates.

• Used as analog switches.

LECTURE 4. FIELD EFFECT TRANSISTORS 52

• Used as amplifiers.

• Used in the applications of power electronics and switch mode power supplies.

• MOSFETs are used as oscillators in radio systems.

• Used in automobile sound systems and in sound reinforcement systems.

4.4 Common FET Configurations

Like the bipolar junction transistor, the field effect transistor being a three terminal device is capable of
three distinct modes of operation and can therefore be connected within a circuit in one of the following
configurations.

4.4.1 Common Source Configuration

In the Common Source configuration (similar to common emitter), the input is applied to the Gate and
its output is taken from the Drain as shown. This is the most common mode of operation of the FET due
to its high input impedance and good voltage amplification and as such Common Source amplifiers are
widely used.

Fig. 4.18: FET Common Source configuration.

The common source mode of FET connection is generally used audio frequency amplifiers and in high
input impedance pre-amps and stages. Being an amplifying circuit, the output signal is 180o “out-of-
phase” with the input.

4.4.2 Common Drain Configuration

In the Common Drain configuration (similar to common collector), the input is applied to the Gate and
its output is taken from the Source. The common drain or “source follower” configuration has a high
input impedance and a low output impedance and near-unity voltage gain so is therefore used in buffer
LECTURE 4. FIELD EFFECT TRANSISTORS 53

amplifiers. The voltage gain of the source follower configuration is less than unity, and the output signal
is “in-phase”, 0o with the input signal.

Fig. 4.19: FET Common Drain configuration.

This type of configuration is referred to as “Common Drain” because there is no signal available at the
drain connection, the voltage present, +VDD just provides a bias. The output is in-phase with the input.

4.4.3 Common Gate Configuration

In the Common Gate configuration (similar to common base), the input is applied to the Source and its
output is taken from the Drain with the Gate connected directly to ground (0V ) as shown. The high input
impedance feature of the previous connection is lost in this configuration as the common gate has a low
input impedance, but a high output impedance.

Fig. 4.20: FET Common Gate configuration.

This type of FET configuration can be used in high frequency circuits or in impedance matching circuits
were a low input impedance needs to be matched to a high output impedance. The output is “in-phase”
with the input.
Lecture 5

Logic Families and Binary Representation

5.1 Logic Families

5.1.1 Overview

The choice of logic levels is arbitrary, but all gates that communicate must have compatible logic levels.
Therefore, gates are grouped into logic families such that all gates in a logic family obey the static
discipline when used with other gates in the family. Logic gates in the same logic family are compatible
in that, they use consistent power supply voltages and logic levels. A logic family is a circuit technology
that can be used to create many different types of gates: inverter, NAND, NOR, etc. Most logic today is
based on CMOS logic families based on MOSFETs.

If we mix logic from two different logic families, we need to be careful to obey the input and output signal
specifications. These specifications also limit our ability to connect logic gates to nonlogic circuits. For
example, a logic gate may not be able to supply enough current to directly drive a speaker.

5.1.2 Common Logic Families

There are many logic families but in this section we will limit ourselves to three major common logic
families. These families are TTL, ECL and CMOS as described briefly in section below. There are
various other families such as dynamic current mode logic (DCML) which operates in differential mode
(hence reducing crosstalk) for small swings (hence leading to fast switching).

5.1.2.1 TTL Family

In transistor-transistor logic (TTL), logic gates and other digital circuits are made using BJTs and resis-
tors. The term transistor-transistor is indicative of the fact that both logic function and amplification are
done by transistors. Using TTL logic family, many logic gate can be fabricated in a single circuit. For

54
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 55

logic gates built using TTL logic family, inputs are given to the emitter of the input transistor. In TTL
logic family, the analog voltage value from 0.0V to 0.8V is regarded as logic 0 while the analog voltage
value from 2.0V to 5.0V is regarded as logic 1. Advantage of TTL logic family is include high switching
speed (125MHz), less noise and more current (3mA) driving capability. One of the logic families closely
related to TTL family is the Low Voltage TTL Logic (LVTTL).

5.1.2.2 ECL Family

Emitter coupled logic (ECL), also referred to as current mode logic family, is a digital technology with
extremely high-speed. Transistors are not allowed to to go into deep saturation thus, eliminating storage
delays like in TTL family. Transistors are driven either in cut-off or in active region. This is achieved by
using voltage values close to each other. For logic one it is -0.90V and for logic zero, it is -1.75V. In the
active region, charge stored in the base region of transistors is kept to minimum. The difference between
these logic states is very small. This improves the speed of operation at the expense of noise margin.
Propagation time for an ECL gate is 0.5 ns to 2 ns which is very low compared to its TTL counterpart.

The disadvantage of ECL family is that it uses a negative power supply such that the logic levels are not
compatible with any other logic family and makes analysis and measurement inconvenient. ECL family
requires large currents, therefore power dissipation is three to ten times higher than that of TTL family.
Because of its large power consumption and high requirement of silicon area, CMOS logic family gates
are preferred over ECL family in large scale integrated circuits.

5.1.2.3 CMOS Logic Family

Because of high noise immunity and low static power dissipation, now the complementary metal oxide
semiconductor (CMOS) logic family is most preferred in large scale integrated circuits. CMOS has
complementary and symmetrical NMOS and PMOS transistors. For an inverter circuit only one transistor
if the CMOS will be ON at a time for an inverter thereby reducing static power loss of a transistor. One
of the closely related families is the Low Voltage CMOS Logic (LVCMOS).

5.1.3 Further Classifications

5.1.3.1 Types of Logic Family

The digital integrated circuits are designed using bipolar devices or Metal Oxide Semiconductor (MOS)
or a combination of both. There are two kinds of semiconductor devices. The logic family which falls
under the first kind Bipolar logic family and the other is Unipolar logic family.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 56

5.1.3.2 Bipolar Logic Family

There are two kinds of operations in bipolar integrated circuits:

(a). Saturated Bipolar Logic family and

(b). Non-saturated Bipolar Logic family.

Saturated Bipolar Logic Families are:

• Diode Logic (DL)

• Resistor Transistor Logic (RTL)

• Diode Transistor Logic (DTL)

• Integrated Injection Logic (IIL or I2L)

• Transistor Transistor Logic (TTL)

Non-saturated Bipolar Logic Families are:

• Schottky TTL

• Emitter Coupled Logic (ECL)

5.1.3.3 Unipolar Logic Family

Unipolar logic family consists of;

(a). Metal Oxide Semiconductor (MOS) Logic families.

They are:

• P-type MOS (PMOS) Logic

• N-type MOS (NMOS) Logic

• Complementary MOS (CMOS) Logic

• Bipolar MOS (BiMOS) Logic

• Bipolar CMOS (BiCMOS) Logic

LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 57

5.1.3.4 Classification of Logic Family

Logic families are mainly classified as;

(a). Bipolar Logic Families and

(b). Unipolar Logic Families.

Bipolar Logic Families

It mainly uses bipolar devices like diodes, transistors in addition to passive elements like resistors and
capacitors. These are sub-classified as saturated bipolar logic family and unsaturated bipolar logic family.

Saturated Bipolar Logic Family: In this family the transistors used in ICs are driven into saturation.
For example:

• Transistor-Transistor Logic (TTL)

• Resistor-Transistor Logic (RTL)

• Direct Coupled Transistor Logic (DCTL)

• Diode Transistor Logic (DTL)

• High Threshold Logic (HTL)

• Integrated Injection Logic (IIL or I2L)

Unsaturated bipolar logic family: In this family the transistors used in IC is not driven into saturation.
For example:

• Schottky TTL

• Emitter Coupled Logic(ECL)

Unipolar Logic Families

It mainly uses Unipolar devices like MOSFETs in addition to passive elements like resistors and capaci-
tors. These logic families have the advantages of high speed and lower power consumption than Bipolar
families. These are classified as:

(a). PMOS or P-Channel MOS Logic Family

(b). NMOS or N-Channel MOS Logic Family

(c). CMOS Logic Family

LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 58

Table 5.1: Logic levels of different logic families.

Family VDD VIL VIH VOL VOH
TTL 5.0 (4.75 - 5.25) 0.8 2.0 0.4 2.4
CMOS 5.0 (4.50 - 6.00) 1.35 3.15 0.33 3.84
LVTTL 3.3 (3.00 - 3.60) 0.8 2.0 0.4 2.4
LVCMOS 3.3 (3.00 - 3.60) 0.9 1.8 0.4 2.7

5.1.3.5 Features of Some Logic Families

(a). TTL - Transistor-Transistor Logic: Standard logic family; used for the longest time.

(b). ECL - Emitter Coupled Logic: Suitable for systems requiring high-speed operations.

(c). MOS - Metal Oxide Semiconductor Logic: Suitable for systems with high component density.

(d). CMOS - Complementary Metal Oxide Semiconductor Logic: Suitable for systems with low power
consumption (VLSI circuits). Gradually becomes the dominant logic family.

5.1.4 Characteristics

The main characteristics of logic families include:

• Speed: Time between input applied and output received.

• Fanin: The number of inputs a logic gate can handle.

• Fanout: The number of circuits a logic gate can drive.

• Noise immunity: Maximum noise that a circuit can withstand without affecting the output.

• Power dissipation: When a circuit switches from one state to another, power is dissipated.

• Supply voltage range: A range of voltage values allowed at logic gate supply pin.

• I/O logic levels: A range of allowed voltage values defining input and output levels of a logic gate.

Fanin and fanout can also be related to current sinking and sourcing capabilities. These characteristics
can also be used as objective measures for comparing the performance different logic families. Size, cost
of production and flexibility can also be added to the list above.

5.1.5 Comparison and Compatibility

The logic levels of four chosen logic families are compared in table 5.1.

Note that a 5 V logic family such as TTL or CMOS may produce an output voltage as HIGH as 5 V. If
this 5 V signal drives the input of a 3.3 V logic family such as LVTTL or LVCMOS, it can damage the
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 59

Table 5.2: Logic families compatibility.

Driver TTL Receiver CMOS Receiver LVTTL Receiver LVCMOS Receiver
TTL Ok No Maybe Maybe
CMOS Ok Ok Maybe Maybe
LVTTL Ok No Ok Ok
LVCMOS Ok No Ok Ok

receiver, unless the receiver is specially designed to be 5-volt-compatible. Table outlines which of the
logic families in table 5.1 can communicate with each other reliably based only on their logic levels

Given this basic understanding of how these logic families work, we can set up a scenario in which
each logic families fail. The mechanisms by which they fail are different due to the different operating
characteristics of the families. CMOS is sensitive to fanout, which is the number of gates attached to the
output of a driver gate. Some logic families are also sensitive to fanin constraints, which is the number
of gates connected to the input of a given gate. Capacitance is at the root of the fanout problem. In
practice, the load capacitance is the gate capacitance of the transistors that form the next logic gate. As
fanout increases, the capacitive load increases.

Typically the input capacitances of the load gates are in parallel so we can add them to find the total
load capacitance. The voltage across this capacitance is equal to the input voltage at each fanout gate;
all fanout gates see the same input voltage. This voltage waveform is a simple ramp which increases
steadily until it reaches the power supply voltage, at which point the driver transistor turns off. The slope
of the ramp depends on the ratio of the load capacitance and the driver current. The output current is
determined by the logic family.

As the load capacitance increases, the slope decreases and the time required for the voltage to reach its
final value increases. Interfaces have timing requirements, which is a maximum delay from the change of
an input to the change at its output. If the slope of the voltage waveform is shallow enough, the logic fails
to satisfy its timing requirement. Given these illustrations of the importance of electrical specifications
to the proper function of logic gates, we can now look at the specifications themselves.

Most logic families represent logic values as voltages; a few logic families use currents to represent logi-
cal values. We talk informally about a high voltage representing a logic 1 and a low voltage representing
a logic 0. In fact, a range of voltages can be used to represent logic values. Accepting a range of signal
values protects the logic functions against noise, which is inevitable in real circuits. Intermediate values
represent invalid logic values. Leaving a gap between the valid logic 0 and logic 1 levels also contributes
to noise immunity. The next section elaborates more on the binary number representation as a means of
representing logic values.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 60

5.2 Binary Number Representation

5.2.1 Number Base Conversion

There are many number systems differing by the base. One of the most common number system is
decimal which uses base ten. There are other numbering systems based on different bases including the
following;

• Binary: Uses base two.

• Octal: Uses base eight.

• Hexadecimal: Uses base sixteen.

In this section we will limit ourselves to binary and decimal. We will proceed to discuss the conversion
between decimal and binary in the next sections.

5.2.1.1 Decimal To Binary

We can convert from decimal to binary by using long division (by 2 as a base number) techniques and
keeping remainders as digits of our binary number. Here is an example with a decimal number 10810 .
Here are the steps:

(a). Divide 108 by 2 to get 54 remainder 0,

(b). Divide 54 by 2 to get 27 remainder 0,

(c). Divide 27 by 2 to get 13 remainder 1,

(d). Divide 13 by 2 to get 6 remainder 1,

(e). Divide 6 by 2 to get 3 remainder 0,

(f). Divide 3 by 2 to get 1 remainder 1,

(g). Divide 1 by 2 to get 0 remainder 1,

(h). Now that we arrived at zero, we stop dividing. We combine all the remainders (starting from the
most recent remainder all the way to the oldest one) to get a binary number 11011002 .

Therefore, we can conclude that the binary conversion of a decimal number 10810 is 11011002 . Here is
another example with a decimal number 17010 ,

(a). Divide 170 by 2 to get 85 remainder 0,

LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 61

(b). Divide 85 by 2 to get 42 remainder 1,

(c). Divide 42 by 2 to get 21 remainder 0,

(d). Divide 21 by 2 to get 10 remainder 1,

(e). Divide 10 by 2 to get 5 remainder 0,

(f). Divide 5 by 2 to get 2 remainder 1,

(g). Divide 2 by 2 to get 1 remainder 0,

(h). Divide 1 by 2 to get 0 remainder 1,

(i). Now that we arrived at zero, we stop dividing. We combine all the remainders (starting from the
most recent remainder all the way to the oldest one) to get a binary number 101010102 .

Therefore, we can conclude that the binary conversion of a decimal number 17010 is 101010102 .

5.2.1.2 Binary To Decimal

Converting from binary to decimal is a bit easier than converting from decimal to binary. We will
demonstrate the conversion using an example. Given a binary number, we convert it to decimal by
treating each digit as if it is a coefficient in a polynomial and the position of that digit is treated as a
power/exponent of a base number 2. The positions of the digits starts from zero at the least significant
bit (LSB) and increases all the way to the most significant bit (MSB). The sum of all the polynomial
terms will give us the decimal number equivalent to the given binary number. As an example, let us
convert the binary number 011011002 to decimal. We write this as follows,

011011002 ⇒ 0 × 27 + 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22 + 0 × 21 + 0 × 20 = 10810

Therefore, the decimal equivalent of the binary number 011011002 is 10810 . Here is another example
for binary number 101010102 .

101010102 ⇒ 1 × 27 + 0 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 0 × 20 = 17010

Therefore, the decimal equivalent of the binary number 101010102 is 17010 .

5.2.2 Unsigned Binary Numbers

5.2.2.1 Overview

We can make the binary numbers into the following two groups − Unsigned numbers and Signed num-
bers. Unsigned numbers contain only magnitude of the number. They don’t have any sign. That means
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 62

all unsigned binary numbers are positive. As in decimal number system, the placing of positive sign
in front of the number is optional for representing positive numbers. Therefore, all positive numbers
including zero can be treated as unsigned numbers if positive sign is not assigned in front of the number.

5.2.2.2 Representation

The bits present in the un-signed binary number holds the magnitude of a number. That means, if the
un-signed binary number contains ‘N’ bits, then all N bits represent the magnitude of the number, since
it doesn’t have any sign bit. As an example, consider the decimal number 108. The binary equivalent of
this number is 1101100. This is the representation of unsigned binary number.

10810 = 11011002

It is having 7 bits. These 7 bits represent the magnitude of the number 108.

5.2.3 Signed Binary Numbers

5.2.3.1 Overview

Signed numbers contain both sign and magnitude of the number. Generally, the sign is placed in front
of number. So, we have to consider the positive sign for positive numbers and negative sign for negative
numbers. Therefore, all numbers can be treated as signed numbers if the corresponding sign is assigned
in front of the number. If sign bit is zero, which indicates the binary number is positive. Similarly, if
sign bit is one, which indicates the binary number is negative.

5.2.3.2 Representation

The MSB (Most Significant Bit) of signed binary numbers is used to indicate the sign of the numbers.
Hence, it is also called as sign bit. The positive sign is represented by placing ‘0’ in the sign bit.
Similarly, the negative sign is represented by placing ‘1’ in the sign bit. If the signed binary number
contains ‘N’ bits, then N − 1 bits only represent the magnitude of the number since one bit MSB is
reserved for representing sign of the number.

There are three types of representations for signed binary numbers which are Sign-Magnitude form, 1’s
complement form, and 2’s complement form. Representation of a positive number in all these three
forms is the same while the representation of negative number will differ in each form. As an example,
consider the positive decimal number +108. The binary equivalent of magnitude of this number is
1101100. These 7 bits represent the magnitude of the number 108. Since it is a positive number, consider
the sign bit as zero, which is placed on left most side of magnitude.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 63

+10810 = 011011002

Therefore, the signed binary representation of positive decimal number +108 is 01101100. The same
representation is valid in sign-magnitude form, 1’s complement form and 2’s complement form for pos-
itive decimal number +108.

Sign-Magnitude Form

In sign-magnitude form, the MSB is used for representing sign of the number and the remaining bits
represent the magnitude of the number. So, just include sign bit at the left most side of unsigned binary
number. This representation is similar to the signed decimal numbers representation. As an example,
consider the negative decimal number −108. The magnitude of this number is 108. We know the
unsigned binary representation of 108 is 1101100. It is having 7 bits. All these bits represent the
magnitude. Since the given number is negative, consider the sign bit as one, which is placed on left most
side of magnitude.

−10810 = 111011002

Therefore, the sign-magnitude representation of −108 is 11101100.

1’s Complement Form

The 1’s complement of a number is obtained by complementing all the bits of signed binary number.
Therefore, the 1’s complement of positive number gives a negative number. Similarly, 1’s complement
of negative number gives a positive number. That means, if you perform two times 1’s complement of a
binary number including sign bit, then you will get the original signed binary number. As an example,
consider the negative decimal number −108. The magnitude of this number is 108. We know the signed
binary representation of 108 is 01101100. It is having 8 bits. The MSB of this number is zero, which
indicates positive number. Complement of zero is one and vice-versa. So, replace zeros by ones and all
ones by zeros in order to get the negative number.

−10810 = 100100112

Therefore, the 1’s complement of 10810 is 100100112 .

2’s Complement Form

The 2’s complement of a binary number is obtained by adding one to the 1’s complement of signed binary
number. So, 2’s complement of positive number gives a negative number. Similarly, 2’s complement
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 64

of negative number gives a positive number. That means, if you perform two times 2’s complement
of a binary number including sign bit, then you will get the original signed binary number. As an
example, consider again the negative decimal number −108. We know the 1’s complement of (108)10 is
(10010011)2 . The 2’s compliment of 10810 = 1’s compliment of 10810 + 110 which is,

10810 + 110 = 100100112 + 12 = 100101002

Therefore, the 2’s complement of 10810 is 100101002 .

5.2.3.3 Addition Operation

Consider the two signed binary numbers A & B, which are represented in 2’s complement form. We
can perform the addition of these two numbers, which is similar to the addition of two unsigned binary
numbers. But, if the resultant sum contains carry out from sign bit, then discard or ignore it in order to
get the correct value. If resultant sum is positive, you can find the magnitude of it directly. But, if the
resultant sum is negative, then take 2’s complement of it in order to get the magnitude. As an example,
let us perform the addition of two decimal numbers +7 and +4 using 2’s complement method. The 2’s
complement representations of +7 and +4 with 5 bits each are shown below.

+710 = 001112

+410 = 001002

The addition of these two numbers is,

(+7)10 + (+4)10 = 001112 + 001002 = 010112

The resultant sum contains 5 bits. So, there is no carry out from sign bit. The sign bit ‘0’ indicates that
the resultant sum is positive. So, the magnitude of sum is 11 in decimal number system. Therefore,
addition of two positive numbers will give another positive number. As another example, let us perform
the addition of two decimal numbers −7 and −4 using 2’s complement method. The 2’s complement
representation of −7 and −4 with 5 bits each are shown below.

−710 = 110012

−410 = 111002
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 65

The addition of these two numbers is,

(−7)10 + (−4)10 = 110012 + 111002 = 1101012

The resultant sum contains 6 bits. In this case, carry is obtained from sign bit. So, we can remove it such
that the resultant sum after removing carry is 101012 . The sign bit ‘1’ indicates that the resultant sum is
negative. So, by taking 2’s complement of it we will get the magnitude of resultant sum as 11 in decimal
number system. Therefore, addition of two negative numbers will give another negative number.

5.2.3.4 Subtraction Operation

Consider the two signed binary numbers A and B, which are represented in 2’s complement form. We
know that 2’s complement of positive number gives a negative number. So, whenever we have to subtract
a number B from number A, then take 2’s complement of B and add it to A. Mathematically we can write
it as,

A − B = A + 20s complement of B

Similarly, if we have to subtract the number A from number B, then take 2’s complement of A and add it
to B. So, mathematically we can write it as,

B − A = B + 20s complement of A

The subtraction of two signed binary numbers is similar to the addition of two signed binary numbers.
But, we have to take 2’s complement of the number, which is supposed to be subtracted. This is the
advantage of 2’s complement technique. We follow the same rules of addition of two signed binary
numbers. As an example let us perform the subtraction of two decimal numbers +7 and +4 using 2’s
complement method. The subtraction of these two numbers is

(+7)10 − (+4)10 = (+7)10 + (−4)10

The 2’s complement representation of +7 and −4 with 5 bits each are shown below.

+710 = 001112

−410 = 111002
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 66

Here, the carry obtained from sign bit. So, we can remove it. The resultant sum after removing carry is

(+7)10 + (−4)10 = 001112 + 111002 = 000112

The sign bit ‘0’ indicates that the resultant sum is positive. So, the magnitude of it is 3 in decimal
number system. Therefore, subtraction of two decimal numbers +7 and +4 is +3. As another example,
let us perform the subtraction of two decimal numbers +4 and +7 using 2’s complement method. The
subtraction of these two numbers is

(+4)10 − (+7)10 = (+4)10 + (−7)10

The 2’s complement representation of +4 and −7 with 5 bits each are shown below.

+410 = 001002

−710 = 110012

In this case the sum becomes,

+410 + −710 = 001002 + 110012 = 111012

Here, carry is not obtained from the sign bit. The sign bit ‘1’ indicates that the resultant sum is negative.
By taking 2’s complement of it we will get the magnitude of resultant sum as 3 in decimal number
system. Therefore, subtraction of two decimal numbers +4 and +7 is −3.

5.2.4 Reflected Binary (or Gray) Code

This an ordering of the binary numeral system such that two successive values differ in only one bit
(binary digit). Gray codes are very useful in the normal sequence of binary numbers generated by the
hardware that may cause an error or ambiguity during the transition from one number to the next. This
means the Gray code can eliminate this problem easily since only one bit changes its value during any
transition between two numbers. The following table shows the first sixteen (or four-bit) Gray codes
along with their corresponding decimal and binary.

There are several ways of converting between binary and Gray code, such as using Karnaugh map and
exclusive OR operation. We will deal with these methods in a few lectures to comes.
LECTURE 5. LOGIC FAMILIES AND BINARY REPRESENTATION 67

Table 5.3: Gray codes and their corresponding binary and decimal equivalents.
Gray Code Binary Decimal
0000 0000 00
0001 0001 01
0011 0010 02
0010 0011 03
0110 0100 04
0111 0101 05
0101 0110 06
0100 0111 07
1100 1000 08
1101 1001 09
1111 1010 10
1110 1011 11
1010 1100 12
1011 1101 13
1001 1110 14
1000 1111 15
Lecture 6

Logic Gates and Boolean Logic

Logic gates have a lot of applications but they are mainly based upon their mode of operations or their
truth table. Basic logic gates are often found in circuits such as safety thermostat, push-button lock,
automatic watering system, light-activated burglar alarm and many other electronic devices. One of
the primary benefits is that basic logic gates can be used in a mixture of different combinations if the
operations are advanced. Besides, there is no limit to the number of gates that can be used in a single
device. However, it can be restricted due to the given physical space in the device. In digital integrated
circuits (ICs) we will find an array of the logic gate area unit.

In this lecture we will study some basic logic gates and their operations. We will also learn two methods
of simplifying logic circuits (or simplifying Boolean expressions) and those are:

(a). Boolean Algebra

(b). Karnaugh Mapping

These simplification method will be very useful in various electronics courses and projects where one
has to design or analyze integrated digital circuits.

6.1 Logic Gates

These are important digital devices that are mainly based on the Boolean function. Logic gates are used
to carry out logical operations on single or multiple binary inputs and give one binary output. In simple
terms, logic gates are the electronic circuits in a digital system.

6.1.1 Basic Logic Gates

There are several basic logic gates used in performing operations in digital systems. The common ones
are;

68
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 69

(a). OR Gate

(b). AND Gate

(c). NOT Gate

(d). XOR Gate

Additionally, these gates can also be found in a combination of one or two. Therefore we get other gates
such as;

(a). NAND Gate,

(b). NOR Gate,

(c). XOR Gate,

(d). XNOR Gate.

6.1.2 OR Gate

Fig 6.1 below shows the symbol for an OR gate.

Fig. 6.1: An OR Gate symbol.

In OR gate the output of an OR gate attains the state 1 if one or more inputs attain the state 1, otherwise
the output is zero. The Boolean expression of OR gate is Y = A + B, read as Y equals A ‘OR’ B. The
truth table of a two-input OR basic gate is given in Table 6.1 below.

Table 6.1: OR Gate truth table.

A B Y
0 0 0
0 1 1
1 0 1
1 1 1
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 70

6.1.3 AND Gate

In AND gate the output of an AND gate attains the state 1 if and only if all the inputs are in state 1. The
Boolean expression of AND gate is Y = A.B. Fig. 6.2 below shows the symbol for an AND gate.

Fig. 6.2: AND Gate symbol.

The truth table of a two-input AND basic gate is given in Table 6.2 below.

Table 6.2: AND Gate truth table.

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

6.1.4 NOT Gate

In NOT gate the output of a NOT gate attains the state 1 if and only if the input does not attain the state
1. The Boolean expression is Y = Ā , read as Y equals NOT A. The symbol of NOT gate is in Fig. 6.3
below.

Fig. 6.3: NOT Gate symbol.

Table 6.3 below shows the truth table of a NOT gate.

Table 6.3: NOT Gate truth table.

A Y
0 1
1 0

6.1.5 NAND Gate

This basic logic gate is the combination of AND and NOT gate. The Boolean expression of NAND gate
is Y = A · B. The symbol of a NAND gate is shown in Fig. 6.4 below.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 71

Fig. 6.4: NAND Gate Symbol.

Table 6.4 below shows the truth table of a NAND gate.

Table 6.4: NAND Gate truth table.

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

6.1.6 NOR Gate

This gate is the combination of OR and NOT gate. The Boolean expression of NOR gate is Y = A + B.
The symbol for a NOR gate is shown in Fig. 6.5 below.

Fig. 6.5: NOR Gate symbol.

Table 6.5 below shows the truth table for a NOR gate.

Table 6.5: NOR Gate truth table.

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

6.1.7 XOR Gate

In XOR gate the output of a two-input XOR gate attains the state 1 if one adds only input attains the state
L
1. The Boolean expression of the XOR gate is Y = ĀB + AB̄ = A B. The symbol for an XOR gate is
shown in 6.6 below.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 72

Fig. 6.6: XOR Gate symbol.

Table 6.6 below shows the truth table of an XOR gate.

Table 6.6: XOR Gate truth table.

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Fig. 6.7 below shows the circuit representation of XOR gate in terms of NOT, AND and OR gates.

Fig. 6.7: XOR Gate symbol.

6.1.8 XNOR Gate

In XNOR gate the output is in state 1 when its both inputs are the same that is, both 0 or both 1. The
Boolean expression of XNOR gate is Y = A B = ĀB + AB̄ = (A + B)(A + B) = AB + AB. The logic
symbol of XNOR gate is shown in Fig. 6.8 below.

Fig. 6.8: XNOR Gate symbol.

Table 6.7 below shows the truth table of an XNOR gate.

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 73

Table 6.7: XNOR Gate truth table.

A B Y
0 0 1
0 1 0
1 0 0
1 1 1

Fig. 6.9 below shows the circuit representation of XNOR gate as a cascade of XOR and NOT gates.

Fig. 6.9: XNOR Gate construction.

6.2 Boolean Algebra

6.2.1 Boolean Expressions Forms

In Boolean expressions we use a plus or sum sign to represent logic operation OR and we also use a dot
or product sign to represent the logic operation AND. Sometimes we omit the dot sign when indicating
AND operation in expressions. Below we outline three standard forms of Boolean expressions.

6.2.1.1 Sum of Products (SOP)

First the product (AND) terms are formed then these are summed (OR). For example we can have the
following expression,

f (A, B,C, D, E, F, G, H, I) = ABC + DEF + GHI

The expression above is the sum of three products. We can use de Morgan’s law to covert this expression
to the product of sums representation.

6.2.1.2 Product of Sums (POS)

First the sum (OR) terms are formed then the products are taken (AND). For example we can have the
following expression

f (A, B,C, D, E, F, G, H, I) = (A + B +C)(D + E + F)(G + H + I)

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 74

It is possible to convert the expression above to the sum of products representation using de Morgan’s
law.

6.2.1.3 Canonical Form (CF)

Canonical form is not efficient but sometimes useful in analysis and design. In an expression in canonical
form, every variable appears in every term as shown in the example below,

f (A, B,C, D) = ABCD + ABCD + ABCD

An SOP expression can be forced into canonical form by ANDing the incomplete terms with terms of
the form (X + X)where X is the name of the missing variable. For example,

f (A, B,C) = AB + BC

= AB(C +C) + (A + A)BC

= ABC + ABC + ABC + ABC

= ABC + ABC + ABC

The product term in a canonical SOP expression is called a minterm

6.2.2 Boolean Algebraic Laws

A set of rules or Laws of Boolean Algebra expressions have been invented to help reduce the number
of logic gates needed to perform a particular logic operation resulting in a list of functions or theorems
known commonly as the Laws of Boolean Algebra. Boolean Algebra is the Mathematics we use to
analyze digital gates and circuits. We can use these “Laws of Boolean” to both reduce and simplify
a complex Boolean expression in an attempt to reduce the number of logic gates required. Boolean
Algebra is therefore a system of Mathematics based on logic that has its own set of rules or laws which
are used to define and reduce Boolean expressions.

The variables used in Boolean Algebra only have one of two possible values, a logic “0” and a logic “1”
but an expression can have an infinite number of variables all labeled individually to represent inputs to
the expression. For example, variables A, B, C etc, giving us a logical expression of A + B = C, but each
variable can only be a 0 or a 1. Examples of these individual laws of Boolean, rules and theorems for
Boolean Algebra are given in the following table in Fig. 6.10.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 75

Fig. 6.10: Boolean Algebra Laws.

6.2.2.1 Annulment Law

Any input A AND´ed with a “0” equals 0 or OR´ed with a “1” will equal 1 A as shown below.

• A · 0 = 0: A variable AND’ed with 0 is always equal to 0.

• A + 1 = 1: A variable OR’ed with 1 is always equal to 1.

6.2.2.2 Identity Law

A term OR´ed with a “0” or AND´ed with a “1” will always equal that term as shown below.

A + 0 = A: A variable OR’ed with 0 is always equal to the variable.

A · 1 = A: A variable AND’ed with 1 is always equal to the variable.

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 76

6.2.2.3 Idempotent Law

An input that is AND´ed or OR´ed with itself is equal to that input as shown below.

A + A = A: A variable OR’ed with itself is always equal to the variable.

A · A = A : A variable AND’ed with itself is always equal to the variable

6.2.2.4 Complement Law

A term AND´ed with its complement equals “0” and a term OR´ed with its complement equals “1” as
shown below.

A · Ā = 0: A variable AND’ed with its complement is always equal to 0.

A + Ā = 1: A variable OR’ed with its complement is always equal to 1.

6.2.2.5 Commutative Law

The order of application of two separate terms is not important as shown below.

A · B = B · A: The order in which two variables are AND’ed makes no difference.

A + B = B + A: The order in which two variables are OR’ed makes no difference.

6.2.2.6 Double Negation Law

A term that is inverted twice is equal to the original term as shown below.
=
A = A: A double complement of a variable is always equal to the variable.

6.2.2.7 de Morgan´s Theorem

There are two de Morgan´s rules or theorems,

(a). Two separate terms NOR´ed together is the same as the two terms inverted (Complement) and
AND´ed for example: A + B = A · B

(b). Two separate terms NAND´ed together is the same as the two terms inverted (Complement) and
OR´ed for example: A · B = A + B
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 77

6.2.2.8 Boolean Postulates

While not Boolean Laws in their own right, these are a set of Mathematical Laws which can be used in
the simplification of Boolean Expressions.

• 0 · 0 = 0: A 0 AND’ed with itself is always equal to 0.

• 1 · 1 = 1: A 1 AND’ed with itself is always equal to 1.

• 1 · 0 = 0: A 1 AND’ed with a 0 is equal to 0.

• 0 + 0 = 0: A 0 OR’ed with itself is always equal to 0.

• 1 + 1 = 1: A 1 OR’ed with itself is always equal to 1.

• 1 + 0 = 1: A 1 OR’ed with a 0 is equal to 1.

• 1 = 0: The Inverse (Complement) of a 1 is always equal to 0.

• 0 = 1: The Inverse (Complement) of a 0 is always equal to 1.

6.2.2.9 Distributive Law

This law permits the multiplying or factoring out of an expression.

• OR Distributive Law: A(B + C) = A · B + A · C

• AND Distributive Law: A + (B · C) = (A + B) · (A + C)

6.2.2.10 Absorptive Law

This law enables a reduction in a complicated expression to a simpler one by absorbing like terms.

• OR Absorption Law: A + (A · B) = (A · 1) + (A · B) = A(1 + B) = A

• AND Absorption Law: A(A + B) = (A + 0) · (A + B) = A + (0.B) = A

6.2.2.11 Associative Law

This law allows the removal of brackets from an expression and regrouping of the variables.

• OR Associate Law: A + (B + C) = (A + B) + C = A + B + C

• AND Associate Law: A(B · C) = (A · B)C = A · B · C

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 78

6.2.3 Boolean Algebra Functions

Using the information above, simple 2-input AND, OR and NOT Gates can be represented by 16 possible
functions as shown in the following table in Fig. 6.11 below.

Fig. 6.11: Boolean Algebra functions.

6.2.4 Boolean Logic Laws Applied

As a way to demonstrate the application of Boolean Logic Laws let us simplify the expression Q =
(A + B) · (A +C). The steps for simplifying this expression are outlined in the Fig. 6.12 below.

Fig. 6.12: Example of Boolean logic laws applied.

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 79

6.3 Karnaugh Mapping

The Karnaugh map (KM or K-map), first introduced by Maurice Karnaugh in 1953, is a method of sim-
plifying Boolean algebra expressions. The Karnaugh map reduces the need for extensive calculations by
taking advantage of human’s pattern-recognition capability. The required Boolean results are transferred
from a truth table onto a two-dimensional grid (called K-map) where the cells are ordered in Gray code
and each cell position represents one combination of input conditions. Each cell value represents the
corresponding output value of the Boolean function. Optimal groups of 1s or 0s are identified, which
represent the terms of a canonical form of the logic in the original truth table. These terms can be used
to write a minimal Boolean expression representing the required logic.

Karnaugh maps are used to simplify real-world logic requirements so that they can be implemented using
a minimum number of logic gates. A sum-of-products expression (SOP) can always be implemented
using AND gates feeding into an OR gate, and a product-of-sums expression (POS) leads to OR gates
feeding an AND gate. The POS expression gives a complement of the function (if F is the function so
its complement will be F). Karnaugh maps can also be used to simplify logic expressions in software
design. Boolean conditions, as used for example in conditional statements, can get very complicated,
which makes the code difficult to read and to maintain.

Once minimized, canonical sum-of-products and product-of-sums expressions can be implemented di-
rectly using AND and OR logic operators. In many digital circuits and practical problems we need to
find expression with minimum variables. We can minimize Boolean expressions of 2, 3, or 4 variables
very easily using the K-map without using any Boolean algebra theorems. The K-map can take two
forms Sum of Product (SOP) and Product of Sum (POS) according to the needs of the problem. The
K-map is table-like representation but it gives more information than truth table.

6.3.1 Filling Karnaugh Maps

We fill the grid of K-map with 0’s and 1’s then solve it by making groups. The order of filling following
the Gray code numbering order. The following tables show the order of filling K-maps.

6.3.1.1 Two-Variable Map

The filling order of a two-variable K-map (for a two-input logic system) is shown in Table 6.8 below.

Table 6.8: A two-variable K-map.

A\B 0 1
0 0th 1st
1 2nd 3rd

As an example suppose we have a logic system with the following truth table in Table 6.9 below.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 80

Table 6.9: Two-variable input logic system’s truth table.

A B Output Y
0 0 Y0
0 1 Y1
1 0 Y2
1 1 Y3

We are going to fill this truth table in our two-variable Karnaugh map as shown in Table 6.10 below.

Table 6.10: A two-variable K-map.

A\B 0 1
0 Y0 Y1
1 Y2 Y3

6.3.1.2 Three-Variable Map

The filling order of a three-variable K-map (for a three-input logic system) is shown in Table 6.11 below.

Table 6.11: A three-variable K-map.

A\BC 00 01 11 10
0 0th 1st 3rd 2nd
1 4th 5th 7th 6th

As an example, suppose we want to fill in the K-map of a three-variable logic system whose truth table
is shown in Table 6.12 below.

Table 6.12: Two-variable input logic system’s truth table.

A B C Output Y
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7

We are going to fill this truth table in our three-variable Karnaugh map as shown in Table 6.13 below.

Table 6.13: A three-variable K-map.

A\BC 00 01 11 10
0 Y0 Y1 Y3 Y2
1 Y4 Y5 Y7 Y6
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 81

6.3.1.3 Four-Variable Map

The filling order of a four-variable K-map (for a four-input logic system) is shown in Table 6.14 below.

Table 6.14: A four-variable K-map.

AB\CD 00 01 11 10
00 0th 1st 3rd 2nd
01 4th 5th 7th 6th
11 12th 13th 15th 14th
10 8th 9th 11th 10th

As an example, consider the following truth table in Table 6.15 that needs to be filled in a K-map.

Table 6.15: Two-variable input logic system’s truth table.

A B C D Output Y
0 0 0 0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15

The K-map will be filled as shown in the Table 6.16 below.

Table 6.16: A four-variable K-map.

AB\CD 00 01 11 10
00 Y 0 Y1 Y3 Y2
01 Y4 Y5 Y7 Y6
11 Y12 Y13 Y15 Y14
10 Y8 Y9 Y11 Y10

6.3.2 Simplification Using K-map

6.3.2.1 Steps To Follow

1. Select K-map according to the number of variables.

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 82

2. Identify minterms or maxterms as given in the problem.

3. For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere).

4. For POS put 0’s in blocks of K-map respective to the maxterms(1’s elsewhere).

5. Make rectangular groups containing total count of terms in powers of two (i.e 2, 4, 8, ..., 2n for integers
n > 0) and try to cover as many elements as you can in one group.

6. From the groups made in step 5 find the product terms and sum them up for SOP form.

Quick note:

• A minterm is a Boolean expression resulting in 1 for the output of a single cell, and 0s for all other
cells in a Karnaugh map, or truth table. If a minterm has a single 1 and the remaining cells as 0s,
it would appear to cover a minimum area of 1s.

• Similarly, a maxterm is a Boolean expression resulting in a 0 for the output of a single cell expres-
sion, and 1s for all other cells in the Karnaugh map, or truth table.

6.3.2.2 Grouping Rules

The Karnaugh map uses the following rules for the simplification of expressions by grouping together
adjacent cells containing ones

(a). No zeros allowed.

(b). No diagonals.

(c). The number of cells in each group should be2n for some integer n > 0.

(d). Groups should be as large as possible.

(e). Every 1 must be in at least one group.

(f). Overlapping groups are allowed.

(g). Wrap around is allowed.

(h). Get the fewest number of groups possible.

The Fig. 6.13 below demonstrates the rights and wrongs of grouping in K-maps.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 83

Fig. 6.13: Rights and Wrongs of K-map grouping.

We perform the sum of minterm also known as sum of products (SOP).

• The minterm for each combination of the variables that produce a 1 in the function and then taking
the OR of all those terms.

We perform the product of maxterm also known as product of sum (POS).

• The maxterm for each combination of the variables that produce a 0 in the function and then taking
the AND of all those terms.

6.3.2.3 An Example

Suppose we have to simplify the following Logic expression using Karnaugh mapping,

f (A, B,C, D) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD

whose truth table is shown in Table 6.17 below.

LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 84

Table 6.17: Example of four-variable input logic system’s truth table.

A B C D Output Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

We start by filling the Karnaugh map as shown in Table 6.18 below,

Table 6.18: A four-variable K-map.

AB\CD 00 01 11 10
00 0 0 1 1
01 0 0 1 1
11 0 0 0 1
10 0 1 1 1

The next step is to proceed with the groupings as shown in Fig. 6.14 below,

Fig. 6.14: Grouping on K-map.

The next step is to analyze each group and deduce the logic expression out of it. From our first group
G1, we can see that A is the same and is equal to 1 throughout the box, therefore it should be included in
the resulting algebraic expression of the minterm. B does not maintain the same state, as it shifts from 1
to 0, and should therefore be excluded. C does not change (i.e it is always 0), hence its complement, C,
should be included. D changes, so it is excluded. The resulting term from this group is therefore AC.
LECTURE 6. LOGIC GATES AND BOOLEAN LOGIC 85

Looking at the second group G2, we have A and B again not changing throughout, while C and D are both
changing. Therefore A and B should be in final expression while C and D are excluded. The resulting
expression is therefore AB. Lastly in the third group G3 only A is changing, hence the final expression
must have B, C and D. The resulting expression is therefore BCD. The final expression is given as,
AC + AB + BCD which is a simplification of the original logic expression as shown below.

f (A, B,C, D) = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD = AC + AB + BCD

We can also use Boolean logic laws to arrive at the same simplified logic expression which can be built
using three NOT gates, four AND gates and three OR gates only as shown in Fig. 6.15 below.

Fig. 6.15: Equivalent circuit with logic gates.

There are cases whereby some entry (i.e. output) values in the K-map are not important. That means
they can take the value 1 or 0 without affecting the behavior of the underlying system. Such entries are
called "Don’t Cares" and usually denoted by a symbol "X". They can either be included or excluded in
the grouping process depending on which choice is more convenient. We will come across a few such
cases in the next lectures.
Lecture 7

Latches and Flip-Flops

86
Lecture 8

Counters and Feedback Circuits

87