UNIT III

I/O INTERFACING
Reference : Chapter 9
MicroComputer Systems,Cheng Liu,Glenn Gibson
I/O interface
An I/O interface must be able to:
1. Interpret the address and memory-I/O select
signals to determinate whether or not it is
being referenced and, if so, determine which
of its registers is being accessed.
2. Determine whether an input or output is
being conducted and accept output data or
control information from the bus or place
input data or status information on the bus.
I/O interface
3.Send interrupt requests and, if there is no
interrupt priority management in the bus
control logic, receive interrupt
acknowledgments and send an interrupt
type.
4. Receive a reset signal and reinitialize itself
and perhaps, its associated device.
I/O interface
5.Send interrupt requests and, if there is no
interrupt priority management in the bus
control logic, receive interrupt
acknowledgments and send an interrupt type.
6.Receive a reset signal and reinitialize itself
and perhaps, its associated device.
Figure 9-1 Typical block diagram of
an I/O device
Function of an I/O interface

to translate signals b/w system

bus and I/O Device
provide buffers needed to
satisfy the timing constraints
Parts Of An Interface
 Part that interfaces to the I/O device
 Part that interfaces to the system bus

Components
 external data bus drivers and receivers
 handshaking logic
 address decoder
Address decoder – a sample

Write Read Address bit 0 Register being

addressed
0 1 0 A
0 1 1 B
1 0 0 C
1 0 1 D
External Interface
 Two ways of interfacing I/O devices
 Serial
 Cheaper
 Slower

 Parallel
 Faster
 Data skew
 Limited to small distances
External Interface (cont‟d)
Two basic modes of data transmission
External Interface (cont‟d)
 Serial transmission
 Asynchronous
 Each byte is encoded for transmission
 Start and stop bits
 No need for sender and receiver synchronization
 Synchronous
 Sender and receiver must synchronize
 Done in hardware using phase locked loops (PLLs)
 Block of data can be sent
 More efficient
 Less overhead than asynchronous transmission
 Expensive
 External Interface (cont‟d)
11-12
Types of serial communication

 Asynchronous - special bit patterns

separate the characters
 Synchronous – characters are sent back

to back, must have “sync” characters at

the beginning and idle characters to fill
up when no info is sent
External Interface (cont‟d)
Asynchronous transmission
SERIAL COMMUNICATION INTERFACE
SERIAL COMM I/F
 Transfer data one bit at a time
 Status register – contains error info & state of
current txn
 Control register- holds info –determines operating
mode
 Data in buffer – paired with SIPO shift register
 Status register – read only
 Control register – written into
Basic transmission modes
Asynchronous transmission
1- mark state, 0 – space state

First bit – always 0 – start bit

Control register format
Errors
 Framing error
A 0 is seen instead of a STOP BIT
 Overrun Error
 When contents of data in buffer register are replaced
by new data before they are input by the computer
 Parity error
 overrun error causes certain status bit to be set

UART – UNIVERSAL ASYNCHRONOUS RECEIVERS &

TRANSMITTERS
SYNCHRONOUS COMMUNICATION

 NO start/stop bits
 Each txed character has 5 to 8 bits optionally
followed by parity
 All char have same number of bits – n
 Same clock control
 Under run error – when a character is not available
at the beginning of the interval,txer inserts idle
characters,rxer – sees idle char as errors
 Serial Data Transfer
 Asynchronous v.s. Synchronous
— Asynchronous transfer does not require clock signal. However, it transfers extra
bits (start bits and stop bits) during data communication
— Synchronous transfer does not transfer extra bits. However, it requires clock
signal
Frame

Asynchronousdata
Data transfer Start
B0 B1 B2 B3 B4 B5 B6 Stop bits
bit Parity

clk
Synchronous
Data transfer
data
B0 B1 B2 B3 B4 B5

Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).
Long distance serial communication
8251 – Programmable Communication
Interface
Pins and signals - 8251
8251- block diagram
Sections of 8251A
 Data Bus buffer
 Read/Write Control Logic
 Modem Control
 Transmitter
 Receiver

1. Data Bus Buffer

 D0-D7 : 8-bit data bus used to read or write status,
command word or data from or to the 8251A
2. Read/Write Control logic

 Includes a control logic, six input signals & three

buffer registers: Data register, control register &
status register.

 Control logic : Interfaces the chip with MPU,

determines the functions of the chip according to the
control word in the control register & monitors the
data flow.
 Input signals

 CS – Chip Select : When signal goes low, the 8251A is selected by

the MPU for communication.
 C/D – Control/Data : When signal is high, the control or status
register is addressed; when it is low, data buffer is addressed.
(Control register & status register are differentiated by WR and
RD signals)
 WR : When signal is low, the MPU either writes in the control
register or sends output to the data buffer.
 RD : When signal goes low, the MPU either reads a status from the
status register or accepts data from data buffer.
 RESET : A high on this signal reset 8252A & forces it into the idle
mode.
 CLK : Clock input, usually connected to the system clock for
communication with the microprocessor.
Control Register

 16-bit register for a control word consist of two

independent bytes namely mode word & command
word.
 Mode word : Specifies the general characteristics
of operation such as baud, parity, number of bits
etc.
 Command word : Enables the data transmission and
reception.
 Register can be accessed as an output port when
the Control/Data pin is high.
Status register
 Checks the ready status of the peripheral.

 Status word in the status register provides the information

concerning register status and transmission errors.
Data register
 Used as an input and output port when the C/D is low

CS C/D WR RD Operation
0 0 1 0 MPU reads data from data buffer
0 0 0 1 MPU writes data to data buffer
0 1 0 1 MPU writes a word to control register
0 1 1 0 MPU reads a word from status register
1 × × × Chip is not selected for any operation
3. Modem Control
 DSR - Data Set Ready : Checks if the Data Set is
ready when communicating with a modem.
 DTR - Data Terminal Ready : Indicates that the
device is ready to accept data when the 8251 is
communicating with a modem.
 CTS - Clear to Send : If its low, the 8251A is
enabled to transmit the serial data provided the
enable bit in the command byte is set to „1‟.
 RTS - Request to Send Data : Low signal indicates
the modem that the receiver is ready to receive a
data byte from the modem.
4. Transmitter section
 Accepts parallel data from MPU & converts them into
serial data.
 Has two registers:
 Buffer register : To hold eight bits
 Output register : To convert eight bits into a stream of serial
bits.

Output Register

Transmitter Buffer

Transmit control
Transmitter
 The MPU writes a byte in the buffer register.
 Whenever the output register is empty; the contents of buffer
register are transferred to output register.
 Transmitter section consists of three output & one input signals
 TxD - Transmitted Data Output : Output signal to transmit the data to
peripherals
 TxC - Transmitter Clock Input : Input signal, controls the rate of
transmission.
 TxRDY - Transmitter Ready : Output signal, indicates the buffer register
is empty and the USART is ready to accept the next data byte.
 TxE - Transmitter Empty : Output signal to indicate the output register is
empty and the USART is ready to accept the next data byte.
5. Receiver Section

 Accepts serial data on the RxD pin and converts

them to parallel data.
 Has two registers :
 Receiver input register
 Buffer register

Input Register
RxD

Receive Buffer

RxRDY
Receive control
RxC
 When RxD goes low, the control logic assumes it
is a start bit, waits for half bit time, and samples
the line again. If the line is still low, the input
register accepts the following data, and loads it
into buffer register at the rate determined by
the receiver clock.
Receiver
 RxRDY - Receiver Ready Output: Output signal,
goes high when the USART has a character in the
buffer register & is ready to transfer it to the MPU.
 RxD - Receive Data Input : Bits are received serially
on this line & converted into a parallel byte in the
receiver input register.
 RxC - Receiver Clock Input : Clock signal that
controls the rate at which bits are received by the
USART.
Sequencing
Mode register format
Control register format
Mode Instruction (Asynchronous)
Mode Instruction (Synchronous)
Command Register
Status Register
Asynchronous modem connection
Synchronous modem connection
Simple Serial I/O Procedures

 Read  Write
start start

Check RxRDY Check TxRDY

No No
Is it logic 1? Is it logic 1?
Yes Yes
Read data register* Write data register*

end end
* This clears RxRDY * This clears TxRDY
Example problem
 Write A program sequence which uses programmed
I/O to input 80 characters from the 8251A, whose
data buffer register's address is 0050, and put
them in the memory buffer beginning at LINE.
Example - solution
Parallel communication
 Simultaneous transfer of bits over separate lines
 Adv: high information rate
 Disadv:cost of lines
Parallel o/p i/f without control lines
Parallel o/p i/f without control lines
 Contents of data buffer Are continually maintained
on data lines connecting the i/f and I/O

 If O/P device has a latch and set of relays and set

of relays controlled by latch, then a comp will
control the relays by simply outputting data to data
buffer register
Parallel i/f with handshaking control
lines & separate I/O connections
 PROGRAMMABLE PERIPHERAL
INTERFACE (PPI)-8255

Features:
 It is a programmable device.

 It has 24 I/O programmable pins PA,PB,PC (3-8 pins).

 T T L compatible.

 Improved dc driving capability

Pin Diagram
Function of pins:
 Data bus(D0-D7):These are 8-bit bi-directional buses,
connected to cpu data bus for transferring data.

 CS: This is Active Low signal. When it is low, then data

is transfer from 8086.

 Read: This is Active Low signal, when it is Low read

operation will be start.

 Write: This is Active Low signal, when it is Low Write

operation will be start.
 Address (A0-A1):This is used to select the ports.

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC

Control
1 1
reg.
PINS AND SIGNALS
 RESET: to reset the device. clear control registers.

 PA0-PA7:8-bit bi-directional I/O pins used to send the

data to peripheral or to receive data from peripheral.

 PB0-PB7:Similar to PA

 PC0-PC7: 8-bit bidirectional I/O pins. These lines are

divided into two groups.
1. PC0 to PC3(Lower Group)
2. PC4 to PC7 (Higher group)
Block Diagram
Data Bus buffer:
 8-bit bidirectional Data bus.

 Used to interface 8255 data bus with system bus.

 The internal data bus and pins D0-D7 pins are

connected

 The direction of data buffer is decided by

Read/Control Logic.
Read/Write Control Logic:
 Gets input signals from control bus and Address
bus

 Control signals are RD and WR.

 Address signals are A0,A1,and CS.

 8255 operation is enabled or disabled by CS.

Group A and Group B control:
 Group A and B get the Control Signal from CPU
and send the command to the individual control
blocks.

• Group A sends the control signal to port A and

Port C (Upper) PC7-PC4.

• Group B send the control signal to port B and

Port C (Lower) PC3-PC0.
PORT A
• 8-bit buffered I/O latch.
• It can be programmed in mode 0 , mode 1, mode 2 .
PORT B
 8-bit buffer I/O latch.
 Used in mode 0 and mode 1.
PORT C
 8-bit Unlatched buffer Input and an Output latch.
 split into two parts.
 It can be programmed by bit set/reset operation.
Modes of operation
BIT SET/RESET MODE:BSR
 PORT C can be Set or Reset by sending OUT instruction
to the CONTROL registers.
I/O MODES:
 MODE 0(Simple input / Output):
 All ports- A, B and C
 Features:
 Outputs are latched , Inputs are buffered not latched.
 Ports do not have Handshake or interrupt capability.
MODE 1 :(Input/output with Hand
shake)
 In this mode, input or output is transferred by hand
shaking Signals.
Computer DATA BUS Printer
STB
ACK

Busy

 Handshaking signals - used to transfer data between

devices operating at different data rates
MODE 2:bi-directional I/O data
transfer:
 This mode allows bidirectional data transfer over a
single 8-bit data bus using handshake signals.
 only Group A
 Port A 8-bit bidirectional.
 PC3-PC7 is used for handshaking purpose.
 The data is sent by CPU through this port , when the
peripheral request it.
 CONTROL WORD FORMATS:
 In the INPUT mode , When RESET is High all 24 pins (3-
ports) are in input mode.
control word format – BSR MODE
D7 D6 D5 D4 D3 D2 D1 D0

BIT
X X X SET/RESET
1=SET
Don‟t care 0=RESET

Bit select
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1B0 1
0 0 0 0 1 1 1B1 1
B2
BIT SET/RESET FLAG
=0 Active
CONTROL WORD
 PC0-PC7 is set or reset as per the status of D0.
 A BSR word is written for each bit
 Example:
 PC3 is Set then control register will be 0XXX0111.
 PC4 is Reset then control register will be
0XXX01000.
 X is a don‟t care.
I/O MODE - CWR
D7 D6 D5 D4 D3 D2 D1 D0

Group B
Group A
Port C Upper
Mode set Port C Lower
1=Input
flag=1=Active 1=Input
0=Output
0=Output
Port B
Port B
1=Input
1=Input
0=Output
0=Output
Mode selection
Mode selection
00=mode 0
0=mode 0
01=mode 1
1=mode 1
1x=mode 2
CWR
 Bit D7 is used for specifying OPERATION MODE (Bit
set/reset mode or I/O Mode .
 D7=1=I/O mode.
 D7=0=Bit set/Reset mode.
8255 MD Control word Contd.
72

Ex. 1: Configure Port A as i/p in Mode 0, Port B as o/p in

mode 0, Port C (Lower) as o/p and Port C (Upper) as i/p
ports.
Required MD control word:
1 0 0 1 1 0 0 0 = 98H
MD control PC Lower as o/p
PA in Mode 0 PB as o/p Reqd. instrns.
PA as i/p PB in Mode 0 MOV AL, 98H
PC Upper as i/p OUT 7FH, AL
8255 MD Control word Contd.
73

Ex. 2: Configure Port A as i/p in Mode 1, Port B as o/p in

mode 1, Port C7-8 as i/p ports. (PC5-0 are handshake lines,
some i/p lines and others o/p. So they are shown as X)
Required MD control word:
1 0 1 1 1 1 0 X = BCH or BDH
MD control PC3-0 as don‘t care
PA in Mode 1 PB as o/p Reqd. Instrns.
PA as i/p PB in Mode 1 MOV AL,BCH
PC Upper(C7-8) as i/p OUT 7FH, AL
 8255 MD Control word Contd.
74

Ex. 3:Configure Port A in Mode 2, Port B as o/p in mode 1.

(PC5-0 are handshake lines for Port A and PC2-0 are
handshake signals for port B)
Required MD control word:
1 1 0 X X 1 0 X = C4H / C5H..
MD control PC3-0 as handshake
PA in Mode 2 PB as o/p Reqd. instrns.
PA bidirectional PB in Mode 1 MOV AL, C4H
PC7-0 as handshake OUT 7FH, AL
8255: Mode 1 Strobed Input
 ~STB : The strobe input loads data into the port latch on a 0-
to-1 transition.
 IBF : Input buffer full is an output indicating that the input latch
contain information.
 INTR : Interrupt request is an output that requests an interrupts.
 INTE : The interrupt enable signal is neither an input nor an
output; it is an internal bit programmed via the PC4 (port A) or
PC2 (port B) bits.
 PC7,PC6 : The port C pins 7 and 6 are general purpose I/O
pins that are available for any purpose.
8255: Mode 1 Strobed Input

Signal definitions for Mode 1 Strobe Input

8255 : Mode 1 Output
 ~OBF : Output buffer full is an output that goes low when
data is latched in either port A or port B. Goes low on ~ACK.
 ~ACK : The acknowledge signal causes the ~OBF pin return to
0. This is a response from an external device.
 INTR : Interrupt request is an output that requests an interrupt.
 INTE : The interrupt enable signal is neither an input nor an
output; it is an internal bit programmed via the PC6(Port A) or
PC2(port B) bits.
 PC5,PC4 : The port C pins 5 and 4 are general-purpose I/O
pins that are available for any purpose.
8255 : Mode 1 Output
8255: Mode 2 Bi-directional Operation

 This functional configuration provides a means for

communicating with a peripheral device or structure
on a single 8-bit bus for both transmitting and
receiving data (bidirectional bus I/O).
 “Handshaking” signals are provided to maintain
proper bus flow discipline in a similar manner to
MODE 1.
 Interrupt generation and enable/disable functions
are also available.
MODE 2 Basic Functional Definitions:

 Used in Group A only.

 One 8-bit, bi-directional bus port (Port A) and a 5-bit
control port (Port C).
 Both inputs and outputs are latched.
 The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A).
: Mode 2 Bi-directional Operation

 INTR : Interrupt request is an output that requests an

interrupt.
 ~OBF : Output Buffer Full is an output indicating that
that output buffer contains data for the bi-directional
bus.
 ~ACK : Acknowledge is an input that enables tri-state
buffers which are otherwise in their high-impedance
state.
 ~STB : The strobe input loads data into the port A
latch.
8255: Mode 2 Bi-directional Operation

 IBF : Input buffer full is an output indicating that the

input latch contains information for the external bi-
directional bus.
 INTE : Interrupt enable are internal bits that enable
the INTR pin. BIT PC6(INTE1) and PC4(INTE2).
 PC2,PC1,PC0 : These port C pins are general-
purpose I/O pins that are available for any purpose.
8255: Mode 2 Bi-directional Operation
Mode definition summary
A/D & D/A Interface
 8255A could be connected to an A/D and D/A
subsystem
 Since during an A/D conversion the analog voltage
must remain unchanged, a sample-and-hold circuit is
needed to keep the analog signal constant while the
conversion is being performed.
 Group A is configured as an input in mode 1. A
conversion is initiated by a signal from the 8255A's
PC7 pin.
A/D & D/A Interface
PROGRAMMING SEQUENCE – Step 1

 Given that port A, port B, port C and the control

register have addresses FFF8, FFF9, FFFA and FFFB,
respectively, the sequence:

 MOV DX,0FFFBH
 MOV AL,10110000B
 OUT DX,AL

 would cause port A to be put in mode 1, port B to be

put in mode 0, and PC7 to be an output.
STEP 2
The sequence:
 MOV DX,0FFFBH
 MOV AL,00001111B
 OUT DX,AL
 MOV AL,00001110B
 OUT DX,AL
 would output a pulse to the convert pin of the A/D converter.
 The first instruction of the sequence puts the address associated
with Set/Reset instruction, which is the same as the address of
the control register, in the DX register.
 The next two instructions cause PC7 to be set and the last two
cause it to be cleared.
Step 3

 A sequence for providing a programmed I/O input of

the converted data is:

 MOV DX,0FFFAH
 AGAIN: IN AL,DX
 TEST AL,00100000B
 JZ AGAIN
 MOV DX,0FFF8H
 IN AL,DX
Step 4
 For outputting a byte from AL to the D/A converter,
the instructions are

 MOV DX,0FFF9H
 OUT DX,AL

 As soon as the byte arrives at port B its bits are

immediately applied to the input pins of the D/A
converter, which, in turn, immediately converts it to an
analog signal.
Step 5
 The sample time could be adjusted by including a "do
nothing" loop, between the inputs or outputs.

 MOV CX,N
 IDLE: NOP
 LOOP IDLE
A flowchart for inputting a block of A/D samples
using programmed timing
UNIT 3
PROGRAMMABLE TIMERS AND EVENT COUNTERS
Functions
1. Interrupt a time-sharing operating system at evenly spaced
intervals so that it can switch programs.
2. Output precisely timed signals with programmed periods
to an I/O device (e.g. an A/D converter).
3. Serve as a programmable baud rate generator.
4. Measure time delays between external events.
5. Count the number of times an event occurs in an external
experiment and provide a means of inputting the count to
the computer.
6. Cause the processor to be interrupted after a programmed
number of external events have occurred.
A typical timer/event counter
PROGRAMMABLE INTERVAL
TIMER - 8254
Features
 Three Independent 16-Bit Counters,
 Clock input upto 10 MHz,
 Status Read-Back Command,
 Six Programmable Counter Modes,
 Binary or BCD Counting,
 Single +5V Supply,
 Superset of PIT-8253.
Pin Diagram
Pin Description
Block Diagram of 8254
Internal Blocks of Counter
 Count Register (CR) to store count (CRL & CRM),
 Counting elements (CE) are used for counting,
 Output Latch (OLL & OLM) to latch the count in
CE,
 The Control Word Register is not part of the
Counter itself, but its contents determine how the
Counter operates.
 The status register, when latched, contains the
current contents of the Control Word Register and
status of the output and null count flag.
Internal Block Diagram
System Interface
Control Word format

8254 Programming
 Each counter is individually programmed by writing a control word,
followed by the initial count.
 The control word allows the programmer to select the counter, mode
of operation, binary or BCD count and type of operation
(read/write).
WRITE Operation

 Control Word to Control register

 Initial count must follow the count format specified
in the Control Word (least significant byte only,
most significant byte only, or least significant byte
and then most significant byte).
READ Operation

Three Possible Methods to read counters

 Simple Read Operation,

 Counter Latch Command,

 Read Back Command.

Note: Two I/O read operations have to be performed to

get first Lower Byte and then higher byte of count.
Simple Read Operation:
After inhibiting counter using GATE or CLK input we
can read count

Counter Latch Command:

D5 D4 = 0 0 Designates the counter latch command

SC1 SC2 = Specify counter to be latched.
X – Don’t care bits must be 0 to ensure compatibility with future
Intel products.
Read Back Command:
Status Byte
Read-back command example
Interleaved Read and Write
Operations:
Valid sequence for read and write of the same
counter set for two byte count:

1. Read least significant byte,

2. Write new least significant byte,
3. Read most significant byte,
4. Write new most significant byte.
Modes of 8254

Six Different Modes

 Mode 0: Interrupt On Terminal Count

 Mode 1: Hardware Retriggerable One-shot

 Mode 2: Rate Generator

 Mode 3: Square Wave Mode

 Mode 4: Software Triggered Strobe

 Mode 5: Hardware Triggered Strobe

(Retriggerable)
Shape of the 8253/54 Output
 Given CLK = 1.193 MHz, the clock period of input
frequency is 838 ns
 If the number N loaded into the counter is even, both
high and low pulse are the same length, which is
N/2 * 838 ns
 If the number N loaded into the counter is odd, the
high pulse is (N+1)/2 * 838 ns and the low pulse is
(N–1)/2 * 838 ns
  If N is odd, the high portion of the output square
wave is slightly wider than the low portion
8253/54 Operation Modes

 Mode 0: Interrupt on terminal count

 The output is initially low, and remain low for the
duration of the count if GATE=1. When the terminal
count is reached, the output will go high and remain
high until a new control word or new count number is
loaded
 Width of low pulse = N * T, where T is clock period
 Example: GATE=1 and CLK = 1 MHz
Clock count N = 1000
8253/54 Operation Modes
 Mode 0: Interrupt on terminal count
 If GATE becomes low at the middle of the count,
the count will stop and the output will be low. The
count resumes when the GATE becomes high again
 This in effect adds to the total time the output is
low.
Mode 1
 Mode 1: HW triggered / programmable one shot
 The triggering must be done through the GATE input by
sending a 0-to-1 pulse to it.
 Steps: 1) Load the count register
2) A 0-to-1 pulse must be sent to the GATE
input to trigger the count
8253/54 Operation Modes

 Mode 1: HW triggered / programmable one shot

 In Mode 1, after sending the 0-to-1 pulse to GATE,
OUT becomes low and stays low for a duration of
N*T, then becomes high and stays high until the GATE
is triggered again
 If during the activation, a retriggered happened, then
restart the down counting
Mode 2

 Mode 2: Rate Generator (Divide-by-N counter)

 In Mode2, if GATE=1, OUT will be high for N*T,
goes low only for one clock pulse, then counter is
reloaded automatically, and the process continues
indefinitely.  Whole period: (N+1) * T
8253/54 Operation Modes
 Mode 3: Square wave rate generator
 Most commonly used
 Mode 4: Software triggered strobe
 Similar to Mode2, except that the counter is not
reloaded automatically
 In Mode4, if GATE=1, the output will go high when
loading the count, it will stay high for duration N*T.
After the count reaches zero, it becomes low for one
clock pulse, then goes high again and stays high until
a new command word or new count is loaded
 To repeat the strobe, the count must be reloaded
8253/54 Operation Modes

 Mode 5: Hardware triggered strobe

 Similarto Mode4, except that the triggering must be
done with the GATE input
 The count starts only when a 0-to-1 pulse is sent to
the GATE input
 If GATE retriggered during the counting, it will restart
the down counting
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
8253 / 8254 Timer
Minimum & Maximum Initial Count
Gate Pin Operations Summery
Applications of 8254
 Real time clock
 Event-counter
 Digital one-shot
 Programmable rate generator
 Square wave generator
 Binary rate multiplier
 Complex waveform generator
 Complex motor controller
Interval Timer Application to A/D
Interval Timer Application to A/D
Objective:
Use a timer to provide sample rate generator to
A/D
Solution:
COUNTER 0 – MODE 2 , initial count - L
COUNTER 1- MODE 1, initial count - M
COUNTER – MODE 3, initial count - N
Interval Timer Application to A/D

 F – clock frequency
 Frequency applied to clock 1 = F/N
 Output – OUT1-Pulse period-MN/F
 Output – OUT0-Pulse period-MN/F-Freq-F/L
 Apply OUT0 to convert i/p of ADC, F/L samples
/sec will be taken for MN/F sec after 3 counters
are initialized and relay is closed
Interval Timer Application to A/D
 Each sample is txed to port A,INTRA is invoked, an
interrupt routine is used to input the sample
 Addresses used
 0070 to 0073
 Initial count L,N – binary
 Initial count M- BCD
Initialization of counters for A/D
example
KEYBOARD AND DISPLAY
 For low-cost small systems, especially single-board
microcomputers and microprocessor-based
instruments, the front panel (or console) is often
implemented by using simple keyboard and display
units as input and output devices.
Keyboard Design
 Unlike a terminal, mechanical contact keyboard, for
which the key switches are organized in a matrix
form, does not include any electronics.
KEYBOARD DESIGN
 a 64-key keyboard can be interfaced to a
microcomputer through two parallel I/O ports such
as those provided by an 8255A.
Organization of a mechanical
keyboard
Keyboard Interface
 INTERFACING KEYBOARD
5V
0 1 2 3
PA0 ROW 0 10K
4
ROW 1 5 6 7
PA1 10K
8 9 A B
PA2 ROW 2 10K
C D E F
PA3
ROW 3 10K

8255 5V
PB0 COL 0 10K 5V
PB1 COL 1 10K
5V
PB2 COL 2 10K 5V

PB3
COL 3 10K
MODE 0 Application (Keyboard
Interface)
 In most applications, the microcomputer scans the
keyboard array. That is, it strobes one row of the
keyboard after the other by sending out a short-
duration pulse, to the 0 logic level, on the row line.
During each row strobe, all column lines are
examined by reading them in parallel.

 Typically, the column lines are pulled up to the 1

logic level; therefore, if a switch is closed, a logic
0 will be read on the corresponding column line. If
no switches are closed, all 1s will be read when
the lines are examined.
Design steps

8086 HAS TO

1. DETECT A KEY PRESS

2. DEBOUNCE A KEY PRESS
3. GENERATE A CODE CORRESPONDING
TO THE KEY BEING PRESSED
ALGORITHM

1. WAIT till all keys are released. Use s.w debounce for each
key check
2. Wait for key closure
3. Confirm key closure
4. Find number of row and column to which key belongs
5. Convert the row and col information to entry number of the
table which contains ASCII code
6. Get code and repeat in infinite loop
 Flow chart

START

NO ANYKEY
ENABLE ALL ROWS
PRESSED
YES
READ ALL COL.S
ENABLE A ROW

ALL NO
READ ALL COL.S
KEYS
OPEN
YES
NO
KEY
DELAY FOR DEBOUN INC ROW NUMBER
DETECTED
YES
READ ALL COL.S
CALC. KEY CODE
NO ALL
KEYS STOP
OPEN YES

READ ALL COL.S

NO ANYKEY
PRESSED
YES

DELAY FOR DEBOUN

READ ALL COL.S

 PROGRAM
DATA SEGMENT
CNTRPRT EQU 8003H
PORTA EQU 8000H
PORTB EQU 8001H
DELAY EQU 6666
TABLE DB 30H,31H,32H,…..39H,41H,….46H ;ASCII CODES FROM 0 TO F
DATA ENDS
CODE SEGMENT
ASUUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AL,82H
MOV DX,CNTRPRT :PORT A AS I/P PORT PORT B AS O/P PORT
OUT DX,AL
XOR AL,AL
MOV DX,PORTA
OUT DX,AL ;ENABLE ALL ROWS
MOV DX,PORTB
RDCOL: IN AL,DX ;GTE COL STATUS
AND AL,0FH ;MASK UNWANTED BITS
CMP AL,0FH ;GET READY FOR CHKING COL SATTUS
JNE RDCOL ;IS ANY COL ACTIVE?IF YES CHK AGAIN
MOV CX,DELAY ;NO DEBOUNCE DEALY
SELF: LOOP SELF
IN AL,DX
AND AL,0FH ;CONFIRM COL STATUS AGAIN
CMP AL,0FH
JNE RDCOL ;IF NOT CONFIRMED CHECK AGAIN
RDAGN: IN AL,DX ;CONFIRMED THAT ALL KEYS ARE OPEN,GET COL STATUS AGAIN
AND AL,0FH
CMP AL,0FH ;CHECK FOR ANY KEY CLOSURE,IF NO CONTINUE TO CHECK,IF YES
JE RDAGN ;NEXT STEP
MOV CX,DELAY
SELF1: LOOP SELF1
 IN AL,DX
AND AL,0FH ;CONFIRM COL STATUS AGAIN
JE RDAGN
MOV AL,0FEH ;KEY CLOSURE CONFIRMES,SELECT ROW PATTTERN TO ENABLE A ROW
MOV BL,AL ;SAVE IT
ENROW: MOV DX,PORTA
OUT DX,AL ;ENABLE CORRESPONDING ROW
MOV DX,PORTB
IN AL,DX ;GET COL STATUS
AND AL,0FH
CMP AL,0FH ;CHECK IF COL IS ACTIVE
JNE CCODE ;IF YES, GO TO CALCULATE ASCII CODE OF KEY PRESSED
ROL BL,1 ;PREPARE TO ENABLE NEXT ROW
MOV AL,BL
JMP ENROW
CCODE: MOV CL,0 ;AL CONTAINS COL PATTERN,BL CONTAINS ROW PATTERN
;INITIALIZE COL COUNT TO 0
NXTCOL: ROR AL,1 ;COL STATUS GOES TO CARRY FLAG
JNC CHKROW ;IS COL ACTIVE, IF YES, CL CONTAINS COL.NUMBER
INC CL ;NO INCREMENT COL COUNT
JMP NXTCOL ;CHECK NEXT COL
CHKROW: MOV DL,0 ;CL CONTAINS COL NUMBER
;INITIALIZE ROW COUNT TO ZERO
NXTROW: ROR BL,1 ;ROW STATUS GOES TO CARRY FLAG
JNC CALADR ;IS ROW ACTIVE? IF YES, DL CONTAINS ROW NUMBER
ADD DL,04H ;ROW COUNT+4 ROW COUNT
JMP NXTROW CHECK NEXT ROW
CALADR: ADD DL,CL ;ROW +COL
MOV AL,DL
LEA BX,TABLE
XLAT ;GET ASCII CODE OF THE KEY PRESSED
INT3H
JMP START
CODE ENDS
END SATRT
Display Design
DISPLAY
DISPLAY UNIT
 WHY 8279???
WHAT WE KNOW,
8255 can be used in interfacing keyboards and displays.
The disadvantage of this method of interfacing keyboard
and display is that the processor has to refresh the display
and check the status of the keyboard periodically using
polling technique.
 Thus a considerable amount of CPU time is wasted,
reducing the system operating speed.
 Intel‘s 8279 is a general purpose keyboard display
controller that simultaneously drives the display of a
system and interfaces a keyboard with the CPU, leaving it
free for its routine task.
INTERNAL ARCHITECTURE
 • Connected to a 64 contact key matrix
• Keyboard entries and debounced and
stored in FIFO
Keyboard • Interrupt signal is generated with each
segment entry

• 16character scanned display

• 16x8 R/W memory ( RAM )
Display • Right entry or left entry
segment
 • The I/O control section controls the flow of data to/from
I/O the 8279
Control • The I/O section is enabled only if CS is low.
and • The pins A0, RD and WR select the command, status or
Data data read/write operations carried out by the CPU with
Buffers 8279.
: • The data buffers interface the external bus of the system
with internal bus of 8279.

Control
• These registers store the keyboard and display modes
and and other operating conditions programmed by CPU.
Timing • The registers are written with A0=1 and WR=0. The
Register Timing and control unit controls the basic timings for the
and operation of the circuit.
Timing • Scan counter divide down the operating frequency of
8279 to derive scan keyboard and scan display
Control frequencies.
:
 • The scan counter has two modes to scan the
key matrix and refresh the display.
• In the encoded mode, the counter provides
binary count that is to be externally decoded
to provide the scan lines for keyboard and
display
Scan • Four externally decoded scan lines may drive
upto 16 displays.
Counter • In the decode scan mode, the counter
: internally decodes the least significant 2 bits
and provides a decoded 1 out of 4 scan on
SL0-SL3
• Four internally decoded scan lines may drive
upto 4 displays.
• The keyboard and display both are in the
same mode at a time.
 Return
Buffers • This section scans for a key closure row wise. If a
and key closer is detected, the keyboard debounce unit
debounces the key entry (i.e. wait for 10 ms).
Keyboard
• After the debounce period, if the key continues to
De- be detected, The code of key is directly
bounce transferred to the sensor RAM along with SHIFT
and and CONTROL key status.
Control:

Display
Address • The display address register holds the address
Register of the word currently being written or read by
the CPU to or from the display RAM.
s and • The contents of the registers are automatically
Display updated by 8279 to accept the next data entry
RAM : by CPU.
 • In keyboard or strobed input mode, this block
acts as 8-byte first-in-firstout (FIFO) RAM.
• Each key code of the pressed key is entered
in the order of the entry and in the mean time
read by the CPU, till the RAM become empty.
• The status logic generates an interrupt after
FIFO/Sensor each FIFO read operation till the FIFO is
RAM and empty.
Status Logic: • In scanned sensor matrix mode, this unit acts
as sensor RAM.
• Each row of the sensor RAM is loaded with the
status of the corresponding row of sensors in
the matrix.
• If a sensor changes its state, the IRQ line goes
high to interrupt the CPU.
FUNCTIONAL UNITS
• Scanned
keyboard mode
• Scanned sensor • Display scan
matrix mode • Display entry
• Strobed input •
Operating
mode
modes of 8279
OUTPUT
INPUT ( (display )
keyboard) MODES
MODES
 Scanned Keyboard 2 key
Mode : lock
This mode allows a key out
matrix to be interfaced
using either encoded or
decoded scans.
encoded scan 8*8
keyboard,
decoded scan  4*8
N – key
keyboard. roll
The code of key pressed over
with SHIFT and
CONTROL is stored in
FIFO RAM.
 2 key
lock out
When a key is pressed, a debounce logic comes into operation. During the
next two scans, other keys are checked for closure and if no other key is
pressed the first pressed key is identified.

The key code is entered with SHIFT and CNTL status, provided the FIFO is
not full, i.e. it has at least one byte free. If not free, data will not be entered
and the error flag is set.

If FIFO has at least one byte free, the above code is entered into it and the
8279 generates an interrupt on IRQ line to the CPU to inform about the
previous key closures.

A key code is entered to FIFO only once for each valid depression,
independent of other keys pressed along with it, or released before it.

If two keys are pressed within a debounce cycle (simultaneously ), no key

is recognized till one of them remains closed and the other is released. The
last key, that remains depressed is considered as single valid key
depression.
N2–key
key
roll
lockover
out
Scanned Keyboard with N-Key Rollover : In
this mode, each key depression is treated
independently.

When a key is pressed, the debounce circuit

waits for 2 keyboards scans and then checks
whether the key is still depressed. If it is still
depressed, the code is entered in FIFO RAM.

Any number of keys can be pressed

simultaneously and recognized in the order,
the keyboard scan recorded them. All the
codes of such keys are entered into FIFO.

In this mode, the first pressed key need not be

released before the second is pressed.

All the keys are sensed in the order of their

depression, rather in the order the keyboard
scan senses them, and independent of the
order of their release.
Scanned Keyboard Special Error Mode :
This mode is valid only under the N-Key rollover
mode.
This mode is programmed using end interrupt / error
mode set command.
If during a single debounce period ( two keyboard
scans ) two keys are found pressed , this is considered
a simultaneous depression and an error flag is set.
This flag, if set, prevents further writing in FIFO
but
allows the generation of further interrupts to the CPU
for FIFO read.
The error flag can be read by reading
the FIFO status word. The error Flag is reset by
sending
Scanned Sensor Matrix :
 In this mode, a sensor array can be interfaced with 8279
using either encoded or decoded scans. With encoded scan 8*8
sensor matrix or with decoded scan 4*8 sensor matrix can be
interfaced.
 The sensor codes are stored in the CPU addressable sensor
RAM.
 In the sensor matrix mode, the debounce logic is inhibited.
The 8-byte FIFO RAM now acts as 8 * 8 bit memory matrix.
The status of the sensor switch matrix is fed directly to sensor
RAM matrix. Thus the sensor RAM bits contains the rowwise
and column wise status of the sensors in the sensor matrix.
 The IRQ line goes high, if any change in sensor value is
detected at the end of a sensor matrix scan or the sensor RAM
has a previous entry to be read by the CPU.
 The IRQ line is reset by the first data read operation, if AI =
0, otherwise, by issuing the end interrupt command. AI is a bit in
read sensor RAM word.
Strobed input:
 In this mode, if the control lines goes low, the data on return lines, is stored
in the FIFO byte by byte.

Output (Display) Modes : 8279

provides two output modes for
selecting the display options.

Display Entry Display Scan :

( right entry or left • In this mode 8279
entry mode ) provides 8 or 16
• 8279 allows options character
for data entry on the multiplexed displays
displays. those can be
• The display data is organized as dual 4-
entered for display bit or single 8-bit
either from the right
side or from the left display units.
side.
 Left Entry Mode Right Entry Mode
( TYPE WRITER) ( CALCULATOR)
• In the left entry mode, the data is • In this right entry mode, the first
entered from left side of the entry to be displayed is entered
display unit. on the rightmost display.
• Address 0 of the display RAM • The next entry is also placed in
contains the leftmost display the right most display but after
characters and address 15 of the the previous display is shifted
RAM contains the right most left by one display position.
display characters. • The leftmost characters is shifted
• It is just like writing in our note out of that display at the
books ie left to right. seventeenth entry and is lost,
• In autoincrement mode, address i.e. it is pushed out of the display
is automatically updated with RAM.sss
successive readsor writes.
• The first entry is displayed on the
leftmost display and the sixteenth
entry on the rightmost display.
• The seventeenth entry is again
displayed at the leftmost display
position.
 All the command words or status words are written or
read with A0 = 1 and CS = 0 to or from 8279.

a) Keyboard Display Mode Set : The format of the command word to select
different modes of operation of 8279 is given below with its bit definitions.

D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
SENSOR MATRIX

SENSOR MATRIX
B) Programmable clock :

The clock for operation of 8279 is obtained by

dividing the external clock input signal by a
programmable constant called prescaler.
 PPPPP is a 5-bit binary constant.
The input frequency is divided by a decimal
constant ranging from 2 to 31, decided by the bits of
an internal prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 P P P P P
c) Read FIFO / Sensor RAM : The format of this command is
given below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A

AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care

This word is written to set up 8279 for reading FIFO/ sensor

RAM.
In scanned keyboard mode, AI and AAA bits are of no use.
The 8279 will automatically drive data bus for each
subsequent read, in the same sequence, in which the data
was entered.
In sensor matrix mode, the bits AAA select one of the 8
rows of RAM.
If AI flag is set, each successive read will be from the
d) Read Display RAM :
This command enables a programmer to read the display RAM
data.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A

The CPU writes this command word to 8279 to prepare

it for display RAM read operation.
AI is auto increment flag and AAAA, the 4-bit address
points to the 16-byte display RAM that is to be read.
If AI=1, the address will be automatically, incremented
after each read or write to the Display RAM.
The same address counter is used for reading and
writing.
d) Write Display RAM :
This command enables a programmer to write the display RAM
data.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A

AI – Auto increment Flag.

AAAA – 4 bit address for 16-bit display RAM to be
written.
e) Display Write Inhibit/Blanking :
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 X IW IW BL BL

IW - inhibit write flag

BL - blank display bit flags
 The IW ( inhibit write flag ) bits are used to mask the
individual nibble.
The output lines are divided into two nibbles ( OUTA0 –
OUTA3 ) and (OUTB0 – OUTB3 ), those can be masked by
setting the corresponding IW bit to 1.
 Once a nibble is masked by setting the corresponding IW
bit to 1, the entry to display RAM does not affect the
nibble even though it may change the unmasked nibble.
The blank display bit flags (BL) are used for blanking A
and B nibbles.
D0, D2 corresponds to OUTB0 – OUTB3
D1, D3 corresponds to OUTA0 - OUTA3 for blanking and
masking.
 If the user wants to clear the display, blank (BL) bits are
available for each nibble as shown in format.
Both BL bits will have to be cleared for blanking both the
nibbles.
g) Clear Display RAM :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA

CD2 CD1 CD0

0X - All zeros ( x don’t care ) AB=00

ENABLES CLEAR DISPLAY 10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
WHEN CD2=1 11 - All ones (AB =FF), i.e. clear RAM
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly
same as above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is
cleared and IRQ line is pulled down and the sensor RAM
pointer is set to row 0.
•If CA=1, this combines the effect of CD and CF bits.
h) End Interrupt / Error mode Set :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1

E- Error mode
X- don’t care

For the sensor matrix mode, this command lowers

the IRQ line and enables further writing into the RAM.
Otherwise, if a change in sensor value is detected,
IRQ goes high that inhibits writing in the sensor RAM.
 For N-Key roll over mode, if the E bit is
programmed to be ‗1‘, the 8279 operates in special
Error mode
 I/O Interface
FIFO status register

•Code given in text for reading keyboard.

•Data returned from 8279 contains raw data that need to be translated to
ASCII:
Use of an 8279 to interface a keyboard
and a multiple-digit display
DEMO
 8279's addresses are FFE8 and FFE9, and the
interrupt request pin IRQ is not used.
First, the device must be initialized by sending a
mode set command to the control register.
Step 1

 Mov DX,0FFE9  set the

keyboard/display
 MOV AL,0 controller to its
encoded keyboard
 OUT DX,AL
scan mode, with
two-key lockout, and
its left entry eight 8-
bit displays mode
Step 2
 characters generated by the depressed keys
can be read through the FIFO
 A program segment is written that uses

programmed I/O to input eight keywords and

store them in an 8-byte array KEYS with the
first byte at the highest address
CODE STEP 2
STEP 3
 To display characters, the CPU must first give a
write display memory command and then
output to the display memory.
 The following instruction sequence displays

eight seven-segment digits which are stored

beginning at DIGITS with the least significant
digit being stored at the low address:
CODE STEP 3
PROGRAMMABLE INTERRUPT
CONTROLLER - 8259
 Why 8259?
196

 8086 has only two interrupt inputs, NMI and INTR.

 If we save NMI for a power failure interrupt, this
leaves only one interrupt for all the other
applications.
 For applications where we have interrupts from
multiple Sources,we use an external device called a
priority interrupt controller ( PIC ) to interrupt signals
into a single interrupt input on the processor.
 8259 – block diagram
197
 Functional Description
198

 Interrupt Request Register (IRR): The

interrupts at IRQ input lines are handled by
Interrupt Request internally. IRR stores all the
interrupt request in it in order to serve them
one by one on the priority basis.
 • In-Service Register (ISR): This stores all the
interrupt requests those are being served, i.e.
ISR keeps a track of the requests being served.
 Priority Resolver
199

 This unit determines the priorities of the interrupt

requests appearing simultaneously.
 The highest priority is selected and stored into the
 corresponding bit of ISR during INTA pulse.
 The IR0 has the highest priority while the IR7 has
the lowest one, normally in fixed priority mode.
 The priorities however may be altered by
programming the 8259A in rotating priority mode.
 IMR and Interrupt Control Logic
200

Interrupt Mask Register (IMR) : This register stores

the bits required to mask the interrupt inputs. IMR
operates on IRR at the direction of the Priority
Resolver
 Interrupt Control Logic: manages the interrupt
and interrupt acknowledge signals to be sent to the
CPU for serving one of the eight interrupt requests.
 This also accepts the interrupt acknowledge (INTA)
signal from CPU that causes the 8259A to release
vector address on to the data bus.
 Data bus buffer
201

 tristate bidirectional buffer interfaces internal

8259A bus to the microprocessor system data bus.
 Control words, status and vector information pass
through data buffer during read or write
operations
 Read/Write Control Logic: accepts and decodes
commands from the CPU.
 Allows the status of the 8259A to be transferred on
to the data bus
 Cascade Buffer/Comparator
202

 compares the ID‟s all the 8259A used in system.

 Three I/O pins CASO-2 are outputs when the 8259A is
used as a master.
 The same pins act as inputs when the 8259A is in
 slave mode.
 8259A in master mode sends the ID of the interrupting
slave device on these lines.
 The slave thus selected, will send its preprogrammed
vector address on the data bus during the next INTA
pulse.
 PIN DIAGRAM
203
 SIGNAL DESCRIPTION
204

 CS: This is an active-low chip select signal for enabling

RD and WR operations of 8259A. INTA function is
independent of CS.
 WR : This pin is an active-low write enable input to
8259A. This enables it to accept command words from CPU.
 RD : This is an active-low read enable input to 8259A.
 A low on this line enables 8259A to release status onto the
data bus of CPU.
 D0-D7 : bidirectional data bus that carries 8-bit data
either to control word or from status word registers. This also
carries interrupt vector information
 SIGNAL DESCRIPTION
205

 CAS0 – CAS2 Cascade Lines : 8259A can provide

upto 64 vectored interrupt lines. These three lines act
as select lines for addressing the slave 8259A.
 PS/EN : When the chip is used in buffered mode, it
can be used as buffered enable to control buffer
transreceivers.
 ELSE pin is used as input to designate whether the
 chip is used as a master (SP =1) or slave (EN = 0)
 SIGNAL DESCRIPTION
206

 • INT : goes high whenever a valid interrupt request

is asserted.
 used to interrupt the CPU and is connected to the
interrupt input of CPU.
 IR0 – IR7 (Interrupt requests) :act as inputs to accept
interrupt request to the CPU.
 In edge triggered mode, an interrupt service is
requested by raising an IR pin from a low to a high
state and holding it high until it is acknowledged, and
just by latching it to high level, if used in level triggered
mode.
 INTA - ( Interrupt acknowledge )
207

 INTA : an input used to strobe-in 8259A interrupt vector

data on to the data bus.
 In conjunction with CS, WR and RD pins, this selects the
different operations like, writing command words, reading
status word, etc.
 8259A can be interfaced with any CPU using either polling
or interrupt.
 In polling, the CPU keeps on checking each peripheral
device in sequence to ascertain if it requires any service
from the CPU.
 If any such service request is noticed, the CPU serves the
request and then goes on to the next device in sequence.
 Interrupt Sequence in an 8086 system
208

1. One or more IR lines are raised high that set

Corresponding IRR bits.
2. 8259A resolves priority and sends an INT signal to
CPU.
3. The CPU acknowledge with INTA pulse.
4. Upon receiving an INTA signal from the CPU, the
highest priority ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive data during this
period.
 Interrupt Sequence in an 8086 system
209

 The 8086 will initiate a second INTA pulse. During this

 period 8259A releases an 8-bit pointer on to a data
bus from where it is read by the CPU.
 This completes the interrupt cycle. The ISR bit is reset at
 the end of the second INTA pulse if automatic end of
 interrupt (AEOI) mode is programmed.
 Otherwise ISR bit remains set until an appropriate EOI
command is issued at the end of interrupt subroutine.
 Command Words of 8259A
210

 1. Initialization command words (ICW)

 2. Operation command words (OCW)

 ICW
211

 If A0 = 0 and D4 = 1, the control word = ICW1. It

contains the control bits for edge/level triggered
mode, single/cascade mode, call address interval
and whether ICW4 is required or not

 If A0=1, the control word = ICW2

 ICW2 stores details regarding interrupt vector

addresses.
 INITIALIZATION SEQUENCE
212
 ICW1 and ICW2
213
 Initialization procedure
214

 The edge sense circuit is reset, i.e. by default 8259A

 interrupts are edge sensitive.
 IMR is cleared.
 IR7 input is assigned the lowest priority.
 Slave mode address is set to 7.
 Special mask mode is cleared and status read is set to
IRR.
 If IC4 = 0, all the functions of ICW4 are set to zero.
 Master/Slave bit in ICW4 is used in the buffered mode
 only.
 ICW
215

 In 8086 based system A15-A11 of the interrupt vector

 address are inserted in place of T7 – T3 respectively
and the remaining three bits A8, A9, A10 are selected
depending upon the interrupt level, i.e. from 000 to
111 for IR0 to IR7.
 ICW1 and ICW2 are compulsory command words
 ICW3 and ICW4 are optional
 The ICW3 is read only when there are more than one
8259A in the system,cascading is used ( SNGL=0 )
 ICW3 and ICW4
216
 ICW4
217

 depends on the IC4 bit of ICW1. If IC4=1, IC4 is used,

otherwise it is neglected.
 SFNM: If BUF = 1, the buffered mode is selected.
 buffered mode, SP/EN acts as enable output and the
 master/slave is determined using the M/S bit of ICW4.
 M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is
slave. If BUF = 0, M/S is to be neglected.
 AEOI: If AEOI = 1, the automatic end of interrupt mode is
selected
 μPM : If the μPM bit is 0, the Mcs-85 system operation is
 selected and if μPM=1, 8086/88 operation is selected.
 OPERATION COMMAND WORDS
218

 OCW1, OCW2 and OCW3

 OCW1 is used to mask the masked and if it is 0 the
request is enabled
 In OCW2 the three bits, R, SL and EOI control the
end of interrupt, the rotate mode and their
combinations
 L2, L1 and L0 in OCW2 determine the interrupt
level to be selected for operation, if SL bit is active
i.e. 1.
 OCW 1 & 3
219
 OCW 2
220
 OPERATING MODES OF 8259
221

 FULLY NESTED MODE - default mode

 EOI – End of Interrupt mode – specific & non-
specific
 Automatic EOI Mode : Till AEOI=1 in ICW4, the
8259A operates in AEOI mode
 Specific Rotation : a bottom priority level can be
selected, using L2, L1 and L0 in OCW2 and R=1,
SL=1, EOI=0
 OPERATING MODES OF 8259
222

 Specific Mask Mode: when a mask bit is set in

OCW1, it inhibits further interrupts at that level and
enables interrupt from other levels, which are not
masked
 Edge and Level Triggered Mode : decides whether
the interrupt should be edge triggered or level
Triggered
 If bit LTIM of ICW1 =0 they are edge
triggered,else level triggered.
 OPERATING MODES OF 8259
223

 Special Fully Nested Mode

 In this mode, when an interrupt request from a
certain slave is in service, this slave can further send
request to the master, if the requesting device
connected to the slave has higher priority than the
one being currently served
 OPERATING MODES OF 8259
224

 Buffered Mode: When the 83259A is used in the

systems where bus driving buffers are used on
data buses. The problem of enabling the buffers
exists.
 8259A sends buffer enable signal on SP/ EN pin,
whenever data is placed on the bus
 OPERATING MODES OF 8259
225

 Cascade Mode :
 one master and eight slaves (maximum) to handle
upto 64 priority levels
 The master controls the slaves using CAS0-CAS2
which act as chip select inputs (encoded) for slaves
 Cascade mode
226
DIRECT MEMORY ACCESS
CONTROLLER
(DMAC – 8237)
Techniques to synchronize data rate of
processor with peripherals

Technique

Polling Interrupt Direct memory

access
I/O Data Transfer
 Basic DMA concept
Direct memory access (DMA) is a feature of modern computer
systems that allows certain hardware subsystems to read/write data
to/from memory without microprocessor intervention, allowing the
processor to do other work.

Used in disk controllers, video/sound cards etc, or

between memory locations
.
Typically, the CPU initiates DMA transfer, does other operations while
the transfer is in progress, and receives an interrupt from the DMA
controller once the operation is complete.
 BASIC DMA TERMINOLOGY
DMA channel: system pathway used by a
device to transfer information directly to and
from memory. There are usually 8 in a
computer system
DMA controller: dedicated hardware used
for controlling the DMA operation
Single-cycle mode: DMA data transfer is
done one byte at a time
Burst-mode: DMA transfer is finished when
all data has been moved
 DMA pins and timing
 x86 Interrupt Pins
 HOLD: DMA request.
 Sampled in the middle of any clocking cycle
 HLDA: DMA acknowledge signal.
 Theaddress, data and control buses are set to high-Z, so the
I/O devices can control the system bus

1 2 3 4 5 6 7 8 9
CLK

HOLD

HLDA

232
 8237 pins
 CLK: System clock
233  CS΄: Chip select (decoder output)
 RESET: Clears registers, sets mask register
 READY: 0 for inserting wait states
 HLDA: Signals that the μp has relinquished buses
 DREQ3 – DREQ0: DMA request input for each channel
 DB7-DB0: Data bus pins
 IOR΄: Bidirectional pin used during programming and during a DMA write cycle
 IOW΄: Bidirectional pin used during programming and during a DMA read cycle
 EOP΄: End of process is a bidirectional signal used as input to terminate a DMA process
or as output to signal the end of the DMA transfer
 A3-A0: Address pins for selecting internal registers
 A7-A4: Outputs that provide part of the DMA transfer address
 HRQ: DMA request output
 DACK3-DACK0: DMA acknowledge for each channel.
 AEN: Address enable signal
 ADSTB: Address strobe
 MEMR΄: Memory read output used in DMA read cycle
 MEMW΄: Memory write output used in DMA write cycle
8237
Minimal System with a DMA Controller

CPU Bus Memory

Arbiter

Interrupt On-Chip-Bus

Request
DMA Peripheral
Controller Acknowledge Device
8237 DMA controller
THE 8237 DMA CONTROLLER
 The 8237 supplies memory & I/O with control signals and
memory address information during the DMA transfer.
 actuallya special-purpose microprocessor
whose job is high-speed data transfer between memory and
I/O
 Figure 13–3 shows the pin-out and block diagram of the
8237 programmable DMA controller.
 8237 is not a discrete component in modern
microprocessor-based systems.
 it appears within many system controller chip sets
 8237 is a four-channel device compatible
with 8086/8088, adequate for small systems.
 expandable to any number of DMA channel inputs
 8237 is capable of DMA transfers at rates up to 1.6M
bytes per second.
 each channel is capable of addressing a full
64K-byte section of memory and transfer up to 64K bytes
with a single programming
8237 Pin Definitions
CLK
 Clock input is connected to the system clock signal as
long as that signal is 5 MHz or less.
 in the 8086/8088 system, the clock must be inverted for
the proper operation of the 8237
8237 Pin Definitions
 Chip select enables 8237 for programming.
 The CS pin is normally connected to the output of a decoder.
 The decoder does not use the 8086/8088 control signal IO/M(M/IO)
because it
contains the new memory and I/O control signals (MEMR, MEMW,
 IOR and IOW).
 8237 Pin Definitions

RESET
 The reset pin clears the command, status, request, and
temporary registers.
 It also clears the first/last flip-flop and sets
the mask register.
 this input primes the 8237 so it is disabled
until programmed otherwise
8237 Pin Definitions
READY
 A logic 0 on the ready input causes the
8237 to enter wait states for slower
memory components.

HLDA
• A hold acknowledge signals 8237 that the
microprocessor has relinquished control of
the address, data, and control buses.
8237 Pin Definitions
DREQ0–DREQ3
 DMA request inputs are used to request a transfer
for each of the four DMA channels.
 the polarity of these inputs is programmable, so
they are either active-high or active-low inputs

DB0–DB7
• Data bus pins are connected to the
processor data bus connections and used
during the programming of the DMA
controller.
8237 Pin Definitions
IOR
 I/O read is a bidirectional pin used during programming
and during a DMA write cycle.

IOW
• I/O write is a bidirectional pin used during
programming and during a DMA read cycle.
8237 Pin Definitions

EOP
 End-of-process is a bidirectional signal
used as an input to terminate a DMA
process or as an output to signal the
end of the DMA transfer.
 often used to interrupt a DMA transfer at
the end of a DMA cycle
 8237 Pin Definitions
A0–A3
 These address pins select an internal
register during programming and provide
part of the DMA transfer address during a DMA action.
 address pins are outputs that provide part of
the DMA transfer address during a DMA action
8237 Pin Definitions

HRQ
 Hold request is an output that connects to
the HOLD input of the microprocessor in
order to request a DMA transfer.
 8237 Pin Definitions
DACK0–DACK3
 DMA channel acknowledge outputs acknowledge a channel
DMA request.
 These outputs are programmable as either active-high or active-
low signals.
 DACK outputs are often used to select the
DMA- controlled I/O device during the DMA transfer.
 8237 Pin Definitions
AEN

 Address enable signal enables the DMA address latch

connected to the DB7–DB0
pins on the 8237.
 also used to disable any buffers in the
system connected to the microprocessor
8237 Pin Definitions
ADSTB
 Address strobe functions as ALE, except
it is used by the DMA controller to latch
address bits A15–A8 during the DMA transfer.

MEMR
• Memory read is an output that causes
memory to read data during a DMA read
cycle.
8237 Pin Definitions
MEMW
 Memory write is an output that causes memory to
write data during a DMA write cycle.
 8237 block diagram
252
 Description
 Five main Blocks
1. Data bus buffer
2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.
DATA BUS BUFFER:
 It contain tristate ,8 bit bi-directional buffer.

 Slave mode ,it transfers data between

microprocessor and internal data bus.
 Master mode ,the outputs A8-A15 bits of memory
address on data lines (Unidirectional).
READ/CONTROL LOGIC:
 It control all internal Read/Write operation.

 Slave mode ,it accepts address bits and control signal

from microprocessor.
 Master mode ,it generate address bits and control
signal.
Control logic block:
 It contains ,
1. Control logic
2. Mode set register and
3. Status Register.
CONTROL LOGIC:
 Master mode -It controls the sequence of DMA
operation during all DMA cycles.
 It generates address and control signals.
 It increments 16 bit address and decrement 14 bit
counter registers.
 It activates a HRQ signal on DMA channel Request.
 Slave mode - it is disabled.
8237 Internal Registers
CWCR
 The current word count register programs
a channel for the number of bytes (up to 64K) transferred
during a DMA action.
 The number loaded into this register is one less than the
number of bytes transferred.
 for example, if a 10 is loaded to CWCR, then
11 bytes are transferred during the DMA action
8237 Internal Registers
BA and BWC
 The base address (BA) and base word count (BWC)
registers are used when
auto-initialization is selected for a channel.
 In auto-initialization mode, these registers
are used to reload the CAR and CWCR
after the DMA action is completed.
 allows the same count and address to be used
to transfer data from the same memory area
 8237 Internal Registers
CR
 The command register programs the operation of the
8237 DMA controller.
 The register uses bit position 0 to select the memory-to-
memory DMA transfer mode.
 memory-to-memory DMA transfers use DMA channel 0 to
hold the source address
 DMA channel 1 holds the destination address

 Similar to operation of a MOVSB instruction.

8237A-5 command register. (Courtesy of Intel Corporation.)
8237 Internal Registers

MR
 The mode register programs the mode of operation
for a channel.
 Each channel has its own mode register as selected
by bit positions 1 and 0.
 remaining bits of the mode register select operation,
auto-initialization, increment/decrement, and mode for
the channel
8237A-5 mode register. (Courtesy of Intel Corporation.)
8237 Internal Registers
BR

 The bus request register is used to request

a DMA transfer via software.
 very useful in memory-to-memory transfers,
where an external signal is not available to
begin the DMA transfer
8237A-5 request register. (Courtesy of Intel Corporation.)
8237 Internal Registers
MRSR
 The mask register set/reset sets or clears the
channel mask.
 ifthe mask is set, the channel is disabled
 the RESET signal sets all channel masks
to disable them
8237A-5 mask register set/reset mode. (Courtesy of Intel Corporation.)
8237 Internal Registers
MSR

 The mask register clears or sets all of

the masks with one command instead of individual
channels, as with the MRSR.
mask register. (Courtesy of Intel Corporation.)
8237 Internal Registers
SR
 The status register shows status of each DMA
channel. The TC bits indicate if the channel has
reached its terminal count (transferred all its bytes).
 When the terminal count is reached, the DMA
transfer is terminated for most modes of operation.
 the request bits indicate whether the DREQ input for a
given channel is active
8237A-5 status register. (Courtesy of Intel Corporation.)
Software Commands
 Three software commands are used to control the
operation of the 8237.
 These commands do not have a binary bit pattern, as
do various control registers within the 8237.
a simple output to the correct port number enables the
software command
 Fig shows I/O port assignments that access all registers
and the software commands.
8237A-5 command and control port assignments. (Courtesy of Intel Corporation.)
8237 Software Commands
Master clear
 Acts exactly the same as the RESET signal
to the 8237.
 as with the RESET signal, this command disables all
channels

Clear mask register

• Enables all four DMA channels.
 8237 Software Commands
Clear the first/last flip-flop
 Clears the first/last (F/L) flip-flop within 8237.
 The F/L flip-flop selects which byte (low or high order) is read/written in
the current address and current count registers.
 if F/L = 0, the low-order byte is selected
 if F/L = 1, the high-order byte is selected
 Any read or write to the address or count register automatically toggles the
F/L flip-flop.
Programming the Address and Count
Registers
 Figure shows I/O port locations for programming the
count and address registers for each channel.
 The state of the F/L flip-flop determines whether the
LSB or MSB is programmed.
 ifthe state is unknown, count and address could be
programmed incorrectly
 It is important to disable the DMA channel before
address and count are programmed.
8237A-5 DMA channel I/O port addresses. (Courtesy of Intel Corporation.)
 Four steps are required to program the 8237:
 (1) The F/L flip-flop is cleared using a clear F/L
command
 (2) the channel is disabled

 (3) LSB & MSB of the address are programmed

 (4) LSB & MSB of the count are programmed

 Once these four operations are performed, the

channel is programmed and ready to use.
 additional programming is required to select
the mode of operation before the channel is enabled and
started
The 8237 Connected to the 80X86

 The address enable (AEN) output of 8237 controls the

output pins of the latches and outputs of the 74LS257
(E).
 during normal operation (AEN=0), latches A & C and the
multiplexer (E) provide address bus bits A19–A16 and A7–
A0
 See Figure in next slide
Complete 8088 minimum mode DMA system.
 The multiplexer provides the system control signals as
long as the 80X86 is in control of the system.
 during a DMA action (AEN=1), latches A & C
are disabled along with the multiplexer (E)
 latches D and B now provide address bits
A19–A16 and A15–A8
 Address bus bits A7–A0 are provided directly by the
8237 and contain part of the DMA transfer address.
 The DMA controller provides control signals.
Memory-to-Memory Transfer with the 8237

 Memory-to-memory transfer is much more powerful

than the automatically repeated MOVSB instruction.
 most
modern chip sets do not support the memory-to-
memory feature
 8237 requires only 2.0 µs per byte, which is over
twice as fast as a software data transfer.
 This is not true if an 80386, 80846, or Pentium is in
use in the system.
A DMA controller allows the peripheral to interface directly with
memory without processor intervention. This allows the data transfer
rate to approach the access time of memory.

Types:
Sequential DMA
Simultaneous DMA
Three methods (MODES) of DMA operation: (a) byte; (b)
burst; (c) block.
Steps in a DMA operation
 Processor initiates the DMA controller
 Gives device number, memory buffer pointer, …
 Called channel initialization
 Once initialized, it is ready for data transfer
 When ready, I/O device informs the DMA
controller
 DMA controller starts the data transfer process
 Obtains bus by going through bus arbitration
 Places memory address and appropriate control signals
 Completes transfer and releases the bus
 Updates memory address and count value
 If more to read, loops back to repeat the process
 Notify the processor when done
 Typically uses an interrupt
Modes of Operation
 Rotating priority Mode:
 The priority of the channels has a circular sequence.
 Fixed Priority Rotating Mode:
 The priority is fixed.
 TC Stop Mode

 Auto Load mode

 Extended Write mode

Three DMA CYCLES: READ,WRITE,VERIFY

CASE STUDIES
Interfacing examples

LED DISPLAY

LCD DISPLAY

KEYBOARD DISPLAY

ALARM CONTROLLER
7-Segement Display

CA Select Segments: Switched Resistors to GND

 Vcc
Anode

Cathode
7-Segement Display
Select Segments: Switched Resistors to Vcc

CC

 GND
7 SEGMENT DISPLAY
MULTIPLEXED
7 SEGMENT LED DISPLAY
Common
To segment
on all Digits

n=8
Digits

Sequentially
Turn ON one digit at a time

Recommended rate: 100 – 1500 times per sec

7 Segment data transistor switches
Controlled by Port A bits, e.g. Tr 2
Address decoding is similar to
that of a 4-byte Read/Write memory

1 turns
segment ON
Tr 1
Tr 2 Most Significa
A: O/P Port:
(MS) Digit
Segment data
For selected digit Multiplex the eight digit displays
(only one is ON at a time)

0 turns digit
B:O/P
O/PPort:
Port:digit ON Vcc
B:
Selectdigit
Select # Displayed
To be displayed
1 digit
. . . . .Digit
. transistor
PLD for 14-bit
GND switch Controlled by
I/O address (A15-A2) + IO/#M decoding Port B bit,
e.g. Tr 1
 MS Digit
MEM+7
.
BX .
; Program the 82C55 for Port A and Port B are output ports in mode 0 .
MOV AL, 80H ; 80H Data into AL MEM LS Digit
MOV DX, 703H ; Address of Command Port into DX
OUT DX, AL ; Write 80H into Command Port
; ; to program PPI
; An assembly language procedure that multiplexes the 8-digit display.
; This procedure must be called often enough for the display to appear stable
DISP PROC NEAR USES AX BX DX SI
PUSHF
MOV BX,8 ;load counter BX with # of display digits
MOV AH,7FH ;load initial digit selection pattern to enable MS digit (01111111)
MOV SI,OFFSET MEM - 1 ;Load SI with offset (MEM) - 1
MOV DX,701H ;address Port B (for Port A: decrement DX)
;
;Sequentially display all 8 digits starting with MS digit
.
.REPEAT .
MOV AL,AH .
OUT DX,AL ;send digit selection pattern to Port B
DEC DX ;Address Port A (to send Digit Data)
MOV AL,[BX+SI] ;Load digit data from memory into AL
OUT DX,AL ;send digit data to Port A
CALL DELAY ;wait 1.0 ms leaving displayed digit ON
ROR AH,1 ;adjust selection pattern to point to next digit
INC DX ;Address port B
DEC BX ;decrement counter for data of next digit.
.UNTIL BX == 0
POPF
RET
DISP ENDP Procedure for 1 ms delay, e.g. a loop of
instructions
i.e. digit remains ON for 1 ms before moving
to next
; Delay Loop

DELAY PROC NEAR USES CX

MOV CX, XXXX ; XXXX determines delay, = Delay required / loop exec time
D1:
LOOP D1
RET Loop execution time is calculated from instruction data
DELAY ENDP and the clock frequency.

An 80486 executes ―LOOP D1‖ in 7 clock cycles

With a 20 MHz clock, loop exec time = 7 x 50 = 350 ns

XXXX = 1ms/350ns
Display Flashing Rate:

- Assume the DISP Procedure is called continuously

- Ignore loop execution times relative to delay time
(e.g. 350 ns << 1 ms)
1 ms DISP Proc DISP Proc
... ... ...
Digit Displayed8 7 2 1 8 7 2 1
8 ms Flashing rate = 1/8 ms = 125 Hz
LIQUID CRYSTAL DISPLAY
INTERFACE
 An LCD Display Interfaced to 8255
299

 LCDs (liquid crystal displays) have replaced LED

displays in many applications.
 Fig shows an Optrex DMC-20481 LCD display
interfaced to an 82C55.
 DMC-20481 is a 4-line by 20-characters-per-line
display that accepts ASCII code as input data
 It also accepts commands that initialize it and control its
application.
 DMC-20481 LCD display interfaced to the 82C55.

300
  The data connections, which are attached to the 82C55
301 port A, are used to input display data and to read
information from the display.
 For a 4-bit interface, D4–D7 pins are used where the data
must be formatted with the high nibble first, followed by
the low nibble.
 A few newer OLED devices contain a serial interface that
uses a single pin for the data.
302
 After initialization, time delays are no longer needed
when sending data or many commands to the display.
 The clear display command still needs a time delay as the
busy flag is not used .
 Instead of a time delay, the busy flag is tested to see
whether the display has completed an operation.
 The BUSY procedure tests the LCD display and only returns
when the display has completed a prior instruction.
303

 Once the BUSY procedure is available, data can be sent

to the display by writing another procedure called
WRITE.
 The WRITE procedure uses BUSY to test before trying to
write new data to the display.
 WRITE procedure, transfers the ASCII character from
the BL register to the current cursor position of the
display.
304

 The only other procedure needed for a basic display is the

clear & home cursor procedure, called CLS.
 This procedure uses the SEND macro from the initialization
software to send the clear command to the display.
 With CLS and the procedures presented thus far, you can
display any message on the display, clear it, display
another message, and basically operate the display.
KEYBOARD DISPLAY
INTERFACE
Keyboard Circuit Connections -Interfacing

 In most keyboards, the keyswitches are connected in a

matrix of rows and columns
 Getting meaningful data from a keyboard, requires
the following three major tasks:
 1. Detect a keypress.
 2. Debounce the keypress.
 3. Encode the keypress
 Three tasks can be done with hardware, software, or
a combination of two, depending on the application.
Interfacing a 4x4 Key Matrix
Row Inputs

I/P
Y

O/P
X
0 0 0 0
Column Outputs 1. All 0’s
0 2. Scan columns with To check
For any
one 0 to locate a Press/Release
pressed key
• With no keys pressed, all row inputs are 1‘s
• due to the pull up resistors connected to Vcc
• Column outputs are sequentially scanned as 0‘s
• If key (X,Y) is pressed, it connects the scanning
0 from column X output to row Y input. If no other key
is pressed on the same column, this allows the pressed
key to be identified.
PORT CONNECTIONS
Keyboard Circuit Connections and
Interfacing - Software Keyboard Interfacing

 When no keys are pressed, the column lines are held high by
the pull-up resistor connected to +5V.
 Pressing a key connects a row to a column. If a low is output
on a row and a key in that row is pressed, then the low will
appear on the column which contains that key and can be
detected on the input port.
 • If the row and column of the pressed key is known , you
then know which key was pressed, and you can convert this
information into any code you want to represent that key.
 An easy way to detect if any key in the matrix is pressed is
to output 0‟s to all rows and then check the column to see if
a pressed key has connected a low to a column
Two key lock out
 first output lows to all the rows and check the
columns over and over until the column are all high.
 This is done before the previous key has been
released before looking for the next one. In the
standard keyboard terminology, this is called two-
key lockout
Software keyboard interfacing - algorithm
 Once the columns are found to be all high, the program enters
another loop, which waits until a low appears on one of the columns,
indicating that a key has been pressed.
 This second loop does the detect task for us. A simple 20- ms delay
procedure then does the debounce task.
 • After the debounce time, another check is made to see if the key is
still pressed. I
 f the columns are now all high, then no key is pressed and the initial
detection was caused by a noise pulse or a light brushing past a key.
 If any of the columns are still low, then the assumption is made that it
was a valid key press.
Flow chart
 Still Wait for any remaining
pressed keys
Software Debounce
to be Released
Of Switch Release

Scan for the next keyWait for next key to

pressed
Software and locate its columnbe Pressed to
Debounce
Of Switch Press determine it
Scan again after things have
settled, and determine coordinates
(row, column) of pressed key 

Here, column is known Read Input Pattern

into CF

Determine row of key pressed

(look for 0 bit in read data)
row Use key position determ
To get its corresponding
Code stored in a lookup
Keyboard Interfacing with Hardware
 For the system where the CPU is too busy to be
bothered doing these
 tasks in software, an external device is used to do them.
 • One of a MOS device which can be do this is the
General Instruments AY5-2376 which can be connected
to the rows and columns of a keyboard switch matrix.
 • The AY5-2376 independently detects a keypress by
cycling a low down through the rows and checking the
columns.
 When it finds a key pressed, it waits a debounce time.
Keyboard Interfacing with Hardware
 If the key is still pressed after the debounce time, the
AY5- 2376 produces the 8-bit code for the pressed key
and send it out to microcomputer port on 8 parallel
lines. T
 The microcomputer knows that a valid ASCII code is on
the data lines, the AY5-2376 outputs a strobe pulse.
 • The microcomputer can detect this strobe pulse and
read in ASCII code on a polled basis or it can detect
the strobe pulse on an interrupt basis.
 • With the interrupt method the microcomputer doesn‟t
have to pay any attention to the keyboard until it
receives an interrupt signal.
Keyboard Interfacing with Hardware
 So this method uses very little of the microcomputer
time.
 The AY5-2376 has a feature called two-key
rollover. This means that if two keys are pressed at
nearly the same time, each key will be detected,
debounced and converted to ASCII.
 • The ASCII code for the first key and a strobe
signal for it will be sent out then the ASCII code for
the second key and a strobe signal for it will be sent
out and compare this with two-key lockout.
 EXERCISE PROBLEM
 Interface a 4 * 4 keyboard with 8086 using 8255 an write an ALP
for detecting a key closure and return the key code in AL. The
debounce period for a key is 10ms. Use software debouncing
technique. DEBOUNCE is an available 10ms delay routine.
Solution:
 Port A is used as output port for selecting a row of keys while Port

B is used as an input port for sensing a closed key.

 Thus the keyboard lines are selected one by one through port A and

the port B lines are polled continuously till a key closure is sensed.
 The routine DEBOUNCE is called for key debouncing. The
key code depends upon the selected row and a low
sensed column.
Interfacing a 4*4 keyboard
Example
 The higher order lines of port A and port B are left unused.
 The address of port A and port B will respectively 8000H and
8002H while address of CWR will be 8006H.
 The flow chart of the complete program is as given.
 The control word for this problem will be 82H. Code segment
CS is used for storing the program code.
 • Key Debounce : Whenever a mechanical push-button is
pressed or released once, the mechanical components of the
key do not change the position smoothly, rather it generates a
transient response
Flowchart
Example
 These transient variations may be interpreted as the multiple
key pressure and responded accordingly by the
microprocessor system.
 To avoid this problem, two schemes are suggested: the first
one utilizes a bistable multivibrator at the output of the key to
debounce .
 The other scheme suggests that the microprocessor should be
made to wait for the transient period ( usually 10ms ), so that
the transient response settles down and reaches a steady
state.
 A logic „0‟ will be read by the microprocessor when the key is
pressed.
Example
 In a number of high
precision applications, a
designer may have two
options- the first is to
have more than one 8-bit
port, read (write) the port
one by one and then from
the multibyte data, the
second option allows
forming 16-bit ports using
two 8-bit ports and use
16-bit read or write
operations.
ALARM CONTROLLER
Pre-Settable Alarm System

Program Statement :
 Design a pre-settable alarm system using
8253/54 timer.
 Use thumbwheel switches to accept 4 digit value in

seconds. Alarm should last for 5 seconds. Do not use

interrupt.
8086 based Pre settable alarm system
 Thumbwheel switches are interfaced through 8255 ports.
 Timing parameters are derived from the 8253/54. 74LS138
decoder is used to generate chip select signals for 8253/54
and 8255.
 One more 74LS138 decoder is used to generate IOR, IOW,
MEMR, and MEMW signals.
8086 based Pre settable alarm system
Alarm controller
 Counter 0 of 8253/54 is programmed in mode 0 to
give the pre-settable time period and counter 2 is
programmed in mode 0 to give delay of 5 seconds
 Clock input for 8253/54 is 10 kHZ count required to
get 1 second time interval is
 Count = Required Period / Clock Period
 = 1sec/100 s = 10000 =1 10 4 = 2710H
Alarm controller
 This count value is loaded in the count register of the
counter 1 and counter 1 is programmed in mode 2 to
generate square wave with frequency 1 Hz.
 The output of counter 1 is fed to the clock input of
counter 0 and counter 2.
 To read four digit of count, we need four
thumbwheels. One thumbwheel switch can be
interfaced using four input lines.
 So to interface four thumbwheels we need 16 lines.
 The IC 8255 is used to interface these thumbwheel
switches. Two thumbewheel switches are connected to
port A and other two are connected to port B.
Address map
Control word format
Control word format
Control word format
Control word format
Program
Program
Program
Delay subroutine