Analog Integrated Circmts and Signal Processing 1, 119-135 (1991)

9 1991 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

The CMOS Gain-Boosting Technique

KLAAS BULT AND GOVERT J.G.M. GEELEN

Phihps Research Laboratories, Eindhoven, The Netherlands

Received January 9, 1991; Revised April 5, 1991.

Abstract. The gain-boosting technique improves accuracy of cascoded CMOS circuits without any speed penalty.
This is achieved by increasing the effect of the cascode transistor by means of an additional gain-stage, thus in-
creasing the output impedance of the subcircuit. Used in opamp design, this technique allows the combination
of the high-frequency behavior of a single-stage opamp with the high DC-gain of a multistage design. Bode-plot
measurements show a DC-gain of 90 dB and a unity-gain frequency of 116 MHz (16 pF load). Settling measurements
with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding with a closed-loop bandwidth
of 18 MHz (35 pF load) and a settling accuracy better than 0.03 percent. A more general use of this technique
is presented in the form of a transistor-like building block: the Super-MOST. This compound circuit behaves as
a normal MOS-transistor but has an intrinsic gain gm. ro of more than 90 dB. The building block is self-biasing
and therefore very easy to design with. An opamp consisting of only 8 Super-MOST's and 4 normal MOST's
has been measured showing results equivalent to the design mentioned above.

1. Introduction means to enhance the DC-gain of an amplifier without

degrading the high-frequency performance. The result
Speed and accuracy are two of the most important pro- is a DC-gain that is proportional to the square of the
perties of analog circuits; optimizing circuits for both intrinsic MOS transistor gain gm. ro. In modern proc-
aspects leads to contradictory demands. In a wide vari- esses with short-channel devices and an effective gate-
ety of CMOS analog circuits such as switched-capacitor driving voltage of several hundreds of millivolts, the
filters [1]-[3], algorithmic A/D converters [41, sigma- intrinsic MOS transistor gain gm. ro is about 20-25 dB,
delta converters [5], sample-and-hold amplifiers and resulting in a DC-gain of the cascoded version of about
pipeline A/D converters [6], speed and accuracy are 40-50 dB. This is however in many cases not sufficient
determined by the settling behavior of operational [1], [8], [91.
amplifiers. Fast-settling requires a high unity-gain fie- Dynamic biasing of transconductance amplifiers
quency and a single-pole settling behavior of the opamp, [10]-[12], was one of the first approaches reported to
whereas accurate settling requires a high DC-gain. combine high DC-gain with high settling speed. In this
The realization of a CMOS operational amplifier approach the bias current is decreased, either as a func-
that combines high DC-gain with high unity-gain fre- tion of time during one clock period [10, 1 l] or as a
quency has been a difficult problem. The high-gain re- function of the amplitude of the input signal [121,
quirement leads to multistage designs with long-channel resulting in a higher DC-gain at the end of the settling
devices biased at low current levels, whereas the high period. This decreases the unity-gain frequency which
unit-gain frequency requirement asks for a single-stage makes the last part of the settling very slow.
design with short-channel devices biased at high cur- In [13] a triple-cascode amplifier has been imple-
rent levels. mented where the gain is proportional to (gin. ro) 3. This
Future processes with submicron channel length will approach has two significant disadvantages. First, every
enable us to realize higher unity-gain frequencies. transistor added in the signal path introduces an extra
However, the intrinsic MOS transistor gain gm. ro will pole in the transfer function. In order to obtain enough
then be lower [7], and the problem of achieving suffi- phase margin, the minimum load capacitance has to
cient DC-gain becomes even more severe. be increased, resulting in a lower unity-gain frequency.
There have been several circuit approaches to cir- Secondly, each transistor reduces the output-swing by
cumvent this problem. Cascoding is a well-known at least the effective gate-driving voltage.
 120 BuIt and Geelen

In [8], positive feedback is used to enhance the gain

of an amplifier. This approach however is limited = Vdd
by matching. A gain enhancement of about 16 dB is
reported. Starting from an original gain of 50 riB,
one could obtain 70 dB DC-gain. For high-Q, high-
frequency switched capacitor filters, this is not suffi- q I'---'- .%
cient. Even a moderate Q of 25 and a maximum devia-

II
tion of 1 percent requires a minimum opamp gain of
74 dB [1, 8]. Therefore, we aim at a DC-gain of at Vref_

't
least 80 dB combined with a unity-gain frequency of I T2
100 MHz.
In [14], a regulated-cascode stage was reported that
increases the DC-gain of a normal-cascode stage. In
Cload
[15], the performance of this circuit with respect to out-
put swing and output impedance was analyzed. The ex- Vi_ w
I1[ T1
tension of this circuit into a general gain-boosting
technique was presented in [16, 17], showing a com-
plete opamp design with a measured DC-gain of 90 dB A
v
_ Vss
and a unity-gain frequency of 116 MHz. It was shown
that this technique enhances the DC-gain of a cascoded Fig. 1. Cascoded gain-stage.
amplifier several orders of magnitude without any
penalty in speed or output swing.
This paper gives a complete overview of the gain- 2.1. Cascode Stage
boosting technique and presents a general use of this
technique in the form of a transistor-like building block: The transfer function of the cascode stage can be found
the Super-MOST. as follows. Suppose an ideal voltage source is connected
In section 2 the principle of the gain-boosting tech- to the output of the stage. If a voltage AVi is applied
nique is explained. Section 3 deals with the high- to the input, a current AIo will flow into the voltage
frequency behavior. Section 4 discusses the optimiza- source. For low frequencies:
tion toward fast settling behavior. In section 5, some
AI o _ (gm2Fol -t- Fol/ro2 )
remarks on output swing are made. In section 6, the -- -- gml = gm,eff. (1)
circuit implementation of an opamp is presented; and AV~ (gm2rm + rol/ro2 + 1)
in section 7 the measurement results of this opamp are This effective transconductance is almost equal to
shown. Then, in section 8, the Super-MOST is gin1, the reduction is caused by the feedback via the
presented, along with measurement results of the device drain of the input transistor. Removing the voltage
on its own as well as of an opamp built with this source causes a change AVo = z~/oRout, where AIo is
building block. calculated using (1) and Rout is the output resistance of
the total circuit. The voltage-gain Ao is

2. Gain-Boosting Principle Ao = gm,effRout (2)

The output impedance of the total circuit can easily
We start this section with the functioning of the simple be calculated to be
cascode stage shown in figure 1. We show that the DC-
gain can be expressed as the product of an effective Rout = (gm2ro2 + 1)rol + ro2 (3)
t r a n s c o n d u c t a n c e gm,eff and the output-impedance.
which leads to the following expression for the
This explanation leads to the gain-boosting principle.
DC-gain:
The repetitive application of this principle leads to a
decoupling of the DC-gain and the unity-gain frequency Ao = gmlrol(gmaro2 + 1) (4)
of an opamp.
 The CMOS Gain-Boosting Technique 121

The behavior of the circuit, in the vicinity of the Moreover, the effective transconductance is slightly
unity-gain frequency, is similar with the voltage source increased:
connected to the output. Now the load capacitor Cload
Ado _ d + 1) + rol//'o2 )
(gmzrol(Aaa
forms the short-circuit to ground. At the unity-gain fre- - - -- g m l = gin,eft
AE (gm2rol(Aadd+ 1) + rol/ro2 + 1)
quency we use the effective transconductance as given
by (1), and this results in the following expression for (7)
the gain-bandwidth product (GBW): Hence, the total DC-gain now becomes:
GBW = gin,elf/Cloud (5) Ao.to t = gralrol(gmzro2(Aada + 1) + 1) (8)
From equations (2) and (5) we may conclude that the Section 3 deals with the high-frequency behavior of this
only way to improve Ao without reducing the GBW is circuit and discusses what happens if the gain of the
to increase the output impedance. Note that this is the additional stage decreases as a function of frequency.
effect of the cascode transistor itself with respect to the
noncascoded situation: the cascode transistor shields
2.3. Repetitive Implementation of Gain Boosting
the drain of the input transistor from the effect of the
signal swing at the output.
If the additional stage is implemented as a cascode
As we can see from (2), the DC-gain is proportional
stage, the gain-enhancement technique as described
to the output impedance of the circuit. This implies that
above can also be applied to this additional stage. In
we may consider the gain of such a stage as the output-
this way, a repetitive implementation of the gain-
impedance normalized on 1/gin,off. We will use this ap-
enhancement technique can be obtained as shown in
proach in section 4.
figure 3. The limitation on the maximum voltage gain
is then set by factors as leakage currents, weak ava-
lanche, and thermal feedback. The implementation of

"I
2.2. Gain-Boosting Principle
the additional stage is discussed in section 6.
The technique presented here is based on increasing 9 ..............................................

the cascoding effect of T2 by adding an additional gain-

stage as shown in figure 2. This stage further reduces :: .......
.~j

the feedback from the output to the drain of the input [

transistor. Thus, the output impedance of the circuit

is further increased by the gain of the additional gain-
stage Aadd: vo -- r...........": r,,*
Rout = (gm2ro2(Aada + 1) + 1)rol + ro2 (6)
3/ ':'-----i"1i
[

............ ~. ,*'"~
31 [

!
i ......

9 L " Vdd I
~F"
I1 I
if"
, !
Vi

Y .Vo
Fig. 3. Repetitive implementation of gain enhancement.

From the above, we may conclude that the repetitive

VreVif'_- _~1 12 Cload usage of the gain-enhancement technique yields a

decoupling of the opamp DC-gain and unity-gain
frequency.

= I
|
1 3. High-Frequency Behavior
9 9 VSS
In this section, we discuss the high-frequency behavior
Fig. 2. Cascoded gain-stage with gain enhancement. of the gain-enhanced cascode stage of figure 2. It is
122 Bult and Geelen

shown that for a first-order roll-off, the additional stage From the above, to obtain a first-order roll-off
need not be fast with respect to the unity-gain frequency of the total transfer function, the additional gain-stage
of the overall design. does not have to be a fast stage. In fact, this stage
In figure 4, a gain Bode-plot is shown for the original can be a cascoded gain-stage as shown in figure 1,
cascoded gain-stage of figure 1 (Aorig), the additional with smaller width and nonminimal length transistors
gain-stage (Aadd) and the improved cascoded gain-stage biased at low current levels. Moreover, as the addi-
of figure 2 (Atot). At DC, the gain enhancement tional stage forms a closed loop with T2, stability
Atot/Aorig equals approximately [1 + Aadd(0)], accord- problems may occur if this stage is too fast. There
ing to equations (4) and (8). For ~0 > c01, the output are two important poles in this loop. One is the domi-
impedance is mainly determined by Cload. In fact, we nant pole of the additional stage and the other is the
have to substitute (Rout//Cload) in equation (2) for Rout. pole at the source of T2. The latter is equal to the
This results in a first-order roll-off of Atot(W). second pole, o~6, of the main amplifier. For stability
Moreover, this implies that Aaad(o~) may have a first- reasons, we set the unity-gain frequency of the addi-
order roll-off for o~ > co2 as long as ~02 > ~01. This tional stage lower than the second pole frequency of
is equivalent to the condition that the unity-gain fre- the main amplifier. A safe range for the location of the
quency (~04) of the additional gain-stage has to be unity-gain frequency o~4 of the additional stage is given
larger than the 3-dB bandwidth (c03) of the original by
stage, but it can be much lower than the unity-gain fre-
quency (r of the original stage. The unity-gain fre- ~3 < ~4 < ~6" (9)
quencies of the improved gain-stage and the original
gain-stage are the same. This can easily be implemented.

t gain (log)

Atot

gain enhancement

Aadd
Aorig"
\\\\\\\~

", \ c0(,og)
, , , \, \
I I I I\ \ \ I~

Fig. 4. GainBode-plotsof the originalcascodedgain-stage(Aong),the additionalgain-stage(Aadd), and the improvedcascodedgain-stage(Atot).

 The CMOS Gain-Boosting Technique 123

4. Settling Behavior Aadd, decreases for frequencies above (.02 (figure 4)

with a slope of - 2 0 dB/decade. For frequencies above
In this section, the settling behavior of the gain- w4, Aada is less than one, and the normal output im-
enhanced cascoded amplifier-stage is discussed. It is pedance Zorig of a cascode stage without gain-
shown that a single-pole settling behavior demands a enhancement remains. This is shown in figure 5. Also
higher unity-gain frequency, of the additional stage than shown is the impedance of the load capacitor Zlo~dand
a simple first-order roll-off in the frequency domain the parallel circuit which forms the total impedance,
requires as discussed in the previous section. The Ztot, at the output node. A closer look at this plot
reason for this is the presence of a closely spaced pole reveals that a doublet is present in the plot of the total
and zero (doublet). In section 4.1 the occurrence of a output impedance near c04.
doublet in the gain-enhanced cascode amplifier-stage Noncomplete doublet cancelation can seriously
is discussed. Section 4.2 presents a graphical represen- degrade the settling behavior of an opamp [18]. If a
tation of the settling behavior of an opamp, and finally doublet is present in an opamp open-loop transfer func-
in section 4.3, the condition for one-pole settling is tion at Wpzwith a spacing of AC0pz,the opamp is used
presented. in a feedback situation with feedback factor/3, a slow-
settling component is present with time constant 1/Wpz.
The relative magnitude (with respect to the total out-
4.1. Doublet put signal) of the slow-settling component is given
by [181:
From (6), the gain-enhancement technique increases
the output impedance, Zout, by a factor approximately AV~176 = Z~C'0PZ " ('OPz -- A('OPZ (10)
equal to (Aadd + 1). The gain of the additional stage, A Vout,tota I r fl(.Ounity ~02un,ty

,,, normalized impedance

gm-1 """%%%. (log)

\ Zouf
\
gin-1
\
\
\
\
\
\
\
Zorig \

gm 1

pole-zero
Oog)
I I I I

Fig. 5. The normalized output impedance as a function of frequency.

124 Bult and Geelen

For a single-pole settling behavior, the relative (10), the slow-settling component has a relative
magnitude of the slow-settling component, given in (10), magnitude of -74 dB in this situation, which is in close
has to be smaller than the ultimate settling accuracy agreement with the result shown. The slope of this line
1/flAtot(O). Note that for opamps with a very high D e - is 50 times smaller than the slope of the fast-settling
gain this requirement can be very difficult to realize. component. Curve C shows the result of a simulation
with an opamp with again the same DC-gain and unity-
gain frequency but now with a doublet at 2.5 MHz and
4.2. Graphical Representation of Settling Behavior a relative spacing of 10 percent. As seen from this
figure, slow-settling components can easily be detected
The settling behavior of an opamp can be judged very in this way. In section 7, where we show the measure-
well by plotting the relative settling error (the ratio of ment results, we use this representation to judge the
the signal at virtual ground of the opamp and the output- settling behavior of our design.
step) versus time, as shown in figure 6. Here an ideal
single-pole settling behavior is shown as a straight line.
In figure 6, the simulated result is shown of an opamp 4.3. Optimization of Settling Behavior
in unity-feedback with a unity-gain frequency of 25
MHz and a DC-gain of 100 dB. Curve A shows the To determine the spacing in the doublet in the transfer
result without the presence of a doublet: a straight line function of the gain-enhanced cascode stage, consider
down to -100 dB with a steep slope corresponding to again the impedance plot of figure 5. The total im-
one small time constant. Curve B shows the result of pedance at the output of the amplifier is the parallel
an opamp with the same DC-gain and unity-gain fre- connection of the load capacitance and the output im-
quency but now with a doublet of 500 KHz and 1 per- pedance of the circuit. At o~2, the output impedance of
cent spacing. The slow-settling component causes a the circuit begins to decrase as a function of frequency
severe deviation from the straight line. According to due to the roll-off of the additional stage. This can be

0.0

I I
-20.0
cn
-(3
i J
-40.0

>1 -60.0
-<..
-80.0

A
-100.0
0 100 200 300 400 500

time [nsec]
Fig. 6 Relative settling error as a function of time.
 The CMOS Gain-Boosting Technique 125

modeled as a small capacitor in parallel with the out- ent fast enough. If the time constant of the doublet
put resistor. The ratio between this small capacitor and 1/Wpzis smaller than the main time constant 1//3C0umty,
the load capacitor is 601/w2 (:603/604), as can be seen the settling time will not be increased by the doublet.
in figure 5. This small capacitor is simply parallel- This situation is achieved when the unity gain frequency
connected to the (large) output capacitance and gives of the additional stage is higher than the - 3 dB band-
a small shift of the total impedance at the output. At width of the closed-loop circuit. On the other hand,
r however, the effect of this small capacitor disap- for reasons concerning stability, the unity-gain fre-
pears due to the 1 in the (A~dd + 1) terms. At this fre- quency must be lower than the second-pole frequency
quency, a small shift in the total output impedance oc- of the main amplifier as indicated by (9). This results
curs, back to the original line (in figure 5) determined in the "safe" area for the unity-gain frequency of the
by the load capacitor only. It is also at this frequency additional stage
where the doublet is located in the total transfer func-
/~605 < C04 < 606 (12)
tion. From the above we can conclude that the relative
spacing of the doublet is approximately 603/w4. This as shown in figure 7. Note that this safe area is smaller
results in a relative magnitude of the slow-settling com- than given by (9). A satisfactory implementation
ponent according to (10) of however is still no problem, even if/3 = 1, because
the load capacitor of the additional stage, which deter-
AV~176 -- 6~ (1 1) mines w4, is much smaller than the load capacitor of
A Vout,totaI /~r the opamp, which determines ws.
which is equal to the inverse of the feedback factor
multiplied by the DC-gain of the original cascode stage 5. Output Swing
without gain enhancement! Thus we may conclude that
the pole-zero cancellation is not accurate enough. Our The output swing is limited by the requirement that all
approach here is to make this "slow'settling compon- transistors have to remain in the saturation region,

gain (log)
t
Aadd
\
\
\
\

Aclosed_loop "\ N

q/
I
co(log)
it-

safe range for 004

Fig. 7. The "safe" range for the unity-gain frequency of the additional stage.
126 BuIt and Geelen

otherwise a severe decrease in gain resulting in large transistor [14, 15, 20]. We have chosen a cascode version
distortion will occur. The edge of saturation of an MOS because of its high gain and the possibility of repetitive
transistor occurs when the gate-drain voltage equals the usage of the gain-enhancement technique as discussed
threshold voltage at the drain [19]: in section 2. The input-stage design of the additional
amplifier is determined by the common-mode range re-
VD,min -- VG -- Vt~ (13) quirement which is close to the Vss as discussed before.
l+c~ As a consequence, a folded-cascode structure with
which is the effective gate-driving voltage divided by PMOS input transistors is chosen for the additional
(1 + a) representing the body effect, where o~is deter- amplifier in figure 2. To realize a very high output im-
mined by processing [19]. Note that a large body-effect pedance, the current source in figure 2 is also realized
is advantageous there. In this design, an effective gate- as a cascoded structure with an additional gain stage.
driving voltage of 250 mV was chosen. With a = 0.3, A fully differential version (figure 8) has been inte-
this results in a minimum drain-source voltage of 190 grated in a 1.6-/zm CMOS process. The two input trans-
inV. Applying this result to the amplifier stage in figure istors connected to Vcm have been added to control the
2 leads to a minimum output voltage of 380 mV and common-mode bias voltage at the output. Using this
to a large-signal output swing of Vda -- 2 * 380 mV. scheme, the circuit can also be used as two single-ended
With a 5.0 V supply, this results in a maximum output opamps. The die photograph of figure 9 clearly shows
swing of 4.2 V. Note that a different criterion is used that the additional stages are much smaller in chip area
for the maximum swing and the output than in [15]. than the main opamp.
To be able to obtain this large output swing, the addi-
tional stage has to have an input common-mode range
close to the supply voltage Vss. 7. Opamp Measurement Results

As it is very difficult to measure differentially at high

6. Opamp Circuit Implementation frequencies with sufficient accuracy, all measurements
have been performed single-ended. The output node
In this section, the implementations of the main opamp of the additional amplifier in figure 2 is connected to
and the additional gain-stages are discussed. The main a bonding pad in order to be able to switch off the gain-
stage is a folded-cascode amplifier [2]. The simplest enhancement technique. Results of gain measurements
implementation of the additional stage is one MOS- both with and without gain enhancement are shown in

Vdd ,
. Vdd
]k- vb., vbpl 11 11~
11 :
~m
tff k---
I

vo., + Vo,,(
i I
I I O lb
---t
i F- v o,
f
Fig. 8, Complete circuit diagram of the opamp.
' Vss
 The CMOS Gain-Boosting Technique 127

# - -

~ ' ~ _ ~ :i..i:!i].i_ i: i-,

i~,~.ib-ii iiiiiiii'i i i:i i.i: iii i.
~ - , , ..~(i~'ii:i i i i:i i:,
' ~ ~ : ~ i iiiii:ii
i

~ ~ i,,,, i m . ~ i i
i~_~i_i~_i.~iiii ii~_ii i i.i i i i i ~ i
'~m ~ _ m ~ .~.~.,~i!:i...i. _i-
" l- - i- - ~- - ~ - - i m ~ ........ ~ a
nl.ll_ . . .i. .N
.. U . ' "
" -4" ~'~ ~ ~ ~ ~

Fig. 9. Die photograph of the opamp.

100
--H~ II I II I
OAIN "~ I III
[dB]

0.0
IIIII
IIII,,'li,lJ!"
II~-. J,lt~ II W":L--IJ,IJJItL
l]~-lfT~- "
0.0

-90
PHASE
[~g]

/ II "
1K 1OK lOOK 1M IOM lOOM

Frequency [Hz]
Fig. 10. Results of gain and phase measurements both with and without gain enhancement.

figure 10. A DC-gain enhancement of 45 dB was mea- with a unity-gain frequency of 116 MHz. This shows a
sured without affecting the gain or phase for higher fre- good agreement with figure 4. Note that when measured
quencies, resulting in a total DC-gain of 90 dB combined differentially, both the DC-gain and the unity-gain
128 Bult and Geelen

frequency are expected to be twice as high. The settling enough to avoid slewing. With the gain enhancement
behavior is measured according to figure 11 by applying switched off, an error signal of 4.75 mV is measured
a step, zXV~,at the input. The resistors are needed for after settling (figure 12a). This corresponds to the
DC-biasing of the opamp and have no influence on the measured DC-gain of 46 dB. Switching on the gain
settling behavior. The error signal V_ at the opamp in- enhancement reduces the error signal to a value smaller
put, and the output signal Vo are shown in figure 12. than 0.1 mV (figure 12b), which corresponds to a DC-
In figures 12a and 12b, 2xVo = 1V which is small gain higher than 80 dB.

Ci ~ Cf
V
v I I, vi :
_.vo .voW;
Cp=22pT : Co=20P
_1._
Fig. 11. S c h e m e for m e a s u r i n g settling behavior.

i
(o) (c)
B=5OOmV B=lV
A=2mV A=10mV
~:;"C.~-:::~............................................

(b) (~)
B=500mV B=IV
A= 1m V A=5mV

Fig. 12. Settling-measurement results. The output signal (upper trace) and the error signal at the opamp input (lower trace) with: (a) AVo
= IV and gain e n h a n c e m e n t switched off, (b) z%Vo = IV and gain e n h a n c e m e n t switched on, (c) ,SVo = 4V a n d gain e n h a n c e m e n t switched
off, (d) AVo = 4V and gain e n h a n c e m e n t switched on.
 The CMOS Gain-Boosting Technique 129

Settling speed can be calculated as follows. In figure Table 1. Main characteristics of the opamp.
11 the feedback factor/3 is given by
Gain enh. on off
/3 = Cf (14) DC gain 90 dB 46 dB
Ci + Cp + Cf Unity-gain freq. 116 M H z 120 MHz
whereas the unity-gain frequency is given by Load cap. 16 pF 16 pF
Phase margin 64 deg. 63 deg.
Power cons. 52 rnW 45 m W
O3umty : gm Ca + Cp + Cf (15)
Output swing 4.2 V 4.2 V
C o ( C i "b Co "-}- Cf) "t- (C, -}- Cp) C f
Supply voltage 5.0 V 5.0 V
The theoretical settling-time constant, r, can now be
calculated: A disadvantage of cascoded amplifiers in general is the
T = Cp -1- C i -]- C O q- ( C i q- C p ) " Co/C f (16) number of required biasing voltages resulting in long
grn wires across the chip. These long wires consume a con-
siderable amount of space and, what is worse, are sus-
In figure 11, Co = 20 pF and Cp = Ci = Cf = 22 pE
ceptible to cross-talk and therefore instability. To cir-
which is relatively large due to probing. With gm =
cumvent this problem, the Super-MOST was developed.
0.012 A/V, we find O~anity = 54 MHz,/3 = 1/3 and r
= 8.8 ns. Settling to 0.1 percent takes 7r -- 62 ns and
corresponds to a 1-mV error at the output. With a feed-
8.1 Basic Idea and Circuit Description
back factor/3 = 1/3, this corresponds to an error signal
of V_ = 0.33 mV. From figure 12b the measured set-
The Super-MOST is a compound circuit that behaves
fling time for 0.1 percent accuracy is 61.5 ns, which is
like a cascoded MOS transistor and has, like a normal
in agreement with the theory. In figure 13, the measured
MOST, a source, a gate, and a drain terminal. The
settling behavior is shown as a function of time as dis-
Super-MOST, however, has an extremely high output
cussed earlier. During the entire settling process, each
impedance due to implementation of the gain-boosting
10-dB increase in settling accuracy takes approximately
technique. Moreover, it does not require any biasing
8 ns. This clearly shows that there are no slow settling
voltage or current other than one single power supply.
components. In figures 12c and 12d, AVo = 4V, C i :
The circuit of an N-type Super-MOST is shown in
33 pE and Cf = 15 pF, showing a normal slewing
figure 14a. The circuit consists of three parts:
behavior and a large output swing. The main measured
characteristics of the opamp are summarized in table 1. 1. Transistors N1 and N2 are the main transistor and
its cascode transistor and form the core of the cir-
-3O cuit. Their size determines the current-voltage rela-
tions and the high-frequency behavior of the
-40
"device"
-(3 OFF
-50 2. Transistors N7, N8, P2, and P4 form the additional
>o stage for the gain-boosting effect.
-60
! i 3. Transistors N3, P1, P3, N4, N5, and N6 are for bias-
>1 -70
i } J r ing purposes and ensure that N2 is always biased
......... ~.......... l.......... r ............l ...........

-80
i ! r oN
in such a way that N1 is just 50-100 mV above the
edge of saturation, independent of the applied gate
3O 40 50 60 70 voltage. This ensures a low saturation voltage of the
l i m e [nsec] Super-MOST.
The size of the transistors of the additional stage and
Fig 13. Measured relative-settling error as a function of time for both
with and without gain enhancement. of the biasing branch is as small as a few percent of
the main transistors.
Figure 14b shows the symbols for the Super-MOST,
8. The Super-MOST S is the source terminal, G is the gate terminal, and
D is the drain terminal. Furthermore, an extra low-
A disadvantage of the above-shown implementation of impedance current-input terminal F is available which
the opamp is the complexity of the design and layout. can be used for folded-cascode structures.
130 Bult and Geeten

9 Vdd

SOURCE/Vss
Fig. 14, a) N-type Super-MOST.
curve, an early voltage of 1750 volts can be calculated
N-type P-type which is an increase of 350 times compared to a single
MOST.
D S
8.3 Fundamental Limitation of the Gain-Boosting
Technique

This measurement (figure 15b) also reveals the upper

G F G~ F limit for the gain-boosting technique. The voltage VF
at the F terminal changes 0.8 mV as the drain voltage
varies 5 V. This would imply an increase in early
"1 voltage and output impedance of 6250 times. The lower
measured early voltage is due to a weak avalanche cur-
S D rent which flows directly from drain to substrate and
is therefore not influenced by the gain-boost technique.
Fig. 14. b) Super-MOSTsymbols.
In fact, this weak avalanche current imposes an upper
limit to the output impedance achievable with the gain-
8. 2. Measured "Device" Characteristics
boosting technique.
Figure 15a shows the measured characteristics of a
single N-type MOST and a Super-MOST for Vgs rang- 8.4. Applications of the Super-MOST
ing from 0.7 V (a) to 1.0 V (g). The single MOST shows
an early voltage of approximately 5 V whereas the The Super-MOST can be used as a normal MOS trans-
Super-MOST has an early voltage several orders of istor. As an example, a current mirror has been realized
magnitude higher. Note that the "device" is already as shown in figure 16a. Figure 16b shows the measured
saturated at a voltage only slightly above the satura- results for a P-type current mirror at several input cur-
tion voltage of one single MOST, indicating a large rents and output voltages. The mirror accuracy is in-
possible output swing. In figure 15b, an enlargement dependent of output voltage and is only determined by
of figure 15a is shown for Vgs = 0.95 V. From the los matching.
 The CMOS Gain-Boosting Technique 131

8 single MOST- J

I
super MOST- .~ ~ "

v~

<

v
E
O3
~ ,,,~., ~ ,ill .,~,~ ~ m"m P

/ .-----#'"

-9ff -if- -- . . . . - _--

m~

. . . . . . . . - _ _ -_ _ .~ - ~ - _ _,

0~ - a ~

0 1 2 3 4 5
Vos (v)
Fig, 15. a) Measured Ids -- Vds characterist]cs of single N-type MOST and Super-MOST for Vgs ranging from 0.7V (a) to 1.0V (g).

The F terminal of the Super-MOST provides a very than 25 percent smaller as compared to the design of
low-ohmic current input which can be used for folded- figure 9.
cascode structures [2]. In figure 17 measurement results
of a P-type Super-MOST show an input impedance
8.5. Advantages of the Super-MOST
lower than 1 ohm for low frequencies.
As an example, figure 18 shows a straightforward
There are several advantages in using Super-MOST's
circuit topology of a folded-cascode opamp but now
as a building block in circuit design:
realized with Super-MOST's. Note that the tail current
of the differential input-pair also consists of a Super- 1. The design of high-quality opamps, OTAs, current
MOST. In this way the common-mode rejection ratio sources, etc., can be split into two parts. First the de-
CMRR is increased several orders of magnitude for low sign of the Super-MOSTs, in which the knowledge of
frequencies. For the input-pair, normal transistors have proper biasing, gain-boosting, optimal settling, and
been used. Measured results of this straightforward stability is used. Much attention can be paid to an opti-
design are equivalent to the results shown in table 1. mal layout also, as this subcircuit is going to be used
Figure 19 shows the die photograph of the chip, con- in many designs at several points in the comprising
taining 1 opamp, 1 N-type Super-MOST, and 2 P-type circuit. Secondly, the design of the comprising cir-
Super-MOST's. As can be seen, a Super-MOST con- cuit, which now becomes rather straightforward. In
sumes only 20 percent more chip area compared to a this higher-level design no knowledge of the gain-
normal cascoded transistor. With a more careful layout boosting principle or of optimal biasing of a cascode
this can be even further reduced. Because there is no transistor is required. This eases the design of such
need for extra biasing, the total opamp chip area is more circuits and shortens the design time considerably.
132 Bult and Geelen

3.510 411.0

<17
v
E
03
3.495 410.5
lJ
J
J
J
J
f' f -

3.480 410.0
0.5 1.5 2.5 3.5 4.5 5.5

VDS (V)
Fig. 15. b) Enlargement of curve f of figure 15a.

2. The design of Super-MOSTs is very suitable for

parameterized automatic generation.
3. As each Super-MOST is self-biasing, no long bias-
| -" ing wires are required on chip, leading to a design
9 [ that is much less susceptible to cross-talk and
9 therefore also for instability problems.
4. As wiring usually consumes a relatively large part
of the chip area, the approach presented here con-
sumes considerably less chip area.
Comparison of the die-photographs of figures 9 and
19 clearly shows the difference in design strategy with
and without Super-MOSTs.

, ii

9. Conclusions

A technique is presented which decouples the DC-gain

and unity-gain frequency of an opamp. A very high DC-
gain can be achieved in combination with any unity-
gain frequency achievable by a (folded-) cascode design.
With this technique, an opamp is realized in a stan-
dard 1.6-gin CMOS process, which has a DC-gain of
I in I out 90 dB together with a unity-gain frequency of 116 MHz.
The opamp shows one-pole roll-off and single-pole set-
Fig. 16. a) Current mirror with Super-MOSTs. fling behavior.
 The CMOS Gain-Boosting Technique 133

10
, single MOST
8 - super M O S T
F

= 4 'C "" "" " ~'

2 -
---- a-"
-r-
0

0 -1 -2 -3 -4 -5
VDs (v)
Fig. 16 b) Measured output current of a P-type current rrnrror with I m ranging from 1.0 mA (a) to 5.0 mA (e).

10 -lin = 5.1 mA - j -820.0

J
< >
E - j v
E
0 5 " "-- - -815.0 >
It.

7-.

0 ~ -810.0
-5.0 0 5.0
I F (mA)
Fig, 17. Measured output current lout and terminal voltage Vf as a function of If for a P-type Super-MOST.
134 Bult and Geeten

"Vdd

Ibias Vout,4 -I Vin

Vout,R
]
--~ Vss
Fig. 18 Folded-cascode opamp realized with Super-MOSTs.

Fig. 19. Die photograph of Super-MOST opamp.

 The CMOS Gain-Boosting Technique 135

This technique does not cause any loss in output 16. K. Bult and G.J.G.M. Geelen, ' ~ fast-settling CMOS opamp
voltage swing. At a supply voltage of 5.0 V, an output with 90-dB DC gain and 116 MHz unity-gain frequency," 1SSCC
swing of about 4.2 V is achieved without loss in Dig. Tech. Papers, February 1990, pp. 108-109.
17. K. Bult and G.J.G.M. Geelen, "~ fast-settling CMOS oparnp
DC-gain. for SC circuits with 90-dB DC gain," IEEE J. Solid-State Cir-
The advantages above are achieved with only an in- cuits, vol. 25, no. 6, 2990, pp. 1379-1384.
crease in chip area of 30 percent and an increase in 18. B.Y. Karnath, R.G. Meyer, and P.R. Gray, "'Relationship between
power consumption of 15 percent. frequency response and settling time of operational amplifiers,"
The Super-MOST presented here considerably eases IEEEJ. Solid-State Circuits, vol. SC-9, no. 6, 1974. pp. 347-352.
19. H. Wallinga and K. Bult, "Design and analysis of CMOS analog
the design of high-gain amplifiers. As the building block signal processing circuits by means of a graphical MOST model"
is completely self-biasing, there are no long wires in IEEEJ. Solid-State Circuits, vool. 24, no. 3, 1989, pp. 672-680.
the design, reducing cross-talk, instability, and chip 20. H.C. Yang and D.J. Allstot, ' ~ n active-feedback eascode cur-
area. rent source" IEEE Trans. Circuits Syst., vol. CAS-37, no. 5, 1990,
pp. 644-646.

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