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Lecture 4

The document discusses computational circuits design using VHDL. It provides examples of a multiplier circuit and comparator circuit designed using VHDL. It also explains different operators that can be used for comparisons in VHDL like equality, relational, and logical operators.

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12 views

Lecture 4

The document discusses computational circuits design using VHDL. It provides examples of a multiplier circuit and comparator circuit designed using VHDL. It also explains different operators that can be used for comparisons in VHDL like equality, relational, and logical operators.

Uploaded by

beshoymaherr1
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Computational

circuits design
using VHDL
Dr. Fatma ElFouly
Multiplier
Multiplier
Y(0)
r1
“0000” 4
x r5
Y(1) 6
x
“00000” r2 5 r
Mult-4bits
x&’0’
Y(2) 8
r y
r3
“000000” 6
x&”00” r6
Y(3) 8

r4
“0000000” 7
x&”000”
Multiplier
1101 x
*
1010 y x
0000 r1 r
Mult-4bits
11010 r2
000000 r3 y

1101000 r4
10000010 r
ENTITY mul IS
port (x,y:in std_logic_vector (3 downto 0);
r:out std_logic_vector (7 downto 0));
END mul ;
ARCHITECTURE rtl OF mul IS
signal r1: unsigned (3 downto 0);
signal r2: unsigned (4 downto 0);
signal r3,r5: unsigned (5 downto 0);
signal r4: unsigned (6 downto 0);
signal r6,r0: unsigned (7 downto 0);
Multiplier BEGIN
r1 <= unsigned (x) when y(0)='1' else (others =>'0');
r2 <= unsigned (x&'0') when y(1)='1' else (others =>'0');
r3 <= unsigned (x&"00") when y(2)='1' else (others=>'0');
r4 <= unsigned (x&"000") when y(3)='1' else
(others=>'0');
r5 <= r1+ ('0'& r2);
r6 <= r3+ ('0'& r4);
r0 <= r5+ r6;
r <= std_logic_vector (r0);
END rtl;
Comparator
Comparator
A comparator compares two or more inputs using one, or a number of different comparisons. When the given
relationship(s) is true, an output signal is given (logic 0 or logic1). Comparators are only modeled using
the if statement with an else clause and no else-if clauses. Any two data objects are compared using equality
and relational operators in the expression part of the if statement. Only two data objects can be compared at
once, that is, statements like “if (a = b = c)” cannot be used. However, logical operators can be used to
logically test the result of multiple comparisons, for example, “if ((a = b) and (a = c))”. These equality,
relational and logical operators are listed in the following Table.

Operators VHDL
=
/=
Equality & <
Relational <=
>
>=
not
Logical and
or
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity simple_comparator is
port (a, b: in std_logic_vector(5 downto 0);
y: out std_logic);
end entity simple_comparator;
architecture rtl of simple_comparator is
begin
process (a, b)
Comparator begin
if (a = b) then
y <= „1‟;
x
else
y <= „0‟; Comp z
end if;
end process; y
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

Comparator entity multiple_comparator is


port (a, b, c, d, e, f: in std_logic_vector(2 downto 0);
y: out std_logic);
end entity multiple_comparator;
architecture rtl of multiple_comparator is
Signal a_temp, b_temp, c_temp, d_temp, e_temp, f_temp: unsigned(2
Extra parentheses enclosing “c /= downto 0);
d or e >= f” means that either one Begin
of these conditions and “a = b” a_temp<=a;
must be true for the output to be b_temp<=b;
at logic 1. c_temp<= c;
e_temp<=e;
f_temp<=f;
process (a_temp, b_temp, c_temp, d_temp, e_temp, f_temp)
begin
if (a_temp = b_temp and (c_temp /= d_temp or e_temp >=f_temp)) then
y <= „1‟;
else
y <= „0‟;
end if;
end process;
end architecture rtl;

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