Scribd
Upload
14 views

VLSI LAB Record-Format

This document outlines steps to design schematics of logic gates in Mentor Graphics Pyxis tool. It describes creating schematics for CMOS inverter, NAND, NOR, AND, OR, XOR and XNOR gates and performing transient analysis on each to verify functionality.

Uploaded by

srinija pallerla
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
14 views

VLSI LAB Record-Format

This document outlines steps to design schematics of logic gates in Mentor Graphics Pyxis tool. It describes creating schematics for CMOS inverter, NAND, NOR, AND, OR, XOR and XNOR gates and performing transient analysis on each to verify functionality.

Uploaded by

srinija pallerla
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 5

Name: Roll no:

Experiment-1: Logic Gates

Aim: To design schematic of all the logic gates in mentor graphics pyxis tool and observe their
transient and DC analysis.
Tools Used: Mentor Graphics Pyxis Tool
Procedure:
 Login into CentOS Linux Environment by Selecting “Not-listed” and entering Username
as root and password as vnrvjiet.
 Open terminal in the following folder location -> /home/software/mentorgraphics/
 Specify the following commands in the terminal to invoke the pyxis tool of mentor
graphics.

#csh // invoking C shell.


#source /home/software/mentorgraphics/cshrc/cshrc130.cshrc
// specifies the environment variables of the mentor graphics tools.

#dmgr ic & //To invoke the tool.


Step-1: Schematic
 Open library and create cell by right clicking on library-> New-> Schematic
--Enter schematic name and cell name->ok
 Connect the circuit by placing the components in the workspace. The required
components are available as follows
Transistors -> in instances
Wires -> Display
VDD / gnd -> library -> generic library
Vin / Vout ports -> library -> source
 Esc + F2 to fix the component in the working space
 To select any transistor, the steps are as follows:
Instance -> generic13->symbols->(NMOS/PMOS)->Ok
 Select the wire option and connect the required terminals and single click to change the
direction of the wire and double click to fix the wire to terminal.
 Select the port-in, port-out and connect them to input and output terminals respectively.
Note that to change the labels of the input and output ports by selecting and pressing “Q”.
 Place VDD and ground at the required positions by selecting them from library
 Check and save to save the workspace
Step-2: Symbol creation:
 Click on add -> Generate symbol -> select on replace existing and activate symbol.
Name: Roll no:

 Choose the symbol shape and click on OK.


 Check and save and a ‘+’ symbol appears, which means the schematic is added to the
symbol. Else check and rectify the errors.
 Close all the subtabs.
Step-3: Test bench
 Click on New (at top right corner) -> schematic -> select library and give the filename as
<schematic name>_tb.
 A blank screen appears. Right click and select instance
 Select choose symbol -> library-> click OK and place the symbol.
 Connect the input and output ports and change the label names of the ports.
 Place the input sourse (pulse) and make the following changes:
Delay = 0us
Pulse value = 5V
Pulse width to be selected such that it is half of that of time period.
 Connect this pulse at the input port and ground the other terminal of the pulse.
 Place the DC voltage and change the value to 5V. Connect VDD and ground.
Step-4: Simulation:
 In this part, no changes in the schematic are allowed.
 Simulation->New design configuration-> name -> ok -> ok.
 At the right side of the screen -> Analysis -> Disable OP
 Enable DC -> Sweep Type -> select source -> select pointer -> click on V1 pulse. Set
start = 0, stop = 5, step = 0.1
 Enable TRAN ->Start time=0, Stop time = 1000n -> Apply
 Select output -> Task -> Select Plot.
 Select Input wire, output wire and symbol, click on add.
 Select x- -> type: power -> add.
 To observe the waveforms, click on view waves in the palatte area.
WDB Error:
 Go to desktop -> open terminal -> #ifconfig and note the inet ex:10.45.24.169
 Places -> computer -> etc -> hosts -> update IP (the first line)->save
Name: Roll no:

A. CMOS INVERTER
Schematic View:

Test bench:

Transient Analysis:
Name: Roll no:

DC Analysis:

Power Consumption:
Delay:
B. NAND GATE
Schematic View:
Test bench:
Transient Analysis:
C. NOR GATE
Schematic View:
Test bench:
Transient Analysis:
D. AND GATE
Schematic View:
Test bench:
Transient Analysis:
E. OR GATE
Schematic View:
Test bench:
Transient Analysis:
F. XOR GATE
Schematic View:
Test bench:
Transient Analysis:
G. XNOR GATE
Schematic View:
Test bench:
Transient Analysis:
Name: Roll no:

Result: Successfully designed schematic for all CMOS logic gates and their functionality
verified through transient analysis.

You might also like