MIPS PROCESSOR USING CISC ARCHITECTURE

Submitted in partial fulfillment of the requirements for the award of

Bachelor of Engineering / Technology degree in __________________
(Specialization of degree)

by

HARA GOPALA KRISHNA (40130288)

NARESH P (40130705)

DEPARTMENT OF MECHANICAL ENGINEERING

SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING

SATHYABAMA
INSTITUTE OF SCIENCE AND TECHNOLOGY
(DEEMED TO BE UNIVERSITY)
Accredited with Grade “A++” by NAAC

JEPPIAAR NAGAR, RAJIV GANDHI SALAI, CHENNAI - 600 119

 APRIL – 2024

DEPARTMENT OF ____________________________

BONAFIDE CERTIFICATE

This is to certify that this Project Report is the bonafide work of HARA
GOPALA KRISHNA (40130288) who carried out the project entitled
MIPS PROCESSOR USING CISC ARCHITECTURE under my / our
supervision from JANUARY 2024 to APRIL 2024.

Internal Guide External Guide

Dr. A. Sahaya Anselin Nisha

Head of the Department

Dr. T. RAVI

Submitted for Viva voce Examination held on

 Internal Guide External Guide
Dr. A. Sahaya Anselin Nisha
DECLARATION

We of HARA GOPALA KRISHNA (40130288), NARESH P

(40130705), hereby declare that the Project Report entitled “MIPS
PROCESSOR USING CICS ARCHITECTURE” done by us under the
guidance of Dr. A. SAHAYA ANSELIN NISHA Ph. D is submitted.

DATE:
PLACE:

SIGNATURE OF THE CANDIDATE(S)

1.
2.
 ACKNOWLEDGEMENT

I am pleased to acknowledge my sincere thanks to The Board of

Management of Sathyabama Institute of Science and Technology for
their encouragement in doing this project and for completing it
successfully. I am grateful to them.

We convey my/our thanks to Dr. N. M. NANDHITHA, M.E., Ph.D.,

Professor & Dean, School of Electrical and Electronics and Dr. T.
RAVI, Ph.D., Professor & Head, Department of Electronics and
Communication Engineering for providing us necessary support and
details at the right time during the progressive reviews.

I would like to express my sincere and deep sense of gratitude to my

Project Guide Dr. A. SAHAYA ANSELIN NISHA for his/her valuable
guidance, suggestions and constant encouragement paved way for the
successful completion of my project work.

I wish to express my thanks to all Teaching and Non-teaching staff

members of the Department of Electronics and Communication
Engineering who were helpful in many ways for the completion of the
project.
 ABSTRACT

This project aims to design and implement a MIPS (Microprocessor without

Interlocked Pipeline Stages) processor based on the CISC (Complex Instruction
Set Computing) architecture with a focus on the pipeline design. The MIPS
processor is a widely used RISC (Reduced Instruction Set Computing)
architecture, but in this project, we will explore the concept of implementing a
CISC application on an FPGA. The project will begin with a comprehensive review
of the MIPS architecture and its RISC characteristics. The CISC architecture,
known for its complex and multi-step instructions, will then be adapted and
integrated into the original MIPS design. The modification will involve creating new
instruction sets, adding microcode support, and designing a pipeline to handle the
decoding and execution of complex instructions. The processor will be designed
and simulated using a hardware description language (HDL) like Verilog or VHDL.
Several pipeline stages will be considered, such as instruction fetch, decode,
execute, memory access, and write-back. The pipeline design will be optimized for
performance and efficiency, taking into account factors like instruction latency, data
hazards, and control hazards. Once implemented, the MIPS processor's pipeline
will undergo extensive testing and verification to ensure its correctness and
functionality. Testbench programs will be developed to validate the execution of
both RISC and CISC instructions, and corner cases will be examined to assess
the processor's stability and reliability
 CHAPTER - I

1.1 INTRODUCTION

The MIPS (Microprocessor without Interlocked Pipeline Stages) processor is a

renowned example of a RISC (Reduced Instruction Set Computing) architecture,
widely recognized for its efficiency and simplicity in handling mathematical
applications. This project focuses on designing and implementing a MIPS
processor tailored for mathematical computations using Verilog. The CISC
(Complex Instruction Set Computing) architecture of the MIPS processor allows for
intricate and multi-step instructions, making it well-suited for efficient handling of
various mathematical operations. Implementing this CISC architecture in Verilog
enables a detailed exploration of instruction decoding, execution, and data
management in mathematical contexts.

The project's core objective involves designing the MIPS processor's instruction
set for mathematical operations, including addition, subtraction, multiplication, and
division. Each mathematical operation will be implemented as a module in Verilog,
accompanied by the necessary control logic to orchestrate these operations
effectively.

Furthermore, the project will delve into optimizing the MIPS processor specifically
for mathematical applications. This optimization process may encompass
techniques such as pipelining and parallel processing to enhance performance
and efficiency in executing mathematical computations.

In essence, this project aims to provide a thorough understanding of the MIPS

processor's CISC architecture and its Verilog implementation for mathematical
applications. It serves as a practical demonstration of designing and optimizing
processors for specialized tasks, showcasing the versatility and effectiveness of
the MIPS architecture in mathematical computing.
1.2 Background

Overview of the MIPS architecture, including its key components like registers,
ALU, control unit, and memory. Explanation of the MIPS instruction set
architecture (ISA). MIPS Pipeline Description of the MIPS pipeline stages (IF, ID,
EX, MEM, WB). Discussion of pipeline hazards and their solutions in MIPS.
Instruction Set Overview of the MIPS instruction formats (R, I, J). Explanation of
key instructions and their functions (e.g., arithmetic, logical, branch, and memory
instructions). MIPS Applications Common uses of MIPS processors in industry and
academia. Comparison with other architectures in terms of performance, power
efficiency, and application domains.

1.3 Description

The heart of this project lies in the development of a custom instruction set that
seamlessly integrates the core principles of MIPS and CISC. This instruction set
will embody variable-length instructions, complex addressing modes, and an
extensive range of operations, offering the versatility required for modern
computing demands. The processor's core will be meticulously crafted,
encompassing components such as the Arithmetic Logic Unit (ALU), control unit,
registers, and data paths. These elements will be optimized to facilitate the
efficient execution of instructions from our hybrid instruction set. To develop a
novel MIPS developed under CISC hybrid processor that seamlessly combines the
efficiency of the MIPS architecture with the versatility of a CISC instruction set,
catering to both simple and complex computing tasks.

The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture,

developed by MIPS Computer Systems in the early 1980s, stands as a hallmark of
RISC (Reduced Instruction Set Computing) designs. Known for its efficiency and
simplicity, MIPS processors have been widely adopted in various computing
domains, including embedded systems, consumer electronics, and high-
performance computing. The architecture's strength lies in its streamlined
instruction set, featuring a fixed-length, 32-bit format and a reduced number of
instructions, which enables fast decoding and execution. MIPS processors employ
a load-store architecture, restricting memory access to load and store operations
while performing all other computations within registers. With 32 general-purpose
registers, MIPS processors minimize memory access, enhancing performance.
Additionally, the architecture's five-stage pipeline, consisting of instruction fetch,
decode, execute, memory access, and write back stages, allows for high clock
frequencies and instruction throughput. These design principles have made the
MIPS architecture a popular choice for applications requiring a balance of
performance and efficiency."

1.3 Statement of the Problem

The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture, while

renowned for its efficiency and simplicity, faces several challenges that impact its
performance and usability in modern computing environments. One significant
issue is the limited number of general-purpose registers in MIPS processors. With
only 32 registers available, programmers often face constraints when attempting to
optimize code for performance. This limitation can lead to frequent data transfers
between registers and memory, which can degrade performance.

The project aims to address a critical challenge in computer architecture by

attempting to reconcile the distinctive design philosophies of RISC and CISC
within a single CPU. The primary problem lies in the divergence of these two
paradigms: while RISC architectures like MIPS emphasize simplicity and efficiency
through a reduced set of instructions, CISC architectures such as x86 offer a
broad array of complex instructions to accommodate diverse computing tasks.

Another challenge is the handling of complex data types and operations in MIPS.
While the architecture is well-suited for basic arithmetic and logical operations,
more complex operations, such as those involving floating-point numbers or
multimedia data, require additional instructions and processing steps. This can
result in inefficient code execution and reduced performance for applications that
rely heavily on these operations.

Furthermore, the MIPS architecture's branch delay slot, a feature that allows an
instruction to be executed after a branch instruction, can be challenging to
optimize. Programmers must carefully select instructions to fill the delay slot,
which can be a non-trivial task and may not always result in performance
improvements.

This disparity poses a dilemma for CPU designers: should they prioritize the
streamlined execution of simple instructions or the versatility needed to handle
complex workloads efficiently. Overall, these challenges highlight the need for
further enhancements and optimizations in the MIPS architecture to address the
evolving demands of modern computing applications.

1.4 Objective of the project

In this project, we will explore the MIPS processor's architecture and functionality.
We will examine its key components, including the instruction set, registers, and
memory organization. By understanding how the MIPS processor processes
instructions and data, we can write more efficient programs tailored to its
architecture. This knowledge will be applied in various contexts, such as
developing algorithms for mathematical calculations, implementing control flow in
programs, and managing data in memory. Additionally, we will study how the MIPS
processor handles interrupts and exceptions, which are crucial for building reliable
and robust systems. Overall, this project will provide a comprehensive overview of
the MIPS processor and its applications in real-world scenarios.

1.5 Project Scope

The scope of this project includes gaining a deep understanding of the MIPS
processor architecture, its instruction set, and its applications. We will explore how
the MIPS processor executes instructions, manages memory, and handles various
types of data. Additionally, we will study the MIPS pipeline and its stages to
understand how instructions are processed. The project will involve writing and
executing code on a MIPS simulator or emulator to gain practical experience with
the architecture.

In the future, this project can be expanded to include advanced topics such as
optimizing code for the MIPS architecture, implementing complex algorithms, and
exploring the use of the MIPS processor in embedded systems and real-time
applications. Additionally, further research can be conducted to compare the MIPS
architecture with other architectures and analyse its strengths and weaknesses.
This project can serve as a foundation for exploring advanced concepts in
computer architecture and processor design.

CHAPTER -2

2.1 LITERATURE SURVEY

For getting an overview about the previous work related to this project have
reviewed many papers and summary of that papers are as follows.

2.1.1 Overview MIPS Architecture:

MIPS (Microprocessor without Interlocked Pipeline Stages) is a RISC (Reduced
Instruction Set Computing) architecture developed by MIPS Computer Systems. It
emphasizes simplicity and efficiency in instruction execution. CISC architectures,
such as x86, traditionally feature complex instructions that can perform multiple
operations, while RISC architectures focus on simpler, single-cycle instructions.
Overall, the MIPS architecture has been successful due to its balance of simplicity,
efficiency, and performance, making it a popular choice for a wide range of
applications. The MIPS architecture has evolved over the years, with several
versions and extensions introduced to improve performance and add new
features. Early versions of MIPS, such as MIPS I and MIPS II, focused on
simplicity and efficiency, with a small set of basic instructions. Later versions, such
as MIPS III and MIPS IV, introduced features like SIMD (Single Instruction,
Multiple Data) instructions for parallel processing, multimedia instructions for
handling multimedia data types, and more complex addressing modes for
improved memory access.

Overview of the types of applications and workloads that benefit from the features
of CISC architectures, such as applications requiring complex data manipulation or
memory access patterns. Case studies or examples of how CISC architectures
have been used in real-world applications.

2.1.2 Evolution of MIPS towards CISC:

The early MIPS architecture, like MIPS I, was purely RISC, with a small set of
simple instructions. This introduction of CISC Features of later versions, such as
MIPS IV and MIPS32/64, the architecture introduced CISC-like features, including
multimedia instructions, complex addressing modes, and instructions for handling
exceptions and interrupts. The inclusion of CISC features in MIPS was driven by
the need to improve performance for certain types of applications, such as
multimedia processing, without sacrificing the simplicity and efficiency of RISC.
Discussion of the challenges faced by traditional CISC architectures, such as
increasing complexity and the need to balance compatibility with performance.

Speculation on future directions for CISC architectures, including potential

improvements and innovations to address these challenges.

The initial MIPS architecture, known as MIPS I, was a pure RISC design with a
focus on simplicity and efficiency. It featured a small set of instructions that could
be executed in a single cycle, a load-store architecture, and a fixed instruction
format.

MIPS, I adhered to the key principles of RISC, including a large number of

general-purpose registers, a simple and regular instruction set, and a focus on
optimizing common case performance.

2.1.3 Establishing the Needs:

Establishing the need is a crucial step in any project or research endeavour. It
involves clearly defining the problem or opportunity that the project aims to
address. This step helps to justify why the project is necessary and sets the stage
for the rest of the work. In the context of your report on the MIPS processor using
CISC architecture, establishing the need would involve:

The initial step of defining the need is crucial. During this process, the problem or
opportunity that the project aims to address is clearly outlined. In the context of
your report on the MIPS processor using CISC architecture, several key aspects
are considered:

Identification of Challenges and Limitations in the MIPS processor with CISC

architecture seeks to overcome specific challenges faced by existing processors
or architectures. By identifying these challenges, the necessity for an alternative
approach becomes evident.

Emphasis on Benefits and Advantages of this potential benefits offered by the

MIPS processor with CISC architecture are highlighted. These advantages may
include improved performance, an enhanced instruction set, or better compatibility
with certain applications.

Presentation of Supporting Evidence are provided to reinforce the importance of

addressing these challenges. Demonstrating real-world scenarios where the MIPS
processor excels strengthens the case.

Alignment with Broader Goals of the project is connected to broader objectives,

such as efficiency improvement, cost reduction, or enabling new functionalities.
Strategic alignment underscores the significance of the project.

In summary, effectively establishing the need sets the stage for a compelling
project report, emphasizing its value and relevance. This foundational step
ensures that subsequent work is purposeful and impactful.

2.2.4 Demonstrating Familiarity with Existing Work

Many recent processor extensions focus on improving the handling of 8- and 16-
bit integers. These data types are prevalent in audio, video, and graphics
applications. However, traditional Arithmetic Logic Units (ALUs) can only process
one integer at a time. The challenge arises when modern processors implement
64-bit data paths, leaving a significant portion of this path unused when dealing
with small integers. To address this inefficiency, a technique involves packing
multiple small integers (four or eight) into a single 64-bit register. By operating on
them in parallel using a Single Instruction, Multiple Data (SIMD) approach,
throughput significantly increases.

Interestingly, MIPS recognized a similar opportunity in the floating-point domain,

yet no other vendor has capitalized on it. While modern microprocessors are
optimized for double-precision floating-point data (utilizing a 64-bit data path in the
Floating-Point Unit), single-precision floating-point data remains common in
applications like 3D graphics and signal processing. Unfortunately, these
applications waste half of the available FP data path. Applying the same SIMD
approach to single-precision data can effectively double throughput.
2.2 EXISTING METHODOLOGY
The existing methodology for designing MIPS processors typically
involves several key steps and methodologies. Here's an overview of the process,
focusing on the design and implementation aspects:

2.2.1 Specification and Architecture Design: Define the high-level architecture

and instruction set architecture (ISA) for the MIPS processor, including features
such as the number of registers, instruction formats, and supported operations.
Determine the target application and performance requirements to guide the
design decisions. Develop the microarchitecture of the processor, including the
pipeline stages, instruction fetch and decode units, execution units, and memory
hierarchy. Choose appropriate techniques for pipelining, instruction scheduling,
and data forwarding to optimize performance.

2.2.2 RTL Design: Use a hardware description language (HDL) such as Verilog or
VHDL to implement the processor's microarchitecture at the register-transfer level
(RTL). Develop modules for each component of the processor, such as the ALU,
register file, control unit, and memory interface. Use simulation tools to verify the
correctness of the RTL design and ensure that it meets the architectural
specifications. Write testbenches and test cases to validate the processor's
behaviour under different conditions and corner cases.

2.2.3 Synthesis and Optimization: Use synthesis tools to translate the RTL
design into a gate-level netlist that can be implemented in silicon. Perform
optimization techniques such as technology mapping, logic synthesis, and timing
analysis to improve performance, area, and power consumption. Perform physical
design tasks such as floor planning, placement, routing, and clock tree synthesis
to convert the gate-level netlist into a layout that can be fabricated. Address issues
such as timing closure, signal integrity, and power distribution to ensure the design
meets the performance targets.

2.2.4 Algorithm for MIPS Architecture Development

An algorithm for a MIPS processor with a CISC architecture involves

outlining the key steps involved in processing instructions and managing the
complexity of CISC-like features. Here's a general algorithm that captures the
essence of such a design,

Fetch Stage: Fetch the next instruction from memory. Decode the instruction to
determine its type (e.g., arithmetic, load/store, control transfer). Identify the
addressing mode and operands required for the instruction.

Execute Stage: Based on the instruction type, perform the necessary operation.
For CISC-like instructions, check for complex addressing modes and handle them
accordingly. Execute any necessary microcode or complex instruction sequences.

Memory Stage: If the instruction is a load or store, perform the memory access.
Handle any memory management tasks, such as virtual to physical address
translation.

Write-back Stage: Write the result of the instruction back to the register file.
Update any status flags or special-purpose registers as needed.

Exception and Interrupt Handling: Check for any exceptions or interrupts that
occurred during instruction execution. If an exception or interrupt occurred, handle
it appropriately (e.g., by jumping to the exception handler).

Complex Instruction Handling: For CISC-like instructions, decode the instruction

further to determine the specific operations to be performed. Execute the required
operations in sequence, possibly using microcode or specialized hardware units.
Manage control flow instructions, such as branches and jumps, to ensure correct
program execution. Update the program counter (PC) based on the outcome of
branch instructions.

Overall Control: Ensure that the processor maintains correct state and behaviour
throughout the instruction execution process. Handle any pipeline hazards or
dependencies to ensure correct instruction ordering and execution.
 CHAPTER – 3

3.1 AIM AND SCOPE OF THE PROJECT

The main aim of this MIPS Architecture is to achieve an efficient timing
for all the mathematical operations of both arithmetic and logical instructions.

3.1.1 AIM
The aim of designing a 32-bit MIPS processor with a CISC architecture is to
combine the efficiency and simplicity of a RISC-based design with the additional
functionality and flexibility provided by CISC-like features. The processor is
intended to execute complex instructions efficiently while maintaining compatibility
with existing MIPS software and hardware.

At its core, the processor features a 32-bit instruction set architecture (ISA) that
includes a variety of complex instructions for tasks such as multimedia processing,
memory management, and control flow manipulation. The ISA is designed to be
compatible with the MIPS IV architecture, allowing software written for MIPS IV to
run on the new processor without modification.

The processor's pipeline architecture consists of several stages, including

instruction fetch, decode, execute, memory access, and write-back. Each stage is
implemented using a combination of registers and latches to store intermediate
results and control signals. The pipeline is designed to minimize stalls and
hazards, ensuring that instructions are executed efficiently and in the correct order.

Key components of the processor include a register file containing 32 general-

purpose registers, as well as special-purpose registers for tasks such as managing
exceptions and interrupts. The processor also includes a variety of hardware units
for tasks such as address calculation, data manipulation, and memory access.

Overall, the aim of the processor is to provide a balance between performance

and complexity, allowing for efficient execution of complex instructions while
maintaining the simplicity and elegance of the MIPS architecture. By incorporating
CISC-like features into the MIPS architecture, the processor aims to expand the
range of applications that can be efficiently executed on MIPS-based systems,
making it a versatile and powerful platform for a wide range of computing tasks.

3.1.2 SCOPE OF THIS ARCHITECTURE

The scope of the MIPS processor with a CISC architecture extends to various
applications and scenarios where its enhanced features and capabilities can be
leveraged. The processor's design, which combines the simplicity of RISC with the
complexity of CISC, makes it suitable for a wide range of computing tasks, from
embedded systems to high-performance computing environments. Here's an
overview of its scope in the context.

Another key feature of the MIPS processor with a CISC architecture is its flexible
instruction encoding. Unlike traditional RISC architectures, which often have fixed-
length instructions, the MIPS CISC architecture allows for variable-length
instructions. This allows complex instructions to be encoded more efficiently,
reducing the overall size of the instruction cache and improving instruction fetch
bandwidth. Additionally, the flexible encoding allows for more diverse instruction
formats, accommodating a wider range of operations and addressing modes. This
flexibility in instruction encoding contributes to the processor's ability to efficiently
execute complex programs with diverse instruction requirements.

In addition to instructions for complex operations, the MIPS processor with a CISC
architecture includes enhanced data processing instructions. These instructions
can operate on larger data types or perform more complex arithmetic operations
than traditional RISC instructions. This allows for more efficient processing of data-
intensive tasks, such as scientific computing or signal processing, where high
precision and performance are required. By providing these enhanced data
processing capabilities, the processor can handle a wider range of applications
with improved efficiency.

The CISC architecture of the MIPS processor also includes enhancements to

control flow instructions, such as branches and jumps. These instructions are
optimized for common programming constructs, allowing for more efficient
implementation of loops, conditionals, and function calls. The processor includes
hardware support for branch prediction and speculation, reducing the impact of
branch penalties and improving overall performance. This makes the processor
well-suited for applications with complex control flow requirements, such as real-
time systems and high-performance computing.

One of the key features of the MIPS processor with a CISC architecture is its
support for a variety of addressing modes. These modes allow for flexible and
efficient memory access, including indexed, and indirect addressing modes. This
flexibility enables the processor to access memory in ways that are more natural
for certain types of operations, such as array processing and data structure
traversal. By providing these advanced addressing modes, the processor can
execute a wider range of applications more efficiently.

High-Performance Computing in the realm of high-performance computing,

clusters of MIPS processors can be used for scientific simulations, data analysis,
and other compute-intensive tasks. The processor's ability to handle complex
instructions and its scalability make it suitable for these demanding applications.
Finally, the MIPS processor is used in educational settings and research
institutions for teaching and research purposes. Its well-documented architecture
and availability of development tools make it a valuable platform for learning about
computer architecture and conducting research in the field.

The MIPS processor is also used in automotive systems, where it can be found in
infotainment systems, driver assistance systems, and other vehicle subsystems.
Its real-time performance and support for multimedia processing make it a good fit
for these applications.

In industrial automation, the MIPS processor can be used in control systems,

robotics, and other automation applications. Its reliability, real-time performance,
and support for complex operations make it suitable for these demanding
environments. MIPS processors are also used in security systems, such as
surveillance cameras, access control systems, and fire detection systems. Their
performance, efficiency, and support for encryption algorithms make them ideal for
these applications.
The MIPS processor is commonly used in networking equipment such as routers,
switches, and access points. Its performance and support for advanced
networking protocols make it ideal for these applications. While not as prevalent as
other architectures in the mobile market, the MIPS processor can be found in
some mobile devices, particularly in emerging markets. Its power efficiency and
performance make it a viable option for budget smartphones and tablets.

CORE OBJECTIVE

The main objective of this project is to design and implement a pipelined MIPS
processor with a CISC architecture that combines the efficiency of RISC with the
flexibility of CISC. The processor aims to improve performance for complex
operations such as multimedia processing, cryptography, and memory
management, while maintaining compatibility with existing MIPS software and
hardware.

The pipelined architecture of the processor is crucial for achieving high

performance. It breaks down the execution of instructions into multiple stages,
allowing multiple instructions to be processed simultaneously. The pipeline
consists of five stages: instruction fetch, instruction decode, execute, memory
access, and write-back.

In the instruction fetch stage, the processor retrieves the next instruction from
memory. The instruction is then decoded in the instruction decode stage, where
the processor determines the operation to be performed and identifies the
operands. The execute stage carries out the operation specified by the instruction.
This stage may involve complex calculations or data manipulation, depending on
the type of instruction.

The memory access stage is responsible for accessing memory if the instruction
involves a memory operation, such as a load or store. Finally, in the write-back
stage, the results of the instruction are written back to the register file.

By dividing the instruction execution process into these stages and allowing
multiple instructions to be processed concurrently, the pipelined architecture
improves the overall throughput of the processor.

| Instruction | Instruction Fetch } -- Instruction fetching state

 | Cache/ Memory | Stage

+-----------------+

+----------------+

+-----------------+

| Instruction | Instruction Decode } --- Decoding State

| Register File | Stage

+-----------------+

+-----------------+

| ALU/ Functional | Execute Stage } --- Execution State

| Units |

+-----------------+

+-----------------+

| Data Cache/ | Memory Access

| Memory | Stage

+-----------------+

|
 v

+-----------------+

| Register File | Write-Back

| | Stage

+-----------------+

Chapter -4

4.1 EXPERIMENTAL METHODOLOGY AND ALGORITHM

4.1.1Three Key CISC-like Features in MIPS:

Multimedia Instructions: MIPS introduced instructions for SIMD (Single Instruction,
Multiple Data) operations, allowing for parallel processing of data.

Complex Addressing Modes: Later versions of MIPS added support for more
complex addressing modes, to improve flexibility in memory access.

Exception and Interrupt Handling: CISC-like features were added to handle

exceptions and interrupts more efficiently, including special instructions and
registers for these purposes.

MIPS II-IV: As the MIPS architecture evolved, starting with MIPS II and continuing
through MIPS III and MIPS IV, CISC-like features began to be introduced.

Multimedia Instructions: One of the key additions was the inclusion of multimedia
instructions, such as SIMD (Single Instruction, Multiple Data) instructions, which
allowed for the parallel processing of data commonly found in multimedia
applications.

2.1.4 Comparison with Traditional CISC Architectures:

The evolution of the MIPS architecture continued with the introduction of the
MIPS32 and MIPS64 architectures, which further refined the CISC-like features
introduced in earlier versions. Efforts were made to optimize the performance of
these features and mitigate the impact of increased complexity on overall
processor performance.
Studies have shown that the addition of CISC-like features in MIPS can improve
performance for certain workloads, such as multimedia applications, compared to
pure RISC designs. However, the inclusion of CISC features also introduces
complexity, which can impact the overall performance and efficiency of the
architecture in certain scenarios. In conclusion, the evolution of the MIPS
architecture towards a CISC design involved the incorporation of features
traditionally associated with CISC architectures, such as multimedia instructions,
complex addressing modes, and improved exception and interrupt handling. This
evolution was driven by the need to improve performance for certain types of
applications while maintaining compatibility with compatibility with existing
software and hardware.

Overview of the MIPS Architecture

The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture is a

well-known example of a Reduced Instruction Set Computer (RISC) architecture.
Here are the key components and concepts:

1. Instruction Set Architecture (ISA):

o The ISA defines the interface through which software interacts with
hardware.
o Compilers translate high-level source code (e.g., C++, Go) into the
ISA for a target processor.
o Example ISAs include:
 MIPS: Commonly used in educational settings and embedded
systems.
 ARM: Popular in mobile devices.
 x86: Widely used in desktops and laptops.
2. Basic Instruction Types:
o Arithmetic/Bitwise Logic: Includes operations like addition, left-
shift, bitwise negation, and XOR.
o Data Transfers: Move data between registers and memory.
o Control Flow: Manage program execution (e.g., unconditional
jumps, conditional branches, function invocations).
 3. RISC vs. CISC:
o RISC (Reduced Instruction Set Computer):
 Emphasizes simplicity and regularity.
 Each instruction performs a specific task.
 Fixed-length instructions for efficient decoding.
 MIPS is a classic RISC ISA.
o CISC (Complex Instruction Set Computer):
 Contains a large number of complex instructions.
 Single instructions can perform multiple tasks.
 Variable-length instructions.
 x86 is a well-known CISC ISA.
4. Registers vs. RAM:
o Registers:
 Extremely fast for ALU access (0.3 ns).
 Limited in number (a few dozen 32-bit or 64-bit registers).
o RAM (Memory):
 Much larger (GBs of RAM).
 Slower access (around 120 ns).
5. Floating-Point Optimization:
o While modern processors optimize for double-precision floating-point
data, single-precision data remains common in applications like 3D
graphics and signal processing.
o Utilizing a SIMD approach (similar to handling small integers), we
can double throughput on single-precision data.

In summary, understanding the MIPS architecture involves grasping its ISA,

instruction types, and the trade-offs between RISC and CISC designs. By
leveraging these concepts, we can design efficient processors and enhance
performance12.

MIPS CISC Architecture: The MIPS architecture, developed by MIPS Computer

Systems, is a prominent. CISC processors prioritize simplicity, efficiency, and
streamlined execution. Here are some essential aspects of the MIPS CISC
architecture:

 Instruction Set: MIPS instructions are simple, fixed-sized,

and operate on registers. The instruction set includes basic
operations like arithmetic, logical, load/store, and control flow
instructions.
 Load/Store Architecture: In MIPS, memory access occurs
only through load and store instructions. Data is loaded from
memory into registers and vice versa.
 Register File: MIPS processors typically have 32 general-
purpose registers (R0 to R31), which are used for
computation and data storage.
 Pipeline: MIPS processors employ a pipelined architecture,
dividing instruction execution into stages (fetch, decode,
execute, memory access, and write-back). Pipelining
improves throughput but requires careful handling of hazards
(e.g., data hazards, control hazards).
 Branch Delay Slot: MIPS branch instructions have a one-
instruction delay slot, where the instruction following the
branch is always executed regardless of the branch outcome.
 Floating-Point Unit (FPU): Some MIPS processors include
an FPU for floating-point arithmetic.