CE222 - Digital Integrated Circuit Design

Nguyen Tran Son

[email protected]

Jan 17, 2023

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Basic CMOS Circuits & Layout

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 Prefixes Used for Large or Small Physical Quantities

Table: Prefixes Used for Large or Small Physical Quantities

Prefix Abbreviation Scale Factor

giga- G 109
meg- or mega- M 106
kilo- k 103
milli- m 10−3
micro- µ 10−6
nano- n 10−9
pico- p 10−12
femto- f 10−15

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Outline

1 CMOS Circuit Structure

2 Basic CMOS Gate

3 Physical Structure

4 Layout Std Cell

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 CMOS Circuit Structure

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NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its

gate signal.
NMOS switch closes when switch control input is high.

NMOS transistor pass a "strong" 0 and a "weak" 1

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 PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low.

PMOS transistor pass a "strong" 1 and a "weak" 0

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Signal Strength

Transistors can be used as switches

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 Complementary CMOS Logic Style

DeMorgan’s Theorem’s
A + B = Ā.B̄

A.B = Ā + B̄

The complementary gate is inverting.

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Example: NAND2

PDN: G = AB → Conduction to GND

PUN: S = Ā + B̄ = A.B → Conduction to VDD

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 Example: NOR2

PDN: G = A + B → Conduction to GND

PUN: S = ĀB̄ = A + B → Conduction to VDD

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Complex CMOS Gate

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Structure of a Complex Gate

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Example: O3AI

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 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well

2: Circuits & Layout CMOS VLSI Design 4th Ed. 23

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Tristates
❑ Tristate buffer produces Z when not enabled

EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1

2: Circuits & Layout CMOS VLSI Design 4th Ed. 24

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 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

2: Circuits & Layout CMOS VLSI Design 4th Ed. 25

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Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output

2: Circuits & Layout CMOS VLSI Design 4th Ed. 26

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 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1

2: Circuits & Layout CMOS VLSI Design 4th Ed. 27

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Gate-Level Mux Design

❑
❑ How many transistors are needed? 20

2: Circuits & Layout CMOS VLSI Design 4th Ed. 28

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 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors

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Inverting Mux
❑ Inverting multiplexer
– Use compound AOI22: Fig 1
– Or pair of tristate inverters: Fig 2
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

Fig 1 Fig 2
2: Circuits & Layout CMOS VLSI Design 4th Ed. 30

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 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates

2: Circuits & Layout CMOS VLSI Design 4th Ed. 31

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Structure and Symbol of MOSFET

This device is symmetric, so either of the n+ regions can

be source or drain.

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State of the Art MOSFET Structure: NMOS

Source/Drain: n+ (n - Diffusion)
The gate is formed by polysilicon, and the insulator
by Silicon dioxide.

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State of the Art MOSFET Structure: PMOS

Source/Drain: p+ (p - Diffusion)

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State of the Art MOSFET Structure: CMOS

Combine NMOS - PMOS

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MOSFET Symbol

D: Drain
G: Gate
S: Source
B: Bulk/Body

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Cell Design

Standard Cells
Used for general purpose logic.
Can be synthesized (automatically generated from
high-level descriptions).
Same height, varying width, to fit different logic
functions.
Datapath Cells
Used for regular, structured designs (e.g., arithmetic
circuits).
Includes some wiring in the cell, to reduce routing
overhead.
Fixed height and width, to ensure regularity and
predictability of the layout.

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Standard Cell Layout Methodology

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Standard Cell

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Standard Cell

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 Stick Diagrams

A Stick diagram is a simple graphical representation of a

circuit layout. It is a type of layout design that uses
stick-like symbols to represent the various components of
a circuit, such as gates, transistors, and interconnects.

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Euler Path

An Euler path is a path that visits every edge exactly

once in a graph.
It make sure the connections between components
can be made without any wires crossing over each
other.

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Multi-Fingered Transistors
Less diffusion capacitance
Better control over channel width
Improved current handling capability, better for
EMIR

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Questions?

Thank you !

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