Power Supply Design Seminar

Practical Considerations in High

Performance MOSFET, IGBT, and
MCT Gate Drive Circuits
Topic Categories:
Design Reviews – Functional Circuit Blocks
Driving Power MOSFETs

Reproduced from
1991 Unitrode Power Supply Design Seminar
SEM800, Topic 6
TI Literature Number: SLUP097

© 1991 Unitrode Corporation

© 2011 Texas Instruments Incorporated

Product Update:
This topic references the UC3708. While this TI device
may still be available, the later-generation UCC27323 may
offer performance enhancements.

Power Seminar topics and online power-

training modules are available at:
power.ti.com/seminars
 Practical Considerations in High Performance
MOSFET, IGBT, and MCT Gate Drive Circuits
Bill Andreycak

Introduction: determine the effective gate capacitance and driver

The switchmode power supply industry trend requirements for optimal performance in a clamped
towards higher conversion frequencies is motivated inductive load (Buck derived) application.
by the desire to achieve higher power densities. As Total Gate Charge (QG): First, a typical high
switching frequencies push towards and beyond power MOSFET "Gate Charge versus Gate-ta-
1 MHz. MOSFET transition periods can become a Source Voltage" curve will be examined. An
significant portion of the total switching period. IRFP460 device has been selected and this curve is
Losses associated with voltage and current overlap applicable to most other MOSFET devices by
during switching transitions not only degrade power adjusting the gate charge numbers accordingly. Both
supply efficiency. but warrant consideration from tum-on and tum-off transitions are shown with the
both a thermal and packaging standpoint. Although respective drain currents and drain-to-source
brief. each of the MOSFET switching transitions voltages.
can be further reduced if driven from a high speed.
high current totem-pole driver. Ogs Ogd
Inadequate gate drive is generally the resuU of
Vgs ~
underestimating the effective load of a power
MOSFET upon its driver.
Vgs (th)
General Applications of Power
MOSFETs
Effective Gate Capacitance: MOSFET input
Id
capacitance (CISS) is frequently misused as the load
represented by a power MOSFET to the gate driver
IC. In reality, the effective input capacitance of a
MOSFET (CEFF) is much higher, and must be
Fig 1. - Turn-On Waveforms
derived from the manufacturers' published total gate
Gate voltage vs. time
charge (00) information. Even the specified
maximum values of the gate charge parameter do Interval to-U: The time required to bring the
not accurately reflect the driver's instantaneous gate voltage from zero to its threshold VGS(th) can
loads during a given switching transition. be expressed as a delay time. Both the voltage
Fortunately, FET manufacturers provide a curve for across the switching device and current through it
the gate-ta-source voltage (VGs) versus total gate are unaffected during this interval.
charge in their data sheets. This will be segmented
Interval U-U: This period starts at time tI when
into four time intervals of interest per switching
The gate voltage has reached VGS(th) and drain
transition. Each of these will be analyzed to
current begins to flow. Current continues to rise

Texas Instruments 1 SLUP097

until essentially reaching its fmal value at time 12. while the drain current continues to flow and equals
While this occurred, the gate to source voltage had I(on). This lossy transition ends at time 12.
also been increasing. The drain-to-source voltage Interval tz-ll: Once the Miller charge is
remains unchanged at VDS(off). Power in the completely removed, the gate voltage is reduced
MOSFET is wasted by the simultaneous overlap of from the plateau to the threshold voltage causing the
voltage and current. drain current to fall from ION to zero. Transition
Interval tz-13: Beginning at time 12 the drain-to- power loss ends at time tI when the gate threshold
source voltage starts to fall which introduces the is crossed.
"Miller" capacitance effects (CGo) from the drain to Interval ll-to: This brief period is of little
the MOSFET gate. The result is the noticeable interest in the turn-off sequence since the device is
plateau in the gate voltage waveform from time 12 off at time tt.
until 13 while a charge equal to QGo is admitted. It
is here that most drive circuits are taxed to their Qgs Qgd
limits. The interval concludes at time 13 when the
drain voltage approaches its minimum. Vgs
'------;..
-I" ~~
Interval 13-t4: During this final interval of
interest the gate voltage rises from the plateau of Vgs (th)
the prior region up to its final drive voltage. This
increasing gate voltage decreases RoS(on), the
MOSFET drain-to-source resistance. Bringing the
gate voltage above 10 - 12V, however, has little
effect on further reducing RoS(on).

SUMMARY OF TURN-ON WAVEFORMS

AND DRIVER LIMITATIONS
Fig 2. Turn Off Waveforms
Intrvl VGS~) 10(1) VOS~) Driver Limitation
to-tl O-threshold 0 VOS(off) Slew rate (dv/dt)
t1-l2 thrs-plateau rising VOS(off) Slew rate (dv/dt) SUMMARY OF TURN-OFF WAVEFORMS
t2-t3 V(plateau) ION(de) falling Peak current I(max) AND DRIVER LIMITATIONS
t3-t4 rising ION(de) ION-ROS(I) Peak I, dv/dt Intrvl VGS~) 10(1) VOS(I) Driver Limitation
t4-t3 falling ION(de) ION-Ros(l) Peak I and dv/dt
The intervals during tum-off are basically the t3-\2 V(plateau) 1000de) falling Peak Current I(max)
same as those described for tum-on, however the \2-" Vplat-thrsh falling VOS(off) Slew rate (dv/dt)
sequence and corresponding waveforms are t1-l0 thrsh-o 0 VOS(off) Slew rate (dv/dt)
reversed:
Interval t4-13: The beginning of the tum-off FET Transition Power Loss: During each of the
cycle can be described as a delay from the final FET tum-on and tum-off sequences power is lost
drive voltage (VGS(on» to the plateau region. Both due to the simultaneous overlap of drain-source
the drain voltage and current waveforms remain voltage and drain current. Since FET voltage and
unchanged while the effective resistance (RoS(on» current are both externally controlled by the
increases as the gate voltage decreases. application, the driver IC can reduce power loss by
making the transition times as brief as possible.
Interval 13-t2: Once the plateau is reached at Minimizing switching losses simply requires a
time 13, the gate voltage remains constant until time competent driver IC, one able to provide high peak
12. Gate charge due to the Miller effect is being currents with high voltage slew rates.
removed, an amount equal to QGo. The drain
voltage rises to its off state amplitUde, VDS(off),

Texas Instruments 2 SLUP097

 A review of the prior transition waveforms determined by dividing the required gate charge
indicates that power is lost between times u to 13. (00) by the gate voltage during a given interval.
While 12 serves as the pivot point for which Likewise, the current necessary to force a transition
waveform is rising or falling, the equations show within a specified time is obtained by dividing the
that t2 is irrelevant in the power loss equation. For gate charge by the desired time.
the purpose of brevity, the waveform of interest can Effective CGS = L\QG / L\VGS
be approximated as a triangle while the other
waveform is constant. The tl to 13 interval can then
Required IG = L\QG I ITRANSITION
be defmed as the net transition time, ITRANSITION, A "large" industry standard FET, the IRFP460
with a conversion period of !PERIOD. device, will be used for an example of the actual
During the two intervals from t1 to 13: gate charge requirements over several intervals.
ION V ds(o/l} (t2 -( 1)
First, the effective capacitance over the typical gate
PLOSS = -....,.............;.........;-- drive voltage of 0 - 10V will be determined. Typical
2 tpERIOD gate to source voltage verses gate charge is shown
V ds(o/l} ION (13 -( )
in the figure below.
2
P wss = --'%"----
2 tpERIOD
As VGS is varied from 0 to 10 Volts:
Effective C =L\Oo /L\VGS = 120nC /lOV = 12nF
Combining the two equations with tTRANSITION =
Notice that the effective load of 12 nanoFarads is
tHI results in a net loss of :
approximately three times greater than the FET
IONVds(o/l} (1 -t
2 1 ) input capacitance, Ciss, specified as 4.1nF.
P wss =-.....,............;.........;--
2 tpERIOD The average, or effective capacitance can also be
Since these losses are incurred twice per cycle, somewhat misleading if used as the driver's load.
first at turn-on and then again at tum-off, the net This can best be demonstrated by the plateau in the
result is a doubling of the power loss. gate voltage waveform where the voltage is virtually
constant yet charge is induced. This indicates that
V ds(o/l} ION t(trans)
PLOSS = - -tpERIOD
---- the gate capacitance during this period is extremely
high.
This relationship displays the need for fast Gate charge, which dictates the driver
transitions at any switching frequency, and is of requirements and obtainable transition times will be
significant concern at one megaHertz. Minimization determined over the three regions of interest.
of the FET transition power loss can be achieved From to to 12:
with high current drivers. L\Oos =20nC; L\ VGS = 6V
Gate Charge: Each transition interval has an Here, the effective capacitance can be calculated
associated gate charge which can be derived from as 2OnC/6V or 3.3nF, slightly lower than CIss.
the FET manufacturers data sheets. Since there are During this period the driver IC is generally slew
three basic shapes to the VGS curve, the interval rate limited, unable to provide a high enough dv/dt
from to to tl can be lumped together with tl to 12. to become peak current limited. The exact process
For most large FET geometries, the amount of used by the manufacturer and the resulting transistor
charge in the to-u span is negligible anyway. This speeds can be approaching their maximums.
simplification allows an easy calculation of the During the plateau region from 12 to 13:
effective gate capacitance for each interval along L\Ooo =0; L\VGS is 0 (approx)
with quantifying the peak current required to
traverse in a given amount of time. The effective capacitance is difficult to calculate
Charge can be represented as the product of given these conditions, but is quite substantial. Of
capacitance multiplied by voltage, or current more importance is the peak driver current which
multiplied by time. The effective gate capacitance is governs the duration of the "Miller" plateau region

Texas Instruments 3 SLUP097

and fall time of the drain voltage. Since charge also Table 1· GATE POWER (mW) vs. SWITCHING
equals current multiplied by time (Q=I1:), the FREQUENCY AND FET SIZE
necessary gate current can be determined based on SWITCHING FREQUENCY(KHZ)
a desired drain fall time. Likewise, the achievable 50 100 150 200 250 500 750 1M-lZ
drain voltage fall time can be determined based
Size 1 10 18 28 36 46 90 136 180
upon peak driver current. Size 2 16 30 46 60 76 153 226 300
IG(max) =ilQGD(plateau) / t(Vds faJI) Size 3 28 54 82 108 136 275 406 504
Size 4 48 96 144 192 240 480 720 960
t(Vds faJI) = ilQGD(plateau) / I(max) driver
Size 5 100 200 300 400 550 1.0W 1.5W 2W
The fmal area of interest is from 13 to t4 where Size 6 144 288 432 576 720 1.4W 2W >2W
ilQg equals 40nC and the gate voltage rises by
about 4 Yolts. Here the interval capacitance of 10nF
approaches that of the average value of 12nF for the Table 2· DC SUPPLY CURRENT (mA) vs. SWITCHING
FREQUENCY AND FET SIZE
entire tum-on or turn-off interval.
In many applications using large FETs, the peak SWITCHING FREQUENCY (KHZ)
driver current dominates as the limiting factor in 50 100 150 200 250 500 750 1MHZ
obtaining rapid MOSFET transition speeds. Size 1 1 1 2 4 5 6 10 12
Size 2 1 2 4 5 6 10 16 20
Gate Drive Power Considerations: Perhaps the Size 3 2 4 6 8 10 16 26 36
most popular misconception in the power supply Size 4 4 8 10 12 16 32 48 64
Size 5 8 14 20 26 32 66 100 130
industry is that a FET gates require NO power from
Size 6 10 20 28 38 48 96 144 190
the auxiliary supply - that both turn-on and turn-off
are miraculously power free. Another fallacy is that
the driver consumes all the measured supply current,
Icc, and none of it is used to transition the gates.
Driver Considerations
As previously demonstrated, the ideal MOSFET
Obviously, both of these statements are false.
In reality, the power required by the gate itself gate drive IC is a unique blend of both high speed
can be quite substantial in high frequency switching and high peak current capability. Initially,
applications. Calculation of this begins by listing the the high speed is required to bring the gate voltage
specified total gate charge for the FET device, QG. from zero to the plateau, but the current is low.
The gate power utilized in charging and discharging Once the plateau is intersected, the driver voltage is
a capacitor at frequency "F" is: fairly constant, and the IC must switch modes.
Instantly, the driver current snaps to its maximum
PCAP = C·Y2 • F as charge is injected to overcome the FET's Miller
Substituting the gate charge for capacitance effects. Finally, a combination of both high slew
multiplied by voltage (Q=C ·Y) in this equation rate and high current is needed to complete the gate
results in : drive cycle.
PGATE =QG·Y· F At tum-off this sequence is reversed, first
demanding both high slew rate and high current
Typical gate power required versus FET size and simultaneously. This is followed by the plateau
switching frequency is tabulated in Table 1. The region which is limited only by the maximum driver
corresponding driver input current at a nominal 12 current. Finally, there is high speed discharge of the
Yolt bias is shown in Table 2. gate to zero Yolts. Optimization of a driver for this
type of application can be difficult. In general, the
MOSFET driver IC output stage is designed to
switch as fast as the manufacturer's process will
allow.

Texas Instruments 4 SLUP097

 Cross Conduction: There are numerous tradeoffs Table 3 - MOSFET DRIVER Ie
involved in the design of these drivers beyond the FEATURE AND PERFORMANCE OVERVIEW
obvious choices of number of outputs and peak: UC1708 UC1710 UC1711
current capability. Cross-conduction is dermed as
Number of outputs 2 1 2
the conduction of current through both of the totem
Peak output current (per output) 3A 6A 1.5A
pole transistors simultaneously from Vin to ground. Noninverting input -{)utput logic I I
It is an unproductive loss in the output stage which Inverting input-output logic I I
results in unnecessary heating of the driver and Maximum supply voltage Vre 35V 20V 40V
wasted power. Cross conduction is the result of Typical supply current Ire (1) 16mA 30mA 17mA
turning one transistor ON before the opposing one Remote Enable I
is fully off, a compromise often necessary to Shutdown Input I 1(2)
minimize the input to output propagation delays. Separate signal, power grounds 1(3) 1(3)
An interesting observation is that cross- Separate Vin and Vc pins 1(3)
conduction is less of a concern with large capacitive 8 pin OIL package I I I
loads ( FETs ) than with unloaded or lightly loaded 16 pin OIL package I I I
5 pin TO-220 package I
driver outputs. Any capacitive load will reduce the
slew of the output stage, slowing down its dv/dt. Note 1. Typical Vc pUs Vee wrrent measured at 200KHZ, 50% duty cycle and no load
This causes a portion of the cross conduction Note 2. Using the device's other input
Note 3. Pad<age dependent
current to flow from the load, rather than from the
input supply through the driver's opposite output should be in the order of low tens of nanoseconds
transistor. The power loss associated with a driver's to yield high efficiency. Also, the propagation
inherent cross-conduction is unchanged with large delays from the driver input to output should be
capacitive loads, however it is not caused by a around ten nanoseconds for quick response.
"shoot-through" of supply current. Thermal Considerations: The driver output
Driver Performance: There are a variety of stage can be modeled as a resistance to the
applications for MOSFET drivers - each with its respective auxiliary supply rail driving an ideal FET
own unique set of speed and peak: current capacitor. All of the energy used to charge and
requirements. Most general purpose drivers feature discharge the MOSFET gate capacitor is converted
1.5 amp peak: totem-pole outputs which deliver rise into heat by the driver. This gate power loss adds to
and fall times of approximately 40nsec into 1 nF. the driver's own power loss - resulting in a net
Propagation delays are in the vicinity of 40 to 50 driver power dissipation equal to its input voltage,
nsec, making these devices quite adaptable to Vec, multiplied by the sum of the gate and driver
numerous power supply and motor control currents, 10 + Icc. This can be calculated or
applications. These specifications can be used for a determined empirically by measuring the driver DC
comparison to those of a new series of higher speed input voltage and current.
and higher current devices: the UC1708, UCl710 Proper IC package selection and/or device heat
and the UC1711 power MOSFET drivers. Each sinking is the only method available to insure a safe
member in this group of 3rd generation driver ICs operating junction temperature, Tl. All IC's are
features significant performance improvements over specified and graded into junction temperature
their predecessors with one parameter optimized for ranges, and priced accordingly_ It should be noted
a specific set of applications. that using a device outside its tested and rated
Propagation delays: The trend towards higher temperature range can result in poor performance,
power densities has thrust switching frequencies parameters out of specifications, and quite possibly-
well beyond IMHz in many low to medium power no operation at all.
systems. With a one microsecond or less total
conversion period, the FET switching transitions

Texas Instruments 5 SLUP097

 Junction Temperature: The junction Table 5 ·PACKAGES AND TEMPERATURE RISE
temperature of the driver IC is obtained by ftrst
For P(diss) < or " 4oomW:
calculating the device thermal rise above the
ambient temperature. This is obtained by <320mW " 8 pin OIL, < 40°C rise
<360mw " 8 pin OIL, < 45°C rise
multiplying the average input power (VIN'IIN) by
<4oomW " 8 pin OIL, < 50°C rise
the device free air thermal impedance, aJA. This
term is then added to the ambient temperature to For P(diss) > 400mW a heat sink is required:
yield the resulting junction temperature, D. <600mW " 8 pin OIL, <40°C rise with heat sink
If the driver is thermally attached to a heat sink <75OmW" 8 pin OIL, <50°C rise with heat sink
or "cold plate", then the thermal impedance from >75OmW" TO-220 Package
the device junction to it's package case, aJC, is used
to determine the thermal rise. Likewise, this thermal High Power MOSFET Applications
rise is added to the heat sink temperature to Many high power applications require the use of
determine the junction temperature. In either case, "monster" MOSFETs or several large FETs in
the maximum junction temperature, D(max), should parallel for each switch. Generally, these are low to
be determined and checked against the device medium frequency applications (less than 200kHz)
absolute maximum specification. where obtaining a low Rns(on) is of primary concern
Average supply currents of the driver ICs vary to minimize the DC switch loss. It is not uncommon
primarily with the switching frequency. A rough to find two, three and even four large devices used
approximation of 25mA will be used as the driver in parallel, although some of these combinations are
supply current, regardless of the specific device unlikely from a cost versus performance standpoint.
utilized and switching frequency. A typical supply Table 6 displays the individual FET device
voltage of 12V will be used which results in a characteristics and several popular parallel
power dissipation of 300mW, excluding any arrangements. Listed in descending order is room
contribution by the gate charging/discharging power. temperature Rns(on) and the total gate charge
The calculated gate power of Table 1 has been required. This will ultimately be used to determine
added to the estimated 300mW driver power to the gate drive current in Table 7 and total power
formulate Table 4 - the total driver power dissipation in Table 8 applications.
dissipation. This is of particular interest in selecting Table 6" PARALLELED MOSFET CHARACTERISTICS
a driver package (8 pin, TO-220, etc) and heat sink
CONFIGURATION ROS(ON) Qg(nC)
determination for a specific maximum junction
temperature, or rise. Typical junction temperature 1 x Size 4 0.85 63
rises vs. frequency and FET size for a IC package, 1 x Size 5 0.40 130
1 x Size 6 0.27 190
and recommendations are shown in Table 5.
2 x Size 4 (1) 0.425 126
3x Size 4 (1) 0.283 189
Table 4 • AVERAGE POWER DISSIPATION (mW)
4 x Size 4 (1) 0.213 252
vs. FREQUENCY AND SIZE
2 x Size 5 0.200 260
SWITCHING FREQUENCY (KHZ) 2 x Size 6 0.135 380
50 100 150 200 250 500 750 1M-lZ 3 x Size 5 (1) 0.133 390
4 x Size 5 (1) 0.100 520
Size 1 310 318 328 336 346 390 436 480
3 x Size 6 (2) 0.090 570
Size 2 316 330 346 360 376 452 526 600
4 x Size 6 (2) 0.068 760
Size 3 328 354 382 408 436 570 706 840
Size 4 348 396 444 492 540 780 1.0W 13N Notes: 1. Consider another selection
Size 5 400 500 600 700 800 900 1.7W 2.4W 2. Consider a "Monster' FET
Size 6 444 588 732 876 1.0W 1.7W 2.5W 3.1W

Texas Instruments 6 SLUP097

 layout or wmng inductance in series with the
Table 7· AVERAGE SUPPLY CURRENT MOSFET or IGBT gate will significantly degrade
vs. FREQUENCY AND SELECTION performance for two reasons. First, the inductance
SWITCHING FREQUENCY (KHZ) limits the gate drive current rate of rise to less than
Configuration 25 50 75 100 150 200 optimal. Second, and most consequential, is that the
1x Size 5
inductance forms a resonant L/C tank with the gate
31 39 45 51 65 77
2x Size 6 35 45 53 63 83 101
capacitance. This causes the gate voltage to
3x Size 6 39 53 69 73 91 139 overshoot during tum-on and rise above the
4x Size 6 45 63 82 101 139 177 auxiliary supply voltage which introduces two other
problems. A Zener clamp must be physically located
directly at the FET gate to prevent exceeding the
Table 8 POWER DISSIPATION (mW) maximum gate-to-source voltage. Also, any
vs. FREQUENCY AND APPUCATION overshoot beyond the supply rails will reverse bias
SWITCHING FREQUENCY (KHZ) the drive transistors as either emitter rings towards
Configuration 25 50 75 100 150 200 the respective base voltage. This immediately turns
OFF which ever drive transistor was ON and puts
2 X SIZE 5 372 468 540 612 780 924
2 X SIZE 6 420 540 636 756 1.0W 121'1 the drive stage into a high impedance state.
3 X SIZE 6 468 636 828 876 101W 1m The overshoot will ring and eventually decay to
4 X SIZE 6 540 756 984 1.2W 107W 2.1W an amplitUde at which the drive transistor will begin
to tum back on. There is a finite time involved with
this process, however. depending on the transistors'
"Homebrew" Totem-poles vs. Integrated speed, base drive and resonant tank period. Before
Circuit Drivers the drive transistor is turned back on. the gate
The prior lack of "off-the-shelf' high current or voltage continues to resonate closer towards its
high speed drivers prompted many to design their opposite state. For example, if the FET was ON,
own gate drive circuits. Traditionally, an NPN-PNP then the gate voltage continues to decrease. And if
emitter follower arrangement as shown in Figure 3 the drive transistor takes too long to turn on, it's
was used in lower frequency applications. This possible for the MOSFET gate voltage to cross its
noninverting configuration interfaces easily with "ON" gate threshold. thus turning the device OFF.
most PWM controllers and performs adequately in Since most MOSFETS have shorter delays than the
many converters. Peak gate drive current does suffer bipolar drivers. it's relatively easy to unintentionally
from dependency on driver transistor gain, and construct a poor gate drive circuit with a discrete
transition times are lengthened by the "slow" PNP design. Both a zener clamp diode and a Schottky
transistor. diode around each drive transistor to the rails is
necessary with NPN/PNP drivers.
+12V---.. For higher speed applications, a P and N channel
FET pair can be used as shown in Figure 4. The
circuit is configured with the P channel MOS as the
INPUT TO LOAD
upper side switch to simplify the auxiliary bias.
Otherwise, a gate drive potential of 10V above the
GND _ _--.J
auxiliary bias would required. Unfortunately, this
configuration also has a few drawbacks. First, it
Fig 3. - Bipolar Gate Driver leads to an inverting logic flow from the driver
The major drawback to this bipolar drive input to its output, complicating matters especially
technique, however, is the potential turn-off of the during power-up and power-down sequences.
drive transistors whenever the gate voltage Without a clever undervoltage lockout circuit the
overshoots the supply voltage rails. Any parasitic main power switch will tend to be ON as the

Texas Instruments 7 SLUP097

auxiliary supply voltage is raised or lowered while three IRFP460 devices in parallel. The discrete drive
the PWM is OFF. circuit utilized an IRFP930 "P" type and an IRF520
"N" channel device connected in series with two
+12V
~
3 PMOS
one-half ohm resistors to limit the shoot-through
current. These FETs were driven from the VCI711
INPUT" Itt- TO LOAD dual driver which can deliver 3A peak gate drive

GND~NMOS
currents for rapid transitions. The performance of
this circuit was compared to that of the VC17IO
driver IC which has 6A capability. The test'results
Fig 4. - FEr Gate Driver as shown in Figure 6 indicate very similar
performance into a 30nF load from either technique.
Cross conduction of both FETs may be Obviously, the "homebrew" approach utilizes a total
unavoidable with this configuration due to the of three devices in comparison to a single driver to
difference between the gate threshold voltages of obtain essentially the same high speed performance.
each device. Depending on the supply voltage, both Additionally, the cost of the P channel FET alone
P and N channel devices can cross conduct while may warrant consideration, not to mention the
their input drive waveform is above VGS(th) of the difference in PC board real estate. As a fInal note,
"N" device and below that of the "P" device. One the discrete FET approach required signiftcantly
technique to minimize the peak cross conduction more supply current than the sole driver IC,
current is to add some resistance between the FETs. primarily due to the higher cross conduction.
While this does minimize the "shoot-through"
current, it also limits the peak current available to
the load. This somewhat defeats the purpose of
UC3710
using the MOSFETs in the fIrst place to deliver
high currents. The resistor serves an additional Discrete
purpose of damping the gate drive oscillations
during the transitions, minimizing the overshoot. In
a practical application, two resistors can be used in
the place of one with the center tap connecting to
the FET gate load as shown in Figure 5.

12V SIZE3
PMOS

INA OUTA 0.5

OHM Fig 6. - Driver Peiformance into 30nF Load
UC (ea)
3711

30
IN B '----._---J OUT B
nF
SIZE 2
GND NMOS

Fig 5. - FEr Driver with Limiting Resistors

The performance of the circuit in Figure 5 was

evaluated and compared to that of the VC1710
driver into a 30nF load, approximately equivalent to

Texas Instruments 8 SLUP097

Power Devices
IGBTs and MCTs: While existing generations of GBT MeT
power MOSFETs continue to be enhanced for lower

GATE ~OR GATE~

RDS(on) and faster recovery internal diodes,
alternative new devices have also been introduced.
Among the most popular, and viable for high
voltage, high power applications are IGBTs
(Insulated Gate Bipolar Transistors) and MCTs
(MOS Controlled Thyristors). Although frequently EM I TTER CATH'ODE
drawn as an NPN structure, the IGBT actually
resembles a PNP bipolar transistor with an internal
~OS de~ic~ to control the base drive. Indicative by Fig 7. - [GBT and MeT Diagrams
Its descnpbon, the MCT is essentially an SCR
structure also utilizing a MOS drive stage. Both
devices offer significant cost advantages over
MOSFETs for a given power capability. !2 Volts at the gate, IGBT performance steadily
Improves up to the suggested 16 Volt maximum
MOSFET, IGBT and MCT Gate Drives: There
gate voltage. Typically, most IGBT manufacturers
are numerous reasons for driving the MOSFET gate
recommend a negative drive voltage between -5 and
to a negative potential during the device's off state.
-15V. Generally, it is most convenient to derive a
Degradation of the gate turn-on threshold over time
negative voltage equal in amplitude to the positive
and especially following high levels of irradiation
supply rail, and ±15V is common.
are amongst the most common. However, with
The gate charge required by an IGBT (for a
IGBTs, the important concern is the ability to keep
given voltage and current rating) is noticeably less
the device off following tum-off with a high drain
than that of a MOSFET. Part of this is due to the
current flowing. On larger IGBT's with ratings up
better utilization of silicon which allows the IGBT
to 300 Amps, inductive effects caused by the
die to be considerably smaller than its FET
device's package alone can "kick" the effective
counterpart. Additionally, the IGBT (being a bipolar
gate-to-emitter voltage positive by several Volts at
transistor) does not suffer from the severe "Miller"
the die - even with the gate shorted to the emitter at
effects of the MOS devices, easing the drive
the package terminals. Actually, this is the result of
requirements in a given application. However.
the high current flowing in the emitter lead
because of their advantages, most available IGBTs
(package) inductance which can less than InH. The
have fairly high gate charge demands - simply
corresponding voltage drop changes polarity at tum
because of their greater power handling capability.
off, thus pulling the emitter below the gate, or
In contrast, MCTs (MOS Controlled Thyristors)
ground. If high enough, a fast tum off will be
exhibit the highest silicon utilization level among
followed by a parasitic tum-on of the switch, and
power switching devices. While relatively new to
potential destruction of the semiconductor. Applying
the market. these devices are quickly gaining
!he correct amplitude of negative gate voltage can
acceptance in very high power (above several
Insure proper operation under these high current
kilowatts) applications because of their high voltage
tum-off conditions. Also, the negative bias protects
(I000V) and high current (to l000A) capability.
against tum-on from high dv/dt related changes that
Recently introduced parts boast maximum ratings to
could couple into the gate through the "Miller"
one megawatt. ideal for large industrial motor drives
capacitance.
and high power distribution-even at the substation
Unlike power MOSFET switches, IGBT trans-
level. These devices are essentially MOS controlled
con~uctance continues to increase with gate voltage.
SCRs and are intended for low frequency
WhIle most MOSFET devices peak with about 10 to
switchmode conversion. They will most likely

Texas Instruments 9 SLUP097

replace high power discrete transistors, r----------~--,,"'"",.........._-lOOUT
Darlingtons and SCRs because of their lK

higher efficiency and lower cost. :---------.._--------------------_.._----j

lK lK
: NE5532 :
Gate Charge And Effective Capacitance 1 :
..._-t--- -+-. +15V
with Negative Bias: While several MOSFET 5NF VCC!f

i - rl
and IGBT manufacturers recommend
negative gate voltages in the device's off
~~
-,. -r~. . . . :sg
51K
state, few publish any curves or information
about gate charge characteristics when the
gate is below zero Volts. This complicates
the gate drive circuit design as each IGBT,
MOSFET or MCT switch must be evaluated I 0.1 0.1 I = 51K

by the user over the ranges of operating

conditions. A test fixture as shown in Figure Fig 8. - Gate Charge Test Circuit
8 can be used to provide empirical generalizations
for devices of interest. A switched constant current
source/sink has been configured using a simple dual
op-amp to drive a "constant" ImA at the device
under test (DUn. Gate voltage versus time can be
monitored which provides the exact gate charge
requirements for a given device. Any application +5
specific requirements can also be accommodated by
modifying the test circuit with external circuitry. Vgs 0
(v) '"
Negative Gate Charge - Empirical Data: -5
Several MOSFET, IGBT and MCT gate charge MGT
·10
measurements were taken to establish the general
characteristics with negative gate bias. The gate -15
charge and effective capacitance during this third
quadrant operation was calculated and compared to VERT 5V1DIV HORIZ 50uS/DIV
of the first quadrant specifications from the
manufacturers data sheets. Figure 9 demonstrates Fig 9. - Gate Charge Comparison
the general relationships of gate charges for Low to High Transition
comparison.
Both the IGBT and MCT have similar negative
bias gate charge requirements as with an applied
positive bias. The MOSFET, however, exhibits a
slightly reduced gate charge in its negative bias
region, somewhere between 70 and 75 percent of its
positive bias charge. The MOSFET's more
significant "Miller" effect in the first quadrant is
responsible for this since the higher effective
capacitance during the plateau region does not occur
with negative bias.

Texas Instruments 10 SLUP097

 Summary
The universal need for improved switching
efficiency in the power management industry is
being addressed by the recent introductions of many
higher performance MOSFET, IGBT and MCT
semiconductors. Moreover, industry demand for
increased power density continually elevates
conversion frequencies. Each of these efforts has
placed considerably more demands on the gate drive
circuitry, especially the integrated circuit gate
drivers. The intent of this paper has been to provide
the designer with a comprehensive, quantitative
VERT 5V1DIV
understanding of gate drive characteristics, suitable
HORIZ SOus/DIV
for a variety of applications.
Fig 10. - Gate Drive Comparison
High to Low Transition Additional Information
Total Gate Power· Negative Drive Voltage UNITRODE Application Note U-118, "New
Applications: All of the previously presented gate Driver IC's Optimize High Speed Power
power equations still apply, however they must be MOSFET Switching Characteristics",
modified to include the additional charge UNITRODE LINEAR IC DATABOOK, IC 600
requirements of the negative supply voltage. For the UNITRODE Application Note U-126, "A New
sake of simplicity, a multiplication factor can be Generation of High Performance MOSFET
used for recalculation of the exact figures. When Drivers Features High Current, High Speed
identical amplitudes of positive and negative supply Outputs"
voltages are used, for example ±15V, then the gate UNITRODE Application Note U-127, "Unique
power utilized can be simply multiplied by a factor Chip Pair Simplifies Isolated High Side Switch
of two. This completes the process for the IGBTs Drive"
and MCfs. The total MOSFET gate charge, on the
INTERNATIONAL RECTIFIER Application
other hand, should only be multiplied by a factor of
Notes AN-937, AN-947 and Data Sheets, I.A.
1.7 to 1.75 to accommodate the reduced negative
HEXFET Power MOSFET Designers Manual
bias demands. Additionally, if a negative supply
HDB-4
voltage different than the positive rail voltage is
used, for example +15V and -5V, then the scaling INTERNATIONAL RECTIFIER AN-983, "IGBT
factor must be adjusted accordingly. In this case, the Characteristics and Applications"; IGBT
new total gate power would be 1 + (-51-15) or 1.33 Designer's Manual
times the initial 0-15V gate power for IGBTs and
MCTs. The negative drive voltage scaling factor
(-5/-15) would be multiplied by the 70 to 75%
index if a MOSFET were used instead of an IGBT
or MCT. This would result in a 1.23 to 1.25 times
net increase over the initial (0-15V) gate power
demand.

Texas Instruments 11 SLUP097

High Performance MOSFET Driver Transition Performance: Using the performance table,
Reference the driver output slew rates and average current delivered
can be calculated. The figures can be compared to lower
UC1711: The UC1711 device features typical power op-amps or comparators to gain a perspective on
propagation delays of three and ten nanoseconds at no the relative speed of these high performance drivers. The
load, depending on the transition. Coupled with duall.5A UC1708 delivers output slew rates (dv/dt) in the order of
peak totem-pole outputs, this device is optimized for high 300 to 480 V/psec, at average load currents of under one
frequency PET drive applications. Its all NPN Schottky amp, depending on the load. The high speed UC1711
transistor construction is not only fast, but radiation exhibits similar characteristics under loaded conditions,
tolerant as well. but can achieve a no load slew rate of over 1700 V/psec-
UC1710 "Miller Killer": High peak gate drive currents nearly 2 V/nsec. For higher power applications, the
are desirable in paralleled PET applications, typical of a UCl710 "Miller Killer" will produce an average current
high power switching section or power factor correction of 4.5A at slew rates of 150 Vpsec. With lighter loads it
stage. Dubbed as "the Miller Killer", the UC1710 boasts will deliver an average current of 1.5A at a slew rate of
a guaranteed 6A peak output current. This hefty driver approximately 500 V/psec. In most applications, the
current minimizes the PET parasitic "Miller" effects UCl710 will easily outperform "homebrew" discrete
which would otherwise result in poor transition MOSPET transistor totem-pole drive techniques.
performance. Higher currents are possible with this driver, Each device in this new generation of MOSPET drivers
but the limiting factor soon becomes the parasitic series is significantly more responsive than the earlier
inductance of the PET package (15 nH) and the layout counterparts for a given application - higher speed
interconnection of 20 nH/inch. An RF type arrangement (UC1711), higher peak current (UCl710) or a
of the PC board layout is an absolute MUST to realize combination of both (UC1708).
this device's full potential.
UCl710 Block Diagram: The UCI710 has "no-load" UC1708/1710 11711 Performance Comparison
rise and fall times of 20 nanoseconds (or less) which do
not change significantly with any loads under 3nF. It is PARAMETER LOAD UC1708 UC1710 UC1711
also specified into a load capacitance of 30nF, represent-
Propagation Delay 0 25 30 10
ative of three paralleled "size 6" PET devices. Propaga-
IpLH 1.0 nF 25 15
tion delays are brief with typical values specified at 35 input to 10"10 output 2.2 nF 25 30 20
nanoseconds from either input to a 10% output voltage 30 nF 30
change.
UC1708: The UC1708 is a unique blend of the high Rise time 0 25 20 12
trLH 1.0 nF 30 25
speed attributes of the UC1711 along with the higher
10"10 to 90"10 rise 2.2 nF 40 25 40
peak current capability of the UCl710. This dual
30 nF 85
noninverting driver accepts positive TTL/CMOS logic
from control circuits and provides 3A peak output from Propagation Delay 0 25 30
each totem pole. IpHL 1.0 nF 25 5
Propagation delays are under 25nsec with rise and fall input to 90"10 output 2.2 nF 25 30 5
times typically 35nsec into 2.2nF. The output stage design 30 nF 30
is a "no float" version incorporating a self biasing
Fall Time 0 25 15 7
technique to hold the outputs low during undervoltage 1.0 nF 30 25
lockout, even with VIN removed. trHL
90"10 to 10"10 fall 2.2 nF 40 20 40
In the 16 pin DIL package, the device features a remote 30 nF 85
ENABLE and SHUTDOWN function in addition to
separate signal and power grounds. The ENABLE
function places the device in a low current standby mode
and the SHUTDOWN circuitry is high speed logic
directly to the outputs.

Texas Instruments 12 SLUP097

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SLUP097
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