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Week4 VLSI Subsystems Assignment Answers

The document contains 10 questions about propagation delays and logical efforts of different logic gates like NAND, NOR, multiplexers. It asks to identify the tpdr, tpdf values for different logic gates based on the number of inputs. It also contains questions to determine the logical effort values and Elmore delay values for 4-input NAND, NOR gates and a 2-input NOR, NAND gate.

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309 views

Week4 VLSI Subsystems Assignment Answers

The document contains 10 questions about propagation delays and logical efforts of different logic gates like NAND, NOR, multiplexers. It asks to identify the tpdr, tpdf values for different logic gates based on the number of inputs. It also contains questions to determine the logical effort values and Elmore delay values for 4-input NAND, NOR gates and a 2-input NOR, NAND gate.

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GPS INNOVATIVES
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© © All Rights Reserved
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Week - 4

1) The tpdf and tpdr of an N input NAND gate is


a) RC(N2+5N)/2, RCN(N+2)
b) RC(2N2+5N)/2, RCN(N+2)
c) RC(5N2+5N)/2, RCN(N-4)
d) RC(3N2+5N)/2, RCN(N)
e) RC(2N2+2N)/2, RCN(N-3)
f) RC(2N2+4N)/2, RCN(N+7)
g) RC(2N2+N)/2, RCN(N-9)
h) RC(2N2+6N)/2, RCN(N-1)

2) The tpdr and tpdf of an N input NOR gate is


a) RC(2N2), RCN(2N+2)
b) RC(3N2+N), RCN(2N)
c) RC(N2+N), RCN(2N+3)
d) RC(4N2+5N), RCN(2N+4)
e) RC(2N), RCN(N+3)
f) RC(2N2+3N), RCN(N+2)
g) RC(2N2+2N), RCN(N+1)
h) RC(N2+2N), RCN(2N+1)

3) What is the logical effort for the input in a tristate based 2:1 multiplexer, considering long
channel current model? Note that select lines are not inputs
a) 8
b) 1
c) 2
d) 16
e) 4/3
f) 5/3
g) 7/3
h) 10

4) For a 4-NAND (4 input NAND gate), what is the propagation delay falling and rising delay
as per the ELMORE Delay method?
a) 16 RC & 16 RC
b) 10 RC & 10 RC
c) 24 RC & 24 RC
d) 17 RC & 17 RC
e) 18 RC & 24 RC
f) 17 RC & 16 RC
g) 16 RC & 16 RC
h) 10 RC & 10 RC
5) For a 4-NOR (4 input NOR gate), what is the propagation delay falling and rising delay as
per the ELMORE Delay method?
a) 16 RC & 16 RC
b) 10 RC & 10 RC
c) 24 RC & 24 RC
d) 17 RC & 17 RC
e) 36 RC & 24 RC
f) 17 RC & 16 RC
g) 16 RC & 16 RC
h) 13.4 RC & 17.6 RC

6) What is the logical effort of 4-NOR (4-input NOR) gate considering long channel current
model?
a) 2.51
b) 6.55
c) 3
d) 6
e) 2
f) 4
g) 8
h) 1

7) What is the logical effort of 4-NAND (4-input NAND) gate considering long channel
current model?
a) 1.59
b) 2.79
c) 3
d) 6
e) 2
f) 4
g) 8
h) 1

8) The elmore delay from node Vin to node 4 is ______________ .


a) R1C1 + R1C6 +R1C7 + R1C8 +(R1 + R2)(C2 + C3) + (R1 + R2 + R4)(C4 + C5)
b) R1C1 + R2C6 +R1C7 + R1C8 +(R3 + R2)(C2 + C3) + (R1 + R2 + R4)(C1 + C5)
c) R1C1 + R2C5 +R1C7 + R1C8 +(R6 + R2)(C2 + C3) + (R1 + R2 + R4)(C3 + C5)
d) R1C1 + R2C3 +R1C7 + R1C8 +(R8 + R2)(C2 + C3) + (R1 + R2 + R4)(C6 + C5)
e) R4C1 + R4C4 +R1C7 + R1C8 +(R3 + R2)(C2 + C3) + (R1 + R2 + R4)(C2 + C5)
f) R4C1 + R4C5 +R1C7 + R1C8 +(R1 + R2)(C2 + C3) + (R1 + R2 + R4)(C3 + C5)
g) R4C1 + R4C7 +R1C7 + R1C8 +(R6 + R2)(C2 + C3) + (R1 + R2 + R4)(C8 + C5)
h) R4C1 + R4C8 +R1C7 + R1C8 +(R1 + R7)(C2 + C3) + (R1 + R2 + R4)(C5 + C5)

9) According to ELMORE delay method, determine the propagation falling delay for 2-NOR
gate which is sized to P:N as 4:1 ?
a) 8RC
b) 16RC
c) 24RC
d) 10RC
e) 72RC
f) 12RC
g) 3RC
h) 9RC

10) According to ELMORE delay, determine the propagation rising delay for 2-NAND gate
which is sized to P:N as 2:2 ?
a) 8RC
b) 16RC
c) 24RC
d) 36RC
e) 72RC
f) 12RC
g) 3RC
h) 9RC

Solution:
1) a) RC(N2+5N)/2, RCN(N+2)
tpdf:

( )
tpdf = 𝑋 𝑁𝐶 + 𝑋 𝑁𝐶 + ⋯ + 𝑋 𝑁𝐶 + 𝑅 𝑋 3𝑁𝐶 = RC(N2+5N)/2
tpdr:

tpdf = 𝑅 𝑋 3𝑁𝐶 + 𝑅 𝑋 𝑁𝐶 𝑋 (𝑁 − 1) = RCN(N+2)

2) h) RC(N2+2N), RCN(2N+1)

( )
tpdr = 𝑋 2𝑁𝐶 + 𝑋 2𝑁𝐶 + ⋯ + 𝑋 2𝑁𝐶 + 𝑅 𝑋 3𝑁𝐶 = RC(N2+2N)

tpdf = 𝑅 𝑋 3𝑁𝐶 + 𝑅 𝑋 2𝑁𝐶 𝑋 (𝑁 − 1) = RCN(2N+1)

3) c) 2

4) e) 18RC and 24RC


Formula based.

5) e) 36RC and 24RC


Formula based.
6) c) 3
g = (1+8)/3 = 3

7) e) 2
g = (2+4)/3 = 2

8) a) R1C1 + R1C6 +R1C7 + R1C8 +(R1 + R2)(C2 + C3) + (R1 + R2 + R4)(C4 + C5)
Application of elmore delay model.

9) d) 10RC
4:1 2-NOR gate is a symmetric gate, with 2:1 inverter as the benchmark. So, direct
application of formula.

10) a) 8RC
2:2 2NAND gate is a symmetric gate, with 2:1 inverter as the benchmark. So, direct
application of formula.

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