MICROCONTROLLER AND EMBEDDED SYSTEMS

(BEC-351)

UNIT-II
8051 Architecture

By
Dr. Ishwar Chandra Yadav
Electronics & Communication Department
Madan Mohan Malaviya University of Technology, Gorakhpur
January 2024

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 syllabus

Syllabus

Unit-I
Introduction to Embedded system: Embedded system and codesign issues, Pro-
cessor Embedded into a System, Embedded Hardware and Software in a system,
Examples of ES, use of VLSI Circuit Design Technology, Use of software tools for
development of an ES.
Introduction to Microcontrollers and Embedded Processors: Microcontrollers
survey, 4-bit,8-bit, 16-bit, 32-bit Microcontrollers, Comparing Microprocessors and
Microcontrollers, Overview of the 8051 Microcontroller family.

Unit-II
8051 Architecture: Hardware, Oscillator and clock-program counter, data pointer
registers, stack and stack pointer, special function registers, memory organization,
program memory, data memory, Input/Output Ports, External memory counter and
timer, serial data Input/output Interrupts.

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 syllabus

Syllabus

Unit-III
8051 Assembly Language Programming:Structure of Assembly language, Assem-
bling and running an 8051 program, addressing modes, Accessing memory using
various addressing modes
Instruction set:arithmetic operations and Programs, Logical operations and Pro-
grams, Jump and Call instructions and Programs, Input/Output Programs, Single
bit instructions and Programs, Timer, counter and Programs.

Unit-IV
8051 Serial Communication: Connection to RS-232, Serial Communication Pro-
gramming, Interrupts Programming,
Microcontroller Interfacing: Keyboard, Displays, Pulse Measurement, D/A and
A/D conversion, Stepper Motor
Basic concept of PIC microcontroller and RTOS: Microcontroller Architec-
ture–PIC16F Family and Introduction to RTOS.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 3 / 83
 syllabus

Syllabus

Reference & Text Books

1 Embedded System: Architecture, Programming and Design by
Rajkamal,2ndedition,2010, Tata McGraw Hill.
2 The 8051 Microcontrollers and Embedded Systems: Muhammed Ali Mazidi,
2nd edition, Pearson Education India.
3 The 8051 Microcontrollers Architecture, Programming & Applications
Kenneth J.Ayala
4 Design with PIC Microcontroller: John Petman.

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 Time Table

Time Table (Section-A)

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 Time Table

Time Table (Section-B)

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 Unit-II: 8051 Architecture [1]–[3]

Contents

8051 Architecture
• Hardware
• Oscillator and clock-program counter
• Data pointer registers
• Stack and stack pointer
• Special function registers
• Memory organization
• Program memory
• Data memory
• Input/Output Ports
• External memory
• counter and timer
• Serial data Input/output
• Interrupts.
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 Unit-II: 8051 Architecture [1]–[3] Hardware

8051 Hardware
8051 Hardware
The architectural block diagram of the 8051 is shown in the following Figure.

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 Unit-II: 8051 Architecture [1]–[3] Oscillator and clock

Oscillator and clock

• The clock is a repetitive sequence of pulses used to synchronize all the internal
activities of a microcontroller/ processor.
• It is the smallest unit of time in which the microcontroller performs a part
of the program execution/operation. The clock pulses are also referred as a
system clock.
• The oscillator unit is responsible for generating the clock signals. All 8051
family microcontrollers contain an on-chip oscillator circuit (of course partial
circuit).
• We need to connect a resonant network (crystal + capacitors) to make it
functional.
• The 8051 on chip oscillator circuit provides external interface option through
two pins of the microcontroller, namely, XTAL1 and XTAL2.
• The cheapest solution is to connect ceramic resonator across the XTAL1 and
XTAL2 pins of the chip with two external capacitors having values 15pF, 22pF,
33pF, etc.

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 Unit-II: 8051 Architecture [1]–[3] Oscillator and clock

Oscillator and clock

• If an external stand alone oscillator unit is used, the output signal of the
oscillator unit should be connected to the pin XTAL1 of the chip and the pin
XTAL2 should be left unconnected for a CMOS* type microcontroller (80C51).
• For an NMOS† type microcontroller, the oscillator output signal should be
connected to the Pin XTAL2 and the pin XTAL1 should be grounded.

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 Unit-II: 8051 Architecture [1]–[3] Oscillator and clock

Oscillator and clock

Execution Speed
• The execution speed of the processor is directly proportional to the oscillator
clock frequency.
• Increasing the clock speed will have direct impact on the speed of program
execution. But the internal processor core design will always have certain
limitations on the maximum clock frequency on which it can be operated.
• During program execution the instructions stored in the code memory is fetched,
decoded and corresponding action is initiated.
• Each instruction fetching consists of the number of machine cycles.Each ma-
chine cycle is made up of a sequence of states called T states.

Machine Cycle, T state, Clock Cycle

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 Unit-II: 8051 Architecture [1]–[3] Programming Models of 8051

Programming Models of 8051

Figure: Programming models of 8051

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

On-Chip Memory Organization

The 8051 On-chip memory is organized into three general categories; Special
Function Registers, internal RAM and internal ROM.
Special Function Registers (SFRs)
• Used to program and control various on-chip hardware peripherals and features
of the 8051.
• Each SFR has a name which specifies the purpose of the SFR.
• 128 bytes (80H to FFH) of the SFR address space is available, but only 21 SFRs
are defined in the standard 8051. Since SFRs are programmed by instructions,
they are RAM locations.
• SFRs are categorized as follows:

1. Math registers: A and B 5. Input output port latches: P0, P1,

2. Status register: PSW (Program P2, and P3
Status Word) 6. Peripheral data registers: TL0,
3. Program counter: PC TH0, TL1, TH1, and SBUF
4. Pointer registers: DPTR (Data 7. Peripheral control registers: IP, IE,
Pointer) and SP (Stack Pointer) TMOD, TCON, SCON, and PCON

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

On-Chip Memory Organization

Special Function Registers (SFRs)

Memory SFR Memory SFR Memory SFR

address Name Address Name Address Name
80H Port 0 8AH TL0 A0H Port 2
81H SP 8BH TL1 A8H IE
82H DPL 8CH TH0 B0H Port 3
83H DPH 8DH TH1 B8H IP
87H PCON 90H Port 1 D0H PSW
88H TCON 98H SCON E0H A
89H TMOD 99H SBUF F0H B
Figure: SFR implementation for standard 8051 architecture

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

On-Chip Memory Organization

Internal RAM
• The 8051 has 128 bytes of internal RAM. Since it is available on-chip, it is
fastest and most flexible in terms of read/write operations. It is used to store
temporary data and results.
• This memory is subdivided into three categories as specified below:
• Register Banks: Bank 0, Bank 1, Bank 2 and Bank 3 (00H to 1FH)
• Bit Addressable RAM: Memory locations from addresses 20H to 2FH
• General Purpose RAM: Memory locations from addresses 30H to 7FH

Internal ROM
• It is used to store program instructions to be executed by the microcontroller.
• It may also be used to store permanent data like constants, passwords and
lookup tables. The 8051 has 4Kbytes of internal ROM.
• Different variants of 8051 has different amount and type of on-chip ROM.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

1. Accumulator: A
• Accumulator register is used to store (collect or accumulate) the result of all
arithmetic and majority of logical operations and because of this reason, it is
named accumulator.
• Accumulator is the most useful and versatile register because it is used in
• All arithmetic operations like addition, subtraction, multiplication and division.
• Majority of logical operations like logical AND, OR, NOT, EX-OR and Rotate.
• All data transfer between the 8051 and any external memory.

2. B
• B is used along with A in multiplication operation to hold one of the operands
(either multiplier or multiplicand) and to store higher-order byte of the result.
• It is also used in division operation to hold divisor and to store remainder of
the result.
• When not used with multiplication or division, it can be used as a general-
purpose register where one byte of data may be stored.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

3. PSW
• Program Status Word is an 8-bit register. It is also referred as flag register or
processor status word.
• Flag is a flip-flop (1-bit storage element) used to store and indicate the nature
of result produced by execution of certain instructions.
• The state of flags (0 or 1) are tested by other instructions (program flow control
or branch instructions) to make decisions.
• PSW structure is shown in the following Table.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

3. PSW

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

3. PSW
• CY: Carry Flag It is a carry (or borrow) used in addition and subtraction
operations. It is set to 1 when there is carry out from MSB (D7 bit) after an
addition (or a borrow into D7 bit during a subtraction). It is also used as the
‘Accumulator’ for the Boolean operations. It can be directly modified by bit
level instructions.
• AC: Auxiliary Carry Flag It is a half carry (carry out from bit D3 to D4) used
in conventional BCD arithmetic.
• F0: Flag 0 It is a general-purpose flag. It can be used as a one-bit memory
location to record some event.
• RS0 and RS1: Register Bank Select Bits These bits are used to select the
register bank.
• OV: Overflow Flag It is set to 1 to indicate that result of signed arithmetic
is erroneous (out of range).
• P: Parity Flag It indicates the parity of the Accumulator; it is set to 1 if the
accumulator register has odd number of ones, otherwise reset to 0, i.e. even
parity.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

4. Program Counter: PC
• Program Counter (PC) is a 16-bit register. It always contains the memory
address of the next instruction to be executed, i.e. it points to the instruction
that is to be executed next.
• As the CPU fetches the op-code (instruction byte) from the program memory,
the PC is incremented automatically to point to the next instruction.
• It should be noted that it is not always incremented by one during instruction
execution, but it depends on size of the instruction being executed, i.e. if
2-byte instruction is being executed, the PC is incremented by 2.
• There is no direct way to modify the PC but it can be modified using jump or
call instructions.
• There is no direct way to read the value of PC.
• PC is a 16-bit register, the 8051 can access program addresses from 0000H to
FFFFH, a total of 64Kbytes of program memory.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

5. Data Pointer: DPTR

• DPTR is a 16-bit register. It is used to point to data byte in external data
(RAM) or program (ROM) memory.
• It can be used as a single 16-bit register or can also be accessed as two separate
8-bit registers named DPL and DPH, where DPH means higher byte of the
DPTR and DPL is lower byte of the DPTR.
• DPL and DPH are each assigned a separate address. DPTR does not have
single address.
• DPTR is under the control of the program, i.e. a programmer can write any
value in it at any time.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

6. Stack Pointer: SP
• Stack pointer always points to the top of the stack and used to access data
from there. It is an 8-bit register.
• Stack memory stores the program counter address, other memory and register
values during a sub routine/function call.
• On power on, it should be initialized to a defined value (its default value is
07H).
• While writing a new data byte on the stack, SP is automatically incremented
by 1 and data byte is stored at an address SP+1.
• While retrieving, data will be read from address in SP and then SP is decre-
mented by 1.
• The data is stored on to the stack using PUSH and CALL instructions and
retrieved using POP and RET instructions.
• Interrupts also use the stack to store the return addresses.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

7. I/O Port Registers (latches): P0, P1, P2 and P3

• The 8051 has four 8-bit ports named as P0, P1, P2 and P3, each can be used
as an input or output or both.
• All ports are byte as well as bit addressable. Each bit corresponds to one of
the pin of the microcontroller.
• P0, P2 and P3 pins have dual functions, but only one function can be used at
a time.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

8. Peripheral Data Registers: TL0, TH0, TL1, TH1, and SBUF

• TL0 (timer 0 lower byte) and TH0 (timer 0 higher byte) together represents
a16-bit register for timer 0. The value in this register determines the timing of
events controlled by a timer.
• They are also used as event counters. Similarly, TL1 and TH1 are registers for
timer1.
• SBUF (serial buffer) register is used to hold data to be transmitted or received
for serial port.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Special Function Registers (SFRs)

8. Peripheral Control Registers: IP, IE, TMOD, TCON, SCON, and PCON
• IP (interrupt priority) register is used to assign priorities to different interrupt
sources. IE (interrupt enable) register is used to enable/disable interrupts.
• TMOD (timer mode) is used to control behavior, i.e. mode of operation of
timers.
• TCON (timer control) is used to start/stop timers. It also contains the status
bits of the timers and status/control bits for the external interrupts.
• SCON (serial port control) register is used to control the modes of operation
of the serial port; it also contains the status bits to indicate completion of data
transmission and reception.
• PCON (power mode control) register is used to select power saving modes of
operations, i.e. power down and idle mode. It contains a bit to double the
baud rate for serial port and two general-purpose user flags.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal RAM

• The 8051 microcontroller has a total

of 128 bytes of internal RAM.
• These bytes are assigned addresses
00H to 7FH.
• These 128 bytes are grouped into
three different areas: Register
Banks, Bit Addressable Memory
and General-Purpose RAM.

1. Register Banks
• The first 32 bytes from addresses
00H to 1FH are organized as four
banks.
• Each bank is made up of eight regis-
ters named R0 to R7.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal RAM
• The four register banks are num-
bered 0 to 3, i.e. bank0, bank1, Addresses
Name RS1 RS0
bank2 and bank3. 00 01 10 11
• Each bank is assigned different ad- R0
(Bank 0)
00H
(Bank 1) (Bank 2)
08H 10H
(Bank 3)
18H
dress range, bank 0 address locations R1 01H 09H 11H 19H
R2 02H 0AH 12H 1AH
00H to 07H are given names R0 to R3 03H 0BH 13H 1BH
R7, i.e. 00H is named R0, 01H is R4 04H 0CH 14H 1CH
R5 05H 0DH 15H 1DH
named R1 and so on. R6 06H 0EH 16H 1EH
R7 07H 0FH 17H 1FH

• Similarly, bank1 (08H to 0FH), bank2 (10H to 17H), bank3 (18H to 1FH)
locations are given names R0 to R7.
• Out of these four banks, only one bank can be accessed at any time.
• Bits RS0 to RS1 in the PSW determines which register bank is currently in use
and can be modified at any time by a program to select any one of the bank.
• Register bank 0 is the default register bank, since after power on, both bits
RS0 and RS1 are initialized with value 0;
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal RAM

2. Bit Addressable Memory

• In an 8-bit microcontroller, the minimum size of data that can be accessed or
processed at a time is one byte.
• In many real-world machine control applications, we may need to manipulate
(read/write/modify) only one bit at a time.
• For example, sensing the state (ON/OFF) of switch, make decision based upon
state of the switch, and turn ON or turn OFF the external device.
• Such operations need to manipulate only required bits of a byte.
• The 8051 has a bit-addressable area of 16 bytes from byte addresses 20H to
2FH in internal RAM, forming a total of 128 (16 × 8) addressable bits.
• An addressable bit can be accessed by its bit addresses from 00H to 7FH.
• Besides these 128 bits, majority of SFRs are also bit addressable, namely:All
ports (P0, P1, P2 and P3), A, B, PSW, IP, IE, ACC, SCON, PCON and TCON
are bit-addressable.

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal RAM

2. Bit Addressable Mem-

ory
• The bit addressable area with address
of each bit is shown in Figure.
• The instruction that uses this address
determines whether a byte or bit is
being referenced without confusion.
• The bit addressable area with address
of each bit is shown in Figure

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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal RAM

3. General-Purpose (Scratchpad) RAM

• Bytes from memory locations 30H to 7FH are used for general-purpose data
storage.
• These 80 locations are widely used by programmers to store temporary data
and intermediate results.
• The advantage of using this memory is that their access is faster compared to
other off-chip RAM.
• This area of memory is also used as a system stack.
The Stack
• The stack is a section of memory in the internal RAM that is used for temporary
storage and retrieval of data (or addresses), while the execution of a program.
• It is the Last In First Out (LIFO) type memory. This section of memory is
accessed by certain instructions or events (like interrupts).
• The register used to access contents of the stack is called stack pointer.
• It is an 8-bit register. The power on default value of the SP register is 07H.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal ROM

• The 8051 contains 4Kbytes of internal ROM (on-chip).

• It occupies address range from 0000H to 0FFFH.
• Since it is used to store program instructions (code), it is also called program
memory or code memory.
• Different members of 8051 family contain different amount and type of on-chip
ROM. For example, 8051 contains 4Kbytes masked ROM, while 8752 contains
8Kbytes of internal EPROM.
• This memory is sufficient for small projects and applications.
• For larger programs, external memory may be connected or family members
with higher amount of internal ROM may be used.
• These days, internal memory up to 64K bytes is available in to variants of the
8051.
• Since PC is a 16-bit register, it can address up to 64Kbytes (from 0000H to
FFFFH) of program memory.
• Program (code) addresses above 0FFFH (which is beyond on-chip ROM ad-
dresses) will be accessed automatically from external program memory.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal ROM
• We can also connect external ROM if 4K of
internal memory is not sufficient for a partic-
ular application.
• Our program may reside partly into internal
ROM and partly into external ROM or en-
tire program can be stored into only external
memory starting from 0000H.
• Memory map of ROM, i.e. organization of
ROM for the 8051 system is shown in Figure.

• EA (external access) pin (pin 31) on the 8051 decides one of the above con-
figuration of ROM used by the 8051.
• If EA pin is connected to VCC (+5 V), the 8051 will access first 4K bytes
(0000H to 0FFFH) from internal ROM and any address above 0FFFH will be
accessed from external ROM.
• If EA is connected to ground (0 V) then only external memory from 0000H
to FFFFH will be accessed by the 8051.
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 Unit-II: 8051 Architecture [1]–[3] On-Chip Memory Organization

Internal ROM
• The interfacing of an exter-
nal program memory chip is
illustrated in Figure.
• The control signal for ex-
ternal program memory ex-
ecution is P SEN (Program
Strobe Enable).
• For internal program mem-
ory fetches P SEN is not ac-
tivated.
• If the program memory is external, 16 I/O lines are used for accessing the
external memory. Port 0 and Port 2 are used for external memory accessing.
• Port 0 serves as multiplexed address/data bus for external program memory
access.
• Similar to the 8085 microprocessor, Port 0 emits the lower order address first.
• This can be latched to an 8bit external latch with the Address Latch Enable
(ALE) signal emitted by 8051.
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 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

• Port is a group of Input/Output (I/O) lines. Each port has its own port control
unit, port driver and buffers.
• The original version of 8051 supports 32 I/O lines grouped into 4 I/O ports,
consisting of 8 I/O lines per port.
• The ports are named as Port 0, Port 1, Port 2 and Port 3.
• One output driver and one input buffer is associated with each I/O line.
• All four ports are bi-directional and an 8-bit latch (Special Function Register)
is associated with each port.
• Each port’s pin consists of a D latch, an Input Buffer and an Output Driver.
• These I/O pins can be accessed directly by instructions during the program
execution.
• The I/O ports are memory mapped in the 8051.
• Out of the 32 I/O pins, 24 pins (P0, P2 and P3) may each be used for two
different functions (but only one at a time).
• The function performed by a pin at any time depends on which instruction is
used to access a pin and what signal is connected to that pin; therefore these
factors can be directly controlled by a programmer.
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 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

• The alternate functions of ports

are given below. Port Pin Alternate Function
• P0: Low-order address/data P3.0 (Pin 10)
P3.1 (Pin 11)
RXD (Serial input: Receive Data)
TXD (serial output: Transmit Data)
bus (AD7–AD0) :Pin 32 to P3.2 (Pin 12) INT0 (External interrupt 0)
Pin 39 P3.3 (Pin 13) INT1 (External interrupt 1)
• P2: High-order address bus P3.4 (Pin 14) T0 (Timer/Counter 0 external input)
P3.5 (Pin 15) T1 (Timer/Counter 1 external input)
(A15–A8): Pin 21 to Pin 28 P3.6 (Pin 16) WR (External Data Memory write strobe)
• P3: Each pin has different P3.7 (Pin 17) RD (External Data Memory read strobe)
function as shown in Table
• Even within a single port, I/O operations may be combined in different ways.
• Different pins can be configured as an input or output independent of each
other or the same pin can be used as an input or output at different times,
i.e. all ports are bit- addressable.

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 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 0
• PORT 0 is a bi-directional port, which is used as a multiplexed address/data
bus in external data memory/ program memory operations.
• Port 0 pin organisation is illustrated in Figure.
• Each port pin has a latch (D latch), input buffers (B1 and B2) and output
driver (T1).
• The data from the internal data bus is written into the D latch when the
‘write to latch’ signal is activated by the internal control unit as a result of
appropriate instruction execution.

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 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 0
• The Q output of the latch is copied into the internal data bus when the ‘read
latch’ signal is activated.
• The level of a port pin is copied into the internal data bus when the ‘read pin’
signal is activated.
• Read Latch reads the content of corresponding port’s SFR/SFR bit latch
whereas Read Pin reads the present state of the corresponding port pin.
• Port 0 is designed acts as an I/O port in normal mode of operation and as
a multiplexed address data bus in external data memory/program memory
operations. I
• If the program memory is external to the chip, Port 0 emits the program counter
low byte in external program memory operation for specifi c time duration and
then acts as an input port to fetch the instruction from the address specified
by the program counter.
• In external data memory operations P0 emits the lower order byte of the DPTR
Register (DPL).
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 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 0
• During external memory related operations the multiplexer disconnects the port
0 bit output line from its corresponding bit latch and directly connect it to the
ADDRESS/DATA line and the output driver circuitry is driven according to
the ADDRESS/DATA line and the control.
• The output drivers of Port 0 are formed by two FETs, out of which the top
FET functions as the internal port pull-up.
• The pull-up FET driver for Port 0 is active only when the address line is emitting
1s during external memory operations.
• The pull-up FET will be off on all other conditions and the Port 0 pins which
are used as output pins will become open drain (Open Collector for TTL logic).
• Port 0 SFR(P0)(SFR-80H): Port 0 SFR is a bit addressable Special Function
Register that acts as the bit latch for each Port 0 pins.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 38 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 1
• PORT 1 is a bi-directional port which is used as a general purpose I/O port.
• The Port 1 pin organisation is given in Figure.
• Port 1 is a true I/O port because it has no alternate function and therefore it
has the simplest structure.
• Port 1 pin contains an internal pull-up resistor.
• In order to make the Port 1 pins as input line, the corresponding SFR latch bit
for Port 1 should be kept as 1.
• Writing a 1 into any of the P1 SFR bit latch turns off the output driver FET
and produces logic high at the corresponding port pin.
• The internal pull up for Port 1 is fixed and weak.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 39 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 1
• When Port 1 pins are configured as inputs (by writing a 1 to the corresponding
Port 1 SFR bit latch) the pins are pulled high and they can source current when
an externally connected device pulls the port pin to low, signaling a logic 0 at
the corresponding input line and places logic 0 to the internal bus in response
to a Read Pin command.
• If the externally connected device forces logic high, the Read Pin control signal
generated by a Read Pin related command places logic high into the internal
bus.
• Since Port 1 holds fi xed internal pull ups and are capable of sourcing current,
it is known as Quasi Bidirectional.
• Port 1 SFR(P1)(SFR-90H): It is also a bit addressable Special Function
Register that acts as the bit latch for each pin of Port 1. The bit details of
Port1 SFR is given below.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 40 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 2
• Port 2 is designed to operate in two different modes.
• It acts as general purpose I/O port in normal operational mode and acts as
higher order address bus in external data memory/program memory operations.
• Following Figure illustrates the Port 2 pin organization.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 41 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 2
• Port 2 emits the higher order byte of external memory address if the address
is 16 bits wide.
• During 16-bit wide external memory operations the base drive for the O/p
driver FET is internally switched to the address line.
• If the address line is emitting a 1, the O/p driver FET is turned off and the
logic 1 is refl ected on the O/p pin.
• If the address line is emitting a 0, the O/p driver FET is turned on and the
logic 0 is reflected at the corresponding pin.
• P2 is a Quasi bi-directional port.
• Port 2 SFR(P2)(SFR-A0H): It is a bit addressable Special Function Register
that acts as the bit latch for each pins of Port 2. The reset value of Port 2
SFR is FFH (All bit latches set to 1).
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 42 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 3
• Port 3 is a general purpose I/O port which is also configurable for implementing
alternative functions.
• Port 3 Pin configuration is shown in following Figure.
• Port 3 is identical to Port 1 in operation. All the settings that need to be done
for configuring Port 1 as I/O port is applicable to Port 3 also.
• The only difference is that the SFR latch for Port 3 is P3. Port 3 supports
alternate I/O functions.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 43 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Port 3
• From the Port 3 pin configuration it is clear that the alternate I/O functions
will come into action only if the corresponding SFR bit latch is set to logic 1.
Otherwise the port pin remains at logic 0.
• Port 3 SFR(P3)(SFR-B0H): It is a bit addressable Special Function Register
that acts as the bit latch for each pin of Port 3. Reset value of Port 3 SFR is
FFH (All bit latches set to 1)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 44 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Source and Sink Currents for 8051 Ports

• Source Current:
• The term source current refers to how much current the 8051 port pin can
supply to drive an externally connected device.
• The device can be an LED, a buzzer or a TTL logic device. For TTL family of
8051 devices the source current is defi ned in terms of TTL logic.
• TTL logic has two logic levels namely logic 1 (High) and logic 0 (Low).
• The typical voltage levels for logic Low and High is given in the following table.
Input Signal level Output signal level
Logic Level
Min Max Min Max
Low 0V 0.8V 0V 0.5
High 2V 5V 2.7V 5V

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 45 / 83
 Unit-II: 8051 Architecture [1]–[3] The 8051 Ports

The 8051 Ports

Source and Sink Currents for 8051 Ports
• Sink Current:
• It refers to the maximum current that the 8051 port pin can absorb through a
device which is connected to an external supply.
• The device can be an LED, a buzzer or a TTL logic device (For TTL logic
based 8051 devices).
• Pins of Ports P1, P2 and P3 can sink a maximum current of 1.6 mA. Port 0
pins can sink currents up to 3.2 mA.
• Under steady state the maximum sink current is limited by the criteria:
Maximum Sink Current per port pin = 10mA, Maximum Sink current per
8-bit port for port 0 = 26 mA, Maximum Sink Current per 8-bit port for port
1, 2, &3 = 15mA, Maximum total Sink current for all output pin = 71mA
• Figure illustrates the circuits for source, sink and ideal port interfacing for 8051
port pins.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 46 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers

• Timers are very essential for generating precise time reference in any system.
• Timers can be implemented in either software or hardware.
• The Standard 8051architecture supports two 16bit hardware timers namely:Timer
0 and Timer 1, that can be configured to operate in either timer mode or
external event counting mode.
• In timer function mode, the timer register is incremented once in each ma-
th
chine cycle i.e. the timer increment rate is 1/12 of the oscillator frequency
(fosc/12).
• In counter mode, external input pins are sampled during S5P2 of each machine
cycle, and if a high-low transition occurs across sampling times, the counter
register increments, with the count updated during S3P1 of the subsequent
machine cycle.
• The maximum count rate for external events is fosc/24.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 47 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers

• Timer 0 and Timer 1 can be configured as timer unit or counter unit by using
timer/ counter mode select bit of the special function register Timer/counter
Mode Control ( TMOD).
• Timer 0 and Timer 1 can be operated in four different modes. The mode
selection is done by the timer mode select bits of TMOD register.
• Timer/Counter Mode Control Register (TMOD) (SFR-89H):
Timer 1 Timer 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GATE C/T M1 M0 GATE C/T M1 M0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 48 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
The following table explains the meaning and use of each bit in the TMOD
register.
Bit Name Description
GATE Gating control when GATE is 1, the timer/counter will
be enabled only when the INT0 /INT1
line is high and run bit TR is enabled
in the TCON register. If GATE bit is 0,
timer/counter will be enabled only when
TR is enabled in the TCON register.
C/T Counter/Timer C/T = 0 configures the timer as a inter-
selector val timer (or time-delay generator), C/T
= 1 will configure the timer as an event
counter
M1 The Timer/Counter operation ‘mode se-
Mode select bits
lect’ bits.
M0 It can be one among the 4 modes.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 49 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
These are Timer/Counter mode select bit as per the below table.

M1 M0 Mode Operation
0 0 0 (13-bit timer mode) 13-bit timer/counter, 8-bit
of THx & 5-bit of TLx
0 1 1 (16-bit timer mode) 16-bit timer/counter, THx
cascaded with TLx
1 0 2 (8-bit auto-reload mode) 8-bit timer/counter (auto-
reload mode), TLx reload
with the value held by THx
each time TLx overflow
1 1 3 (split timer mode) Split the 16-bit timer into
two 8-bit timers i.e. THx
and TLx like two 8-bit timer

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 50 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
Timer/Counter Control Register (TCON) (SFR-88H)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TF1 TR1 TF0 TR 0 IE1 IT1 IE0 IT0
TF1 Timer/Counter 1 overflow flag: Set by hardware when timer/counter 1 overflows. The fl
ag is automatically cleared when timer 1 interrupt is vectored.
TR1 Timer/Counter 1 Run control: TR1=1 Start timer/counter1, TR1= 0 Stops timer/counter
1
TF0 Timer/Counter 0 overflow flag: Set by hardware when timer/counter 0 overflows. The flag
is automatically cleared when timer 0 interrupt is vectored.
TR0 Timer/Counter 0 Run control: TR0 = 1 Start Timer/Counter 0, TR0 = 0 Stops Timer/-
Counter 0
IE1 External Interrupt 1 edge detect flag: Set by hardware when external interrupt 1 edge is
detected. Cleared by hardware when interrupt is vectored
IT1 External Interrupt 1 type control: IT1 = 1 Configures the external interrupt 1 to edge
triggered (Falling Edge), IT1= 0 Configures the external interrupt 1 to level triggered (Low
level)
IE0 External interrupt 0 edge detect flag: Set by hardware when external interrupt 0 edge is
detected. Cleared by hardware when interrupt is vectored
IT0 External interrupt 0 type control: IT0 = 1 Configures the external interrupt 0 to edge
triggered (Falling edge), IT0 = 0 Configures the external interrupt 0 to level triggered (Low
level)
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 51 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
Timer/Counter in Mode 0
• Timer/Counter-x in mode 0 acts as a 13bit timer/counter for which 8 bits of
THx (Timer High) and 5 bits of TLx (Timer Low) are used.
• The timer/counter mode selection is done by the bit C/T of the register
TMOD.
• It is commonly used for generating precise delays and suitable for applications
where a 16-bit timer is needed.

Figue: Timer (Counter) 0/ Timer (Counter) 1 in Mode 0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 52 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
Timer/Counter in Mode 1
• Timer/Counter-x in mode 1 acts as a 16bit timer/counter for which 8 bits of
THx (Timer High) and 8 bits of TLx (Timer Low) are used.
• The timer/counter mode selection is done by the bit C/T of the register
TMOD.
• It is commonly used for generating delays.

Figue: Timer (Counter) 0/ Timer (Counter) 1 in Mode 1

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 53 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
Timer/Counter in Mode 2
• Timer/Counter-x in mode 0 acts as a 8bit timer/counter with auto reload on
the timer/counter register overflow.
• We load an 8-bit value into the THx (Timer High) register.
• When the timer starts, the TLx (Timer Low) value gets automatically loaded
from THx.
• TLx then starts counting from that value.
• When the timer overflows, it reloads the value from THx automatically.
• Mode 2 is commonly used for generating precise delays.

Figue: Timer (Counter) 0/ Timer (Counter) 1 in Mode 2

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 54 / 83
 Unit-II: 8051 Architecture [1]–[3] Timers

Timers
Timer/Counter in Mode 3
• Timer 0 in Mode 3 behaves as two completely separate 8-bit timers
• TL0 is an 8-bit interval timer/event counter controlled by Timer 0 control bits
(C/T, GATE, TR0, TF0 and INT0)
• TH0 is the only 8-bit interval timer controlled by Timer 1 control bits TR1
and TF1 and, therefore, controls the Timer 1 interrupt. Timer Mode 3 is also
referred as split timer mode.

Figue: Timer (Counter) 0 in Mode 3

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 55 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

Interrupts

• In microprocessor and microcontroller systems, an interrupt is defined as a

signal that initiates changes in normal program execution flow.
• Interrupts are used to get controller attention towards important events/activ-
ities.
• They allow the microcontroller system to respond to the asynchronous events
while another task is being executed; therefore, they give the illusion of handling
many tasks simultaneously.
• The asynchronous event means we do not know in advance when they will
occur.
• An interrupt can originate externally, from a connected device, or internally,
from the processor’s own units like timers, signaling the need for immediate
attention.
• The key distinction between call instructions and interrupts lies in their oc-
currence within a program. The call instructions are executed only from the
location where they are placed in a program. While interrupts are generated
anywhere and any time in a program, i.e. interrupts are asynchronous events.
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 56 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

Interrupts

Use of Interrupts
In any interrupt based systems, interrupts are mainly used for accomplishing
the following tasks:
• I/O data transfer between peripheral devices and processor/controller
• Timing applications
• Handling emergency situations (e.g. switch off the system when the battery
status falls below the critical limit in battery operated systems)
• Context switching/ Multitasking/Real-Time application programming
• Event driven programming

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 57 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

• The basic 8051 and its ROMless counterpart 8031AH supports five interrupt
sources.
• Three of them are internal interrupts:namely Timer 0 (TF0), Timer1 (TF1)
and Serial Port (TI or RI) interrupts.
• The remaining two are external interrupts INT0 and INT1. These external
interrupts are also referred as IE0 and IE1 respectively.
• For each interrupt source, there is a fixed location in the program memory that
contains its Interrupt Service Routine (ISR). This part of the memory which-
stores the ISRs is called the Interrupt Vector Table (IVT) which is shown in th
efollowing Table.

Interrupt source Interrupt vector address Interrupt type Interrupt flag clearing
External interrupt 0 (INT0) 0003H External Auto*
Timer 0 interrupt (TF0) 000BH Internal Auto
External interrupt 1 (INT1) 0013H External Auto*
Timer 1 interrupt (TF1) 001BH Internal Auto
Serial port interrupt (TI or RI) 0023H Internal By program

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 58 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Enabling Interrupts
• The interrupt system of 8051 can be enabled or disabled totally under software
control and achieved by setting or clearing the global interrupt enable bit of
the Special Function Register Interrupt Enable (IE).
• :The bit details of the Interrupt Enable (IE) (SFR- A8H) Register is as:
IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
EA RSD RSD ES ET1 EX1 ET0 EX0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 59 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Enabling Interrupts
The table given below explains the meaning and use of each bit.

Bit Name Description

EA Enable All EA = 0 disable all interrupts. EA = 1 enable all in-
terrupts, which are individually enabled by setting their
corresponding enable bit in Interrupt Enable SFR.
RSD Reserved Unimplemented. Reserved for future use
ES Enable Serial ES = 1 enables Serial Interrupt. ES = 0 disables
it
ET1 Enable Timer 1 ET1 = 1 enable Timer1 Interrupt. ET1 = 0
disables it
EX1 Enable External 1 EX1 = 1 enable External Interrupt 1. EX1
= 0 disables it
ET0 Enable Timer 0 ET0=1 enable Timer0 Interrupt. ET0=0 dis-
ables it
EX0 Enable External 0 EX0=1 enable External Interrupt 0. EX0 =
0 disables it
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 60 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Setting Interrupt Priorities

• In a Real World application, interrupts can occur at any time (asynchronous
behaviour) and different interrupts may occur simultaneously.
• This may confuse the processor on deciding which interrupt is to be serviced
first.
• This arbitration problem is resolved by setting interrupt priorities.
• Interrupt priority is configured under software control.
• The Special Function Register Interrupt Priority (IP) Register is the one holding
the interrupt priority settings for each interrupt.
• Interrupt Priority (IP) Register(IP) (SFR-B8H):The bit details of the In-
terrupt Priority Register is explained in the table below.
IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0
RSD RSD RSD PS PT1 PX1 PT0 PX0

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 61 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Setting Interrupt Priorities

• The table given below explains the meaning and use of each bit in the IP
register.

Bit Name Description

RSD Reserved Unimplemented. Reserved for future use
PS Serial interrupt priority PS = 1 sets priority to Serial Interrupt
PT1 Timer 1 interrupt priority PT1 = 1 sets priority to Timer1 Interrupt
PX1 External 1 interrupt priority PX1 = 1 sets priority to External Interrupt 1
PT0 Timer 0 interrupt priority PT0 = 1 sets priority to Timer 0 interrupt
PX0 External 0 interrupt priority EX0 = 1 sets priority to External interrupt 0
• The status of each interrupt flags are latched and updated during S5P2 of
every machine cycle
• The latched samples are polled during the following machine cycle. If the flag
for an enabled interrupt is found to be set in S5P2 of the previous cycle, the
interrupt system transfers the program flow to the corresponding interrupt’s
service routine in the code memory.
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 62 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Setting Interrupt Priorities

• Some general info on 8051 interrupts is given below:
• If two interrupt requests of different priority levels are received simultaneously,
the request of higher priority interrupt is serviced.
• If interrupt requests of the same priority level are received simultaneously, the
order in which the interrupt fl ags are polled internally is served first. First
polled first served. (Also known as internal polling sequence.)
• A low-priority interrupt can always be interrupted by a high priority interrupt.
• A low-priority interrupt in progress can never be interrupted by another low
priority interrupt.
• A high priority interrupt in progress cannot be interrupted by a low priority
interrupt or an interrupt of equal priority.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 63 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Different conditions blocking an Interrupt

It is not necessary that an interrupt should be serviced immediately on re-
quest.The following situations can block an interrupt request or delay the ser-
vicing of an interrupt request in 8051 architecture.
1. All interrupts are globally disabled by clearing the Enable All (EA) bit of Inter-
rupt Enable register.
2. The interrupt is individually disabled by clearing its corresponding enable bit
in the Interrupt Enable Register (IE).
3. An interrupt of higher priority or equal priority is already in progress.
4. The current polling machine cycle is not the final cycle in the execution of the
instruction in progress
5. The instruction in execution is RETI or a write to the IE/IP Register. (Ensures
the interrupt related instructions will not make any conflicts).

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 64 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Returning from an Interrupt Service Routine

• An Interrupt Service Routine should end with an RETI instruction as the last
executable instruction for the corresponding ISR.
• Executing the RETI instruction informs the interrupt system that the service
routine for the corresponding interrupt is fi nished and it clears the corre-
sponding priority-X (X=1 High priority) interrupt in progress flag by clearing
the corresponding flip flop.
• This enables the system to accept any interrupts with low priority or equal
priority of the interrupt which was just serviced.
• Executing the RETI instruction POPs (retrieves) the Program Counter (PC)
content from stack and the program fl ow is brought back to the point where
the interruption occurred.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 65 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Priority Levels for 8051 Interrupts

• By default the 8051 architecture supports two levels of priority which is already
explained in the previous sections.
• The first priority level is determined by the settings of the Interrupt Priority
(IP) register. The second level is determined by the internal hardware polling
sequence.
• The internal polling based priority within the same level of priority is listed
below in the descending order of priority.
Interrupt Priority
External interrupt 0 HIGHEST
Timer 0 overflow interrupt


External interrupt 1


Timer 1 overflow interrupt
y
Serial interrupt LOWEST

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 66 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

What Happens when an Interrupt Occurs?

On identifying the interrupt request number, the following actions are gener-
ated by the processor:
1. Complete the execution of instruction in progress.
2. The Program Counter (PC) content is pushed automatically to the stack.
Program Counter Low byte (PCL) is pushed first and Program Counter High
(PCH) byte is pushed next.
3. Clear the corresponding interrupt flags if the interrupt is a timer or external
interrupt (only for transition activated (edge triggered) configuration).
4. Set interrupt in progress flip flop.
5. Generate a long call ( LCALL) to the corresponding Interrupt Service Routine
address in the code memory (Known as vectoring of interrupt).

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 67 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Interrupt Latency
• Interrupt latency is the time elapsed between the assertion of the interrupt and
the start of the ISR for the same.
• Interrupt latency is highly signifi cant in real-time applications and is very
crucial in time-critical applications.
• Interrupt latency can happen due to various reasons.
• For external interrupts there is no synchronisation with the system (asyn-
chronous in behaviour) and so it can occur at any point of time.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 68 / 83
 Unit-II: 8051 Architecture [1]–[3] Interrupts

The 8051 Interrupt System

Interrupt Latency
• The processor latches each interrupt flag only at S5P2 of each machine cycle.
• So there is no point even if the interrupt occurs at S1P1 of the machine cycle.
• It is latched only at S5P2 of the current machine cycle
• The latched interrupts flags are polled at S5P2 of the following machine cycle
• An LCALL is generated to the corresponding ISR, if no other conditions block
the call.
• So this delay itself contributes a significant part in interrupt latency.
• The interrupt latency part which contributes the delay in servicing the ISR is
the sum of the following time delays: Time between the interrupt assertion to
the start of state S5 of current machine cycle (polling cycle) + (Time for S5
& S6) + Remaining machine cycles for the current instruction in execution

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 69 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

Basics of Serial Communication

• Computers transfer data in two ways:
– Parallel: Often 8 or more lines (wire conductors) are used to transfer data to
a device that is only a few feet away.
– Serial: To transfer to a device located many meters away, the serial method is
used. The data is sent one bit at a time.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 70 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

Basics of Serial Communication

• Serial data communication uses two methods
– Synchronous method transfers a block of data at a time
– Asynchronous method transfers a single byte at a time

• There are special IC’s made by many manufacturers for serial communications.

– UART (universal asynchronous Receiver transmitter)

– USART (universal synchronous-asynchronous Receiver- transmitter)

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 71 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port
Asynchronous – Start & Stop Bit

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 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

Data Transfer Rate

• The rate of data transfer in serial data communication is stated in bps (bits
per second).
• Another widely used terminology for bps is baud rate.
– It is modem terminology and is defined as the number of signal changes per
second
– In modems, there are occasions when a single change of signal transfers
several bits of data
• As far as the conductor wire is concerned, the baud rate and bps are the same.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 73 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

8051 Serial Port

• Synchronous and Asynchronous

• SCON Register is used to Control
• Data Transfer through TXd & RXd pins
• Some time - Clock through TXd Pin
• Four Modes of Operation:
Mode 0 Shift Register
Mode 1 :8-Bit UART with Timer Data Rate
Mode 2 :9-Bit UART with Set Data Rate
Mode 3 :9-Bit UART with Timer Data Rate

• Registers related to Serial Communication:

1 SBUF Register
2 SCON Register
3 PCON Register

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 74 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

8051 Serial Port

SBUF (Serial Data Buffer) Register – One Name-Two Registers

• SBUF is an 8-bit register used solely

for serial communication.
• A data byte must be written to SBUF
for transmission through the TXD
pin.
• Same way, it also holds a byte of data
received from RXD pin. Though
there is only one name (and, there-
fore, address) given to SBUF regis-
ter, there are two separate physical
registers—Transmit Buffer and Re-
ceive Buffer.
• These registers are differentiated by a
microcontroller as per the operation
being performed with them.
Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 75 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

Serial Control Register (SCON) (SFR-98H)

• SCON is a bit addressable Special Function Register holding the Serial Port
Control related bits.
• The details of SCON bits are given below.
SCON.7 SCON.6 SCON.5 SCON.4 SCON.3 SCON.2 SCON.1 SCON.0
SM0 SM1 SM2 REN TB8 RB8 TI RI

SM0 Used in setting the serial port operation mode

SM1 Used in setting the serial port operation mode
SM2 Multiprocessor communication fl ag:Enables multiprocessor I/O in Modes
2 and 3. When set to 1, an interrupt is generated if bit 9 of received data is
1, no interrupt is generated if bit 9 is 0. If Set to 1 for Mode 1, no interrupt
will be generated unless a valid stop bit is received. Clear to 0 for Mode 0.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 76 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

Serial Control Register (SCON) (SFR-98H)

REN Serial data reception enable:REN = 1 Enables, REN = 0 Disables serial
data reception
TB8 9th Data bit that will be transmitted in Modes 2 & 3. Setting/Clearing under
software control
RB8 9th Data bit received in Modes 2 & 3. Counterpart for TB8. In Mode 1, if
multiprocessor mode is disabled, RB8 will be the stop bit received in serial
transmission. RB8 is not used in Mode 0. RB8 is Software controllable
TI Transmit interrupt:Set by internal circuitry at the end of transmission of the
8th bit in Mode 0. For other modes it is set at the beginning of the stop bit
(9th bit). TI should be cleared by firmware.
RI Receive interrupt:Set by internal circuitry at the end of reception of the 8th
bit in Mode 0. For other modes it is set on half way of reception of the stop
bit (9th bit). RI should be cleared by firmware.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 77 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

8051 Serial Port – Mode 0

• The Mode 0 operation of serial port is same as that of the operation of a
clocked shift register.
• In Mode 0 operation Pin RXD (Port Pin P3.0) is used for transmitting and
receiving serial data and Pin TXD (Port Pin P3.1) outputs the shift clock.
• 8 data bits are transmitted in this mode with LSB first.
• The baudrate is fixed for this mode and it is 1/12 of the oscillator frequency.
• Mode 0 is half duplex, meaning it supports only unidirectional communication
at a time. It can be either transmission or reception.
• Serial data transmission is initiated by a write access to the SBUF register
(Any Instruction that uses SBUF as the destination register).

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 78 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

8051 Serial Port – Mode 1

• Mode 1 is a full duplex mode
• Serial data enters through RXD
• Serial data exits through TXD
• On receive, the stop bit goes into RB8 in SCON
• 10 bits are transmitted / received
1. Start bit (0)
2. Data bits (8)
3. Stop Bit (1)
• The baudrate is variable and it can be confi gured for different bauds and can
be determined by the Timer 1 over flow rate.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 79 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

8051 Serial Port – Mode 2

• Serial data enters through RXD
• Serial data exits through TXD
• 9th data bit (TB8) can be assign value 0 or 1
• On receive, the 9th data bit goes into RB8 in SCON
• 11 bits are transmitted / received
1. Start bit (0)
2. Data bits (9)
3. Stop Bit (1)
• Baud rate is programmable

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 80 / 83
 Unit-II: 8051 Architecture [1]–[3] Serial Port

Serial Port

8051 Serial Port – Mode 3

• Serial data enters through RXD
• Serial data exits through TXD
• 9th data bit (TB8) can be assign value 0 or 1
• On receive, the 9th data bit goes into RB8 in SCON
• 11 bits are transmitted / received
1. Start bit (0)
2. Data bits (9)
3. Stop Bit (1)
• Baud rate is determined by Timer 1 overflow rate.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 81 / 83
 References

References I
[1] R. Kamal, Embedded Systems Architecture Programming and Design, 2nd. The McGraw
Hill Companies, 2017.
[2] M. K. Patel, The 8051 Microcontroller Based Embedded Systems. McGraw Hill Education
(India) Private Limited, 2014, isbn: 9332901252; 9789332901254.
[3] K. Shibu, Introduction to embedded systems. Tata McGraw-Hill Education, 2009.

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 82 / 83
 References

Thank you
&
Any Query?

Dr. Ishwar Chandra Yadav (Ph.D. NIT Patna) February 21, 2024 83 / 83