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Low-power, high-speed dual modulus prescalers based on branch-merged

true single-phase clocked scheme

Article · March 2015

DOI: 10.1049/el.2014.4146

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Low-power, high-speed dual modulus
prescalers based on branch-merged true
single-phase clocked scheme SET Qn1 SET
Qn2
D Q D Q
Song Jia✉, Shilin Yan, Yuan Wang and Ganggang Zhang DFF1 DFF2
MC
CLR Q CLR Q
A new design scheme intended to improve the performance of true
single-phase clocked (TSPC) dual modulus prescalers is presented. CK
Two branches of TSPC D flip-flops are merged to reduce both
power and device count. An HSPICE simulation of the proposed
scheme demonstrates the highest power efficiency and best
power–delay product among the referenced designs. CK
CK CK Qn1 CK
M16 M1 M4 T2 M7
M10 M13
T1
Introduction: The power consumption of radio-frequency building S1 M17 M2 M6 Qn2
blocks presents a problem for long battery lifetimes in devices. The fre- M11 M14 S2 M5 M8
quency divider, which is also called a prescaler when working at the
MC CK CK
highest frequency, is a critical component for low-power design [1].
M12 M15 M18 M3 M9
The frequency synthesiser, which is usually implemented using a phase-
locked loop, is one of the most critical blocks for average power dissipa-
tion because it operates extensively for both reception and transmission DFF1 DFF2
purposes. This high power consumption occurs mainly because the first
stage of the frequency divider often dissipates half of the total power [2]. Fig. 2 Conventional divide-by-2/3 prescaler from [6]
A high-speed prescaler with low power consumption is thus highly
desirable. A schematic of the circuit introduced in [6] is shown in the lower part
Several prescaler topologies are available for the gigahertz range, of Fig. 2. Simple logic gates are absorbed into the TSPC DFFs to save
including metal–oxide-semiconductor (MOS), current-mode logic power and improve speed. Each DFF is clearly constructed using three
(CML), true single-phase clocked (TSPC) logic and extended TSPC TSPC branches.
(E-TSPC) logic [3]. The CML topology is commonly used to achieve In this Letter, we propose a novel scheme that focuses on reducing the
high operating frequencies, but dissipates high power. TSPC offers structure of the DFF1. In Fig. 2, we see that the first latch branches in the
high speed and low power, but cannot reach the speed of CML logic two DFFs can be merged to simplify the 2/3 prescaler. We therefore
[4]. E-TSPC uses dynamic logic similar to the TSPC logic, but has eliminate the first latch stage in the left DFF, including transistors
one less transistor per branch, improving the maximum operating M10, M11 and M12 in the design shown in Fig. 2, and connect nodes
speed at the cost of short-circuit current power. S1 and S2 together. The proposed divide-by-2/3 prescaler is shown in
In this Letter, a new design technique based on a branch-merged Fig. 3. The latch, which is composed of M1, M2 and M3, is actually
scheme is introduced to reduce TSPC prescaler power consumption shared by the two DFFs.
without sacrificing speed.

Design: TSPC logic gates refer to structures with a series of M10

critical path
single-phase-clock-controlled latches in their N-type MOS logic gates, M7
CK CK CK CK T2
P-type MOS logic gates or both. By cascading multiple stages of Qn1
M13 M16 M1 M4
basic TSPC logic gates, which can be regarded as clocked inverters, M6
T1 M17 M2 Qn2
M5
we can construct an edge-triggered TSPC D flip-flop (DFF) [5]. Fig. 1 S1 M14
S2 M8
shows a typical TSPC DFF consisting of three stages: an N latch, a CK
M15 CK
dynamic inverter and a P latch. CK CK
M18 M9
MC M3 M11
M12

DFF1 DFF2
M1 M4 M7
CK CK
Fig. 3 Proposed design based on branch-merged technique
Qb
M2 M5 M8 Since nodes S1 and S2 are now of the same node, the unnecessary
switching activity of the branch consisting of M10, M11 and M12 is
reduced. Moreover, the load capacitance of node Qn2, which lies on
D M3 M6 M9 the critical path, is reduced. This improvement thus helps to reduce
CK CK power and improve speed by reducing the number of transistors.
We also add an extra transistor, M10, to control the gate voltage of
M4. If Qn1 is low, then when CK jumps to low, it cannot charge
dynamic
node T1. Thus there is no short-circuit path passing through M4 and M6.
N latch inverter P latch The critical path is marked in Fig. 3, which appears similar to the
design shown in Fig. 2. The difference is that the critical path in the pro-
posed design contains M5, M7 and M11, but that of the design given in
Fig. 1 Typical three-branch edge-triggered TSPC DFF
[6] only contains M5 and M7. If M11 in the proposed design is elim-
inated, then the latch formed by M4 and M5 will become a ratioed
Conventional dual modulus prescaler designs can be based on these latch and node T1 cannot always reach a perfect logic high. This will
TSPC DFFs. Fig. 2 shows a divide-by-2/3 design from [6]. The logic then affect the speed of the discharge path consisting of M8 and M9,
structure, consisting of two DFFs and some simple logic circuitry, is and this path will become the new critical path. Simulation results
shown in the upper part of the Figure. The mode control (MC) deter- show that elimination of M11 will make the speed only slightly faster,
mines the output frequency from the second DFF to be either 1/2 or but at the cost of much higher power consumption. Therefore, to
1/3 of the clock frequency. In the divide-by-2 mode (MC = 0), node produce a better power-delay product (PDP), we retain M11 in the
Qn1 is fixed to be low and only the right half of the prescaler works. design.
The prescaler works like a TSPC DFF with feedback. In the divide-by-3 The proposed scheme can also be applied to a divide-by-4/5 structure,
mode (MC = 1), both DFFs work and the left half is responsible for as shown in Fig. 4. The prescaler contains three DFFs, and the first two
extending the output period by one clock cycle. DFFs share the latch branch composed of transistors M8, M9 and M10.

ELECTRONICS LETTERS 19th March 2015 Vol. 51 No. 6 pp. 464–465

 The improvement provided by the branch-merged scheme was verified The power curves of the proposed designs are much lower than those
by HSPICE simulations. of all other designs in both operating modes. The proposed designs
have the lowest power consumption, but can still work faster than all
other designs. The simulation results confirm that the proposed
designs can greatly reduce power consumption while operating with
comparable working speed.
SET SET SET
D Q D Q D Q

MC 0.5 mW [6]
Q Q Q
CLR CLR CLR [7]
CK [8]
0.4 mW
topology of divide-by-4/5 unit [9]
proposed 2/3
a 0.3 mW proposed 4/5

simplified no short-circuit
structure current power
0.2 mW
M1 M5 M8 M18 M21 M24
CK CK CK M10 M15 CK CK
Qn1 M11 X 0.1 mW
M2 T3
M9
T1 T2 Qn2
M6 M12 M22 Qn3
S2 M19
M3
CK
M16
S3
M25 0 mW

2 GHz
6 GHz
10 GHz
14 GHz
18 GHz
22 GHz
26 GHz
30 GHz
34 GHz

2 GHz
6 GHz
10 GHz
14 GHz
18 GHz
22 GHz
26 GHz
30 GHz
34 GHz
M7 M10 M13 M14 M20 M23
M4 CK M17 CK M26
CK CK CK
MC

a b
proposed structure of divide-by-4/5 unit

b Fig. 5 Power comparison between different prescalers

a Divide-by-n mode
Fig. 4 Proposed divide-by-4/5 prescaler based on branch-merged scheme b Divide-by-n + 1 mode
a Topology of divide-by-4/5 unit Conclusion: In this Letter, novel dual-modulus prescalers based on a
b Proposed structure of divide-by-4/5 unit
branch-merged technique are proposed. Simulations indicate that the
proposed design consumes less power than conventional designs and
achieves the highest PDP. In addition, the proposed designs can
Simulation results: A complete simulation and performance compar- operate at high speeds to meet the demand for high-frequency operation.
ison of the proposed prescalers with the reference designs [6–9] was
carried out. Design [6] shown in Fig. 1 and design [7] are based on
the TSPC scheme. Designs [8, 9] are TSPC and E-TSPC mixed struc- © The Institution of Engineering and Technology 2015
tures. Transistor sizes were chosen to provide good characteristic match- 26 November 2014
ing at the expense of power consumption. The HSPICE simulations doi: 10.1049/el.2014.4146
were based on the Semiconductor Manufacturing International Song Jia, Shilin Yan, Yuan Wang and Ganggang Zhang (Key
Corporation 40 nm CMOS process with a 1.1 V supply. Laboratory of Microelectronic Devices and Circuits, Institute of
The simulation results show that the proposed 2/3 prescaler can reach Microelectronics, Peking University, Beijing 100871, People’s
a maximum operating frequency of 30 GHz with a power consumption Republic of China)
of 0.118 and 0.151 mW in the divide-by-2 and divide-by-3 modes, ✉ E-mail: [email protected]
respectively. The proposed 4/5 prescaler can reach the same speed as
the referenced design with much better power performance. References
Table 1 summarises the design features and performance of the refer-
enced prescalers. The PDP is measured at the maximum working fre- 1 Gao, H., Sun, L., and Liu, J.: ‘Pulse swallow frequency divider with idle
DFFs automatically powered off’, Electron. Lett., 2012, 48, (11),
quency and can be regarded as the normalised power consumption or
pp. 636–638
the energy consumption per clock cycle. From Table 1, we see that 2 Guo, C., Zhu, S., Hu, J., Diao, J., Sun, H., and Lv, X.: ‘Design and
the divider in [8] has a high operating frequency, but poor power con- optimization of dual modulus prescaler using the extended
sumption. In contrast, the designs in [6, 7] do not reach such a high oper- true-single-phase-clock’. Microwave and Millimeter Wave Technology
ating frequency, but have better power consumption than that of design Conf. (ICMMT), Chengdu, China, May 2010
[8]. The proposed design can work at high frequencies like the E-TSPC 3 Pellerano, S., Levantino, S., Samori, C., and Lacaita, A.L.: ‘A 13.5 mW
designs, but still dissipates low power. The PDP of the proposed design 5 GHz frequency synthesizer with dynamic-logic frequency divider’,
is thus far better than the PDPs of the conventional designs, and is IEEE J. Solid-State Circuits, 2004, 39, (11), pp. 378–383
smaller by 58.8% in divide-by-2 operations and 49.5% in divide-by-3 4 Jung, M., et al.: ‘Design of a 12 GHz low-power extended true single
phase clock (E-TSPC) prescaler in 0.13 µm CMOS technology’. Proc.
operations than the best PDP of the referenced designs.
of 2011 Asia-Pacific, Microwave Conf. (APMC), Melbourne,
Australia, December 2011
Table 1: Features and performance of prescalers 5 Deng, Z., and Niknejad, A.: ‘The speed-power trade-off in the design of
Design parameter [6] [7] [8] Pro 2/3 [9] Pro 4/ CMOS true-single-phase-clock dividers’, IEEE J. Solid-State Circuits,
5 2010, 45, (11), pp. 2457–2465
Division ratio 2/3 2/3 2/3 2/3 4/5 4/5 6 Chen, W.-H., Roa, E., Loke, W.-F., and Jung, B.: ‘A 14.1 GHz dual-
modulus prescaler in 130 nm CMOS technology using sequential impli-
Number of transistors 20 21 22 18 34 29
cation logic cells’. 2012 IEEE Radio Frequency Integrated Circuits
Maximum frequency 6.67 10.4 23.8 30 17.9 17.9 Symp. (RFIC), Montreal, Canada, June 2012, pp. 341–344
(GHz)
7 Wu, J., Wang, Z., Ji, X., and Huang, C.: ‘A low-power high-speed true
Power (μW) n/n + 1 94.7/ 91.7/ 239/ 118/ 263/ 153/ single phase clock divide-by-2/3 prescaler’, IEICE Electron. Express,
168 124 505 151 313 197
2013, 10, (2), pp. 20 120 913–20 120 913
PDP (fJ) n/n + 1 14.2/ 8.82/ 10.4/ 3.81/ 14.7/ 8.55/ 8 Manthena, V.K., et al.: ‘A low-power single-phase clock multiband flex-
25.2 11.9 21.2 4.87 17.5 11 ible divider’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012,
20, (2), pp. 376–380
9 Jau, T.-S., Yang, W.-B., and Lo, Y.-L.: ‘A new dynamic floating input D
Fig. 5 shows the detailed power against clock frequency simulation flip-flop (DFIDFF) for high speed and ultra low voltage divided-by 4/5
results for the prescalers listed in Table 1 in the divide-by-n and prescaler’. IEEE Int. Conf. on Electronics, Circuits and Systems
divide-by-n + 1 modes. The charts show that the prescaler in [8] can (ICECS), Nice, France, December 2006, pp. 902–905
work at high frequencies, but at the cost of high power consumption.

ELECTRONICS LETTERS 19th March 2015 Vol. 51 No. 6 pp. 464–465

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