SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD2829T

Advanced Information

MIPI D-PHY Tx Bridge Chip

This document contains information on a new product. Specifications and information herein are subject to change
without notice.

http://www.solomon-systech.com
SSD2829T Rev 1.2 P 1/159 Feb 2018 Copyright  2018 Solomon Systech Limited
 Appendix: IC Revision history of SSD2829T Specification

Version Change Items Effective Date

st
1.0 1 Release 14-Mar-17
1. Added Power up/off sequence 17-Jul-17
1.1 2. Change PEN range in 0xBA from “501 to 1000” to “501 to 1500”
3. Change PLL configuration, from 5MHz<fIN=<100 to 5MHz<fIN=<40MHz
1. Revised 1.2V power supply to 1.3V 02-Mar-18
2. Revised DC operating condition
3. Revised DC characteristic
4. Added “Support MIPI DSI standard version 2.0” to feature list
5. Corrected MCU mode type B timing to match with type A
6. Added VDDIO 3.3V and VCIP current consumption for DC characteristic
7. Reserved VID_COMPRESSED_BYTE_COUNT of 0xC8
1.2 8. Reserved BYP_BIT_DIV of 0xBB
9. Revised 0xBA bit[15:14] from PEN to FR
10. Added mipi timing description of 0xBA
11. Added mipi timing description of 0xBB
12. Added mipi timing description of 0xC9
13. Added mipi timing description of 0xCA
14. Added mipi timing description of 0xCB
15. Added mipi timing description of 0xCC

Solomon Systech Feb 2018 P 2/159 Rev 1.2 SSD2829T

CONTENTS
1 GENERAL DESCRIPTION ....................................................................................................9
2 FEATURES ..............................................................................................................................9
3 ORDERING INFORMATION ................................................................................................9
4 BLOCK DIAGRAM ............................................................................................................... 10
5 FUNCTIONAL DESCRIPTION ........................................................................................... 11
5.1 RGB INTERFACE .......................................................................................................................................... 11
5.2 COMMAND INTERFACE.................................................................................................................................. 11
5.3 DATA BUFFER .............................................................................................................................................. 11
5.4 COMMAND BUFFER....................................................................................................................................... 11
5.5 MIPI DSI-TX ............................................................................................................................................... 11
5.6 XTAL OSC .................................................................................................................................................. 13
5.7 PLL ............................................................................................................................................................. 13
5.8 PMU ............................................................................................................................................................ 13
6 PIN ARRANGEMENT .......................................................................................................... 14
6.1 128 PINS LQFP ............................................................................................................................................. 14
7 PIN DESCRIPTIONS ............................................................................................................ 16
7.1 POWER SUPPLY PIN ...................................................................................................................................... 16
7.2 MIPI PIN ...................................................................................................................................................... 16
7.3 CONTROL SIGNAL PIN ................................................................................................................................... 17
7.4 INTERFACE LOGIC PIN .................................................................................................................................. 18
8 COMMAND TABLE ............................................................................................................. 19
8.1 LOCAL REGISTERS (NON-APB) DESCRIPTIONS ............................................................................................... 19
8.1.1 RGB Interface Control Register 1 ......................................................................................................... 19
8.1.2 RGB Interface Control Register 2 ......................................................................................................... 20
8.1.3 RGB Interface Control Register 3 ......................................................................................................... 22
8.1.4 RGB Interface Control Register 4 ......................................................................................................... 23
8.1.5 RGB Interface Control Register 5 ......................................................................................................... 24
8.1.6 RGB Interface Control Register 6 ......................................................................................................... 25
8.1.7 Configuration Register ......................................................................................................................... 28
8.1.8 Virtual Channel Control Register.......................................................................................................... 31
8.1.9 PLL Control Register............................................................................................................................ 33
8.1.10 PLL Configuration Register .................................................................................................................. 34
8.1.11 Clock Control Register ......................................................................................................................... 35
8.1.12 Packet Size Control Register 1 .............................................................................................................. 36
8.1.13 Packet Size Control Register 2 .............................................................................................................. 38
8.1.14 Packet Size Control Register 3 .............................................................................................................. 39
8.1.15 Packet Drop Register............................................................................................................................ 40
8.1.16 Operational Control Register................................................................................................................ 41
8.1.17 Maximum Return Size Register ............................................................................................................. 43
8.1.18 Return Data Count Register .................................................................................................................. 44
8.1.19 Acknowledge Response Status Register ................................................................................................. 45
8.1.20 Line Control Register ........................................................................................................................... 46
8.1.21 Interrupt Control Register .................................................................................................................... 49
8.1.22 Interrupt Status Register ....................................................................................................................... 52
8.1.23 Error Status Register ............................................................................................................................ 56
8.1.24 Compressed Register ............................................................................................................................ 60
8.1.25 Delay Adjustment Register 1 ................................................................................................................. 61
8.1.26 Delay Adjustment Register 2 ................................................................................................................. 62
8.1.27 Delay Adjustment Register 3 ................................................................................................................. 63
8.1.28 Delay Adjustment Register 4 ................................................................................................................. 64
8.1.29 Delay Adjustment Register 5 ................................................................................................................. 65

SSD2829T Rev 1.2 P 3/159 Feb 2018 Solomon Systech

 8.1.30 Delay Adjustment Register 6 ................................................................................................................. 66
8.1.31 HS TX Timer Register 1 ........................................................................................................................ 67
8.1.32 HS TX Timer Register 2 ........................................................................................................................ 68
8.1.33 TE Status Register ................................................................................................................................ 69
8.1.34 SPI Read Register................................................................................................................................. 71
8.1.35 PLL Lock Register ................................................................................................................................ 72
8.1.36 Test Register ........................................................................................................................................ 73
8.1.37 TE Count Register ................................................................................................................................ 75
8.1.38 Analog Control Register 1 .................................................................................................................... 76
8.1.39 RGB Interface Control Register 7 ......................................................................................................... 78
8.1.40 INOUT Configuration Control Register ................................................................................................ 80
8.1.41 APB Write Register .............................................................................................................................. 82
8.1.42 APB Read Register ............................................................................................................................... 83
8.2 LOCAL (APB) REGISTER DESCRIPTIONS ........................................................................................................ 84
8.2.1 SCM Registers Descriptions ................................................................................................................. 85
8.2.1.1 SCM Miscellaneous Control Register ................................................................................................ 85
8.2.1.2 SCM Scratch Register ....................................................................................................................... 87
8.2.2 Video BIST Register Descriptions ......................................................................................................... 88
8.2.2.1 Video BIST Register 0 ...................................................................................................................... 88
8.2.2.2 Video BIST Register 1 ...................................................................................................................... 89
8.2.2.3 Video BIST Register 2 ...................................................................................................................... 90
8.2.2.4 Video BIST Register 3 ...................................................................................................................... 91
8.2.2.5 Video BIST Register 4 ...................................................................................................................... 92
8.2.2.6 Video BIST Register 5 ...................................................................................................................... 93
8.2.2.7 Video BIST Register 6 ...................................................................................................................... 94
8.2.3 Pixel Peek Registers Descriptions ......................................................................................................... 95
8.2.3.1 Pixel Peek Register 0 ........................................................................................................................ 95
8.2.3.2 Pixel Peek Register 1 ........................................................................................................................ 96
8.2.3.3 Pixel Peek Register 2 ........................................................................................................................ 97
8.2.3.4 Pixel Peek Register 3 ........................................................................................................................ 98
9 MAXIMUM RATINGS .......................................................................................................... 99
10 DC OPERATING CONDITIONS ......................................................................................... 99
10.1 DC CHARACTERISTICS ......................................................................................................................... 100
11 AC CHARACTERISTICS ................................................................................................... 101
11.1 POWER UP TIMING...................................................................................................................................... 101
11.2 RESET TIMING .......................................................................................................................................... 101
11.3 INTERFACE TIMING ..................................................................................................................................... 102
11.3.1 MCU Interface (Type A) Timing.......................................................................................................... 102
11.3.2 MCU Interface (Type B) Timing.......................................................................................................... 103
11.3.3 SPI Interface Timing........................................................................................................................... 105
11.3.4 RGB Interface Timing ......................................................................................................................... 106
12 POWER UP SEQUENCE .................................................................................................... 107
13 POWER OFF SEQUENCE.................................................................................................. 108
14 MIPI DPHY CHARACTERISTICS .................................................................................... 109
14.1 MIPI DPHY HS CHARACTERISTICS ...................................................................................................... 111
15 OPERATING MODE........................................................................................................... 114
15.1 PROGRAMMING MODEL .............................................................................................................................. 114
15.1.1 Access Local (non-APB) Registers ...................................................................................................... 115
15.1.2 Access Local (APB) Registers for Write .............................................................................................. 116
15.1.3 Access APB Registers for Read ........................................................................................................... 117
15.2 SPI INTERFACE ........................................................................................................................................... 119
15.2.1 SPI Interface 8-Bit 4 Wire................................................................................................................... 119
15.2.2 SPI Interface 8-Bit 3 Wire................................................................................................................... 121

Solomon Systech Feb 2018 P 4/159 Rev 1.2 SSD2829T

 15.2.3 SPI Interface 24-Bit 3 Wire ................................................................................................................. 123
15.3 MCU INTERFACE ........................................................................................................................................ 125
15.3.1 MCU Interface Type A, fixed E mode .................................................................................................. 125
15.3.2 MCU Interface Type A, Clocked E mode ............................................................................................. 127
15.3.3 MCU Interface Type B ........................................................................................................................ 129
15.3.4 MCU Interface for MIPI Command Packet ......................................................................................... 131
15.3.5 MCU Interface for Local Registers ..................................................................................................... 132
15.4 RGB INTERFACE ........................................................................................................................................ 133
15.5 VIDEO MODE USE CASES ............................................................................................................................ 133
15.5.1 RGB + SPI ......................................................................................................................................... 133
15.5.1.1 Interleaving Non-Video Packets with Video Packets.................................................................... 136
15.5.2 Interrupt Operation ............................................................................................................................ 137
15.5.3 Internal Buffer Status.......................................................................................................................... 139
15.6 COMMAND MODE USE CASES ..................................................................................................................... 140
15.6.1 Write Operation ................................................................................................................................. 141
15.6.2 Read Operation .................................................................................................................................. 142
15.7 VIDEO TO COMMAND MODE CONVERSION ................................................................................................... 143
15.7.1 Example of switching sequence ........................................................................................................... 144
15.8 STATE MACHINE OPERATION ....................................................................................................................... 144
15.9 PHY CONTROLLER OPERATION ................................................................................................................... 145
15.10 PLL CONFIGURATION ............................................................................................................................. 145
15.11 CLOCK SOURCE E XAMPLE ....................................................................................................................... 146
15.12 ACKNOWLEDGEMENT OPERATION ........................................................................................................... 147
15.13 TEARING EFFECT (TE) OPERATION .......................................................................................................... 149
15.13.1 Using IO Pins ................................................................................................................................. 149
15.13.2 Using MIPI Escape Mode ............................................................................................................... 150
15.14 CONTENTION DETECTION AND TIMER OPERATION ................................................................................... 150
15.15 VIDEO BIST ........................................................................................................................................... 151
15.16 PIXEL PEEK ............................................................................................................................................ 156
15.17 IMAGE FLIPPING (HORIZONTAL) .............................................................................................................. 157
16 PACKAGE INFORMATION .............................................................................................. 158
16.1 QFP 128 PINS (14MM X 14MM) .................................................................................................................... 158

SSD2829T Rev 1.2 P 5/159 Feb 2018 Solomon Systech

TABLES
TABLE 3-1: ORDERING INFORMATION ............................................................................................................................. 9
TABLE 5-1: DSI-TX SUPPORT FORMAT ......................................................................................................................... 12
TABLE 5-2 SSD2829T RGB DATA ARRANGEMENT ........................................................................................................ 13
TABLE 6-1: LQFP PIN ASSIGNMENT TABLE .................................................................................................................. 15
TABLE 7-1: POWER SUPPLY PIN DESCRIPTION ............................................................................................................... 16
TABLE 7-2: MIPI PIN DESCRIPTION .............................................................................................................................. 16
TABLE 7-3: CONTROL SIGNAL PIN DESCRIPTION ........................................................................................................... 17
TABLE 7-4: MCU/RGB INTERFACE DESCRIPTION ......................................................................................................... 18
TABLE 7-5: SPI INTERFACE DESCRIPTION ..................................................................................................................... 18
TABLE 8-1: RGB INTERFACE CONTROL REGISTER 1 DESCRIPTION ................................................................................. 19
TABLE 8-2: RGB INTERFACE CONTROL REGISTER 2 DESCRIPTION ................................................................................. 20
TABLE 8-3: RGB INTERFACE CONTROL REGISTER 3 DESCRIPTION ................................................................................. 22
TABLE 8-4: RGB INTERFACE CONTROL REGISTER 4 DESCRIPTION ................................................................................. 23
TABLE 8-5: RGB INTERFACE CONTROL REGISTER 5 DESCRIPTION ................................................................................. 24
TABLE 8-6: RGB INTERFACE CONTROL REGISTER 6 DESCRIPTION ................................................................................. 25
TABLE 8-7: RGB DATA ARRANGEMENT ........................................................................................................................ 27
TABLE 8-8: CONFIGURATION REGISTER DESCRIPTION ................................................................................................... 28
TABLE 8-9: VIRTUAL CHANNEL CONTROL REGISTER DESCRIPTION ............................................................................... 31
TABLE 8-10: PLL CONTROL REGISTER DESCRIPTION .................................................................................................... 33
TABLE 8-11: PLL CONFIGURATION REGISTER DESCRIPTION .......................................................................................... 34
TABLE 8-12: CLOCK CONTROL REGISTER DESCRIPTION ................................................................................................ 35
TABLE 8-13: PACKET SIZE REGISTER 1 DESCRIPTION .................................................................................................... 36
TABLE 8-14: PACKET SIZE REGISTER 2 DESCRIPTION .................................................................................................... 38
TABLE 8-15: PACKET SIZE REGISTER 3 DESCRIPTION .................................................................................................... 39
TABLE 8-16: PACKET DROP REGISTER DESCRIPTION ..................................................................................................... 40
TABLE 8-17: OPERATIONAL CONTROL REGISTER DESCRIPTION ..................................................................................... 41
TABLE 8-18: MAXIMUM RETURN SIZE REGISTER DESCRIPTION ..................................................................................... 43
TABLE 8-19: RETURN DATA COUNT REGISTER DESCRIPTION ......................................................................................... 44
TABLE 8-20: ACKNOWLEDGE RESPONSE STATUS REGISTER DESCRIPTION ..................................................................... 45
TABLE 8-21: LINE CONTROL REGISTER DESCRIPTION .................................................................................................... 46
TABLE 8-22: INTERRUPT CONTROL REGISTER DESCRIPTION .......................................................................................... 49
TABLE 8-23: INTERRUPT STATUS REGISTER DESCRIPTION ............................................................................................. 52
TABLE 8-24: ERROR STATUS REGISTER DESCRIPTION ................................................................................................... 56
TABLE 8-25: COMPRESSED REGISTER DESCRIPTION ...................................................................................................... 60
TABLE 8-26: DELAY ADJUSTMENT REGISTER 1 DESCRIPTION ........................................................................................ 61
TABLE 8-27: DELAY ADJUSTMENT REGISTER 2 DESCRIPTION ........................................................................................ 62
TABLE 8-28: DELAY ADJUSTMENT REGISTER 3 DESCRIPTION ........................................................................................ 63
TABLE 8-29: DELAY ADJUSTMENT REGISTER 4 DESCRIPTION ........................................................................................ 64
TABLE 8-30: DELAY ADJUSTMENT REGISTER 5 DESCRIPTION ........................................................................................ 65
TABLE 8-31: DELAY ADJUSTMENT REGISTER 6 DESCRIPTION ........................................................................................ 66
TABLE 8-32: HS TX TIMER REGISTER 1 DESCRIPTION ................................................................................................... 67
TABLE 8-33: HS TX TIMER REGISTER 2 DESCRIPTION ................................................................................................... 68
TABLE 8-34: TE STATUS REGISTER DESCRIPTION ......................................................................................................... 69
TABLE 8-35: SPI READ REGISTER DESCRIPTION ............................................................................................................ 71
TABLE 8-36: PLL LOCK REGISTER DESCRIPTION .......................................................................................................... 72
TABLE 8-37: TEST REGISTER DESCRIPTION ................................................................................................................... 73
TABLE 8-38: TE COUNT REGISTER DESCRIPTION .......................................................................................................... 75
TABLE 8-39: ANALOG CONTROL REGISTER 1 DESCRIPTION ........................................................................................... 76
TABLE 8-40: RGB INTERFACE CONTROL REGISTER 7 DESCRIPTION ............................................................................... 78
TABLE 8-41: INOUT CONFIGURATION REGISTER DESCRIPTION..................................................................................... 80
TABLE 8-42: DELAY ADJUSTMENT REGISTER DESCRIPTION ........................................................................................... 82
TABLE 8-43: APB READ REGISTER DESCRIPTION .......................................................................................................... 83
TABLE 8-44: SCM MISCELLANEOUS CONTROL DESCRIPTION ........................................................................................ 85
TABLE 8-45: SCM SCRATCH REGISTER DESCRIPTION ................................................................................................... 87
TABLE 8-46: VIDEO BIST REGISTER 0 DESCRIPTION ..................................................................................................... 88
TABLE 8-47: VIDEO BIST REGISTER 1 DESCRIPTION ..................................................................................................... 89
TABLE 8-48: VIDEO BIST REGISTER 2 DESCRIPTION ..................................................................................................... 90
TABLE 8-49: VIDEO BIST REGISTER 3 DESCRIPTION ..................................................................................................... 91

Solomon Systech Feb 2018 P 6/159 Rev 1.2 SSD2829T

TABLE 8-50: VIDEO BIST REGISTER 4 DESCRIPTION ..................................................................................................... 92
TABLE 8-51: VIDEO BIST REGISTER 5 DESCRIPTION ..................................................................................................... 93
TABLE 8-52: VIDEO BIST REGISTER 6 DESCRIPTION ..................................................................................................... 94
TABLE 8-53: PIXEL PEEK REGISTER 0 DESCRIPTION ...................................................................................................... 95
TABLE 8-54: PIXEL PEEK REGISTER 1 DESCRIPTION ...................................................................................................... 96
TABLE 8-55: PIXEL PEEK REGISTER 2 DESCRIPTION ...................................................................................................... 97
TABLE 8-56: PIXEL PEEK REGISTER 3 DESCRIPTION ...................................................................................................... 98
TABLE 9-1: MAXIMUM RATINGS (VOLTAGE REFERENCED TO VSS)................................................................................. 99
TABLE 10-1 : RECOMMENDED OPERATING CONDITIONS ................................................................................................ 99
TABLE 11-1 MCU INTERFACE (TYPE A) TIMING CHARACTERISTICS ............................................................................ 102
TABLE 11-2: MCU INTERFACE (TYPE B) TIMING CHARACTERISTICS ........................................................................... 103
TABLE 11-3 RGB INTERFACE TIMING CHARACTERISTICS ............................................................................................ 106
TABLE 14-1 : CLOCK SIGNAL SPECIFICATION .............................................................................................................. 110
TABLE 14-2 HS TRANSMITTER DC SPECIFICATIONS .................................................................................................... 111
TABLE 14-3 HS TRANSMITTER AC SPECIFICATIONS .................................................................................................... 111
TABLE 14-4 LP TRANSMITTER DC SPECIFICATIONS .................................................................................................... 112
TABLE 14-5 LP TRANSMITTER AC SPECIFICATIONS .................................................................................................... 113
TABLE 13-1: SSD2829T LOCAL REGISTER MAP ......................................................................................................... 114
TABLE 15-2: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE FOR LEGACY REGISTERS ........................... 115
TABLE 15-3: MCU INTERFACE DATA PIN MAPPING FOR LEGACY REGISTER ................................................................ 115
TABLE 15-4: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE FOR E XTENDED REGISTERS WRITE ............ 116
TABLE 15-5: MCU INTERFACE DATA PIN MAPPING FOR E XTENDED REGISTERS WRITE ................................................ 116
TABLE 15-6: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE FOR E XTENDED REGISTERS READ .............. 117
TABLE 15-7: MCU INTERFACE DATA PIN MAPPING FOR E XTENDED REGISTERS ADDRESS SET ..................................... 117
TABLE 15-8: MCU INTERFACE DATA PIN MAPPING FOR E XTENDED REGISTERS ADDRESS SET ..................................... 118
TABLE 15-9: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE ................................................................. 131
TABLE 15-10: MCU INTERFACE DATA PIN MAPPING FOR PARAMETER CYCLES ........................................................... 132

SSD2829T Rev 1.2 P 7/159 Feb 2018 Solomon Systech

FIGURES
FIGURE 4-1: SSD2829T BLOCK DIAGRAM .................................................................................................................... 10
FIGURE 6-1 : PINOUT DIAGRAM – 128 PINS LQFP (TOPVIEW) ........................................................................................ 14
FIGURE 11-1 MCU INTERFACE (TYPE A) TIMING DIAGRAM ........................................................................................ 102
FIGURE 11-2 SPI INTERFACE TIMING CHARACTERISTICS ............................................................................................. 105
FIGURE 11-3: SPI INTERFACE TIMING DIAGRAM ........................................................................................................ 105
FIGURE 11-4: RGB INTERFACE TIMING DIAGRAM ....................................................................................................... 106
FIGURE 14-1 D-PHY SIGNALING LEVELS.................................................................................................................... 109
FIGURE 14-2 DDR CLOCK DEFINITION ....................................................................................................................... 109
FIGURE 15-1: SPI INTERFACE 8-BIT 4 WIRE FOR WRITE ................................................................................................ 119
FIGURE 15-2: SPI INTERFACE 8-BIT 4 WIRE FOR READ ................................................................................................. 120
FIGURE 15-3: SPI INTERFACE 8-BIT 3 WIRE FOR WRITE ................................................................................................ 121
FIGURE 15-4: SPI INTERFACE 8-BIT 3 WIRE FOR READ ................................................................................................. 122
FIGURE 15-5: SPI INTERFACE 24-BIT 3 WIRE FOR WRITE .............................................................................................. 123
FIGURE 15-6: SPI INTERFACE 24-BIT 3 WIRE FOR READ ................................................................................................ 124
FIGURE 15-7: ILLUSTRATION OF WRITE OPERATION FOR TYPE A, FIXED E MODE INTERFACE ....................................... 126
FIGURE 15-8: ILLUSTRATION OF READ OPERATION FOR TYPE A, FIXED E MODE INTERFACE ........................................ 126
FIGURE 15-9: ILLUSTRATION OF WRITE OPERATION FOR TYPE A, CLOCKED E MODE INTERFACE ................................. 127
FIGURE 15-10: ILLUSTRATION OF READ OPERATION FOR TYPE A, CLOCKED E MODE INTERFACE ................................. 128
FIGURE 15-11: ILLUSTRATION OF WRITE OPERATION FOR TYPE B INTERFACE .............................................................. 129
FIGURE 15-12: ILLUSTRATION OF READ OPERATION FOR TYPE B INTERFACE ............................................................... 130
FIGURE 15-13: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC PULSES .............. 135
FIGURE 15-14: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC EVENTS AND BURST
MODE ................................................................................................................................................................ 135
FIGURE 16-1: PACKAGE INFORMATION – LQFP 128 PINS ............................................................................................ 158

Solomon Systech Feb 2018 P 8/159 Rev 1.2 SSD2829T

1 GENERAL DESCRIPTION

SSD2829T is a MIPI master bridge chip that converts RGB / MCU interface to MIPI DPHY DSI Output.
For RGB interface, it can support resolution up to WQHD (2560x1600) (native) and UHD (4096x2160)
(compressed in/out) format with 60Hz refresh rate.
For MCU interface, it can support resolution up to WQHD (2560x1600) (native) and UHD (4096x2160)
(compressed in/out) format with 30Hz refresh rate.

2 FEATURES
 Support panel at refresh rate of 60Hz with resolution up to
- WQHD (2560x1600) (native)
- UHD (4096 x 2160) (compressed in/out)
 Support MIPI DSI standard version 2.0
 Support MIPI D-PHY standard version 1.1
 Support MIPI DCS standard version 2.0
 Support 2 MIPI D-option DSI engines with throughput up to 12Gbps using 8 D-PHY lanes for each
DSI-TX (Each lane is up to 1.5Gbps)
 Support single or dual DSI mode at DSI-TX output
 Support 16, 18, 24-bit per pixel color
 Support MCU interface (DBI version 2.0) up to 24-bits bus width at the input
 Support RGB interface (DPI version 2.0) 48-bits bus width with SDR or DDR pixel clock at the input
 Support serial SPI interface (DBI version 2.0) up to 16-bits at the input
 Support both Video and Command mode
 Support input Left-right or odd-even split in the RGB input
 Support Video BIST generation at the DSI-TX output with different color patterns
 Support Burst or Non-burst video modes
 Each DSI-TX port can control the number of lane independently
 On-chip PLL with variable output frequency
 Power supply: (VDDD and VDDA) 1.3V +/-10%
 IO Power supply: 1.8V +/-10% or 3.3V +/-10%

3 ORDERING INFORMATION
Table 3-1: Ordering Information

Ordering Part Number Package Form

SSD2829TQL9 LQFP 128L, 14mm x 14mm

SSD2829T Rev 1.2 P 9/159 Feb 2018 Solomon Systech

4 BLOCK DIAGRAM

Figure 4-1: SSD2829T Block Diagram

xtal_in/
out
XTAL
PLL
OSC

RGB
RGB Interface

MIPI
Data Buffer DPHY DSI TX
1
MIPI
DSI
TX
Command MIPI
MCU Buffer DPHY DSI TX
Command
1
Interface
SPI

Local
Register

APB Master PMU

Solomon Systech Feb 2018 P 10/159 Rev 1.2 SSD2829T

5 FUNCTIONAL DESCRIPTION
5.1 RGB Interface

The RGB interface receives parallel video data and routes them to the data buffer. The RGB interface supports
2 pixels per PCLK cycle. The RGB interface input is 48-bit wide and it supports 2-pixels per RGB module
using SDR or DDR input pixel clock. The maximum speed for the RGB interface is 160MHz.

5.2 Command Interface

The Command interface receives parallel MCU data or SPI data and routes them to the command buffer. The
MCU interface supports 8-bit, 16-bit and 24-bit data width. The maximums speed for the MCU interface is
160MHz.

5.3 Data Buffer

The data buffer consists of line buffers to store one line worth of video data before packetizing them for MIPI
TX transmission. Data for command 0x2C and 0x3C also make use of the data buffer for storage, instead of
going to the command buffer.
There are one line buffer per MIPI DSI TX port. For DSI TX0, the line buffer size is 2560 pixels. For DSI
TX1, the size is 2064 pixels. Dual DSI TX port can support up to 2 x 2064 = 4128 pixels.

5.4 Command Buffer

The command buffer consist of a 4096 bytes deep FIFO to store commands before packetizing them to
command packets for MIPI TX transmission. Command 0x2C and 0x3C are excluded in this command buffer.
They are routed to use data buffer instead.
There are one command FIFO per MIPI DSI TX port.

5.5 MIPI DSI-Tx

MIPI DSI-TX is a dual DSI TX module, up to 8 lanes for D-option.

Each DSI is 1.5Gbps per lane for D-option.

The main features of MIPI DSI-TX transmitter pairs are,

 Dual DSI-TX D-option up to 8-lanes
 4 lanes for each DSI-TX D-option
 Support up to 2560 pixel/line for 1 DSI
 Up to 1.5Gbps per lane for each D-option lane or 12Gbps for 2 DSI DPHY
 Single or dual DSI mode
 Support 16, 18, 24-bit per pixel
 Support burst or non-burst mode
 Support new commands in DSI-2, such as Execute Queue, Scrambler On/Off, Compressed packets
 Support MIPI Alliance Standard for Display Serial Interface-2, version 1
 Support MIPI Alliance Standard for Display Command Set, version 1.02
 Support MIPI Alliance Standard for D-PHY, version 1.00

The MIPI packets that are supported by MIPI DSI-TX are listed in the table below.

SSD2829T Rev 1.2 P 11/159 Feb 2018 Solomon Systech

 Table 5-1: DSI-TX Support Format

Data Type Data Type Type Description

(Hex) (Bin)
0x01 00 0001 Short Sync Event V Start
0x11 01 0001 Short Sync Event V End
0x21 10 0001 Short Sync Event H Start
0x31 11 0001 Short Sync Event H End
0x08 00 1000 Short End of Transmission (EoT)
0x02 00 0010 Short Color Mode (CM) Off
0x12 01 0010 Short Color mode (CM) On
0x22 10 0010 Short Shut Down Peripheral
0x32 11 0010 Short Turn On Peripheral
0x03 00 0011 Short Generic Short Write, no parameter
0x13 01 0011 Short Generic Short Write, 1 parameter
0x23 10 0011 Short Generic Short Write, 2 parameters
0x04 00 0100 Short Generic Read, no parameter
0x14 01 0100 Short Generic Read, 1 parameter
0x24 10 0100 Short Generic Read, 2 parameters
0x05 00 0101 Short DCS Short Write, no parameter
0x15 01 0101 Short DCS Short Write, 1 parameter
0x06 00 0110 Short DCS Read, no parameter
0x16 01 0110 Short Execute Queue
0x37 11 0111 Short Set Maximum Return Packet Size
0x27 10 0111 Short Scrambling Mode Command
0x09 00 1001 Long Null Packet
0x19 01 1001 Long Blanking Packet
0x39 11 1001 Long DCS Long Write
0x0A 00 1010 Long Picture Parameter Set
0x0B 00 1011 Long Compressed Pixel Stream
0x0E 00 1110 Long Packed Pixel Stream, 16-bit RGB, 5-6-5 Format
0x1E 01 1110 Long Packed Pixel Stream, 18-bit RGB, 6-6-6 Format
0x2E 10 1110 Long Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6
Format
0x3E 11 1110 Long Packed Pixel Stream, 24-bit RGB, 8-8-8 Format
0x02 00 0010 Short Acknowledge and Error Report
0x11 01 0001 Short Generic Short Read Response, 1 byte returned
0x12 01 0010 Short Generic Short Read Response, 2 bytes returned

Solomon Systech Feb 2018 P 12/159 Rev 1.2 SSD2829T

 Data Type Data Type Type Description
(Hex) (Bin)
0x1A 01 1010 Long Generic Long Read Response
0x1C 01 1100 Long DCS Long Read Response
0x21 10 0001 Short DCS Short Read Response, 1 byte returned
0x22 10 0010 Short DCS Short Read Response, 2 bytes returned

MIPI DSI Link controller provides MIPI DSI packet assembly and disassembly. During transmission, it will
form the DSI packet according to the instruction from the state machine. During reception, it will extract
necessary information from the packet and pass to the higher level block. The MIPI DSI Link Controller is also
responsible for generating the CRC and ECC for the out-going bit stream. During reception, it will check the
correctness of the ECC and CRC field of the incoming stream.
When operated in 2-DSI mode, the MIPI DSI Link Controller is able to split the incoming video into 2 equal
portions and send each half of the line to each of the MIPI DSI engines. Each MIPI DSI engine take the half
video data and reformat it into RGB 16/18/24-bit packet and send out as 1 packet per line.
A line buffer is used to buffer a single video line from the upstream module and it will regenerate the Video
timing with the video settings stored inside the local registers. The output rate from the buffer must be greater
than the input rate to prevent data overflow.
MIPI DSI Link controller is also capable of sending DCS/Generic commands to external MIPI DSI drivers via
multiple sources.

Table 5-2 SSD2829T RGB data arrangement

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

24bpp R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

18bpp X X X X X X R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

16bpp X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

5.6 XTAL OSC

This is a crystal oscillator pad. From a circuit point of view, the crystal oscillator I/O cells are not real oscillators,
but amplifiers used to generate high quality clock signals. Full range configurable output driving capability

5.7 PLL

This is a PLL control the MIPI output frequency.

5.8 PMU

The PMU (Power Management Unit) is responsible for putting SSD2829T into deep-sleep mode, cutting the
power consumption to ultra-low level. Internally, it uses APB interface for register programming

SSD2829T Rev 1.2 P 13/159 Feb 2018 Solomon Systech

6 PIN ARRANGEMENT
6.1 128 pins LQFP
Figure 6-1 : Pinout Diagram – 128 pins LQFP (Topview)

Solomon Systech Feb 2018 P 14/159 Rev 1.2 SSD2829T

 Table 6-1: LQFP Pin Assignment Table

Pin # QFP Pin name Pin # QFP Pin name Pin # QFP Pin name Pin # QFP Pin name
1 AVDD 33 DATA0_13 65 DATA0_44 97 AVDD
2 VSS 34 DATA0_14 66 DATA0_45 98 AVDD_CDR
3 VDD_CORE 35 DATA0_15 67 DATA0_46 99 TXB_DN3
4 IF_SEL0 36 DATA0_16 68 DATA0_47 100 TXB_DP3
5 VDDIO 37 DATA0_17 69 DATA0_48 101 TXB_DN0
6 VSS 38 DATA0_18 70 DATA0_49 102 TXB_DP0
7 VSS 39 DATA0_19 71 DATA0_50 103 VDRV
8 VSS 40 DATA0_20 72 DATA0_51 104 AVDD
9 RST_IN 41 DATA0_21 73 DATA0_52 105 TXB_CN
10 VDDIO 42 DATA0_22 74 DATA0_53 106 TXB_CP
11 VDD_CORE 43 DATA0_23 75 SDO 107 TXB_DN1
12 VSS 44 TE_OUT_0 76 SDI 108 VDRV
13 CSX0 45 TE_OUT_1 77 SCK 109 TXB_DP1
14 CLK_IN 46 VDDIO 78 DEN 110 TXB_DN2
15 PD_N 47 XTAL_IN 79 PCLK 111 TXB_DP2
16 VSYNC 48 XTAL_OUT 80 HSYNC 112 AVDD_RC
17 HSYNC 49 VSS 81 VSYNC 113 VCIP
18 PCLK 50 VDD_CORE 82 TE_IN_1_CM 114 VDRV_REG
19 DEN 51 DATA0_30 83 TE_IN_0_CM 115 AVSS
20 DATA0_0 52 DATA0_31 84 VSS 116 TXA_DN3
21 DATA0_1 53 DATA0_32 85 VDD_CORE 117 TXA_DP3
22 DATA0_2 54 DATA0_33 86 VDDIO 118 TXA_DN0
23 DATA0_3 55 DATA0_34 87 SDC 119 TXA_DP0
24 DATA0_4 56 DATA0_35 88 PS4 120 VDRV
25 DATA0_5 57 DATA0_36 89 PS3 121 AVDD
26 DATA0_6 58 DATA0_37 90 PS2 122 TXA_CN
27 DATA0_7 59 DATA0_38 91 PS1 123 TXA_CP
28 DATA0_8 60 DATA0_39 92 PS0 124 TXA_DN1
29 DATA0_9 61 DATA0_40 93 INT_B 125 VDRV
30 DATA0_10 62 DATA0_41 94 VDD_CORE 126 TXA_DP1
31 DATA0_11 63 DATA0_42 95 VSS 127 TXA_DN2
32 DATA0_12 64 DATA0_43 96 AVDD 128 TXA_DP2

SSD2829T Rev 1.2 P 15/159 Feb 2018 Solomon Systech

7 PIN DESCRIPTIONS

Key:
I = Input
O =Output
IO = Bi-directional (input/output)
P = Power pin

7.1 Power Supply Pin

Table 7-1: Power Supply Pin Description

When not
Pin name Type Connect to Description
in use
VDD P Power Core Power Supply, 1.3V -
VDDIO P Power I/O Power Supply, 1.8V or 3.3V -
VSS P GND Ground -
AVDD_CDR P Power Analog Regulator Output for DPHY CDR, 1.3V -
AVDD_RC P Power Analog Power Supply 1.3V -
AVDD P Power Analog Power Supply 1.3V -
AVDD_CORE P Power Analog Core Power Supply 1.3V -
AVSS P GND Ground -
VCIP P Power Power for Bandgap, 3.3V -
VDRV_REG P Power LV Regulator Output -
Power for MIPI TX Driver (to be connected to
VDRV P Power -
VDRV_REG, 0.5V)

7.2 MIPI Pin

Table 7-2: MIPI Pin Description

When not
Pin name Type Connect to Description
in use
TX0_DP0 I/O TX0 DSI Data Lane Positive 0
TX0_DN0 I/O TX0 DSI Data Lane Negative 0
TX0_DP1 O TX0 DSI Data Lane Positive 1
TX0_DN1 O TX0 DSI Data Lane Negative 1
TX0_DP2 O TX0 DSI Data Lane Positive 2
TX0_DN2 O TX0 DSI Data Lane Negative 2
TX0_DP3 O TX0 DSI Data Lane Positive 3
TX0_DN3 O MIPI Tx TX0 DSI Data Lane Negative 3 Open
TX0_CP O TX0 DSI Clock Lane Positive
TX0_CN O TX0 DSI Clock Lane Negative
TX1_DP0 I/O TX1 DSI Data Lane Positive 0
TX1_DN0 I/O TX1 DSI Data Lane Negative 0
TX1_DP1 O TX1 DSI Data Lane Positive 1
TX1_DN1 O TX1 DSI Data Lane Negative 1
TX1_DP2 O TX1 DSI Data Lane Positive 2

Solomon Systech Feb 2018 P 16/159 Rev 1.2 SSD2829T

 TX1_DN2 O TX1 DSI Data Lane Negative 2
TX1_DP3 O TX1 DSI Data Lane Positive 3
TX1_DN3 O TX1 DSI Data Lane Negative 3
TX1_CP O TX1 DSI Clock Lane Positive
TX1_CN O TX1 DSI Clock Lane Negative

7.3 Control Signal Pin

Table 7-3: Control Signal Pin Description

When not
Pin name Type Connect to Description
in use
VDDIO /
RESET I System Reset signal to the whole chip, active low
GND VDDIO
INT_B O - Output Interrupt Signal Open
VDDIO /
PD_N I Power Down, active low
GND VDDIO
Interface selection signals
VDDIO / - 0 : A combination of RGB and SPI interface is
IF_SEL[0] I
GND selected VDDIO /
- 1 : MCU interface is selected GND
Interface selection signal
PS[1:0] is for SPI interface
- 00: 3 wire 24-bit SPI interface
- 01: 3 wire 8-Bit SPI interface
- 10: 4 wire 8-Bit SPI interface
- 11: Reserved

PS[4:2] is for the MCU interface

When if_sel is ‘01’
VDDIO / - 000: 8-Bit MCU interface (MIPI DBI type B)
PS[4:0] I
GND - 001: 16-bit MCU interface (MIPI DBI type B)
- 010: 8-Bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 011: 16-bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 100: 24-bit MCU interface (MIPI DBI type B)
- 110: 24-bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 101: reserved VDDIO /
- 111: reserved GND
CLK_IN I - Reserved Open
XTAL_OUT I - Crystal inout for System PLL Open
External Crystal in for System PLL
XTAL_IN I
CLK Frequency range: 8MHz to 30MHz -

SSD2829T Rev 1.2 P 17/159 Feb 2018 Solomon Systech

7.4 Interface Logic Pin

Table 7-4: MCU/RGB Interface Description

When not
Pin name Type Connect to Description
in use
DATA0[53:30] I/O RGB data for RGB Interface Open
RGB data for RGB Interface Open
DATA0[23:0] I/O
MCU data for MCU interface
- Vsync for lower RGB interface VDDIO /
- E clock signal for MCU interface GND
VSYNC / E /
I (This is for MIPI DBI type A interface)
WRX
- Write enable signal for MCU interface. Enabled
when low. (This is for MIPI DBI type B interface)
- PCLK for lower RGB interface VDDIO /
- Read/Write selection signal for MCU interface. GND
PCLK / RWX / Read cycle when high, write cycle when low.
I
RDX (This is for MIPI DBI type A interface)
MCU/RGB
- Read enable signal for MCU interface. Enabled
Signals
when low. (This is for MIPI DBI type B interface.)
- Hsync for lower RGB interface VDDIO /
HSYNC I
GND
- Den for lower RGB interface VDDIO /
DEN; DCX I
- Data or command signal for MCU interface GND
Input Tearing Effect Signal for MCU VDDIO /
TE_IN_0 I
GND
TE_OUT_0 O Output Tearing Effect Signal for MCU Open
Reserved VDDIO /
TE_IN_1 I
GND
TE_OUT_1 O Reserved Open

Table 7-5: SPI Interface Description

When not
Pin name Type Connect to Description
in use
CSX0 I Chip Select for SPI interface VDDIO
VDDIO /
SDC I Data or Command for SPI interface (for 8-bit 4 wire)
GND
VDDIO /
SCK I SPI Signal Serial clock for SPI interface
GND
VDDIO /
SDI I Serial data input for SPI interface
GND
SDO O Serial data output for SPI interface Open

Solomon Systech Feb 2018 P 18/159 Rev 1.2 SSD2829T

8 COMMAND TABLE

8.1 Local Registers (non-APB) Descriptions

8.1.1 RGB Interface Control Register 1

Offset Address
RICR1 RGB Interface Control Register 1 0xB1
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VSA
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HSA
TYPE RW
RESET 0x0A

Table 8-1: RGB Interface Control Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
VSA VSA – Vertical Sync Active Period Per Application Condition
Bit 15-8
These bits specify the Vsync active period.
The Hsync active period is from the Vsync
falling edge to rising edge, in terms of Hsync
lines. It is only used in non-burst mode with
Sync pulses.
(The minimum value is 1)
HSA HSA – Horizontal Sync Active Period Per Application Condition
Bit 7-0
These bits specify the Hsync active period.
The Hsync active period is from the Hsync
falling edge to rising edge, in terms of pclk. It is
only used in non-burst mode with Sync pulses.
(The minimum value is 1)

SSD2829T Rev 1.2 P 19/159 Feb 2018 Solomon Systech

8.1.2 RGB Interface Control Register 2
Offset Address
RICR2 RGB Interface Control Register 2 0xB2
BIT 31 30 29 28 27 26 25 24
NAME VBP[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HBP[15:8]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME VBP[7:0]
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HBP[7:0]
TYPE RW
RESET 0x14

Table 8-2: RGB Interface Control Register 2 Description

Name Description Setting

VBP[15:8] VBP – Vertical Back Porch Period High Byte Per Application Condition
Bit 31-24
Refer to VBP[7:0] for description
HBP[15:8] HBP – Horizontal Back Porch Period High Byte Per Application Condition
Bit 23-16
Refer to HBP[7:0] for description
VBP[7:0] VBP – Vertical Back Porch Period Low Byte Per Application Condition
Bit 15-8
These bits specify the vertical back porch period
in terms of Hsync pulses. The vertical back
porch period depends on the video mode setting.

If the mode is non-burst mode with Sync pulses,

it is from the Vsync rising edge to the Hsync of
the first line of active display.
If the mode is non-burst mode with Sync events
or burst mode, it is from the Vsync falling edge
to the Hsync of the first line of active display.
(The minimum value is 1)
HBP[7:0] HBP – Horizontal Back Porch Period Low Byte Per Application Condition
Bit 7-0
These bits specify the horizontal back porch
period in terms of pclk. The horizontal back
porch period depends on the non-burst mode
setting.

Solomon Systech Feb 2018 P 20/159 Rev 1.2 SSD2829T

 Name Description Setting
If the mode is non-burst mode with Sync pulses,
it is from the Hsync rising edge to the start of
the valid display pixel.
If the mode is non-burst mode with Sync events
or burst mode, it is from the Hsync falling edge
to the start of the valid display pixel.
(The minimum value is 1)

SSD2829T Rev 1.2 P 21/159 Feb 2018 Solomon Systech

8.1.3 RGB Interface Control Register 3
Offset Address
RICR3 RGB Interface Control Register 3 0xB3
BIT 31 30 29 28 27 26 25 24
NAME VFP[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HFP[15:8]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME VFP[7:0]
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HFP[7:0]
TYPE RW
RESET 0x14

Table 8-3: RGB Interface Control Register 3 Description

Name Description Setting

VFP[15:8] VFP – Vertical Front Porch Period High Byte Per Application Condition
Bit 31-24
Refer to VFP[7:0] for description
HFP[15:8] HFP – Horizontal Front Porch Period High Byte Per Application Condition
Bit 23-16
Refer to HFP[7:0] for description
VFP[7:0] VFP – Vertical Front Porch Period Low Byte Per Application Condition
Bit 15-8
These bits specify the vertical front porch period
in terms of Hsync pulses. The vertical front
porch period is from the first Hsync after the last
line of active display to the next Vsync falling
edge.
HFP[7:0] HFP – Horizontal Front Porch Period Low Byte Per Application Condition
Bit 7-0
These bits specify the horizontal front porch
period in terms of pclk. The horizontal front
porch period is from the end of the valid display
pixel to the next Hsync falling edge.

Solomon Systech Feb 2018 P 22/159 Rev 1.2 SSD2829T

8.1.4 RGB Interface Control Register 4
Offset Address
RICR4 RGB Interface Control Register 4 0xB4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HACT[15:8]
TYPE RW
RESET 0x07

BIT 7 6 5 4 3 2 1 0
NAME HACT[7:0]
TYPE RW
RESET 0x80

Table 8-4: RGB Interface Control Register 4 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
HACT HACT – Horizontal Active Period Per Application Condition
Bit 15-0
These bits specify the horizontal active period in
terms of pclk. During the horizontal active
period, the den signal should always be high.

SSD2829T Rev 1.2 P 23/159 Feb 2018 Solomon Systech

8.1.5 RGB Interface Control Register 5
Offset Address
RICR5 RGB Interface Control Register 5 0xB5
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VACT[15:8]
TYPE RW
RESET 0x04

BIT 7 6 5 4 3 2 1 0
NAME VACT[7:0]
TYPE RW
RESET 0x38

Table 8-5: RGB Interface Control Register 5 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
VACT VACT – Vertical Active Period Per Application Condition
Bit 15-0
These bits specify the vertical active period in
terms of Hsync pulses.

Solomon Systech Feb 2018 P 24/159 Rev 1.2 SSD2829T

8.1.6 RGB Interface Control Register 6
Offset Address
RICR6 RGB Interface Control Register 6 0xB6
BIT 31 30 29 28 27 26 25 24
NAME VSD
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HSD
TYPE RW
RESET 0x02

BIT 15 14 13 12 11 10 9 8
NAME VS_P HS_P PCLK_P SDR RGB_PACK_SEQ VPF_EXT CBM
TYPE RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x1 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME NVB NVD BLLP VCS VM VPF
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x1 0x0 0x1 0x0

Table 8-6: RGB Interface Control Register 6 Description

Name Description Setting

VSD VSD – Vertical Sync Delay Per Application Condition
Bit 31-24
These bits control the internal pipeline delay of
the Vsync input.
HSD HSD – Horizontal Sync Delay Per Application Condition
Bit 23-16
These bits control the internal pipeline delay of
the Hsync input.
VS_P VS_P – Vertical Sync Polarity 0 – Vsync Pulse is active low
Bit 15 1 – Vsync Pulse is active high
This bit control the polarity of the Vsync pulse
input.
HS_P HS_P – Horizontal Sync Polarity 0 – Hsync Pulse is active low
Bit 14 1 – Hsync Pulse is active high
This bit control the polarity of the Hsync pulse
input.
PCLK_P PCLK_P – Pixel Clock Polarity 0 – Data is launch at falling edge,
Bit 13 SSD2829T latch data at rising edge
This bit control the polarity of the PCLK input. 1 – Data is launch at rising edge,
This bit is valid when SDR is 1. SSD2829T latch data at falling
edge
SDR SDR - Single Data Rate 0 – Data is launch at both rising and
Bit 12 falling edge
This bit control whether the RGB input is single 1 – Data is launch at either rising or
data rate or dual data rate. falling edge, depends on the
PCLK_P bit

SSD2829T Rev 1.2 P 25/159 Feb 2018 Solomon Systech

 Name Description Setting
RGB_PACK RGB_PACK_SEQ - RGB Packing Sequence For RGB input and 2 DSI_TX
_SEQ output(1 to 2)
Bit 11-10 This is applicable for 1 RGB to 2 DSI_TX 0 - Odd/Even split. RGB lower
output(1 to 2) configurations. order pixel = pixel[0] on DSI_TX0,
RGB higher order pixel = pixel[1]
on DSI_TX1.
1 - Left/Right split. pixel[0] to
pixel[n/2-1] on DSI_TX0,
pixel[n/2] to pixel[n-1] on
DSI_TX1.
2 - Broadcast split. DSI_TX0 is
duplicated to DSI_TX1.
3 - Reserved
VPF_EXT VPF_EXT - Video Pixel Format Extension [VPF_EXT, VPF]
Bit 9 000 - 16-bit
This bit is used in conjunction with the 001 - 18-bit
VPF[1:0] bits to define the output pixel format. 010 - 18-bit loosely
011 - 24-bit
100 - Reserved
111 - Compressed pixel
CBM CBM – Compress Burst Mode Control 0 – Video with blanking packet.
Bit 8 1 – Video with no blanking packet
If the video mode is burst(VM=0x2) and this bit
is 1, MIPITX will send video packet in
compressed burst mode (i.e. no blanking packet
after horizontal sync packet)
NVB NVB – Non Video Data Burst Mode Control 0 - Non video data will be
Bit 7 transmitted during any BLLP
This bit specifies how non video data will be period
interleaved with video data transmission in burst 1 - Non video data will only be
mode. transmitted during vertical blanking
period
NVD NVD – Non Video Data Transmission Control 0 – Non video data will be
Bit 6 transmitted using HS mode
This bit specifies how non video data will be 1 – Non video data will be
interleaved with video data transmission. transmitted using LP mode
The SSD2829T will send non video data
(written from the SPI interface) during the
vertical blanking period (non burst mode) or any
BLLP period in burst mode (depends on NVB
setting). The data can be sent either in high
speed mode or low power mode. This bit selects
which mode to use. If LP mode is selected, the
data lane will enter LP mode for BLLP period,
even if there is no non-video data to send.
Please note that sending data in LP mode is
much slower than HS mode. It is the
responsibility of the host processor to make sure
that the duration is long enough to finish the
data transfer and the timing of Hsync and Vsync
is not affected.

BLLP BLLP – Blanking and Low Power Control 0 – Blanking packet will be sent
Bit 5 during BLLP period
This bit specifies the SSD2829T operation 1 – LP mode will be used during
during BLLP period. This bit takes effect only BLLP period
for non burst mode and NVD being 0.

Solomon Systech Feb 2018 P 26/159 Rev 1.2 SSD2829T

 Name Description Setting

When the video mode is burst mode, the

SSD2829T will not send any blanking packet
during BLLP. It will enter LP mode.
When NVD is 1 in non burst mode, the
SSD2829T will stay in LP mode after sending
the non video data (if there is any), until the
BLLP period ends.

When NVD is 0 in non burst mode, the

SSD2829T will use this bit to decide whether to
send blanking packet or enter LP mode after
sending non video data (if there is any), until the
BLLP period ends.
Please note that entering and exiting from LP
mode needs more time, as the speed of LP mode
is slow. It is the responsibility of the host
processor to make sure that the period is long
enough to finish the data transfer and the timing
of Hsync and Vsync is not affected.
VCS VCS – Video Clock Suspend 0 – During burst mode, the clock
Bit 4 lane remains in HS mode, when
This bit specifies how non video data will be there is no data to transmit. During
interleaved with video data transmission in burst non burst mode, the clock lane will
mode. remain in HS mode all the time.
This bit specifies the clock lane behavior 1 – During burst mode, the clock
lane enters LP mode when there is
no data to transmit. During non
burst mode, the clock lane enters
LP mode during vertical blanking
period.
VM VM – Video Mode 00 – Non burst mode with sync
Bit 3-2 pulses
These bits specify the video mode when RGB 01 – Non burst mode with sync
interface is selected. events
10 – Burst mode
11 – Reserved
VPF VPF – Video Pixel Format [VPF_EXT, VPF]
Bit 1-0 000 - 16-bit
This bit is used in conjunction with the 001 - 18-bit
VPF_EXT bit to define the output pixel format. 010 - 18-bit loosely
011 - 24-bit
100 - Reserved
111 - Compressed pixel
Table 8-7: RGB data arrangement

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

24bpp R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

18bpp X X X X X X R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

16bpp X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

SSD2829T Rev 1.2 P 27/159 Feb 2018 Solomon Systech

8.1.7 Configuration Register
Offset Address
CFR Configuration Register 0xB7
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
OTHER_
NAME VEN_CTR SCR_EN TXD LPE EOT ECD
CMD
TYPE RO RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1

BIT 7 6 5 4 3 2 1 0
NAME REN DCS CSS HCLK VEN SLP CKE HS
TYPE RW RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-8: Configuration Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-15
VEN_CTR VEN_CTR – Video Enable Control 0 – Internal video enable follows
Bit 14 the VEN bit
This bit specifies whether the SSD2829T will 1 – Internal video enable extends
extend the internal video enable bit until frame until the frame boundary
boundary.

SCR_EN SCR_EN – Scrambler Mode Enable 0 – Scrambling is disable

Bit 13 1 – Scrambling is enable
This bit specifies whether the SSD2829T will
send the long packets with scrambled data.
SSD2829T will send the Scrambling Mode
Packet prior to the Long packet.
OTHER_C OTHER_CMD – Other Command 0 – DCS bit defines DCS or
MD Generic command.
Bit 12 This bit defines how DCS, Generic, PPS or 1 – DCS bit defines PPS or
Compression Mode packet is sent. Compression mode packet.

TXD TXD –Transmit Disable 0 – Transmit on

Bit 11 1 – Transmit halt
This bit specifies whether the SSD2829T will
disable the sending of MIPI Packets stored in
the buffers. Software can enable TXD, fill out
the buffers and then disable it to send all packets
out in 1 burst.
LPE LPE –Long Packet Enable 0 – Short Packet

Solomon Systech Feb 2018 P 28/159 Rev 1.2 SSD2829T

 Name Description Setting
Bit 10 1 – Long Packet
This bit specifies whether the SSD2829T will
send out a Generic Long Write Packet or
Generic Short Write Packet when the payload is
no more than 2 bytes.
It also specifies whether the SSD2829T will
send out a DCS Long Write Packet or DCS
Short Write Packet when the payload is no more
than 1 byte.

EOT EOT – EOT Packet Enable 0 – Do not send

Bit 9 1 – Send
This bit specifies whether the SSD2829T will
send out the EOT packet at the end of HS
transmission or not. This is only valid in DPHY
mode.
ECD ECD – ECC CRC Check Disable 0 – Enable
Bit 8 1 – Disable
This bit specifies whether SSD2829T will
perform ECC and CRC checking for the packets
received from the MIPI slave.
REN REN – Read Enable 0 – Write operation
Bit 7 1 – Read operation
This bit specifies whether the next operation is a
write or read operation.
REN DCS – DCS or Generic When OTHER_CMD is 0,
Bit 6
This bit specifies whether the packet to be sent 0 – Generic packet (The packet
is DCS packet or generic packet. This bit can be any one of Generic Long
applies for both write and read operation. When Write, Generic Short Write,
OTHER_CMD bit is set, this bit specifies Generic Read packet, depending
whether the packet to be sent is PPS or on the configuration.)
Compress Mode packet. 1 – DCS packet (The packet can
be any one of DCS Long Write,
DCS Short Write, DCS Read
packet, depending on the
configuration.)

When OTHER_CMD is 1,

0 – Picture Parameter Setting

Packet
1 – Compress Mode Packet
CSS CSS – Clock Source Select 0 – The clock source is XTAL_IN
Bit 5 1 – The clock source is pclk
This bit selects the clock source for the PLL.
The CSS setting should be programmed only
when PEN is 0. It has no effect when PEN is 1.
HCLK HCLK – High Speed Clock Disable 0 – HS clock is enabled
Bit 4 1 – HS clock is disabled
This bit controls the clock lane behavior during
the reverse direction communication. This bit
takes effect only when CKE is 0 and VEN is 0.
VEN VEN – Video Mode Enable 0 – Video mode is disabled
Bit 3 1 – Video mode is enabled

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 Name Description Setting
This bit controls the video mode operation.
Only after this bit is set to 1, video mode is
enabled.
SLP SLP – Sleep Mode Enable 0 – Sleep mode is disabled
Bit 2 1 – Sleep mode is enabled Only
This bit controls the sleep mode operation. the register interface is active
When this bit is set to 1, the HS bit will be
cleared to 0 automatically.
CKE CKE – Clock Lane Enable 0 – Clock lane will enter LP mode,
Bit 1 if it is not in reverse direction
This bit controls the clock lane mode when data communication.
lane enters LP mode. Clock lane will follow the setting
of HCLK, if it is in reverse
direction communication.
1 – Clock lane will enter HS mode
for all the cases
HS HS – High Speed Mode 0 – LP mode
Bit 0 1 – HS mode
This bit controls whether the SSD2829T is using
HS or LP mode to send data.
This bit can be affected by the SLP bit value.

Solomon Systech Feb 2018 P 30/159 Rev 1.2 SSD2829T

8.1.8 Virtual Channel Control Register
Offset Address
VCCR Virtual Channel Control Register 0xB8
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME VCM VCE VC2 VC1
TYPE RW RW RW RW
RESET 0x1 0x0 0x1 0x1

Table 8-9: Virtual Channel Control Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-8
VCM VCM – Virtual Channel ID for Maximum Per Application Condition
Bit 7-6 Return Size Packet

These bits specify the VC ID for the Maximum

Return Size Packet sent by SSD2829T.
This register field is included as the VC ID for
this packet might be different from the
VC ID for the packets carrying the actual data.
VCE VCE – Virtual Channel ID for EOT Packet Per Application Condition
Bit 5-4
These bits specify the VC ID for the EOT
Packet sent by SSD2829T.
This register field is included as the VC ID for
this packet might be different from the VC ID
for the packets carrying the actual data.
VC2 VC2 – Virtual Channel ID for SPI Interface Per Application Condition
Bit 3-2
These bits specify the VC ID for the packets
written in through the SPI interface, when
the interface setting is RGB + SPI(if_sel[0] = 0).
VC1 VC1 – Virtual Channel ID for RGB and MCU Per Application Condition
Bit 1-0 Interface

These bits specify the VC ID for the packets

written in through the RGB

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 Name Description Setting
interface, when the interface is RGB +
SPI(if_sel[0] = 0).
These bits specify the VC ID for the packets
written in through the MCU interface, when the
interface setting is MCU(if_sel[0] = 1).

Solomon Systech Feb 2018 P 32/159 Rev 1.2 SSD2829T

8.1.9 PLL Control Register
Offset Address
PCR PLL Control Register 0xB9
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PEN
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-10: PLL Control Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-1
PEN PEN – PLL Enable 0 – PLL power down
Bit 0 1 – PLL enable
This bit controls the PLL operation.

Note: Frequency of PLL can only be changed during PEN=0

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8.1.10 PLL Configuration Register
Offset Address
PCFR PLL Configuration Register 0xBA
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
PLL_TES
NAME FR MS
T
TYPE RW RW RW
RESET 0x3 0x0 0x01

BIT 7 6 5 4 3 2 1 0
NAME NS
TYPE RW
RESET 0x20

Table 8-11: PLL Configuration Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
FR FR(PLL frequency Range) – Frequency Range 00 – 62.5 to 125
Bit 15-14 01 – 126 to 250
These bits select the range of the output clock. 10 – 251 to 500
11 – 501 to 1500
PLL_TEST PLL_TEST – PLL Test Mode Not Applicable
Bit 13
This bit set the TEST_MODE pin of the PLL. It
should be set to 0 in normal mode.
MS MS(PLL frequency POSTDIV) – PLL Divider 0x00 - Reserved
Bit 12-8 0x01 - MS=1
These bits specify the PLL pre-divider value, 0x02 - MS=2
MS. …
0x1F - MS=31
NS NS(PLL frequency MULT) – PLL Multiplier 0x00 - NS=1
Bit 7-0 0x01 - NS=1
These bits specify the PLL output frequency 0x02 - NS=2
multiplier value, NS. …
0xFF - NS=255

e.g. XTAL_IN = 20MHz, 0xBAh = 0xC132h

PLL = 50 x 20 / 1 = 1Gbps

Solomon Systech Feb 2018 P 34/159 Rev 1.2 SSD2829T

8.1.11 Clock Control Register
Offset Address
CCR Clock Control Register 0xBB
BIT 31 30 29 28 27 26 25 24
BYP_BIT
NAME
_DIV
TYPE RO RO RO RW RW
RESET 0x0 0x0 0x0 0x1 0x6

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RW
RESET 0x07

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME TX_LPD
TYPE RW
RESET 0x03

Table 8-12: Clock Control Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-29
BYP_BIT_D Reserved Not Applicable
IV
Bit 28
Reserved Reserved Not Applicable
Bit 27-24
Reserved Reserved Not Applicable
Bit 23-16
Reserved Reserved Not Applicable
Bit 15-8
TX_LPD TX_LPD(Low Power Divider) – LP Clock 0x0 – Divide by 1
Bit 7-0 Divider for MIPITX 0x1 – Divide by 2
0x2 – Divide by 3
These bits give the divider value for generating …
the LP mode clock from the system clock. 0x3F – Divide by 64

Remark: e.g. LPD = 0x9

PLL = 1Gbps
LP clock = 1Gbps / (LPD+1) / 8 = 1000 / 10 / 8 = 12.5MHz

SSD2829T Rev 1.2 P 35/159 Feb 2018 Solomon Systech

8.1.12 Packet Size Control Register 1
Offset Address
PSCR1 Packet Size Control Register 1 0xBC
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TDC_L[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TDC_L[7:0]
TYPE RW
RESET 0x00

Table 8-13: Packet Size Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
TDC_L TDC_L – Transmit Data Count Low Per Application Condition
Bit 15-0
These bits, together with TDC_H, forms the 32
bit value for TDC.

TDC set the total number of data bytes to be

transmitted by the SSD2829T in the next
operation. The SSD2829T will use the value in
this field to decide what type of packet to send
out.

The settings of TDC and PST will configure the

transfer mode into partition
and non-partition mode when the command is
0x2C or 0x3C.

Partition mode(TDC > PST) - For DCS Long

Write packet with DCS command being 0x2C or
0x3C, there is no
limit in the maximum number of bytes to be
transmitted in 1 write. The PST value can
be set to maximum of 8191 bytes. The
SSD2829T will auto insert 0x3C command at
these boundaries. This is valid in RGB+SPI
mode.

Solomon Systech Feb 2018 P 36/159 Rev 1.2 SSD2829T

 Name Description Setting
Non-Partition mode(TDC <= PST) For DCS
Long Write packet with DCS command being
0x2C or 0x3C, the
maximum number of bytes to be transmitted in 1
write is 10560 bytes for MIPITX0 and 8544
bytes for MIPITX1. In this mode,
the PST value is the same or greater than the
TDC value.

e.g.
1 1440
1

LCD
1440 (H) x 2560 (V)
2560

Total transmitted data per frame = 1440 x 2560 x 3 = 11,059,200 (= 0xA8C000h)

1 line data = 1440 x 3 =4,320 (=0x10E0h)
0xBC = 0xC000 //1 frame RAM (lower 16bit)
0xBD = 0x00A8 //1 frame RAM (higher 16bit)
0xBE = 0x10E0 //1 line RAM

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8.1.13 Packet Size Control Register 2
Offset Address
PSCR2 Packet Size Control Register 2 0xBD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TDC_H[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TDC_H[7:0]
TYPE RW
RESET 0x00

Table 8-14: Packet Size Register 2 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
TDC_H TDC_H – Transmit Data Count High Per Application Condition
Bit 15-0
Please see TDC_L for description.

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8.1.14 Packet Size Control Register 3
Offset Address
PSCR3 Packet Size Control Register 3 0xBE
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME PST[12:8]
TYPE RO RO RO RW
RESET 0x0 0x0 0x0 0x1F

BIT 7 6 5 4 3 2 1 0
NAME PST[7:0]
TYPE RW
RESET 0xFF

Table 8-15: Packet Size Register 3 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-13
PST PST – Packet Size Threshold Per Application Condition
Bit 12-0
These bits give the threshold value for
partitioning the incoming long packet data into
smaller packets. The partitioning only applies to
the DCS Long Write packet with DCS
command being 0x2C or 0x3C in Command
mode(if_sel[1:0]=01). The payload will be
partitioned into multiple packets. The PST
represents the threshold in term of bytes.

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8.1.15 Packet Drop Register
Offset Address
PDR Packet Drop Register 0xBF
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME PD[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME PD[7:0]
TYPE RW
RESET 0x00

Table 8-16: Packet Drop Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
PD PD – Packet Drop Per Application Condition
Bit 15-0
This register is not a true register. It is the entry
point for the internal buffer. The payload of the
generic packets (Generic Short Write, Generic
Long Write, Generic Read, DCS Short Write,
DCS Long Write, DCS Read, PPS Long Write,
Compress Mode Write).

The application processor can treat this

register as an FIFO and continuously write
data into it.

Since the register is only the entry point

of the internal buffer, the application
processor is not able to read the data
written into the buffer.

Solomon Systech Feb 2018 P 40/159 Rev 1.2 SSD2829T

8.1.16 Operational Control Register
Offset Address
OCR Operational Control Register 0xC0
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME SWR
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME COP
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-17: Operational Control Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-9
SWR SWR - Software Reset Per Application Condition
Bit 8
Writing a ‘1’ to this bit will reset the entire
module. This bit will be cleared after the reset is
completed.
Writing a ‘1’ to this bit will cause the MIPI link
enters TX stop state immediately and any
outgoing MIPI packet will be terminated
immediately.
Reserved Reserved Not Applicable
Bit 7-1
COP COP – Cancel Operation Per Application Condition
Bit 0
This bit is to cancel the current operation.
When this bit is set to 1, the SSD2829T will still
finish transmitting the current packet.
(Otherwise, the serial link operation will lose
sync.) Afterwards, the SSD2829T will stop any
further transmission. It will clear its
internal buffer such that all the data being
written in and not sent out yet will be cleared. It
will also bring the state machine to its initial
state.
Once this process is finished, the COP bit will
be automatically set to 0. At the same
time, the PO bit of the status register will be

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 Name Description Setting
set to 1 too. At this stage, there is no data
in the internal buffer. The application
processor can start a new operation. This
operation is not valid in video
mode(VEN=1).

Solomon Systech Feb 2018 P 42/159 Rev 1.2 SSD2829T

8.1.17 Maximum Return Size Register
Offset Address
MRSR Maximum Return Size Register 0xC1
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME MRS[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME MRS[7:0]
TYPE RW
RESET 0x01

Table 8-18: Maximum Return Size Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
MRS MRS – Maximum Return Size Per Application Condition
Bit 15-0
These bits set the maximum return size of the
read response packet returned by the MIPI slave.
The SSD2829T will automatically send out the
Set Maximum Return Size packet using the
value in this field, before every read operation.
It informs the MIPI slave about the limit of the
SSD2829T. The application processor does not
need to program the register before every read
operation, if the maximum return size does not
change. The Set Maximum Return Size packet
will always be sent.

SSD2829T Rev 1.2 P 43/159 Feb 2018 Solomon Systech

8.1.18 Return Data Count Register
Offset Address
RDCR Return Data Count Register 0xC2
BIT 31 30 29 28 27 26 25 24
NAME RDC1[15:8]
TYPE RO
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME RDC1[7:0]
TYPE RO
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME RDC0[15:8]
TYPE RO
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME RDC0[7:0]
TYPE RO
RESET 0x00

Table 8-19: Return Data Count Register Description

Name Description Setting

RDC1 RDC1 – Return Data Count from MIPITX1 Per Application Condition
Bit 31-16
These bits reflect the number of data bytes
received from the MIPI slave read response
packet from MIPITX1. This register can only be
updated by the SSD2829T.
RDC0 RDC0 – Return Data Count from MIPITX0 Per Application Condition
Bit 15-0
These bits reflect the number of data bytes
received from the MIPI slave read response
packet from MIPITX0. This register can only be
updated by the SSD2829T.

Solomon Systech Feb 2018 P 44/159 Rev 1.2 SSD2829T

8.1.19 Acknowledge Response Status Register
Offset Address
ARSR Acknowledge Response Status Register 0xC3
BIT 31 30 29 28 27 26 25 24
NAME ACK1[15:8]
TYPE RO
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME ACK1[7:0]
TYPE RO
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME ACK0[15:8]
TYPE RO
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME ACK0[7:0]
TYPE RO
RESET 0x00

Table 8-20: Acknowledge Response Status Register Description

Name Description Setting

ACK1 ACK1 – ACK Response from MIPITX1 Per Application Condition
Bit 31-16
These bits contain the ACK response from the
MIPI slave from MIPITX1. The register will be
updated when ACK with Error Report packet is
received. Otherwise, the value will be set to 0.
The bits in this register follow the definition in
MIPI DSI.
This register can only be updated by the
SSD2829T.
ACK0 ACK0 – ACK Response from MIPITX0 Per Application Condition
Bit 15-0
These bits contain the ACK response from the
MIPI slave from MIPITX0. The register will be
updated when ACK with Error Report packet is
received. Otherwise, the value will be set to 0.
The bits in this register follow the definition in
MIPI DSI.
This register can only be updated by the
SSD2829T.

SSD2829T Rev 1.2 P 45/159 Feb 2018 Solomon Systech

8.1.20 Line Control Register
Offset Address
LCR Line Control Register 0xC4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME RT1 RTB1 FBC1 FBT1 FBW1
TYPE RO RO RO RWAC RWAC RWAC RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME RT0 RTB0 FBC0 FBT0 FBW0
TYPE RO RO RO RWAC RWAC RWAC RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-21: Line Control Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-21
RT1 RT1 – Reset Trigger for MIPITX1 0 – Do not send
Bit 20 1 – Send Reset Trigger
This bit is to send a Reset Trigger Message.
When this bit is set to 1, the SSD2829T will
send a Reset Trigger Message. It is
recommended to enter LP mode and send this
trigger message. If this bit is programmed
during vertical active data is being sent on MIPI
link, the reset trigger will be delayed to next
vertical blanking period so that the reset trigger
message will not disturb the video timing on the
MIPI link. Once the Reset Trigger Message is
sent out, RT1 bit will be automatically set to 0.
RTB1 RTB1 – Register Triggered BTA for MIPITX1 0 – Do not send
Bit 19 1 – Send BTA
This bit automatically perform Bus
Turnaround(BTA) when link is not used.
When bus is returned back from the slave, the
link will remains in Low Power state until
a new request come in where HS bit
determination the transfer mode.
FBC1 FBC1 – Force Bus Contention for MIPITX1 0 – Do not force
Bit 19 1 – Force Bus Contention
This bit controls whether to force a bus
contention on the

Solomon Systech Feb 2018 P 46/159 Rev 1.2 SSD2829T

 Name Description Setting
data lane. This bit will be changed to 0, after the
bus contention is not detected.
FBT1 FBT1 – Force Bus Turnaround Tearing for 0 – Do not force
Bit 18 MIPITX1 1 – Force BTA for Tearing

This bit controls whether to perform automatic

BTA after previous BTA so as to get the TE
response from MIPI slave.
FBW1 FBW1 – Force Bus Turnaround after write for 0 – Do not force
Bit 17 MIPITX1 1 – Force BTA after write

This bit controls whether to automatically

generate a BTA after a write operation. It is only
valid for write operation.
After performing BTA, the bus authority has
been passed to the MIPI slave. The SSD2829T
is not able to send any data to the MIPI slave
before the bus authority is passed back. It is the
responsibility of the application processor to
check the status of the bus before sending any
data.
Reserved Reserved Not Applicable
Bit 16-5
RT0 RT0 – Reset Trigger for MIPITX0 0 – Do not send
Bit 4 1 – Send Reset Trigger
This bit is to send a Reset Trigger Message.
When this bit is set to 1, the SSD2829T will
send a Reset Trigger Message. It is
recommended to enter LP mode and send this
trigger message. If this bit is programmed
during vertical active data is being sent on MIPI
link, the reset trigger will be delayed to next
vertical blanking period so that the reset trigger
message will not disturb the video timing on the
MIPI link. Once the Reset Trigger Message is
sent out, RT1 bit will be automatically set to 0.
RTB0 RTB0 – Register Triggered BTA for MIPITX0 0 – Do not send
Bit 3 1 – Send BTA
This bit automatically perform Bus
Turnaround(BTA) when link is not used.
When bus is returned back from the slave, the
link will remains in Low Power state until
a new request come in where HS bit
determination the transfer mode.
FBC0 FBC0 – Force Bus Contention for MIPITX0 0 – Do not force
Bit 2 1 – Force Bus Contention
This bit controls whether to force a bus
contention on the
data lane. This bit will be changed to 0, after the
bus contention is not detected.
FBT0 FBT0 – Force Bus Turnaround Tearing for 0 – Do not force
Bit 1 MIPITX0 1 – Force BTA for Tearing

This bit controls whether to perform automatic

BTA after previous BTA so as to get the TE
response from MIPI slave.

SSD2829T Rev 1.2 P 47/159 Feb 2018 Solomon Systech

 Name Description Setting
FBW0 FBW0 – Force Bus Turnaround after write for 0 – Do not force
Bit 0 MIPITX0 1 – Force BTA after write

This bit controls whether to automatically

generate a BTA after a write operation. It is only
valid for write operation.
After performing BTA, the bus authority has
been passed to the MIPI slave. The SSD2829T
is not able to send any data to the MIPI slave
before the bus authority is passed back. It is the
responsibility of the application processor to
check the status of the bus before sending any
data.

Solomon Systech Feb 2018 P 48/159 Rev 1.2 SSD2829T

8.1.21 Interrupt Control Register
Offset Address
ICR Interrupt Control Register 0xC5
BIT 31 30 29 28 27 26 25 24
NAME CBEE1 CBAE1 MLEE1 MLAE1
TYPE RW RW RO RO RO RO RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTOE1 HSTOE1 ARRE1 BTARE1 RDRE1
TYPE RO RW RW RO RW RW RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CBEE0 CBAE0 MLEE0 MLAE0
TYPE RW RW RO RO RO RO RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PLSE LPTOE0 HSTOE0 ARRE0 BTARE0 RDRE0
TYPE RW RW RW RO RW RW RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-22: Interrupt Control Register Description

Name Description Setting

CBEE1 CBEE1 – Command Buffer Empty Enable for 0 – Do not enable
Bit 31 MIPITX1 1 – Enable

This bit enables the mapping of CBE1 interrupt

to the interrupt pin, INT_B.
CBAE1 CBAE1 – Command Buffer Available Enable 0 – Do not enable
Bit 30 for MIPITX1 1 – Enable

This bit enables the mapping of CBA1 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 29-26
MLEE1 MLEE1 – MCU Long Buffer Empty Enable for 0 – Do not enable
Bit 25 MIPITX1 1 – Enable

This bit enables the mapping of MLE1 interrupt

to the interrupt pin, INT_B.
MLAE1 MLAE1 – MCU Long Buffer Available Enable 0 – Do not enable
Bit 24 for MIPITX1 1 – Enable

This bit enables the mapping of MLA1 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 23
LPTOE1 LPTOE1 – LP RX Time Out Enable for 0 – Do not enable
Bit 22 MIPITX1 1 – Enable

SSD2829T Rev 1.2 P 49/159 Feb 2018 Solomon Systech

 Name Description Setting
This bit enables the mapping of LPTO1
interrupt to the interrupt pin, INT_B.
HSTOE1 HSTOE1 – HP TX Time Out Enable for 0 – Do not enable
Bit 21 MIPITX1 1 – Enable

This bit enables the mapping of HSTO1

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 20
ARRE1 ARRE1 – ACK Response Ready Enable for 0 – Do not enable
Bit 19 MIPITX1 1 – Enable

This bit enables the mapping of ARR1 interrupt

to the interrupt pin, INT_B.
BTARE1 BTARE1 – Bus Turnaround Response Enable 0 – Do not enable
Bit 18 for MIPITX1 1 – Enable

This bit enables the mapping of BTAR1

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 17
RDRE1 RDRE1 – Read Data Ready Enable for 0 – Do not enable
Bit 16 MIPITX1 1 – Enable

This bit enables the mapping of RDR1 interrupt

to the interrupt pin, INT_B.
CBEE0 CBEE0 – Command Buffer Empty Enable for 0 – Do not enable
Bit 15 MIPITX0 1 – Enable

This bit enables the mapping of CBE0 interrupt

to the interrupt pin, INT_B.
CBAE0 CBAE0 – Command Buffer Available Enable 0 – Do not enable
Bit 14 for MIPITX0 1 – Enable

This bit enables the mapping of CBA0 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 13-10
MLEE0 MLEE0 – MCU Long Buffer Empty Enable for 0 – Do not enable
Bit 9 MIPITX0 1 – Enable

This bit enables the mapping of MLE0 interrupt

to the interrupt pin, INT_B.
MLAE0 MLAE0 – MCU Long Buffer Available Enable 0 – Do not enable
Bit 8 for MIPITX0 1 – Enable

This bit enables the mapping of MLA0 interrupt

to the interrupt pin, INT_B.
PLSE PLSE – PLL Lock Status Enable 0 – Do not enable
Bit 7 1 – Enable
This bit enables the mapping of PLS interrupt to
the interrupt pin, INT_B.
LPTOE0 LPTOE0 – LP RX Time Out Enable for 0 – Do not enable
Bit 6 MIPITX0 1 – Enable

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 Name Description Setting
This bit enables the mapping of LPTO0
interrupt to the interrupt pin, INT_B.
HSTOE0 HSTOE0 – HP TX Time Out Enable for 0 – Do not enable
Bit 5 MIPITX0 1 – Enable

This bit enables the mapping of HSTO0

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 4
ARRE0 ARRE0 – ACK Response Ready Enable for 0 – Do not enable
Bit 3 MIPITX0 1 – Enable

This bit enables the mapping of ARR0 interrupt

to the interrupt pin, INT_B.
BTARE0 BTARE0 – Bus Turnaround Response Enable 0 – Do not enable
Bit 2 for MIPITX0 1 – Enable

This bit enables the mapping of BTAR0

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 1
RDRE0 RDRE0 – Read Data Ready Enable for 0 – Do not enable
Bit 0 MIPITX0 1 – Enable

This bit enables the mapping of RDR0 interrupt

to the interrupt pin, INT_B.

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8.1.22 Interrupt Status Register
Offset Address
ISR Interrupt Status Register 0xC6
BIT 31 30 29 28 27 26 25 24
NAME CBE1 CBA1 CLS1 DLS1 MLE1 MLA1
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTO1 HSTO1 ATR1 ARR1 BTAR1 RDRE1
TYPE RO RESW1C RESW1C RESW1C RESW1C RESW1C RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CBE0 CBA0 CLS0 DLS0 MLE0 MLA0
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PLS LPTO0 HSTO0 ATR0 ARR0 BTAR0 RDR0
TYPE RO RESW1C RESW1C RESW1C RESW1C RESW1C RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-23: Interrupt Status Register Description

Name Description Setting

CBE1 CBE1 – Command Buffer Empty for MIPITX1 0 – The command buffer is not
Bit 31 empty
This bit reflects the status of the internal 1 – The command buffer is
command buffer of the SPI/MCU interface. If empty
the command buffer is empty, this bit will be set
to 1. The application processor can write up to
the maximum size of the command buffer.
CBA1 CBA1 – Command Buffer Available for 0 – The command buffer is not
Bit 30 MIPITX1 available
1 – The command buffer is
This bit reflects the status of the internal available
command buffer of the SPI/MCU interface. If
the command buffer is not full, this bit will be
set to 1. The application processor can
write at least 1 packet to the command buffer.
Reserved Reserved Not Applicable
Bit 29-28
CLS1 CLS1 – Clock Lane Status for MIPITX1 0 – Clock lane is not in LP-11
Bit 27 1 – Clock lane is in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX1.
DLS1 DLS1 – Data Lane Status for MIPITX1 0 – Data lanes are not in LP-11
Bit 26 1 – Data lanes are in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX1.
MLE1 MLE1 – MCU Long Buffer Empty for 0 – The long buffer is not empty
Bit 25 MIPITX1 1 – The long buffer is empty

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 Name Description Setting
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
empty, this bit will be set to 1. The application
processor can write up to the maximum size of
the long buffer for DCS command 0x2C and
0x3C.
MLA1 MLA1 – MCU Long Buffer Available for 0 – The long buffer is not
Bit 24 MIPITX1 available
1 – The long buffer is available
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
not full, this bit will be set to 1. The application
processor can write at least 1
packet to the long buffer for DCS command
0x2C and 0x3C.
Reserved Reserved Not Applicable
Bit 23
LPTO1 LPTO1 – LP RX Time Out for MIPITX1 0 – The LP RX timer has expired
Bit 22 1 – The LP RX timer has not
This bit reflects the status of the LP RX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
HSTO1 HSTO1 – HP TX Time Out for MIPITX1 0 – The HS TX timer has expired
Bit 21 1 – The HS TX timer has not
This bit reflects the status of the HS TX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
ATR1 ATR1 – ACK Trigger Response for MIPITX1 0 – ACK trigger message has not
Bit 20 been received
This bit reflects whether the ACK trigger 1 – ACK trigger message has been
message has been received or not. received

It will remain as 1 until the application

processor writes 1 to clear it.
ARR1 ARR1 – ACK Response Ready for MIPITX1 0 – Response has not been
Bit 19 received
This bit reflects whether the ACK response has 1 – Response has been received
been received or not. The ACK response can be
an ACK trigger message or ACK with Error
Report packet.

It will remain as 1 until the application

processor writes 1 to clear it.
BTAR1 BTAR1 – Bus Turnaround Response for 0 – The MIPI slave has not passed
Bit 18 MIPITX1 the lane authority back
1 – The MIPI slave has passed the
This bit reflects the data lane status after lane authority back
SSD2829T has made a BTA.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 17
RDR1 RDR1 – Read Data Ready for MIPITX1 0 – Not ready

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 Name Description Setting
Bit 16 1 – Ready
This bit reflects whether the data from the MIPI
slave is ready for read by the application
processor. This bit is valid only during the read
operation.

This bit will be automatically cleared when all

the received data are read out.
CBE0 CBE0 – Command Buffer Empty for MIPITX0 0 – The command buffer is not
Bit 15 empty
This bit reflects the status of the internal 1 – The command buffer is
command buffer of the SPI/MCU interface. If empty
the command buffer is empty, this bit will be set
to 1. The application processor can write up to
the maximum size of the command buffer.
CBA0 CBA0 – Command Buffer Available for 0 – The command buffer is not
Bit 14 MIPITX0 available
1 – The command buffer is
This bit reflects the status of the internal available
command buffer of the SPI/MCU interface. If
the command buffer is not full, this bit will be
set to 1. The application processor can
write at least 1 packet to the command buffer.
Reserved Reserved Not Applicable
Bit 13-12
CLS0 CLS0 – Clock Lane Status for MIPITX0 0 – Clock lane is not in LP-11
Bit 11 1 – Clock lane is in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX0.
DLS0 DLS0 – Data Lane Status for MIPITX0 0 – Data lanes are not in LP-11
Bit 10 1 – Data lanes are in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX0.
MLE0 MLE0 – MCU Long Buffer Empty for 0 – The long buffer is not empty
Bit 9 MIPITX0 1 – The long buffer is empty

This bit reflects the status of the internal long

buffer of the MCU interface. If the long buffer is
empty, this bit will be set to 1. The application
processor can write up to the maximum size of
the long buffer for DCS command 0x2C and
0x3C.
MLA0 MLA0 – MCU Long Buffer Available for 0 – The long buffer is not
Bit 8 MIPITX0 available
1 – The long buffer is available
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
not full, this bit will be set to 1. The application
processor can write at least 1
packet to the long buffer for DCS command
0x2C and 0x3C.
PLS PLS – PLL Lock Status 0 – PLL is not locked
Bit 7 1 – PLL is locked
This bit reflects the status of the PLL. Before the
PLL is locked, the whole system is running at
the reference clock input of the PLL, as the PLL

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 Name Description Setting
has no output before getting lock. Hence, the
application processor must access the registers
using slow speed.
LPTO0 LPTO0 – LP RX Time Out for MIPITX0 0 – The LP RX timer has expired
Bit 6 1 – The LP RX timer has not
This bit reflects the status of the LP RX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
HSTO0 HSTO0 – HP TX Time Out for MIPITX0 0 – The HS TX timer has expired
Bit 5 1 – The HS TX timer has not
This bit reflects the status of the HS TX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
ATR0 ATR0 – ACK Trigger Response for MIPITX0 0 – ACK trigger message has not
Bit 4 been received
This bit reflects whether the ACK trigger 1 – ACK trigger message has been
message has been received or not. received

It will remain as 1 until the application

processor writes 1 to clear it.
ARR0 ARR0 – ACK Response Ready for MIPITX0 0 – Response has not been
Bit 3 received
This bit reflects whether the ACK response has 1 – Response has been received
been received or not. The ACK response can be
an ACK trigger message or ACK with Error
Report packet.

It will remain as 1 until the application

processor writes 1 to clear it.
BTAR0 BTAR0 – Bus Turnaround Response for 0 – The MIPI slave has not passed
Bit 2 MIPITX0 the lane authority back
1 – The MIPI slave has passed the
This bit reflects the data lane status after lane authority back
SSD2829T has made a BTA.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 1
RDR1 RDR0 – Read Data Ready for MIPITX0 0 – Not ready
Bit 0 1 – Ready
This bit reflects whether the data from the MIPI
slave is ready for read by the application
processor. This bit is valid only during the read
operation.

This bit will be automatically cleared when all

the received data are read out.

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8.1.23 Error Status Register
Offset Address
ESR Error Status Register 0xC7
BIT 31 30 29 28 27 26 25 24
NAME CRCE1 ECCE2_1 ECCE1_1
TYPE RO RO RO RO RO RESW1C RESW1C RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME CBO1 MLO1 CONT1 VMM1
TYPE RESW1C RO RO RESW1C RO RO RO RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CRCE0 ECCE2_0 ECCE1_0
TYPE RO RO RO RO RO RESW1C RESW1C RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME CBO0 MLO0 CONT0 VMM0
TYPE RESW1C RO RO RESW1C RO RO RO RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-24: Error Status Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-27
CRCE1 CRCE1 – CRC Error for MIPITX1 0 – No CRC error since this bit is
Bit 26 cleared
This bit reflects the status of CRC checking for 1 – At least 1 CRC error since
the packets received from the MIPI slave. The this bit is cleared
status is valid only when the ECD bit is set to 0.
Once a CRC error occurs, this bit will be set to
1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE2_1 ECCE2_1 – ECC Multi Bit Error for MIPITX1 0 – No ECC multi-bit error since
Bit 25 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC multi-bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC multi-bit error occurs, this bit will
be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE1_1 ECCE1_1 – ECC Single Bit Error for MIPITX1 0 – No ECC single bit error since
Bit 24 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC single bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.

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 Name Description Setting
Once an ECC single-bit error occurs, this bit
will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
CBO1 CBO1 – Command Buffer Overflow for 0 – Overflow has not occurred
Bit 23 MIPITX1 1 – Overflow has occurred

This bit reflects the status of internal command

buffer of the SPI/MCU interface. If the
command buffer has overflowed, this bit will be
set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 22-21
MLO1 MLO1 – MCU Long Buffer Overflow for 0 – Overflow has not occurred
Bit 20 MIPITX1 1 – Overflow has occurred

This bit reflects the status of internal long buffer

of the MCU interface. If the long buffer has
overflowed, this bit will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 19
CONT1 CONT1 – Contention Detected for MIPITX1 0 – No contention
Bit 18 1 – Contention has occurred
This bit reflects the status of the data lane
contention detector.
Reserved Reserved Not Applicable
Bit 17
VMM1 VMM1 – VC Mis-Match for MIPITX1 0 – No mismatch
Bit 16 1 – Mismatch has occurred
This bit reflects whether there is a mismatch
between the VC ID transmitted by the
SSD2829T and the VC ID received from the
MIPI slave.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 15-11
CRCE0 CRCE0 – CRC Error for MIPITX0 0 – No CRC error since this bit is
Bit 10 cleared
This bit reflects the status of CRC checking for 1 – At least 1 CRC error since
the packets received from the MIPI slave. The this bit is cleared
status is valid only when the ECD bit is set to 0.
Once a CRC error occurs, this bit will be set to
1.

It will remain as 1 until the application

processor writes 1 to clear it.

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 Name Description Setting
ECCE2_0 ECCE2_0 – ECC Multi Bit Error for MIPITX0 0 – No ECC multi-bit error since
Bit 9 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC multi-bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC multi-bit error occurs, this bit will
be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE1_0 ECCE1_0 – ECC Single Bit Error for MIPITX0 0 – No ECC single bit error since
Bit 8 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC single bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC single-bit error occurs, this bit
will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
CBO0 CBO0 – Command Buffer Overflow for 0 – Overflow has not occurred
Bit 7 MIPITX0 1 – Overflow has occurred

This bit reflects the status of internal command

buffer of the SPI/MCU interface. If the
command buffer has overflowed, this bit will be
set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 6-5
MLO0 MLO0 – MCU Long Buffer Overflow for 0 – Overflow has not occurred
Bit 4 MIPITX0 1 – Overflow has occurred

This bit reflects the status of internal long buffer

of the MCU interface. If the long buffer has
overflowed, this bit will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 3
CONT0 CONT0 – Contention Detected for MIPITX0 0 – No contention
Bit 2 1 – Contention has occurred
This bit reflects the status of the data lane
contention detector.
Reserved Reserved Not Applicable
Bit 1
VMM0 VMM0 – VC Mis-Match for MIPITX0 0 – No mismatch
Bit 0 1 – Mismatch has occurred
This bit reflects whether there is a mismatch
between the VC ID transmitted by the
SSD2829T and the VC ID received from the
MIPI slave.

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 Name Description Setting
It will remain as 1 until the application
processor writes 1 to clear it.

SSD2829T Rev 1.2 P 59/159 Feb 2018 Solomon Systech

8.1.24 Compressed Register
Offset Address
CR Compressed Register 0xC8
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VID_COMPRESSED_BYTE_COUNT[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME VID_COMPRESSED_BYTE_COUNT[7:0]
TYPE RW
RESET 0x00

Table 8-25: Compressed Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
Reserved Reserved Not Applicable
Bit 15-0

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8.1.25 Delay Adjustment Register 1
Offset Address
DAR1 Delay Adjustment Register 1 0xC9
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HZD
TYPE RW
RESET 0x14

BIT 7 6 5 4 3 2 1 0
NAME HPD
TYPE RW
RESET 0x02

Table 8-26: Delay Adjustment Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
HZD HZD(Ths-zero-HZD) – HS Zero Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for HS zero delay period THS-ZERO.

The minimum value is 1.

HPD HPD(Ths-prepare-HPD) – HS Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for HS prepare delay period THS-PREPARE.

The minimum value is 1.

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8.1.26 Delay Adjustment Register 2
Offset Address
DAR2 Delay Adjustment Register 2 0xCA
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CZD
TYPE RW
RESET 0x28

BIT 7 6 5 4 3 2 1 0
NAME CPD
TYPE RW
RESET 0x03

Table 8-27: Delay Adjustment Register 2 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
CZD CZD(Tclk-zero-CZD) – Clock Zero Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for HS zero delay period TCLK-ZERO.

The minimum value is 1.

CPD CPD(Tclk-prepare-CPD) – Clock Prepare Per Application Condition
Bit 7-0 Delay

These bits specifies the number of system clock

for HS prepare delay period TCLK-PREPARE.

The minimum value is 1.

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8.1.27 Delay Adjustment Register 3
Offset Address
DAR3 Delay Adjustment Register 3 0xCB
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CPED
TYPE RW
RESET 0x04

BIT 7 6 5 4 3 2 1 0
NAME CPTD
TYPE RW
RESET 0x16

Table 8-28: Delay Adjustment Register 3 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
CPED CPED(Tclk-pre-CPED) – Clock Pre Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for CLK pre delay period TCLK-PRE.

The minimum value is 1.

CPTD CPTD(Tclk-post-CPTD) – Clock Prepare Per Application Condition
Bit 7-0 Delay

These bits specifies the number of system clock

for CLK post delay period TCLK-POST.

The minimum value is 1.

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8.1.28 Delay Adjustment Register 4
Offset Address
DAR4 Delay Adjustment Register 4 0xCC
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CTD
TYPE RW
RESET 0x0A

BIT 7 6 5 4 3 2 1 0
NAME HTD
TYPE RW
RESET 0x0A

Table 8-29: Delay Adjustment Register 4 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
CTD CTD(Tclk-trail-CTD) – Clock Pre Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for CLK trail delay period TCLK-TRAIL.

The minimum value is 1.

HTD HTD(Ths-trail-HTD) – Clock Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for HS trail delay period THS-TRAIL.

The minimum value is 1.

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8.1.29 Delay Adjustment Register 5
Offset Address
DAR5 Delay Adjustment Register 5 0xCD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME WUD[15:8]
TYPE RW
RESET 0x10

BIT 7 6 5 4 3 2 1 0
NAME WUD[7:0]
TYPE RW
RESET 0x00

Table 8-30: Delay Adjustment Register 5 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
WUD WUD – Wake Up Delay Per Application Condition
Bit 15-0
These bits specifies the number of clock cycles
for wake up delay period TWAKEUP. The
delay is used to wake up the MIPI slave from
ULPS state. The clock is the low power clock.

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8.1.30 Delay Adjustment Register 6
Offset Address
DAR6 Delay Adjustment Register 6 0xCE
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TGO
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x4

BIT 7 6 5 4 3 2 1 0
NAME TGET
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x5

Table 8-31: Delay Adjustment Register 6 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-12
TGO TGO – TA Go Delay Per Application Condition
Bit 11-8
These bits specifies the number of TLPX for TA
go delay period TTA-GO.
Reserved Reserved Not Applicable
Bit 7-4
TGET TGET – TA Get Delay Per Application Condition
Bit 3-0
These bits specifies the number of TLPX for TA
get delay period TTA-GET.

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8.1.31 HS TX Timer Register 1
Offset Address
HTTR1 HS TX Timer Register 1 0xCF
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HTT_L[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME HTT_L[7:0]
TYPE RW
RESET 0x00

Table 8-32: HS TX Timer Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
HTT_L HTT_L – HS TX Timer Low Per Application Condition
Bit 15-0
These bits are the lower 16 bits of the HTT.

These bits specify the HS TX timer timeout

value. PLL reference clock is used to increment
an internal timer. The timer starts when the
SSD2829T enters HS transmit mode. When the
SSD2829T exits from HS transmit mode, the
timer will be reset. If the timer expires before
the end of HS transmission, the SSD2829T will
signal an error and switch to LP mode to
continue the transmission. At the same time, the
HS bit will be cleared to 0. Software
intervention is required so that the SSD2829T
can go back to proper HS transmission mode.

SSD2829T Rev 1.2 P 67/159 Feb 2018 Solomon Systech

8.1.32 HS TX Timer Register 2
Offset Address
HTTR2 HS TX Timer Register 2 0xD0
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HTT_H[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME HTT_H[7:0]
TYPE RW
RESET 0x00

Table 8-33: HS TX Timer Register 2 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
HTT_H HTT_H – HS TX Timer High Per Application Condition
Bit 15-0
These bits are the upper 16 bits of the HTT.

These bits specify the HS TX timer timeout

value. PLL reference clock is used to increment
an internal timer. The timer starts when the
SSD2829T enters HS transmit mode. When the
SSD2829T exits from HS transmit mode, the
timer will be reset. If the timer expires before
the end of HS transmission, the SSD2829T will
signal an error and switch to LP mode to
continue the transmission. At the same time, the
HS bit will be cleared to 0. Software
intervention is required so that the SSD2829T
can go back to proper HS transmission mode.

Solomon Systech Feb 2018 P 68/159 Rev 1.2 SSD2829T

8.1.33 TE Status Register
Offset Address
TESR TE Status Register 0xD3
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
TE_OUT_ TE_OUT_ TE_IN_SE TE_IN_SE
NAME CMD_BC TER1 TER0
SEL1 SEL0 L1 L0
TYPE RO RW RW RW RW RW RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-34: TE Status Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-7
CMD_BC CMD_BC – Command Broadcast 0 - No Broadcast
Bit 6 1 - Broadcast
This bit select whether to broadcast the 2C/3C
content from MIPITX0 to MIPITX1 when the
configuration is 1x2(TX_DUAL=1) for MCU or
DSI input.
TE_OUT_SE Reserved Not Applicable
L1
Bit 5
TE_OUT_SE TE_OUT_SEL0 – TE output from MIPITX0 0 - Internal TE is sent to
L0 TE_OUT_0 pin
Bit 4 This bit select whether to send the TE output 1 - Reserved
from MIPITX0 via TE_OUT0 pin.
TE_IN_SEL Reserved Not Applicable
1
Bit 3
TE_IN_SEL TE_OUT_SEL0 – TE output from MIPITX0 0 - TE is taken from TE_IN_0
0 pin
Bit 2 This bit select which TE input to be used for 1 - TE is taken from MIPITX0
pulse shaping.
TE_RESP1 Reserved Not Applicable
Bit 1
TE_RESP0 TE_RESP0 – TE Response from MIPITX0 0 –TE response has not been
Bit 0 received

SSD2829T Rev 1.2 P 69/159 Feb 2018 Solomon Systech

 Name Description Setting
This bit reflects whether a TE response has been 1 – TE response has been
received or not. Once a TE response is received, received
this bit will be set to 1. At the same time, the
output TE signal will go high. The host
processor can write 1 to clear this bit. Once the
bit is cleared, the TE signal will go low.

Solomon Systech Feb 2018 P 70/159 Rev 1.2 SSD2829T

8.1.34 SPI Read Register
Offset Address
SRR SPI Read Register 0xD4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME RRA
TYPE RW
RESET 0xFA

Table 8-35: SPI Read Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-8
RRA RRA – Register Read Address Per Application Condition
Bit 7-0
These bits specify the address of the register to
be read through the SPI interface, when the
interface is SPI 8-bit (either 3 wire or 4 wire).

SSD2829T Rev 1.2 P 71/159 Feb 2018 Solomon Systech

8.1.35 PLL Lock Register
Offset Address
PLR PLL Lock Register 0xD5
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME LOCK[15:8]
TYPE RW
RESET 0x14

BIT 7 6 5 4 3 2 1 0
NAME LOCK[7:0]
TYPE RW
RESET 0x50

Table 8-36: PLL Lock Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-16
LOCK LOCK – Lock Counter Per Application Condition
Bit 15-0
These bits specify the PLL lock range in term of
PLL reference frequency. The maximum PLL
lock period is 500us and the default setting
assumed the reference clock is 10Mhz.

Solomon Systech Feb 2018 P 72/159 Rev 1.2 SSD2829T

8.1.36 Test Register
Offset Address
TR Test Register 0xD6
BIT 31 30 29 28 27 26 25 24
NAME EHS
TYPE RO RO RO RW RW
RESET 0x0 0x0 0x0 0x1 0x0

BIT 23 22 21 20 19 18 17 16
NAME COMP_SLICE
TYPE RW RO RW
RESET 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
DIS_CON
NAME TM EIC
T
TYPE RW RW RW
RESET 0x0 0x00 0x1

BIT 7 6 5 4 3 2 1 0
NAME PNB END CO
TYPE RW RW RW
RESET 0x01 0x0 0x1

Table 8-37: Test Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-29
EHS EHS – Early High Speed clock 0 - disable
Bit 28 1 - enable
This bit is used to allow MIPI output to enter HS
1 line earlier before the video data transmission.
Reserved Reserved Not Applicable
Bit 27-21
Reserved Reserved Not Applicable
Bit 20
COMP_SLI COMP_SLICE – Number of Compressed Slice 0 – 1 slice per line
CE per Line ..
Bit 19-16 15 –16 slices per line
These bits indicate the number of slice per line
when the input DSI video stream is compressed
data.
TM TM – Test Mode 00 – Normal mode
Bit 15-14 01 – Inject CRC error
These bits selects whether to inject CRC/ECC 10 – Inject 1 bit ECC error
error for the outgoing streams. They are used for 11 – Inject 2 bit ECC error
debugging purpose only. They should be set to
00 in normal mode.

EIC EIC – Error Injection Control Per Application Condition

Bit 13-9

SSD2829T Rev 1.2 P 73/159 Feb 2018 Solomon Systech

 Name Description Setting
These bits control the position of the error being
injected for testing. It is only applicable when
TM is 01.
DIS_CONT DIS_CONT – Disable Contention input from 0 – Enable
Bit 8 Analog 1 – Disable

This bit selects whether to ignore the error

contention signals output from the Phy.

PNB PNB – Packet Number during Blanking Per Application Condition

Bit 7-2
These bits control the number of packet to send
during video mode blanking period.
END END – Endian-ness 0 – Least significant byte sent first
Bit 1 1 – Most significant byte sent first
This bit specifies the endian-ness of the data
transmitted over the serial link. During video
mode transmission, this bit must be set to 0 so as
to follow the MIPI DSI specification.
CO CO – Color Order 0 – RGB. R is in the higher
Bit 0 portion of the pixel
This bit specifies the order of the color 1 – BGR. B is in the higher
component in the pixel. During video mode portion of the pixel
transmission, this bit must be set to 1 so as to
follow the MIPI DSI specification

Solomon Systech Feb 2018 P 74/159 Rev 1.2 SSD2829T

8.1.37 TE Count Register
Offset Address
TECR TE Count Register 0xD7
BIT 31 30 29 28 27 26 25 24
NAME TEC1[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME TEC1[7:0]
TYPE RW
RESET 0x01

BIT 15 14 13 12 11 10 9 8
NAME TEC0[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TEC0[7:0]
TYPE RW
RESET 0x01

Table 8-38: TE Count Register Description

Name Description Setting

TEC1 TEC1 – TE Counter for MIPITX1 Per Application Condition
Bit 31-16
These bits determines the pulse width of the
output TE signal. A counter will be started after
the TE signal goes to 1. When the counter
reaches the value in TEC1 field, the TE signal
will be set to 0. The counter uses the PLL
reference clock to do counting.

The minimum value is 1.

TEC0 TEC0 – TE Counter for MIPITX0 Per Application Condition
Bit 15-0
These bits determines the pulse width of the
output TE signal. A counter will be started after
the TE signal goes to 1. When the counter
reaches the value in TEC0 field, the TE signal
will be set to 0. The counter uses the PLL
reference clock to do counting.

The minimum value is 1.

SSD2829T Rev 1.2 P 75/159 Feb 2018 Solomon Systech

8.1.38 Analog Control Register 1
Offset Address
ACR1 Analog Control Register 1 0xD8
BIT 31 30 29 28 27 26 25 24
THFT_T THFT_TL LPTX_DS
NAME EN_REG HSTX_RO_IN
LFT1 FT0 [2]
TYPE RW RW RW RW RW
RESET 0x0 0x0 0x1 0x5 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTX_DS[1:0] BG_TRIM_V0P6
TYPE RW RW RW
RESET 0x0 0x3 0x4

BIT 15 14 13 12 11 10 9 8
BG_IDUT
NAME BG_TC BG_TEN BG_TRIM_0P5
Y[2]
TYPE RW RW RW RW
RESET 0x4 0x0 0x3 0x1

BIT 7 6 5 4 3 2 1 0
NAME BG_IDUTY[1:0] BG_IREG BG_ISEL EN_BG
TYPE RW RW RW RW
RESET 0x0 0x1 0x4 0x1

Table 8-39: Analog Control Register 1 Description

Name Description Setting

THFT_TLF THFT_TLFT1 – Low Power Receiver Input Per Application Condition
T1 Threshold High/Low Adjust Bit 1
Bit 31
THFT_TLF THFT_TLFT0 – Low Power Receiver Input Per Application Condition
T0 Threshold High/Low Adjust Bit 0
Bit 30
EN_REG EN_REG – 0.5V LDO enable Per Application Condition
Bit 29
HSTX_RO_I HSTX_RO_IN – Driver output resistance Per Application Condition
N control
Bit 28-25
LPTX_DS LPTX_DS – Low Power Transmitter Drive Per Application Condition
Bit 24-22 Strength
BG_TRIM_ BG_TRIM_V0P6 – Voltage trimming bits Per Application Condition
V0P6
Bit 21-19
Reserved Reserved Not Applicable
Bit 18-16
BG_TC BG_TC – Temperature coefficient Per Application Condition
Bit 15-13 programming bits of bandgap
BG_TEN BG_TEN – Bandgap Test Enable Per Application Condition
Bit 12
BG_TRIM_0 BG_TRIM_0P5 – Voltage trimming bits of Per Application Condition
P5 0.5V LDO
Bit 11-9

Solomon Systech Feb 2018 P 76/159 Rev 1.2 SSD2829T

 Name Description Setting
BG_IDUTY BG_IDUTY – Biasing current adjustment of Per Application Condition
Bit 8-6 duty cycle regulation circuit
BG_IREG BG_IREG – Biasing current adjustment of Per Application Condition
Bit 5-4 0.5V LDO
BG_ISEL BG_ISEL – Biasing current adjustment of Per Application Condition
Bit 3-1 contention detection
EN_BG EN_BG – Bandgap Enable Per Application Condition
Bit 0

SSD2829T Rev 1.2 P 77/159 Feb 2018 Solomon Systech

8.1.39 RGB Interface Control Register 7
Offset Address
RICR7 RGB Interface Control Register 7 0xDD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VEC XEQ1 XEQ0
TYPE RO RO RO RO RO RW RWAC RWAC
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME VBN VFN
TYPE RW RW
RESET 0x0 0x0

Table 8-40: RGB Interface Control Register 7 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-11
VEC VEC – Video Enable Control 0 - Any command received will
Bit 10 output immediately if there is no
This bit controls how command is handled video packet to send.
during video mode, VEN.
1 - Any command received will
only be output during the
blanking period after first video
packet is received. If
there is no video packet to be
sent, the command is held.
XEQ1 XEQ1 – Execute Queue for MIPITX1 0 - Do nothing
Bit 9 1 - Send Execute Queue
This bit will cause SSD2829T to generate Packet(0x16) at the last line of
Execute Queue Packet(0x16) at the last line of the current frame, after hsync.
the frame, after hsync packet. It will be cleared
when Execute Queue Packet is sent out.

This bit is auto cleared by hardware.

XEQ0 XEQ – Execute Queue for MIPITX0 0 - Do nothing
Bit 8 1 - Send Execute Queue
This bit will cause SSD2829T to generate Packet(0x16) at the last line of
Execute Queue Packet(0x16) at the last line of the current frame, after hsync.
the frame, after hsync packet. It will be cleared
when Execute Queue Packet is sent out.

This bit is auto cleared by hardware.

Solomon Systech Feb 2018 P 78/159 Rev 1.2 SSD2829T

 Name Description Setting
VBN VBN – Vertical Back Porch Non Video Data Per Application Condition
Bit 7-4 Window

These fields specify the number of vertical back

porch counting backward from the first vertical
active line in which non-video data is not
allowed to be sent via MIPI link.
This field is only valid when VEN is 1 and the
interface setting is RGB + SPI(if_sel[0] = 0).

This field should not larger than VBP

VFN VFN – Vertical Front Porch Non Video Data Per Application Condition
Bit 3-0 Window

These fields specify the number of vertical front

porch counting forward from the last vertical
active line in which non-video data is not
allowed to be sent via MIPI link.
This field is only valid when VEN is 1 and the
interface setting is RGB + SPI(if_sel[0] = 0).

This field should not larger than VFP.

SSD2829T Rev 1.2 P 79/159 Feb 2018 Solomon Systech

8.1.40 INOUT Configuration Control Register
Offset Address
IOCR INOUT Configuration Register 0xDE
BIT 31 30 29 28 27 26 25 24
MCU_SW MCU_SW BIT_SWA
NAME
AP1 AP0 P1
TYPE RO RO RO RO RO RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
BIT_SW PIXEL_S PIXEL_S
NAME
AP0 WAP1 WAP0
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
TX_REA
NAME TX_WRITE TX_DUAL TX_LS1 TX_LS0
D
TYPE RW RW RW RW RW
RESET 0x0 0x1 0x0 0x0 0x0

Table 8-41: INOUT Configuration Register Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-27
MCU_SWA Reserved Not Applicable
P1
Bit 26
MCU_SWA MCU_SWAP0 – MCU data swap for MCU 0 – No Swap
P0 1 –Swap MCU data MSB to
Bit 25 This bit defines how the SSD2829T interpret the LSB
MCU input.
BIT_SWAP1 Reserved Not Applicable
Bit 24
BIT_SWAP0 BIT_SWAP0 – RGB bit swap for RGB 0 – No Swap
Bit 23 1 –Swap RGB pixel MSB to
This bit defines how the SSD2829T interpret the LSB
RGB video input.
PIXEL_SW Reserved Not Applicable
AP1
Bit 22
PIXEL_SW BIT_SWAP0 – RGB pixel swap for RGB 0 – No Swap
AP0 1 –Swap RGB pixel upper and
Bit 21 This bit defines how the SSD2829T interpret the lower
RGB video input.
Reserved Reserved Not Applicable
Bit 20

Solomon Systech Feb 2018 P 80/159 Rev 1.2 SSD2829T

 Name Description Setting
Reserved Reserved Not Applicable
Bit 19-18
Reserved Reserved Not Applicable
Bit 17-16
Reserved Reserved Not Applicable
Bit 15-8
TX_READ TX_READ – TX read 0 - Read from MIPITX0
Bit 7 1 - Read from MIPITX1
This bit determines the destination of the read
command when SSD2829T is configured as 1
input with 2 output(MIPITX).
TX_WRITE TX_WRITE – TX write 00 - Discard
Bit 6-5 01 - Write to MIPITX0
This bit determines the destination of the write 10 - Write to MIPITX1
command when SSD2829T is configured as 1 11 - Write to MIPITX0 and
input with 2 output(MIPITX). MIPITX1
TX_DUAL TX_DUAL – MIPITX dual mode 0 – Single mode
Bit 4 1 – Dual mode
This bit defines the dual/single mode of
MIPITX.
TX_LS1 TX_LS1 – Lane Select for MIPITX1 00 – 1 lane mode
Bit 3-2 01 – 2 lane mode
These bits define the number of lane to be used 10 – 3 lane mode
for MIPITX1 in SSD2829T. 11 – 4 lane mode
TX_LS0 TX_LS0 – Lane Select for MIPITX0 00 – 1 lane mode
Bit 1-0 01 – 2 lane mode
These bits define the number of lane to be used 10 – 3 lane mode
for MIPITX0 in SSD2829T. 11 – 4 lane mode

SSD2829T Rev 1.2 P 81/159 Feb 2018 Solomon Systech

8.1.41 APB Write Register
Offset Address
AWR APB Write Register 0xE0
BIT 47 46 45 44 43 42 41 40
NAME DATA[31:24]
TYPE W
RESET 0x00

BIT 39 38 37 36 35 34 33 32
NAME DATA[23:16]
TYPE W
RESET 0x00

BIT 31 30 29 28 27 26 25 24
NAME DATA[15:8]
TYPE W
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME DATA[7:0]
TYPE W
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME ADDR[15:8]
TYPE W
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME ADDR[7:0]
TYPE W
RESET 0x00

Table 8-42: Delay Adjustment Register Description

Name Description Setting

DATA DATA – 32-bit write data for APB Refer to APB write section
Bit 47-16
ADDR ADDR – 16-bit address for APB write/read Refer to APB write section
Bit 15-0

Solomon Systech Feb 2018 P 82/159 Rev 1.2 SSD2829T

8.1.42 APB Read Register
Offset Address
ARR APB Read Register 0xE1
BIT 31 30 29 28 27 26 25 24
NAME DATA[31:24]
TYPE R
RESET 0x0

BIT 23 22 21 20 19 18 17 16
NAME DATA[23:16]
TYPE R
RESET 0x0

BIT 15 14 13 12 11 10 9 8
NAME DATA[15:8]
TYPE R
RESET 0x0

BIT 7 6 5 4 3 2 1 0
NAME DATA[7:0]
TYPE R
RESET 0x0

Table 8-43: APB Read Register Description

Name Description Setting

DATA DATA – 32 bits read data Refer to APB read section
Bit 31-0

SSD2829T Rev 1.2 P 83/159 Feb 2018 Solomon Systech

8.2 Local (APB) Register Descriptions
The APB registers have 16 bit address, of which the most significant 4 bits represent the base address of the
APB peripheral, and the least significant 16 bits represent the offset within the APB peripheral. The table
below shows the APB peripherals and their respective base address & address range.

Address Module

0x0000 – 0x0FFF SCM

0x1000 – 0x1FFF Reserved

0x2000 – 0x2FFF Reserved

0x3000 – 0x3FFF Reserved

0x4000 – 0x4FFF Reserved

0x5000 – 0x7FFF Video BIST

0x6000 – 0x6FFF Pixel Peek

Solomon Systech Feb 2018 P 84/159 Rev 1.2 SSD2829T

8.2.1 SCM Registers Descriptions

8.2.1.1 SCM Miscellaneous Control Register

Offset Address
SCM_MISC SCM Miscellaneous Control Register 0x0010
BIT 31 30 29 28 27 26 25 24
NAME ckmon lpstate
TYPE RO RO RW RW RW RW RW
RESET 0x0 0x0 0x1 0x0 0x1 0x1 0x0

BIT 23 22 21 20 19 18 17 16
NAME v2c
TYPE RW RW RW RW RW RW
RESET 0x2 0x1 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RW RW RW RW
RESET 0x0 0x3 0x1 0x0

BIT 7 6 5 4 3 2 1 0
NAME flip1 flip0
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-44: SCM Miscellaneous Control Description

SSD2829T Rev 1.2 P 85/159 Feb 2018 Solomon Systech

 Name Description Setting
Reserved Not Applicable
Reserved
Bit31-30
Clock Monitor on TE_OUT0 – Per Application Condition
clkmon
This bit enable the TE_OUT0 to be used as
Bit29
clkout monitor signals
LP State – 0=LP00
lpstate
This bit controls the state of the link when the 1=LP11
Bit28
chip is powered down
Reserved
Reserved Not Applicable
Bit 27-17
v2c Video to Cmd – Indicates whether video is 0=Disable
Bit 16 converted to 2C/3C commands. 1=Enable
Reserved Not Applicable
Reserved
Bit 15-12
Reserved Not Applicable
Reserved
Bit 11-9
Reserved Reserved Not Applicable
Bit 8
MIPI Left/Right Flip for DSI1 – 0x0 = Data received from read
mtx_flip1 This bit configures the left and right image swap from left to right (Default)
Bit 7 at the MIPI output. 0x1 = Data received from read
from right to left
MIPI Left/Right Flip for DSI0 – 0x0 = Data received from read
mtx_flip0 This bit configures the left and right image swap from left to right (Default)
Bit 6 at the MIPI output. 0x1 = Data received from read
from right to left
Reserved Reserved Not Applicable
Bit 5-4
Reserved Reserved Not Applicable
Bit 3
Reserved Reserved Not Applicable
Bit 2-1
Reserved Reserved Not Applicable
Bit 0

Solomon Systech Feb 2018 P 86/159 Rev 1.2 SSD2829T

8.2.1.2 SCM Scratch Register
Offset Address
SCM_SCRATCH SCM Scratch Register 0x0014
BIT 31 30 29 28 27 26 25 24
NAME scratch[31:24]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME scratch[23:16]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME scratch[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME scratch0[7:0]
TYPE RW
RESET 0x00

Table 8-45: SCM Scratch Register Description

Name Description Setting

scratch Scratch Register – User can use this register to Per Application Condition
Bit 31-0 store any value

SSD2829T Rev 1.2 P 87/159 Feb 2018 Solomon Systech

8.2.2 Video BIST Register Descriptions

8.2.2.1 Video BIST Register 0

Offset Address
VBISTR0 Video BIST Register 0 0x000
BIT 31 30 29 28 27 26 25 24
NAME VB_REPEAT_CNT[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_REPEAT_CNT[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_MODE{3:0} VB_CFG_MODE[1:0] VB_CSPF VB_EN
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-46: Video BIST Register 0 Description

Name Description Setting
VB_REPEAT_CNT[1 Video BIST Repeat Count – These Video BIST section for more
5:0] bits set the repeat count for video information.
Bit 31-16 pattern generation. It will have
different meaning for different
VB_MODE.
Reserved Reserved Not Applicable
Bit15-8
VB_MODE[3:0] Video BIST Mode – These bits select Video BIST section for more
Bit 7-4 the Video BIST image pattern. information.
VB_CFG_MODE[1:0 Video BIST Config Mode – These 0 – Single data buffer mode
] bits select the mode that video bist (Normal)
Bit 3-2 generate the pattern 1 – Reserved
2 – Reserved
3 – Dual data buffer mode
(Broadcast)
VB_CSPF Video BIST Color Swap per Frame 0 – Disable
Bit 1 – This bit enable the color swap per 1 – Enable
frame
VB_EN Video BIST Enable – This bit enable 0 – Disable
Bit 0 the Video BIST function 1 – Enable

Solomon Systech Feb 2018 P 88/159 Rev 1.2 SSD2829T

8.2.2.2 Video BIST Register 1
Offset Address
VBISTR1 Video BIST Register 1 0x004
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_X_R[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_X_R[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-47: Video BIST Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31-10
VB_COLOR_X_R[ Video BIST Color X Red Component 30bpp – [9:0]
9:0] – These bits specify the Color X Red 24bpp – [7:0]
Bit 9-0 Component.

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8.2.2.3 Video BIST Register 2
Offset Address
VBISTR2 Video BIST Register 2 0x008
BIT 31 30 29 28 27 26 25 24
NAME VB_COLOR_X_G[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_COLOR_X_G[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_X_B[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_X_B[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-48: Video BIST Register 2 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31–26
VB_COLOR_X_G[ Video BIST Color X Green 30bpp – [9:0]
9:0] Component – These bits specify the 24bpp – [7:0]
Bit 25–16 Color X Red Component.
Reserved Reserved Not Applicable
Bit 15–10
VB_COLOR_X_B[ Video BIST Color X Blue Component 30bpp – [9:0]
9:0] – These bits specify the Color X Red 24bpp – [7:0]
Bit 9-0 Component.

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8.2.2.4 Video BIST Register 3
Offset Address
VBISTR3 Video BIST Register 3 0x00C
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_Y_R[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_Y_R[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-49: Video BIST Register 3 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31–10
VB_COLOR_Y_R[ Video BIST Color X Red Component 30bpp – [9:0]
9:0] – These bits specify the Color X Red 24bpp – [7:0]
Bit 9-0 Component.

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8.2.2.5 Video BIST Register 4
Offset Address
VBISTR4 Video BIST Register 4 0x010
BIT 31 30 29 28 27 26 25 24
NAME VB_COLOR_Y_G[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_COLOR_Y_G[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_Y_B[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_Y_B[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-50: Video BIST Register 4 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31–26
VB_COLOR_Y_G[ Video BIST Color Y Green 30bpp – [9:0]
9:0] Component – These bits specify the 24bpp – [7:0]
Bit 25–16 Color Y Red Component.
Reserved Reserved Not Applicable
Bit 15–10
VB_COLOR_Y_B[ Video BIST Color Y Blue Component 30bpp – [9:0]
9:0] – These bits specify the Color Y Red 24bpp – [7:0]
Bit 9-0 Component.

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8.2.2.6 Video BIST Register 5
Offset Address
VBISTR5 Video BIST Register 5 0x014
BIT 31 30 29 28 27 26 25 24
NAME VB_X_START[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_X_START[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_X_END[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_X_END[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-51: Video BIST Register 5 Description

Name Description Setting

VB_X_START[15 Video BIST X Start – These bits define Per Application Condition
:0] the X starting position.
Bit 31–16
VB_X_END[15:0] Video BIST X End – These bits define Per Application Condition
Bit 15–0 the X end position.

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8.2.2.7 Video BIST Register 6
Offset Address
VBISTR6 Video BIST Register 6 0x018
BIT 31 30 29 28 27 26 25 24
NAME VB_Y_START[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_Y_START[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_Y_END[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_Y_END[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-52: Video BIST Register 6 Description

Name Description Setting

VB_Y_START[15 Video BIST Y Start – These bits define Per Application Condition
:0] the Y starting position.
Bit 31–16
VB_Y_END[15:0] Video BIST Y End – These bits define Per Application Condition
Bit 15–0 the Y end position.

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8.2.3 Pixel Peek Registers Descriptions

8.2.3.1 Pixel Peek Register 0

Offset Address
PIXELPEEKR0 Pixel Peek Register 0 0x000
BIT 31 30 29 28 27 26 25 24
NAME CURSOR_POSITION_Y[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME CURSOR_POSITION_Y[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME CURSOR_POSITION_X[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME CURSOR_POSITION_X[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-53: Pixel Peek Register 0 Description

Name Description Setting

CURSOR_POSITION_Y Cursor Position Y – These bits set Per Application Condition
[15:0] the y-coordinate to measure
Bit 31–16
CURSOR_POSITION_X Cursor Position X – These bits set Per Application Condition
[15:0] the x-coordinate to measure
Bit 15–0

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8.2.3.2 Pixel Peek Register 1
Offset Address
PIXELPEEKR1 Pixel Peek Register 1 0x004
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
CURSOR
PREVEN
CURSOR _COLOR
NAME T_UPDAT CURSOR_COLOR_RGB[2:0]
_VISIBLE _DYNAM
E
IC
TYPE RO RO RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-54: Pixel Peek Register 1 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31–6
PREVENT_UPDATE Prevent Update – Set this bit Per Application Condition
Bit 5 before reading the values.
CURSOR_VISIBLE Cursor Visible – This bit enable 0 = disable
Bit 4 cursor display. 1 = enable
CURSOR_COLOR_DYN Cursor Color Dynamic – This 0 = disable
AMIC bit enable dynamic color for 1 = enable
Bit 3 cursor
CURSOR_COLOR_BGR[ Cursor Color BGR – These bits Per Application Condition
2:0] set the color for cursor (BGR, B
Bit 2–0 on MSB).

Solomon Systech Feb 2018 P 96/159 Rev 1.2 SSD2829T

8.2.3.3 Pixel Peek Register 2
Offset Address
PIXELPEEKR2 Pixel Peek Register 2 0x008
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 15 14 13 12 11 10 9 8
NAME MEAS_VALUE_B[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 7 6 5 4 3 2 1 0
NAME MEAS_VALUE_B[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00

Table 8-55: Pixel Peek Register 2 Description

Name Description Setting

Reserved Reserved Not Applicable
Bit 31–16
MEAS_VALUE_B[15 Measure Value B – Measured value Per Application Condition
:0] for Blue.
Bit 15–0

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8.2.3.4 Pixel Peek Register 3
Offset Address
PIXELPEEKR3 Pixel Peek Register 3 0x00C
BIT 31 30 29 28 27 26 25 24
NAME MEAS_VALUE_G[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME MEAS_VALUE_G[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME MEAS_VALUE_R[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME MEAS_VALUE_R[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0

Table 8-56: Pixel Peek Register 3 Description

Name Description Setting

MEAS_VALUE_G[1 Measure Value G – Measured value Per Application Condition
5:0] for Green.
Bit 31–16
MEAS_VALUE_R[15 Measure Value R – Measured value Per Application Condition
:0] for Red.
Bit 15–0

Solomon Systech Feb 2018 P 98/159 Rev 1.2 SSD2829T

9 MAXIMUM RATINGS
Table 9-1: Maximum Ratings (Voltage Referenced to VSS)

Symbol Parameter Min Typ Max Unit

AVDD Analog Power Supply -0.3 - 1.44 V

AVDD_RC Analog Power Supply -0.3 - 1.44 V

VCIP Analog Power for Bandgap, 3.3V -0.3 - 3.96 V

VDRV Analog Power for MIPI TX Driver -0.3 - 1.44 V

VDD_CORE Digital Core Power Supply -0.3 - 1.44 V

VDDIO I/O Power Supply -0.3 - 3.96 V

o
TSTG Storage Temperature -40 - 150 C

Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to the
limits in the Electrical Characteristics tables or Pin Description section

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance
circuit. For proper operation it is recommended that VCI and VOUT be constrained to the range VSS < VDD  VCI < VOUT. Reliability of
operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g., either V SS or VDD). Unused outputs must
be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during
normal operation. This device is not radiation protected.

10 DC OPERATING CONDITIONS

Table 10-1 : Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

AVDD Analog Power Supply 1.17 1.3 1.43 V

AVDD_RC Analog Power Supply 1.17 1.3 1.43 V

VDD_CORE Digital Core Power Supply 1.17 1.3 1.43 V

I/O Power Supply 1.62 1.8 1.98 V

VDDIO
I/O Power Supply 2.7 3.3 3.6 V
o
TA Operating Temperature -40 25 85 C

SSD2829T Rev 1.2 P 99/159 Feb 2018 Solomon Systech

10.1 DC CHARACTERISTICS

Symbol Parameter Test Condition Min Typ Max Unit

Current for all 1.3V

IDD_1.3V_active supplies for active Active Mode (Video Mode) - 165 275 mA
mode 2560x1600@60Hz,
Current for all 1.8V [email protected] x 8 lanes
IDD_1.8V_active supplies for active - 7 15 mA
mode

Current for VCIP

IDD_3.3V_active supply for active - 100 200 uA
mode

Current for all 1.3V

IDD_1.3V_powerdown supplies for power Power Down mode - 121 275 A
down mode MIPIRX off
MIPITX off
Current for all 1.8V
IDD_1.8V_powerdown supplies for power - 300 600 A
down mode

Current for VDDIO

(1.8/3.3V) supplies
IDD_1.8V_powerdown - 300 600 A
for power down
mode

Output High Voltage

VOH (CMOS) IOH = -2 ~ -16 mA VDDIO*80% - - V
(CMOS)

Output Low Voltage

VOL (CMOS)
(CMOS)
IOL= 2 ~ 16 mA - - VDDIO*15% V

Input High Voltage

VIH (CMOS) - VDDIO*70% - - V
(CMOS)

Input Low Voltage

VIL (CMOS) - - - VDDIO*20% V
(CMOS)

Tri-state Output
IOZ - -1 - +1 A
Leakage Current

Input Leakage
IIN - -1 - +1 A
Current

Solomon Systech Feb 2018 P 100/159 Rev 1.2 SSD2829T

11 AC CHARACTERISTICS

11.1 Power Up Timing

Symbol Parameters Min Typ Max Units

Rise time for all 1.3V VDD supplies (10% to

TVDD12_RISE 1 - 10 ms
90%)

Rise time for all 1.8V VDD supplies (10% to

TVDD18_RISE 1 - 10 ms
90%)

Time from 1.3V supplies on to 1.8V and 3.3V

supplies on.
TVDD18_ON Note: If VDD18 is applied before VDD12 is applied, there -5 - 30 ms
could be up to 1mA of additional leakage during the period
when VDD12 is still not available.

11.2 RESET Timing

Symbol Parameters Min Typ Max Units

TRESET RESET_IN “Low” Pulse Width 10 - - us

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11.3 Interface Timing

11.3.1 MCU Interface (Type A) Timing

Symbol Parameter Min Typ Max Unit
TMC MCU clock frequency - - 160 Mhz
tCYCLE_W
Clock Cycle Time(Write) 1 - - TMC
R
tCYCLE_RD Clock Cycle Time(Read) 8 - - TMC
pwCSL Control Pulse Low Width 0.5 - - TMC
pwCSH Control Pulse High Width 0.5 - - TMC
tAS Address Setup Time 1.6 - - ns
tAH Address Hold Time 1.6 - - ns
tDSW Data Setup Time 1.6 - - ns
tDHW Data Hold Time 1.6 - - ns
tACC Data Access Time 12 - - ns
tDHR Read Data Hold time tCYCLE_RD ns
- -
/2
tR Rise time 1 - - ns
tF Fall time 1 - - ns

Table 11-1 MCU Interface (Type A) Timing Characteristics

VIH VIH
dcx
VIL VIH
tAS
tAH
VIH VIH
rwx
VIL VIL

VIH VIH
tF tR
csx
VIL VIL
tCYCLE_WR /tCYCLE_RD
pwCSH pwCSL
e

tDHW
tDSW
VIH VIH
data
Valid Data
(WRITE) VIL VIL

tACC tDHR
data VIH VIH
(READ)
Valid Data
VIL VIL

Figure 11-1 MCU Interface (Type A) Timing Diagram

Note: VIL and VIH refers to DC CHARACTERISTICS

Solomon Systech Feb 2018 P 102/159 Rev 1.2 SSD2829T

11.3.2 MCU Interface (Type B) Timing
Symbol Parameter Min Typ Max Unit
TMC MCU Clock Frequency - - 160 Mhz
tCYCLE_W
Clock Cycle Time(Write) 1 - - TMC
R
tCYCLE_RD Clock Cycle Time(Read) 8 - - TMC
pwCSL Control Pulse Low Width 0.5 - - TMC
pwCSH Control Pulse High Width 0.5 - - TMC
tAS Address Setup Time 1.6 - - ns
tAH Address Hold Time 1.6 - - ns
tDSW Data Setup Time 1.6 - - ns
tDHW Data Hold Time 1.6 - - ns
tACC Data Access Time 12 - - ns
tDHR Read Data Hold time tCYCLE_RD ns
- -
/2
tR Rise time 1 - - Ns
tF Fall time 1 - - Ns

Table 11-2: MCU Interface (Type B) Timing Characteristics

Write

VIH VIH
dcx
VIL VIL

tAS tAH
VIH VIH
csx tF tR
VIL VIL
tCYCLE_WR
pwCSH
pwCSL
wrx

rdx
tDHW
tDSW

VIH VIH
data Valid Data
VIL VIL

SSD2829T Rev 1.2 P 103/159 Feb 2018 Solomon Systech

Read

VIH VIH
dcx
VIL
VIL
tAS tAH
VIH VIH
csx tR
tF
VIL VIL

wrx
tCYCLE_RD PWCSH
PWCSL

rdx

tACC tDHR
data VIH VIH
Valid Data
VIL VIL

Note: VIL and VIH refers to DC CHARACTERISTICS

Solomon Systech Feb 2018 P 104/159 Rev 1.2 SSD2829T

11.3.3 SPI Interface Timing
Symbol Parameters Min Typ Max Units
TMC SPI Clock Frequency - - 50 Mhz
tCYCLE_WR Clock Cycle Time(Write) 1 - - TMC
tCYCLE_RD Clock Cycle Time(Read) 4 - - TMC
tCSS Chip Select Setup Time 2 - - ns
tCSH Chip Select Hold Time 4 - - ns
tDCS Chip Select Setup Time(for 4 wire 8 bit mode) 2 - - ns
tDCH Chip Select Hold Time(for 4 wire 8 bit mode) 4 - - ns
tDSW Write Data Setup Time 2 - - ns
tOHW Write Data Hold Time 4 - - ns
tACC Read Data Access Time 8 - - ns
tCYCLE_RD
tDHR Read Data Hold Time - - ns
/2
tCSWD Chip Select Write Delay Time 1 - - TBC
tCSRD Chip Select Read Delay Time 1 - - TBC
tR Rise time 1 - - ns
tF Fall time 1 - - ns

Figure 11-2 SPI Interface Timing Characteristics

Write

csx/dcx tCSS /tDCS tCSH /tDCH VIH VIH

VIL VIL tCSWD

tCYCLE_WR
VIH
VIH VIH
sck VIL
tF VIL tR VIL

tDSW tDHW
VIH VIH
sdin Valid Data
VIL VIL

Read

tCSS VIH VIH

tCSH
csx
VIL VIL
tCSRD
tCYCLE_RD

VIH VIH VIH

sck
VIL VIL VIL
tF tR

tACC tDHR

VIH VIH
sdout Valid Data
VIL VIL

Figure 11-3: SPI Interface Timing Diagram

Note: VIL and VIH refers to DC CHARACTERISTICS

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11.3.4 RGB Interface Timing
Symbol Parameters Min Typ Max Units
tpclk pclk Period 5.5 - - ns
tvsys Vertical Sync Setup Time 1.7 - - ns
tvsyh Vertical Sync Hold Time 1.7 - - ns
thsys Horizontal Sync Setup Time 1.7 - - ns
thsyh Horizontal Sync Hold Time 1.7 - - ns
thv Phase difference of Sync Signal Falling Edge -1 0 1 tpclk
tds Data Setup Time 1.7 - - ns
tdh Data hold Time 1.7 - - ns
tch2ch Phase difference of channel 0 and 1 -1 0 2 tpclk
Table 11-3 RGB Interface Timing Characteristics

Note: The link should run at greater or equal than the pclk frequency * bit per pixel (bpp).

tvsys tvsyh

vsync
thsys thsyh

hsync
thv
tDOTCLK

pclk

tds tdh

data

tch2ch

Ch 0 RGB

Ch 1 RGB

Figure 11-4: RGB Interface Timing Diagram

Solomon Systech Feb 2018 P 106/159 Rev 1.2 SSD2829T

12 POWER UP SEQUENCE

VDDIO
VCIP
>=0ms

AVDD
VDD_CORE

>=0ms

>=10ms

RESB

>=0ms

XTAL_IN

>=1ms

Input
interface PLL ON
e.g. SPI
Leave ULP mode
>=1ms

Sleep out PEN = 1 SLP = 0 VEN&HS = 1

command Video mode ON
>=1ms

RGB signals

SSD2829T Rev 1.2 P 107/159 Feb 2018 Solomon Systech

13 POWER OFF SEQUENCE

VDDIO
VCIP
>=0ms

AVDD
VDD_CORE

>=0ms

RESB

>=0ms

XTAL_IN

Video mode OFF Enter ULP mode PLL OFF

>=10ms
Sleep in
command VEN&HS = 0 SLP = 1 PEN = 0
>=0ms

RGB signals

Solomon Systech Feb 2018 P 108/159 Rev 1.2 SSD2829T

14 MIPI DPHY CHARACTERISTICS

Figure 14-1 D-PHY Signaling Levels

Figure 14-2 DDR Clock Definition

SSD2829T Rev 1.2 P 109/159 Feb 2018 Solomon Systech

 Table 14-1 : Clock Signal Specification

Solomon Systech Feb 2018 P 110/159 Rev 1.2 SSD2829T

14.1 MIPI DPHY HS CHARACTERISTICS

Table 14-2 HS Transmitter DC Specifications

Table 14-3 HS Transmitter AC Specifications

SSD2829T Rev 1.2 P 111/159 Feb 2018 Solomon Systech

 Table 14-4 LP Transmitter DC Specifications

Solomon Systech Feb 2018 P 112/159 Rev 1.2 SSD2829T

 Table 14-5 LP Transmitter AC Specifications

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15 OPERATING MODE
15.1 Programming Model
The table below shows the local register map summary in SSD2829T.

Table 15-1: SSD2829T Local Register Map

Command Description
Some of the commands would have additional data parameters added to support
0xB0 – 0xDF
extension of certain register fields. For example VBP (Vertical back porch) is an 8-
bit field. With the extension of the number of data parameters, VBP can now
become a 16-bit field. The original register fields’ location would be maintained in
the first 2 data parameters for back-ward compatibility purpose. Only 2 data
parameters would be added.
This is the command for APB peripheral access (e.g. SCM)
0xE0

If all 6 data parameters are given, SSD2829T would issue APB write access with
the APB_ADDR and APB_DATA.

If only 2 data parameters are given, SSD2829T would store the APB_ADDR for
read operation. Host can do a data read to read back the APB_DATA.

Data Parameter Description

1 APB_ADDR[7:0]
2 APB_ADDR[15:8]
3 APB_DATA[7:0]
4 APB_DATA[15:8]
5 APB_DATA[23:16]
6 APB_DATA[31:24]

0xE1 – 0xFE Reserved

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15.1.1 Access Local (non-APB) Registers

The legacy registers (16-bit accessed) are accessed in term of 2 bytes per cycle for all MCU interfaces, except
8-bit format which requires 3 cycles to access (1 command, 2 data cycles)
In the first write cycle, only 8-bit data are written into the SSD2829T, as the address can only be 8-bit. No
matter whether the interface is 8-bit, 16-bit and 24-bit lower 8 bits are used. Please refer to the table below.

Interface Data pins

types
D53-D30 D23-D16 D15-D8 D7-D0
24-bit,
16-bit, Don’t care Don’t care Don’t care Address
8-bit
Table 15-2: MCU Interface Data Pin Mapping for Command Cycle for Legacy Registers
In the sub-sequent read or write cycle, the data width is only 16-bit or 2 bytes no matter the interface width is
selected, except for 8-bit format. Please refer to the table below.
If there are 4 bytes in the legacy registers due to data parameters extension, there will be additional data cycles
accordingly.

Interface Data pins

types Cycle Note
D53-D30 D23-D16 D15-D8 D7-D0
24-bit, 1st Don’t care Don’t care Data Byte 1 Data Byte 0 (1)
16-bit
2nd Don’t care Don’t care Data Byte 3 Data Byte 2 (2)
1st Don’t care Don’t care Don’t care Data Byte 0 (1)
2nd Don’t care Don’t care Don’t care Data Byte 1 (2)
8-bit
3rd Don’t care Don’t care Don’t care Data Byte 2 (3)
4th Don’t care Don’t care Don’t care Data Byte 3

Table 15-3: MCU Interface Data Pin Mapping for Legacy Register
Note:
(1) If the local registers have 4 bytes of data, host can either write 2 bytes or 4 bytes of data.
(2) If the local registers have only 2-bytes of data, any extra write will be ignored
(3) For 8-bit interface, all writes must be in multiple of 2 cycles

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15.1.2 Access Local (APB) Registers for Write

The APB peripheral’s registers are accessed by 0xE0. The data content of 0xE0 are 6 bytes and arranged in the
order of {addr low, addr high, data0, data1, data2, data3}, where addr low is sent first.
In the first write cycle, only 8-bit data are written into the SSD2829T, as the address can only be 8-bit. No
matter whether the interface is 8-bit, 16-bit and 24-bit, lower 8 bits are used. Please refer to the table below.

Interface Data pins

types
D53-D30 D23-D16 D15-D8 D7-D0
24-bit,
16-bit, Don’t care Don’t care Don’t care 0xE0
8-bit
Table 15-4: MCU Interface Data Pin Mapping for Command Cycle for Extended Registers Write
In the sub-sequent write cycle, the data width is only 16-bit or 2 bytes, no matter the interface width is selected,
excepted for 8-bit format. Please refer to the table below.
Interface Data pins
types Cycle
D53-D30 D23-D16 D15-D8 D7-D0
1st Don’t care Don’t care Addr High Addr Low
24-bit, 2nd Don’t care Don’t care Data Byte 1 Data Byte 0
16-bit
3rd Don’t care Don’t care Data Byte 3 Data Byte 2
1st Don’t care Don’t care Don’t care Addr Low
2nd Don’t care Don’t care Don’t care Addr High
3rd Don’t care Don’t care Don’t care Data Byte 0
8-bit
4th Don’t care Don’t care Don’t care Data Byte 1
5th Don’t care Don’t care Don’t care Data Byte 2
6th Don’t care Don’t care Don’t care Data Byte 3

Table 15-5: MCU Interface Data Pin Mapping for Extended Registers Write

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15.1.3 Access APB Registers for Read

The APB peripheral’s registers are accessed by 0xE0. The content of 0xE0 are 2 bytes and arranged in the order
of {addr low, addr high}, where addr low is sent first.
In the first write cycle, only 8-bit data are written into the SSD2829T, as the address can only be 8-bit. No
matter whether the interface is 8-bit, 16-bit or 24-bit, lower 8 bits are used. Please refer to the table below.

Interface Data pins

types
D53-D30 D23-D16 D15-D8 D7-D0
24-bit,
16-bit, Don’t care Don’t care Don’t care 0xE0
8-bit
Table 15-6: MCU Interface Data Pin Mapping for Command Cycle for Extended Registers Read

Prior to the read cycles, the host must set the address of the extended registers to be read through write 0xE1.
In the sub-sequent write cycle, the data width is only 16-bit or 2 bytes no matter what interface width is selected,
except for 8-bit format. Please refer to the table below.

Interface Data pins

types Cycle
D53-D30 D23-D16 D15-D8 D7-D0
24-bit,
1st Don’t care Don’t care Addr High Addr Low
16-bit
1st Don’t care Don’t care Don’t care Addr Low
8-bit
2nd Don’t care Don’t care Don’t care Addr High

Table 15-7: MCU Interface Data Pin Mapping for Extended Registers Address Set

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For the read cycles, the host read the data in 16-bit or 2 bytes format no matter what interface width is selected
except for 8-bit format. Please refer to the table below. Please refer to the table below.

Interface Data pins

types Cycle
D53-D30 D23-D16 D15-D8 D7-D0

24-bit, 1st Don’t care Don’t care Read Data 1 Read Data 0
16-bit 2 nd
Don’t care Don’t care Read Data 3 Read Data 2
1 st
Don’t care Don’t care Don’t care Read Data 0
2nd Don’t care Don’t care Don’t care Read Data 1
8-bit
3rd Don’t care Don’t care Don’t care Read Data 2
4th Don’t care Don’t care Don’t care Read Data 3

Table 15-8: MCU Interface Data Pin Mapping for Extended Registers Address Set

Solomon Systech Feb 2018 P 118/159 Rev 1.2 SSD2829T

15.2 SPI Interface
SSD2829T supports three types of SPI interface,
8-Bit 3 wire (type C option 1, DBI 2.0)
8-Bit 4 wire (type C option 3, DBI 2.0)
24-bit 3 wire
The selection is controlled by ps[1:0] pins. The least significant byte should be written first

15.2.1 SPI Interface 8-Bit 4 Wire

This interface consists of sdc, sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-Bit
data. The first cycle should be a command write cycle to specify the register address for access. The subsequent
cycles are read or write cycles for read or write operations.
The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1
operation, the application processor can write or read multiple bytes.
sdcx indicates whether the operation is for data or command. When sdcx is 1, the operation is for data. When
sdcx is 0, the operation is for command. sdcx is sampled at every 8 th rising edge of sck during 1 operation.
During write operation, sdin will be sampled by SSD2829T at the rising edge of sck. The first rising edge of
sck after the falling edge of csx samples the bit 7 of the 8-Bit data. The second rising edge of sck samples the
bit 6 of the 8-Bit data, and so on. The value of sdcx is sampled at the 8 th rising edge of sck, together with bit 0
of the 8-Bit data. Please see the diagram below for illustration. Optionally, the csx can be driven to 1 in between
cycles.

Figure 15-1: SPI Interface 8-bit 4 wire for write

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 Figure 15-2: SPI Interface 8-bit 4 wire for read

Solomon Systech Feb 2018 P 120/159 Rev 1.2 SSD2829T

15.2.2 SPI Interface 8-Bit 3 Wire

This interface consists of sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-Bit data.
The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read
or write cycles for read or write operations.
The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During 1
operation, the application processor can write or read multiple bytes.
Instead of sdcx, an sdcx bit is used to indicate whether the operation is for data or command. Each byte is
associated with an sdcx bit. When sdcx is 1, the operation is for display data. When sdcx is 0, the operation is
for command. The sdcx bit is sent priori to each byte. In other words, the sdcx bit is the first bit of every 9 bits
during 1 operation.
During write operation, sdin will be sampled by SSD2829T at the rising edge of sck. The first rising edge of
sck after the falling edge of csx samples the sdcx bit. The second rising edge samples bit 7 of the 8-Bit data.
The third rising edge of sck samples the bit 6 of the 8-Bit data, and so on. Please see the diagram below for
illustration. Optionally, the csx can be driven to 1 in between cycles.

Figure 15-3: SPI Interface 8-bit 3 wire for write

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 Figure 15-4: SPI Interface 8-bit 3 wire for read

Solomon Systech Feb 2018 P 122/159 Rev 1.2 SSD2829T

15.2.3 SPI Interface 24-Bit 3 Wire

This interface consists of sck, sdin, sdout and csx. It only supports 16-bit data. Each cycle contains 16-bit data.
The first cycle should be a write cycle to specify the register address for access. The subsequent cycles are read
or write cycles for read or write operations.
The csx should be driven from 1 to 0 to start cycle and from 0 to 1 to end a cycle. During 1 operation, the
application processor can have multiple write or read cycles. However, the csx must go from 0 to 1 at the end
of each cycle.
Each cycle contains 24-bit data. Among the 24-bit data, the first 8-Bit are for control purpose and the next 16-
bit are the actual data. The first 6 bits are the ID bit for SSD2829T, which must be 011100. If this field does
not match, the cycle will not be taken in. The 7th bit is the sdcx bit which is the same as the 8-Bit 3 wire interface.
The 8th bit is the RW bit which indicates whether the current cycle is a read or write cycle. When RW is 1, the
cycle is a read cycle. When RW is 0, the cycle is a write cycle.

Figure 15-5: SPI Interface 24-bit 3 wire for write

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 Figure 15-6: SPI Interface 24-bit 3 wire for read

Solomon Systech Feb 2018 P 124/159 Rev 1.2 SSD2829T

15.3 MCU Interface
The SSD2829T supports three types of MCU interface,

Type A, fixed E mode, DBI 2.0

Type A, clocked E mode, DBI 2.0
Type B, DBI 2.0
The selection is controlled by ps[4:2] pins.

PS[4:2] is for the MCU interface

 000: 8-Bit MCU interface (MIPI DBI type B)
 001: 16-bit MCU interface (MIPI DBI type B)
 010: 8-Bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 011: 16-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 100: 24-bit MCU interface (MIPI DBI type B)
 110: 24-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 101: Reserved
 111: Reserved

MCU interfaces support 8-bit, 16-bit and 24-bit data bus. Below are the data pins used for each interface. For
8-Bit interface, the least significant byte should be written first. For 16 or 24-bit interfaces, the lease significant
word should be written first.

 data[15:0] for 16-bit interface

 data[23:0] for 24-bit interface

The local registers are always accessed in 16-bit data word for the data phase of the MCU cycle, irrespective of
any bus width selection.

15.3.1 MCU Interface Type A, fixed E mode

This interface consists of data, rwx, dcx, e and csx. It supports 24-bit, 16-bit and 8-bit data bus. The first cycle
should be a command write cycle to specify the register address for access. The subsequent cycles are read or
write cycles for read or write operations.
‘e’ signal should be driven to 1 in this mode.
rwx indicates whether the operation is a read or a write operation. When rwx is 1, the operation is a read
operation. When rwx is 0, the operation is a write operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the
operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should
be 1.
During the write operation, data are sampled at the rising edge of csx. During read operation, data are provided
at the falling edge of csx and the application processor should use the rising edge of csx to sample.

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 Figure 15-7: Illustration of Write Operation for Type A, Fixed E Mode Interface

Figure 15-8: Illustration of Read Operation for Type A, Fixed E Mode Interface

Solomon Systech Feb 2018 P 126/159 Rev 1.2 SSD2829T

15.3.2 MCU Interface Type A, Clocked E mode

This interface consists of data, rwx, dcx, e and csx. It supports 24-bit, 16-bit and 8-bit data bus. The first cycle
should be a command write cycle to specify the register address for access. The subsequent cycles are read or
write cycles for read or write operations.
csx should be driven to 0 in this mode.
rwx indicates whether the operation is a read or a write operation. When rwx is 0, the operation is a write
operation. When rwx is 1, the operation is a read operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the
operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should
be 1.
During the write operation, data are sampled at the falling edge of E. During read operation, data[23:0] are
provided at the rising edge of e and the application processor should use the falling edge of e to sample.
Below is a diagram for illustration.

Figure 15-9: Illustration of Write Operation for Type A, Clocked E Mode Interface

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 Figure 15-10: Illustration of Read Operation for Type A, Clocked E Mode Interface

Solomon Systech Feb 2018 P 128/159 Rev 1.2 SSD2829T

15.3.3 MCU Interface Type B

This interface consists of data, rdx, wrx, dcx, and csx. It supports 24-bit,16-bit and 8-bit data bus. The first
cycle should be a command write cycle to specify the register address for access. The subsequent cycles are
read or write cycles for read or write operations.
csx should be driven to 0 in this mode.
When wrx is driven from 1 to 0 and 0 to 1, the operation is a write operation. When rdx is driven from 1 to 0
and 0 to 1, the operation is a read operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1, the
operation is for data. When dcx is 0, the operation is for command. During the read operation, the dcx should
be 1.
During the write operation, data are sampled at the rising edge of wrx. During read operation, data[23:0] are
provided at the falling edge of rdx and the application processor should use the rising edge of rdx to sample.
Below is a diagram for illustration.

Figure 15-11: Illustration of Write Operation for Type B Interface

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 Figure 15-12: Illustration of Read Operation for Type B Interface

Solomon Systech Feb 2018 P 130/159 Rev 1.2 SSD2829T

15.3.4 MCU Interface for MIPI Command Packet

Any write to the address ranges from 0x00 to 0xAF will be sent out as MIPI command packet. The type of
packet, whether it is short or long packet, DCS or generic packet is determined by the SSD2829T local registers.
Hence the user should program the local registers prior to any transmission at the MIPI link.
If the host wants to send any addresses in the range of 0xB1 to 0xFF to external MIPI receiver, it can do so
using packet drop command in the 0xBF register.
In the first write cycle, only 8-Bit data are written into the SSD2829T, as the command can only be 8-Bit. No
matter whether the interface is 8-bit, 16-bit or 24-bit, lower 8-bits are used. Please refer to the table below.

Interface Data pins

types
D53-D30 D23-D16 D15-D8 D7-D0
24-bit Don’t care Don’t care Don’t care Command
16-bit Don’t care Don’t care Don’t care Command
8-bit Don’t care Don’t care Don’t care Command

Table 15-9: MCU Interface Data Pin Mapping for Command Cycle

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In the sub-sequent read or write cycles, command parameters can be written into the SSD2829T. Depending
on the interface width, different data pin mapping is adopted. Please refer to the table below.
When the number of parameters is not an integer of the width of the interface type, the remaining bytes should
be put on the lower data buses at the last data cycle.

Interface Data pins

types Cycle
D53-D30 D23-D16 D15-D8 D7-D0
24-bit 1st Don’t care Parameter 3 Parameter 2 Parameter 1
2nd Don’t care Parameter 6 Parameter 5 Parameter 4
3rd Don’t care Parameter 9 Parameter 8 Parameter 7
16-bit 1st Don’t care Don’t care Parameter 2 Parameter 1
2nd Don’t care Don’t care Parameter 4 Parameter 3
3rd Don’t care Don’t care Parameter 6 Parameter 5
1st Don’t care Don’t care Don’t care Parameter 1

8-Bit 2nd Don’t care Don’t care Don’t care Parameter 2

3rd Don’t care Don’t care Don’t care Parameter 3

Table 15-10: MCU Interface Data Pin Mapping for Parameter Cycles

15.3.5 MCU Interface for Local Registers

The local registers for SSD2829T resided in the range from 0xB1 to 0xFF. There are 2 types of local registers,
legacy registers and extended registers.
To expand certain field in the legacy registers, the data bits in that address is extended to 32-bit, or 4-bytes
width from 2-bytes.
The extended registers can be accessed by indirect addressing through the address location 0xE0. The content
of 0xE0 defines the 16-bits addresses and 32-bits data for the extended registers.

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15.4 RGB Interface
SSD2829T supports RGB interface. The input is 48-bit wide and it supports 2-pixels per RGB module using
SDR or DDR input pixel clock.

To support different bpp settings, the following data pins are used. For all cases, Red component should be at
the upper bits and Blue component should be at the lower bits. The type of video packets supported for each
RGB interface is shown below.
Data Bus RGB format
[15:0] 16-bits per pixel for Pixel 1
[45:30] 16-bits per pixel for Pixel 2
[17:0] 18 bits per pixel for Pixel 1

[47:30] 18 bits per pixel for Pixel 2

[23:0] 24-bits per pixel for Pixel 1

[53:30] 24-bits per pixel for Pixel 2

[23:0] Compressed Stream Data(lower)

[53:30] Compressed Stream Data(Upper)

User can also send command mode data through SPI interface, during the video mode transmission. The data
will be sent during the horizontal or vertical blanking period. Since the RGB and SPI interface are completely
separated, the two interfaces can operate independently. The RGB interface is used to provide display data for
the video mode. The SPI interface is used to program the local registers of SSD2829T, or to send command
across the link to the MIPI receiver.

2 supporting data type for compressed stream data:

 Compressed data - PPS (DT=0xA)
 Compression Mode (DT=0x7)
There is a register to be set if incoming MCU command bytes are to be packed as PPS, or Compression-Mode
packet. All the parameters are carried in the PPS packet data, as defined by VESA standard.

15.5 Video Mode Use Cases

15.5.1 RGB + SPI

For this mode, the user must set if_sel[1:0] to “00” to select the interface as a combination of RGB and SPI
interface. The video data come from the RGB interface and the configuration is done through the SPI interface.

The possible video paths (and non-video command paths) supported in this mode are shown below. The SPI
interface can be used to program local registers or transmit command packets during video blanking to MIPI
output.

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 RGB Interface Input, Single MIPI Video Output

RGB Interface 0 MIPI DPHY TX 0

SSD2829T

SPI Interface Local registers

RGB Interface Input, Dual MIPI Video Output

This is either a split use case or a broadcast use case. For split use case, it can be
either odd/even pixel split, or left/right image split

RGB Interface 0 MIPI DPHY TX 0

SSD2829T
MIPI DPHY TX 1

SPI Interface Local registers

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The user, first, needs to set the video parameters through registers programming with correct values. After
programming those register fields, the user can turn on the RGB interface and enable the SSD2829T to start
transmission. All three video mode sequence defined in the MIPI DSI specification are supported.
The PLL multiplication factor should be set such that the serial link data rate is faster than the incoming data
rate. Please refer to the table below for the PLL settings.
Below is the diagram to illustrate the definition of all the fields.

HSA
Hsync

DEN
HBP HACT HFP

Pclk

MIPI_Data[23:0]

VSA
Vsync

VBP VACT VFP

Hsync

Figure 15-13: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Pulses

Hsync

DEN
HBP HACT HFP

Pclk

MIPI_Data[23:0]

Vsync

VBP VACT VFP

Hsync

Figure 15-14: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Events and Burst
Mode

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15.5.1.1 Interleaving Non-Video Packets with Video Packets

Non-video data can be transmitted during the vertical blanking of the video frames, or when nvb (in 0xB6
register) is set, during any BLLP period (including those in the horizontal blanking). It is recommended to
send non-video data during vertical blanking.

The nvd and bllp field (in 0xB6 command) determines how the non-video data is sent. See below table for
illustration.

NVD BLLP Non-burst mode Burst mode

0 0 If there is no non-video data to send, If there is no non-video data to send,
the serial link will send blanking the serial link will enter LP mode
packet in HS mode during BLLP during BLLP period.
period.
If there is non-video data to send,
If there is non-video data to send, the non-video data will be sent in HS
non-video data will be sent in HS mode. Afterwards, the serial link will
mode. Afterwards, the serial link enter LP mode for the remaining
will send blanking packet in HS period of BLLP period.
mode for the remaining period of
BLLP period.
0 1 If there is no non-video data to send, Same as non-burst mode.
the serial link will enter LP mode
during BLLP period.
If there is non-video data to send,
non-video data will be sent in HS
mode. Afterwards, the serial link
will enter LP mode for the remaining
period of BLLP period.
1 x The serial link will enter LP mode Same as non-burst mode.
for BLLP mode. If there is non-
video data to send, the data will be
sent in LP mode at the beginning of
BLLP period.

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15.5.2 Interrupt Operation

An interrupt signal int has been provided to interrupt the application processor so that it does not need to poll
the status all the time. This will save the processing time of the application processor. int can be
programmed to active high or active low, when the event has happened.
There are many sources that can be mapped to the interrupt signal. The user can select different source to
perform different task. If more than 1 source is selected, the int signal will be asserted when the event for 1 of
the sources has happened. In this case, the user needs to read the register ISR to determine what event has
happened. The different sources can be enabled/disabled through register ICR. Below is the list of available
interrupt sources and their usage.
RDR
To indicate that return data from one of the MIPI slave is available for read.
BTAR
To indicate whether the SSD2829T has the bus authority or not. It can be used after SSD2829T makes a
BTA. If the MIPI slave has returned the bus authority back to SSD2829T, the interrupt will be set to indicate
so. Please note that, on power up, the bus authority is already on the SSD2829T. Hence, the SSD2829T will
show that it has the bus authority.
ARR
To indicate whether the SSD2829T has received the acknowledge response from the MIPI slave. The
acknowledge response can either report error or not error. This is to be determined by the ATR bit.
The above three interrupts are provided to the user to handle reading data from the MIPI slave or getting
acknowledgement response from the MIPI slave.
PLS
To indicate whether the PLL has been locked or not. If the PLL is not locked, the programming speed at the
external interface must be slow. After changing the PLL setting or changing the reference clock source, the
user also needs to use this interrupt to determine the PLL status.
On power up, only PLS interrupt is enabled. This is to let the user determine the programming speed before
configuring the SSD2829T.
LPTO
To indicate that there is LP RX time out.
HSTO
To indicate that there is HS TX time out.
The above two interrupts are provided to the user for error handling.
PO
To indicate whether the SSD2829T is ready to accept any data from the user. The SSD2829T has several
internal buffers to hold the data written by the user. When the user writes after than the serial link speed,
those buffers will be full. If the user still writes data to SSD2829T, those data will be lost. The length of the
payload of the next packet that the user is going to write is determined by TDC, PST, and DCS fields. The
SSD2829T will use these fields to decide whether the user can write the next packet or not. Hence, after
programming the above mentioned fields, the user needs to check the interrupt status before writing.

CBE, CBA, MLE, MLA

All these interrupts (CBE = command buffer empty, CBA = command buffer available, MLE = MCU line
buffer empty, MLA = MCU line buffer available) are provided to indicate the status of the internal data

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buffers. They are used if the user is familiar with the buffer management of the SSD2829T. Otherwise, it is
recommended to use the PO interrupt.
One important thing to note is the interrupt latency. The output interrupt signal does not change immediately
after an operation. This is due to the internal processing of the SSD2829T. For example, after changing the
interrupt source from one to another, the output int level will remain at the old level for a short period after
the programming is done. Another example is that after programming the TDC field, the interrupt will take a
short period to reflect the correct PO status on int. There is always a delay between the actual event and the
interrupt.
In order to guarantee that the user can get the correct interrupt, it is recommended that the user performs a
read of any SSD2829T local register before taking in the interrupt signal or polling the interrupt status bits.
The read operation will cover the interrupt latency period. Alternatively, the user can wait for certain amount
of time to make sure the interrupt reflects the true status. Below is a diagram for illustration.

Start of read Interrupt reflects

operation true status End of read
operation
Event
happens

int

Time

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15.5.3 Internal Buffer Status

There are 2 types of buffers inside the SSD2829T, which are MCU interface line buffer (ML) and MCU/SPI
command interface buffer (CB).
The ML buffers are used to store the data (DCS command 0x2C and 0x3C) written through MCU interface
when the if_sel is ‘01’. They are also used to store the video data written through RGB interface when the
if_sel is ‘00’. However, since there is no flow control for the RGB interface video packets, the status is only
valid for MCU interface.
For CB buffers, all command packets will be stored into them. They can store multiple packets, up to 4096
bytes in total. Below is a list of possible packets
 Generic Short Write Packet
 Generic Read Packet
 DCS Short Write Packet
 DCS Read Packet
 Generic Long Write Packet
 DCS Long Write Packet
In case of automatic partitioning, the packet length is determined by the PST field. It is not recommended to
make the PST field so small.
When the if_sel is “00”, the user can write the data through SPI interface. All packets will be written into the
CB buffers. Hence, the user needs to check the corresponding interrupts. The usage of the interrupts is listed
below.
CBE
To indicate that the Command buffer is empty.
CBA
To indicate that the Command buffer can hold at least 1 more packet. The user can write 1 such packet into
CB buffer.
MLE
To indicate that MCU Long buffer is empty. Since the ML buffer can hold 2 packets, the user can write up to
2 such packets into ML buffer without needing to look at the interrupt status.
MLA
To indicate that the MCU Long buffer can hold at least 1 more packet. The user can write 1 such packet into
ML buffer.

The interrupts mentioned here can be used as flow control between the application processor and the
SSD2829T. However, it requires the user to know the buffer operation well. The PO interrupt is a
combination of the eight. It makes decision according to the parameters provided by the user for the next
packet to be written. Hence, the user does not need to know which buffer is going to be used and how the
buffer status is.

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15.6 Command Mode Use Cases
MCU interface supports 8-bit, 16-bit and 24-bit data bus. To support different bus width, the following data
pins of each MCU interface are used.
 data[7:0] for 8-bit interface.
 data[15:0] for 16-bit interface.
 data[23:0] for 24-bit interface.

The address range for the SSD2829T local register is from 0xB1 to 0xFF. The user can access the registers in
this range to configure and control the SSD2829T. For Generic packet that starts from 0xB1 to 0xFF, it can be
written through the Packet Drop register. When the user writes data to it, the data will be sent over the serial
link to the MIPI slave. The data packet sent will either be DCS or generic packet.

The following command mode use cases are possible:

MCU Input, Single MIPI Command/Video Output

To select MCU(s) input, if_sel[1:0] needs to “01”.

MCU-0 MIPI DPHY TX 0

SSD2829T

Local registers

MCU Input, Dual MIPI Command Output

This is a broadcast use case. To select MCU(s) input, if_sel[1:0] needs to “01”.

MCU-0
MIPI DPHY TX 0

SSD2829T
MIPI DPHY TX 1

Local registers

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15.6.1 Write Operation

The SSD2829T can issue four kinds of packets for write operation, which are Generic Short Write Packet,
Generic Long Write Packet, DCS Short Write Packet and DCS Long Write Packet. The VC ID of the outgoing
packets can also be programmed through registers.
The SSD2829T needs to know the payload size of the outgoing packets. Hence, the user needs to program the
corresponding control registers prior to sending the MIPI data.
To send a DCS or Generic Write Packet in address 0xB1 to 0xFF, the user needs to write the command/header
and the payload to the Packet Data Drop register. If the size field is no more than 2 for Generic packet and 1
for DCS packet, the SSD2829T will send out DCS or Generic Short Write Packet with the correct type.
Otherwise, DCS or Generic Long Write Packet will be sent out.
For DCS Write Packet, partition is supported for 0x2C or 0x3C DCS command. This is because the DCS
command 0x2C and 0x3C are to write display data into the LCD panel display memory. The payload will be
partitioned into a few packets where the payload of each packet is determined by the Partition register. The
first byte is the DCS command and the following partition bytes are the payload. Only the last packet might
contain less payload, as the total payload might not be integer multiple of partition size. If the incoming DCS
command is 0x2C, the DCS command for the first packet is 0x2C and the DCS command for all other packets
is 0x3C. If the incoming DCS command is 0x3C, the DCS command of all the packets is 0x3C.
For example, if the byte size field is 200 and partition field is 80, 3 packets will be sent. The first two have 80
bytes of payload. The last packet has 40 bytes of payload.
After performing a write operation, the user can optionally make a BTA to let the MIPI slave report its status.
The SSD2829T will automatically make a BTA after each write operation.

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15.6.2 Read Operation

The SSD2829T can issue two kinds of packets for read operation, which are Generic Read Packet, and DCS
Read Packet. The bit DCS controls whether Generic Read Packet or DCS Read Packet will be sent out. The
VC ID of the outgoing packets can also be programmed through registers.
Before the read packet is sent out, the SSD2829T will always send out the Set Maximum Return Size Packet.
This is to limit the Read Response Packet sent by the MIPI slave such that there is no over flow. Two factors
determine the maximum size. One is the limit of the SSD2829T and the other is the limit of the application
processor. The user should choose the smaller one among these two limits to use as the maximum return size.
The parameter in the Set Maximum Return Size Packet is taken from local register. The user could program
the Set Maximum Return Size Register before every read so that the correct value is sent through Set
Maximum Return Size Packet. If the value is already the desired value, the user can choose not to program it.
SSD2829T will always automatically send out Set Maximum Return Size Packet before the Read Packet.
To send a DCS Read or Generic Read Packet, the user just needs to write the DCS (as there is no parameter
for DCS read) or Generic command, or write to Packet Drop Data register when the address is from 0xB1 to
0xFF.
Similar to the write operation, the Total Data Count Register field is used to determine the payload size of the
outgoing packet. For DCS Read Packet, the payload is just the DCS command. There is no parameter
associated. For Generic Read Packet, the SSD2829T will send out the correct packet type according to the
Total Data Count value.
After sending out the read packet, the SSD2829T will automatically perform a BTA to wait for the Read
Response Packet from the MIPI slave. The return data will be stored in a data register. No matter what read
packet is sent out, there is only one packet returning data. Therefore, no matter whether the read is DCS read
or Generic read, no matter what command is used in DCS read, the return data is always stored in the same
data register. The user can read the data out when the read valid status bit is set to 1. After seeing read valid
status bit been set to 1, the user should first check the number of bytes returned by the MIPI slave. By using
this information, the user will know how many data should be read out from data register. After all the return
data are read out, the read valid status bit will be set to 0 by the SSD2829T.
Even the read valid status bit is set to 1, the user can choose not to read the data out from data register. The
user can continue performing another operation. Once the user does so, the read valid status bit will be set to
0 by the SSD2829T.
There might be Acknowledge and Error Report Packet sent by the MIPI slave at the same time.

Under certain circumstance, the MIPI slave might only send back Acknowledge and Error Report Packet
without any data. Thus, the read valid status bit will not be set. Therefore, it is recommended that the user
check the bus turnaround bit first. The bus turnaround bit is to indicate whether the MIPI slave has passed the
bus authority back to the SSD2829T or not. Only when the bus turnaround is 1, there might be return data. If
there is no return data, the user should follow Acknowledgement Operation to handle the acknowledgement.

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15.7 Video to Command Mode conversion

The MIPI TX output of SSD2829T can convert video packets to command mode packets (i.e. 0x2C command
for the first video line, and 0x3C commands for the subsequent video lines).

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15.7.1 Example of switching sequence

Note:
For this feature, it is important to note that once Video-to-Command mode is turned on, the MIPI would be in
HS link when there is active video input. It would remain in HS link until the mode is turned off. Since there
is a HS timeout built-in SSD2829T, user is recommended to switch off Video-to-command mode periodically
(e.g. after a 2-3 frames of conversion)

15.8 State machine operation

The state machine controls the sending and receiving of the data packet over the serial link. It is triggered by
an event from the application processor or the received data. Once a complete packet is written into the
SSD2829T buffer, it will send it out through the serial link. The user can write 1 to bit COP (cancel-operation)
at any time to cancel all the current operations.
When the SSD2829T is in high speed mode, the serial link is mainly used to send display data. If there is no
data to send, it will send null packet to maintain the serial link timing. If the application processor does not
have display data to send in a long period, it can turn the serial link into low power mode by setting the register
bit HS to 0.
When the SSD2829T is in low power mode, the serial link is mainly used to send command and configuration
data. If there are no data to be sent, the SSD2829T will be idle in LP TX stop mode.
The user can also enter sleep mode by writing 1 to SLP bit. Once the SLP bit is set to 1, the SSD2829T will
automatically enter LP mode. If the HS bit is 1, the SSD2829T will clear the HS bit to 0 and switch from HS
to LP mode. Afterwards, the SSD2829T will issue ULPS trigger message to the MIPI slave to enter Ultra Low
Power State. During this state, the clock to SSD2829T can be switched off such that the SSD2829T only
consumes leakage current. This will save the overall system power consumption. When exiting from the ULPS,
the user can write 0 to SLP bit. However, the user should be aware that the time to exit from ULPS is relatively
long. Hence, the user cannot perform any data transmission before the system exits from ULPS.64

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During reception, the state machine will disassemble the incoming data packet and put the received register
content into the internal buffer for reading out. Once all the data are put into the buffers, it will set the register
bit RDY to 1 to indicate that the SSD2829T is ready for read. The total number of received bytes will also be
stored in RDCR.
After the reception is completed, the SSD2829T will perform a bus turn around to enter the transmission mode.
It will always come back to the LP TX stop mode before it enters any other

15.9 PHY controller Operation

PHY-controller controls the operation of the analog transceiver. It controls whether the serial link is in high
speed or low power mode and whether it’s in transmit or receive mode.
In transmit mode, the PHY controller will perform the handshaking procedure when switching between LP
mode and HS mode according to the control from PCU. During HS mode, PHY controller will provide parallel
data and clock to the analog transmitter for transmitting in differential signals serially. During LP mode, the
PHY controller will provide the serial data to the analog transmitter.
In receive mode, the PHY controller will detect the handshaking sequence in LP mode and inform the PCU.
Once entering escape mode, it will collect the serial data from analog receiver and put them in parallel form for
the PCU to process.
Various timing parameter has been defined in MIPI DPHY specification. The timing parameters are a mixture
of absolute time and cycle counts. Hence, for different operation speed, there is different timing requirement.
The user can adjust the value in these registers to have different DPHY timing parameters. This gives maximum
flexibility for different operation speed.

15.10 PLL Configuration

The PLL output frequency is calculated by the equations below,

f IN
f PRE 
MS
f OUT  f PRE * NS
where the f IN is the input reference clock frequency and f OUT is the output clock frequency of the PLL.
The clock frequencies need to satisfy the constraint below.
5𝑀𝐻𝑧 < 𝑓𝐼𝑁 ≤ 40𝑀𝐻𝑧
5𝑀𝐻𝑧 < 𝑓𝑅𝐸𝐹 ≤ 100𝑀𝐻𝑧
62.5𝑀𝐻𝑧 < 𝑓𝑂𝑈𝑇 ≤ 1500𝑀𝐻𝑧
The value of FR, MS, and NS are controlled in the register PLCR.
All the values of FR, MS and NS can only be modified when the PLL is turned off (PEN=0). Hence, the
sequence for modification is to turn off PLL, modify register value, and turn on PLL.

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15.11 Clock Source Example

Pin Connection
XTAL_OUT Open

Solution 2

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15.12 Acknowledgement Operation

The SSD2829T can perform a BTA to give the bus authority to the MIPI slave and let it report its status. The
BTA can be enabled by setting FBW bit to 1 and performing a write operation, or just performing a read
operation. After the MIPI slave passes the bus authority back, the SDD2829T will set bit BTAR to 1.
If there is no error on the slave side, the MIPI slave will return ACK trigger message, if the packet before
BTA is a write packet. The MIPI slave will return Read Response Packet, if the packet before BTA is a read
packet. In this case, after receiving the response from the MIPI slave, SSD2829T will set bit ARR and ATR
bits to 1. ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI
slave has reported no error with ACK trigger message. Consequently, the register ARSR will be cleared to 0.
If there is error on the slave side, the MIPI slave will return Acknowledge and Error Report packet, if the
packet before BTA is a write packet. The MIPI slave will return Read Response Packet (depending on the
error type) and Acknowledge and Error Report Packet, if the packet before BTA is a read packet. In this case,
after receiving the response from the MIPI slave, SSD2829T will set bit ARR bit to 1 and ATR bits to 0.
ARR indicates that response has been received from MIPI slave. ATR indicates that the MIPI slave has sent
Acknowledge and Error Report Packet instead of ACK trigger message. Therefore, the MIPI slave has
reported error. The error reported by the MIPI slave will be stored in register ARSR. The user can read this
register to see what error the MIPI slave has encountered.
For the detailed description of each error bit, please refer to MIPI DSI specification. Below are the flow
charts of handling the MIPI slave acknowledgement. They are just for reference.

N
BTAR == 1?

Y
N Error!
ARR == 1?
No Acknowledgement
Y
N Handle Slave Error
ATR == 1?
Report

Slave has no error.

Proceed

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 N
BTAR == 1?

Y
N
ARR == 1? Error!
No Acknowledgement
Y N
Slave has no error. Y Handle Slave Error
Proceed ATR == 1?
Report

N Y
RDR == 1? Correctable?

Y N
Y
RDR == 1?

Read return data and Error! Error! Proceed

Proceed No return data Extra return data

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15.13 Tearing Effect (TE) Operation

15.13.1Using IO Pins

SSD2829T takes 1 TE_in pin, reshape them and output them to 1 TE_out pin. The programmable parameters
are the pulse width, polarity, and delay.

TE_out 0 TE_in 0
Pulse
Modifier

SSD2829T
Application Display Driver
Processor

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15.13.2Using MIPI Escape Mode

The TE operation is to perform a BTA following the previous BTA without transmitting anything in between.
The bus is handed to the MIPI slave for providing TE information. After getting the TE event from display
driver, the MIPI slave will pass the bus authority back to the SSD2829T by using BTA trigger message.
The TE operation can be enabled by setting bit FBT and FBW to 1 before writing the last command to the
MIPI slave. Afterwards, the application processor can instruct the SSD2829T to send out the last command in
a write packet. Since FBW is 1, the SSD2829T will automatically perform a BTA after the write operation.
The MIPI slave will response and pass the bus authority back. Since FBT is 1, the SSD2829T will perform
another BTA without sending any data. This makes the MIPI slave enter TE mode.
The MIPI slave will send a TE trigger message back when it gets the TE event. After getting the trigger message,
the SSD2829T will set the TE pin to 1 to indicate that TE event has been received. At the same time, bit TER
will be set to 1. The application processor can write 1 to this bit to clear it. As the TE trigger message only
determines when the TE pin will be set to 1, a counter is used to determine when to set the TE pin to 0. The
TE pin will be set to 0, once the counter reaches the value in TEC. The counter uses the reference clock to do
counting.
If the MIPI slave does not send back the TE trigger message but just perform a BTA to pass the bus back, the
SSD2829T will automatically perform another BTA to pass the bus to the MIPI slave again. It will continue
do so until the MIPI slave respond with the TE trigger message, or the FBT bit is set to 0, or the LP RX timer
expires.
If the MIPI slave does not send back the TE trigger message and still holds the bus, the user can set the bit FBC
to 1 to force a bus contention. After bus contention is resolved, the slave will pass the bus back to SSD2829T.
SSD2829T supports dual MIPI TX port. Hence there would be 2 TE outputs accordingly.

15.14 Contention Detection and Timer Operation

Two timers have been defined in SSD2829T to resolve the potential contention issue on the bus. The two timers
are the HS TX timer and LP RX timer. Please see the register description for the detailed usage.
Whenever the SSD2829T sees a contention being detected, it will reset the state machine and enter the default
mode, which is LP TX idle mode. The data line will be kept at LP11.

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15.15 Video BIST
SSD2829T supports the following pattern generation for video BIST.

Parameter Required: 17 bytes

Offset 7 6 5 4 3 2 1 0 Default R/W Description

vb_mode : VBIST test mode selection

vb_cspf: Enable color 1 & 2 swapping
on every frame. (Note: This feature is
vb_cs
0 vb_mode vb_en 0x00 R/W intended to be used together with
pf
vb_mode=0xC. The usage in other
vb_mode is not verified.)
vb_en : VBIST enable

1 vb_repeat_cnt_h 0x00 R/W

Repeat count
2 vb_repeat_cnt_l 0x3C R/W
3 vb_r1 0x00 R/W
4 vb_g1 0x00 R/W RGB value for color 1
5 vb_b1 0x00 R/W
6 vb_r2 0x00 R/W
7 vb_g2 0x00 R/W RGB value for color 2
8 vb_g2 0x00 R/W
9 vb_x_start_h 0x00 R/W
10 vb_x_start_l 0x00 R/W
11 vb_x_end_h 0x00 R/W
12 vb_x_end_l 0x00 R/W
13 vb_y_start_h 0x00 R/W
14 vb_y_start_l 0x00 R/W
15 vb_y_end_h 0x00 R/W
16 vb_y_end_l 0x00 R/W

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MODE 0x0 Parameter Usage
Solid color loop in sequential order of 16 pre-defined color of (0XFF0000, 1 vb_repeat_cnt_h Number of frames pause between
0X00FF00, 0X0000FF, 0X00FFFF, 0XFF00FF, 0XFFFF00, 0XFFFFFF, 2 vb_repeat_cnt_l different colors
0XDFDFDF, 0XBFBFBF, 0X9F9F9F, 0X7F7F7F, 0X5F5F5F, 0X3F3F3F, 3 vb_r1
0X1F1F1F, 0X0F0F0F, 0X000000)
4 vb_g1 Not used
5 vb_b1
6 vb_r2
1 2 3 4 5 6 7 8 7 vb_g2 Not used
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
9 10 11 12 13 14 15 16 11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0x1, 0x2 Parameter Usage

Vertical (mode 0x1) / Horizontal (mode 0x2) repeating 16 colors bars with 1 vb_repeat_cnt_h Color bar width in pixels (MODE 0x1
configurable bar width. Color repeating order are (0XFF0000, 0X00FF00, 2 vb_repeat_cnt_l only : Must be even number)
0X0000FF, 0X00FFFF, 0XFF00FF, 0XFFFF00, 0XFFFFFF, 0XDFDFDF, 3 vb_r1
0XBFBFBF, 0X9F9F9F, 0X7F7F7F, 0X5F5F5F, 0X3F3F3F, 0X1F1F1F,
4 vb_g1 Not used
0X0F0F0F, 0X000000)
5 vb_b1
6 vb_r2
7 vb_g2 Not used
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0x3 Parameter Usage

Checker box with configurable width (>= 2) and color. 1 vb_repeat_cnt_h Box width (>=2, must be even
2 vb_repeat_cnt_l number)
3 vb_r1
4 vb_g1 Color 1 RGB value
5 vb_b1
6 vb_r2
7 vb_g2 Color 2 RGB value
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

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MODE 0x4, 0x5 Parameter Usage
Horizontal (0x4) or vertical (0x5) gradient ramp with programmable line width and 1 vb_repeat_cnt_h For Mode 0x4 - # of pixels for each
color increment value. color step. NOTE: It must be an even
number.
repeat_cnt
256 px 0 – 1 pixel.
2 – 2 pixels.
4 – 4 pixels.
…

2 vb_repeat_cnt_l
For Mode 0x5 - # of lines for each
color step.
0 – 1 line.
1 – 1 line.
2 – 2 lines.
r1,g1,b1 = (0,0,0) r1,g1,b1 = (0,0,0) …
r2,g2,b2 = (1,1,1) r2,g2,b2 = (63,0,0)
3 vb_r1
repeat_cnt = 1 Start color (common for mode 0x4,
4 vb_g1
0x5)
MODE 0x4 MODE 0x5 5 vb_b1
6 vb_r2
Color increment value for each step
7 vb_g2
(common for mode 0x4, 0x5)
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0x6 Parameter Usage

Solid filled rectangle with configurable position, size and foreground / background 1 vb_repeat_cnt_h
color Not used
2 vb_repeat_cnt_l
3 vb_r1
4 vb_g1 Foreground color
5 vb_b1
6 vb_r2
7 vb_g2 Background color
8 vb_g2
9 vb_x_start_h Rectangle’s left boundary (Must be
10 vb_x_start_l even number)
11 vb_x_end_h Rectangle’s right boundary (Must be
12 vb_x_end_l even number)
13 vb_y_start_h
Rectangle’s top boundary
14 vb_y_start_l
15 vb_y_end_h
Rectangle’s bottom boundary
16 vb_y_end_l

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MODE 0x7 Parameter Usage
Single pixel width full size rectangle with two 45° cross touching screen corners. 1 vb_repeat_cnt_h 0x0 : Original Box + Cross
Or single 45° diagonal line drawn from top left / top right corner. Foreground and 0x1 : Line from (0,0) - (W,W)
background color are configurable. 2 vb_repeat_cnt_l 0x2 : Line from (0,W) - (W,0)
3 vb_r1
4 vb_g1 Foreground color RGB value
5 vb_b1
6 vb_r2
7 vb_g2 Background color RGB value
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
0x0 Not used
0x1 0x2 12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0x8, 0x9 Parameter Usage

Vertical (0x8) or Horizontal (0x9) repeating color bars with width of 1 pixel per 1 vb_repeat_cnt_h
color. Color repeating order is [C1, !C2, !C1, C2] Not used
2 vb_repeat_cnt_l
3 vb_r1
4 vb_g1 Color 1 RGB value
5 vb_b1
6 vb_r2
7 vb_g2 Color 2 RGB value
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0xA Parameter Usage

Single pixel width vertical and horizontal line with configurable foreground and 1 vb_repeat_cnt_h
background color No used
2 vb_repeat_cnt_l
x_start 3 vb_r1
4 vb_g1 Foreground color RGB value
5 vb_b1
y_start
6 vb_r2
7 vb_g2 Background color RGB value
8 vb_g2
9 vb_x_start_h
x-coordinate of the vertical line
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
y-coordinate of the horizontal line
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0xB Parameter Usage

This mode is not used. 1
to Not used
16

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MODE 0xC Parameter Usage
Check box with configurable color, vertical offset and vertical repeat count. 1 vb_repeat_cnt_h Vertical repeat in rows.
(Original single pixel checkbox can be obtained by setting offset=0 & repeat=0) 0: 1 line.
2 vb_repeat_cnt_l 1: 2 lines.
…
Vertical Offset = 1
3 vb_r1
4 vb_g1 Color 1 RGB value
Vertical Repeat = 2 5 vb_b1
6 vb_r2
7 vb_g2 Color 2 RGB value
Vertical Repeat = 2 8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
Vertical Repeat = 2 11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h Vertical Offset in rows. (Must be <=
Vertical repeat)
0: “vertical repeat” - 0 lines.
14 vb_y_start_l 1: “vertical repeat” - 1 lines.
…
Vertical repeat: 0 line. (Same as 0)
15 vb_y_end_h
Not used
16 vb_y_end_l

MODE 0xD, 0xE Parameter Usage

Vertical (0xD) or Horizontal (0xE) moving bar with configurable speed, width, step 1 vb_repeat_cnt_h Number of frames pause between
(with direction) and foreground / background color. 2 vb_repeat_cnt_l steps
3 vb_r1
4 vb_g1 Foreground color RGB value
5 vb_b1
6 vb_r2
7 vb_g2 Background color RGB value
8 vb_g2
9 vb_x_start_h Move step (For mode 0xD, must be
10 vb_x_start_l even number, signed)
11 vb_x_end_h Bar width (For mode 0xD, must be
12 vb_x_end_l even number)
13 vb_y_start_h
Move step (For mode 0xE, singed)
14 vb_y_start_l
15 vb_y_end_h
Bar width (For mode 0xE)
16 vb_y_end_l
MODE 0xF Parameter Usage
Full screen solid fill with configurable color. 1 vb_repeat_cnt_h
Not used
2 vb_repeat_cnt_l
3 vb_r1
4 vb_g1 Solid fill color RGB value
5 vb_b1
6 vb_r2
7 vb_g2 Not used
8 vb_g2
9 vb_x_start_h
Not used
10 vb_x_start_l
11 vb_x_end_h
Not used
12 vb_x_end_l
13 vb_y_start_h
Not used
14 vb_y_start_l
15 vb_y_end_h
Not used
16 vb_y_end_l

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15.16 Pixel Peek

SSD2829T supports pixel peek, which is allows user to peek at the pixel value on a programmable pixel location
in the video frame. The pixel location can be configured to be marked out on the screen (through SSD2829T
MIPI TX output) through a cursor (example shown below).

Note:
Pixel peek can only be supported for the following modes:

For single RGB0 input and 2 DSI_TX output(1 to 2)

RICR6.RGB_PACK_SEQ = 1: Left/Right split. pixel[0] to pixel[n/2-1] on DSI_TX0, pixel[n/2] to pixel[n-1] on
DSI_TX1.

 The cursor shown

crosses at the (x,y)
location programmed by
the user.
 The cursor is
programmed to be
visible, with ‘blue’color.
 The actual pixel value of
the location is stored in
the register for user to
read-back

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15.17 Image Flipping (Horizontal)

Each of the dual MIPI TX can be configured to perform horizontal flip independently of each other. For example:

No Flip Left: Flip

Right: Flip

Left: Flip Left: No Flip

Right: No Flip Right: Flip

SSD2829T Rev 1.2 P 157/159 Feb 2018 Solomon Systech

16 PACKAGE INFORMATION

16.1 QFP 128 pins (14mm x 14mm)

Figure 16-1: Package Information – LQFP 128 Pins

Solomon Systech Feb 2018 P 158/159 Rev 1.2 SSD2829T

Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application
or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation consequential or incidental damages.
“Typical” parameters can and do vary in different applications. All operating parameters, including “Typical” must be validated for each customer
application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon
Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application,
Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associate d with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.

The product(s) listed in this datasheet comply with Directive 2011/65/EU of the European Parliament and of the council of 8 June 2011
on the restriction of the use of certain hazardous substances in electrical and electronic equipment and People’s Republic of China
Electronic Industry Standard GB/T 26572-2011 “Requirements for concentration limits for certain hazardous substances in electronic
information products (电子电器产品中限用物質的限用要求)”. Hazardous Substances test report is available upon request.

http://www.solomon-systech.com

SSD2829T Rev 1.2 P 159/159 Feb 2018 Solomon Systech