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Project DLD Lab - Spring 2024

Students are assigned to groups to complete a digital logic design project implementing either a water level detection system, clap activated lock, parking space tracker, logic gate tester, or digital clock on both software and hardware. The projects aim to design circuits using combinational and sequential logic. Students must submit a report and have their work evaluated in lab by the deadline.

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34 views

Project DLD Lab - Spring 2024

Students are assigned to groups to complete a digital logic design project implementing either a water level detection system, clap activated lock, parking space tracker, logic gate tester, or digital clock on both software and hardware. The projects aim to design circuits using combinational and sequential logic. Students must submit a report and have their work evaluated in lab by the deadline.

Uploaded by

pqydjpwvh8
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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National University of Computer and Emerging Sciences, Lahore Campus

Course: Digital Logic Design Lab Course Code: EL-1005


Program: BS(EE) Semester: Spring 2024
Duration: 2 Weeks Total Marks: 50
Section: All Weight 30%
CLO CLO-4

PROJECT STATEMENT:

Implement the project assigned to you on both software (Logic Works) and hardware (on
breadboard) in groups of 2 students.

Project Groups:
A. Water level detection
The multi- level water level monitoring system enables real-time monitoring of water levels across
three distinct levels. It employs sensors to ensure accurate and reliable data collection. Users can
visualize water level data and receive alerts for abnormal conditions, contributing to effic ie nt
resource management. This system facilitates better control and decision-making in applicatio ns
requiring multi- level water level monitoring.

B. Clap Lock
Voice (clap only) activated Moore state machine design with synchronous reset. A state-machine
based digital combination lock circuit which transitions from one state to the next at the clap of
hands, not on the clock. The circuit should be intelligent enough not to trigger at other sounds. The
decision must be taken after the entire code has been entered. The lock must have at least 10,000
possible combinations. (i.e. a total maximum of 8 claps which may or may not have pauses in
between)

C. Parking Counter System


This system will track the number of available parking spaces in real-time, display this informa tio n
on digital screens at entry points and update it dynamically as vehicles enter and exit the parking
lot.

D. Universal Gates Tester


The Universal Gates Tester is a digital logic design project aimed at creating a versatile tool to test
the functionality of universal logic gates. This project involves designing a circuit capable of
testing various types of logic gates, such as AND, OR, NOT, NAND, NOR, and XOR gates. The
tester will provide inputs to the gates and verify their outputs against expected truth table results.

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It will offer a user-friendly interface for inputting gate configurations and analyzing test results,
making it an essential tool for digital logic designers and educators.

E. Digital Clock
A digital clock is an alternative to a traditional analogue clock. This type of clock shows numbers
to display the time in a digital format, such as on a watch, phone, or an alarm clock. This can be
in both 12 and 24-hour formats. You have to design the digital clock using the 7-segment display
that can also perform the following function.

 If 𝑠𝑒𝑡𝑚𝑖𝑛𝑢𝑡𝑒𝑠 is pressed a minute should be updated to set the desire minutes of time.
 If 𝑠𝑒𝑡ℎ𝑜𝑢𝑟𝑠 is pressed a minute should be updated to set the desire hours of time.

All the operations mentioned above should be performed using the combinational and sequentia l
circuits. You can use the BCD to seven segment converters if required. You can either use a 12-
or 24-hours format. If you are using the 12 hours format than a separate led should be used that
will work as an indicator of the AM/PM.

Project Deliverables:

Prepare a detailed report on the completion of project which will summarize all the relative information
related to different tasks of the project.
 Report Submission on Google Classroom.
 Hardware Evaluation in your respective lab sessions. (Bring hardcopy of report during
evaluation)
Deadline: 29th April-3rd May 2023

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