MEMORY DESIGN & TESTING

(ELL749)
A Project Report
on
Design of 128K x 8 High Speed Full CMOS SRAM

Under the guidance of

Dr. Kaushik Saha

Submitted by: -

Manish Kumar Singh 2018CRF2528

Manu Kashyap 2018CRF2531
 ABSTRACT

The semiconductor memory, SRAM uses a bi-stable latch circuit to store the logic data 1 or 0.

It differs from Dynamic RAM (DRAM) which needs periodic refreshment operation for the

storage of logic data. Depending upon the frequency of operation SRAM power consumption

varies, i.e. it consumes very high power at higher frequencies like DRAM. The Cache memory

present in the microprocessor needs high speed memory, hence SRAM can be used for that

purpose in microprocessors. The DRAM is normally used in the Main memory of processors,

where importance is given to the density than its speed. The SRAM is also used in industrial

subsystems, scientific and automotive electronics.

In this Project 128Kx8 High Speed SRAM is designed by using the memory banking

method in UMC 65nm Technology. The pre- layout simulation for the critical path is

performed and obtained the delay of the circuit. All peripherals like pre-charge, Row Decoder,

Word line driver, Sense amplifier, Column Decoder/MUX and write driver are designed and

layouts of all the above peripherals also drawn in an optimized manner such that their layout

occupies the minimum area. The 6T SRAM cell is designed and stability analysis are also

performed for single SRAM cell. The layout of the Single SRAM cell is drawn in a symmetric

manner, such that two adjacent cells can share same contact, which results reduction in the area

of cell layout. The Static Noise Margin, Read Noise Margin and Write Noise Margin of single

cells are found to be 540.91mV, 261.04mV and 571.69mV respectively, for a supply voltage

of 1.2V. The effect of the pull-up ratio and cell ratio on the stability of SRAM cell is observed.

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 Table of Contents

1. INTRODUCTION .................................................................................................................................................. 3
1.1 FEATURES ................................................................................................................................................. 3
1.2 PROCESS TECHNOLOGY............................................................................................................................ 5
1.3 DESIGN FLOW AND TOOLS USED ............................................................................................................. 5
2. SRAM BANK DESIGN ......................................................................................................................................... 6

2.1 ARCHITECTURE ........................................................................................................................................... 6

2.2 ARRAY PARTITIONING ................................................................................................................................... 7
2.3 6T SRAM BIT CELL .......................................................................................................................................... 8

3. DETAILED BLOCK .............................................................................................................................................. 13

3.1 DECODER ................................................................................................................................................... 13
3.1.1 ROW DECODER ................................................................................................................................... 13
3.1.2 COLUMN DECODER ............................................................................................................................. 18
3.2 PRECHARGE CIRCUIT .................................................................................................................................. 19
3.3 WRITE DRIVER ........................................................................................................................................... 21

3.4 SENSE AMPLIFIER (LATCH TYPE) ................................................................................................................. 22

3.5 ADDRESS TRANSITION DETECTION CIRCUIT ............................................................................................... 26

3.6 MONTE CARLO SIMULATION OF NOISE MARGINS ..................................................................................... 29

3.6.1 READ NOISE MARGIN .......................................................................................................................... 29

3.6.2 WRITE NOISE MARGIN ......................................................................................................................... 29

3.6.3 STATIC NOISE MARGIN ........................................................................................................................ 30

4. LAYOUT OF MEMORY ARRAY & TIMING ANALYSIS ................................................................................... 31

4.1 16X16 MEMORY ARRAY ............................................................................................................................. 31

4.2 32X32 MEMORY ARRAY ............................................................................................................................. 32

4.3 TIMING CIRCUIT ANALYSIS ......................................................................................................................... 33

4.4 CRITICAL PATH SIMULATION ...................................................................................................................... 34

4.4.1 READ CRITICAL PATH SIMULATION ..................................................................................................... 34

4.4.2 WRITE CRITICAL PATH SIMULATION ................................................................................................... 35

5. SUMMARY ................................................................................................................................................ 36

4. REFERENCES .............................................................................................................................................. 38

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 1. INTRODUCTION

Static random-access memory (static RAM or SRAM) is a type of

semiconductor random-access memory (RAM) that uses bistable
latching circuitry (flip-flop) to store each bit. SRAM exhibits data
remanence, but it is still volatile in the conventional sense that data is
eventually lost when the memory is not powered. The term static
differentiates SRAM from DRAM (dynamic random-access memory)
which must be periodically refreshed. SRAM is faster and more
expensive than DRAM; it is typically used for CPU cache while
DRAM is used for a computer's main memory.
In this project we are making a 128Kx8 High Speed Asynchronous
SRAM. The fast access time of SRAM makes asynchronous SRAM
appropriate as main memory for small cache-less embedded processors
used in everything from industrial electronics and measurement
systems to hard disks and networking equipment, among many other
applications.
1.1 FEATURES
The Specifications of the SRAM that we are going to design are as
follows-
Pin and function compatible with CY7C1019BV33
High speed—tAA = 10 ns
Low Active Power: ICC = 60 mA @ 10 ns
Data retention at 2.0V
Low CMOS Standby Power: ISB = 3 mA
Easy memory expansion with CE and OE options
Automatic power-down when deselected.
Size of the Data Width is 8 bits.
Total 7 Layers of Metal and a POLY is used.
Area size of 1-bit cell is 1.524 um2 with a core efficiency of
around 65%.
Total chip area is around 3.95 mm2.
The CY7C1019CV33 is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion is
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provided by an active LOW Chip Enable (CE), an active LOW Output
Enable (OE), and three-state drivers.

Writing to the device is accomplished by taking Chip Enable (CE) and

Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the address
pins (A0 through A16). Reading from the device is accomplished by
taking Chip Enable (CE) and Output Enable (OE) LOW while forcing
Write Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the I/O
pins.

Figure1: Logic Block Diagram Figure 2: Pin Configuration

1.3 PROCESS TECHNOLOGY

Process: UMC 65nm Low Leakage. Regular Transistors are used.

Design Library: LVT Tap-Less Standard Cell Library.
All the gates used are custom design and standard cell are used in the
designing of the decoders.

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1.3 Data Flow and Tools Used

Following are the list of tools used during complete process:

• Schematic Editor - Cadence Design Tool Kit - Schematic Editor
Layout Editor - Cadence Design Tool Kit - Virtuoso
• Design Rule Checker – Mentor Graphics Calibre LVS
• Layout vs Schematic tool – Mentor Graphics Calibre LVS
Parasitic Extraction – Mentor Graphics Calibre PEX
• Spectre for the spice Simulations.

Literature Survey and Specs finalization

Architecture and Floor Plannng

Block Level circuit design

,layout and simulation

Top Level Simulation and Result

Analysis on PreLayout

Layout Integration

Post Layout simulation

Figure 3: DATA FLOW

2. SRAM BANK DESIGN

2.1 ARCHITECTURE

The objective of our design is to get high speed SRAM cell. So in

divide word line architecture is followed to obtain high speed The
power down technique for unused circuitry can save power
consumption significantly. This technique eliminates the load of the
bit-lines in unselected row blocks, and reduces the selected word-
line delay appropriately

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 Figure4: Divide wordline Architecture

2.2 ARRAY PARTITIONING

Since this memory is intended for the high-speed applications so, single
array of 128Kx8 will be large also will require gates with large driving
capacity. We explored the possibilities to partition the whole memory
in banks. Now, the question was to decide in how many numbers of
banks we should divide, for this we performed few experiments and
benchmarked them against their results. After comparing we found that
8 memory banks would give us the optimal results as per our
requirements.

Figure 5: Memory Division

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In our memory design we have divided our 128K X 8 bit memory into
8 banks .Each Bank will have 16KB of memory .3 address lines are
used to switch between banks .In each bank we have divided 16KB of
memory in 4 blocks ,so 2 address lines are needed to switch between
these blocks .In each block we have 12 address lines to be used. For
high speed SRAM we are taking column size more than the row size.
In our design we have taken 5 row and 7 column

Figure 7: Bank Architecture

In Figure 7 division into blocks can be seen clearly. Control Logic is in

the middle with 4 blocks at the corners. Each Block is connected to
Sense Amplifier followed by write driver and column decoder. Here,
column decoder is shared between two blocks. Signal from Column
decoder will go to I/O buffer.

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2.3 6T SRAM BIT CELL

Further we explored which bit cell out of 6T, 4T and 11T would be
suitable and found that 6T cell would be most appropriate for low
power applications. Schematic diagram of the 6T bit-cell is shown
below:

Figure 8: 6T Cell

To meet our high speed design, we have taken different W/L ratios
and finally getting the most optimized results on these values.
AREA ESTIMATION: -
• w/l(PUN) = 100/60
• w/l(PDN) = 195/60
• w/l(Access Transistor) = 100/80
• Area of 1-Bit Cell = 1.355(W) * 1.125(H) = 1.524 um2

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To design a memory, we must take care of the sizes also. We must
make the layout of the 1-bit 6T cell in the most optimized way.
Layout of the cell can be seen in the figure below:

Figure 9: Layout of 6T cell

Size of 1-bit cell is coming out to be 1.524 um2 with a core efficiency
of 65%.

STATIC NOISE MARGIN: -

Figure 10 : Static Noise Margin Measurement setup

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Static noise margin is the maximum Temperature Static Noise Margin

-40º C 589.16 mV
noise voltage VN that can come
simultaneously on both the voltage -6.5º C 574.61 mV

sources as shown in the figure above and 27º C 540.91 mV

will not be able to flip the contents of the 56º C 533.67 mV

cell. The cell is in hold mode during this 85º C 522.05 mV

time.
Figure 12 : SNM Analysis

540.91 mV

Figure 11 : Static Noise Margin Plot for CR = 2.6 & PR = 1.11

Static Noise Margin is calculated by giving some voltage to Q and Q’

and then see the response of bit and bitline_bar as we change the value
of the voltage .Response of bit and bitline_bar can be seen in the figure
11 .To calculate the Static noise margin inverse of the curve is plotted
and a maximum possible square is made and the distance between the
diagonal points is calculated which gives the Static noise margin.

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Write Noise Margin
Write noise margin is the maximum noise voltage VN that can come
simultaneously on both the voltage sources as shown in above section
that will prevent write operation to flip the content of the cell. Cell is
put in write mode with word lines enabled and one of the bit lines pulled
to ground.

571.69 mV Temperature Write Noise Margin

-40º C 604.07 mV

-6.5º C 592.88 mV

27º C 571.69 mV

56º C 563.36 mV

85º C 555.6 mV

Figure 13 : Write Margin Plot for CR = 2.6 & PR = 1.11 Figure 14 : SNM Analysis

Read Noise Margin: -

Cell Ratio Read Noise Margin

1.4 160.21 mV

1.8 197.40 mV

2.2 229.41 mV

2.6 261.06 mV

3.0 288.24 mV

Figure 14 : Read noise margin for different CR Ratio

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Based on the VTCs, we define the read Margin to characterize the
SRAM cell’s read stability. Read Margin is directly proportional to the
cell ratio. Read Margin with the increase in value of the pull up ratio .
So carefully we must design SRAM cell invertors before calculating
read noise margin of SRAM cell in read operations.

Process Corner -40º C -6.5º C 27º C 56º C 85º C

FnSp 271.32 mV 251.77 mV 222.52 mV 208.21 mV 190.36 mV

FF 282.25 mV 261.91 mV 232.45 mV 218.46 mV 201.12 mV

TT 310.30 mV 288.98 mV 262.87 mV 245.95 mV 229.35 mV

SS 279.45 mV 258.64 mV 293.85 mV 215.08 mV 197.23 mV

SnFp 289.11 mV 268.96 mV 302.54 mV 226.78 mV 208.14 mV

Figure 15 : Read Noise Margin PVT Analysis for 1-bit Cell

3. DETAILED BLOCK
3.1 DECODERS
3.1.1 ROW DECODER
The Row decoder is Used to Generate Worldline Address for the
Memory Cluster. In our decoder design, hierarchical scheme has been
used for the design of decoders.
The decoder block is divided into two stages.
Pre-decoder
Post decoder
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The Row Decoder is Designed in Such a way that it saves both area,
power and provide a faster access. To ensure the Low Power and Speed,
Hierarchal Decoding is used, and the driving power of Gates are
Increased in a step Fashion (Tapered Buffering), the Other concept is
the use of Negative Body Biasing for ensuring very low leakage
current. For Faster Access, NAND Gates are used over NOR gate
which Provide Faster Access. Here we are dividing row and column in
the ratio of 5:7 which means that row uses 5 address line and column
uses 7 address line .Since we are dividing our 1MB of memory into 8
banks and these blocks are again sub divided into 4 blocks .So we
require total three types of row decoder i.e.,3x8 for bank select ,2x4 for
block select and 5x32 for bit selection.

2x4 decoder: -

Figure 16: Layout of 2x4 decoder

2x4 decoder is designed using NAND gate and layout of this decoder
can be seen in the figure above. We have done its MONTE CARLO
simulation to find the collect value of the delay. In this decoder we are
getting a mean delay of 89.2 ps.

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 Yield = 100 %

( 99.7 % within 6 sigma)

Figure 17: Monte Carlo Simulation

2x4 Block Select Decoder Delay Histogram Plot for 100 Points Mismatch

Yield = 100 %

( 99.7 % within 6 sigma)

Figure 18: Monte Carlo Simulation

2x4 Block Select Decoder Delay Histogram Plot for 100 Points Process + Mismatch

3x8 Decoder: -

Figure 19: Layout of 3x8 decoder

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Layout of the 3x8 is shown in the figure 19 and from MONTE CARLO
simulation mean delay is found to be 181.93 ps.
Yield = 100 %

( 99.7 % within 6 sigma)

Figure 20: Monte Carlo Simulation

3x8 Block Select Decoder Delay Histogram Plot for 100 Points Mismatch

Yield = 100 %

( 99.7 % within 6 sigma)

Figure 21: Monte Carlo Simulation

3x8 Block Select Decoder Delay Histogram Plot for 100 Points Process + Mismatch

5x32 Decoder: -

Figure 22: Layout of 5x32 decoder

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Layout of the 5x32 is shown above and from MONTE CARLO
simulation mean delay is found to be 258 ps.

Yield = 100 %

( 99.7 % within 6 sigma)

Figure 23: Monte Carlo Simulation

5x32 Block Select Decoder Delay Histogram Plot for 100 Points Mismatch

Yield = 100 %

( 99.7 % within 6 sigma)

Figure 24: Monte Carlo Simulation

5x32 Block Select Decoder Delay Histogram Plot for 100 Points Process + Mismatch

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3.1.2 COLUMN DECODER

Figure 22: Layout of 7x128 decoder

Figure 23: Monte Carlo Simulation

7x128 Column Decoder Delay Histogram Plot for 100 Points Mismatch

Figure 24: Monte Carlo Simulation

7x128 Column Decoder Delay Histogram Plot for 100 Points Process + Mismatch

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3.2 PRECHARGE CIRCUIT

Pre-charging is done at the end of every clock cycle. Both static and
dynamic pre-charge schemes are used. Static precharge transistors are
used to avoid the bit-lines floating, when the core is not in use. Also,
they do not affect the normal operation of the core in any way. Size of
Dynamic transistors selected such that it can charge up the Bitline
Capacitance within the allocated precharge budget. Equalization
transistor is also used to ensure the BL and BL_BAR lines equal at the
start of read operation.

Figure 25: PRECHARGE CIRCUIT

Each column of SRAM core has a pre-charge circuit at the top/bottom.

For pre-charge each bank, 128x8 such circuits are required. PMOS

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transistors in the middle are controlled by EN. When EN signal is at
low logic level, the circuit is in pre-charge mode and bit line and bit bar
lines pulled to high logic level. The middle transistor in between the
bitline and bitline bar acts as equalizer. The layout of pre-charge has
been made taking care of the pitch of the SRAM cell. To match the
pitch of the dynamic transistor, the layout width is restricted by the bit
cell width. The bit and bit bar lines are perfectly aligned with bit cell
lines

Figure 26: PRECHARGE CIRCUIT LAYOUT

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3.3 WRITE DRIVER

The tremendous bit line swing can bring about huge power dissipation
in write operation and during read operation, the bit line voltage swing
is normally limited to 180mV, and consequently the write cycle can
consume around 1/8th more power than a read operation. Initially,
before write operation both bit line voltages are charging to supply
voltage and the write operation is performed by enabling WR_EN
signal. Suppose if we want to write logic 0 in to the memory cell, then
the BB line voltage charges to supply voltage VDD and BT line voltage
is discharges to lower potential i.e. ground. The data stored in bit line,
BT and bit line bar, BB is accessed by enabling word line. The sizing
of transistors in write driver is quite large to provide large driving
current.

Figure 27: WRITE DRIVER CIRCUIT

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 Figure 28: CONTROL PART

Figure 29: DRIVER PART

3.4 SENSE AMPLIFIER (Latch-Type)

Sense amplifier is one of the most critical peripheral circuits in the

SRAM and has significant influence on speed and power consumption
of SRAM. Sense amplifier is utilized to access data fast by sensing and
amplifying the small different signal on the bit lines. However, due to
the capacitive loads are large usually, and time of charge and discharge
will be very long, therefore, the design of high-performance sense
amplifier has become the key of high-speed SRAM design. The latch-
type sense amplifier applied to SRAM is a differential voltage mode
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amplifier, this kind of amplifier has a simple structure, fast access speed
and the device size of this structure is easy to design, therefore latch-
type sense amplifier is widely used.

The conventional latch-type sense amplifier is shown in Fig. 30

Figure 30: Conventional Latch type Sense Amplifier

Two CMOS inverters (M1, M3 and M2, M4) are the main bodies of
this amplifier, they connect to each other in a cross-coupling way
including a positive feedback, thus the amplifier turns very fast.
Bitlines BL and BLN are not only inputs but also outputs, so full swing
output is conducted on signal is used to turn on/off the transistor M5 to
control the state of the sense amplifier. Transistors M6-M8 constitute a
typical precharge circuit, in which M6 and M7 are used to precharge
BL and BLN to VDD, M8 as a balanced transistor is used to ensure that
the two bitlines have the same initial voltage which is necessary to
prevent sense amplifier turning unexpectedly when it starts to amplify
signal. In the precharge stage, bitlines are charged to VDD through
pulling down PC signal, at the same time, transistor M8 is turned on to
eliminate the voltage difference between BL and BLN caused by the
change of device’s threshold. At the end of the precharge stage, M6-
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M8 are turned off, and then a word line is turned on to start the read
operation. After that, one of the bitlines will be pulled down by the
selected storage cell, when voltage difference of the two bitlines is big
enough, SE signal turns to VDD from GND, and transistor M5 is turned
on to enable the sense amplifier, under the effect of positive
feedback(M1-M4), bitline voltage is amplified to CMOS levels
quickly.

The sense amplifier shown in Fig. 30 has a characteristic that its input
is the same as output, thus the full swing voltage conversion is
conducted on the bitlines. Since massive storage cells are connected to
the bitline in SRAM, parasitic capacitance of the bitline is also large,
therefore the delay time and power consumption needed for the
amplification process will be severe and this kind of amplifier is rare to
be used in SRAM.

Figure 31: Improved Latch type Sense Amplifier

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Separating from input and output is one of the methods to improve
speed and reduce power consumption of sense amplifier. An improved
latch type sense amplifier is shown in Fig. 31. Compared to the
amplifier shown in Fig. 30, transistors M9 and M10 are added as
switching PMOS to transfer voltage difference from bitlines to sense
amplifier. Enable signal SE turns off M9 and M10, then the large bitline
capacitance is separated from sense amplifier, so that in the interior of
the amplifier, bitline capacitance will have little impact on the speed of
the circuit and power consumption is reduced outstandingly.

Figure 32: Schematic of Sense Amplifier

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 Figure 33: Layout of Sense Amplifier

Figure 34: Monte Carlo Simulation

Sense Amplifier Delay Histogram Plot for 100 Points Process Variation

The Designed Sense Amplifier provides a delay of 48.8 pS for the

BL/BLN Difference voltage of 60mV.
3.5 ADDRESS TRANSITION DETECTION CIRCUIT (ATD):
In an Asynchronous semiconductor memory device, the change of
address is immediately responded. So, it also responds to such wrong
address information and internal circuit selects the wrong address

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information and operates corresponds to that wrong address. The ATD
circuit is used to avoid such problem. When any address signal changes
it generates the pulse. And during that period an internal circuit of the
memory device is held in the non-operating condition in response to
change in address signal. And thus, responding to wrong address
information which is generated due to noise or deviation of timing in
address signal is prevented by using ATD circuit.

Figure 35: Address Transition Detection Circuit

The EXOR Circuit used in the above ATD is designed using DPL
Logic.

Figure 36: EXOR using DPL Logic

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 Figure 37: Output Waveform of ATD Circuit

Figure 38: Monte Carlo Simulation

ATD Pulse Width Histogram Plot for 100 Points Process + Mismatch

The Pulse width of the ATD designed considering all the worst-case
delay of each circuit comes out equals to 823.3 pS. The Monte-Carlo
Simulation shows the Yield equal to 100% within 6 sigma limits.

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3.6: Monte Carlo Simulation of Noise Margins
3.6.1: Read Noise Margin:
RNM= 261.06 mV
SD = 0.9420 mV

Figure 39: Monte Carlo Simulation

6T Cell Read Noise Margin Plot for 100 Points Process+Mismatch

3.6.2: Write Noise Margin:

WNM= 571.69 mV
SD = 1.0051 mV

Figure 40: Monte Carlo Simulation

6T Cell Write Noise Margin Plot for 100 Points Process+Mismatch

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3.6.3: Static Noise Margin:
SNM= 540.91 mV
SD = 0.9603 mV

Figure 41: Monte Carlo Simulation

6T Cell Static Noise Margin Plot for 100 Points Process+Mismatch

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 4: Layout of Memory Array & Timing Analysis
4.1: 16x16 Memory Array

Figure 42: Layout of 16x16 Memory Array

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4.2: 32x32 Memory Array

VDD VSS
Tapping

Figure 42: Layout of 32x32 Memory Array

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4.3: Timing Circuit Analysis

Figure 43: Output Waveform of Timing Circuit

The Output of the ATD is divided into Read, Write & Precharge Signal
with the help of WE Signal. At every transition of Address, ATD circuit
generates a pulse for read and write operation. When the Write Enable
Signal is Low, it generates a Write Pulse and for that duration it turns
off the Precharge Circuit by making Precharge Signal High. When the
Write Enable Signal is High, it generates a Read Pulse and for that
duration it turns off the Precharge Circuit by making Precharge Signal
High. The Read Pulse also goes to the enable of Sense Amplifier.

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4.4: Critical Path Simulation
4.4.1: Read Critical Path Simulation

Figure 44: Read Critical Path Output Waveform

When the address change is detected by the Address Transition

Detection Circuit, it generates a pulse for the read and write Operation
of SRAM. When the WE Signal is High, Read Signal is High, and it
turns ON the Sense Amplifier. As the BL/BLN starts to discharge as
per the data at Q and Q_Bar, the Sense Amplifier after sensing the
appropriate BL/BLN Difference Voltage gives the Output as according.

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4.4.2: Write Critical Path Simulation

Figure 44: Write Critical Path Output Waveform

When the address change is detected by the Address Transition

Detection Circuit, it generates a pulse for the read and write Operation
of SRAM. When the WE Signal is Low, Write Signal is High, and it
turns ON the Write Driver. The BL/BLN starts to charge as per the data
given to write driver. As a result, the Data is written to Q and Q_Bar.
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5. SUMMARY

The 6T SRAM 128K x 8 High Speed Memory Design is performed.

The control circuit is placed and routed through unique methodology
which works seamlessly. Also, it is advantageous to define the design
floorplan through the top-down approach such that the relative
positions of pins are fixed in the block with respect to the top level. As
this flow includes two different design platforms, technology layers
map files are required which should be correctly defined to avoid layer
mismatches. The 16KB bank is assembled by using the decoders,
control and array units, area of this block is 0.321 mm^2. Section 4
provides details of address decode, write and read timing.

In section 2.1 and 2.2, the SRAM 16KB bank abstraction and
characterization are described. This is performed to design the SRAM
1Mb block that uses eight 16KB banks. Also, the SRAM 1Mb RTL
synthesis is discussed that generates gate level netlist and gives an
estimate about the timing details and worst path based on gate delays
and wire load models.
In section 3.4 and 3.5, Design of Critical Components like Sense
Amplifier and Address Transition Detection Circuit is shown with its
simulation results. The MONTE CARLO Simulation shows that both
the circuits are robust against Process and Mismatch Variation. The
Yield is 100% within 6 Sigma limit.

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6. REFERENCES

1. Bharadwaj S Amrutur Mark A. Horowitz "A replica Technique for Wordline and Sense
Control in Low-Power SRAM's" IEEE journal of Solid State Circuits vol. 33 pp. 1208-
1219 1998.

2. Seevinck, E., F. J. List, and J. Lohstroh. "Static-Noise Margin Analysis of MOS SRAM
Cells." IEEE Journal of Solid-State Circuits, vol. 22, no. 5, 1987, pp. 748-754.

3. Chellappa, Srivatsan, and Lawrence T. Clark. "SRAM-Based Unique Chip Identifier

Techniques." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.
24, no. 4, 2016, pp. 1213-1222.

4. Bharadwaj S. Amrutur and Mark A. Horowitz ‖Speed and Power Scaling of

SRAMs‖,IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2,
FEBRUARY 2000

5. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.:‘Digital Integrated Circuits A

Design Perspective(Second Edition)’, 2004.

6. Neil Weste, David Harris. CMOS VLSI Design: A Circuits and Systems
Perspective(4thEdition),2010.

7. CHOW H C, CHANG S H. High performance sense amplifier circuit for low power
SRAM applications[C]. IEEE ISCAS’04, 2004: 741-744.

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