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Electrical Project

The document describes a project to design an automated vending machine using finite state machines. It details the objectives, apparatus, overview, technical working including states and circuit design using D flip-flops. It also includes Verilog code, testbench, waveform output and circuit design to display change using 7-segment displays.

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Utkarsh Dubey
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0% found this document useful (0 votes)
10 views8 pages

Electrical Project

The document describes a project to design an automated vending machine using finite state machines. It details the objectives, apparatus, overview, technical working including states and circuit design using D flip-flops. It also includes Verilog code, testbench, waveform output and circuit design to display change using 7-segment displays.

Uploaded by

Utkarsh Dubey
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Vending Machine Simulation

OM GOEL (2022MT12071)
Subhojit Ghosal (2022MT61976)
Kabir Uberoi (2022MT61202)
Utkarsh Dubey (2022MT61045)
27th April, 2024

Objective
This project aims to use the concept of FSM to design an automated vending
machine with balance and change management and a display facility.

Apparatus
• CPLD board
• CPLD ribbon cable
• IC-7404 (NOT Gate)
• Breadboard

• 7 segment displays
• Power supply
• Connecting wires

1
Overview
The Vending machine is designed as a Finite State Machine (FSM), specifically a
Mealy FSM. It functions by processing a series of inputs according to predefined
rules to determine the sequence of actions. Each state and input governs the
transition based on the denomination entered and handles the return of change
to the customer. Each item is priced at $15 and accepts denominations of $5
and $10. The machine advances through states to ensure seamless operation
and precise dispensing of change.

Technical Working of Circuit


The vending machine operates through a series of defined states, each corre-
sponding to the current balance it holds. Initially set at the 00 state, indicating
a zero balance, the machine remains in this state if no denomination is entered
(out=0). Upon inserting a $5 bill (input 01), the machine transitions to the 01
state (out=0), and with the addition of a $10 bill (input 10), it progresses to
the 10 state (out=0).
In the 01 state, returning to the 00 state occurs if no further denomination is
added (out=0), with the machine dispensing $5 in change. Similarly, inserting
another $5 bill moves the machine to the 10 state (out=0), followed by transi-
tioning back to the 00 state upon inserting a $10 bill, indicating a total of $15
entered.
Transitioning from the 10 state back to the 00 state occurs if no additional
denomination is inputted (out=0). Inserting a $5 bill also returns the machine
to the 00 state with an output of 1 and no change. Conversely, inserting a $10
bill returns the machine to the 00 state with an output of 1 and dispensing $5
in change.

Figure 1: State transition diagram.

Building Circuit using D flip flop


Since we have three states, we’ll need two D flip-flops, designated as Da and
Db . Here, QA and QB denote the current states, z represents the output, and

2
y1 and y2 indicate the change received.

DA = QA QB x2 x1 + QA QB x2 x1

DB = QA QB x2 x1

y2 = QA QB x2 x1

y1 = QA QB x2 x1 + QA QB x2 x1

z = QA QB (x1 ⊕ x2 ) + QA QB x1 x1

Verilog code
module v e n d i n g m a c h i n e (
input clk ,
input rst ,
i n p u t [ 1 : 0 ] in , // 01 = 5 r s , 10 = 10 r s
output r e g out ,
output r e g [ 1 : 0 ] change
);
w i r e q0 ;
w i r e qn0 ;
w i r e q1 ;
w i r e qn1 ;

dff dff inst0 (


. d ( ( ( i n [ 1 ] ) & ( ˜ i n [ 0 ] ) & ( ˜ q0 )&(˜ q1 ) ) | ( ( ˜ i n [ 1 ] ) & ( i n [ 0 ] ) & ( ˜ q0 )&( q1 ) ) ) ,
. clk ( clk ) ,
. rst ( rst ) ,
. q ( q0 ) ,
. qn ( qn0 ) ) ;

dff dff inst1 (


. d ( ( ˜ i n [ 1 ] ) & i n [ 0 ] & ( ˜ q0 )&(˜ q1 ) ) ,
. clk ( clk ) ,
. rst ( rst ) ,
. q ( q1 ) ,
. qn ( qn1 ) ) ;

3
always @∗ b e g i n
out = ( i n [ 1 ] & ( ˜ i n [ 0 ] ) & ( q0 ˆ q1 ) ) | ( ( ˜ i n [ 1 ] ) & i n [ 0 ] & q0&(˜q1 ) ) ;
change [ 1 ] = ( ˜ i n [ 1 ] ) & ( ˜ i n [ 0 ] ) & ( q0 )&(˜ q1 ) ;
change [ 0 ] = ( ˜ i n [ 1 ] ) & ( ˜ i n [ 0 ] ) & ( ˜ q0 )&( q1 ) | ( i n [ 1 ] ) & ( ˜ i n [ 0 ] ) & ( q0 )&(˜ q1 ) ;
end
endmodule

module d f f (
input d ,
input clk ,
input rst ,
output r e g q ,
output qn ) ;

always @ ( p o s e d g e c l k o r p o s e d g e r s t )
i f ( rst )
q <= 0 ;
else
q <= d ;

a s s i g n qn = ˜q ;
endmodule

TESTBENCH
module v e n d i n g m a c h i n e t b ;
// I n p u t s
reg clk ;
reg [ 1 : 0 ] in ;
reg r s t ;

// Outputs
w i r e out ;
w i r e [ 1 : 0 ] change ;
wire [ 1 : 0 ] c s t a t e ;
wire [ 1 : 0 ] n s t a t e ;

// I n s t a n t i a t e t h e u n i t under t e s t
v e n d i n g m a c h i n e uut (
. clk ( clk ) ,
. rst ( rst ) ,
. in ( in ) ,
. out ( out ) ,

4
. change ( change )
);

// Clock g e n e r a t i o n
always #5 c l k = ˜ c l k ; // Toggle t h e c l o c k e v e r y 5 time u n i t s

// Monitor c s t a t e and n s t a t e
always @( p o s e d g e c l k ) b e g i n
$ d i s p l a y ( ” At time %t : c s t a t e = %b , n s t a t e = %b ” , $time , c s t a t e , n s t a t e ) ;
end

// Test c a s e
i n i t i a l begin

// Dump waveform
$ d u m p f i l e ( ” v e n d i n g m a c h i n e . vcd ” ) ;
$dumpvars ( 0 , v e n d i n g m a c h i n e t b ) ;

// I n i t i a l i z e i n p u t s
rst = 1;
clk = 0;
in = 0;

#1

rst = 0;

#1
in = 1;

// Input s e q u e n c e
#5; // Wait f o r 5 time u n i t s
#10; // Wait f o r a d d i t i o n a l 10 time u n i t s

// F i n i s h s i m u l a t i o n
#100 $ f i n i s h ;
end
endmodule

5
EP Wavefrom obtained is

Displaying Change using 7-segment display


• Change received:
– For (y2 y1 ) = 00 → change = 00$
– For (y2 y1 ) = 01 → change = 05$
– For (y2 y1 ) = 10 → change = 10$
• To display change, we used two common anode 7-segment displays namely
display left and display right and the circuit is shown below

6
the Circuit diagram for designing the circuit

7
final designed circuit

Conclusion
The vending machine successfully achieves its objectives of dispensing $15 items
while accepting $5 and $10 currencies at each clock pulse and displaying change
when required. It showcases the integration of different digital electronics com-
ponents, thus creating an efficient and user-friendly automated system.

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