A B C D E

1 1

Compal Confidential
EL4C4 & FL454
2 2

DIS M/B Schematic Document

Intel Whiskey Lake Processor with DDR4
www.teknisi-indonesia.com
MX110 (23x23mm)

2018-10-18
3 3

LA-H082P

R E V：1.0

4 4

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

2018/04/09 2019/04/09 Tiiitllle
Issued Date Deciphered Date Cover Page
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
Custtom
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P 0..2

Date: Monday,,, Octttober 22,,, 2018 Sheet 1 of 53

A B C D E
 A B C D E

NVIDIA N17S-G0
NVIDIA N17S-G2 DDR4 3200MHz CH-A SO-DIMM X1
TDP:18W PCIe x4 , Gen3 8Gb/s
1
CH-B memory down x4 1

VRAM(GDDR5) X2
2GB

USB2.0 x1, 480Mb/s USB Charger USB2.0 x1, 480Mb/s

NGFF (Key M) PCIe x4 , Gen3 8Gb/s
PCIE/SATA SSD SATA , Gen3 6Gb/s TI SN1702001
USB Conn.
2242/2280 conn. with AOU
USB3.1 x1, Gen1 5Gb/s USB3 redriver USB3.1 x1, Gen1 5Gb/s
Parade PS8713B
NGFF (Key M) PCIe x2 , Gen3 8Gb/s
PCIE/SATA SSD SATA , Gen3 6Gb/s USB3.1 x1, Gen1 5Gb/s
USB3.1 x1, Gen1 5Gb/s USB3 redriver
2242/2280 conn. Parade PS8713B USB Conn.
S540-14 Only USB2.0 x1, 480Mb/s

NGFF (Key E) PCIe x1 , Gen1 2.5Gb/s

Intel WHL/CML-U On Sub Board
2
WLAN/BT 2

USB2.0 x1, 480Mb/s

2230 conn. 15W USB2.0 x1, 480Mb/s
FingerPrint
1528pin BGA
eDP Panel eDP x2 , HBR 2.7Gb/s USB2.0 x1, 480Mb/s
FHD LCD Int. Camera
S540-14 Only , use on-cell module
USB2.0 x1, 480Mb/s
I2C Touch Panel
HDMI Conn. DDI x4 , 2.9GT/s

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C340-14 Only , use T-S module On Sub Board
Parade
PS8407A
PCIe x1 , Gen1 2.5Gb/s Card Reader SDIO
SD Card Conn.
Realtek RTS5232S

VBus
3
5V Switch 3

USB2.0 x1, 480Mb/s HDA HP

Combo Jack
Type-C Conn. Audio Codec SPK
USB3.1 Gen1
USB3.1Gen1 Mux/CC USB3.1x1, Gen1 USB3 redriver USB3.1x1, Gen1 Int. Speaker
Parade PS8713B CX11880
CC/Vconn I2C_3VLP DMIC
EC Int. Array Mic *2
RTS5448
I2C (C340)
On Sub Board
USB2.0 (S540) TouchPad

SPI SPI ROM

16MB

LPC

4 4

Int. KBD
KBC
Hall Sensor ENE KB9022

LED Securrriittty Cllassiiifffiiicatttiiion Compalll Secrettt Dattta

Tiiitttlle
Compal Electronics, Inc.
IIIssued Dattte Decipheii rrred Datett
THIIISSHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
Block Diagram
SECRET IIINFORMATIIION... THIIISSHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIIONOF R&D DEPARTMENT EXCEPT AS Siiize Documenttt Numberrr Re v
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIISSHEET NOR THE IIINFORMATIIION IIITCONTAIIINS D 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIORWRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... LA-H082P
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 2 offf53
A B C D E
 1 2 3 4 5

Voltage Rails BOM Structure Table

USB 2.0 Port Table
Item BOM Structure Item BOM Structure
Port External USB Port
DIS Only Components DIS@ X4E X4ES540@
+5VS
UMA Only Components UMA@ X4EC340@ 1 USB2/3 Port (IO - 1)
power HDMI Logo 45@ On Board RAM MD@ 2 USB2/3 Port (IO - 2)
plane +3VS
Touch Screen TS@ no On Board RAM NO_MD@ 3 USB2/3 Port (Type-C)
Memory Down - SDP Package SDP@ On Board RAM X76 Resistors X76RAM@ 4 Touch Screen
+5VALW +1.2V +1.05VS_VCCSTG
+VCC_CORE
Memory Down - DDP Package DDP@ DRAM (Hynix 4GB) H4G_S540@ 5
B+ +3VALW +2.5V
GPU GC6 Components GC6@ DRAM (Micron 4GB) M4G_S540@ 6 Camera
+1.8VALW +VCC_GT
A
Un-Mount GPU GC6 Components NOGC6@ DRAM (Samsung 4GB) S4G_S540@ 7 Fingrt Print
A

+1.05VALW +VCC_SA
Colay SATA/PCIE on M2 SSD_DET@ 8
State
EMI Category EMI@ H4G_VRAM@ 9
+1.05VS_VCCIO
ESD Category ESD@ H4G@ 10 NGFF WLAN+BT
+1.8VS VRAM (Hynix 4GB)
RF Category RF@ H4G_R1@
+0.6VS
Test Point TP@ H4G_R3@ USB 3.0 Port Table PCIE Port Table
KBL@ S4G_VRAM@
Keyboard BackLight
NOKBL@ S4G@ Port Port Lane
VRAM (Samsung 4GB)
S0 S540@ S4G_R1@ 1 USB2/3 Port (IO - 1) 1
O O O O Project select S340@ S4G_R3@ 2 USB2/3 Port (IO - 2) 2
C340@ M4G_VRAM@ 3 USB2/3 Port (Type-C) 3
ONEKEY@ M4G@ 4 4 0
S3 O O O X OneKeyBattery
NON_ONEKEY@
VRAM (Micron 4GB)
M4G_R1@ 5 5 0
CNVi@ M4G_R3@ 6 6 1
S5 S4/AC O O X X Intel CNVi
NONCNVi@ 7 2
DGPU
N17S_G0@ SATA Port Table 8 3
S5 S4/ Battery only O X X X N17S_G2@ 9 3
GPU select Port
N16S@ 10 2
S5 S4/AC & Battery
don't exist X X X X N17S@ 0 11 1
SSD1
Connectors ME@ 1A SSD1 12 0
B
13 0 CardReader B
14 0 NGFF WLAN+BT
1B 15 1
SSD2
2 SSD2 16 0

EC SM Bus1 address EC SM Bus2 address

Device Address Device Address
Smart Battery 0001 011x 16h NCT7718W 1001 100x 98h
thermal sensor 1001 101xb 21h CPU PCB X4E X4E_S540_14 X4E_C340_14
ZZZ PCB@ ZZZ X4ES540@ ZZZ X4EC340@

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UC1 I3_8145U@ UC1 I5_8265U@ UC1 I7_8565U@

PCH SM Bus address GPU SM Bus address

Device Address Device Address X4E_S540_14 X4E_C340_14
QQK9 W 0 2.1GBGA QQTG W 0 1.6GBGA QQK6 W 0 1.8G BGA PCB 2GA LA-H081P REV0 M/B 4 X4EAF638L51 X4EAF638L01
D D R _ JDIM M1 SA0000C6R20 SA0000C6Q20 SA0000C6P20 DA8001H4000
1010 000x A0h Internal thermal sensor 1001 111x 9Eh
Touch Pad

UC1 I3_8145U_R3@ UC1 I5_8265U_R3@ UC1 I7_8565U_R3@ GPU

SMBUS Control Table

UV1 N17S_G0@ UV1 N17S_G2@

SRD1V W 0 2.1G SREJQ W 0 1.6G SREJP W 0 1.8G

SA0000C6R30 SA0000C6Q30 SA0000C6P30
G- THM
SOURCE DGPU BATT CHARGER NECP388 SODIMM TP PCH SENSOR sensor
N17S-G0-A1
SA0000CC900
N17S-G2-A1
SA0000CCB00

C EC_SMB_CK1
NECP388 X V V X X X X X X DRAM S540
C

EC_SMB_DA1 +3VL +3VALW +19 V_VIN

VRAM S540
EC_SMB_CK2
V X X V X X V X V
ZZZ S4G_S540@ ZZZ H4G_S540@ ZZZ M4G_S540@
NECP388 ZZZ VH4G_S540@ ZZZ VM4G_S540@
EC_SMB_DA2 +3VS +3 VS +3 VS + 3VS +3VS
EC_SMB_CK4
EC_SMB_DA4
NECP388
+3VS
X X X X X X X V
+3VS
X K4A8G165W C-BCTD H5AN8G6NCJR-VKC MT40A512M16LY-075:E
X7680638L05 X7680638L04 X7680638L06 H5GC8H24AJR-R2C MT51J256M32HF-80:B
SOC_SMBCLK
X X X X V V X X X
X7680638L01 X7680638L03
PCH
SOC_SMBDATA +3VALW +3 VS +3VS
SOC_SML0CLK
SOC_SML0DATA
PCH X X X X X X X X X DRAM C340 VRAM C340
+3VALW ZZZ3 S4G_C340@ ZZZ2 H4G_C340@ ZZZ1 M4G_C340@ ZZZ VH4G_C340@ ZZZ VM4G_C340@
EC_SMB_CK2
EC_SMB_DA2
PCH V
+3 VS
X X V
+3 VS
X X X X X
+3VS
K4A8G165W C-BCTD H5AN8G6NCJR-VKC MT40A512M16LY-075:E H5GC8H24AJR-R2C MT51J256M32HF-80:B
X7680538L06 X7680538L04 X7680538L05 X7680538L01 X7680538L03

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF

D D

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW LOW OFF OFF OFF OFF

Securiiity Clllassiiifiiicatiiion Compalll Secret Data

Tiitttlle
Compal Electronics, Inc.
Issued Date 2018/04/09 Deciiiphered Date 2019/04/09
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
Notes List
Siiize Documenttt Numberrr Rev
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT
Custttom 0..2
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,,2018
LA-H082P
Sheettt 3 o ff53
1 2 3 4 5
 5 4 3 2 1

-PowerMap_KBL_DDR4_Volume_NON CS]

B+

D D

C C

www.teknisi-indonesia.com

B B

A A

Securiirr tyt Classiil fffiicatiitton Compalll Secrettt Dattta Compal Electronics, Inc.
IIIssued Dattte 2018/04/09//// Deciipherrred Dattte 2019/04/09//// Tiitle

THISISHEET OF ENGINEIIERINGIIDRAWINGIIISTI HE PROPRIEII TARY PROPERTY OF COMPAL ELECTRONICII S,,,INCI..AND CONTAINSII CONFIDII ENTIAI L AND TRADE SECRET INFI
Power MAP
Siize Documenttt Numberrr Re v
LA-H082P
ORMATION...II THISISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVIISIONIOF R&D DEPARTMENT EXCEPT AS AUTHORIZEII D
BY COMPAL ELECTRONICII S,,,INCI..NEITHEIIR THISISHEET NOR THE INFIORMATIONII ITICONTAINSII 0..2
MAY BE USED BY OR DISICLOSED TO ANY THIRDIIPARTY WITHOUTII PRIORIIWRITTEIIN CONSENT OF COMPAL ELECTRONICII S,,,INCI..
Dattte::: Monday,,, Octttoberrr22,,, 2018 Sheettt 4 o fff53
5 4 3 2 1
 5 4 3 2 1

G3->S0 S0->S3/DS3 S0/DS3->S0 S0->S5

+3VL_RTC +3VL_RTC
tPCH01_Min : 9 ms
SOC_RTCRST# SOC_RTCRST#

B+ B+

D D
+3VLP/+5VLP +3VLP/+5VLP

EC_ON EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW/+3VALW_DSW +5VALW/+3VALW/+3VALW_DSW
Pull-up to DSW well if not implemented.
PM_BATLOW# PM_BATLOW#

PCH_PWR_EN (SLP_SUS#) PCH_PWR_EN (SLP_SUS#)

+3V_PRIM +3V_PRIM

+1.8V_PRIM +1.8V_PRIM

EXT_PWR_GATE# If EXT_PWR_GATE# Toffmin is too small, Pwr EXT_PWR_GATE#

gate may choose to completely ignore it

+1.0V_MPHYPLL +1.0V_MPHYPLL

+1.0V_PRIM_CORE +1.0V_PRIM_CORE
tPCH34_Max : 20 ms
+1.0V_PRIM tPCH06_Min : 200 us +1.0V_PRIM

SUSACK# SUSACK#
tPCH02_Min : 10 ms
PCH_DPWROK PCH_DPWROK
tPCH03_Min : 10 ms
EC_RSMRST# EC_RSMRST#
tPLT02_Min : 0 ms Max : 90 ms
C C
AC_PRESENT AC_PRESENT

ON/OFF ON/OFF
tPCH43_Min : 95 ms
PBTN_OUT# PBTN_OUT#
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

PM_SLP_S5# PM_SLP_S5#
tPCH18_Min : 90 us
ESPI_RST# ESPI_RST#

PM_SLP_S4# PM_SLP_S4#

SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC
www.teknisi-indonesia.com SYSON

+1.0V_VCCST/+1.0V_VCCSFR

+1.35V_VDDQ/+1.35V_VCCSFR_OC

PM_SLP_S3# PM_SLP_S3#

SUSP# SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG +1.0VS_VCCSTG
tCPU10 Min : 1 ms

B
+1.0VS_VCCIO +1.0VS_VCCIO B

T <=10msec
+5VS/+3VS/+1.5VS/+1.05VS
+5VS/+3VS/+1.5VS/+1.05VS
T = 10msec
EC_VCCST_PG EC_VCCST_PG

VR_ON VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA +VCC_SA

+VCC_CORE +VCC_CORE

+VCC_GT +VCC_GT

VR_PWRGD VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK PCH_PWROK

H_CPUPWRGD H_CPUPWRGD

SYS_PWROK SYS_PWROK
A A

SUS_STAT# SUS_STAT#

SOC_PLTRST#
SOC_PLTRST#

Securiiittty Clllassifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

2018///04///09 2019///04///09 Tiittle
IssuedII Datett Deciiiphererr d Dattte
THISII SHEET OF ENGINII EERINII G DRAWINIIG ISITHE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,II INCI...AND CONTAINSII CONFIDII ENTIALII AND TRADE SECRET INFII
Power Sequence
ORMATIONII ...THISIISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIII OF R&D DEPARTMENT EXCEPT AS AUTHORIZII Siiize Documenttt Numberrr Re v
ED BY COMPAL ELECTRONICII S,,,INCI...NEITIIHER THISII SHEET NOR THE INIFORMATIONII ITICONTAINIIS 0..2
MAY BE USED BY OR DISCLIIOSED TO ANY THIRDII PARTY WITIIHOUT PRIORII WRITIITEN CONSENT OF COMPAL ELECTRONICII S,,,INC...II
LA-H082PSheettt 5
Dattte::: Monday,,, Octttoberrr 22,,, 2018 o ff53
5 4 3 2 1
 A B C D E

UC1A
AL5 AG4
AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 [28]
AJ5 DDI1_TXP_0 EDP_TXP_0 AG2 EDP_TXP0 [28]
AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 [28] <eDP>
AF6 DDI1_TXP_1 EDP_TXP_1 AJ4 EDP_TXP1 [28]
AF5 DDI1_TXN_2 EDP_TXN_2 AJ3 EDP_TXN2 [28]
AE5 DDI1_TXP_2 EDP_TXP_2 AJ2 EDP_TXP2 [28]
AE6 DDI1_TXN_3 EDP_TXN_3 AJ1 EDP_TXN3 [28]
DDI1_TXP_3 EDP_TXP_3 EDP_TXP3 [28]
AC4
[29] CPU_DP2_N0 AC3 DDI2_TXN_0 AH4
[29] CPU_DP2_P0 AC1 DDI2_TXP_0 EDP_AUX_N AH3 EDP_AUXN [28]
[29] CPU_DP2_N1 AC2 DDI2_TXN_1 EDP_AUX_P EDP_AUXP [28]
1 [29] CPU_DP2_P1 DDI2_TXP_1 AM7 1
<HDMI> [29] CPU_DP2_N2
AE4
DDI2_TXN_2 DISP_UTILS
AE3
[29] CPU_DP2_P2 AE1 DDI2_TXP_2 AC7 +3VS
[29] CPU_DP2_N3 AE2 DDI2_TXN_3 DDI1_AUX_N AC6
[29] CPU_DP2_P3 DDI2_TXP_3 DDI1_AUX_P
AD4
DDI2_AUX_N AD3 EC_SCI# RC1 1 2 10K_0201_5%
DDI2_AUX_P AG7
DDI3_AUX_N AG6
DDI3_AUX_P

CN6
GPP_E13/DDPB_HPD0/DISP_MISC0 CM6
GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 CPU_DP2_HPD [29] From HDMI
GPP_E15/DPPD_HPD2/DISP_MISC2 CP6
GPP_E16/DPPE_HPD3/DISP_MISC3 CM7 EC_SCI# [33]
GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD [28] From eDP
CK11
EDP_BKLTEN CG11 ENBKL [33]
EDP_VDDEN CH11 PCH_ENVDD [28]
EDP_BKLTCTL INVPWM [28]

EDP_COMP AM6
DISP_RCOMP
CC8
CC9 GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_W AKE#
GPP_E19/DPPB_CTRLDATA
CH4
[29] CPU_DP2_CTRL_CLK CH3 GPP_E20/DPPC_CTRLCLK
< Compensation PU For eDP > HDMI DDC (Port 2) [29] CPU_DP2_CTRL_DATA GPP_E21/DPPC_CTRLDATA
CP4
+1.05VS_VCCIO CN4 GPP_E22/DPPD_CTRLCLK
[28] TS_I2C_RST# GPP_E23/DPPD_CTRLDATA
CR26
2
RC2 1 2 EDP_COMP CP26 GPP_H16/DDPF_CTRLCLK 2
24.9_0201_1% GPP_H17/DDPF_CTRLDATA

Trace width=20 mils, Spacing=25mil, Maxlength=600mils

CFLU-43E_BGA1528
@
1 of 20

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+1.05VS_VCCIO
< Test Point for CMC Debug >
1

If routed MS, PECI requires 18 mils spacing to other signals

RC3
1K_0201_5% UC1D
CATERR# AA4 T6 CPU_XDP_TCK0
H_PECI CATERR# PROC_TCK SOC_XDP_TDI TP@ T2408
AR1 U6
[33] H_PECI TP@ T2409
2

1 2 H_PROCHOT#_R Y4 PECI PROC_TDI Y5 SOC_XDP_TDO

+1.05V_VCCST [33] H_PROCHOT# H_THERMTRIP# PROCHOT# PROC_TDO SOC_XDP_TMS TP@ T2410
RC4 499_0402_1% BJ1 T5 TP@ T2411
THRMTRIP# PROC_TMS AB6 SOC_XDP_TRST#
PROC_TRST# TP@ T2412
U1
U2 BPM#_0
1 2 H_THERMTRIP# U3 BPM#_1 W6 PCH_JTAG_TCK1
BPM#_2 PCH_TCK SOC_XDP_TDI TP@ T2413
3 RC8 1K_0201_5% U4 U5 3
BPM#_3 PCH_TDI W5 SOC_XDP_TDO
PCH_TDO SOC_XDP_TMS
P5
PCH_TMS SOC_XDP_TRST#
@ CE9 Y6
GPP_E3/CPU_GP0 PCH_TRST# CPU_XDP_TCK0
2 1 CATERR# CN3 P6
GPP_E7/CPU_GP1 PCH_JTAGX
RC10 49.9_0402_1% CB34
GPP_B3/CPU_GP2
CC35 GPP_B4/CPU_GP3
PROC_PREQ# W2
TP@ T1
W1
PROC_PRDY# TP@ T2
RC11 2 1 49.9_0402_1% CPU_POPIRCOMP BP27 PROC_POPIRCOMP
RC12 2 1 49.9_0402_1% PCH_OPIRCOMP BW 25
PCH_OPIRCOMP
RC14 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP L5 OPCE_RCOMP

RC15 2 @ 1 49.9_0402_1% EOPIO_RCOMP N5

OPC_RCOMP

CFLU-43E_BGA1528
@
4 of 20

4 4

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
WHL-U(1/12)DDI,EDP,MISC,CMC
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev

LA-H082P
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custttom 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Date: Monday,,, Octttober 22,,, 2018 Sheet 6 o f 53
A B C D E
 5 4 3 2 1

Non-Interleaved Memory
D D

UC1C
[18] DDR_A_D[16..31] DDR_A_D16 DDR_B_CLK#0
UC1B J22 AF28 DDR_B_CLK#0 [19]
[18] DDR_A_D[0..15] DDR_A_D0 DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 DDR_B_CLK0
A26 H25 AF29 DDR_B_CLK0 [19]
DDR_A_D1 D26 DDR0_DQ_0/DDR0_DQ_0 V32 DDR_A_CLK#0 DDR_A_D18 G22 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 AE28 DDR_B_CLK#1
DDR_A_CLK0 DDR_A_CLK#0 [18] DDR_B_CLK#1 [19]
DDR_A_D2 D28 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 V31 DDR_A_D19 H22 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 AE29 DDR_B_CLK1
DDR_B_CLK1 [19]
DDR_A_CLK#1 DDR_A_CLK0 [18]
DDR_A_D3 C28 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 T32 DDR_A_D20 F25 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1
DDR_A_D4 DDR_A_CLK1 TP@ T3 DDR_A_D21 DDR1_DQ_4/DDR0_DQ_20 DDR_B_CKE0
B26 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 T31 J25 T28
DDR_A_D5 TP@ T4 DDR_A_D22 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 [19]
C26 DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 G25 T29
DDR_A_D6 DDR_A_CKE0 DDR_A_D23 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE1 [19]
B28 DDR0_DQ_5/DDR0_DQ_5 U36 F22 V28
DDR_A_D7 DDR_A_CKE1 DDR_A_CKE0 [18,20] DDR_A_D24 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC
A28 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 U37 D22 V29
DDR_A_D8 TP@ T6 DDR_A_D25 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
B30 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 U34 C22
DDR_A_D9 D30 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC U35 DDR_A_D26 C24 DDR1_DQ_9/DDR0_DQ_25 AL37 DDR_B_CS#0
DDR_A_D10 DDR_A_D27 DDR1_DQ_10/DDR0_DQ_2D 6DR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 [19]
B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC D24 AL35
DDR_A_D11 DDR_A_CS#0 DDR_A_D28 DDR1_DQ_11/DDR0_DQ_2D 7DR1_CS#_1/DDR1_CS#_1 DDR_B_O DT0 DDR_B_CS#1 [19]
D32 DDR0_DQ_10/DDR0_DQ_10 DDR0_DQ_11/DDR0_DQ_11 AE32 A22 AL36 DDR_B_ODT0 [19]
DDR_A_D12 DDR_A_CS#1 DDR_A_CS#0 [18,20] DDR_A_D29 DDR1_DQ_12/DDR0_DQ_2D8DR1_ODT_0/DDR1_ODT_0 DDR_B_O DT1
A30 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_12/DDR0_DQ_12 AF32 B22 AL34 DDR_B_ODT1 [19]
DDR_A_D13 DDR_A_ODT0 TP@ T5 DDR_A_D30 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 DDR_B_MA0
C30 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_13/DDR0_DQ_13 AE31 A24 AG36 DDR_B_MA0 [19]
DDR_A_D14 DDR_A_ODT0 [18,20] DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0
B32 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_14/DDR0_DQ_14 AF31 DDR_A_ODT1
TP@ T7
DDR_A_D31 B24 AG35 DDR_B_MA1 DDR_B_MA1 [19]
DDR_A_D15 C32 NC/DDR0_ODT_1 [18] DDR_A_D[48..63] DDR_A_D48 G31 DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 DDR_B_MA2 DDR_B_MA2 [19]
AF34
[18] DDR_A_D[32..47] DDR_A_D32 DDR0_DQ_15/DDR0_DQ_15 DDR0_DQ_16/DDR0_DQ_32 DDR_A_MA0 DDR_A_D49 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 DDR_B_MA3 DDR_B_MA3 [19]
H37 AC37 G32 AG37
DDR_A_D33 DDR_A_MA1 DDR_A_MA0 [18,20] DDR_A_D50 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 DDR_B_MA4 DDR_B_MA4 [19]
H34 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_17/DDR0_DQ_33 AC36 H29 AE35
DDR_A_D34 DDR_A_MA2 DDR_A_MA1 [18,20] DDR_A_D51 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA5 [19]
K34 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_18/DDR0_DQ_34 AC34 DDR_A_MA2 [18,20] H28 AF35
DDR_A_D35 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_19/DDR0_DQ_35 DDR_A_MA3 DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 DDR_B_MA6 DDR_B_MA6 [19]
K35 AC35 DDR_A_MA3 [18,20] G28 AE37 DDR_B_MA7 [19]
DDR_A_D36 H36 NC/DDR0_MA_3 AA35 DDR_A_MA4 DDR_A_MA4 [18,20] DDR_A_D53 G29 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 AC29 DDR_B_MA7
DDR_B_MA8 [19]
DDR_A_D37 H35 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 AB35 DDR_A_MA5 DDR_A_MA5 [18,20] DDR_A_D54 H31 DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 AE36 DDR_B_MA8
DDR_B_MA9 [19]
DDR_A_D38 K36 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 AA37 DDR_A_MA6 DDR_A_MA6 [18,20] DDR_A_D55 H32 DDR1_DQ_22/DDR0_DQ_54 DDR1_CAA_3/DDR1_MA_8 AB29 DDR_B_MA9
DDR_B_MA10 [19]
DDR_A_D39 K37 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 AA36 DDR_A_MA7 DDR_A_MA7 [18,20] DDR_A_D56 L31 DDR1_DQ_23/DDR0_DQ_55 DDR1_CAA_1/DDR1_MA_9 AG34 DDR_B_MA10 DDR_B_MA11 [19]
DDR_A_D40 N36 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 AB34 DDR_A_MA8 DDR_A_MA8 [18,20] DDR_A_D57 L32 DDR1_DQ_24/DDR0_DQ_5 D6DR1_CAB_7/DDR1_MA_10 AC28 DDR_B_MA11 DDR_B_MA12 [19]
DDR_A_D41 N34 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_A_MA9 DDR_A_MA9 [18,20] DDR_A_D58 N29 DDR1_DQ_25/DDR0_DQ_5 D7DR1_CAA_7/DDR1_MA_11 DDR_B_MA12 DDR_B_MA13 [19]
W 36 AB28
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 DDR_A_MA10 DDR_A_MA10 [18,20] DDR_A_D59 DDR1_DQ_26/DDR0_DQ_5 D8DR1_CAA_6/DDR1_MA_12 DDR_B_MA13
R37 Y31 DDR_A_MA11 [18,20]
N28 AK35
C DDR_A_D43 R34 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 W 34 DDR_A_MA11 DDR_A_D60 L28 DDR1_DQ_27/DDR0_DQ_5 D9DR1_CAB_0/DDR1_MA_13 C
DDR_A_MA12 [18,20]
DDR_A_D44 N37 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 AA34 DDR_A_MA12 DDR_A_D61 L29 DDR1_DQ_28/DDR0_DQ_60 AJ35 DDR_B_MA14
DDR_A_MA13 [18,20] DDR_B_MA14 [19]
DDR_A_D45 N35 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 AC32 DDR_A_MA13 DDR_A_D62 N31 DDR1_DQ_29/DDR0_DQ_6 D1DR1_CAB_2/DDR1_MA_14 AK34 DDR_B_MA15
DDR1_DQ_30/DDR0_DQ_6 D2DR1_CAB_1/DDR1_MA_15 DDR_B_MA15 [19]
DDR_A_D46 R36 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_A_D63 N32 AJ34 DDR_B_MA16
[19] DDR_B_D[16..31] DDR_B_MA16 [19]
DDR_A_D47 R35 DDR0_DQ_30/DDR0_DQ_46 DDR0_DQ_31/DDR0_DQ_47 AC31 DDR_A_MA14 DDR_B_D16 AJ29 DDR1_DQ_31/DDR0_DQ_6 D3DR1_CAB_3/DDR1_MA_16
[19] DDR_B_D[0..15] DDR_B_D0 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_32/DDR1_DQ_0 DDR_A_MA15 DDR_A_MA14 [18,20] DDR_B_D17 DDR1_DQ_32/DDR1_DQ_16 DDR_B_BA0
AN35 AB32 DDR_A_MA15 [18,20] AJ30 AJ37 DDR_B_BA0 [19]
DDR_B_D1 AN34 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_33/DDR1_DQ_1 Y32 DDR_A_MA16 DDR_B_D18 AM32 DDR1_DQ_33/DDR1_DQ_17DDR1_CAB_4/DDR1_BA_0 AJ36 DDR_B_BA1
DDR_A_MA16 [18,20] DDR_B_BA1 [19]
DDR_B_D2 AR35 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_34/DDR1_DQ_2 DDR_B_D19 AM31 DDR1_DQ_34/DDR1_DQ_18DDR1_CAB_6/DDR1_BA_1 W 29 DDR_B_BG 0
DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 DDR_ B_BG0 [19]
DDR_B_D3 AR34 W 32 DDR_A_BA0 DDR_B_D20 AM30 DDR1_DQ_35/DDR1_DQ_19DDR1_CAA_5/DDR1_BG_0
DDR_B_D4 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 DDR_A_BA0 [18,20] DDR_B_D21 DDR1_DQ_36/DDR1_DQ_20 DDR_B_BG 1
AN37 AB31 DDR_A_BA1 [18,20]
AM29 Y28
DDR_B_D5 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG 0 DDR_B_D22 DDR1_DQ_37/DDR1_DQ_21DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_ B_BG1 [19]
AN36 V34 DDR_ A_BG0 [18,20]
AJ31 W 28
DDR_B_D6 DDR0_DQ_38/DDR1_DQ_6 DDR_B_D23 DDR1_DQ_38/DDR1_DQ_22DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# [19]
AR36 AJ32
DDR_B_D7 AR37 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# V35 DDR_A_ACT# DDR_B_D24 AR31 DDR1_DQ_39/DDR1_DQ_23 H24 DDR_A_DQS#2
DDR_B_D8 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG 1 DDR_A_ACT# [18,20] DDR_B_D25 DDR1_DQ_40/DDR1_DDQ_DR
241_DQSN_0/DDR0_DQSN_2 DDR_A_DQ S2 DDR_A_DQS#2 [18]
AU35 W 35 AR32 G24
DDR_B_D9 DDR0_DQ_41/DDR1_DQ_9 DDR_ A_BG1 [18] DDR_B_D26 DDR1_DQ_41/DDR1_DDQ_D2
R51_DQSP_0/DDR0_DQSP_2 DDR_A_DQS#3 DDR_A_DQS2 [18]
AU34 AV30 C23 DDR_A_DQS#3 [18]
DDR_B_D10 AW 35 DDR0_DQ_42/DDR1_DQ_D1D0R0_DQSN_0/DDR0_DQSN_0 C27 DDR_A_DQS#0 DDR_B_D27 AV29 DDR1_DQ_42/DDR1_DDQ_DR261_DQSN_1/DDR0_DQSN_3 D23 DDR_A_DQ S3
DDR_A_DQS#0 [18] DDR_A_DQS3 [18]
DDR_B_D11 AW 34 DDR0_DQ_43/DDR1_DQ_D1D1R0_DQSP_0/DDR0_DQSP_0 D27 DDR_A_DQ S0 DDR_B_D28 AR30 DDR1_DQ_43/DDR1_DDQ_D2R71_DQSP_1/DDR0_DQSP_3 G30 DDR_A_DQS#6 DDR_A_DQS#6 [18]
DDR_B_D12 DDR0_DQ_44/DDR1_DQ_D1D2R0_DQSN_1/DDR0_DQSN_1 DDR_A_DQS#1 DDR_ A_DQS0 [18] DDR_B_D29 DDR1_DQ_44/DDR1_DDQ_DR
281_DQSN_2/DDR0_DQSN_6 DDR_A_DQ S6
AU37 D31 DDR_A_DQS#1 [18] AR29 H30 DDR_A_DQS6 [18]
DDR_B_D13 AU36 DDR0_DQ_45/DDR1_DQ_D1D3R0_DQSP_1/DDR0_DQSP_1 C31 DDR_ A_DQS1 DDR_B_D30 AV32 DDR1_DQ_45/DDR1_DDQ_D2
R91_DQSP_2/DDR0_DQSP_6 L30 DDR_A_DQS#7 DDR_A_DQS#7 [18]
DDR_ A_DQS1 [18]
DDR_B_D14 AW 36 DDR0_DQ_46/DDR1_DQ_D1D4R0_DQSN_2/DDR0_DQSN_4 J35 DDR_A_DQS#4 DDR_A_DQS#4 [18] DDR_B_D31 AV31 DDR1_DQ_46/DDR1_DDQ_DR
301_DQSN_3/DDR0_DQSN_7 N30 DDR_A_DQ S7 DDR_A_DQS7 [18]
DDR_B_D15 AW 37 DDR0_DQ_47/DDR1_DQ_D1D5R0_DQSP_2/DDR0_DQSP_4 J34 DDR_A_DQ S4 DDR_ A_DQS4 [18]
[19] DDR_B_D[48..63] DDR_B_D48 BA32 DDR1_DQ_47/DDR1_DDQ_D3
R11_DQSP_3/DDR0_DQSP_7 AL31 DDR_B_DQ S#2 DDR_B_DQS#2 [19]
[19] DDR_B_D[32..47] DDR_B_D32 BA35 DDR0_DQ_48/DDR1_DQ_D3D2R0_DQSN_3/DDR0_DQSN_5 P34 DDR_A_DQS#5 DDR_A_DQS#5 [18] DDR_B_D49 BA31 DDR1_DQ_48/DDR1_DDQ_DR
481_DQSN_4/DDR1_DQSN_2 AL30 DDR_B_DQ S2 DDR_ B_DQS2 [19]
DDR_B_D33 DDR0_DQ_49/DDR1_DQ_D3D3R0_DQSP_3/DDR0_DQSP_5 DDR_A_DQ S5 DDR_ A_DQS5 [18] DDR_B_D50 DDR1_DQ_49/DDR1_DDQ_D4
R91_DQSP_4/DDR1_DQSP_2 DDR_B_DQ S#3 DDR_B_DQS#3 [19]
BA34 P35 BD31 AU31 DDR_ B_DQS3 [19]
DDR_B_D34 BC35 DDR0_DQ_50/DDR1_DQ_D3D4R0_DQSN_4/DDR1_DQSN_0 AP35 DDR_B_DQ S#0 DDR_ B_DQS#0 [19] DDR_B_D51 BD32 DDR1_DQ_50/DDR1_DDQ_DR
501_DQSN_5/DDR1_DQSN_3 AU30 DDR_B_DQ S3
DDR0_DQ_51/DDR1_DQ_D3D5R0_DQSP_4/DDR1_DQSP_0 DDR_ B_DQS0 [19] DDR1_DQ_51/DDR1_DDQ_D5
R11_DQSP_5/DDR1_DQSP_3 DDR_B_DQS#6 [19]
DDR_B_D35 BC34 AP34 DDR_B_DQ S0 DDR_B_D52 BA30 BC31 DDR_B_DQ S#6
DDR_ B_DQS6 [19]
DDR_B_D36 BA37 DDR0_DQ_52/DDR1_DQ_D3D6R0_DQSN_5/DDR1_DQSN_1 AV34 DDR_B_DQ S#1 DDR_ B_DQS#1 [19] DDR_B_D53 BA29 DDR1_DQ_52/DDR1_DDQ_DR
521_DQSN_6/DDR1_DQSN_6 BC30 DDR_B_DQ S6
DDR_ B_DQS1 [19] DDR_B_DQS#7 [19]
DDR_B_D37 BA36 DDR0_DQ_53/DDR1_DQ_D3D7R0_DQSP_5/DDR1_DQSP_1 AV35 DDR_B_DQ S1 DDR_B_D54 BD29 DDR1_DQ_53/DDR1_DDQ_D5
R31_DQSP_6/DDR1_DQSP_6 BH31 DDR_B_DQ S#7 DDR_ B_DQS7 [19]
DDR0_DQ_54/DDR1_DQ_D3D8R0_DQSN_6/DDR1_DQSN_4 DDR_ B_DQS#4 [19] DDR1_DQ_54/DDR1_DDQ_DR
541_DQSN_7/DDR1_DQSN_7
DDR_B_D38 BC36 BB35 DDR_B_DQ S#4 DDR_B_D55 BD30 BH30 DDR_B_DQ S7
DDR_ B_DQS4 [19]
DDR_B_D39 BC37 DDR0_DQ_55/DDR1_DQ_D3D9R0_DQSP_6/DDR1_DQSP_4 BB34 DDR_B_DQ S4 DDR_B_D56 BG31 DDR1_DQ_55/DDR1_DDQ_D5
R51_DQSP_7/DDR1_DQSP_7
DDR_ B_DQS#5 [19]
DDR_B_D40 BE35 DDR0_DQ_56/DDR1_DQ_D4D0R0_DQSN_7/DDR1_DQSN_5 BF34 DDR_B_DQ S#5 DDR_ B_DQS5 [19] DDR_B_D57 BG32 DDR1_DQ_56/DDR1_DQ_56 Y29 DDR_B_ALERT#
DDR_B_D41 BE34 DDR0_DQ_57/DDR1_DQ_D4D1R0_DQSP_7/DDR1_DQSP_5 BF35 DDR_B_DQ S5 DDR_B_D58 BK32 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# AE34 DDR_B_PARITY DDR_B_ALERT# [19]
DDR0_DQ_58/DDR1_DQ_42 DDR0_DQ_59/DDR1_DQ_43 DDR_B_PARITY [19]

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DDR_B_D42 BG35 DDR_B_D59 BK31 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR BU31 DDR_DRAMRST#
DDR_B_D43 NC/DDR0_ALERT# DDR_A_ALERT# DDR_B_D60 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# DDR_DRAMRST# [18,19]
BG34 W 37 BG29
DDR_B_D44 BE37 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR W 31 DDR_A_PARITY DDR_A_ALERT# [18] DDR_B_D61 BG30 DDR1_DQ_60/DDR1_DQ_60 BN28 SM_RCO MP0
RC17 1 2 121_0402_1%
DDR_B_D45 DDR0_DQ_61/DDR1_DQ_45 DDR_VREF_CA +0.6V_A_VREFCA DDR_A_PARITY [18,20] DDR_B_D62 DDR1_DQ_61/DDR1_DQ_61 DDR_COMP_0 SM_RCO MP1
BE36 F36 +0.6V_A_VREFCA [18]
BK30 BN27 RC18 1 2 80.6_0402_1%
B
DDR_B_D46 BG36 DDR0_DQ_62/DDR1_DQ_46 DDR0_VREF_DQ_0 D35 DDR_B_D63 BK29 DDR1_DQ_62/DDR1_DQ_62 DDR_COMP_1 BN29 SM_RCO MP2 B
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_1 RC19 1 2 100_0402_1%
DDR_B_D47 BG37 D37 Trace width/Spacing >= 20mils DDR1_DQ_63/DDR1_DQ_63 DDR_COMP_2
DDR1_VREF_DQ +0.6V_B_VREFDQ #543016 PDG1.5 P.168
DDR_VTT_CNTL E36 +0.6V_B_VREFDQ [19] W=12-15 Space= 20/25 L=500mil
C35 DDR_PG _CTRL CFLU-43E_BGA1528
@
3of 20
CFLU-43E_BGA1528
@

2of 20

+1.2V
Recommended By IntelMax
+1.2V +3VS
< For ODT & VTT Power Control >
DDR_VTT_CNTL to DDR

1
Remove RC17 for SDP/DDP BOM selection by PDG
VTT supplied ramped RC2 0
1

470_0402_5%
<35uS 1
CC1 @
(tCPU18) 0.1U_0201_10V6K RC2 1

2
@ 100K_0201_5%
UC11 2 DDR_DRAMRST#
2

1 5
NC VCC
1
DDR_ PG_ CTRL 2
CC2
A 4 100P_0402_50V8J
Y DDR_VTT_PG_CTRL [44]
3 ESD@
GND 2
74AUP1G 07G W _TSSO P5
Close to CPU
SA00005U600

A A

Security Clllassifiiicatiiion Compalll Secret Data Compal Electronics,Inc.

Issued Date 2018///04///09 Deciiiphered Dattte 2019/0// 4/0// 9 Tiitttlle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
WHL-U(2/12)DDR4
Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT AS
LA-H082P
Custttom 0.. 2
AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,, 2018 Sheettt 7 of 53
5 4 3 2 1
 5 4 3 2 1

+3VALW
SML0ALERT# (Internal Pull Down):
RC23 1 2 100K_0201_5% SOC_SPI_0_SI
RC24 1 2 100K_0201_5% SOC_SPI_0_IO2 eSPI or LPC
RC25 1 2 100K_0201_5% SOC_SPI_0_IO3

0 = LPC is selected for EC ==> Default

1 = eSPI is selected for EC

D D
UC1E
SOC_SPI_0_CLK CH37 CK14 SOC_SMBCLK
SOC_SPI_0_SO SPI0_CLK GPP_C0/SMBCLK SOC_SMBDATA
SOC_SMBCLK [19] SMB
CF37 CH15 SOC_SMBDATA [19]
SOC_SPI_0_SI CF36 SPI0_MISO GPP_C1/SMBDATA CJ15 SOC_SMBALERT# (Link to DDR)
SPI ROM SOC_SPI_0_IO2 CF34 SPI0_MOSI GPP_C2/SMBALERT# TP@ T8
SOC_SPI_0_IO3 CG34 SPI0_IO2 CH14 SOC_SML0CLK
SOC_SPI_0_CS#0 CG36 SPI0_IO3 GPP_C3/SML0CLK CF15 SOC_SML0DATA
CG35 SPI0_CS0# GPP_C4/SML0DATA CG15 SOC_SML0ALERT#
SPI0_CS1# GPP_C5/SML0ALERT# TP@ T9
CH34
SPI0_CS2# CN15
GPP_C6/SML1CLK EC_SMB_CK2 [24,33,35] SML1
CM15 EC_SMB_DA2 [24,33,35]
CF20 GPP_C7/SML1DATA CC34 SOC_SML1ALERT# (Link to EC,DGPU,Thermal Sensor)
CG22 GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT#
CF22 GPP_D2/SPI1_MISO_IO1/BK2/SBK2
CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 CA29 LPC_AD0
GPP_D21/SPI1_IO2 GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 [33]
CH23 BY29 LPC_AD1 [33]
CG20 GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 BY27 LPC_AD2
+3VS GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 [33]
BV27 LPC_AD3 [33]
GPP_A4/LAD3/ESPI_IO3 CA28 LPC_FRAME#
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [33]
CA27
RC26 1 2 10K_0201_5% KB_RST# CH7 GPP_A14/SUS_STAT#/ESPI_RESET#
CH8 CL_CLK
CH9 CL_DATA BV32 LPC_CLK0 RC27 1 EMI@ 2 22_0402_5%
CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC [33]
BV30
KB_RST# BV29 GPP_A10/CLKOUT_LPC1 BY30 PM_CLKRUN#
GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN# PM_CLKRUN# [33]
+3VS SERIRQ BV28
[33] SERIRQ GPP_A6/SERIRQ
C C
RC28 1 2 8.2K_0402_5% SERIRQ CFLU-43E_BGA1528
@
5 of 20

+3VS

RPC1, RPC3 and RC30 are close to UC3

SOC_SPI_0_SO RC29 1

SOC_SPI_0_SI RC32 1
SOC_SPI_0_IO3 RC34 1
2 33_0402_5% SOC_SPI_0_SO_R
SOC_SPI_0_CLK RC31 1 EMI@ 2 33_0402_5% SOC_SPI_0_CLK_R
2 33_0402_5% SOC_SPI_0_SI_R
2 33_0402_5% SOC_SPI_0_IO3_R
www.teknisi-indonesia.com EC_SMB_CK2

EC_SMB_DA2
RC30 1

RC33 1
2 1K_0201_5%

2 1K_0201_5%

From SOC SOC_SML1ALERT# 1 @ 2

RC35 150K_0402_5%
SOC_SPI_0_IO2 RC36 1 2 33_0402_5% SOC_SPI_0_IO2_R
SOC_SMBCLK RC37 1 2 1K_0201_5%
SOC_SMBDATA RC38 1 2 1K_0201_5%
SOC_SML0CLK RC39 1 2 1K_0201_5%
SOC_SML0DATA RC40 1 2 1K_0201_5%

B EC_SPI_CLK RC41 1 EMI@ 2 33_0402_5% SOC_SPI_0_CLK_R B

[33] EC_SPI_CLK EC_SPI_MOSI RC42 1 2 33_0402_5% SOC_SPI_0_SI_R +3VS
[33] EC_SPI_MOSI EC_SPI_CS0#
From EC RC43 1 2 33_0402_5% SOC_SPI_0_CS#0
[33] EC_SPI_CS0# EC_SPI_MISO RC44 1 2 33_0402_5% SOC_SPI_0_SO_R
[33] EC_SPI_MISO
PM_CLKRUN# 1 2
RC45 8.2K_0402_5%

< SPI ROM - 16M >

+3VALW
@
UC12 CC3 1 2 0.1U_0201_10V K X5R
SOC_SPI_0_CS#0 1 8
SOC_SPI_0_SO_R CS# VCC SOC_SPI_0_IO3_R
2 7
SOC_SPI_0_IO2_R DO(IO1) IO SOC_SPI_0_CLK_R
3 6
IO2 CLK SOC_SPI_0_SI_R
4 5
GND DI(IO0)
W25Q128JVSIQ SOIC8P
SA00005VV20

A A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(3/12)SPI,SMB,LPC,ESPI
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 8 of 53

5 4 3 2 1
 5 4 3 2 1

< HD AUDIO > HDA_RST#

[32] HDA_RST#_R RC163 1 2 33_0201_5%

D D

RC46 1 EMI@ 2 33_0201_5% HDA_BIT_CLK UC1G

[32] HDA_BIT_CLK_R HDA_SYNC BN34
RC48 1 2 33_0201_5% HDA_SYNC HDA_BIT_CLK BN37 HDA_SYNC/I2S0_SFRM CH36
[32] HDA_SYNC_R HDA_SDOUT HDA_BCLK/I2S0_SCLK GPP_G0/SD_CMD
BN36 CL35
RC47 1 2 33_0201_5% HDA_SDOUT BN35 HDA_SDO/I2S0_TXD GPP_G1/SD3_DATA0 CL36
[32] HDA_SDOUT_R [32] HDA_SDIN0 HDA_SDI0/I2S0_RXD GPP_G2/SD3_DATA1
BL36 CM35
HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD3_DATA2

1
HDA_RST# BL35 CN35
RC49 CK23 HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 CH35
@ GPP_D23/I2S_MCLK GPP_G5/SD_CD# CK36
499_0402_1%
BL37 GPP_G6/SD_CLK CK34
BL34 I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP

2
I2S1_TXD/SNDW2_DATA

CNV_RF_RESET# CJ32
[30] CNV_RF_RESET# CH32 GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CLKREQ_CNV# CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
[30] CLKREQ_CNV# GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH30 BW 36
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7 BY31
< To Enable ME Override > CP24 GPP_A16/SD_1P8_SEL
CN24 GPP_D19/DMIC_CLK0/SNDW4_CLK
GPP_D20/DMIC_DATA0/SNDW4_DATA CK33
CK25 SD_1P8_RCOMP CM34 SOC_SD_RCOMP RC50 1 2 200_0402_1%
CJ25 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
GPP_D18/DMIC_DATA1/SNDW3_DATA
RC51 1 @ 2 0_0402_5% HDA_SDOUT HDA_SPKR CF35
[33] ME_EN [32] HDA_SPKR GPP_B14/SPKR
CFLU-43E_BGA1528
C C
@
7 of 20

GPP_H21 XTAL frequency select.

www.teknisi-indonesia.com
0: 38.4 / 19.2 MHz
CNV_RF_RESET#
75K_0402_5% 1 CNVi@ 2 RC52 1: 24MHz XTAL select.
UC1I
+3VALW
CNV_CRX_DTX_N0 CR30 CN27 SOC_C10_GATE#
[30] CNV_CRX_DTX_N0 CP30 CNV_WR_D0N GPP_H18/CPU_C10_GATE# TP@ T10
CNV_CRX_DTX_P0
[30] CNV_CRX_DTX_P0 CNV_WR_D0P
CM27
CNV_CRX_DTX_N1 CM30 GPP_H19/TIMESYNC_0
Follow Jefferson Peak schematic check list. [30] CNV_CRX_DTX_N1
[30] CNV_CRX_DTX_P1
CNV_CRX_DTX_P1 CN30 CNV_WR_D1N CF25 SOC_GPP_H21 RC53 1 2 4.7K_0201_5%
[30] CNV_CTX_DRX_N0
CNV_CTX_DRX_N0 CN32 CNV_WR_D1P GPP_H21 CN26
[30] CNV_CTX_DRX_P0
CNV_CTX_DRX_P0 CM32 CNV_WT_D0N GPP_H22 CM26
CNV_WT_D0P GPP_H23 CK17
CNV_CTX_DRX_N1 CP33 GPP_F10
[30] CNV_CTX_DRX_N1 CNV_CTX_DRX_P1 CN33 CNV_WT_D1N BV35 SOC_GPD7 RC54 1 2 100K_0201_5%
+3VS [30] CNV_CTX_DRX_P1 CNV_WT_D1P GPD7 CN20
CLK_CNV_CRX_DTX_N CN31 GPP_F3
[30] CLK_CNV_CRX_DTX_N
B CLK_CNV_CRX_DTX_P CP31 CNV_WR_CLKN CG25 B
RC55 1 @ 2 2.2K_0402_5% HDA_SPKR
[30] CLK_CNV_CRX_DTX_P CLK_CNV_CTX_DRX_N CP34 CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25 XTAL INPUT MODE (HVM ONLY) LOW:
[30] CLK_CNV_CTX_DRX_N XTAL INPUT IS SINGLE ENDED HIGH:
CLK_CNV_CTX_DRX_P CN34 CNV_WT_CLKN GPP_H20/IMGCLKOUT_1
[30] CLK_CNV_CTX_DRX_P CNV_WT_CLKP
CNV_WT_RCOMP CP32
CR20
GPP_F12/EMMC_DATA0 CM20 XTAL IS ATTACHED
SPKR (Internal Pull Down): 1 CNVi@ 2
RC56 150_0402_1% CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19
CP20 CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2 CM19
GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3 CN18
TOP Swap Override GPP_F16/EMMC_DATA4
For MX150 GC6_FB_EN1V8 CK19 CR18
[11] GC6_FB_EN1V8 CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18
0 = Disable TOP Swap mode. ==> Default GPP_F2 GPP_F18/EMMC_DATA6 CM18
CR14 GPP_F19/EMMC_DATA7
[34] TP_INT#
CP14 GPP_C8/UART0_RXD
1 = Enable TOP Swap Mode. SOC_GPIO_C10 CN14 GPP_C9/UART0_TXD CM16
CM14 GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CP16
[30] WLBT_OFF# GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
+3VALW +3VS CJ17 GPP_F11/EMMC_CMD CN16
CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
GPP_F9/CNV_MFUART2_TXD CK15 SOC_SD_RCOMP
RC57 1 2 SOC_A4WP_PRESENT CF17 EMMC_RCOMP
GPP_F23/A4WP_PRESENT
RC58 1 @ 2 10K_0201_5% W LBT_OFF# 10K_0201_5%
CFLU-43E_BGA1528
@
RC164 1 @ 2 10K_0201_5% 9 of 20

SOC_GPIO_C10 RC59 1 @ 2 0_0402_5% GPU_EVENT#

A TO DGPU GPU_EVENT# [24] A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(4/12)HDA,EMMC,SDIO,CSI2
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 9 of 53

5 4 3 2 1
 5 4 3 2 1

+3VS
UC1J XCLK_BIASREF RC60 1 2 60.4_0402_1%

AW 2 AU1 CLKIN_XTAL RC65 1 2 10K_0201_5%

CLKREQ_PEG#0 [21] CLK_PEG_N0 AY3 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N AU2
RC66 1 2 10K_0201_5% DGPU [21] CLK_PEG_P0
RC61 1 2 10K_0201_5% CLKREQ_PCIE#1 CLKREQ_PEG#0 CF32 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P
CLKREQ_PCIE#2 [21] CLKREQ_PEG#0 GPP_B5/SRCCLKREQ0#
RC62 1 2 10K_0201_5% BT32 SUSCLK
CLKREQ_PCIE#3 GPD8/SUSCLK SUSCLK [30]
RC63 1 2 10K_0201_5% BC1
CLKREQ_PCIE#4 [31] CLK_PCIE_N1 BC2 CLKOUT_PCIE_N_1 33E_SOC_XTAL24_IN_R
D
RC64 1 2 10K_0201_5% SSD1 [31] CLK_PCIE_P1
CK3
D
CLKREQ_PCIE#1 CE32 CLKOUT_PCIE_P_1 XTAL_IN CK2 33E_SOC_XTAL24_OUT_R
[31] CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# XTAL_OUT
BD3 CJ1 XCLK_BIASREF
CLKREQ_PEG#0 [31] CLK_PCIE_N2 BC3 CLKOUT_PCIE_N_2 CLK_BIASREF CM3 CLKIN_XTAL
RC67 1 @ 2 10K_0201_5% SSD2 [31] CLK_PCIE_P2 CLKIN_XTAL [30]
RC68 1 @ 2 10K_0201_5% CLKREQ_PCIE#4 CLKREQ_PCIE#2 CF30 CLKOUT_PCIE_P_2 CLKIN_XTAL
[31] CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# SOC_RTCX1
BN31
RTCX1 BN32 SOC_RTCX2
Follow CFL-U PDG_Rev_0.7
BH3
WLAN
[30] CLK_PCIE_N3 BH4 CLKOUT_PCIE_N_3 RTCX2 Stuff 60.4 ohm(RC110) PD for CNL-U/ WHL-U and CFL-U
[30] CLK_PCIE_P3 CLKREQ_PCIE#3 CE31 CLKOUT_PCIE_P_3 BR37 SOC_SRTCRST#
[30] CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# SRTCRST# BR34 EC_CLEAR_CMOS#
BA1 RTCRST# 33E_SOC_XTAL24_IN_R 1 2 33E_SOC_XTAL24_IN
[36] CLK_PCIE_N4 BA2 CLKOUT_PCIE_N_4
+3VL_RTC Card Reader [36] CLK_PCIE_P4
RC69 EMI@ 33_0201_5%
CLKREQ_PCIE#4 CE30 CLKOUT_PCIE_P_4
[36] CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4#
BE1 LC1 @EMI@
RC70 1 2 20K_0402_5% SOC_SRTCRST# BE2 CLKOUT_PCIE_N_5 1 2
CF31 CLKOUT_PCIE_P_5 1 2
CC5 1 2 1U_0201_6.3V6M GPP_B10/SRCCLKREQ5#
SE00000UC00 CFLU-43E_BGA1528 4 3
4 3
@
10 of 20 DLM0NSN900HY2D_4P

RC71 1 2 20K_0402_5% 33E_SOC_XTAL24_OUT_R 1 2 33E_SOC_XTAL24_OUT

EC_CLEAR_CMOS# [33]
RC73 EMI@ 33_0201_5%
CC6 1 2 1U_0201_6.3V6M
SE00000UC00 1 2
CLRP1 1 2 SHORT PADS CLR CMOS RC74 200K_0402_1%

RC75 1 2 1M_0402_5% SM_INTRUDER# < PCH PLTRST Buffer > YC1

24MHZ_18PF_XRCGB24M000F2P51R0
SJ10000UJ00

3 1
3 1
C NC NC C

27P_0402_50V8J
CC7

J
27P_0402_50V8
CC8
1 1
4 2

+3VALW
SOC_PLTRST# RC76 1 2 0_0402_5% 2 2
PCI_RST# [21,30,31,33,36]
RC77 1 2 10K_0201_5% SYS_RESET#
RC78 1 2 10K_0201_5% PCH_PW ROK
RC79 1 2 10K_0201_5% EC_RSMRST#

1
SOC_RTCX2
RC80 CC9 ESD@
100K_0201_5% 100P_0402_50V8J

21
www.teknisi-indonesia.com
SOC_RTCX1

2
RC81 1 2 10M_0402_5%

YC2
ESD@ 1 2 SYS_RESET# 1 2
CC10 100P_0402_50V8J
ESD@ 1 2 EC_RSMRST# 32.768KHZ_9PF_X1A000141000200
CC11 100P_0402_50V8J SJ10000PW00
ESD@ 1 2 SYS_PWROK
1 1
CC12 100P_0402_50V8J Common part
CC13 CC14
6.8P_0402_50V8C 6.8P_0402_50V8C
UC1K 2 2

BJ37 PM_SLP_S0#
SOC_PLTRST# GPP_B12/SLP_S0# BU36 PM_SLP_S3# TP@T12
BJ35
PM_SLP_S3# [33]
B SYS_RESET# CN10 GPP_B13/PLTRST# GPD4/SLP_S3# BU27 PM_SLP_S4# B
EC_RSMRST# BR36 SYS_RESET# GPD5/SLP_S4# BT29 PM_SLP_S5# PM_SLP_S4# [33,42,45]
[33] EC_RSMRST# RSMRST# GPD10/SLP_S5# TP@T13
+3VALW T11 TP@ H_CPUPW RGD AR2 BU29
EC_VCCST_PG BJ2 PROCPW RGD SLP_SUS# BT31
RC82 1 2 1K_0201_5% WAKE# VCCST_PW RGOOD SLP_LAN# BT30 SLP_W LAN#
SYS_PW ROK GPD9/SLP_W LAN# BU37 PM_SLP_A# TP@T14
CR10
[33] SYS_PWROK TP@T15
PCH_PW ROK BP31 SYS_PW ROK GPD6/SLP_A# +3VALW
[33] PCH_PWROK EC_RSMRST# BP30 PCH_PW ROK BU28 PBTN_OUT#
DSW _PW ROK GPD3/PW RBTN# PBTN_OUT# [33]
BU35
GPD1/ACPRESENT PM_BATLOW# AC_PRESENT [24,33] PM_BATLOW # 2
BV34 BV36 1
BY32 GPP_A13/SUSW ARN#/SUSPW RDACK GPD0/BATLOW # RC84 8.2K_0402_5%
GPP_A15/SUSACK# AC_PRESENT 1 @ 2
W AKE# BU30 BR35 SM_INTRUDER# RC85 10K_0201_5%
BU32 W AKE# INTRUDER# SOC_VRALERT# 1 @ 2
BU34 GPD2/LAN_W AKE# CC37 RC86 10K_0201_5%
GPD11/LANPHYPC GPP_B11/EXT_PW R_GATE# CC36 SOC_VRALERT# SOC_INPUT3VSEL 2
1 @
GPP_B2/VRALERT# RC87 4.7K_0402_5%
BT27 SOC_INPUT3VSEL
From EC (Open-Drain) +1.05V_VCCST INPUT3VSEL
RC88
1 2
4.7K_0402_5%
1

CFLU-43E_BGA1528
RC89 @
11 of 20
1K_0201_5%
2

RC90 1 2 60.4_0402_1% EC_VCCST_PG

[33] VCCST_PWRGD

1
CC15
100P_0402_50V8J
ESD@
2
A A

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
WHL-U(5/12)CLK,PM,GPIO
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Custttom
LA-H082P 0..2

Date: Monday,,, Octttober 22,,, 2018 Sheet 10 o f 53

5 4 3 2 1
 5 4 3 2 1

GSPI0_MOSI (Internal Pull Down): GPP B19 GPP B20 GPP B21
Capacity Description X76 PART NUMBER R1 _
OBRAM ID _
0 OBRAM ID _
1 OBRAM ID2
No Reboot ( )
WITHOUT ON-BOARD RAM N/A N/A 0 _ 0_ 0_
0 = Disable No Reboot mode. ==> Default SAMSUNG 2666MHz K4A8G165WC-BCTD EL451 X7680638L05 SA0000B6F00
0 0 1
SAMSUNG 2666MHz(K4A8G165WC-BCTD EL4C1
) X7680538L06 SA0000B6F00
1 = Enable No Reboot Mode. (PCH will disable the TCO ( )
Timer system reboot feature). This funct i oni s us eful HYNIX 2666MHz H5AN8G6NCJR-VKC EL451 X7680638L04 SA0000BMN00
0 1 0
when running ITP/XDP. 4GB HYNIX 2666MHz(H5AN8G6NCJR-VKC EL4C1
) X7680538L04 SA0000BMN00
( )
MICRON 2666MHzMT40A512M16LY-075:E EL451 X7680638L06 SA0000ARD20
0 1 1
D D
MICRON 2666MHz(MT40A512M16LY-075:E EL4C1
) X7680538L05 SA0000ARD20
GSPI1_MOSI (Internal Pull Down): N/A ( ) N/A N/A
+3VS
Boot BIOS Strap Bit
RTOUCH5
TS_INT#
0 = SPI Mode ==> Default RC94 NO_MD@ RC95 NO_MD@ RC96 NO_MD@ 1 2
10K_0201_5% 10K_0201_5% 10K_0201_5%
+3VS +3VS +3VS
4.7K_0402_5%
1 = LPC Mode

Function MODEL SETTING1 MODEL SETTING0

1
RC91 RC92 RC93
_
GPP D12 GPP _D11
10K_0201_5% 10K_0201_5% 10K_0201_5%
+3VS
X76RAM@ X76RAM@ X76RAM@ C340 ( _ 0) ( _ 0 )

S340 0 1

2
RC97 1 @ 2 4.7K_0402_5% GSPI0_MOSI OBRAM_ID0 OBRAM_ID1 OBRAM_ID2

S540 1 0

1
RC94 RC95 RC96
RC98 1 @ 2 150K_0402_5% GSPI1_MOSI
10K_0201_5% 10K_0201_5% 10K_0201_5%
X76RAM@ X76RAM@ X76RAM@
+3VS

2
+3VS RC99 1 S540@ 2 10K_0201_5% MODEL_SETTING1
RC100 1 C340@ 2 10K_0201_5%
RC1011 2 10K_0201_5% DGPU_PWR_EN

RC1021 2 10K_0201_5% SOC_GPIO_A7

+3VS
RC1671 2 2.2K_0402_5% I2C_1_SDA
RC1681 2 2.2K_0402_5% I2C_1_SCL RC107 1 S340@ 2 10K_0201_5% MODEL_SETTING0
C C
RC104 1 C340@ 2 10K_0201_5%

RC1031 2 49.9K_0402_1% UART0_RX

RC1081 2 49.9K_0402_1% UART0_TX RC100 S340@ RC104 S540@
RC1091 2 2.2K_0402_5% I2C_0_SDA 10K_0201_5% 10K_0201_5%
RC1051 2 2.2K_0402_5% I2C_0_SCL
RC106 1 @ 2 10K_0201_5% DGPU_HOLD_RST#
RC112 1 DIS@ 2 10K_0201_5%
UC1F
CC27
DGPU PRSNT
Function GPP_ C15
SOC_GPIO_A7 CC32 GPP_B15/GSPI0_CS0# CN22
GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
( 0_ )
SOC_GPIO_B16 CE28 CR22
+1.8VALW SENSOR_EC_INT CE27 GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK CM22 MODEL_SETTING0 DIS
[33] SENSOR_EC_INT GSPI0_MOSI CE29 GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO/GSPI2_MISO CP22 MODEL_SETTING1
UMA Only 1

www.teknisi-indonesia.com
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
OBRAM_ID0 CA31 CK22
GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA CH20
RC113 1 @ 2 20K_0201_5% CNV_RGI_CRX_DTX RC114 1 @ CA32
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PW R_EN# GPP_D6/ISH_I2C0_SCL
OBRAM_ID1
2 20K_0201_5% CNV_BRI_CRX_DTX CC29
OBRAM_ID2 CC30 GPP_B20/GSPI1_CLK CH22
GSPI1_MOSI CA30 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA CJ22 +3VS
GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL
CNV_BRI_CRX_DTX CK20 RC115 1 UMA@ 2 10K_0201_5% DGPU_PRSNT
[30] CNV_BRI_CRX_DTX CNV_RGI_CTX_DRX CG19 GPP_F5/CNV_BRI_RSP CJ27
[30] CNV_RGI_CTX_DRX
CC182 1 2 100P_0402_50V8J I2C_0_SDA CNV_BRI_CTX_DRX CJ20 GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA CJ29 RC116 1 DIS@ 2 10K_0201_5%
[30] CNV_BRI_CTX_DRX CNV_RGI_CRX_DTX CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL
2 100P_0402_50V8J I2C_0_SCL [30] CNV_RGI_CRX_DTX GPP_F7/CNV_RGI_RSP
CC185 1 CM24
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA CN23
CR12 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL CM23
[30] UART0_RX
CP12 GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# CR24
[30] UART0_TX
CC183 1 2 100P_0402_50V8J I2C_1_SDA CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
CM12 GPP_C22/UART2_RTS# CG12 DGPU_PWR_EN
2 100P_0402_50V8J I2C_1_SCL GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD CH12 DGPU_HOLD_RST# DGPU_PWR_EN [26,33]
CC186 1
GPP_C13/UART1_TXD/ISH_UART1_TXD CF12 GPU_ALL_PGOOD DGPU_HOLD_RST# [21]
CM11
[34] I2C_0_SDA GPU_ALL_PGOOD [26]
Touch PAD CN11 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# CG14 DGPU_PRSNT
Function
[34] I2C_0_SCL GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
B MODEL SETTING2 B
CC184 1 2 100P_0402_50V8J I2C_2_SDA GPP_ A20
CK12 BW 35 TS_INT#
[28] I2C_1_SDA TS_INT# [28]
CJ12 GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 BW 34 DGPU_SEL0
Touch Screen [28] I2C_1_SCL GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 CA37 Arrary MIC ( _ )
CC187 1 2 100P_0402_50V8J I2C_2_SCL DGPU_SEL1
GPP_A20/ISH_GP2 CA36
[33] I2C_2_SDA
CF27
CF29 GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 CA35 SingleMIC 10
EC sensor Hub [33] I2C_2_SCL GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 CA34
CH27 GPP_A23/ISH_GP5 BW 37
CH28 GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
GPP_H7/I2C3_SCL
CJ30 +3VS @
CJ31 GPP_H8/I2C4_SDA
PCH EDS : M.2 CNV Mode Select GPP_H9/I2C4_SCL DGPU_SEL1
RC119 1 2 10K_0201_5%
CFLU-43E_BGA1528
GPP_F6/CNV_RGI_DT @
RC120 1 2 10K_0201_5%
6 of 20
0 = Integrated CNVi enable. @

1 = Integrated CNVi disable.

+1.8VALW +3VS

RC160 1 @ 2 10K_0201_5% DGPU_SEL0

RC162 2 1 20K_0201_5% CNV_RGI_CTX_DRX

NONCNVi@ RC159 1 @ 2 10K_0201_5%

CNVi RGI_DT pin gets the pull-down resistor (1K ohm) from the internal CRF module when CNVi is enabled.
There must not be any pull-down resistor connected on the board.

A A

SOC_GPIO_B16 RC121 1 2 0_0201_5% GC6_FB_EN TO DGPU

GC6_FB_EN [24,25]
N16S@
GC6_FB_EN1V8 RC122 1 2 0_0201_5%
[9] GC6_FB_EN1V8
N17S@
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
WHL-U(6/12)GPIO,I2C,GSPI
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Custttom
LA-H082P 0..2

Date: Monday,,, Octttober 22,,, 2018 Sheet 11 o f 53

5 4 3 2 1
 5 4 3 2 1

D UC1H D
CB5
BW9 PCIE1_RXN/USB31_1_RXN CB6 USB3_CRX_DTX_N1 [36]
[21] PCIE_CRX_DTX_N5 PCIE5_RXN/USB31_5_RXN PCIE1_RXP/USB31_1_RXP USB3_CRX_DTX_P1 [36]
[21] PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5
BW8
BW4 PCIE5_RXP/USB31_5_RXP PCIE1_TXN/USB31_1_TXN
CA4
CA3 USB3_CTX_DRX_N1 [36] USB2.0 / 3.0 Port (IO - 1)
CC17 DIS@ 1 2 0.22U_0201_6.3V6M USB3_CTX_DRX_P1 [36]
[21] PCIE_CTX_C_DRX_N5 PCIE_CTX_DRX_P5 PCIE5_TXN/USB31_5_TXN PCIE1_TXP/USB31_1_TXP
CC18 DIS@ 1 2 0.22U_0201_6.3V6M BW 3
[21] PCIE_CTX_C_DRX_P5 PCIE5_TXP/USB31_5_TXP BY8
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN BY9 USB3_CRX_DTX_N2 [36]
BU6 USB3_CRX_DTX_P2 [36]
[21] PCIE_CRX_DTX_N6 BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP CA2
USB3_CTX_DRX_N2 [36] USB2.0 / 3.0 Port (IO - 2)
[21] PCIE_CRX_DTX_P6 CC19 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N6 BU4 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1
USB3_CTX_DRX_P2 [36]
[21] PCIE_CTX_C_DRX_N6 CC20 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P6 BU3 PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
[21] PCIE_CTX_C_DRX_P6 PCIE6_TXP/USB31_6_TXP
dGPU BY7
PCIE3_RXN/USB31_3_RXN BY6 USB3_CRX_DTX_N3 [37]
BT7 USB3_CRX_DTX_P3 [37]
[21] PCIE_CRX_DTX_N7 BT6 PCIE7_RXN PCIE3_RXP/USB31_3_RXP BY4
USB3_CTX_DRX_N3 [37] USB2.0 / 3.0 Port (Type-C)
[21] PCIE_CRX_DTX_P7 CC16 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N7 BU2 PCIE7_RXP PCIE3_TXN/USB31_3_TXN BY3
USB3_CTX_DRX_P3 [37]
[21] PCIE_CTX_C_DRX_N7 CC21 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P7 BU1 PCIE7_TXN PCIE3_TXP/USB31_3_TXP
[21] PCIE_CTX_C_DRX_P7 PCIE7_TXP BW 6
BU9 PCIE4_RXN/USB31_4_RXN BW5
[21] PCIE_CRX_DTX_N8 BU8 PCIE8_RXN PCIE4_RXP/USB31_4_RXP BW2
[21] PCIE_CRX_DTX_P8 CC22 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_N8 BT4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN BW1
[21] PCIE_CTX_C_DRX_N8 CC23 DIS@ 1 2 0.22U_0201_6.3V6M PCIE_CTX_DRX_P8 BT3 PCIE8_TXN PCIE4_TXP/USB31_4_TXP
[21] PCIE_CTX_C_DRX_P8 PCIE8_TXP CE3 USB20_N1
USB2_1N CE4 USB20_N1 [36]
[31] PCIE_CRX_DTX_N9 BP5 USB20_P1
USB20_P1 [36] USB2.0 / 3.0 Port (MB - 1)
[31] PCIE_CRX_DTX_P9 BP6 PCIE9_RXN USB2_1P
[31] PCIE_CTX_DRX_N9 BR2 PCIE9_RXP CE1 USB20_N2
USB20_N2 [36]
[31] PCIE_CTX_DRX_P9 BR1 PCIE9_TXN USB2_2N CE2 USB20_P2 USB2.0 / 3.0 Port (MB - 2)
PCIE9_TXP USB2_2P USB20_P2 [36]
BN6 CG3 USB20_N3
[31] PCIE_CRX_DTX_N10 BN5 PCIE10_RXN USB2_3N CG4 USB20_N3 [38]
[31] PCIE_CRX_DTX_P10 BR4 PCIE10_RXP USB2_3P
USB20_P3
USB20_P3 [38] USB2.0 / 3.0 Port (Type-C)
C C
[31] PCIE_CTX_DRX_N10 BR3 PCIE10_TXN USB20_N4
[31] PCIE_CTX_DRX_P10 CD3
PCIE10_TXP USB20_N4 [28]
SSD1 BN10
USB2_4N
USB2_4P
CD4 USB20_P4
USB20_P4 [28] Touch Screen
[31] PCIE_CRX_DTX_N11 BN8 PCIE11_RXN/SATA0_RXN CG5
[31] PCIE_CRX_DTX_P11 BN4 PCIE11_RXP/SATA0_RXP USB2_5N CG6
[31] PCIE_CTX_DRX_N11 BN3 PCIE11_TXN/SATA0_TXN USB2_5P
[31] PCIE_CTX_DRX_P11 PCIE11_TXP/SATA0_TXP
CC1 USB20_N6
[31] SATA_CRX_DTX_N1 BL6 USB2_6N CC2 USB20_P6 USB20_N6 [28] Camera
[31] SATA_CRX_DTX_P1 BL5 PCIE12_RXN/SATA1A_RXN USB2_6P USB20_P6 [28]
[31] SATA_CTX_DRX_N1 BN2 PCIE12_RXP/SATA1A_RXP CG8 USB20_N7
USB20_N7 [34]
[31] SATA_CTX_DRX_P1 BN1 PCIE12_TXN/SATA1A_TXN USB2_7N CG9 USB20_P7
USB20_P7 [34] Finger Print

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PCIE12_TXP/SATA1A_TXP USB2_7P
BK6 CB8
[36] PCIE_CRX_DTX_N13 BK5 PCIE13_RXN USB2_8N CB9
[36] PCIE_CRX_DTX_P13 BM4 PCIE13_RXP USB2_8P
Card Reader [36] PCIE_CTX_DRX_N13 BM3 PCIE13_TXN CH5
[36] PCIE_CTX_DRX_P13 PCIE13_TXP USB2_9N
CH6
BJ6 USB2_9P
[30] PCIE_CRX_DTX_N14
[30] PCIE_CRX_DTX_P14 BJ5 PCIE14_RXN CC3 USB20_N10
USB20_N10 [30]
NGFF WLAN+BT [30] PCIE_CTX_DRX_N14 BL2 PCIE14_RXP USB2_10N CC4 USB20_P10 NGFF WLAN+BT
USB20_P10 [30]
[30] PCIE_CTX_DRX_P14 BL1 PCIE14_TXN USB2_10P
PCIE14_TXP CC5 USB2_COMP RC123 1 2 113_0402_1%
BG5 USB2_COMP CE8 USB2_ID RC124 1 @ 2 1K_0201_5%
[31] PCIE_CRX_DTX_N15
BG6 PCIE15_RXN/SATA1B_RXN USB2_ID CC6 USB2_SENSE RC125 1 @ 2 1K_0201_5%
[31] PCIE_CRX_DTX_P15
BL4 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE Trace length max: 450mils
[31] PCIE_CTX_DRX_N15
[31] PCIE_CTX_DRX_P15 BL3 PCIE15_TXN/SATA1B_TXN CK6 USB_OC0#
USB_OC0# [36]
PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK CK5
SSD2 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8
USB_OC1#
USB_OC1# [36]
BE5 USB_OC2#
[31] SATA_CRX_DTX_N2
B
[31] SATA_CRX_DTX_P2 BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9 USB_OC3# B

[31] SATA_CTX_DRX_N2 BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#

[31] SATA_CTX_DRX_P2 BJ3 PCIE16_TXN/SATA2_TXN CP8 W L_OFF#
PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0 CR8 WL_OFF# [30]
DEVSLP1 DEVSLP1 [31]
RC1261 2 100_0402_1% PCIE_RCOMPN CE6 GPP_E5/DEVSLP1 CM8 DEVSLP2 DEVSLP2 [31]
PCIE_RCOMPP CE5 PCIE_RCOMP_N GPP_E6/DEVSLP2
PCIE_RCOMP_P CN8 +3VALW
CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10 NGFF_SSD_PEDET
NGFF_SSD_PEDET [31]
CP28 GPP_H12/M2_SKT2/CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 CP10 NGFF_SSD2_PEDET
NGFF_SSD2_PEDET [31]
CN28 GPP_H13/M2_SKT2/CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 USB_OC0# RC127 2 1 10K_0201_5%
CM28 GPP_H14/M2_SKT2/CFG_2 CN7 USB_OC1# RC128 2 1 10K_0201_5%
GPP_H15/M2_SKT2/CFG_3 GPP_E8/SATALED#/SPI1_CS1# USB_OC2# RC129 2 1 10K_0201_5%
AR3 USB_OC3# RC130 2 1 10K_0201_5%
UFS_RESET#
CFLU-43E_BGA1528
@
8 of 20
+3VS +3VALW
When PCIE16/SATA2 is used as SATA Port 1 (ODD), then
PCIE15/SATA1B (M.2 SSD) cannot be used as SATA Port 1. NGFF_SSD_PEDET RC166 1 2 10K_0201_5%

NGFF_SSD2_PEDET RC131 1 2 10K_0201_5%

W L_OFF# RC132 1 @ 2 10K_0201_5%

A
RC165 1 @ 2 10K_0201_5% A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(7/12)PCIE,USB,SATA
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 12 of 53

5 4 3 2 1
 5 4 3 2 1

+1.2V

+1.05VALW TO +1.05V_VCCST
+VL +1.05VS_VCCIO
UC1N
AK24 3.679A
+1.05V_VCCST 3.3A AD36 VCCIO1 AK26
I(Max) : 0.16 A(+1.05V_VCCST) AH32 VDDQ1 VCCIO2 AL24
VDDQ2 VCCIO3
RON(Max) : 25 mohm

M
1U_0201_6.3V6
1 AH36 AL25
RC133 1 2 0_0402_5% AM36 VDDQ3 VCCIO4 AL26
V drop : 0.004 V VDDQ4 VCCIO5

CC24
AN32 AL27
VDDQ5 VCCIO6

K
0.1U_0201_10V6
CC25 @
1 AW32 AM25
2 UC14 AY36 VDDQ6 VCCIO7 AM27
1 14 BE32 VDDQ7 VCCIO8 BH24
+1.05VALW VDDQ8 VCCIO9
2 VIN1 VOUT1 13 BH36 BH25
VIN1 VOUT1 2 R32 VDDQ9 VCCIO10 BH26
D D
RC134 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 Y36 VDDQ10 VCCIO11 BH27
[33,44] SYSON ON1 CT1 +1.05V_VCCST VDDQ11 VCCIO12 BJ24
CC26
4 VCCIO13 BJ26
11 8200P_0402_25V7K
VBIAS GND VCCIO14 BP16
EN_1.8VS +1.2V +1.05VS_VCCIO VCCIO15 +VCCSA
RC135 1 @ 2 0_0402_5% 5 10 1 2 BC28 BP18
[33,39,44] SUSP# ON2 CT2 RSVD1 VCCIO16
CC27 Follow 543977_SKL_PDDG_Rev0_91
6 9 1000P_0402_50V7K BP11 BG8 6A
7 VIN2 VOUT2 8 CC24 10PF ->22us(Spec:<= 65us) VCCST1 VCCSA2
+1.8VALW BP2 BG10
VIN2 VOUT2 VCCST2 VCCSA1 BH9
+1.8VS VCCSA3
15 BJ8
GPAD VCCSA5
0.02A BG1
VCCSTG1 VCCSA6
BJ9

+1.8VALW TO +1.8VS
AOZ1331 DFN 14P BG2 BJ10
VCCSTG2 VCCSA4
SA0000BKC00 RC136 1 @ 2 0_0603_5% BK8
VCCSA9
I(Max) : 0.2 A(+1.8VS) 0.12A BL27
VCCPLL_OC1 VCCSA7
BK25
RON(Max) : 25 mohm

K
0.1U_0201_10V6
CC28 @
1 BM26 BK27
VCCPLL_OC2 VCCSA8
V drop : 0.005 V BL8
VCCSA13
0.19A BR11
VCCPLL1 VCCSA14
BL9
BT11 BL10
2 VCCPLL2 VCCSA10
BL24
VCCSA11
+1.05VALW TO +1.05VS_VCCIO
BL26
VCCSA12
VCCSA15 BM24
+VL +1.05VALW BN25
VCCSA16
I(Max) : 3.675 A(+1.05VS_VCCIO) VCCIO_SENSE
BP28
RON(Max) : 6.2 mohm BP29 Trace Length Match < 25 mils
VSSIO_SENSE
0.1U_0201_10V KX5R

M
1U_0201_6.3V6

1 1 V drop : 0.019 V +1.05VS_VCCIO VSSSA_SENSE

CC29

BE7
VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE [47]
CC30

UC15 BG7
1 1uF X1 VCCSA_SENSE VCCSA_SENSE [47] C
C @
2 2 2 VIN1 0.1uF X1 CFLU-43E_BGA1528
VIN2
+1.05V_VCCST @
7 6 +1.05VS_VCCIO_STG RC137 1 @ 2 0_0805_5% PSC Side 14 of 20
VIN thermal VOUT +1.2V +1.05VS_VCCIO
1
3 CC31 @ PSC Side PSC Side
VBIAS

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6
0.1U_0201_10V K X5R
SUSP# 4 5 1 1 1 1 1
ON GND 2

M
1U_0201_6.3V6

M
1U_0201_6.3V6
1 1

@ CC32

@ CC34
CC33

CC35

CC36

CC37

CC38
EM5201V_DFN8_3X3
SA00008R600 2 2 2 2 2

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2 2

Close to BP11 & BP2 Close to BR11 & BT11 Close to BM26 Close to BG1 & BG2

+1.2V change package of 1U from 0201 to 0402

PSC Side BSC Side

+1.05VS_VCCIO
change package of 1U from 0201 to 0402
BSC Side PSC Side

M
4.7U_0402_6.3V6

M
10U_0402_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6
M
10U_0402_6.3V6

M
10U_0402_6.3V6
B
1 1 1 1 1 1 1 1 1 B

@ CC53

@ CC55
CC49

CC50

CC51

CC52

CC54

CC56

CC57
2 2 2 2 2 2 2 2 2
M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
1U_0201_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

M
10U_0402_6.3V6

1 1 1 1 1 1 1 1 1 1 @ @
@ CC45

@ CC46
CC39

CC40

CC41

CC42

CC43

CC44

CC47

CC48

2 2 2 2 2 2 2 2 2 2
Underneath CPU Close to CPU

Close to CPU Underneath CPU

A A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(8/12)Power
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 13 of 53

5 4 3 2 1
 5 4 3 2 1

+1.05VALW +1.05VALW

1
@ 1
CC61
CC62
2 1U_0201_6.3V6M
2 1U_0201_6.3V6M

Close to BV18 Close to BP20

Imax : 4.982A
D
+1.05VALW D
+1.05VALW +1.05VALW
+1.05VALW +3VALW
UC1P RTC Bat t ery
BP20
BW 16 VCCPRIM_1P05_1 CB16
1 1 1 VCCPRIM_1P05_9 VCCPRIM_3P3_3
BW 18 +3VL_RTC +RTCBATT
BW 19 VCCPRIM_1P05_10 +3VL_RTC
CC63 CC64 CC65
VCCPRIM_1P05_11
4.7U_0402_6.3V6M 10U_0402_6.3V6M BY16 W=20mils
2 1U_0201_6.3V6M 2 2 +1.8VALW CA14 VCCPRIM_1P05_12 BR23
VCCPRIM_1P05_14 VCCRTC
RC1411 2 0_0402_5%
CC15 BY20 @
Imax : 0.702A CD15 VCCPRIM_1P8_1 VCCPRIM_1P05_13 BP24 DCPRTC CC66 1 2 1U_0201_6.3V6M
Close to BV12 VCCPRIM_1P8_4 DCPRTC 1
CD16
+3VALW CP17 VCCPRIM_1P8_5 Close to BP24 CC67
Close to BV2 VCCPRIM_1P8_8 BR20
CB22 VCCPRIM_1P05_3 2 1U_0201_6.3V6M
Imax : 0.21A VCCPRIM_3P3_4 Close to BR23
CB23 BT12
CC22 VCCPRIM_3P3_5 VCCAPLL_1P05_3
+1.8VALW CC23 VCCPRIM_3P3_6 BP14
CD22 VCCPRIM_3P3_7 VCCA_BCLK_1P05
VCCPRIM_3P3_8
Saf t y s ugges t i onr emoveE s i de, KeepPWRs i de
CD23 BR14
CP29 VCCPRIM_3P3_9 VCCAPLL_1P05_1
VCCPRIM_3P3_10
1
BU15 BU12
BU22 VCCPRIM_CORE1 VCCA_SRC_1P05
CC68 +1.05VALW
BV15 VCCPRIM_CORE2 CP5
2 1U_0201_6.3V6M BV16 VCCPRIM_CORE3 VCCA_XTAL_1P05
BV18 VCCPRIM_CORE4 BY24
BV19 VCCPRIM_CORE5 VCCDPHY_1P24_2 CA24
BV20 VCCPRIM_CORE6 VCCDPHY_1P24_4 +VCCDPHY_1.24V
BV22 VCCPRIM_CORE7 BY23
VCCPRIM_CORE8 VCCDPHY_1P24_1 CA23 Close to CP25 1
BW 20 Intenal LDO CC70
Close to CP17 BW 22 VCCPRIM_CORE9 VCCDPHY_1P24_3 CP25 VCCDPHY_EC_1P24 CC69 1 2 4.7U_0402_6.3V6M 1U_0201_6.3V6M
CA12 VCCPRIM_CORE10 VCCDPHY_EC_1P24
CA16 VCCPRIM_CORE11 BT23 +1.05VALW 2
C CA18 VCCPRIM_CORE12 VCCDSW _3P3_2 C
+3VALW CA19 VCCPRIM_CORE13 BR12
CA20 VCCPRIM_CORE14 VCCA_19P2_1P05
CB12 VCCPRIM_CORE15
CB14 VCCPRIM_CORE16 +1.8VALW
1 1 VCCPRIM_CORE17 Close to CP5
@ @ Close to BT24 CB15
Internal LDO VCCPRIM_CORE18 CC18
CC71 CC72
BT24 VCCPRIM_1P8_2 CC19
Imax : 0.702A
0.1U_0201_10V K X5R CC73 1 2 1U_0201_6.3V6M DCPDSW
2 1U_0201_6.3V6M 2 VCCDSW _1P05 VCCPRIM_1P8_3 CD18
BU14 VCCPRIM_1P8_6 CD19
VCCAPLL_1P05_4 VCCPRIM_1P8_7 CP23
BV12 VCCPRIM_1P8_9
BW 12 VCCPRIM_MPHY_1P05_1 BW 23
Close to CP29 BW 14 VCCPRIM_MPHY_1P05_3 VCCPRIM_3P3_2
BY12 VCCPRIM_MPHY_1P05_4

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BY14 VCCPRIM_MPHY_1P05_5 +VCCDPHY_1.24V
VCCPRIM_MPHY_1P05_6 BP23
+3VALW BV2 VCCPRIM_3P3_1 +1.8VALW
VCCAMPHYPLL_1P05 CB36
BR15 GPP_B0/CORE_VID0 CB35 VCCDPHY_EC_1P24 R1 1 CNVi@ 2 0_0201_5%
VCCAPLL_1P05_2 GPP_B1/CORE_VID1
+3VALW CC12
VCCDUSB_1P05 1
When CNVi is not used in the design:
1 @
@ BR24 VCCDPHY_1P24 pin shall be disconnected from the VCCLDOSRAM_IN_1P24 pin.
VCCDSW _3P3_1 CC75
CC74 +3V_1.8V_HDA The decoupling capacitor shall remain connected to the VCCDPHY_1P24 pin.
0.1U_0201_10V K X5R BT20 2 1U_0201_6.3V6M
2 VCCHDA
BV23
BT18 VCCSPI
BT19 VCCPRIM_1P05_4
Close to BR24 BU18 VCCPRIM_1P05_5 Close to CP23
BU19 VCCPRIM_1P05_7
VCCPRIM_1P05_8
BT22
+3VALW RF@ +3V_1.8V_HDA BP22 VCCPRIM_1P05_6
B VCCPRIM_1P05_2 B
LC2 BV14
1 2 VCCPRIM_MPHY_1P05_2
BLM15BB221SN1D_2P CFLU-43E_BGA1528
SM01000BV00 @
16 of 20
CC76
0.1U_0402_25V6
21

RF@

UC1O

RF request K12
K14 VCCOPC1 VCCEOPIO1
AA24
AA26
K15 VCCOPC2 VCCEOPIO2 AB25
K17 VCCOPC3 VCCEOPIO3 AC24
K18 VCCOPC4 VCCEOPIO4 AC25
K20 VCCOPC5 VCCEOPIO5 AC26
L25 VCCOPC6 VCCEOPIO6 AD24
M24 VCCOPC7 VCCEOPIO7 AD26
M26 VCCOPC8 VCCEOPIO8
P24 VCCOPC9 V25
P26 VCCOPC10 VCCEOPIO_SENSE T25
R24 VCCOPC11 VSSEOPIO_SENSE
VCCOPC12
R25
VCCOPC13
R26
VCCOPC14

W 25
VCC_OPC_1P8_2
V24
VCC_OPC_1P8_1
Y25
VCC_OPC_1P8_4
Y24
VCC_OPC_1P8_3

A A
CFLU-43E_BGA1528
@
15 of 20
VCCOPC and VCCEOPIO for CFL U43e only

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
WHL-U(9/12)Power
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Custtom
LA-H082P 0..2

Date: Monday,,, Octttober 22,,, 2018 Sheet 14 o f 53

5 4 3 2 1
 5 4 3 2 1

+VCC_GT +VCC_GT
+VCC_CORE +VCC_CORE
UC1M
UC1L
A5 D15
AN9 AW 24 A6 VCCGT8 VCCGT58 D17
AN10 VCCCORE5 VCCCORE35 AW25 A8 VCCGT9 VCCGT59 D18
AN24 VCCCORE1 VCCCORE36 AW26 A11 VCCGT10 VCCGT60 D20
D D
AN26 VCCCORE2 VCCCORE37 AW27 A12 VCCGT1 VCCGT61 E4
AN27 VCCCORE3 VCCCORE38 AY24 A14 VCCGT2 VCCGT64 F5
AP2 VCCCORE4 VCCCORE44 AY26 A15 VCCGT3 VCCGT69 F6
AP9 VCCCORE6 VCCCORE45 BA5 +VCC_CORE A17 VCCGT4 VCCGT70 F7
AP24 VCCCORE9 VCCCORE48 BA7 A18 VCCGT5 VCCGT71 F8
AP26 VCCCORE7 VCCCORE49 BA8 A20 VCCGT6 VCCGT72 F11
AR5 VCCCORE8 VCCCORE50 BA25 AA9 VCCGT7 VCCGT65 F14
AR6 VCCCORE13 VCCCORE46 BA27 AB2 VCCGT11 VCCGT66 F17
AR7 VCCCORE14 VCCCORE47 BB2 AB8 VCCGT13 VCCGT67 F20
AR8 VCCCORE15 VCCCORE51 BB26 AB9 VCCGT14 VCCGT68 G11
AR10 VCCCORE16 VCCCORE52 BC5 AB10 VCCGT15 VCCGT73 G12
AR25 VCCCORE10 VCCCORE56 BC6 AC8 VCCGT12 VCCGT74 G14
VCCCORE11 VCCCORE57 AD9 VCCGT16 VCCGT75 G15
AR27 BC7
VCCCORE12 VCCCORE58 AE8 VCCGT17 VCCGT76 G17
AT9 BC9
VCCCORE19 VCCCORE59 AE9 VCCGT19 VCCGT77 G18
AT24 BC10
VCCCORE17 VCCCORE53 AE10 VCCGT20 VCCGT78 G20
AT26 BC26
VCCCORE18 VCCCORE54 AF2 VCCGT18 VCCGT79 H5
AU5 BC27
VCCCORE24 VCCCORE55 AF8 VCCGT22 VCCGT87 H6
AU6 BD5
VCCCORE25 VCCCORE63 AF10 VCCGT23 VCCGT88 H7
AU7 BD8
VCCCORE26 VCCCORE64 AG8 VCCGT21 VCCGT89 H8
AU8 BD10
VCCCORE27 VCCCORE60 AG9 VCCGT24 VCCGT90 H11
AU9 BD25
VCCCORE28 VCCCORE61 AH9 VCCGT25 VCCGT80 H12
AU24 BD27
VCCCORE20 VCCCORE62 AJ8 VCCGT26 VCCGT81 H14
AU25 BE9
VCCCORE21 VCCCORE69 AJ10 VCCGT28 VCCGT82 H15
AU26 VCCCORE22 VCCCORE65 BE24
AU27 BE25 AK2 VCCGT27 VCCGT83 H17
VCCCORE23 VCCCORE66 AK9 VCCGT29 VCCGT84 H18
AV2 VCCCORE30 VCCCORE67 BE26
AV5 BE27 AL8 VCCGT30 VCCGT85 H20
VCCCORE32 VCCCORE68 AL9 VCCGT32 VCCGT86 J7
AV7 VCCCORE33 VCCCORE70 BF2
AL10 VCCGT33 VCCGT95 J8
C AV10 VCCCORE29 VCCCORE73 BF9 C
AM8 VCCGT31 VCCGT96 J11
AV27 VCCCORE31 VCCCORE71 BF24
B3 VCCGT34 VCCGT91 J14
AW 5 VCCCORE39 VCCCORE72 BF26
B4 VCCGT39 VCCGT92 J17
AW 6 VCCCORE40 VCCCORE74 BG27
B6 VCCGT40 VCCGT93 J20
AW 7 VCCCORE41
B8 VCCGT41 VCCGT94 K2
AW 8 VCCCORE42 AN6 VCCCORE_SENSE [47]
VCC_SENSE VCCGT42 VCCGT98
AW 9 VCCCORE43 AN5 VSSCORE_SENSE [47] Trace Length Match < 25 mils B11
VCCGT35 VCCGT97
K11
AW 10 VSS_SENSE B14 L7
VCCCORE34 SOC_SVID_ALERT# VCCGT36 VCCGT100
AA3 B17 L8
VIDALERT# B20 VCCGT37 VCCGT101 L10
VR_SVID_CLK C2 VCCGT38 VCCGT99 M9
BB9 AA1 VCCGT49 VCCGT102
RSVD3 VIDSCK VR_SVID_CLK [47] C3 N7
BC24 VCCGT51 VCCGT104

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AY9 RSVD4 AA2 VR_SVID_DATA C6 N8
RSVD1 VIDSOUT VCCGT52 VCCGT105
BB24 C7 N9
RSVD2 C8 VCCGT53 VCCGT106 N10
RSVD5 Y3 +1.05VS_VCCIO VCCGT54 VCCGT103
C11 P2
C12 VCCGT43 VCCGT107 P8
BG3 VCCGT44 VCCGT108
VCCSTG1 C14 R9
C15 VCCGT45 VCCGT109 T8
CFLU-43E_BGA1528 VCCGT46 VCCGT111
C17 T9
@ VCCGT47 VCCGT112
12 of 20 C18 T10
VCCGT48 VCCGT110
C20 U8
VCCGT50 VCCGT114
D4 U10
VCCGT62 VCCGT113
SVID ALERT D7
D11
VCCGT63
VCCGT55
VCCGT115
VCCGT116
V2
V9
+1.05V_VCCST
Place the PU D12
VCCGT56 VCCGT117
W8
D14 W9
resistors close to CPU Y10
VCCGT57 VCCGT118
Y8
VCCGT119 VCCGT120
1

B E3 VCCGT_SENSE B
VCCGT_SENSE D2 VSSGT_SENSE VCCGT_SENSE [47]
RC147
VSSGT_SENSE VSSGT_SENSE [47]
56_0402_5%
CFLU-43E_BGA1528 Trace Length Match < 25 mils
13 of 20
@
2

SOC_SVID_ALERT# 1 2
VR_ALERT# [47]
(To VR)
RC148 220_0402_5%

+1.05V_VCCST

SVID DATA Place the PU

resistors close to CPU
1

RC149
100_0402_1%
2

VR_SVID_DATA
VR_SVID_DATA [47] (To VR)
A A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(10/12)Power,SVID
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 15 of 53

5 4 3 2 1
 5 4 3 2 1

D D

UC1R UC1S UC1T

BT35 BY25
CR34 BL7 D6 VSS_145 VSS_217 J18 N6 CF23
BT5 VSS_1 VSS_73 AE25 AL32 VSS_146 VSS_218 AU32 B37 VSS_290 VSS_362 V4
BY5 VSS_2 VSS_74 BM33 BT36 VSS_147 VSS_219 BY28 CB3 VSS_291 VSS_363 BE30
CP35 VSS_3 VSS_75 CM5 D8 VSS_148 VSS_220 J21 P10 VSS_292 VSS_364 CF28
CM37 VSS_4 VSS_76 AE27 AL7 VSS_149 VSS_221 AV25 B5 VSS_293 VSS_365 W10
CK37 VSS_5 VSS_77 BM35 D9 VSS_150 VSS_222 BY33 CB33 VSS_294 VSS_366 BE31
AW1 VSS_6 VSS_78 CM9 AM10 VSS_151 VSS_223 J24 P3 VSS_295 VSS_367 CF3
CM1 VSS_7 VSS_79 AE30 BU11 VSS_152 VSS_224 AV28 B7 VSS_296 VSS_368 W27
BD6 VSS_8 VSS_80 BM36 E23 VSS_153 VSS_225 BY35 CB4 VSS_297 VSS_369 CF4
AY4 VSS_9 VSS_81 CN13 AM28 VSS_154 VSS_226 J33 P33 VSS_298 VSS_370 W30
B34 VSS_10 VSS_82 AE7 E27 VSS_155 VSS_227 AV3 B9 VSS_299 VSS_371 BF3
E35 VSS_11 VSS_83 BM9 AM33 VSS_156 VSS_228 BY36 CB7 VSS_300 VSS_372 CG33
A4 VSS_12 VSS_84 CN17 BU23 VSS_157 VSS_229 J36 P36 VSS_301 VSS_373 W7
AE24 VSS_13 VSS_85 AF27 E29 VSS_158 VSS_230 AV33 BA10 VSS_302 VSS_374 BF33
VSS_14 VSS_86 VSS_159 VSS_231 CC11 VSS_303 VSS_375 CG7
AE26 BN30 AM35 J6
VSS_15 VSS_87 VSS_160 VSS_232 P4 VSS_304 VSS_376 BF36
AF25 CN21 BU24 AV36
VSS_16 VSS_88 VSS_161 VSS_233 BA28 VSS_305 VSS_377 Y26
AG24 AF3 E31 C1
VSS_17 VSS_89 VSS_162 VSS_234 P7 VSS_306 VSS_378 BF4
AG26 BN7 BU25 K21
VSS_18 VSS_90 VSS_163 VSS_235 BA3 VSS_307 VSS_379 CH31
AH24 CN25 E33 AV4
VSS_19 VSS_91 VSS_164 VSS_236 CC20 VSS_308 VSS_380 Y27
AH25 AF30 AN25 C21
VSS_20 VSS_92 VSS_165 VSS_237 R27 VSS_309 VSS_381 BG25
B2 CN29 BU7 K22
VSS_21 VSS_93 VSS_166 VSS_238 BB3 VSS_310 VSS_382 Y30
B36 AF33 E9 AV6
VSS_22 VSS_94 VSS_167 VSS_239 CC25 VSS_311 VSS_383 BG28
C36 BP15 AN28 C25
VSS_23 VSS_95 VSS_168 VSS_240 R28 VSS_312 VSS_384 CJ11
C37 AF36 BV11 K24
VSS_24 VSS_96 VSS_169 VSS_241 BB33 VSS_313 VSS_385 Y33
C CN1 AF4 F12 AV8 C
VSS_25 VSS_97 VSS_170 VSS_242 CC28 VSS_314 VSS_386 CJ14
CN2 CN5 AN29 VSS_171 VSS_243 C29
VSS_26 VSS_98 R29 VSS_315 VSS_387 Y35
CN37 VSS_27 VSS_99 AF7 F15 VSS_172 VSS_244 K25
BB36 VSS_316 VSS_388 BH28
CP2 VSS_28 VSS_100 BP25 AN30 VSS_173 VSS_245 AW28
CC31 VSS_317 VSS_389 CJ19
D1 VSS_29 VSS_101 CN9 F18 VSS_174 VSS_246 C33
R30 VSS_318 VSS_390 Y7
A32 VSS_30 VSS_102 AG10 AN31 VSS_175 VSS_247 K27
BB4 VSS_319 VSS_391 BH29
F33 VSS_31 VSS_103 BP3 BV3 VSS_176 VSS_248 AW29
CC7 VSS_320 VSS_392 CJ23
A3 VSS_32 VSS_104 CP1 F2 VSS_177 VSS_249 C4
R31 VSS_321 VSS_393 BH32
BJ7 VSS_33 VSS_105 BP32 AN7 VSS_178 VSS_250 K28
BC25 VSS_322 VSS_394 CJ28
CJ36 VSS_34 VSS_106 CP11 BV31 VSS_179 VSS_251 AW3
CD11 VSS_323 VSS_395 BH33
A36 VSS_35 VSS_107 AH27 F21 VSS_180 VSS_252 C9
T27 VSS_324 VSS_396 CJ33
BK10 VSS_36 VSS_108 BP33 AN8 VSS_181 VSS_253 K29
VSS_325 VSS_397

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CJ4 CP13 BV33 AW30 CD12 BH35
VSS_37 VSS_109 VSS_182 VSS_254 T30 VSS_326 VSS_398 CJ35
AB27 VSS_38 VSS_110 AH28 F24 VSS_183 VSS_255 CA11 VSS_327 VSS_399
BK2 BP4 BV4 K3 BC29 BP19
VSS_39 VSS_111 VSS_184 VSS_256 VSS_328 VSS_400
CK1 CP15 F3 AW31 CD14 BR16
VSS_40 VSS_112 VSS_185 VSS_257 VSS_329 VSS_401
AB3 AH29 AP3 CA15 T33 BY18
VSS_41 VSS_113 VSS_186 VSS_258 VSS_330 VSS_402
BK28 BP7 BW11 K30 T35 BY19
VSS_42 VSS_114 VSS_187 VSS_259 VSS_331 VSS_403
AB30 CP19 F4 AY33 BC32 CC16
VSS_43 VSS_115 VSS_188 VSS_260 VSS_332 VSS_404
BK3 AH30 AP33 CA22 CD24 BU16
VSS_44 VSS_116 VSS_189 VSS_261 VSS_333 VSS_405
CK4 CP21 BW15 K31 T36 CC14
VSS_45 VSS_117 VSS_190 VSS_262 VSS_334 VSS_406
AB33 AH31 G21 AY35 CD25 BR22
VSS_46 VSS_118 VSS_191 VSS_263 VSS_335 VSS_407
BK33 BR19 AP36 K32 T7 BU20
VSS_47 VSS_119 VSS_192 VSS_264 VSS_336 VSS_408
CK7 CP27 G27 B12 BC8 CD20
VSS_48 VSS_120 VSS_193 VSS_265 VSS_337 VSS_409
AB36 AH33 AP4 K4 CE33 BT14
VSS_49 VSS_121 VSS_194 VSS_266 VSS_338 VSS_410
BK4 BR25 G33 VSS_195 VSS_267 B15 U26 BP12
VSS_50 VSS_122 VSS_339 VSS_411
CL2 VSS_51 VSS_123 AH35 AR28 VSS_196 VSS_268 CA25 BD28 CB24
VSS_340 VSS_412
AB4 VSS_52 VSS_124 CP37 G35 VSS_197 VSS_269 K9 CE35 CC24
VSS_341 VSS_413
BK7 VSS_53 VSS_125 AJ25 G36 VSS_198 VSS_270 B18 U7 J5
VSS_342 VSS_414
B CM13 VSS_54 VSS_126 BT15 AT33 VSS_199 VSS_271 CB11 BD33 U24 B
VSS_343 VSS_415
AB7 VSS_55 VSS_127 AJ28 BW24 VSS_200 VSS_272 L27 CE36 BD7
VSS_344 VSS_416
BL25 VSS_56 VSS_128 BT16 G9 VSS_201 VSS_273 B21 V26 AR4
VSS_345 VSS_417
CM17 VSS_57 VSS_129 CP9 AT35 VSS_202 VSS_274 L33 BD35 AU4
VSS_346 VSS_418
AC10 VSS_58 VSS_130 AJ7 H21 VSS_203 VSS_275 B23 CE7 AW4
VSS_347 VSS_419
BL28 VSS_59 VSS_131 CR2 AT36 VSS_204 VSS_276 L35 V27 BA6
VSS_348 VSS_420
CM21 VSS_60 VSS_132 AK3 BW 7 VSS_205 VSS_277 B25 BD36 BC4
VSS_349 VSS_421
AC27 VSS_61 VSS_133 CR36 H27 VSS_206 VSS_278 CB18 CF11 VSS_350 VSS_422 BE4
BL29 VSS_62 VSS_134 AK33 AT4 VSS_207 VSS_279 L36 V3 VSS_351 VSS_423 BE8
CM25 VSS_63 VSS_135 D21 BY11 VSS_208 VSS_280 B27 BE10 VSS_352 VSS_424 BA4
AC30 VSS_64 VSS_136 AK36 AU10 VSS_209 VSS_281 CB19 CF14 VSS_353 VSS_425 BD4
BL30 VSS_65 VSS_137 BT25 BY15 VSS_210 VSS_282 L6 V30 VSS_354 VSS_426 BG4
CM29 VSS_66 VSS_138 D25 H9 VSS_211 VSS_283 B29 BE28 VSS_355 VSS_427 CJ2
BL31 VSS_67 VSS_139 AK4 AU28 VSS_212 VSS_284 CB2 CF19 VSS_356 VSS_428 CJ3
CM31 VSS_68 VSS_140 BT28 BY22 VSS_213 VSS_285 N25 V33 VSS_357 VSS_429 AM5
AD33 VSS_69 VSS_141 AL28 J12 VSS_214 VSS_286 B31 BE29 VSS_358 VSS_430 CM4
BL32 VSS_70 VSS_142 BT33 AU29 VSS_215 VSS_287 CB20 CF2 VSS_359 VSS_431 AC5
CM33 VSS_71 VSS_143 D5 J15 VSS_216 VSS_288 N27 V36 VSS_360 VSS_432 AG5
AD35 VSS_72 VSS_144 AL29 CB25 BE3 VSS_361 VSS_433 CR6
VSS_289

CFLU-43E_BGA1528 CFLU-43E_BGA1528 CFLU-43E_BGA1528

@ @ @
17 of 20 18 of 20 19 of 20

A A

Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(11/12)GND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D SiiizeDocument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W IT HOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 16 of 53

5 4 3 2 1
 5 4 3 2 1

D
+1.05VS_VCCIO D

RC150 1 @ 2 10K_0201_5% CFG0 UC1Q

CFG0 T4 F37
1 @ 2 CFG3 CFG_0 RSVD_TP5 F34
RC151 1K_0201_5% R4 RSVD_TP4
T3 CFG_1 CP36
CFG3 R3 CFG_2 IST_TRIG CN36
CFG4 J4 CFG_3 RSVD_TP3
M4 CFG_4 BJ36
J3 CFG_5 RSVD15 BJ34
M3 CFG_6 RSVD14
R2 CFG_7
BK34
N2 CFG_8 TP_1 BR18
R1 CFG_9 TP_3
N1 CFG_10
J2 CFG_11
L2 CFG_12
BT9
J1 CFG_13 RSVD21 BT8
L1 CFG_14 RSVD20
CFG_15 BP8
L3 RSVD18 BP9
N3 CFG_16 RSVD19
L4 CFG_18 CR4
N4 CFG_17 RSVD29
CFG_19 CP3
C RSVD26 CR3 C
CFG_RCOMP AB5 RSVD27
CFG_RCOMP
W4
ITP_PMODE
CG2
CG1 RSVD25
RSVD24
AT3
RSVD12 AU3
RSVD13
H4

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H3 RSVD34
RSVD33 AN1
BV24 RSVD8 AN2
BV25 RSVD22 RSVD9
RSVD23 AN4
RSVD11 AN3
RSVD10
AL2
G3 RSVD3 AL1
G4 VSS_436 RSVD2
VSS_437
AL4
RSVD5 AL3
BK36 RSVD4
BK35 RSVD17 BP34
RSVD16 TP1 BP36
W3 TP_2 BP35
B AM4 RSVD35 TP_4 B
RSVD7 C34
AM3 VSS_435
RSVD6 A34
RSVD_TP1 B35
RSVD_TP2

A35
RSVD28
CR35 RSVD28 TP@ T2407 Follow Intel suggetion reserve TP
D34 RSVD1
RSVD30 AH26
1 2 CFG_RCOMP G2 ZVM# AJ27
RC152 49.9_0402_1% G1 RSVD32 MSM#
RSVD31 E1
1 2 CFG4 SKTOCC#
RC153 1K_0201_5%
CFLU-43E_BGA1528
@
20 of 20

DFX Privacy Strap

1 : Disabled;
Set DFX disable bit in debug interface MSR
CFG3
0 : Enabled;
Set DFX enable bit in debug interface MSR
A A

Display Port Presence Strap

1 : Disabled;
No Physical Display Port at t achedt o E mbedded Dis play port
Security Classification
2018/04/09
Compal Secret Data
2019/04/09 Tiiitllle
Compal Electronics, Inc.
CFG4 Issued Date Deciphered Date
0 : Enabled; THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
WHL-U(12/12)CFG,RSVD
SiiizeDocument Number Rev
An external Display Port device is connected to the Embedded Display Port TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY
BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.2

Date: Monday, October 22, 2018 Sheet 17 of 53

5 4 3 2 1
 5 4 3 2 1

Interleaved Memory

+DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA

+DDR_VREF_CA

U1 U2 U3
U4
DDR_A_D4 DDR_A_D17 DDR_A_D47
D
M1 G2 M1 G2 M1 G2 D
VREF CA DQ L0 DDR_A_D1 VREF CA DQ L0 DDR_A_D20 VREF CA DQ L0 DDR_A_D43 DDR_A_D59
F7 F7 F7 M1 G2
DQ L1 DDR_A_D0 DQ L1 DDR_A_D21 DQ L1 DDR_A_D46 VREF CA DQL 0 F7 DDR_A_D57
H3 H3 H3
DDR_A_MA0 DQ L2 DDR_A_D5 DDR_A_MA0 DQ L2 DDR_A_D22 DDR_A_MA0 DQ L2 DDR_A_D42 DQL 1 H3 DDR_A_D62
1 P3 H7 1 P3 H7 1 P3 H7
DDR_A_MA1 A0 DQ L3 DDR_A_D7 DDR_A_MA1 A0 DQ L3 DDR_A_D19 DDR_A_MA1 A0 DQ L3 DDR_A_D45 DDR_A_MA0 DQL 2 H7 DDR_A_D56
CD2 P7 H2 CD3 P7 H2 CD1 P7 H2 1 P3
.047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D2 .047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D18 .047U_0402_16V7K DDR_A_MA2 A1 DQ L4 DDR_A_D41 DDR_A_MA1 P7 A0 DQL 3 H2 DDR_A_D63
R3 H8 R3 H8 R3 H8 CD4
DDR_A_MA3 A2 DQ L5 DDR_A_D3 DDR_A_MA3 A2 DQ L5 DDR_A_D16 DDR_A_MA3 A2 DQ L5 DDR_A_D44 .047U_0402_16V7K DDR_A_MA2 R3 A1 DQL 4 H8 DDR_A_D60
SE076473K80 N7 J3 SE076473K80 N7 J3 SE076473K80 N7 J3
2 DDR_A_MA4 A3 DQ L6 DDR_A_D6 2 DDR_A_MA4 A3 DQ L6 DDR_A_D23 2 DDR_A_MA4 A3 DQ L6 DDR_A_D40 DDR_A_MA3 N7 A2 DQL 5 J3 DDR_A_D58
N3 J7 N3 J7 N3 J7 SE076473K80
MD@ DDR_A_MA5 A4 DQ L7 MD@ DDR_A_MA5 A4 DQ L7 MD@ DDR_A_MA5 A4 DQ L7 2 DDR_A_MA4 N3 A3 DQL 6 J7 DDR_A_D61
P8 P8 P8 @
DDR_A_MA6 A5 DDR_A_MA6 A5 DDR_A_MA6 A5 DDR_A_MA5 P8 A4 DQ L7
P2 P2 P2
DDR_A_MA7 A6 DDR_A_D9 DDR_A_MA7 A6 DDR_A_D28 DDR_A_MA7 A6 DDR_A_D35 DDR_A_MA6 P2 A5
R8 A3 R8 A3 R8 A3
DDR_A_MA8 A7 DQ U0 DDR_A_D10 DDR_A_MA8 A7 DQ U0 DDR_A_D31 DDR_A_MA8 A7 DQ U0 DDR_A_D34 DDR_A_MA7 R8 A6 DDR_A_D50
R2 B8 R2 B8 R2 B8 A3
DDR_A_MA9 A8 DQ U1 DDR_A_D15 DDR_A_MA9 A8 DQ U1 DDR_A_D25 DDR_A_MA9 A8 DQ U1 DDR_A_D38 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D49
R7 C3 R7 C3 R7 C3
DDR_A_MA10 A9 DQ U2 DDR_A_D13 DDR_A_MA10 A9 DQ U2 DDR_A_D26 DDR_A_MA10 A9 DQ U2 DDR_A_D39 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D51
M3 C7 M3 C7 M3 C7
DDR_A_MA11 A10/AP DQ U3 DDR_A_D11 DDR_A_MA11 A10/AP DQ U3 DDR_A_D24 DDR_A_MA11 A10/AP DQ U3 DDR_A_D37 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D48
T2 C2 T2 C2 T2 C2
DDR_A_MA12 A11 DQ U4 DDR_A_D12 DDR_A_MA12 A11 DQ U4 DDR_A_D27 DDR_A_MA12 A11 DQ U4 DDR_A_D33 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D55
M7 C8 M7 C8 M7 C8
DDR_A_MA13 A12/BC DQ U5 DDR_A_D14 DDR_A_MA13 A12/BC DQ U5 DDR_A_D29 DDR_A_MA13 A12/BC DQ U5 DDR_A_D32 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D52
T8 D3 T8 D3 T8 D3
DDR_A_MA14 A13 DQ U6 DDR_A_D8 DDR_A_MA14 A13 DQ U6 DDR_A_D30 DDR_A_MA14 A13 DQ U6 DDR_A_D36 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D54
L2 D7 L2 D7 L2 D7
A14/W E DQ U7 A14/W E DQ U7 A14/W E DQ U7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D53
DDR_A_BA0 DDR_A_BA0 DDR_A_BA0 A14/W E DQ U7
N2 N2 N2
[7,20] DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA1 BA0 DDR_A_BA0
N8 B3 N8 B3 N8 B3 N2
[7,20] DDR_A_BA1 BA1 VDD +1.2V BA1 VDD +1.2V BA1 VDD +1.2V DDR_A_BA1
B9 B9 B9 N8 BA0 B3
VDD VDD VDD BA1 VDD +1.2V
E2 D1 E2 D1 E2 D1 B9
+1.2V DMU/DBIU VDD +1.2V DMU/DBIU VDD +1.2V DMU/DBIU VDD VDD
E7 G7 E7 G7 E7 G7 E2 D1
DML/DBIL VDD DML/DBIL VDD DML/DBIL VDD +1.2V
J1 J1 J1 E7 DMU/DBIU VDD G7
VDD VDD VDD DML/DBIL VDD J1
J9 J9 J9
VDD VDD VDD VDD J9
L1 L1 L1
DDR_A_CLK0 VDD DDR_A_CLK0 VDD DDR_A_CLK0 VDD VDD L1
K7 L9 K7 L9 K7 L9
[7] DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK#0 CK_t VDD DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD L9
K8 R1 K8 R1 K8 R1 K7
[7] DDR_A_CLK#0 VDD VDD VDD DDR_A_CLK#0
DDR_A_CKE0 K2 CK_c T9 DDR_A_CKE0 K2 CK_c T9 DDR_A_CKE0 K2 CK_c T9 K8 CK_t VDD R1
[7,20] DDR_A_CKE0 CKE VDD CKE VDD CKE VDD DDR_A_CKE0 K2 CK_c VDD T9
CKE VDD
A1 A1 A1
VDDQ VDDQ VDDQ
A9 A9 A9 A1
VDDQ VDDQ VDDQ VDDQ A9
C1 C1 C1
VDDQ VDDQ VDDQ VDDQ C1
D9 D9 D9
VDDQ VDDQ VDDQ VDDQ D9
F2 F2 F2
VDDQ VDDQ VDDQ VDDQ F2
F8 F8 F8
DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ VDDQ F8
K3 G1 K3 G1 K3 G1
[7,20] DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ
L7 G9 L7 G9 L7 G9 K3 G1
[7,20] DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_MA16 CS VDDQ DDR_A_MA16 CS VDDQ DDR_A_CS#0 L7 ODT VDDQ G9
L8 J2 L8 J2 L8 J2
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA16 L8 CS VDDQ J2
M8 J8 M8 J8 M8 J8
CAS VDDQ CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ B2 Replace with 240 Ohm to Support DDP@ CAS VDDQ
VSS DDP@ VSS DDP@ VSS DDP@
E1 E1 E1 B2 Replace with 240 Ohm to Support DDP@
VSS RD55 1 2 240_0402_1% VSS RD56 1 2 240_0402_1% VSS RD57 1 2 240_0402_1% VSS E1
C
E9 E9 E9 DDP@ C
VSS VSS VSS VSS E9 RD58 1
G8 G8 G8 2 240_0402_1%
DDR_A_DQS#1 VSS DDR_A_DQS#3 VSS DDR_A_DQS#4 VSS VSS G8
A7 K1 A7 K1 A7 K1
DDR_A_DQS1 DQ SU_c VSS DDR_A_DQS3 DQ SU_c VSS DDR_A_DQS4 DQ SU_c VSS DDR_A_DQS#6 VSS K1
B7 K9 B7 K9 B7 K9 A7
DDR_A_DQS#0 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS#2 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS#5 DQ SU_t VSS DDR_A_BG1_R DDR_A_DQS6 B7 DQSU_ c VSS K9
F3 M9 F3 M9 F3 M9
DQ SL_c VSS DDR_A_BG1_R [20] DQ SL_c VSS DQ SL_c VSS
DDR_A_DQS0 G3 N1 DDR_A_DQS2 G3 N1 DDR_A_DQS5 G3 N1 DDR_A_DQS#7 F 3 DQSU_ t VSS M9 DDR_A_BG1_R
DQSL_t VSS DQSL_t VSS DQSL_t VSS DDR_A_DQS7 G3 DQSL _ c VSS N1
T1 T1 T1
VSS VSS VSS DQSL_t VSS T1
MEMRST# P1 MEMRST# P1 MEMRST# P1
RESET RESET RESET P1 VSS
MEMRST#
1 2 RU1 F9 1 2 RU2 F9 1 2 RU3 F9 RESET
240_0402_1% ZQ 240_0402_1% ZQ 240_0402_1% ZQ 1 2 RU4 F9
240_0402_1% ZQ
MD@
DDR_A_ACT# MD@
DDR_A_ACT# MD@
DDR_A_ACT#
L3 A2 L3 A2 L3 A2 MD@
[7,20] DDR_A_ACT# DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ DDR_A_ACT#
[7,20] DDR_A_BG0 M2 A8 M2 A8 M2 A8 L3 A2
BG0 VSSQ BG0 VSSQ BG0 VSSQ DDR_A_BG0 M2 ACT VSSQ A8
N9 C9 N9 C9 N9 C9
DDR_A_ALERT# TEN VSSQ DDR_A_ALERT# TEN VSSQ DDR_A_ALERT# TEN VSSQ N9 BG0 VSSQ C9
[7] DDR_A_ALERT# P9 D2 P9 D2 P9 D2
DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_ALERT# P9 TEN VSSQ D2
[7,20] DDR_A_PARITY T3 D8 T3 D8 T3 D8
PAR VSSQ PAR VSSQ PAR VSSQ DDR_A_PARITY T3 ALERT VSSQ D8
E3 E3 E3
VSSQ VSSQ VSSQ PAR VSSQ E3
T7 E8 T7 E8 T7 E8

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NC VSSQ NC VSSQ NC VSSQ VSSQ E8
B1 F1 B1 F1 B1 F1 T7
+2.5V VPP VSSQ +2.5V VPP VSSQ +2.5V VPP VSSQ
R9 H1 R9 H1 R9 H1 B1 NC VSSQ F1
VPP VSSQ VPP VSSQ VPP VSSQ +2.5V
H9 H9 H9 R9 VPP VSSQ H1
96-B AL L VSSQ 96-B AL L VSSQ 96-B AL L VSSQ VPP VSSQ H9
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 96-B AL L VSSQ
K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 SDRAM DDR4
@ @ @ K4AAG165WB-MCRC C38
@

Co-lay for SDP / DDP Memory DIE

[7,20] DDR_A_MA[0..16]

[7] DDR_A_DQS#[0..7]

[7] DDR_A_DQS[0..7]
SDP@

On Board RAM - DataMapping

[7] DDR_A_D[0..63]
RD55
SD034000080
B B
0_0402_1%

SDP@
RD56
DDP@ SD034000080 U4 DQ U2 DQ U3 DQ U1 DQ
DDR_A_BG1_R RD7 1 2 0_0402_5% 0_0402_1%
DDR_A_BG1 [7]
DQL0 D13 DQL0 D29 DQL0 D43 DQL0 D60
SDP@
RD57 DQL1 D12 DQL1 D25 DQL1 D40 DQL1 D61
SDP@ For SDP@ SD034000080
RD9 1 2 0_0402_5% 0_0402_1% DQL2 D11 DQL2 D27 DQL2 D42 DQL2 D62
CLOCKTERMINATION SDP@
RD58
DQL3 D8 DQL3 D24 DQL3 D41 DQL3 D57
SD034000080 DQL4 DQL4 DQL4 DQL4
D10 D30 D47 D58
0_0402_1%
DQL5 D9 DQL5 D28 DQL5 D45 DQL5 D56
+1.2V
DQL6 D14 DQL6 D31 DQL6 D46 DQL6 D59
DQL7 D15 DQL7 D26 DQL7 D44 DQL7 D63
DDR_A_CLK0 2 33_0402_1% CU25 1
RU5 1 2 DQU0 D6 DQU0 D22 DQU0 D38 DQU0 D50
DDR_A_CLK#0 2 33_0402_1%
RU6 1
MD@ 0.01U_0402_16V7K DQU1 D1 DQU1 D17 DQU1 D37 DQU1 D52
DDR_A_CLK0 MD@ MD@
1 DQU2 D7 DQU2 D23 DQU2 D35 DQU2 D51
+1.2V
@
CD5 DQU3 D5 DQU3 D20 DQU3 D32 DQU3 D48
3300P_0402_50V7K
DDR_A_CLK#0 2
DQU4 D3 DQU4 D19 DQU4 D33 DQU4 D54
+1.2V
DQU5 D4 DQU5 D16 DQU5 D36 DQU5 D53
2

DDR_A_ALERT# RD11 2
DQU6 D2 DQU6 D18 DQU6 D39 DQU6 D55
1 49.9_0402_1% RD12
1.8K_0402_1% DQU7 D0 DQU7 D21 DQU7 D34 DQU7 D49
MD@ RD13 +DDR_VREF_CA
MD@
2.7_0402_1%
1

2 1
[7] +0.6V_A_VREFCA

MD@
1
DDR_DRAMRST# RD14 1 @ 2 0_0402_5% MEMRST#
[7,19] DDR_DRAMRST#
CD6
A A
1 0.022U_0402_16V7K
@ 2
CD7 MD@
1

100P_0201_25V8J
2 RD15 RD16
24.9_0402_1% 1.8K_0402_1%
MD@
2

MD@

Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data

2018///04///09 2019/04/09//// Tiitttlle
IIIssued Dattte Deciphered Dattte

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
DDR4 ON BOARD CHIPS
LA-H082P
Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
Custttom 0..2
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 18 offf 53
5 4 3 2 1
 A B C D E

[7] DDR_B_DQS#[0..7]
Reverse Type
[7] DDR_B_D[0..63]

[7] DDR_B_DQS[0..7] 2-3A to 1 DIMMs/channel

[7] DDR_B_MA[0..16]
DDR_B_BA0
[7] DDR_B_BA0 DDR_B_BA1 +1.2V +1.2V +1.2V
[7] DDR_B_BA1 DDR_B_BG0
JDIMM1
[7] DDR_B_BG0 DDR_B_BG1
[7] DDR_B_BG1
1 2
DDR_B_D1 VSS1 VSS2 DDR_B_D0
3 4
DQ5 DQ4 +DIMM_VREF_DQ
5 6
DDR_B_D4 VSS3 VSS4 DDR_B_D5
7 8
DDR_B_CLK0 DQ1 DQ0

2
9 10
[7] DDR_B_CLK0 DDR_B_CLK#0 DDR_B_DQS#0 VSS5 VSS6 RD17
11 12
[7] DDR_B_CLK#0 DDR_B_CLK1 DDR_B_DQS0 DQ S0_c DM0_n/DBI0_n
1 [7] DDR_B_CLK1 13 14 1K_0402_1% 1
DDR_B_CLK#1 DQ S0_t VSS7 DDR_B_D3
15 16 RD18
[7] DDR_B_CLK#1 DDR_B_D6 17
VSS8 DQ 6
18 20mil 2_0402_1%
DQ7 VSS9

1
19 20 DDR_B_D2 2 1
DDR_B_CKE0 DDR_B_D7 VSS10 DQ 2 [7] +0.6V_B_VREFDQ
21 22
[7] DDR_B_CKE0 DDR_B_CKE1 DQ3 VSS11 DDR_B_D11
23 24
[7] DDR_B_CKE1 DDR_B_CS#0 DDR_B_D9 VSS12 DQ 12
[7] DDR_B_CS#0 25 26 1
DDR_B_CS#1 DQ1 3 VSS13 DDR_B_D8
[7] DDR_B_CS#1 27 28
DDR_B_D13 VSS14 DQ 8
29 30 CD8
DQ9 VSS15 DDR_B_DQS#1
31 32 0.022U_0402_16V7K
SOC_SMBDATA VSS16 DQ S1_c DDR_B_DQS1 2
33 34
[8] SOC_SMBDATA SOC_SMBCLK DM1_n/DBI_n DQ S1_t
35 36
[8] SOC_SMBCLK DDR_B_D10 VSS17 VSS18 DDR_B_D15

2
37 38
DQ1 5 DQ 14
39 40 RD19 RD20
DDR_B_ODT0 DDR_B_D14 VSS19 VSS20 DDR_B_D12
41 42 24.9_0402_1% 1K_0402_1%
[7] DDR_B_ODT0 DDR_B_ODT1 DQ1 0 DQ 11
43 44
[7] DDR_B_ODT1 DDR_B_D32 VSS21 VSS22 DDR_B_D37
45 46
DQ2 1 DQ 20

1
47 48
DDR_B_D36 VSS23 VSS24 DDR_B_D33
49 50
DQ1 7 DQ 16
Note: DDR_B_DQS#4
51
VSS25 VSS26
52
Layout Note: Check voltage tolerance of DDR_B_DQS4
53
DQ S2_c DM2_n/DBI2_n
54
Place near JDIMM1 VREF_DQ at the DIMM socket
55
57
DQ S2_t VSS27
56
58 DDR_B_D35
DDR_B_D39 VSS28 DQ22
59 60
DQ2 3 VSS29 DDR_B_D34
61 62
DDR_B_D38 VSS30 DQ18
63 64
DQ1 9 VSS31 DDR_B_D40
65 66
DDR_B_D45 VSS32 DQ28
67 68
DQ2 9 VSS33 DDR_B_D41
+1.2V 69 70
DDR_B_D44 VSS34 DQ24
71 72
DQ2 5 VSS35 DDR_B_DQS#5
73 74
VSS36 DQ S3_c DDR_B_DQS5
75 76
DM3_n/DBI3_n DQ S3_t
77 78
DDR_B_D42 VSS37 VSS38 DDR_B_D46
1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M

SE00000UC00

1U_0201_6.3V6M
1U_0201_6.3V6M

79 80
SE00000UC00

SE00000UC00

DQ3 0 DQ 31
1

81 82
DDR_B_D43 VSS39 VSS40 DDR_B_D47
CD10

CD11

CD12

CD13

CD14

CD15

CD16
CD9

83 84
DQ2 6 DQ 27
85 86
VSS41 VSS42
2

87 88
CB5/NC CB4/NC
89 90
VSS43 VSS44
91 92
CB1/NC CB0/NC
@ @ 93 94
VSS45 VSS46
95 96
DQ S8_c DM8_n/DBI_n/NC
4 as near side of the DIMM close to VDD pins 97
DQ S8_t VSS47 98
99 100
VSS48 CB6/NC
101 102
2 CB2/NC VSS49 2
+1.2V 103 104
VSS50 CB7/NC
105 106
CB3/NC VSS51 DDR_DRAMRST#_R
107 108
DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1
@ 109 110
@ SE00000UD00

CD22 10U_0402_6.3V6M
@ SE00000UD00

CD25 10U_0402_6.3V6M
CD18 10U_0402_6.3V6M

CD19 10U_0402_6.3V6M

CD20 10U_0402_6.3V6M

CD21 10U_0402_6.3V6M

CD23 10U_0402_6.3V6M

CD24 10U_0402_6.3V6M

CKE0 CKE1 1
111 VDD2 112 CD17
DDR_B_BG1 VDD1 100P_0402_50V8J
113 114
SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

DDR_B_BG0 BG1 ACT_n DDR_B_ACT# [7]

1 1 1 1 1 1 1 1 115 116 ESD@
BG0 ALERT_n DDR_B_ALERT# [7] 2
117 VDD4 118
DDR_B_MA12 VDD3 DDR_B_MA11
119 A11 120
DDR_B_MA9 A12 DDR_B_MA7
121 A7 122
2 2 2 2 2 2 2 2 A9
123 VDD6 124
DDR_B_MA8 VDD5 DDR_B_MA5
125 A5 126
DDR_B_MA6 A8 DDR_B_MA4
127 A4 128
A6
129 VDD8 130
DDR_B_MA3 VDD7 DDR_B_MA2
@ 131 A2 132
DDR_B_MA1 A3
133 EVENT_n/NF 134
A1 136 +1.2V
135 VDD10
DDR_B_CLK0 VDD9 DDR_B_CLK1
137 CK1_t/NF 138
DDR_B_CLK#0 CK0_t DDR_B_CLK#1
139 CK1_c/NF 140

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CK0_c
141 VDD12 142
VDD11 DDR_B_MA0
143 A0 144
[7] DDR_B_PARITY DDR_B_BA1 PARITY DDR_B_MA10
145 A10/AP 146
BA1
147 VDD14 148
DDR_B_CS#0 VDD13 DDR_B_BA0

1
149 BA0 150
DDR_B_MA14 CS0_n DDR_B_MA16 RD23
151 RAS_n/A16 152
W E_n/A14 +DIMM_VREF_DQ
153 VDD16 154 470_0402_1%
DDR_B_ODT0 VDD15 DDR_B_MA15
155 CAS_n/A15 156
DDR_B_CS#1 ODT0 DDR_B_MA13
157 A13 158
CS1_n

2
159 VDD18 160
DDR_B_ODT1 VDD17 DDR_DRAMRST#_R
161 C0/CS2_n/NC 162 RD24 1 @ 2 0_0402_5%
ODT1 DDR_DRAMRST# [7,18]
163 164
VDD19 VREF CA DDR_B_SA2
Place these caps on the VTT plane close to DIMM 165
C1, CS3_n,NC SA2 166
167 168
DDR_B_D22 VSS53 VSS54 DDR_B_D23
169 DQ 36 170
DQ3 7
+0.6VS 171 VSS56 172
DDR_B_D17 VSS55 DDR_B_D16
173 DQ 32 174
DQ3 3
175 VSS58 176
DDR_B_DQS#2 VSS57
177 DM4_n/DBI4_n 178
DDR_B_DQS2 DQ S4_c
179 180
@ CD31 SE00000UD00

DQ S4_t VSS59
DDR_B_D21
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

181 182
SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 VSS60 DQ39
DDR_B_D19
1

183 184
CD30 SE00000UD00

DQ3 8 VSS61
DDR_B_D20
CD26

CD27

CD28 @

CD29 @

185 186
JDIMM1 ADDRESS PLACE CLOSE TO DIMM
VSS62 DQ35
DDR_B_D18 187 188
VSS63
( )
DQ3 4
2

2 2 189 190 DDR_B_D29

VSS64 DQ45
DDR_B_D24 191 192
3 VSS65 3
DQ4 4 DDR_B_D25
193 DQ41 194
DDR_B_D28 VSS66
195 VSS67 196
DQ4 0 DDR_B_DQS#3
197 DQ S5_c 198
VSS68 DDR_B_DQS3
199 DQ S5_t 200
DM5_n/DBI5_n +3VS
201 VSS70 202
DDR_B_D31 VSS69 DDR_B_D27
203 DQ 47 204
DQ4 6
205 VSS72 206
DDR_B_D30 VSS71 DDR_B_D26
207 DQ 43 208
DQ4 2
209 VSS74 210
DDR_B_D52 VSS73 DDR_B_D49
211 DQ 53 212
DQ5 2
213 VSS76 214
DDR_B_D53 VSS75 DDR_B_D48
215 DQ 48 216
DQ4 9
217 VSS78 218
+3VS DDR_B_DQS#6 VSS77
219 DM6_n/DBI6_n 220
DDR_B_DQS6 DQ S6_c
221 VSS79 222
DQ S6_t DDR_B_D50 DDR_B_SA2 DDR_B_SA1 DDR_B_SA0
223 DQ54 224
DDR_B_D55 VSS80
225 VSS81 226
DQ5 5 DDR_B_D51
227 DQ50 228
DDR_B_D54 VSS82
229 VSS83 230
DQ5 1 DDR_B_D56

1
+3VS 231 DQ60 232
DDR_B_D60 VSS84 RD27
233 VSS85 234 RD28
DQ6 1 DDR_B_D61 0_0402_5%
235 DQ57 236 @ 0_0402_5%
DDR_B_D57 VSS86 @
237 238
2.2U_0402_6.3V6M

1 1 DQ5 6 VSS87
DDR_B_DQS#7
CD32 239 DQ S7_c 240
VSS88 DDR_B_DQS7

2
C1

0.1U_0201_10V6K +2.5V 241 DQ S7_t 242 +0.6VS

DM7_n/DBI7_n
243 VSS90 244
2 2 DDR_B_D62 VSS89 DDR_B_D59
245 DQ 63 246
DQ6 2
247 VSS92 248
DDR_B_D63 VSS91 DDR_B_D58
249 DQ 59 250
DQ5 8
251 VSS94 252
SOC_SMBCLK VSS93 SOC_SMBDATA
close to DIMM 253
SCL SDA 254
DDR_B_SA0
+3VS 255 SA0 256
VDDSPD
257 VTT 258
VPP1 DDR_B_SA1
259 SA1 260
VPP2
261 GND2 262
GND1
+2.5V

DEREN_40-42271-26001RHF
SP07001CY00
ME@
4 4

1
1

@ C2 CD33
10U_0402_6.3V6M 1U_0201_6.3V6M
SE00000UD00 SE00000UC00
2

Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

IIIssued Dattte 2018/04/09//// Deciphered Dattte 2019///04///09 Tiitttlle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
DDR4_DIMM
Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
LA-H082P
Custttom 0..2
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 19 offf 53
A B C D E
 5 4 3 2 1

[7,18] DDR_A_MA[0..16]

D D

+1.2V

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00
1

1
+0.6VS

CU1

CU2

CU3

CU4

CU5

CU6

CU7

CD34

CD35

CD36

CD37

CD38

CD39

CD40

CD41

CD42
2

2
@ @
@ @
MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ MD@ DDR_A_MA9
RD29 1 2 36_0201_5%
DDR_A_MA2
RD30 1 2 36_0201_5%
DDR_A_MA4 RD31 1 MD@ 2 36_0201_5%
DDR_A_BA1 RD32 1 MD@ 2 36_0201_5%
[7,18] DDR_A_BA1
4 as near each on board RAM device as possible MD@
MD@

DDR_A_MA10
RD33 1 2 36_0201_5%
DDR_A_MA3 RD34 1 2 36_0201_5%
DDR_A_MA12 RD35 1 MD@ 2 36_0201_5%
CD43 10U_0402_6.3V6M

CD44 10U_0402_6.3V6M

CD45 10U_0402_6.3V6M

CD46 10U_0402_6.3V6M

CD47 10U_0402_6.3V6M
DDR_A_BG0 RD36 1 MD@ 2 36_0201_5%
[7,18] DDR_A_BG0
SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00
MD@
1 1 1 1 1 MD@

2 2 2 2 2

DDR_A_MA16
RD37 1 2 36_0201_5%
DDR_A_ACT#
RD38 1 2 36_0201_5%
[7,18] DDR_A_ACT# DDR_A_CS#0
MD@ MD@ MD@ @ MD@ RD39 1 MD@ 2 36_0201_5%
[7,18] DDR_A_CS#0 DDR_A_MA15 RD40 1 MD@ 2 36_0201_5%
MD@
MD@

C C

DDR_A_CKE0 RD41 1 2 36_0201_5%

[7,18] DDR_A_CKE0 DDR_A_ODT0 RD42 1 2 36_0201_5%
[7,18] DDR_A_ODT0 DDR_A_MA14 RD43 1 MD@ 2 36_0201_5%
MD@
MD@

DDR_A_MA13
RD44 1 2 36_0201_5%
DDR_A_MA8
RD45 1 2 36_0201_5%
DDR_A_PARITY RD46 1 MD@ 2 36_0201_5%
[7,18] DDR_A_PARITY DDR_A_MA11 RD47 1 MD@ 2 36_0201_5%
+2.5V +0.6VS MD@
MD@
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
www.teknisi-indonesia.com
SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00

SE00000UC00
1

1
CU9

CU10

CU11

CU12

CU13

CU14

CU15

CU16

CU17

CU18

CU19

CU20

CU21

CU22

CU23

CU24
@
DDR_A_MA1
RD48 1 2 36_0201_5%
DDR_A_BA0
2

2
@ @ RD49 1 2 36_0201_5%
[7,18] DDR_A_BA0 DDR_A_MA7
@ @ RD50 1 MD@ 2 36_0201_5%
MD@ MD@ MD@ MD@ MD@ MD@ @ MD@ MD@ MD@ MD@ MD@
MD@
2 as near each on board RAM device as possible
2 as near each on board RAM device as possible

DDR_A_MA5 RD51 1 2 36_0201_5%

DDR_A_MA6 RD52 1 2 36_0201_5%
DDR_A_MA0 RD53 1 MD@ 2 36_0201_5%
MD@
MD@

@ @ @ @
CD48 10U_0402_6.3V6M

CD49 10U_0402_6.3V6M

CD50 10U_0402_6.3V6M

CD51 10U_0402_6.3V6M

CD52 10U_0402_6.3V6M

CD53 10U_0402_6.3V6M

CD54 10U_0402_6.3V6M
SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

SE00000UD00

DDR_A_BG1_R RD54 1 DDP@ 2 36_0201_5%

1 1 1 1 1 1 1 [18] DDR_A_BG1_R

B B
2 2 2 2 2 2 2

MD@ MD@ MD@

A A

LA---H081P
Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data
IIIssued Dattte 2018/04/09//// Deciphered Dattte 2019///04///09 Tiitttlle

DDR4 MISC
LA-H082P
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE Siiize DDDocume nt Numbe r Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
Custttom ocument Numbe r 0..2
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS ocument Numbe r
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,,IIINC...
Dattte::: Monday,,, Octttoberrr 22L,,A2-0H108882P Sheettt 20 offf 53
5 4 3 2 1
 1 2 3 4 5

UV1A
COMMON
1/14 PCI_EXPRESS

Place Place near BGA

+1.0VS_DGPU
AB6 PEX_WAKE# under GPU
1.0V
P E X _ IO V DD AA22
PLT_RST_VGA_MON# PLT_RST_VGA#

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
AB23

1U_0402_6.3V6K

4.7U_0402_6.3V6M

22U_0603_6.3V6M
RV1 1 2 0_0402_5% AC7 P E X _RST# P E X _ IO V DD

CV2 N17S@

CV12 DIS@

10U_0402_6.3V6M
CV4 N17S@
AC24

CV1 DIS@

CV3 N17S@

M
10U_0402_6.3V6
CV5 N17S@
N17S@ P E X _ IO V DD 1 1 1 1 1 1 1
CLKREQ_PEG#0_R AD25

CV13 N17S@
AC6 P E X _ CLKREQ # P E X _ IO V DD
P E X _ IO V DD AE26
AE8 P E X _ REF C LK P E X _ IO V DD AE27
[10] CLK_PEG_P0 2 2 2 2 2 2 2
PCIE CLK [10] CLK_PEG_N0 AD8 P E X _REF C LK#
PCIE_CRX_DTX_P5 CV14 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_CRX_C_DTX_P5 AC9 P E X _ TX 0
[12] PCIE_CRX_DTX_P5 PCIE_CRX_DTX_N5 PCIE_CRX_C_DTX_N5
CV6 DIS@ 1 2 0.22U_0402_6.3V6K AB9 P E X _TX 0 #
A [12] PCIE_CRX_DTX_N5 A
PCIE_CTX_C_DRX_P5 AG6 P E X _ RX0
[12] PCIE_CTX_C_DRX_P5 PCIE_CTX_C_DRX_N5 AG7 P E X _R X0# P E X _ IO V DDQ AA10
[12] PCIE_CTX_C_DRX_N5
P E X _ IO V DDQ AA12 Place Place near BGA +1.0VS_DGPU
PCIE_CRX_DTX_P6 PCIE_CRX_C_DTX_P6
[12] PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6
CV7 DIS@ 1 2 0.22U_0402_6.3V6K
PCIE_CRX_C_DTX_N6
AB10 P E X _ TX 1 P E X _ IO V DDQ AA13 under GPU RV447
[12] PCIE_CRX_DTX_N6
CV8 DIS@ 1 2 0.22U_0402_6.3V6K AC10 P E X _ TX 1# P E X _ IO V DDQ AA16 1.0V N16S@
P E X _ IO V DDQ AA18 1 2
PCIE_CTX_C_DRX_P6

1U_0402_6.3V6K

22U_0603_6.3V6M
AA19

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

M
4.7U_0402_6.3V6

4.7U_0402_6.3V6M
AF7 P E X _ RX1 P E X _ IO V DDQ
[12] PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6

CV16 N17S@
AA20

CV15 DIS@

CV733 N17S@

CV734 N17S@

CV17 DIS@

CV18 N17S@

M
10U_0402_6.3V6
CV19 N17S@

M
10U_0402_6.3V6
CV20 DIS@
AE7 P E X _ RX1# P E X _ IO V DDQ 1 1 1 1 1 1 1 1 1 0_0805_5%
[12] PCIE_CTX_C_DRX_N6

CV10 DIS@
P E X _ IO V DDQ AA21
PCIE_CRX_DTX_P7 PCIE_CRX_C_DTX_P7
PCIE X4 Bus [12] PCIE_CRX_DTX_P7 PCIE_CRX_DTX_N7
CV9 DIS@ 1 2 0.22U_0402_6.3V6K
PCIE_CRX_C_DTX_N7
AD11 P E X _TX 2 P E X _ IO V DDQ AB22
CV11 DIS@ 1 2 0.22U_0402_6.3V6K AC11 P E X _ TX 2# P E X _ IO V DDQ AC23 +1.8VGS_+3VGS
[12] PCIE_CRX_DTX_N7 2 2 2 2 2 2 2 2 2
P E X _ IO V DDQ AD24
PCIE_CTX_C_DRX_P7 AE9 P E X _ RX2 P E X _ IO V DDQ AE25 RV458
[12] PCIE_CTX_C_DRX_P7 PCIE_CTX_C_DRX_N7 AF9 P E X _RX 2# P E X _ IO V DDQ AF26 N17S@
[12] PCIE_CTX_C_DRX_N7 AF27
P E X _ IO V DDQ 1 2
PCIE_CRX_DTX_P8 CV21 DIS@ 1 2 0.22U_0402_6.3V6K PCIE_CRX_C_DTX_P8 AC12 P E X _TX 3
[12] PCIE_CRX_DTX_P8 PCIE_CRX_DTX_N8 PCIE_CRX_C_DTX_N8
CV22 DIS@ 1 2 0.22U_0402_6.3V6K AB12 P E X _TX 3# 0_0805_5%
[12] PCIE_CRX_DTX_N8
PCIE_CTX_C_DRX_P8 AG9 P E X _ RX3
[12] PCIE_CTX_C_DRX_P8 PCIE_CTX_C_DRX_N8
[12] PCIE_CTX_C_DRX_N8 AG10 P E X _RX 3#

Near UV1 AB13 P E X _ TX 4

AC13 P E X _TX 4 #
+1.8VGS_+3VGS
RV445
AF10 P E X _ RX4 N17S@
AE10 P E X _RX 4# 1 2

AD14 NC FOR GF119 0_0805_5%

P E X _TX 5
AC14 P E X _TX 5 # P E X _ PLL_HVDD AA8 +1.8VGS_+3VGS_AON
P E X _ PLL_HVDD AA9

NC FOR GM108
AE12 P E X _ RX5 RV446
AF12 P E X _RX5# Place near BGA N16S@
P E X _ SVDD_3V 3 AB8 1 2 1 2
AC15 P E X _TX 6 0_0402_5%
B AB15 B

0.1U_0201_10V6K

M
4.7U_0402_6.3V6

M
4.7U_0402_6.3V6
P E X _TX 6# RV460 0_0805_5%

CV23 DIS@

CV24 DIS@

CV25 DIS@
N16S@ 1 1 1
AG12 P E X _ RX6
AG13 P E X _RX 6#

AB16 P E X _ TX 7 2 2 2
AC16 P E X _TX 7 #

AF13 P E X _ RX7
AE13
Reset Control P E X _RX 7#
+1.8VGS_+3VGS_AON
AD17 P E X _TX 8
UV6
AC17 P E X _TX 8 #
5

MC74VHC1G08DFT2G_SC70-5
AE15

www.teknisi-indonesia.com
P E X _ RX8
1 AF15
GND VCC

IN1 P E X _RX8#
(From PCH) [10,30,31,33,36] PCI_RST# 4
2 OUT PLT_RST_VGA_MON# [24] VDD_SENSE_GPU
IN2 AC18 P E X _TX 9 V D D _ SENSE F2
[11] DGPU_HOLD_RST# VDD_SENSE_GPU [50]
AB18 P E X _TX 9# To POWER
AG15 GND_SENSE_GPU
DIS@ P E X _ RX9 G N D _ S ENSE F1
GND_SENSE_GPU [50] trace width: 16mils
3

AG16 P E X _RX 9#
differential voltage sensing.
+1.8VGS_+3VGS_AON AB19 P E X _TX 10 differential signal routing.
AC19 P E X _ TX 10#
UV7
5

MC74VHC1G08DFT2G_SC70-5 AF16 P E X _RX10

AE16 P E X _ RX10#
1
GND VCC

IN1

NC FOR GF117/GK208/GM108
4 PLT_RST_VGA# AD20 P E X _TX 1 1
2 OUT AC20 P E X _ TX 11#
(From GPU) [24] PLT_RST_VGA_HOLD# IN2
1

AE18 P E X _RX 11
RV2
AF18 P E X _ RX11#
N16S@ 10K_0201_5%
3

DIS@
C
AC21 P E X _TX 1 2 C
AB21
2

P E X _ TX 12#

AG18 P E X _RX 12 PEX_PLL_CLK_OUT RV3 2 @ 1200_0402_1%

P E X _ TS TC LK_O U T AF22
AG19 P E X _ RX12# PEX_PLL_CLK_OUT#
P E X _ TS TC LK_O U T# AE22

CLK_REQ +1.8VGS_+3VGS
AD23
AE23
P E X _TX 1 3
RV4 +1.0VS_DGPU
P E X _ TX 13#
1.0V N16S@
AF19 PEX_PLLVDD_GPU 1 2
P E X _RX13 P E X _ PLLVDD AA14
AE19 P E X _ RX13# P E X _ PLLVDD AA15
1

Place near BALL

1U_0402_6.3V6K
0.1U_0201_10V6K

4.7U_0402_6.3V6M
0_0805_5%
AF24

CV27 N16S@

CV28 N16S@
RV5 P E X _TX 14 1 1 1
AE24

CV26 N16S@
10K_0201_5% P E X _ TX 14#
DIS@ Place near BGA
AE21 P E X _RX 14
2

AF21 P E X _ RX14# 2 2 2
RV6 1 @ 2 0_0402_5% AD9 GPU_TESTMODE
[25,26,50] DGPU_PWROK TE S TM O D E GPU_TESTMODE [24]
AG24 P E X _TX 1 5
AG25 P E X _ TX 15#
+1.8VGS_+3VGS_AON
K
1U_0402_6.3V6
CV29 @

1
AG21 P E X _RX 15
AG22 P E X _ RX15#
1

RV7 2
10K_0201_5% QV150 PEX_TERMP
P E X _ TE R M P AF25
DIS@ DIS@
2

1
G

BSS138W-7-F_SOT323-3
2

N16S-GT-S-A2_BGA595 RV8
CLKREQ_PEG#0_R 3 1 @ 2.49K_0402_1%
CLKREQ_PEG#0 [10]
S

DIS@
(To SOC)

2
1

VGS(Max) : 1.5 V RV9

10K_0201_5%
D @ D
2

RV10 1 @ 2 0_0402_5%

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/10/27 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
NV(1/5)-PCIE
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 21 o f 53
1 2 3 4 5
 1 2 3 4 5

UV1K
DAC_A
UV1G IFPA/B
COMMON
3/14 DACA UV1H
COMMON
IFPC
COMMON GF117/GM108 GF117 GM108/GK208 5/14 IFPC
4/14 IFPAB W5 D A C A _VD D NC NC I2CA_SCL B7 IFPC
NC I2CA_SDA A7
AE2 D A C A _VREF T6 IF P C _ R S E T GF119/GK208
TSEN_VREF
IF P A _TX C # AC4 Note:
IF P A _ TX C AC3 AF2 AE3 IFPC/D/E/F interface are XVDDs pin for N17S GPU,
D A C A_R SET NC NC D A C A _HSYN C DVI/HDMI DP
AE4 and connect them to NVVDD power for improving
NC D A C A _VSYNC
AA6 NVVDD power rail routing M7 N5
IF P A B _RS E T IF P C_P LLV D D I2CW _SDA IF P C_A U X #

NC FOR GF117/GM108
IF P A _TX D0# Y3 N7 IF P C_P LLV D D I2CW _SCL IF P C _ A U X N4
IF P A _ TX D 0 Y4 D A C A _RED AG3
A A

NC FOR GF117/GM108
NC
V7 IF P A B _P LLV DD D A C A _G REE N AF4 TXC IF P C_L3# N3
NC
IF P A _TX D1# AA2 IFPC_L3 N2
TXC
W7 IF P A B _P LLV DD IF P A _ TX D 1 AA3 D A C A _BLUE AF3
NC
IF P C_L2# R3
NC FOR GF117/GM108

TXD0
GM108 IFPC_L2 R2
GK208 TXD0
IF P A _TX D2# AA1 GF117
IF P A _ TX D 2 AB1 TXD1 IF P C_L1# R1
N16S-GT-S-A2_BGA595 TXD1 IFPC_L1 T1
@
NC FOR GF117/GM108

IFPA_TXD3# AA5 IF P C_L0# T3

TXD2
IF P A _ TX D 3 AA4 IFPC_L0 T2
TXD2

IF P B _TX C # AB4 GF117

IF P B _ TX C AB5 P6 IFPC_IOVDD G P IO 1 5 C3
NC

W6 IFPA_IOVDD IF P B _TX D4# AB2

IF P B _ TX D 4 AB3 N16S-GT-S-A2_BGA595
Y6 IFPB_IOVDD @

IF P B _TX D5#
IF P B _ TX D 5
AD2
AD3
UV1I
COMMON
IFPD
6/14 IFPD

IF P B _TX D6# AD1

IF P B _ TX D 6 AE1 U6 GF119/GK208
IF P D _ R S E T

DVI/HDMI DP
IFPB_TXD7# AD5
IF P B _ TX D 7 AD4 T7 IFPD_PLLVDD I2CX_SDA IF P D_A U X # P4
I2CX_SCL IF P D _ A U X P3

NC FOR GF117/GM108
R7 IFPD_PLLVDD

NC FOR GF117/GM108
B +1.8VGS_+3VGS R5 B
GF117
RV448 TXC IF P D_L3#
N17S@ IFPD_L3 R4
TXC
G P IO 1 4 B3 1 2
NC
IFPAB 0_0805_5%
TXD0
TXD0
IF P D_L2#
IFPD_L2
T5
T4
N16S-GT-S-A2_BGA595
@ TXD1 IF P D_L1# U4
+1.0VS_DGPU IFPD TXD1 IFPD_L1 U3

N16S@ IF P D_L0# V4
GPU_PLLVDD TXD2 V3
LV1 1 2 HCB1005KF-300T25_2P IFPD_L0
TXD2

Place near balls

22U_0603_6.3V6M

0.1U_0201_10V K X5R
GF117
1 1

CV30 N16S@

CV31 DIS@
R6 D4

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IFPD_IOVDD G P IO 1 7

IFPE/F
NC

UV1J
COMMON 2 2

7/14 IFPEF

GF119/GK208
N16S-GT-S-A2_BGA595
DVI-DL DVI-SL/HDMI DP @
I2CY_SDA I2CY_SDA IF P E _ A U X# J3
I2CY_SCL I2CY_SCL IF P E _ A U X J2
J7 IF P E F _P LLV DD

IF P E _L3# J1
TXC TXC
IFPE_L3 K1
TXC TXC
NC FOR GF117/GM108

K7 IF P E F _P LLV DD
IF P E _L2# K3
NC FOR GF117/GK208/GM108

TXD0 TXD0 K2
IFPE_L2
TXD0 TXD0 PLLVDD RV457
K6 IF P E F _R S E T IFPE_L1# M3 N17S@
TXD1 TXD1
IFPE_L1 M2 1 2

X'TAL
TXD1 TXD1
C C
IF P E _L0# M1 0_0805_5% UV1M
TXD2 TXD2
IFPE_L0 N1 COMMON
TXD2 TXD2
9/14 XTAL_PLL
IFPE NC FOR GK208 L6 P LLV D D
+1.0VS_DGPU RV456 Place near BGA Place near balls M6 S P _P LLV DD
+1.8VGS_+3VGS_AON
N16S@ RV11 @
C2 1 2 VID_PLLVDD N6 10K_0402_1%
HPD_E G P IO 18 VID_PLLVDD NC
HPD_E XTAL_OUTBUFF 1 2
22U_0603_6.3V6M

22U_0603_6.3V6M

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
0_0805_5% GF117/GM108
NC FOR GF117 GF119/GK208

10U_0402_6.3V6M
CV34 N16S@
1 1 1 1 1
CV32 N16S@

CV33 N16S@

CV35 DIS@

CV36 DIS@
RV12 DIS@ RV13 DIS@
H6 IFPE_IOVDD 10K_0402_1% 10K_0402_1%
GF119/GK208 2 1 A10 X TA L S S IN X TA L O U TB U F F C10
XTAL_OUTBUFF 1 2
J6 2 2 2 2 2
IFPF_IOVDD
DVI-DL DVI-SL/HDMI DP

IF P F _ A U X # H4 C11 XTALIN XTALOU T B10

I2CZ_SDA
I2CZ_SCL IF P F _ A U X H3
N16S-GT-S-A2_BGA595
@
TXC IF P F _L3# J5 90-OHM DIFF Impedance for XTALIN & XTALOUT.

2
TXC IFPF_L3 J4
NC FOR GF117/GM108

YV1 RV14 DIS@

TXD3 TXD0 IF P F _L2# K5 27MHZ_10PF_XRCGB27M000F2P18R0 1.5K_0402_1%
IFPF_L2 K4 SJ10000UI00
TXD3 TXD0

1
L4 1 3
TXD4 TXD1 IFPF_L1# 1 3
IFPF TXD4 TXD1 IFPF_L1 L3
NC NC
1 1
TXD5 TXD2 IF P F _L0# M5 DIS@
IFPF_L0 M4 CV37 DIS@ 2 4 CV38 DIS@
TXD5 TXD2
2 18P_0402_50V8J 2 18P_0402_50V8J
NC FOR GK208

D D
G P IO 19 F7
HPD_F

NC FOR GF117

N16S-GT-S-A2_BGA595
@
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/10/27 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
NV(2/5)-IFP_ABCDEF_DAC_XTAL
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 22 o f 53
1 2 3 4 5
 1 2 3 4 5

UV1D UV1F
+1.35VS_VRAM COMMON COMMON
Place under GPU 12/14 FBVD D Q

B26 F B V D D Q GPU_Decoupling A2
AB17
13/14 GND

GND
GND
GND
GND
M13
M15

CAPs @ Power
C25 FBVDDQ AB20 GND GND M17
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
K
1U_0402_6.3V6

K
1U_0402_6.3V6

K
1U_0402_6.3V6

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

K
1U_0402_6.3V6

K
1U_0402_6.3V6

K
0.1U_0201_10V6

K
0.1U_0201_10V6
E23 FBVDDQ AB24 GND GND N10

CV43 N16S@

CV39 N16S@
1 1 1 1 1 1 1 1 1 1 1 1 E26 FBVDDQ AC2 GND GND N12
CV724

CV721

CV722
CV723

CV719

CV720

CV40

CV41

CV42

CV44
AC22 N14

Page
A F14 FBVDDQ GND GND A
F21 FBVDDQ AC26 GND GND N16
G13 FBVDDQ AC5 GND GND N18
2 2 2 2 2 2 2 2 2 2 2 2
N17S@

N17S@

N17S@

N17S@

N17S@

N17S@

DIS@

DIS@

N16S@

N16S@
G14 FBVDDQ AC8 GND GND P11
G15 FBVDDQ AD12 GND GND P13
G16 FBVDDQ AD13 GND GND P15
G18 FBVDDQ A26 GND GND P17
G19 +VGA_CORE UV1E AD15 GND P2
FBVDDQ GND
G20 FBVDDQ COMMON AD16 GND GND P23
G21 FBVDDQ Voltage by GPU SKU 11/14 NVVD D AD18 GND GND P26
L22 FBVDDQ K10 V D D AD19 GND GND P5
K12 V D D

M
10U_0402_6.3V6
CV726 N17S@

M
10U_0402_6.3V6
CV725 N17S@
1 1 L24 FBVDDQ AD21 GND GND R10
L26 FBVDDQ
K14 V D D AD22 GND GND R12
M21 F B V D D Q K16 V D D AE11 GND R14
GND
N21 FBVDDQ
K18 V D D AE14 GND R16
GND
2 2 R21 L11 V D D AE17 R18
FBVDDQ GND GND
T21 L13 V D D AE20 GND T11
F B V DD Q GND
V21 L15 V D D AB11 GND T13
FBVDDQ GND
W 21 F B V D D Q L17 V D D AF1 T15
GND GND
M10 V D D AF11 T17
GND GND
M12 V D D AF14 U10
GF117 GND GND
M14 V D D AF17 U12
GF119 GND GND
M16 V D D AF20 U14
GK208 GND GND
M18 V D D AF23 U16
GND GND
N11 V D D AF5 U18
H24 F B V D D Q _ A O N FBVDDQ GND GND
N13 V D D AF8 U2
H26 FB V DDQ_A ON FBVDDQ GND GND
N15 V D D
M
22U_0603_6.3V6

M
22U_0603_6.3V6

M
22U_0603_6.3V6
J21 FB V DDQ_A ON FBVDDQ
AG2 GND GND U23
N17 V D D

M
10U_0402_6.3V6
CV46 DIS@
1 1 1 1 K21 F B V D D Q _ A O N FBVDDQ
AG26 GND GND U26
P10 V D D
CV728

CV727

CV45
AB14 GND GND U5
P12 V D D
B1 GND GND V11
P14 V D D
B11 GND GND V13
2 2 2 2 P16 V D D
N17S@

N17S@

DIS@
B14 GND GND V15
P18 V D D
R11 V D D B17 GND GND V17
R13 V D D B20 GND GND Y2
R15 V D D B23 GND GND Y23
R17 V D D B27 GND GND Y26
B B5 Y5 B
T10 V D D GND GND
Place near GPU T12 V D D B8 GND
T14 V D D E11 GND
E14
CIZ00 22uF x1 change to 10uF x2 T16 V D D
E17
GND
T18 V D D GND
U11 V D D E2 GND
U13 V D D E20 GND
U15 V D D E22 GND
U17 V D D E25 GND
Near Ball +1.35VS_VRAM V10 V D D E5 GND
V12 V D D E8 GND
V14 V D D H2 GND
F B _ C A L_PD_VD DQ D22 RV15 1 DIS@ 2 40.2_0402_1% V16 V D D H23 GND
V18 V D D H25 GND
H5

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GND
F B _ C A L_PU_G N D C24 RV16 2 DIS@ 1 40.2_0402_1% K11 GND
K13 GND
N16S-GT-S-A2_BGA595 K15 GND
F B _ C A LTE RM _G ND B25 RV17 2 DIS@ 1 60.4_0402_1% @ K17 GND
L10 GND
L12 GND
N16S-GT-S-A2_BGA595 L14 GND
@ L16 GND
L18 GND
L2 GND
L23 GND
L25 GND
L5 GND GND AA7
M11 GND GND AB7

N16S-GT-S-A2_BGA595
@
UV1C
C COMMON C
14/14 XVDD/VDD33
+1.8VGS_+3VGS
Under GPU Near GPU
AD10 N C VDD33 G8
AD7 N C GM108 V D D 3 3 G9
+1.8VGS_+3VGS PLLVDD G10

K
0.1U_0201_10V6

K
0.1U_0201_10V6

K
1U_0402_6.3V6

M
4.7U_0402_6.3V6
3V3_AON VDD33
Near GPU Under GPU VDD33
G12 1 1 1 1
3V3_AON
F11
CV47

CV48

CV49

CV50 DIS@
1 2 F11 3 V 3 A UX_NC
22U_0603_6.3V6M

4.7U_0402_6.3V6M

LV10 N17S@
2 2 2 2
0.1U_0201_10V6K

DIS@

DIS@

DIS@
HCB1005KF-300T25_2P 1 1 V5 F E R M I_ R SVD 1_NC
CV396 N17S@

CV395 N17S@

1 V6 F E R M I_ R SVD 2_NC
CV394 N17S@

+1.8VGS_+3VGS_AON
2 2
2 Under GPU Near GPU
C ONFI GURABLE

POW ER CHANNELS
K
0.1U_0201_10V6

K
0.1U_0201_10V6

K
1U_0402_6.3V6

M
4.7U_0402_6.3V6
* nc on substrate
CV740

1 1 1 1
CV51

CV52

CV53 DIS@
G1 X PW R_G 1
G2 X PW R_G 2
G3 X PW R_G 3
2 2 2 2
DIS@

G4 X PW R_G 4
N17S@

DIS@

G5 X PW R_G 5
G6 X PW R_G 6
G7 X P W R_G 7

V1 X P W R_V1
V2 X P W R_V2
** XPWR pins are configurable.
These pins are not connected on the substrate.
D W1 X PW R_W 1 Therefore, XPW R pins can be assigned as needed, D
W2 X PW R_W 2
W3 X PW R_W 3
W4 to improve Top layer routing, power delivery.
X P W R_W 4

N16S-GT-S-A2_BGA595
@

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/10/27 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
NV(3/5)-POWER
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 23 o f 53
1 2 3 4 5
 1 2 3 4 5

+1.8VGS_+3VGS_AON

UV1N
COMMON GPIO +1.8VGS_+3VGS_AON
PLT_RST_VGA_HOLD#
DGPU_MAIN_EN RV18 1 2 10K_0201_5% DIS@
RV20 1 2 10K_0201_5% DIS@
8/14 MISC1 I2CS_SCL
I2 CS _ S CL
D9
D8
I2CS_SDA RV19 1 DIS@ 2 2.2K_0402_5%
RV21 1 DIS@ 2 2.2K_0402_5%
I2CS SMBUS: 0x96 PSI
VGA_AC_DET RV22 1 2 10K_0201_5% DIS@
RV23 1 2 10K_0201_5% DIS@
and 0x9E(Default)
I2 CS _ S DA

I2CC_S CL
A9
I2CC_S DA B9

GF117
GPU_EVENT#_D
E12 TH E R M D N RV26 1 GC6@ 2 10K_0201_5%
I2CB _S CL
C9
NC GPIO8_OVERT#
F12 TH E R M D P I2CB _S DA C8 RV27 1 DIS@ 2 100K_0201_5%
NC

GPU_JTAG_TCK
T231 TP@ GPU_JTAG_TMS AE5 J TA G _ TC K
AD6 J TA G _ TM S
T232 TP@ GPU_JTAG_TDI GPIO9_ALERT# RV28 1 2 10K_0201_5% DIS@
AE6 J TA G _ TD I
T242 TP@ GPU_JTAG_TDO AF6
J TA G _ TDO
T243 TP@ GPU_JTAG_TRST#
AG4 C6 GPU_VID0 To DGPU VR
GPU_JTAG_TRST# RV30 1
2 10K_0201_5% DIS@
J TA G _ TR S T# G P IO 0 GPIO0_GC6_FB_EN GPU_VID0 [50]
G P IO 1 B2 GPU_EVENT#_D RV29 1 2 0_0402_5% GC6_FB_EN [11,25]
G P IO 2 D6 DV1 DIS@ 2 1 RB751V-40_SOD323-2 GPU_EVENT# [9]
G P IO 3 C7 DGPU_MAIN_EN
G P IO 4 F9 DGPU_MAIN_EN [26]
G P IO 5
A3
G P IO 6
A4PSI
GK208 PSI [50]
GM108 G P IO 7 B6 GPIO8_OVERT#
OVE R T G P IO 8 A6 GPIO9_ALERT#
G P IO 9 F8 MEM_VREF DV2 DIS@ 2 1 RB751V-40_SOD323-2 GPU_PROHOT# [33,42]
A G P IO 10
C5 MEM_VREF [27] A
G P I O 1 1 E7 VGA_AC_DET
G P IO 12
D7
G P I O 1 3 B4

GM108 GK208 GF117 GF119 GPU_BUFRST

RV36 1 @ 2 10K_0201_5%
D5 RV2466 1 2 0_0402_5%
GPIO16 GPIO16 N C G P IO 16 PLT_RST_VGA_MON# [21]
GPIO20 GPIO20 N C G P IO 20
E6 PLT_RST_VGA_HOLD# N16S@ RV37 1 DIS@ 2 10K_0201_5%
[21] GPU_TESTMODE
C4 MEM_VREF
GPIO21 GPIO8 N C G P IO 21 PLT_RST_VGA_HOLD# [21]
RV38 1 DIS@ 2 100K_0201_5%
GPIO8 NC N C NC
E9 RV2467 1 2 0_0402_5%
@
PLT_RST_VGA_MON#
RV39 1 @ 2 10K_0201_5%

N16S-GT-S-A2_BGA595 GC6_FB_EN
RV40 1 GC6@ 2 10K_0201_5%
@

+1.8VGS_+3VGS_AON
UV1L
COMMON
Internal Thermal Sensor
10/14 MISC2

Link to PCH SML 1

2 G
PU @ PCH SIDE
E10 V M O N_IN0_NC
F10 V M O N_IN1_NC ROM _CS # D12
I2CS_SCL 6
1
ROM_SI EC_SMB_CK2 [8,33,35]

S
R O M _ S I B12 ROM_SO

D
R O M _ S O A12
ROM_SCLK
C12 QV147A
STRAP0 D1 S TR A P 0 ROM _S CLK
STRAP1 D2 S TRA P 1 S TR PJT138KA 2N SOT363-6

5
STRAP2 E4 S TRA P 2
NC F OR
DIS@

G
STRAP3 E3 S TRA P 3
GM 10 8

STRAP4 D3 S TRA P 4 VGS(Max) : 0.8~1.1 V

I2CS_SDA
4 3
EC_SMB_DA2 [8,33,35]

D
+1.8VGS_+3VGS_AON STRAP5 C1 S TR A P 5 _ N C
RV49 D11 GPU_BUFRST QV147B
B U F R S T#
0_0402_5% S TR PJT138KA 2N SOT363-6
1 @ 2 STRAPREF0 F6 M U L TI S TR A P _ R E F0 _ GN D PGOOD D10 DIS@
NC
GF117
GK208 GF117 GF119
1

GM108 GK208
RV58 F4 M U L TI S TR A P _ R E F1 _ GN D
GM108
40.2K_0402_1% NC

N16S@ F5 M U L TI S TR A P _ R E F2 _ GN D NC
2

N16S-GT-S-A2_BGA595
@

+3VS
B B
2

STRAP
10K_0201_5%
RV60
DV3 @
1

RB751V-40_SOD323-2
VGA_AC_DET 21 AC_PRESENT
10/13 - Strap Pin Modify for MX110/130 (Pop RV81, Un-Pop RV64)
AC_PRESENT [10,33]

NV Suggest
RV61 1 @ 2 0_0402_5%
+1.8VGS_+3VGS +1.8VGS_+3VGS_AON STRAP STRAP0 : PU 49.9K (50K)
STRAP[1:5] : Reserved
+1.8VGS_+3VGS_AON
2

RV473 RV474
0_0402_5% N16S@ 0_0402_5% N17S@

1
%
100K_0402_5

%
49.9K_0402_1
%
45.3K_0402_1

%
4.99K_0402_1

%
4.99K_0402_1

N16S@
RV444

RV384
%
10K_0402_1
@@@@ @
11

11

RV2470

RV389

RV382

RV51
1
%
14.7K_0402_1

%
4.99K_0402_1
%
4.99K_0402_1
N16S@

RV2468

2
RV2469

RV2471

@ @ STRAP0
STRAP1

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2

STRAP2
ROM_SI
ROM_SO STRAP3
STRAP4
ROM_SCLK
STRAP5
1

1
%
100K_0402_5

%
4.99K_0402_1
%
45.3K_0402_1

%
4.99K_0402_1

%
4.99K_0402_1

%
4.99K_0402_1
1

1
%
4.99K_0402_1

%
4.99K_0402_1

RV443

RV383
%
4.99K_0402_1

RV385

RV387

RV388

RV390
@ @ @ @ @ @
@

N16S@
RV65

RV381
RV64

2
2

N16S VRAM Res.

N17S-G0/G2 VRAM Strap R A M_ CF G S T RA P1 S T RA P0 N O TE N17S Strap

S T RA P2
RV51
RV388 N17_M2G@ RV383
N17_M2G@ N17_M2G@
0 x 9( LM L ) M2G
100K_0402_5% 100K_0402_5% R O M_ SI R O M_ SO R O M_ SC L K S T RA P3 S T RA P4 S T RA P5
100K_0402_5% RV390
N17_M2G@
100K_0402_5% RV2471
N17S@
RV388 RV51 RV384
Strap RV2469 RV2468 RV387 RV385 RV443
N17S@ N17S@ S RES 1/16W 100K +-5% 0402 N17S@ N17S@ N17S@
N17_H2G@ N17_H2G@ N17_H2G@ S RES 1/16W 100K +-5%0402 S RES 1/16W 100K +-5% 0402 S RES 1/16W 100K +-5% 0402 S RES 1/16W 100K +-5% 0402 S RES 1/16W 100K +-5% 0402
RV381
0xA (LMH) H2G 100K_0402_5% 100K_0402_5%
100K_0402_5%
N17S@
C
RV390 S RES 1/16W 100K +-5% 0402 C
N17_H2G@
100K_0402_5%

N17S-G1 VRAM Strap

R A M_ CF G S T RA P2 S T RA P1 S T RA P0

RV388 RV390 RV383

0 x 00 (L LL ) S2G @ @ @

0 x 01 (L L H)

0 x 02 (L H L)
D D
0 x 03 (L H H)

0 x 04 (H L L) M2G RV382
@
RV390
@
RV383
@
RV382 RV390 RV384
0 x 05 (H L H) H2G @ @ @

0 x 06 (H H L)

0x 07 ( HH H)

0x 08 ( LL M)

Securrriiittty Cllassiiifffiiicatttiiion Compalll SecrrretttDattta Compal Electronics, Inc.

2017///10///27 2019///04///09 Tiittllle
IIIssued Dattte Decipherrrii ed Dattte
THISI SHEET OF ENGINEERINGIII DRAWINGII ISITHE PROPRIETARYII PROPERTY OF COMPALLLELLLECTRONICS,,,II INC...IIAND CONTAN
I SI CONFIDENTII A I LLLI AND TRA DE SECRET N
I FI
NV(4/5)-GPIO/Strap
ORMATIOII N...THISISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DV ISI IOI N OF R&D DEPARTMENT EXCEPT AS AUTHORIZEDII BY Sizzze Documenttt Numberrr Revv
COMPALLLELLLECTRONICS,,,II INC...IINEITIHER THISI SHEET NOR THE N
I FIORMATIOIIN T
IICONTAINSII
0..2
MAY BE USED BY OR DS I CLLLIOS E D TO ANY THIRDII PARTY WITIHOUT PRO I IR WRITITE N CONSENT OF COMPALLLELLLECTRONICS,,,II INC...II LA-H082P
Dattte:::Mondayyy,,Occcttoberrr22,,,2018 Sheettt 24 o fff53
1 2 3 4 5
 1 2 3 4 5

For GC6
+1.8VGS_+3VGS_AON

Normal:1.8V
GC6:1.3V
UV1B
COMMON CV54 @
1
1.8V OR GATE SA000099200 (Main) : VIH(min) = 0.8V
SA00008I400 (2nd) : VIH(min) = 0.8V
2/14 F BA N17S@ 0.1U_0201_10V6K
[27] FB_A_D[0..31] FB_A_D0 E18 FBA_D0 FB_CLAMP F3 RV2456 1 2 10K_0402_5%
FB_A_D1 NC 2
F18 FBA_D1 UV20 @

5
FB_A_D2 E16 FBA_D2 74AUP1G32GW_TSSOP5
A GF119 2 A
FB_A_D3 F17 FBA_D3 SA000054300 DV6 GC6@
FB_A_D4 [11,24] GC6_FB_EN A 4 GC6_FB_EN

G Vcc
D20 FBA_D4 2
FB_A_D5 1 Y 1.35V_PWR_EN [51] 1.35V_PWR_EN
D21 FBA_D5 1
FB_A_D6 [21,26,50] DGPU_PWROK B DGPU_PWROK
F20 FBA_D6 3
FB_A_D7 E21 FBA_D7

1
FB_A_D8 E15 FBA_D8 BAV70W_SOT323-3
FB_A_D9 D15 FBA_D9 RV2462
FB_A_D10 F15 FBA_D10 16.5K_0402_5%
FB_A_D11 F13 FBA_D11 GC6@
FB_A_D12 C13 FBA_D12

2
FB_A_D13 B13 FBA_D13
FB_A_D14 E13 FBA_D14 RV68 1 2 0_0402_5%
FB_A_D15 D13 FBA_D15 NOGC6@
FB_A_D16 B15 FBA_D16
FB_A_D17 C16 FBA_D17 Stuff RV201 if not support GC6
FB_A_D18 A13 FBA_D18
FB_A_D19 A15 FBA_D19
FB_A_D20 B18 FBA_D20
FB_A_D21 A18 FBA_D21
FB_A_D22 A19 FBA_D22
FB_A_D23
FB_A_D24
C19 FBA_D23
B24 FBA_D24 From DG-07158-001_v05_secured(NVDIA Spec)
FB_A_D25 C23 FBA_D25
FB_A_D26 A25 FBA_D26
FB_A_D27 A24 FBA_D27
FB_A_D28 A21 FBA_D28
FB_A_D29 B21 FBA_D29
FB_A_D30 FB_A_CMD[0..31] [27]
C20 FBA_D30
FB_A_D31 C21 FBA_D31
[27] FB_A_D[32..63] FB_A_D32 R22 FBA_D32
FB_A_D33 R24 FBA_D33 FBA_CMD0 C27 FB_A_CMD0
FB_A_D34 T22 FBA_D34 FBA_CMD1 C26 FB_A_CMD1
FB_A_D35 R23 FBA_D35 FBA_CMD2 E24 FB_A_CMD2
FB_A_D36 N25 FBA_D36 FBA_CMD3 F24 FB_A_CMD3
FB_A_D37 N26 FBA_D37 FBA_CMD4 D27 FB_A_CMD4
FB_A_D38 N23 FBA_D38 FBA_CMD5 D26 FB_A_CMD5
FB_A_D39 N24 FBA_D39 FBA_CMD6 F25 FB_A_CMD6
B FB_A_D40 V23 FBA_D40 FBA_CMD7 F26 FB_A_CMD7 B
FB_A_D41 V22 FBA_D41 FBA_CMD8 F23 FB_A_CMD8 +1.35VS_VRAM
FB_A_D42 T23 FBA_D42 FBA_CMD9 G22 FB_A_CMD9
FB_A_D43 U22 FBA_D43 FBA_CMD10 G23 FB_A_CMD10
FB_A_D44 Y24 FBA_D44 G24 FB_A_CMD11 FBA_CKE_L FB_A_CMD14 RV69 1 DIS@ 2 10K_0201_1%
FBA_CMD11
FB_A_D45 AA24 FBA_D45 FBA_CMD12 F27 FB_A_CMD12 FBA_CKE_H FB_A_CMD30 RV70 1 DIS@ 2 10K_0201_1%
FB_A_D46 Y22 FBA_D46 FBA_CMD13 G25 FB_A_CMD13
FB_A_D47 AA23 FBA_D47 FBA_CMD14 G27 FB_A_CMD14
FB_A_D48 AD27 FBA_D48 G26 FB_A_CMD15 FBA_RST_L FB_A_CMD13 RV71 1 DIS@ 2 10K_0201_1%
FBA_CMD15
FB_A_D49 AB25 FBA_D49 FBA_CMD16 M24 FB_A_CMD16 FBA_RST_H FB_A_CMD29 RV72 1 DIS@ 2 10K_0201_1%
FB_A_D50 AD26 FBA_D50 FBA_CMD17 M23 FB_A_CMD17
FB_A_D51 AC25 FBA_D51 FBA_CMD18 K24 FB_A_CMD18
FB_A_D52 AA27 FBA_D52 FBA_CMD19 K23 FB_A_CMD19
FB_A_D53
FB_A_D54
AA26 FBA_D53
W26 FBA_D54
FBA_CMD20
FBA_CMD21
M27
M26
FB_A_CMD20
FB_A_CMD21 GDDR5 design
FB_A_D55 Y25 FBA_D55 M25 FB_A_CMD22

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FBA_CMD22
FB_A_D56 R26 FBA_D56 FBA_CMD23 K26 FB_A_CMD23
FB_A_D57 T25 FBA_D57 FBA_CMD24 K22 FB_A_CMD24
FB_A_D58 N27 FBA_D58 FBA_CMD25 J23 FB_A_CMD25
FB_A_D59 R27 FBA_D59 FBA_CMD26 J25 FB_A_CMD26
FB_A_D60 V26 FBA_D60 FBA_CMD27 J24 FB_A_CMD27
FB_A_D61 V27 FBA_D61 FBA_CMD28 K27 FB_A_CMD28
FB_A_D62 W27 FBA_D62 FBA_CMD29 K25 FB_A_CMD29
FB_A_D63 W25 FBA_D63 FBA_CMD30 J27 FB_A_CMD30
FBA_CMD31 J26 FB_A_CMD31

[27] FB_A_DBI[3..0] FB_A_DBI0 D19 FBA_DQM0

FB_A_DBI1 D14 FBA_DQM1 FBVDDQ_GPU
FB_A_DBI2 C17 FBA_DQM2
FB_A_DBI3 GF117/GF119
C22 FBA_DQM3 +1.35VS_VRAM
[27] FB_A_DBI[7..4] FB_A_DBI4 G K208
P24 FBA_DQM4
FB_A_DBI5 W24 FBA_DQM5
NC
FBA_CMD32 B19 1.35V
FB_A_DBI6 AA25 FBA_DQM6
FB_A_DBI7 U25 FBA_DQM7 FBA_CMD34 F22 RV73 1 @ 2 60.4_0402_1%
F B A_ D EB UG 0
F B A_ D EB UG 1 FBA_CMD35 J22 RV74 1 @ 2 60.4_0402_1%
[27] FB_A_EDC[3..0] FB_A_EDC0 E19 FBA_DQS_WP0
FB_A_EDC1 C15 FBA_DQS_WP1
C FB_A_EDC2 B16 FBA_DQS_WP2 FBA_CLK0 D24 FB_A_CLK0 C
FB_A_EDC3 FB_A_CLK#0 FB_A_CLK0 [27]
B22 FBA_DQS_WP3 FBA_CLK0# D25
[27] FB_A_EDC[7..4] FB_A_EDC4 FB_A_CLK1 FB_A_CLK#0 [27]
R25 FBA_DQS_WP4 FBA_CLK1 N22
FB_A_EDC5 FB_A_CLK#1 FB_A_CLK1 [27]
W23 FBA_DQS_WP5 FBA_CLK1# M22
FB_A_EDC6 AB26 FBA_DQS_WP6 FB_A_CLK#1 [27]
FB_A_EDC7 T26 FBA_DQS_WP7

F19 FBA_W CK01 D18 FB_A_WCK0

FBA_DQS_RN0 FB_A_WCK0 [27]
C14 FBA_DQS_RN1 FBA_W CK01# C18 FB_A_WCK#0
FB_A_WCK1 FB_A_WCK#0 [27]
A16 FBA_DQS_RN2 FBA_W CK23 D17
FB_A_WCK#1 FB_A_WCK1 [27]
A22 FBA_DQS_RN3 FBA_W CK23# D16
P25 FBA_W CK45 T24 FB_A_WCK2 FB_A_WCK#1 [27]
FBA_DQS_RN4
W22 FBA_W CK45# U24 FB_A_WCK#2 FB_A_WCK2 [27]
FBA_DQS_RN5
AB27 FBA_W CK67 V24 FB_A_WCK3 FB_A_WCK#2 [27]
FBA_DQS_RN6
T27 FBA_W CK67# V25 FB_A_WCK#3 FB_A_WCK3 [27]
FBA_DQS_RN7
FB_A_WCK#3 [27]

GF119
FB_PLLAVDD F16
PLLAVDD PLLAVDD +1.0VS_DGPU
NC
FB_PLLAVDD P22 RV2464
Close to P22 Close to F16 1.0V DIS@ N16S@
F B_ PL L AVDD FB_DLLAVDD H22 1 2 HCB10015KF-300T252_2P
LV3
0.1U_0201_10V K X5R
CV55 DIS@

0.1U_0201_10V K X5R
CV57 DIS@

SM01000NV00 0_0805_5%
0.1U_0201_10V K X5R
CV56 DIS@

M
22U_0603_6.3V6
CV58 DIS@

GF117
1 2 1 1
+1.8VGS_+3VGS

For VRAM DEBUG using 2 1 2 2 RV2465

N17S@
FB_VREF D23 FB_VREF_PROBE 1 2
T2402 @
Close to H22 Near GPU 0_0805_5%
N16S-GT-S-A2_BGA595
@
0.1U_0201_10V K X5R
CV793 N17S@

0.1U_0201_10V K X5R
CV794 N17S@

D D
1 2

2 1

Close to H22
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/10/27 Decipherii ed Dae
t 2019/04/09 Tiiitttllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
NV(5/5)-MEMORY FBA
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Dattte::: Monday,,, Octttober 22,,, 2018 Sheettt 25 off 53
1 2 3 4 5
 5 4 3 2 1

+1.8VS

RV66 1 2 N17S@
+3VS to +3VS_DGPU +5VALW
+3VS
0_0603_5%
+1.8VGS_+3VGS
QV3 DIS@ ME2301DC-
G_SOT23-3

2
RV67 1 2 N16S@ +1.8VGS_+3VSGS_S
RV75

D
3 1
47K_0402_5% 0_0402_5%

1
DIS@
RV76

G
1

2
22_0603_1%
DGPU_MAIN_EN# 1 DIS@ 2 DGPU_MAIN_EN#_GATE RV77 DIS@
4.7K_0201_5%

2
D D
RV81
0_0402_5% D 1 1 2 1 1

1
DIS@
DGPU_MAIN_EN 1

6
2 2 D

1U_0402_6.3V6K
CV61 DIS@

0.1U_0201_10V K X5R
CV736 DIS@

0.1U_0201_10V K X5R
CV737 DIS@
0.1U_0201_10V K X5R
CV59 DIS@

4.7U_0402_6.3V6M
CV60 DIS@
[24] DGPU_MAIN_EN QV148 DGPU_MAIN_EN#
G BSS138W-7-F_SOT323-3 2
S 2 2 1 2 2 G

3
QV6A

1U_0402_6.3V6K
CV62 @
1
S 2N7002KDW_SOT363-6

1
DIS@
2

+5VALW +1.0VS_DGPU

+3VS to +3VS_DGPU_AON

1
+5VALW +1.8VGS_+3VGS_AON

100K_0402_1%
RV78 DIS@

22_0603_1%
RV79 DIS@
QV7 DIS@ ME2301DC-
G_SOT23-3
2

2
+1.8VGS_+3VSGS_S

D
3 1

6 2
RV83
47K_0402_5% D QV5A
1.0VS_DGPU_EN#

1
DIS@ 2 2N7002KDW_SOT363-6

G
1

2
G

470_0603_5%
RV84 @
RV85 DIS@ DIS@
DGPU_PW R_EN# 10K_0201_5% DGPU_PWR_EN#_GATE

3
1 2 D QV5B S
C C

1
5 2N7002KDW_SOT363-6
[26,46] 1.0VS_DGPU_EN G
DIS@

32
RV86 1 1 2 1 1
D S
0_0402_5% D

4
DGPU_PW R_EN#
1

DIS@ 5

0.1U_0201_10V K X5R
CV63 DIS@

4.7U_0402_6.3V6M
CV64 DIS@

1U_0402_6.3V6K
CV65 DIS@

0.1U_0201_10V K X5R
CV739 N17S@
CV738 DIS@
DGPU_PWR_EN 1 2 2 QV149 G

0.1U_0201_10V K X5R
[11,26,33] DGPU_PWR_EN 2 2 1 2 2
G BSS138W-7-F_SOT323-3
S S QV6B
3

4
2N7002KDW_SOT363-6
DIS@
+3VALW +3VS
1U_0402_6.3V6K
CV66 @

+3VS
2

1
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RV106 DIS@ RV108 DIS@ UV10 DIS@
100K_0402_5% 10K_0402_5% NL17SZ08DFT2G_SC70-5

5
+1.8VGS_+3VGS_AON +3VS Output 3.3V

2
1.8VSDGPU_MAIN
DV4 DIS@ RB751S- SA00009WE00 (Main) : VIH(min) = 1.2V
1

GND VCC
IN B GPUCORE_EN 40_SOD523-2
4 1 2
OUT Y VGA_CORE_EN [50]
2

3
2
5
D
IN A
RG1 RG82 G

6
10K_0201_5% 10K_0201_5% S RV105 DIS@ 1
DGPU_MAIN_EN 2
D
N16S@ N17S@
G
40.2K_0402_1%

3
4
S
1 2
1

1 QV152B DIS@ QV152A DIS@ CV197 DIS@

1
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 2 0.1U_0201_10V6K

Output 2.6V
DGPU_PW ROK
DIS@ DV5 DIS@ RB751S- SA0000ACG00(Main) : VIH(min) = 1.6V
DG1 1 2 RB751V-40_SOD323-2 40 SOD-523
[21,25,50] DGPU_PWROK
1 2 1.0VS_DGPU_EN [26,46]
[11,26,33] DGPU_PWR_EN
0_0402_5% RV103 DIS@
+1.35VGS_PGOOD

2
B RG2 1 2 56K_0402_1% 1 B
[51] +1.35VGS_PGOOD GPU_ALL_PGOOD [11]
RV256 @ 1 2
100K_0402_5%
CV196 DIS@
2 0.1U_0201_10V6K

1
A A

Securiiity Clllassiiifiiicatiiion Compalll Secret Data Compal Electronics, Inc.

Issued Date 2017/10/27 Deciiiphered Date 2019/04/09 Tiitttlle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
DGPU_DC/DC Interface
Siiize Documenttt Numberrr Rev
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIORWRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... LA-H082P 0..2

Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 26 o ff53

5 4 3 2 1
 5 4 3 2 1

VRAM Memory Partition A UV22 MF=0

UV21 MF=0 MF=0 MF=1 MF=1 MF=0

MF=0 MF=1 MF=1 MF=0 FB_A_D32

A4
FB_A_EDC4 DQ 24 DQ0 A2 FB_A_D33
C2
FB_A_D0 FB_A_EDC5 C13 EDC0 EDC3 DQ 25 DQ1 B4 FB_A_D34
A4
FB_A_EDC0 DQ 24 DQ0 FB_A_D1 FB_A_EDC6 R13 EDC1 EDC2 DQ 26 DQ2 FB_A_D35
FB_A_EDC1
C2
EDC3 DQ 25
A2
EDC1 DQ 27
B2 BYTE4
C13 EDC0 DQ1 B4 FB_A_D2 FB_A_EDC7 R2 EDC2 DQ3 E4 FB_A_D36
FB_A_EDC2 R13 EDC1 EDC2 DQ 26 DQ2 B2 FB_A_D3 EDC3 EDC0 DQ 28 DQ4 E2 FB_A_D37
FB_A_EDC3 R2 EDC2 EDC1 DQ 27 DQ3 FB_A_D4 DQ 29 DQ5 FB_A_D38
EDC3 EDC0 DQ 28 DQ4
E4
FB_A_D5
BYTE0 DQ 30 DQ6
F4
FB_A_D39
E2 D2 F2
DQ 29 DQ5 F4 FB_A_D6 [25] FB_A_DBI4 D13 DBI0# DBI3# DQ 31 DQ7 A11 FB_A_D40
DQ 30 DQ6 [25] FB_A_DBI5 DBI2# DQ 16
D2 F2 FB_A_D7 P1 3 DBI1# DQ8 A13 FB_A_D41
[25] FB_A_DBI0 DBI3# DQ 31 [25] FB_A_DBI6 DBI1# DQ 17
D13 DBI0# DQ7 A11 FB_A_D8 P2 DBI2# DQ9 B1 1 FB_A_D42
[25] FB_A_DBI1 DBI2# DQ 16 [25] FB_A_DBI7 DBI0# DQ 18
D P1 3 DBI1# DQ8 A13 FB_A_D9 DBI3# DQ1 0 B1 3 FB_A_D43
D
[25] FB_A_DBI2 DBI1# DQ 17 FB_A_CLK1 DQ 19
P2 DBI2# DQ9 B1 1 FB_A_D10 J12 DQ1 1 E1 1 FB_A_D44
BYTE5
[25] FB_A_DBI3 DBI3# DBI0# DQ 18 DQ1 0 FB_A_D11 [25] FB_A_CLK1 FB_A_CLK#1 DQ 20 DQ1 2 FB_A_D45
FB_A_CLK0 DQ 19 DQ1 1
B1 3 BYTE1 [25] FB_A_CLK#1 J11 CK
DQ 21
E1 3
J12 E1 1 FB_A_D12 FB_A_CMD30 J 3 CK# DQ1 3 F11 FB_A_D46
[25] FB_A_CLK0 FB_A_CLK#0 DQ 20 DQ1 2 FB_A_D13 CKE# DQ 22 DQ1 4 FB_A_D47
J11 CK E1 3 F13
[25] FB_A_CLK#0 DQ 21 DQ 23
FB_A_CMD14 J 3 CK# DQ1 3 F11 FB_A_D14 DQ1 5 U11 FB_A_D48
CKE# DQ 22 DQ1 4 F13 FB_A_D15 F B_A_CMD18 DQ8 DQ1 6 U13 FB_A_D49
H11
DQ 23 DQ1 5 U11 FB_A_D16 FB_A_CMD20 K1 0 BA0/A2 BA2/A4 DQ9 DQ1 7 T11 FB_A_D50
FB_A_CMD2 DQ8 DQ1 6 U13 FB_A_D17 FB_A_CMD19 K1 1 BA1/A5 BA3/A3 DQ 10 DQ1 8 T13 FB_A_D51
H11
FB_A_CMD4 K1 0 BA0/A2 BA2/A4 DQ9 DQ1 7 FB_A_D18 FB_A_CMD17 H10 BA2/A4 BA0/A2 DQ 11 DQ1 9 FB_A_D52
BA3/A3 DQ 10
T11
BA1/A5 DQ 12
N11 BYTE6
FB_A_CMD3 K1 1 BA1/A5 DQ1 8 T13 FB_A_D19
BYTE2 BA3/A3 DQ2 0 N13 FB_A_D53
FB_A_CMD1 H10 BA2/A4 BA0/A2 DQ 11 DQ1 9 N11 FB_A_D20 DQ 13 DQ2 1 M11 FB_A_D54
BA3/A3 BA1/A5 DQ 12 DQ2 0 N13 FB_A_D21 FB_A_CMD22 DQ 14 DQ2 2 M13 FB_A_D55
K4
DQ 13 DQ2 1 M11 FB_A_D22 FB_A_CMD27 H5 A8/A7 A10/A0 DQ 15 DQ2 3 U4 FB_A_D56
FB_A_CMD6 DQ 14 DQ2 2 M13 FB_A_D23 FB_A_CMD26 H4 A9/A1 A11/A6 DQ0 DQ2 4 U2 FB_A_D57
K4
FB_A_CMD11 H5 A8/A7 A10/A0 DQ 15 DQ2 3 U4 FB_A_D24 FB_A_CMD23 K5 A10/A0 A8/A7 DQ1 DQ2 5 T4 FB_A_D58
FB_A_CMD10 H4 A9/A1 A11/A6 DQ0 DQ2 4 U2 FB_A_D25 FB_A_CMD25 J 5 A11/A6 A9/A1 DQ2 DQ2 6 T2 FB_A_D59
FB_A_CMD7 K5 A10/A0 A8/A7 DQ1 DQ2 5 FB_A_D26 A12/RFU/NC DQ3 DQ2 7 FB_A_D60
A9/A1 DQ2
T4
DQ4
N4 BYTE7
FB_A_CMD9 J 5 A11/A6 DQ2 6 T2 FB_A_D27
BYTE3 A5 DQ2 8 N2 FB_A_D61
A12/RFU/NC DQ3 DQ2 7 N4 FB_A_D28 U5 VPP/ NC DQ5 DQ2 9 M4 FB_A_D62
DQ4 DQ2 8 N2 FB_A_D29 VPP/NC DQ6 DQ3 0 M2 FB_A_D63
A5
U5 VPP/ NC DQ5 DQ2 9 M4 FB_A_D30 DQ7 DQ 31
VPP/NC DQ6 DQ3 0 M2 FB_A_D31 +1.35VS_VRAM
RV88 DIS@ 2 1 1K_0402_1% J1
DQ7 DQ 31 RV90 DIS@ 2 1 1K_0402_1% J10 MF
RV87 DIS@ 2 1 1K_0402_1% J1 +1.35VS_VRAM RV92 DIS@ 2 1 121_0402_1% J13 SEN B1
ZQ VDDQ
RV89 DIS@ 2 1 1K_0402_1% J10 MF D1
J13 SEN VDDQ
RV91 DIS@ 2 1 121_0402_1% B1 F1
ZQ VDDQ FB_A_CMD24 VDDQ
D1 J4 M1
VDDQ FB_A_CMD28 G3 ABI# VDDQ
F1 P1
FB_A_CMD8 VDDQ FB_A_CMD16 G1 2 RAS# CAS# VDDQ
J4 M1 T1
FB_A_CMD12 G3 ABI# VDDQ FB_A_CMD31 L3 CS# W E# VDDQ
P1 G2
FB_A_CMD0 G1 2 RAS# CAS# VDDQ FB_A_CMD21 L12 CAS# RAS# VDDQ
T1 L2
FB_A_CMD15 L3 CS# W E# VDDQ W E# CS# VDDQ
G2 B3
FB_A_CMD5 L12 CAS# RAS# VDDQ VDDQ
L2 D3
W E# CS# VDDQ VDDQ
B3 F3
VDDQ FB_A_W CK#2 VDDQ
D3 D5 H3
VDDQ [25] FB_A_WCK#2 FB_A_WCK2 D4 W CK01# W CK23# VDDQ
F3 K3
FB_A_W CK#0 VDDQ [25] FB_A_WCK2 W CK01 W CK23 VDDQ
D5 H3 M3
[25] FB_A_WCK#0 FB_A_WCK0 D4 W CK01# W CK23# VDDQ FB_A_W CK#3 VDDQ
K3 P5 P3
[25] FB_A_WCK0 W CK01 W CK23 VDDQ [25] FB_A_WCK#3 FB_A_WCK3 W CK01# VDDQ
M3 P4 W CK23 # T3
FB_A_W CK#1 VDDQ [25] FB_A_WCK3 W CK23 W CK01 VDDQ
P5 P3 E5
[25] FB_A_WCK#1 FB_A_WCK1 P4 W CK23 # W CK01# VDDQ VDDQ
T3 N5
FB_A_CMD[0..15] [25] FB_A_WCK1 W CK23 W CK01 VDDQ VDDQ
E5 A10 E1 0
[25] FB_A_CMD[0..15] VDDQ U10 VREF D VDDQ
N5 N10
FB_A_CMD[16..31] VDDQ +FBA_VREFC0 J14 VREF D VDDQ
A10 E1 0 B1 2
C [25] FB_A_CMD[16..31] U10 VREF D VDDQ VREF C VDDQ C
N10 D12
+FBA_VREFC0 J14 VREF D VDDQ VDDQ
B1 2 F12
FB_A_D[0..63] VREF C VDDQ VDDQ
D12 H12
[25] FB_A_D[0..63] VDDQ FB_A_CMD29 VDDQ
F12 J2 K1 2
FB_A_EDC[7..0] VDDQ RESET# VDDQ
H12 M12
[25] FB_A_EDC[7..0] FB_A_CMD13 VDDQ VDDQ
J2 K1 2 P1 2
RESET# VDDQ VDDQ
M12 T12
VDDQ VDDQ
P1 2 G1 3
VDDQ VDDQ
T12 H1 L13
VDDQ VSS VDDQ
G1 3 K1 B1 4
VDDQ VSS VDDQ
H1 L13 B5 D14
VSS VDDQ VSS VDDQ
K1 B1 4 G5 F14
RV93 DIS@ RV94 DIS@ VSS VDDQ VSS VDDQ
B5 D14 L5 M14
40.2_0402_1% 40.2_0402_1% VSS VDDQ VSS VDDQ
G5 F14 T5 P1 4
FB_A_CLK0 FB_A_CLK#0 VSS VDDQ VSS VDDQ
1 2 1 2 L5 M14 B10 T14
VSS VDDQ VSS VDDQ
T5 P1 4 D10
VSS VDDQ VSS
1 B10 T14 G 10
VSS VDDQ VSS
Near to UV6 CV67 DIS@
0.01U_0402_16V7K
D10
G 10
VSS
L10
P10
VSS VSSQ
A1
C1

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VSS VSS VSSQ
L10 A1 T10 E1
2 VSS VSSQ VSS VSSQ
P10 C1 H14 N1
VSS VSSQ VSS VSSQ
T10 E1 K14 R1
VSS VSSQ +1.35VS_VRAM VSS VSSQ
H14 N1 U1
VSS VSSQ VSSQ
K14 R1 H2
+1.35VS_VRAM VSS VSSQ VSSQ
U1 G1 K2
VSSQ VDD VSSQ
H2 L1 A3
RV95 DIS@ RV96 DIS@ VSSQ VDD VSSQ
G1 K2 G4 C3
40.2_0402_1% 40.2_0402_1% VDD VSSQ VDD VSSQ
L1 A3 L4 E3
FB_A_CLK1 FB_A_CLK#1 VDD VSSQ VDD VSSQ
1 2 1 2 G4 C3 C5 N3
VDD VSSQ VDD VSSQ
L4 E3 R5 R3
VDD VSSQ VDD VSSQ
1 C5 N3 C10 U3
VDD VSSQ VDD VSSQ
Near to UV7 CV68 DIS@
0.01U_0402_16V7K
R5
C10
VDD
VDD
VSSQ
VSSQ
R3
U3
R10
D11
VDD
VDD
VSSQ
VSSQ
C4
R4
R10 C4 G 11 F5
2 VDD VSSQ VDD VSSQ
D11 R4 L11 M5
VDD VSSQ VDD VSSQ
G 11 F5 P11 F10
VDD VSSQ VDD VSSQ
L11 M5 G 14 M10
VDD VSSQ VDD VSSQ
P11 F10 L14 C11
VDD VSSQ VDD VSSQ
G 14 M10 R11
VDD VSSQ VSSQ
L14 C11 A12
VDD VSSQ VSSQ
R11 C12
VSSQ VSSQ
A12 E1 2
VSSQ VSSQ
C12 N12
VSSQ VSSQ
E1 2 R12
VSSQ VSSQ
B N12 170-B AL L U12 B
VSSQ VSSQ
R12 H13
VSSQ VSSQ K1 3
170-B AL L U12 SGRAM GDDR5
+1.35VS_VRAM VSSQ VSSQ
H13 A14
VSSQ K1 3 VSSQ
SGRAM GDDR5 C14
VSSQ VSSQ
A14 E1 4
VSSQ VSSQ
1

C14 N14
RV97 DIS@ VSSQ VSSQ R14
E1 4
549_0402_1% VSSQ VSSQ U14
N14
VSSQ VSSQ
R14
VSSQ
U14 @ K4G80325FB-HC03_FBGA170~D
VSSQ
2

RV98 1 DIS@ 2 931_0402_1% +FBA_VREFC0 @ K4G80325FB-HC03_FBGA170~D

W=16mils
D
1

1.33K_0402_1%
RV99 DIS@

820P_0402_25V7
CV85 DIS@

820P_0402_25V7
CV86 DIS@

1 1
2 QV8 DIS@ +1.35VS_VRAM Near VRAM Near ball +1.35VS_VRAM Near VRAM Near ball
[24] MEM_VREF G L2N7002WT1G_SC-70-3
S
3

2 2
2

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 2 1 1 1 1 1 1 2 2 1 1 1 1 1 1
CV69 DIS@

CV70 DIS@

CV77 DIS@

CV78 DIS@
DIS@ CV71

DIS@ CV72

DIS@ CV73

DIS@ CV74

DIS@ CV75

DIS@ CV76

DIS@ CV79

DIS@ CV80

DIS@ CV81

DIS@ CV82

DIS@ CV83

DIS@ CV84
1 1 2 2 2 2 2 2 1 1 2 2 2 2 2 2
Place near pin J14 of each vram

+1.35VS_VRAM Near ball +1.35VS_VRAM Near ball

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
CV87 DIS@

CV88 DIS@

CV89 DIS@

CV90 DIS@

CV91 DIS@

CV92 DIS@

CV93 DIS@

CV94 DIS@

CV95 DIS@

CV96 DIS@

CV97 DIS@

CV98 DIS@

CV99 DIS@

CV100 DIS@

CV101 DIS@

CV102 DIS@

CV103 DIS@

CV104 DIS@

CV105 DIS@

CV106 DIS@
2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1

2 1
A A

Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

IIIssued Dattte 2018/04/09//// Deciphered Dattte 2019///04///09 Tiitttlle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE
N16P_GDDR5_A
Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D DEPARTMENT EXCEPT
0..2
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC... LA-H082P
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 27 o ff53
5 4 3 2 1
 5 4 3 2 1

LCD POWER SWITCH CAMERA POWER CIRCUIT

+3VS +LCDVDD_CONN
+3VS +3VS_CMOS
W=60mils U5 W=60mils
5 1 +LCDVDD R2 1 2 0_0805_5%
IN OUT
2 1
D GND D
1
C4 4 3 C3 W=20mils W=20mils
1U_0201_6.3V6M EN OC 4.7U_0402_6.3V6M R3 1 @ 2 0_0603_5%
SE00000UC00 EM5203AJ-20 SOT23 5P 2
1 1
2

SA00008R900 C6 @
C5 10U_0402_6.3V6M
[6] PCH_ENVDD
0.1U_0201_10V K X5R SE00000UD00
2 2

1
R4
100K_0201_5%

DISPLAY OFF HOT PLUG DETECT

C C

R5 1 2 0_0402_5% DISPOFF# R6 1 2 0_0402_5% EDP_HPD_R

Through EC [33] BKOFF# [6] EDP_HPD

2
2
R8
R7 100K_0201_5%
100K_0201_5%

1
1
eDP CONNECTOR www.teknisi-indonesia.com
B+ +LEDVDD

Touch Screen POWER CIRCUIT

JEDP1
R9 1 2 0_0805_5% 1
2 1
1 2
3
4 3
C7 @
5 4
4.7U_0603_25V6K [6] INVPWM
2 6 5
DISPOFF#
B EDP_HPD_R 7 6 B
W=60mils 8 7
+LCDVDD_CONN 8
9
C8 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
[6] EDP_AUXN EDP_AUXP_C 10
C9 1 2 0.1U_0201_10V K X5R 11
[6] EDP_AUXP 11
12
C10 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 13 12
eDP [6] EDP_TXP0
C11 1 2 0.1U_0201_10V K X5R EDP_TXN0_C 14 13 +3VS +3VS_TS
[6] EDP_TXN0 14
15
C12 1 2 0.1U_0201_10V K X5R EDP_TXP1_C 16 15
[6] EDP_TXP1 EDP_TXN1_C 17 16
C13 1 2 0.1U_0201_10V K X5R
[6] EDP_TXN1 17
18
C232 1 2 0.1U_0201_10V K X5R EDP_TXP2_C 19 18
[6] EDP_TXP2 EDP_TXN2_C 20 19
C233 1 2 0.1U_0201_10V K X5R W=20mils @ W=20mils
[6] EDP_TXN2 20
21 R264 1 2 0_0805_5%
C234 1 2 0.1U_0201_10V K X5R EDP_TXP3_C 22 21
[6] EDP_TXP3 EDP_TXN3_C 22 1 1
C235 1 2 0.1U_0201_10V K X5R 23 TS@ C231 @
[6] EDP_TXN3 23
24 C230 10U_0402_6.3V6M
[6] TS_I2C_RST# 24
25 0.1U_0201_10V K X5R SE00000UD00
[11] TS_INT# USB20_N4_C 25 2 2
RTOUCH1 1 C340@ 2 0_0402_5% 26
[11] I2C_1_SDA USB20_P4_C 26
RTOUCH2 1 C340@ 2 0_0402_5% 27
Touch Screen 11 I2C_1_SCL
28 27
12 USB20_N4 RTOUCH3 1 S540@ 2 0_0402_5% +3VS_TS
RTOUCH4 1 S540@ 2 0_0402_5% TS_DISABLE# 29 28
[12] USB20_P4 USB20_N6 29
[33] TS_DISABLE# 30
[12] USB20_N6 USB20_P6 31 30
Camera [12] USB20_P6
32 31
W=20mils +3VS_CMOS 33 32
[33,35] EC_SMB_DA4 34 33
G-Sensor [33,35] EC_SMB_CK4
35 34
[33] TAB_SW# 35
36 41
+3VALW 36 GND 42
37
+3VS 37 GND 43
DMIC [32] DMIC_CLK
DMIC_CLK 38
DMIC_DAT 39 38 GND 44
[32] DMIC_DAT 39 GND 45
40
40 GND
A CVILU_CVS3402M1RM-NH A
ME@
SP01002FV00
DT6
USB20_N6 3 6 DMIC_DAT
I/O2 I/O4

2 5
GND VDD
Securiiity Clllassiiifiiicatiiion Compal Secret Data ComeDpPal/EClaemcterroan/icMsI,CInc.
DMIC_CLK USB20_P6 Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle
1 4
I/O1 I/O3
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
CEST236LC5VU-M SOT23-6 TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
SC300006000 DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custttom 0..2
@ESD@ MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 28 o f 53
5 4 3 2 1
 5 4 3 2 1

HDMI +5VS +5V_Display

UH1

3
W=40mils
OUT
+1.2V_HDMI 1
Near Pin20 Near Pin12 Near Pin40 Near Pin31 Near Pin19 IN 1
CH5
1 2
@ 0.1U_0201_10V K X5R
D GND D
+1.2V +1.2V_HDMI CH6
0.1U_0201_10V KX5R 2
2

0.1U_0201_10V6K
CLS226 LS@
S IC AP2330W-7 SC59 3P PW R SW
K
0.01U_0402_16V7
CLS228 LS@

K
0.01U_0402_16V7
CLS225 LS@

K
0.1U_0201_10V6
CLS229 LS@

K
0.1U_0201_10V6
CLS222 LS@

K
0.1U_0201_10V6
CLS223 LS@
W = 40mils
2 2 2 2 2 2 SA00004ZA00
RLS3 1 @ 2 0_0603_5%

1 1 1 1 1 1 +3VS

Near Pin11 Near Pin37

ULS1 LS@
19 11
20 VDDTA VDD33 37
31 VDDTX VDD33
12 VDDTX

K
0.01U_0402_16V7
CLS224 LS@

K
0.1U_0201_10V6
CLS227 LS@
40 VDDRX 30 HDMI_RD_TX_P2 +5V_Display
VDDRX OUT_D2p 29 HDMI_RD_TX_N2 2 2
Near ULS1 LS@ OUT_D2n
CLS9 1 2 0.1U_0201_10V6K HDMI_TX_P2 1 27 HDMI_RD_TX_P1 HDMI_CTRL_DAT RH252 2 1 2.2K_0402_5%
[6] CPU_DP2_P0 HDMI_TX_N2 2 IN_D2p OUT_D1p 26 HDMI_RD_TX_N1 1 1
CLS10 1 2 0.1U_0201_10V6K
[6] CPU_DP2_N0 IN_D2n OUT_D1n HDMI_CTRL_CLK
LS@ To HDMI RH253 2 1 2.2K_0402_5%
CLS11 1 LS@2 0.1U_0201_10V6K HDMI_TX_P1 4 25 HDMI_RD_TX_P0
[6] CPU_DP2_P1 HDMI_TX_N1 5 IN_D1p OUT_D0p 24 HDMI_RD_TX_N0
CLS12 1 LS@2 0.1U_0201_10V6K
[6] CPU_DP2_N1 IN_D1n OUT_D0n
From CPU CLS13 1 LS@2 0.1U_0201_10V6K HDMI_TX_P0 6 22 HDMI_RD_CLKP
[6] CPU_DP2_P2 HDMI_TX_N0 7 IN_D0p OUT_CKp 21 HDMI_RD_CLKN
CLS14 1 LS@2 0.1U_0201_10V6K
[6] CPU_DP2_N2 IN_D0n OUT_CKn
CLS15 1 LS@2 0.1U_0201_10V6K HDMI_CLKP 9 39 CPU_DP2_CTRL_DATA
[6]
[6]
CPU_DP2_P3
CPU_DP2_N3
CLS16 1 LS@2 0.1U_0201_10V6K HDMI_CLKN 10 IN_CKp
IN_CKn
SDA_SRC 38
SCL_SRC 33
SDA_SNK 32
CPU_DP2_CTRL_CLK
HDMI_CTRL_DAT
HDMI_CTRL_CLK
CPU_DP2_CTRL_DATA [6]
CPU_DP2_CTRL_CLK [6]
From CPU
EMI Near JHDMI1
SCL_SNK To HDMI
+3VS
DDCBUF 14 For HDMI
C
RLS247 1 LS@ 2 4.7K_0402_5% 13 DDCBUF/SDA_CTL 3 CPU_DP2_HPD C
17 DCIN_EN/SCL_CTL HPD_SRC CPU_DP2_HPD [6] TO CPU
EQ 34 ISET HDMI_RD_CLKP RH10 1 EMI@ 2 6.8_0402_1%~D HDMI_L_CLKP RH11
I2C_CTL_EN_LS 8 EQ/I2C_ADDR0 ISET 28 HDMI_HPD HDMI_RD_CLKN 1 EMI@ 2 6.8_0402_1%~D HDMI_L_CLKN
I2C_CTL_EN HPD_SNK From HDMI

RLS249 1 LS@ 2 4.99K_0402_1% 18 HDMI_RD_TX_P0 RH12 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_P0

36 REXT HDMI_RD_TX_N0 RH13 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_N0
23 PD# 15
From HDMI Re-driver
RLS251 1 @ 2 4.7K_0402_5%
PRE 16 CFG / I2C_ADDR1 GND 35
PRE GND 41 HDMI_RD_TX_P1 RH14 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_P1
EPAD HDMI_RD_TX_N1 RH15 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_N1
PS8407ATQFN40GTR2A1_TQFN40_5X5
HDMI_RD_TX_P2 RH16 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_P2
HDMI_RD_TX_N2 RH17 1 EMI@ 2 6.8_0402_1%~D HDMI_L_TX_N2

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RF request
CPU_DP2_CTRL_DATA
+3VS +3VS +3VS +3VS +3VS CPU_DP2_CTRL_CLK
HDMI_CTRL_DAT
1
HDMI_CTRL_CLK
1

1
CLS238 HDMI_L_CLKP RH2 1 @EMI@ 2 150_0402_5% HDMI_L_CLKN
RLS257 RLS254 RLS255 RLS258 RLS256 1 2 10PF_0402_50V9
LS@ 4.7K_0402_5% LS@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @RF@
CLS239 HDMI_L_TX_P0 RH4 1 @EMI@ 2 150_0402_5% HDMI_L_TX_N0
1 2 10PF_0402_50V9
2

DDCBUF EQ I2C_CTL_EN_LS PRE ISET @RF@

CLS240 HDMI_L_TX_P1 RH5 1 @EMI@ 2 150_0402_5% HDMI_L_TX_N1
1

1 2 10PF_0402_50V9
RLS262 RLS307 RLS260 RLS263 RLS261 @RF@
HDMI_L_TX_P2 HDMI_L_TX_N2
@ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% @ 4.7K_0402_5% CLS241 RH6 1 @EMI@ 2 150_0402_5%
10PF_0402_50V9
2 @RF@
2

B B

+5V_Display

JHDMI1
HDMI_HPD 19
18 HP_DET
17 +5V
DH1 @ESD@ DH2 @ESD@ DH3 @ESD@
DDC/CEC_GND
HDMI_CTRL_CLK 9 10 1 1 HDMI_CTRL_CLK HDMI_L_TX_P1 9 10 1 1
HDMI_L_TX_P1 HDMI_L_TX_P2 9 10 1 1
HDMI_L_TX_P2 HDMI_CTRL_DAT 16
SDA
HDMI_CTRL_CLK 15
SCL
HDMI_CTRL_DAT 8 9 2 2 HDMI_CTRL_DAT HDMI_L_TX_N1
8 9 2 2
HDMI_L_TX_N1 HDMI_L_TX_N2
8 9 2 2
HDMI_L_TX_N2 14
Reserved
13
CEC
+5V_Display 7 7 4 4 +5V_Display HDMI_L_CLKP 7 7 4 4
HDMI_L_CLKP HDMI_L_TX_P0 7 7 4 4
HDMI_L_TX_P0 HDMI_L_CLKN 12
CK- GND
20
11 21
CK_shield GND
HDMI_HPD 6 6 5 5 HDMI_HPD HDMI_L_CLKN 6 6 5 5
HDMI_L_CLKN HDMI_L_TX_N0 6 6 5 5
HDMI_L_TX_N0 HDMI_L_CLKP 10
CK+ GND
22
HDMI_L_TX_N0 9 23
D0- GND
3 3 3 3 8
33 HDMI_L_TX_P0
D0_shield
7 D0+
8 8 8 HDMI_L_TX_N1 6 D1-
5 D1_shield
L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD L05ESDL5V0NA-4 SLP2510P8 ESD HDMI_L_TX_P1 4 D1+
HDMI_L_TX_N2 3 D2-
2 D2_shield
HDMI_L_TX_P2 1 D2+

ACON_HMR2E-AK120F
A ME@ A
DC231807181

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal ElecHtrDoMniIcs,Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custtom 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 29 o f 53
5 4 3 2 1
 A B C D E

NGFF WLAN /BT(Key E)

1 1

+3VS_W LAN

10P_0402_50V8J
@RF@ CW78 1 1 1 1
CW 2 CNVi@ CW 3
CW 1 CNVi@ 0.1U_0201_10V6K 0.01U_0402_16V7K
4.7U_0402_6.3V6M CNVi@ +3VALW
2 2 2 2 Need to stuff for CNVi power sequence control +3VS_W LAN

Close to KEY E pin72,74 Imax : 2.0 A Imax : 2.0 A

1U_0201_6.3V6M
+3VS_WLAN 1
CW 11

CW9 CNVi@
CNVi@ 0.1U_0201_10V6K

21
+3VS_W LAN UC13 2
5 1
IN OUT
2
GND

10P_0402_50V8
0.01U_0402_16V7
1 1 1 1
1 CNVi@ 2 CNVi_PWR_EN#_R

CW82 RF@
CW 4 CW 5 4 3 RW 41 1 @ 2
[33] CNVi_PWR_EN# EN(EN#) OC#

CNVi@ CW6
0.1U_0201_10V6K RW 42 0_0402_5% 10K_0402_5%

1U_0201_6.3V6M
4.7U_0402_6.3V6M CNVi@ G524B2T11U_SOT23-5
2 2 2 2

CW10 CNVi@
SA00007BW00
CNVi@

21
Close to KEY E pin2,4
K
I (Max) : 2.0 A(+3VS_WLAN)
RDS(Typ) : 70 mohm
V drop : 0.14 V
Jefferson Peak:1360mA@peak current
Thunder_Peak_2:1100mA@peak current
2 2

+3VS_W LAN
CNVi Module PIN Def i ne
1 JWLAN1 2 +3P3A
GND GND_1 3.3VAUX_2 4 +3P3A
[12] USB20_P10 USB_D+ 3 USB_D+
3.3VAUX_4 6 LED#1
BT [12] USB20_N10 USB_D- 5 USB_D-
7 LED1# 8 PCM_CLK
CNV_CRX_DTX_N1
GND GND_7 PCM_CLK CNV_RF_RESET#_R
10 RF_RESET_B 2 33_0201_5%
[9] CNV_CRX_DTX_N1 CNV_CRX_DTX_P1
WGR_D1N 9 SDIO_CLK PCM_SYNC 12 PCM_IN
RW 4 1 CNVi@ CNV_RF_RESET# [9]
[9] CNV_CRX_DTX_P1 WGR_D1P 11 SDIO_CMD PCM_OUT 14 CLKREQ0 CLKREQ_CNV#_R 2 33_0201_5%
GND 13 SDIO_DAT0 RW 6 1 CNVi@

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CNV_CRX_DTX_N0 PCM_IN 16 LED2# CLKREQ_CNV# [9]
[9] CNV_CRX_DTX_N0 CNV_CRX_DTX_P0
WGR_D0N 15 SDIO_DAT1 LED2# 18 GND/LNA_EN
[9] CNV_CRX_DTX_P0 WGR_D0P 17 SDIO_DAT2 GND_18 20 UART WAKE#
CLK_CNV_CRX_DTX_N
GND 19 SDIO_DAT3 UART_W AKE 22 BRI_RSP CNV_BRI_CRX_R_DTX
RW 9 1 NONCNV2i@ 0_0201_5%
UART0_RX [11]
[9] CLK_CNV_CRX_DTX_N CLK_CNV_CRX_DTX_P
WGR_CLKN 21 SDIO_W AKE UART_TX
RW 11 1 CNVi@ 2 22_0402_5%
CNV_BRI_CRX_DTX [11]
[9] CLK_CNV_CRX_DTX_P WGR_CLKP 23 SDIO_RST
RW 13 1 NONCNV2i@ 0_0201_5%
Near JWLAN1 24 RGI_DT CNV_RGI_CTX_R_DRX RW 14 1 CNVi@ 2 75_0402_5%
UART0_TX [11]
UART_RX 26 RGI_RSP CNV_RGI_CRX_R_DTX CNV_RGI_CTX_DRX [11]
PCIE_CTX_C_DRX_P14 GND 25 GND_33 RW 15 1 CNVi@ 2 22_0402_5% CNV_RGI_CRX_DTX [11]
CC82 1 2 0.1U_0201_10V6K PETp0 27 PET_RX_P0
UART_RTS 28 BRI_DT CNV_BRI_CTX_R_DRX RW 16 1 CNVi@ 2 75_0402_5% CNV_BRI_CTX_DRX [11]
[12] PCIE_CTX_DRX_P14 PCIE_CTX_C_DRX_N14 UART_CTS 30 Clink RESET
+3VS_W LAN CC83 1 2 0.1U_0201_10V6K PETn0 29 PET_RX_N0
[12] PCIE_CTX_DRX_N14 CLink_RST EC_TX [33]
GND 31 GND_39
32 Clink DATA EC_RX [33]
PERp0 33 PER_TX_P0
CLink_DATA 34 Clink CLK
[12] PCIE_CRX_DTX_P14 CLink_CLK 36 COEX3
WLAN [12] PCIE_CRX_DTX_N14 PERn0 35 PER_TX_N0
GND 37 GND_45 COEX3 38 COEX_RXD
REFCLKP039 REFCLK_P0 COEX2 40 COEX_TXD
[10] CLK_PCIE_P3 COEX1 42 C_P32K
[10] CLK_PCIE_N3 REFCLKN041 REFCLK_N0 SUSCLK [10]
GND 43 GND_51
SUSCLK(32KHz) 44 PERST0#
PERST0# 46 W_DISABLE2# PCI_RST# [10,21,31,33,36]
1 @ 2 CLKREQ_PCIE#3_R RW L1 1 2 0_0402_5% CLKREQ_PCIE#3_R
CLKREQ0#45 CLKREQ0#
[10] CLKREQ_PCIE#3 WLBT_OFF# [9]
RW 169 10K_0201_5% [33] PCIE_WAKE# RW L2 1 @ 2 0_0402_5% W AKE#_R PEWake04#7 PEW AKE0# W _DISABLE2# 48 W_DISABLE1# WL_OFF# [12]
GND 49 GND_57
W _DISABLE1# 50 A4WP_I2C_DATA W LBT_OFF# 1 @ 2
3 CNV_CTX_DRX_N1 I2C_DAT 52 A4WP_I2C_CLK 3
[9] CNV_CTX_DRX_N1 WT_D1N 51 RSVD/PCIE_RX_P1 RW 158 10K_0402_5%
CNV_CTX_DRX_P1
WT_D1P 53 RSVD/PCIE_RX_N1 I2C_CLK 54 A4WP_IRQ# W L_OFF# 1 @ 2
[9] CNV_CTX_DRX_P1 I2C_IRQ 56 REFCLK0 CLKIN_XTAL
GND 55 GND_63 CLKIN_XTAL [10]
RW 159 10K_0402_5%
CNV_CTX_DRX_N0
WT_D0N 57 RSVD/PCIE_TX_P1 RSVD_64 58 PERST1#
[9] CNV_CTX_DRX_N0 CNV_CTX_DRX_P0 RSVD_66 60 CLKREQ1#
[9] CNV_CTX_DRX_P0 WT_D0P 59 RSVD/PCIE_TX_N1 RSVD_68
GND 61 GND_69 62 PEWake1#
CLK_CNV_CTX_DRX_N
WT_CLKN63 RSVD_71 RSVD_70 64 +3P3A
[9] CLK_CNV_CTX_DRX_N CLK_CNV_CTX_DRX_P 3.3VAUX_72 66 +3P3A
[9] CLK_CNV_CTX_DRX_P WT_CLKP65 RSVD_73 3.3VAUX_74
GND 67 GND_75 68 GND
GND1
GND 69 GND2
BELLW _80152-3221
SP070013E00
ME@

Note: The real behavior of BT_DISABLE are

The connectivity module power supply pin shall be BT_DISABLE=LOW, BT=OFF
connected directly to thr rail DSW. BT_DISABLE=HIGH, BT=ON
From
567240_Intel_Wireless_AC_9560_Jefferson_Peak_EPS_Rev1.
1

PCH EDS : M.2 CNV Mode Select

GPP_F6/CNV_RGI_DT
0 = Integrated CNVi enable.

1 = Integrated CNVi disable.

+1.8VALW

4 4

CNV_RGI_CTX_R_DRX RW 156 1 CNVi@ 2 20K_0201_5%

CNV_BRI_CTX_R_DRX RW 157 1 @ 2 20K_0201_5%

100K_0201_5% 2 1 RW 26 EC_TX

71.5K_0402_1% 1 2 RW 27 CLKREQ_CNV#

CNVi@
Securiiity Clllassiiifiiicatiiion
2018/04/09
Compal Secret Data
2019/04/09
ComNGpaFlFEWleLcAtrNon/BicTs,Inc.
Issued Date Deciphered Date Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 30 o f 53
A B C D E
 5 4 3 2 1

SSD(TYPE M)
+3VS_SSD1

+3VS +3VS_SSD1

7K
0.01U_0402_16V

0.1U_0201_10V6K

M
10U_0402_6.3V6

M
10U_0402_6.3V6
1 1 1 1 +3VS_SSD1

C19
C18
R10

C20

C21
1 2
@
2 2 2 2
0_0805_5% R11 1 @ 2 0_0402_5% NGFF_SSD_PEDET [12]

2
R12
D D
10K_0201_5%
JSSD1
1 2

1
3 GND 3P3VAUX 4
5 GND 3P3VAUX 6
[12] PCIE_CRX_DTX_N9 PERn3 NC 8 D

1
7
[12] PCIE_CRX_DTX_P9 9 PERp3 NC 10 NGFF_SSD_PEDET# 2
CC92 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N9 11 GND DAS/DSS# 12 G
[12] PCIE_CTX_DRX_N9 PCIE_CTX_C_DRX_P9 13 PETn3 3P3VAUX 14
CC93 1 2 0.22U_0201_6.3V6M Q1
[12] PCIE_CTX_DRX_P9 15 PETp3 3P3VAUX 16
S 2N7002KW_SOT323-3

3
17 GND 3P3VAUX 18
[12] PCIE_CRX_DTX_N10 PERn2 3P3VAUX 20 SB000009Q80
19
[12] PCIE_CRX_DTX_P10 PERp2
SSD PCIE CC94 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N10
21
23 GND
NC 22
NC 24
[12] PCIE_CTX_DRX_N10 PCIE_CTX_C_DRX_P10 25 PETn2 NC 26
CC95 1 2 0.22U_0201_6.3V6M
[12] PCIE_CTX_DRX_P10 27 PETp2 NC 28
29 GND NC 30
[12] PCIE_CRX_DTX_N11 31 PERn1 NC 32
[12]

[12]
PCIE_CRX_DTX_P11

PCIE_CTX_DRX_N11
CC84 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N11
PCIE_CTX_C_DRX_P11
33
35
PERp1
GND
PETn1
NC 34
NC 36 NGFF_SSD_PEDET#
CC85 1 2 0.22U_0201_6.3V6M 37 NC 38
[12] PCIE_CTX_DRX_P11 39
41
PETp1
GND
DEVSLP 40
NC 42
DEVSLP1 [12]
H : PCIE Interface
SSD SATA
[12]
[12]
SATA_CRX_DTX_P1
SATA_CRX_DTX_N1
43
45
PERn0/SATA-B+
PERp0/SATA-B-
NC 44
NC 46
L : SATA Interface
[12] SATA_CTX_DRX_N1
CC86 1 2 0.22U_0201_6.3V6M
CC87 1 2 0.22U_0201_6.3V6M
SATA_CTX_C_DRX_N1
SATA_CTX_C_DRX_P1
47
49
GND
PETn0/SATA-A-
NC 48
NC 50 PCI_RST#
Fellow 543016_SKL_U_Y_PDG_0_9
[12] SATA_CTX_DRX_P1 51 PETp0/SATA-A+ PERST# 52 PCI_RST# [10,21,30,33,36]
53 GND CLKREQ# 54 CLKREQ_PCIE#1 [10]
[10] CLK_PCIE_N1 55 REFCLKN PEWake# 56
[10] CLK_PCIE_P1 57 REFCLKP NC 58
GND NC

59 60
NGFF_SSD_PEDET# 61 NC SUSCLK(32kHz) 62
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
C C
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
GND1 69
GND2
BELLW_80159-3221
SP070018L00
ME@

SSD(TYPE M)
+3VS_SSD2

www.teknisi-indonesia.com +3VS_SSD2
K
0.01U_0402_16V7

+3VS
0.1U_0201_10V6K

M
10U_0402_6.3V6

M
10U_0402_6.3V6

1 1 1 1
C23
C22

R13
C24

C25

1 2
2 2 2 2 +3VS_SSD2
0_0805_5%
@
@
R269 1 2 0_0402_5% NGFF_SSD2_PEDET [12]
S540@ S540@ S540@ @

2
JSSD2
1 2 R268
3 GND 3P3VAUX 4
10K_0201_5%
5 GND 3P3VAUX 6
B
7 PERn3 NC 8 S540@ B
PERp3

1
9 NC 10
11 GND DAS/DSS# 12
PETn3 D

1
13 3P3VAUX 14
15 PETp3 3P3VAUX 16 NGFF_SSD2_PEDET# 2
17 GND 3P3VAUX 18 G S540@
19 PERn2 3P3VAUX 20 Q5
21 PERp2 NC 22
S 2N7002KW_SOT323-3

3
23 GND NC 24
SB000009Q80
25 PETn2 NC 26
27 PETp2 NC 28
29 GND NC 30
[12] PCIE_CRX_DTX_N15
31 PERn1 NC 32
[12] PCIE_CRX_DTX_P15 PERp1
S540@ 33 NC 34
CC88 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N15 35 GND NC 36
[12] PCIE_CTX_DRX_N15 PCIE_CTX_C_DRX_P15 PETn1
CC89 1 2 0.22U_0201_6.3V6M 37 NC 38
[12] PCIE_CTX_DRX_P15 39 PETp1 DEVSLP2 [12]
DEVSLP 40
S540@ 41 GND NC 42
[12] SATA_CRX_DTX_P2 43 PERn0/SATA-B+ NC 44
[12] SATA_CRX_DTX_N2 45 PERp0/SATA-B- NC 46
S540@
CC90 1 2 0.22U_0201_6.3V6M SATA_CTX_C_DRX_N2 47 GND NC 48
[12] SATA_CTX_DRX_N2 SATA_CTX_C_DRX_P2 49 PETn0/SATA-A- NC 50 PCI_RST#
CC91 1 2 0.22U_0201_6.3V6M
[12] SATA_CTX_DRX_P2 51 PETp0/SATA-A+ PERST# 52
53 GND CLKREQ# 54 CLKREQ_PCIE#2 [10]
S540@
[10] CLK_PCIE_N2 55 REFCLKN PEWake# 56
[10] CLK_PCIE_P2 57 REFCLKP NC 58
GND NC

59 60
NGFF_SSD2_PEDET# 61 NC SUSCLK(32kHz) 62
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
67 GND 3P3VAUX
GND 68
GND1 69
GND2
A A
BELLW_80159-3221
SP070018L00
ME@

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Decipherii ed Dae
t 2019/04/09 Tiiitttllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
SSD
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS C 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Dattte::: Monday,,, Octttober 22,,, 2018 Sheettt 31 o ff53
5 4 3 2 1
 A B C D E

+5VALW CA38 1 2 1U_0201_6.3V6M

Speaker Connector PN
CX11880
RA66 1 2 0_0402_5%
+1.8VDD_CODEC +5VDDA_CODEC

Speaker SP02000RR00

CA30
RA67 1 @ 2 0_0402_5%

CA31
1U_0201_6.3V6M

1U_0201_6.3V6M
+1.8VDD_CODEC G NDA
EMI wide 40MIL

CA54

CA53
+IOVDD_CODEC

2.2U_0402_6.3V6M

0.1U_0201_10V K X5R
1 1 +5VDDA_CODEC
1 1
+3VDD_CODEC
@ @
SPEAK 4 ohm : 40MIL JSPK1
SPEAK 8 ohm : 20MIL

0.47U_0402_25V6K
2 2 6
1 G2
2 2 5
SPK_L1- SPK_L1-_CO NN G1
RA18 1 @ 2 0_0603_5% 4

CA42
SPK_L2+ SPK_L2+_CO NN 4
RA19 1 @ 2 0_0603_5% 3
2 +1.8VS SPK_R1- SPK_R1-_CONN 3
RA16 1 @ 2 0_0603_5% 2

39

38

18

29

13

16

37

28

27
1 2

9
SPK_R2+ SPK_R2+_CONN 1
UA1 RA17 1 @ 2 0_0603_5% 1
1
Place near Pin18

LDO_V12

PVDD5_L
VDD18

PVDD5_R

LDO_AVDD
CP_AVDD18

AVDD5

VREFP
DVDD_IO

VREF_DAC
HDA_VDDIO
ME@

1000P_0402_50V7K

1000P_0402_50V7K
1
SP02000VH00

1000P_0402_50V7K

1000P_0402_50V7K
1 1 1 1 CVILU_CI4404M1HRT-NH
RA39

EMI@ CA20

EMI@ CA21

EMI@ CA22
EMI@ CA19
HDA_RST#_R 5.11K_0402_5%
[9] HDA_RST#_R 2
[9] HDA_BIT_CLK_R

2
RESET# 2 2 2 2
@EMI@ @EMI@ CX11880-11Z MICBIASB
32 MICBIASB
CA29 22P_0402_50V8J RA36 2 1 33_0402_5% 40
41 HDA_BUS_BCLK 35 PLUG _IN_R PLUG _IN
[9] HDA_SYNC_R RA1 1 2 39.2K_0402_1%
HDA_BUS_SYNC JSENSE
[9] HDA_SDIN0
[9] HDA_SDOUT_R
RA35 1 2 33_0402_5% HDA_SDIN0_R 42
1 HDA_BUS_SDI ESD protection needs to be placed near connector side
HDA_BUS_SDO
RA59 1 2 20K_0402_5%
34 Port_B_R

+3VS RA56 1 2 100K_0201_5%

11
7
SPKR_MUTE#/SPDIF/GPIO1
PORT_B_R 33
PO RT_B_L
Port_B_L
ESD
R A34 1 2 0_0402_5% PDB
[33] EC_MUTE# Bi-directional EAPD 31 EXT_MIC_RING2 +5VS
PC_BEEP 36 PORTD_B_MIC 30 EXT_MIC_SLEEVE
PCBEEP PO RTD_A_MIC @ESD@ DA1
6 SPK_R1-_CONN 6 3 SPK_L2+_CONN
MUSIC_REQ/SPDIF/GPIO0 I/O4 I/O 2
26 HGNDB
EMI@ HGNDB 25 HGNDA
LA1 1 2 BLM15PX221SDNM1DIC__2CPLK_R 10 HG NDA
[28] DMIC_CLK DMIC_DAT 8 PORTC_DMIC_CLK1/GPIO2 5 2
[28] DMIC_DAT PORTC_DMIC_DATA1/GPIO3 HP_O UTR VDD G ND
24
+3VDD_CODEC
RA32 1 2 10K_0201_5% 4 PORTA_R 23 HP_O UTL
Headphone
5 HSCL/TEST1 PO RTA_L
HSDA/TEST2 SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O 3 I/O 1
12 21 AZC099-04S.R7G_SOT23-6
14 LEFT+ CP_VNEG 22
LEFT- CP_VPO S

CA33

CA34
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
CA32
15 20

2.2U_0402_6.3V6M
17 RIGHT- CP_FLY_N 19

EP_GND
RIG HT+ CP_FLY_P 1 1 1
2 2

CX11880-11Z_QFN42_5X5 2 2 2
RF request

43
HDA_RST#_R
@
2 1 CA52 2 @ 1 RA40 SPK_R2+ HDA_BIT_CLK_R
220P_0402_50V7K 10_0402_5% HDA_SYNC_R
@ HDA_SDIN0
2 1 CA51 2 @ 1 RA42 SPK_R1- HDA_SDOUT_R

@
220P_0402_50V7K 10_0402_5%

SPK_L1-
Speaker EMI
2 1 CA45 2 @ 1 RA44
220P_0402_50V7K 10_0402_5%

CA35 2.2P_0402_50V8C

CA59 2.2P_0402_50V8C

CA60 2.2P_0402_50V8C

CA61 2.2P_0402_50V8C

CA62 2.2P_0402_50V8C
@ 1111 1
2 1 CA46 2 @ 1 RA43 SPK_L2+ EXT_MIC_SLEEVERA62 1 2 100_0402_5% CA55 1 2 1U_0201_6.3V6M SM010009U00 LA2 2 EMI@ 1 BLM15PX221SN1D_2P HG NDB
W=40m ils EXT_MIC_RING2 RA63 1 1 BLM15PX221SN1D_2P
220P_0402_50V7K 10_0402_5% W=40m ils 2 100_0402_5% CA56 1 2 1U_0201_6.3V6M SM010009U00 LA3 2 EMI@ HG NDA
HP_O UTL EMI@ RA22 1 2 47_0402_5% HPO UT_L
HP_O UTR HPO UT_R

www.teknisi-indonesia.com
Reserved Snubber Networks 2222 2 EMI@ RA23 1 2 47_0402_5%
SD028470A80
Place near Codec Pins

@RF@

@RF@

@RF@

@RF@

@RF@
SD028470A80

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
RA24

RA25
10K_0201_5%
1 1

10K_0201_5%

CA25

CA26
@ 2
@

CA50

CA24

1 2
12
2 2

1
GNDA GNDA GNDA GNDA GNDA GNDA
EMI@ EMI@ EMI@ EMI@

+5VS --> +5VDDA_CODEC +3VS --> +IOVDD_CODEC +3VS --> +3VDD_CODEC SM010009U00LA5 2 EMI@ 1 BLM15PX221SN1D_2P RA64 1
SM010009U00LA4 2 EMI@ 1 BLM15PX221SN1D_2P RA65 1
2
2
100_0402_5%
100_0402_5%
CA57 1
CA58 1
2
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
Port_B_R
Port_B_L

1
3K_0402_1%

3K_0402_1%
+5VS +5VDDA_CO DEC +3VS +3VDD_CODEC
3
wide 40MIL +3VS +IOVDD_CODEC 3

RA60

RA61
RA9 1 @ 2 0_0603_5% RA10 1 @ 2 0_0603_5% RA11 1 @ 2 0_0402_5%

2
MICBIASB
Combo Jack
4.7U_0402_6.3V6M

0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R

(Normal Open)
4.7U_0402_6.3V6M

1 1 1 1 1 1 1
1U_0201_6.3V6M

1U_0201_6.3V6M
CA39

CA40

CA37

CA12

CA28 CA13 CA14

2 2 2 2 2 2 2 JHP1
HGNDA / HGNDB , W=60mils
HGNDA 3 RING2_L
HPOUT_L RA28 1 @ 2 0_0402_5% HPOUT_L1 1 HPOUT_L_2

5 HP_PLUG#
Place near Pin3 PLUG _IN 6 GND
Place near Pin13,16,29 Place near Pin9 HPO UT_R HPO UT_R1 2 HPOUT_R_2
2 0_0402_5%
RA29 1 @ 4 SLEEVE_L
HGNDB 7 GND
1 1

2200P_0402_25V7K
CA71
YUQIU_PJ784-F07M1BE-A

100P_0402_50V8J
CA73
DC23000FJ00

@ESD@

ESD@
1 ME@
2 2

L03ESDL5V0CC3-2_SOT23-3
DA3 SCA00002900

CEST23LC5VB C/A SOT-23

DA4 SCA00004300
3

2
CA72
100P_0402_50V8J
+1.8VS --> +1.8VDD_CODEC

@ESD@
1
2

2200P_0402_25V7K
CA70
ESD@
2

@ESD@

ESD@
RA57 1 @ 2 0_0402_5%
+1.8VS +1.8VDD_CODEC

RA31 1 @ 2 0_0402_5%
PC Beep RA14 1 @ 2 0_0402_5%

1
0.1U_0201_10V K X5R

1 1 RA15 1 @ 2 0_0402_5%
1 2 1 2 PC_BEEP
CA41

CA43
1U_0201_6.3V6M

[33] BEEP#
4 RA12 4.7K_0402_5% CA15 0.1U_0201_10V K X5R 4
1 2 1 2 RA58 1 @ 2 0_0402_5%
2 2 [9] HDA_SPKR
RA41 4.7K_0402_5% CA44 0.1U_0201_10V K X5R

GND GNDA

Place near Pin38

Securiiity Clllassifiiicatiiion Compal Secret Data Compal Electronics, Inc.
Issued Date 2018/05/04 Deciphered Date 2019/04/09 Tii t l e

THIIIS SHEET O F ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY O F COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
HD Audio Codec_CX11880
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSF ERED F ROM THE CUSTODY O F THE COMPETENT DIIIVIIISIIION O F R&D Size Documenttt Num ber R ev
Custttom 0.. 2
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIIT CONTAIIINS
MAY BE USED BY O R DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT O F COMPAL ELECTRONIIICS,,, IIINC... LA-H082P
Dattte::: Tuesday,,, Octttober 23,,, 2018 Sheettt 32 o ff 53
A B C D E
 +3VL +3VL +5VALW
L1
1 2
+3VALW _EC +EC_VCCA +3VALW_EC USB_EN#
BLM15AX601SN1D _2P R14 1 @ 2 0_0805_5% 1 R15 1 2 10K_0201_5%
SM01000KL00 C26
1 1 100P_0402_50V8J
C27 C28 1 1 1 1 @
VCIN1_BATT_TEMP C32

0.1U_0201_10V K X5R
C29

0.1U_0201_10V K X5R
C30

K
1000P_0402_50V7
C31

K
1000P_0402_50V7
C33
0.1U_0201_10V KX5R 1000P_0402_50V7K 2 1 2 100P_0402_50V8J
@
2 2 VCIN1_AC_IN C34 1 2 100P_0402_50V8J
L2 2 2 @2 @2 +EC_VCCA
1 2 ECAGND R16 1 @ 2 4.7K_0402_5%
BLM15AX60 1SN1D _2P
SM01000KL 00

M12
K12

B11
K7
J4

J7
ECAGND U11

EC_VCC0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
+3VS
M2 M9 VCCST_PWRGD
L2 GATEA20/GPIO00 PW M0/GPIO0F M8 VCCST_PWRGD [10] EC_SMB_CK4 R17 1 C340@ 2 1K_0201_5%
KBRST#/GPIO01 PW M1/GPIO10 M10 BEEP# [32] EC_SMB_DA4
M3 R18 1 C340@ 2 1K_0201_5%
[8] SERIRQ SERIRQ FANPW M0/GPIO12 N10 EC_FAN_PWM2 [35]
K4

EMI [8] LPC_FRAME#

[8] LPC_AD3
[8] LPC_AD2
N3
M4
K5
LPC_FRAME#
LPC_AD3
LPC_AD2 PW M Output
FANPW M1/GPIO13

B13
EC_FAN_PWM1 [35]
+3VS

[8] LPC_AD1 N4 LPC_AD1 BATT_TEMP/AD0/GPIO38 A13 VCIN1_BATT_TEMP [41,42]

@EMI@ @EMI@
[8] LPC_AD0 LPC_ADL0 PC & MISC AD1/GPIO39 B12 I2C_2_SCL
C35 2 1 22P_0402_50V8J R19 2 1 10_0402_1% R20 1 C340@ 2 2.7K_0402_5%
ADP_I [42]
[8] CLK_LPC_EC
N5 AD Input ADP_I/AD2/GPIO3A A12
CUST_TEMP3 [35]
I2C_2_SDA R21 1 C340@ 2 2.7K_0402_5%
PCI_RST# M5 CLK_PCI_EC AD3/GPIO3B D8
[10,21,30,31,36] PCI_RST# EC_RST# K13 PCIRST#/GPIO05 AD4/GPIO42 D7 TS_DISABLE# [28]
+3VALW _EC R22 1 @ 2 47K_0402_5%
N6 EC_RST# IMON/AD5/GPIO43 CUST_TEMP2 [35]
[6] EC_SCI# 1 @ 2 PM_CLKRUN#_R M6 EC_SCI#/GPIO0E +3VALW
2 [8] PM_CLKRUN# CLKRUN#/GPIO1D
0.1U_0201_10V K X5R
C36

R23 0_0402_5%
B10 NOVO# EC_PCIE_WAKE# R24 1 @ 2 4.7K_0402_5%
BA0/GPIO3C A9 NOVO# [36]
1
DA Output DA1/GPIO3D A10 TP_DISABLE# [34]
KSI0 E9
E12 KSI0/GPIO30 DA2/GPIO3E B9 USB_EN# DGPU_PWR_EN [11,26]
KSI1
E13 KSI1/GPIO31 DA3/GPIO3F USB_EN# [36]
KSI2
KSI3 D12 KSI2/GPIO32 D6 I2C_2_SCL LID_SW # R26 1 2 100K_0201_5%
D13 KSI3/GPIO33 PSCLK1/GPIO4A E7 I2C_2_SDA I2C_2_SCL [11]
KSI4
KSI5 C12 KSI4/GPIO34 PSDAT1/GPIO4B E5 EC_SMB_CK4 I2C_2_SDA [11] TAB_SW # R27 1 2 100K_0201_5%
KSI6 C13 KSI5/GPIO35 PSCLK2/GPIO4C D5 EC_SMB_DA4 EC_SMB_CK4 [28,35]
E10 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D A5 EC_SMB_DA4 [28,35]
KSI7
J13 KSI7/GPIO37 PSCLK3/GPIO4E B5 TAB_SW # USB_CHG_ILIM_SEL [36] EC_MUTE#
KSO0 R28 1 @ 2 10K_0201_5%
J12 KSO0/GPIO20 PSDAT3/GPIO4F TAB_SW# [28]
KSO1
KSO2 H12 KSO1/GPIO21
KSO[0..15] KSO3 H13 KSO2/GPIO22 B1
[34] KSO[0..15] J10 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 A1 ENBKL [6] EC_SPI_CS0#
KSO4 R30 1 2 100K_0201_5%
KSO4/GPIO24 W OL_EN/GPXIOA01 C1 SYS_PWROK [10]
KSI[0..7] KSO5 J9
KSO5/GPIO25
Int. K/B ME_EN [9]
[34] KSI[0..7] KSO6 H9 ME_EN/GPXIOA02 C2 Follow ENE suggestion for Auto load
KSO7 H10 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 [41]
G13 KSO7/GPIO27 SPI DeviceInterface
KSO8
KSO9 G12 KSO8/GPIO28 K2
F13 KSO9/GPIO29 SPIDI/GPIO5B J2 EC_SPI_MISO [8]
ESD 1

0.1U_0201_10V K X5R
C37 @ESD@
KSO10
KSO10/GPIO2A EC_SPI_MOSI [8]
KSO11 F12
KSO11/GPIO2B SPI Flash ROM SPIDO/GPIO5C
SPICLK/GPIO58
L1
EC_SPI_CLK [8]
KSO12 G10 N2
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# [8] 2
KSO13 G9
KSO14 F10 KSO13/GPIO2D
KSO15 F9 KSO14/GPIO2E B6
D9 KSO15/GPIO2F ENBKL/AD6/GPIO40 B7 CUST_TEMP1 [35]

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[34] KB_MUTLI_KEY D10 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 B4 EC_MUTE# SENSOR_EC_INT [11]
+3VL [24,42] GPU_PROHOT# KSO17/GPIO49 FSTCHG/GPIO50 BATT_CHG_LED# EC_MUTE# [32]
A4
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# [34]
B3
EC_SMB_CK1 EC_SMB_CK1 CAPS_LED#/GPIO53 CAPS_LED# [34] +3VL
R31 1 2 2.2K_0402_5% A8 GPIO A3
[41,42] EC_SMB_CK1 PWR_LED# [36]
R32 1 2 2.2K_0402_5% EC_SMB_DA1 EC_SMB_DA1 A7 EC_SMB_CK1/GPIO44 PW R_LED#/GPIO54 A2 BATT_LOW_LED#
[41,42] EC_SMB_DA1 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [34]
B8 EC_SMB_DA1/GPIO45 SM Bus B2 SYSON
[8,24,35] EC_SMB_CK2 SYSON [13,44]
A6 EC_SMB_CK2/GPIO46 SYSON/GPIO56 H5 VR_ON [47] NOVO# R33 1 2 100K_0201_5%
[8,24,35] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 M1 AC_PRESENT [10,24]
PM_SLP_S4#/GPIO59 KB_MUTLI_KEY R25 1 2 10K_0201_5%

J5 D4 ON/OFF# R34 1 2 100K_0201_5%

[10] PM_SLP_S3# N9 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 D1 EC_RSMRST# [10]
[36] USB_CHG_CTL1 L13 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 D2 3V/5VALW_PG [36,39,43,45]
[10] EC_CLEAR_CMOS# K6 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 E2 VCOUT1_PROCHOT#
[36] USB_CHG_CTL3 N7 GPIO0A H_PROCHOT#_EC/GPXIOA06 E4 VCOUT1_PROCHOT# [42]
+3VS [36] USB_CHG_EN M7 GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_MAIN_PWR_ON [43]
[36] USB_CHG_CTL2 GPIO0C GPO BKOFF#/GPXIOA08 E1 BKOFF# [28] @
N8 F4 SUSP# R35 1 2 100K_0201_5%
[36] USB_CHG_STATUS# GPIO0D GPIO PBTN_OUT#/GPXIOA09 F2 TYPEC_LIMIT_CTL1 [38]
K8
EC_FAN_SPEED1 [34] KB_BL_PWM EC_INVT_PW M/GPIO11 PCH_APW ROK/GPXIOA10 F1 EC_PCIE_WAKE# CNVi_PWR_EN# [30] PCIE_WAKE#
R36 1 2 10K_0201_5% EC_FAN_SPEED2 M11 1 2
EC_FAN_SPEED2 [35] EC_FAN_SPEED2 N11 FANFB0/GPIO14 SA_PGOOD/GPXIOA11 PCIE_WAKE# [30]
R38 1 2 10K_0201_5% EC_FAN_SPEED1 R37 0_0402_5%
[35] EC_FAN_SPEED1 K10 FANFB1/GPIO15
[30] EC_TX EC_TX/GPIO16 F5
K9
GPU_PROHOT# [30] EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 G1 VCIN1_AC_IN [42]
R39 1 @ 2 10K_0201_5% PCH_PW ROK N12
[10] PCH_PWROK EC_ON/GPXIOD02 EC_ON [43]
PWR_BATT_LOW# M13 PCH_PW ROK/GPIO18 G5 ON/OFF#
[36] PWR_BATT_LOW# VR_PW RGD L12 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 H1 ON/OFF# [36,39]
[47] VR_PWRGD NUM_LED#/GPIO1A GPI LID_SW #/GPXIOD04 G4 LID_SW# [35] VCOUT1_PROCHOT#
SUSP# R40 1 2 0_0402_5%
SUSP#/GPXIOD05 SUSP# [13,39,44]
H4
GPXIOD06 H2 PECI 1 2
PBTN_OUT# PECI_KB9012/GPXIOD07 H_PECI [6]
J1 R41 43_0402_1% R42 1 2 0_0402_5% H_PROCHOT# [6]
+3VALW [10] PBTN_OUT# K1 XCLKI/GPIO5D VCC_IO2 [47] VR_HOT#
N1 1@2
[10,42,45] PM_SLP_S4# XCLKO/GPIO5E V18R +3VALW _EC
R43 0_0402_5% 1
AGND
GND0

1
GND

R44 1 @ 2 10K_0201_5% PBTN_OUT# C38 ESD@

C39
4.7U_0402_6.3V6M 100P_0402_50V8J
2
G2

2
N13

KB9022GD_VFBGA124
ECAGND A11

ESD

ESD
Keyboard BackLight_SELECT 3V/5VALW_PG PCI_RST# PCH_PWROK VR_PW RGD VCCST_PWRGD BATT_CHG_LED# BATT_LOW_LED# SYSON
Funct i on KBL_ID
1 1 1
@ESD@
0.1U_0201_10V K X5R
C41 SE00000SV00

100P_0402_50V8J
C44 @ESD@
KBL 1
ESD@
0.1U_0201_10V K X5R
C40

J
100P_0402_50V8
C42 ESD@

J
100P_0402_50V8
C45 @ESD@

J
100P_0402_50V8
C46 @ESD@

0.1U_0201_10V K X5R
C47 @ESD@
J
100P_0402_50V8
C43 ESD@
1 1 1 1 1

NO KBL 0 2 2 2
SE00000SV00

2 2 2 2 2

PH on KB side
KB_BL_PWM
1

R45
10K_0201_5%
Securiiity Clllassiiifiiicatiiion Compal Secret Data ComECpaKlBE9l0e2c2trQoDnics,Inc.
NOKBL@
Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle
2

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custtom 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 33 o f 53
Finger printer Keyboard
JFP1
1
2 1
3 2
4 3
5 4
65 9
[12] USB20_P7 7 6 G1 10
[12] USB20_N7 RFP1 1 @ 8 7 G2
+3VS 2 0_0402_5%
8 +5VS
+3VALW RFP2 1 2 0_0402_5%
ME@ KSI[0..7] JKB1
KSI[0..7] [33]
SP01001AE00
ACES_51522-00801-001 KSO[0..15] RTP4 1 2 0_0402_5% 32
KSO[0..15] [33] 32
R265 2 1 866_0402_5% CAPS_LED#_R 31
[33] CAPS_LED# KSO15 30 31
KSO10 29 30
CFP1
29

C229
0.1U_0201_10V K X5R KSO11 28 34
KSO14 27 28 GND 33
1 27 GND

3
KSO13 26
ESD@ KSO12 25 26
25

0.1U_0201_10V K X5R
DFP1 KSO3 24
ESD@ 2 KSO6 23 24
CEST23LC5VB C/A SOT-23 KSO8 22 23
SCA00004300 KSO7 21 22

1
KSO4 20 21
KSO2 19 20
KSI0 18 19
KSO1 17 18
KSO5 16 17
ESD KSI3 15
KSI2 14
16
15
KSO0 13 14
KSI5 12 13
KSI4 11 12
KSO9 10 11
KSI6 9 10
KSI7 8 9

Touch Pad
KSI1 7 8
6 7
5 6
4 5
3 4
+3VS +3VS 2
[33] KB_MUTLI_KEY 3
RTP1 1 2
1
1
JXT_FP257H-032S10M
20_0402_5% @ SP01002FA00
CTP1 ME@
1

0.1U_0201_10V K X5R
RTP2
4.7K_0402_5%
2

JTP1
+TP_VCC 8
7 8 10
[11] I2C_0_SCL 7 G2
6 9
[11] I2C_0_SDA 6 G1
5
4 5
3 4
2 3
[9] TP_INT# 2
1
[33] TP_DISABLE# 1
ME@
100P_0402_50V8J

ACES_51522-00801-001

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8J
100P_0402_50V

1 1
2

3
CTP2

SP01001AE00
CTP3
@

@ DTP1
2 2 @ESD@
1

L03ESDL5V0CC3-2_SOT23-3

ESD

Keyboard Backlight BATT LED

LED1
+5VS +5VS_KBL White
RS1
+5VALW BATT_CHG_LED# 1 @2 BATT_CHG_LED#_R 2
[33] BATT_CHG_LED#
KBL@ JKBL1 412_0402_1%
QKBL1 1 RS3 1 RS2 1 2 0_0402_5% +VL
2 1
2

KBL@ BATT_LOW_LED# 1 @2 BATT_LOW_LED#_R 3

2 [33] BATT_LOW_LED#
3 1 3 5 523_0402_1%
S

RKBL1
10K_0201_5% 4 3 GND 6
ME2301DC-G_SOT23-3 4 GND Amber
RS1 RS1
0.1U_0201_10V K X5R

SC50000FV10
CKBL

JXT_FP202DH-004M10M
10U_0402_6.3V6M

1 2
G
1

RKBL2 SP010022U00 C340@ S540@ HT-210UD5-BP5_AMBER-WHITE

KBL@ CKBL2

1 2 ME@ 330_0402_1% 604_0402_1% C340@

[33] KB_BL_PWM
30K_0402_1% 2@ 1
1 RS3 RS3
KBL@ KBL@
CKBL3 C340@ S540@
1

0.01U_0402_16V7K 330_0402_1% 523_0402_1% LED2

2 White

1
3

Amber
SC50000FV10
HT-210UD5-BP5_AMBER-WHITE
S540@

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

2017/5/3 2019/04/09
Issued Date Decipherii ed Dae
t Tiiitttllle
KBL/KBD/LED/TP/HS Conn.
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number C Rev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Dattte::: Monday,,, Octttober 22,,, 2018 Sheettt 34 o ff53
 5 4 3 2 1

THERMISTOR

+3VS_THM
+3VS +3VS_THM

RTH3 1 @ 2 0_0402_5% 1
D D
CTH1
0.1U_0201_10V6K
2 TOP DDR
BOTTOM VCORE REMOTE1+ Close UTH1 UTH1
+3VS_THM

QTH1 C 1 G-Sensor
1

1
CTH3 1 10 EC_SMB_CK2
MMBT3904WH_SOT323-3 2 2200P_0402_25V7K VCC SCL EC_SMB_CK2 [8,24,33]
CTH4
B REMOTE1+ 2 9 EC_SMB_DA2 @ RTH2
@ 2200P_0402_25V7K
2

E 2 DP1 SDA EC_SMB_DA2 [8,24,33] 10K_0402_5%

3

REMOTE1- REMOTE1- 3 8

2
DN1 ALERT#
REMOTE2+ REMOTE2+ 4 7 THM_ALERT#
BOTTOM GPU DP2 THERM# +3VS
REMOTE2- 5 6 +3VS_GS_R
1 DN2 GND
1

C CTH5 UGS1
QTH2 2 2200P_0402_25V7K CT114 RGS1 1 2 0_0402_5% +3VS_GS_R 7 3
B F75303M_MSOP10 10 VDD VDDIO 11

0.1U_0201_10V K X5R
MMBT3904WH_SOT323-3E @ 2200P_0402_25V7K
2

2 @ CSB PS
SA000046C00
3

REMOTE2- 5 4
2 6 INT1 NC
Address 1001_101xb C340@
INT2
1

CGS1
2 SDO 9
REMOTE1,2 (+/-) : 1 [28,33] EC_SMB_DA4 12 SDx GND 8
[28,33] EC_SMB_CK4 SCx GNDIO
Trace width/space:10/10 mil BMA253_LGA12
Trace length:<8" SA000096W00
C340@

SMB Address: 0X18

C
DDR4 GPU_CHOKE Charger CHOKE C

+EC_VCCA +EC_VCCA +EC_VCCA

1

1
RTS1 RTS2 RTS3
16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1%
2

2
[33] CUST_TEMP1 [33] CUST_TEMP2 [33] CUST_TEMP3

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1

1
RTS4 RTS5 RTS6
100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
2

2
ECAGND ECAGND ECAGND

+5VS

FAN RF1 2 1 0_0603_5% +5VS_FAN1

B B
1 2
@RF@
CF3 CF1 JFAN1
6.8P_0402_50V8C 10U_0402_6.3V6M 1
2 1 2 1
[33] EC_FAN_PWM1 2
3
EC_FAN_PWM1 [33] EC_FAN_SPEED1 4 3
5 4
EC_FAN_SPEED1 6 G1

1
G2
CVILU_CI4404M1HRT-NH +3VALW UHS1 UHS2
1 1

GND

GND
@RF@ @RF@ SP02000VH00 TCS40DPR_SOT23F3 TCS40DPR_SOT23F3
CF4 CF5 ME@ S540@ +3VALW C340@

VOUT

VOUT
6.8P_0402_50V8C 6.8P_0402_50V8C

VCC

VCC
2 2

3
+5VS

RF2 2 1 0_0603_5% +5VS_FAN2 LID_SW# LID_SW#

LID_SW# [33]
1 2
@RF@
CF6 CF2 JFAN2 2 1 2 1
6.8P_0402_50V8C 10U_0402_6.3V6M 1 CHS2 CHS3 CHS4
2 1 2 1 0.1U_0201_10V K X5R 0.1U_0201_10V K X5R 10P_0402_50V8J
[33] EC_FAN_PWM2 CHS1
3 2 S540@ C340@ C340@
[33] EC_FAN_SPEED2 4 3 1 2 10P_0402_50V8J
S540@ 1 2
5 4
6 G1
G2
CVILU_CI4404M1HRT-NH
SP02000VH00
EC_FAN_PWM2 ME@
EC_FAN_SPEED2
A A
1 1
@RF@ @RF@
CF8 CF7
6.8P_0402_50V8C 6.8P_0402_50V8C
2 2

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 Decipherii ed Dae
t 2019/04/09 Tiiitttllle

FAN / Thermal Senser

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number R ev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS C 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Dattte::: Monday,,, Octttober 22,,,2018 Sheettt 35 o ff53
5 4 3 2 1
 A B C D E F G H

USB3.0_Port (AOU_Port)
USB Charge switch
+VL +5VALW _CHG +5VALW

+5VALW _CHG
+3VL
+5VALW _USB1
1

+3VL NON_ONEKEY@
R270
10K_0201_5%

10K_0201_5%
R108 R110
1
ME2301DC-G_SOT23-3

10U_0603_6.3V6M
C50
10U_0603_6.3V6M
C48

10U_0603_6.3V6M
C49
1 1 1
@

1
R111 1 @ 2 0_0603_5% 3 1

10K_0201_5%

D
10U_0603_6.3V6M
C51

10U_0603_6.3V6M
C52
1 Q2 1
2

2 2 2

2
USB_CHG_CTL2

2 G
U12
1 80mil 1

2
1 12 2 2
9 IN OUT 10 USB20_P1_C
[33] USB_CHG_STATUS# USB_OC0#_R 13 STATUS# DP_IN 11 USB20_N1_C
R112 2 @ 1 0_0402_5%
[12] USB_OC0#
[33] USB_CHG_ILIM_SEL
4 FAULT# DM_IN 2 +VL
5 ILIM_SEL DM_ OUT 3 USB20_N1 [12]
[33] USB_ CHG_ EN NON_ONEKEY@
EN DP_ OUT USB20_P1 [12]
[33] USB_CHG_CTL1 6 15 R113 1 2 2.7M_0402_1% R115
7 CTL1 ILIM_LO 16 R114 1 2 24.9K_0402_1% 1 2
[33] USB_CHG_CTL2
8 CTL2 ILIM_HI 14
[33] USB_CHG_CTL3
CTL3 GND 17 100K_0201_5%
T-PAD

0.1U_0201_10V K X5R
C53
D 1

1
10K_0201_5%
R117

2N7002K_SOT23-3

NON_ONEKEY@
Q3
SN1702001RTER_WQFN16_3X3 2
[33,39,43,45] 3V/5VALW _PG G @
S 2

3
0.1U_0201_10V K X5R
C54
1

@
2

+5VALW +5VALWP
22U_0603_6.3V6M
C55

22U_0603_6.3V6M
C56

22U_0603_6.3V6M
C57

22U_0603_6.3V6M
C63

22U_0603_6.3V6M
C64
10U 6.3V M X5R 0402
C58

10U 6.3V M X5R 0402

C59

1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2

2 For USB Charger to improve +5VALWP power ripple 2

USB3.0_Port I/O CONN JIO1

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1
+3VALW 1
2
[12] USB3_CRX_DTX_P1 2
[12] USB3_CRX_DTX_N1 3
3
4
[12] USB3_CTX_DRX_P1 4
5 5
[12] USB3_CTX_DRX_N1
6 6
USB20_N1_C 7 7
USB20_P1_C
8 8
9 9
10 10
[12] USB3_CRX_DTX_P2
11 11
[12] USB3_CRX_DTX_N2
12 12
[12] USB3_CTX_DRX_P2 13
13
[12] USB3_CTX_DRX_N2 14
14
15
15
[12] USB20_N2 16
16
[12] USB20_P2 17
17 18
+5VALW _USB1
18 19
19 20
20 21
21 22
22 23
+5VALW _USB2 23 24
24 25
25 26
26 27
+3VS 28
3
27 3
29
28
[10,21,30,31,33] PCI_RST# PCIE_CTX_C_DRX_P13 30
C236 1 2 0.1U_0201_10V6K 29
[12] PCIE_CTX_DRX_P13 PCIE_CTX_C_DRX_N13 31
C237 1 2 0.1U_0201_10V6K 30 32
[12] PCIE_CTX_DRX_N13
31 33
[12] PCIE_CRX_DTX_P13
32 34
[12] PCIE_CRX_DTX_N13
33 35
CLK_PCIE_P4_R
34 36
[10] CLK_PCIE_P4 CLK_PCIE_N4_R
35 37
[10] CLK_PCIE_N4 38
36
[10] CLKREQ_PCIE#4 39
NOVO# 37
[33] NOVO# 40
38
[33,39] ON/OFF# 41
39
+VL PW R_LED# 42 GND
40
[33] PW R_LED# PW R_BATT_LOW# GND
41
[33] PW R_BATT_LOW# 42 43
44

2A/Active Low ACES_50501-04201-001

SP01001O300

+5VALW +5VALW _USB2 ME@

U9 W=80mils
W=80mils OUT
1
5
IN
2
USB_EN# 4
[33] USB_EN# GND EN
3 USB_OC1#_R 1 @ 2 R122
OCB USB_OC1# [12]
1 0_0402_5%
C66 G524B2T11U_SOT23-5
0.1U_0201_10V6K SA00007BW00

4 4

Securiiittty Clllassiiifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

Tiitttlle
IIIssued Dattte 2018///04///09 Deciphered Dattte 2019/04/09//// IO board
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND TRADE Siiize Documenttt Numberrr Re v
SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISION OF R&D DEPARTMENT EXCEPT
AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,,IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
Custttom LA-H082P 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 36 offf 53
A B C D E H
F G
 5 4 3 2 1

USB3.0_Port
TI @ UT4 TI@ RT48 TI@ RT22 TI@ RT49 TI@ RT50 TI@ RT51 TI@
SN65LVPE502ARGER 0_0402_5% 0_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
D D

PA@ UT4 PA@ RT25 PA@

PS8713BTQFN24GTR2-A2 4.7K_0402_5%

PE@ UT4 PE@ RT49 PE@ RT24 PE@ RT28 PE@

PI3EQX7502AIZDEX TQFN24 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%

ZZZ X76_TI@ ZZZ X76_PA@ ZZZ X76_PE@

+3VALW +3VALW

USB3.0 re-driver_TI USB3.0 re-driver_PARADE USB3.0 re-driver_PERICOM

X7680638L08 X7680638L09

0.01U_0402_16V7K

0.1U_0201_10V K X5R
X7680638L07

1 1

CT31

CT32
USB3 Re-driver
UT4 @
1 2 2
VDD 13
VDD
P3_A_EQ1 4
P3_A_DE0 3 NC 15 P3_B_EQ1
P3_A_EQ0 2 DE_A NC 16 P3_B_DE0
To CPU P3_A_DE1 6 EQ_A DE_B 17 P3_B_EQ0
NC EQ_B 18 P3_B_DE1
NC
C CT29 2 1 0.1U_0201_10V K X5R USB3_CRX_C_RD_DTX_P3 12 19 USB3_CRX_RD_DTX_P3 C
[12] USB3_CRX_DTX_P3 USB3_CRX_C_RD_DTX_N3 11 TXB+ RXB+ USB3_CRX_RD_DTX_P3 [38]
CT30 2 1 0.1U_0201_10V K X5R 20 USB3_CRX_RD_DTX_N3
[12] USB3_CRX_DTX_N3 TXB- RXB- USB3_CRX_RD_DTX_N3 [38]

CT27 2 1 0.1U_0201_10V K X5R USB3_CTX_C_RD_DRX_P3 9 22 USB3_CTX_RD_DRX_P3

[12] USB3_CTX_DRX_P3 USB3_CTX_C_RD_DRX_N3 8 RXA+ TXA+ USB3_CTX_RD_DRX_N3 USB3_CTX_RD_DRX_P3 [38]
CT28 2 1 0.1U_0201_10V K X5R 23
[12] USB3_CTX_DRX_N3 RXA- TXA- USB3_CTX_RD_DRX_N3 [38]

5 PD#_1
10 RXD_EN 7
21 EN_A# NC 14 TEST3
EN_B# NC I2C_EN1

4.99K_0402_1%
25 24

1
GPAD NC

4.7K_0402_5%
www.teknisi-indonesia.com

RT46

RT47
PI3EQX7502AIZDEX_TQFN24_4X4
@ @

2
+3VALW +3VALW
+3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
B B
1

RT29 RT45
RT56 RT55 RT52 RT53 RT23 RT25 RT27 RT54 4.7K_0402_5% 4.7K_0402_5%
4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% @ @

2
@ @ @ @ @ @ @ @
2

P3_B_EQ0 P3_B_EQ1 P3_B_DE0 P3_B_DE1 P3_A_EQ0 P3_A_EQ1 P3_A_DE0 P3_A_DE1 TEST3 PD#_1
1

RT49 RT50 RT51 RT22 RT24 RT26 RT28 RT48 +3VALW

4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
@ @ @ @ @ @ @ @
1
2

RT30
4.7K_0402_5%
@
2

I2C_EN1

A A

Security Classification Compal Secret Data Type-C USB redriver

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiitlle

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Siiize Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-H082P
Date: Monday, October 22, 2018 Sheet 37 o f 53

5 4 3 2 1
 5 4 3 2 1

TYPE-C - CC+MUX (RTS5448-GR) TYPE-C CONNECTOR

Over Current Protection Pin:
+5VALW +VCON_IN_5448 +5VALW +5V_IN_5448 If Over Current Occurred - From High to Low.
+VBUS_5448 +VBUS_5448_R
JT1 @
1 2
RT1 1 2 0_0603_5% RT2 1 2 0_0603_5% +5VALW +VBUS_5448 1 2
JUMP_43X79
+5V_IN_5448
CT22 1 1 CT21
UT3
10U_0402_6.3V6M 10U_0402_6.3V6M
CC1_5448_CONN CC2_5448_CONN SE00000UD00 B1 C2 SE00000UD00
20V_PRTCT@ 2
1 C1 VINT VBUS D1 B2 2 20V_PRTCT@
D +VCON_IN_5448 +LDO_3V3_5448 UT2 CT12 VINT VBUS D2 VINT D
5 1 10U_0402_6.3V6M VBUS
IN OUT
1

1
SE00000UD00
CT3 CT4 OCP_DET_5448_R 3 2 A3
VBUS_EN_5448 4 FLAG 2 +VBUS_5448 A2 ILIM
220P_0402_50V8J 220P_0402_50V8J 1 1 1 1
2

2
CT2 CT1 CT5 CT6 EN(#EN) GND FAULT B3
G517G1TO1U_TSOT23-5 A1 GND C3
0.1U_0201_10V K X5R 4.7U_0402_6.3V6M 10U_0402_6.3V6M 0.1U_0201_10V K X5R
SE00000SO00 SE00000UD00 SA00009XD00 EN GND D3

1
2 2 2 2 GND
1

1
CT11 NX5P3090UK_WLCSP12 RT15
10U_0402_6.3V6M RT14 SA00009LF00 16K_0402_1%
20V_PRTCT@

13

19

20
10K_0201_5%
UT1 2 SE00000UD00 20V_PRTCT@
20V_PRTCT@

2
USB3_MRX_DTX_P2 CT23 1 2 0.1U_0402_6.3V7K USB3_MRX_C_DTX_P2 1

LDO_3V3
5V_IN

2
USB3_MRX_C_DTX_N1 2 C_RX2_1N/2P CC2_5448_CONN

VCON_IN
USB3_MRX_DTX_N1 CT24 1 2 0.1U_0402_6.3V7K 14
USB3_MRX_DTX_P1 USB3_MRX_C_DTX_P1 3 C_RX1_1P/2N CC2 15 VBUS_EN_5448
CT25 1 2 0.1U_0402_6.3V7K USB3_CRX_C_MTX_N3 VBUS_EN 16 OCP_DET_5448
[37] USB3_CRX_RD_DTX_N3 CT19 1 2 0.1U_0201_10V6K 4 C_RX1_1N/2P
CT20 1 2 0.1U_0201_10V6K USB3_CRX_C_MTX_P3 SSRX_1P/2N OCP_DET 17 VMON_5448
[37] USB3_CRX_RD_DTX_P3 USB3_CTX_C_MRX_N3 5 SSRX_1N/2P VMON
CT18 1 2 0.1U_0201_10V6K INPUT 18 RT3 1 REXT 2 6.2K_0402_1%
[37] USB3_CTX_RD_DRX_N3 USB3_CTX_C_MRX_P3 6 SSTX_1P/2N Only limit o n 0.9A
[37] USB3_CTX_RD_DRX_P3 CT17 1 2 0.1U_0201_10V6K USB3_MTX_DRX_N1 7 SSTX_1N/2P
USB3_MTX_C_DRX_N1 CT7 1 2 0.1U_0201_10V6K USB3_MTX_DRX_P1 8 21 TYPEC_LIMIT_CTL1 20 Volts ProtectionCircuit
USB3_MTX_C_DRX_P1 CT8 1 2 0.1U_0201_10V6K 9 C_TX1_1P/2N TYPEC_LIMIT_CTL1 [33]
USB3_MTX_DRX_P2 RP_SEL_M1 22 TYPEC_LIMIT_CTL2
USB3_MTX_C_DRX_P2 CT9 1 2 0.1U_0201_10V6K C_TX1_1N/2P
USB3_MTX_DRX_N2 10 RP_SEL_M0 23
USB3_MTX_C_DRX_N2 CT10 1 2 0.1U_0201_10V6K DIR_SET
11 C_TX2_1N/2P USB3_MRX_C_DTX_N2 CT26 1

1
CC1_5448_CONN NC 24 2 0.1U_0402_6.3V7K USB3_MRX_DTX_N2
12 C_TX2_1P/2N C_RX2_1P/2N 25 RT17 +VBUS_5448_R +VBUS_5448_R
CC1
GND 10K_0201_5%
USB3_MRX_DTX_P2 RT18 1 2 220K_0402_5%
USB3_MRX_DTX_N1 RT19 1 2 220K_0402_5%

2
USB3_MRX_DTX_P1 RT20 1 2 220K_0402_5% RTS5448-GR QFN 24P TYPE-C JUSBC1
USB3_MRX_DTX_N2 SA0000AXR00 A1 B12
RT21 1 2 220K_0402_5% GND GND
USB3_MTX_C_DRX_P1 A2 B11 USB3_MRX_DTX_P1
USB3_MTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 USB3_MRX_DTX_N1
SSTXN1 SSRXN1
CT13 1 2 0.47U_0402_25V6K A4 B9 CT14 1 2 0.47U_0402_25V6K
VBUS VBUS
CC1_5448_CONN
A5 B8
CC1 SBU2

MUX MISC.
USB20_P3_R USB20_N3_R
A6 B7
USB20_N3_R A7 DP1 DN2 B6 USB20_P3_R
C DN1 DP2 C
CC2_5448_CONN
A8 B5
SBU1 CC2
CT15 1 2 0.47U_0402_25V6K CT16 1 2 0.47U_0402_25V6K
A9 B4
VBUS VBUS USB3_MTX_C_DRX_N2
USB3_MRX_DTX_N2
A10 B3 USB3_MTX_C_DRX_P2
USB3_MRX_DTX_P2
+LDO_3V3_5448 +LDO_3V3_5448 A11 SSRXN2 SSTXN2 B2

ESD
SSRXP2 SSTXP2
1 A12 B1
GND GND

2
CT33 +
2

150U_B2_6.3VM_R35M DT5
SGA00001E10 1 4
RT12 RT13 2 GND GND 5 PESD24VS2UT_SOT23-3
DIS@ 2
10K_0201_5% 10K_0201_5% 3 GND GND 6 SCA00000R00
GND GND ESD@
1

1
TYPEC_LIMIT_CTL1 TYPEC_LIMIT_CTL2
DEREN_560Q10-002H

www.teknisi-indonesia.com
SP061806210
ME@
1

RT4 @ RT5 @
10K_0201_5% 10K_0201_5%
2

USB2.0
Rp Configuration
SM070005U00
DLM0NSN900HY2D_4P
4 3 USB20_P3_R
[12] USB20_P3 4 3

1 2 USB20_N3_R
+5V_IN_5448 [12] USB20_N3 1 2
+VBUS_5448 +5V_IN_5448
LT1 EMI@
1

B B
RT6 RT7 RT8

ESD COMPONENTS
200K_0402_1% 4.7K_0402_5% @ 4.7K_0402_5%
2

OCP_DET_5448 1 2 OCP_DET_5448_R
VMON_5448 VBUS_EN_5448
RT16 0_0603_5%
1
1

RT11 @
10K_0201_5% DT1
USB3_MTX_C_DRX_P1 9 10 USB3_MTX_C_DRX_P1
RT9 RT10 1 1
10K_0402_1% 10K_0201_5%
USB3_MTX_C_DRX_N1 USB3_MTX_C_DRX_N1
2

8 9 2 2
2

USB3_MTX_C_DRX_N2 7 7 4 4 USB3_MTX_C_DRX_N2

USB3_MTX_C_DRX_P2 6 6 5 5 USB3_MTX_C_DRX_P2
For C_VBUS For C_VBUS
3 3
(Power Switch Enable Pin) (Power Switch OCP Pin)
8

CESD2510UC3V3U DFN2510 USB3.1

SC300006600
ESD@

DT2 DT4
USB3_MRX_DTX_P1 9 10 USB3_MRX_DTX_P1 USB20_P3_R CC1_5448_CONN
1 1 3 6
I/O2 I/O4
USB3_MRX_DTX_N1 USB3_MRX_DTX_N1
8 9 2 2
USB3_MRX_DTX_N2 7 7 4 4 USB3_MRX_DTX_N2 2 5
GND VDD
USB3_MRX_DTX_P2 6 6 5 5 USB3_MRX_DTX_P2

3 3 CC2_5448_CONN 1 4 USB20_N3_R
A I/O1 I/O3 A
8
CEST236LC5VU-M SOT23-6
SC300006000
ESD@
CESD2510UC3V3U DFN2510 USB3.1
SC300006600
ESD@

Securiiity Clllassiiifiiicatiiion Compalll Secret Data CompaTlyEpele-cCtronics,Inc.

Issued Date 2018/04/09 Deciiiphered Date 2019/04/09 Tiitttlle

THISII SHEET OF ENGINEERINGIIII DRAWINGII ISITHE PROPRIETARYII PROPERTY OF COMPAL ELECTRONICS,,,II INC...II AND CONTAINSII CONFD
I ENTI IALIIAND Siiize Documenttt Numberrr Rev
TRADE SECRET INFORMII ATION...II THISIISHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D DEPARTMENT
Custttom
EXCEPT AS AUTHORIZEDII BY COMPAL ELECTRONICS,,,II INC...II NEITII HER THISII SHEET NOR THE INFORMII ATIONIIITICONTAINSII
MAY BE USED BY OR DISCLOSEDII TO ANY THIRDII PARTY WITI HOUT PRIORII WRITIITEN CONSENT OF COMPAL ELECTRONICS,,,II INC...II
LA-H082P 0..2

Dattte::: Monday,,, Octttoberrr 22,,, 2018 Sheettt 38 o ff53

5 4 3 2 1
 A B C D E

DC to DC

1 1
+3VALW +3VS
J1
2 1
+VL 2 1

0.1U_0201_10V K X5R
JUMP_43X79

0.1U_0201_10V K X5R
1 1
+3VALW to +3VS 1 1

C71

C74
C72 @ @ C73
10U_0402_6.3V6M 10U_0402_6.3V6M
SE00000UD00 SE00000UD00
2 2 2 2
U10
1 14 +3VALW _3VS
2 VIN1 VOUT1 13
VIN1 VOUT1
3 12 C75 1 2 S CER CAP 1000P 50V K X7R 0402
ON1 CT1 SE074102K80
4 11
[13,33,44] SUSP# VBIAS GND +5VS
5 10 C76 1 2 S CER CAP 2200P 25V K X7R 0402
+5VALW ON2 CT2 SE075222K80 J2
6 9 +5VALW _5VS 2 1
7 VIN2 VOUT2 8 2 1
VIN2 VOUT2

0.1U_0201_10V K X5R
JUMP_43X79 1 1
0.1U_0201_10V K X5R

C80
1 1 15 @ C79
GPAD
C77

C78 @ 10U_0402_6.3V6M
10U_0402_6.3V6M S IC G2898KD1U TDFN 14P LOAD SWITCH SE00000UD00
SE00000UD00 SA0000BKC00 2 2
2 2

+5VALW to +5VS

2 2

DISCHARGE CIRCUIT MISC.

www.teknisi-indonesia.com H1
HOLEA
CPU
H2
HOLEA
H3
HOLEA
GPU
H4
HOLEA
H5
HOLEA
WLAN
H6
HOLEA
SSD2
H7
HOLEA
SSD1 FAN
H16 H17 HOLEA
HOLEA
ON/OFF# SHORT PADS
@
JP1 2 1 ON/OFF#
ON/OFF# [33,36]
SHORT PADS

1
H_2P9 H_2P9 H_2P9 H_3P3 H_3P3 H_3P2 H_3P2 H_3P3 H_3P3 @
JP2 2 1 ON/OFF#
For +1.8VALW Discharge
SHORT PADS

3 3
+5VALW +1.8VALW H9 H10 H11 H12 H18 HOLEA HOLEA H13 H14
HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
R129 @ R130 @
100K_0402_1% 22_0603_1%

H_2P5 H_2P5N H_2P5 H_3P7 H_2P8 H_2P5X2P8N H_2P5X2P8

2

2
6

D
1.8VALW_PWR_EN# 2
G

S
DDR Shielding Clip LASER BARCODE
1

@ Q4A
2N7002KDW _SOT363-6 Larger FD1 FD2
CLIP1 CLIP10 CLIP11 CODE1 @ CODE2 @
HOLEA HOLEA HOLEA
3

1
5
[33,36,43,45] 3V/5VALW_PG G @ @ @
1

S FD3 FD4 BARCODE_8X8 BARCODE_12X4

4

@ Q4B
2N7002KDW _SOT363-6

Smaller

1
CODE3 @ CODE4 @
CLIP2 CLIP3 CLIP4 CLIP5 CLIP6 CLIP7 CLIP8 CLIP9 HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA

4 4
@ @ @ @ @ @ @ @
1

1 BARCODE_20X4 BARCODE_10X10

Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
DC to DC / Discharge / MISC
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS Custttom 0..2
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC... LA-H082P
Date: Monday,,, Octttober 22,,, 2018 Sheet 39 o f 53
A B C D E
 5 4 3 2 1

D EMI@ PL1 D
ACES_50278-00401-001
6 PF1
5A_Z80_0805_2P
1 2
+19V_VIN
G2 5
G1 4 7A_32VDC_0437007.W RML
APDIN 1 2 +19V_APDIN
43 EMI@ PL2
3 2 5A_Z80_0805_2P
2 1 1 2

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
1
JDCIN1

1
CONN@

EMI@ PC1

EMI@ PC2

EMI@ PC3

EMI@ PC4
2

2
C C

+CHGRTC
2

PR1 @
45.3K_0603_1%

PR2 0_0603_5%
1

1 2
PD1
+3VL
LRB715FT1G_SOT323-3
2

www.teknisi-indonesia.com
+RTCBATT 1
3
+RTCBATT_R

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiitlle

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
Siiize Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBL
Date: Monday, October 22, 2018 Sheet 40 o f 53
5 4 3 2 1
 5 4 3 2 1

EMI@ PL3
VMB2 +8.4V_VMB 5A_Z80_0805_2P
Conn@ PF2 1 2
JBAT1 F1206HB12V024TM 12A 24V UL FAST
1 1 2
1 2 +12.6V_BATT+
EMI@ PL4
2 3 EC_SMCA 5A_Z80_0805_2P
3 4 EC_SMDA 1 2
4 5
5 6
+RTCBATT_R

1
6 7

1
8

100_0402_1%

100_0402_1%
7
8 9 PC5 EMI@ PC6 EMI@
D 10 1000P_0402_50V7K 0.01U_0402_16V7K D
G1

2
PR4

PR5
G2 11

2
G3 12
G4

ACES_60757-00802-001
EC_SMB_CK1 [33,42]

EC_SMB_DA1 [33,42]
1 2
+3VL
PR6
1 2 200K_0402_1% +3VALW
PR7
@200K_0402_1%
1 2
PR8
VCIN1_BATT_TEMP [33,42] PH201 under CPU botten side :
10K_0402_5%
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

+EC_VCCA

16.5K_0402_1%
1
C C

PR9
2
[33] VCIN0_PH1

1
PH1
100K +-1% 0402 B25/50 4250K

2
www.teknisi-indonesia.com
ECAGND

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiitlle

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
Siiize Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBL
Date: Monday, October 22, 2018 Sheet 41 o f 53
5 4 3 2 1
 A B C D

Module model information

ISL95520A_Hybrid_Boost_V2.mdd +3VS
Pull high on HW side

1
VGA@

1
VGA@ PR1680
Protection for reverse input PR1681 10K_0402_5%
10K_0402_5%

2
2
1 Vgs = 20V VGA@ 1

Vds = 60V PQ1660A

GPU_PROHOT# [24,33]

6
D
Id = 250mA 2
D

1
G

1
2 PQ314 2N7002KDW_SOT363-6
G L2N7002W T1G_SC70-3 S

1
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W B[3+3,42] VCOUT1_PROCHOT#

3
Rds(on) = 15.8mohm max CSR rating: 1W 2 VGA@
1 2 1 2
Vgs = 20V VCSIP-VCSIN spec < 81mV PQ1661
SSM3K35MFV 1N VESM
PR301 PR302 Vds = 30V
1M_0402_1% 3M_0402_5%
PQ311
ID = 10.5A (Ta=70C)

3
EMB04N03H_EDFN5X6-8-5 +19V_P1 PQ312
Need check the SOA for inrush 1 AON7506_DFN33-8-5 PR303
2 1 +19V_P2 0.01_1206_1% +19VB_CHG VGA@
5 3 2 @PJP301 PQ1660B
1 2

3
3 5 1 4 D
+19V_VIN 1 2
5
2 3 JUMP_43X118 G

PC304 EMI@
2200P_0402_25V7K
4
[33,42] VCIN1_AC_IN

10U_0603_25V6

10U_0603_25V6

@EMI@ PC303
0.1U_0402_25V6
2N7002KDW_SOT363-6

2 1
S

CSIP_CHG_R

4
PC301

PC302
CSIN_CHG_R

21
21

21
M

M
2

2
0_0402_5

0_0402_5
PR304

PR305
1
392K_0402_1
PR306

ASGATE_CHG_R @

1%

1%
@
PC305
PQ313
% 2

1 2

4.02K_0402_1%
PR307 4.02K_0402_1%
2
AON7506_DFN33-8-5 2

1
0.1U_0402_25V6

1
1
2
5 3

PR309
PR729 and PR732 are ACDET set t i ng base on your proj ect to se.t 100_0402_1%

2
2

4
PC307 0.47U_0402_25V6K
PR308
1 2 +12.6V_BATT+ Rds(on) = 32mohm max
Vgs = 20V
Vds = 30V
CMSRC_CHG ID = 8A (Ta=70C)
1

@
PC308
2200P_0402_50V7K
49.9K_0402_1

PC306
PR310

ASGATE_CHG

1
1 2

www.teknisi-indonesia.com
2 1

BGATE_CHG
% 2

0.1U_0402_25V6

OPCN_CHG 2
CSIN_CHG
CSIP_CHG

OPCP_CHG
0x3CH <BIT9> PSYS current gain

VBAT_CHG
Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 10m Ω and Rs2 = 10mΩ BIT0 Rds(on) = 32mohm max
VDD_CHG

= 1.14uA/W Vgs = 20V

BIT1 = 0.285uA/W
Vds = 30V

5
=========================================================
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω and Rs2 = 20mΩ ID = 8A (Ta=70C) PQ301
PU301
BIT0 = 2.28uA/W support Turbo boost : 2200P no Support max charge 3.5A

32

31

30

29

28

27

26

25
1

support Turbo boost : 0.1u

100K_0402_1

ISL95520AHRZ-T_QFN32_4X4
BIT1 = 0.57uA/W
AON7408L_DFN8-5 7X7X3 Power loss: 0.245W
PR311

CSR rating: 1W

OPCN

QPCP

BGATE
CSIN
CSIP

ASGATE

CMSRC

VBAT
PC309 4
PR313 0_0603_5% 0.47U_0402_25V6K Isat: 6.5A VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R 1 2 DCR: 28mohm
%
2

Ipsys = KPSYS x ( VAD P x IAD P + VBA T x IBAT ) ACIN BOOT PR315

23 UG_CHG PL301
R_Psys = 1.2V / Ipsys 2 0.01_1206_1%

3
2
1
KPSYS = 1.14uA/W [33,42] VCIN1_AC_IN ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M +12.6V_BATT+
22 LX_CHG +17.4V_BATT_CHG 1
1

adapter wattage = 45W @ PR312 1 2 0_0402_5% 3 1 2 4

[33,41] EC_SMB_DA1 SDA PHASE
158K_0402_1
PR314

Battery wattage = 40Wh 21 LG_CHG

@ PR320 1 2 0_0402_5% 4 2 3
Ipsys = 1.14 x (45+40) = 96.9uA

5
SCL LGATE

1
[33,41] EC_SMB_CK1

4.7_1206_5
PQ302

RF@ PR317
3 R_Psys = 1.2V / 96.9uA = 12.3K-ohm. @ PR316 1 2 0_0402_5% 5 20 VDDP_CHG 3

=====================================
% 2

PROCHOT# VDDP

10U_0603_25V6

10U_0603_25V6

10U_0603_25V6
[33,42] VCOUT1_PROCHOT#
adapter wattage = 65W PR318 1 2 1K_0402_1%AMON_ISL95520 6 19 VDD_CHG 1 2
Battery wattage = 40Wh [33] ADP_I AMON VDD

PC310

PC311

PC312
Ipsys = 1.14 x (65+40) = 119.7uA

2
2 1K_0402_1%BMON_ISL95520 7

21

21

21
PR321 1 18 PR319 4.7_0402_5% 4
BMON DCIN

1
R_Psys = 1.2V / 96.9uA = 10K-ohm.
Close to EC. 8 17 PC313 PC314

BATGONE
PSYS NTC

M
1U_0402_16V6K 1U_0402_16V6K

2
CCLIM

ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET PR323 PC315 RF@

3
2
1

2 1
1
100K_0402_1% AON7506_DFN3X3-8-5 680P_0402_50V7K
1

PC316 PC317
0.1U_0402_25V6 0.1U_0402_25V6 PD301
33

10

11

12

14

15

16
9

13

**Design Notes** Follow adapter and PR324 10_1206_5% 3

+19V_VIN
2

battery wattage in 1 2 1
For 45W/65W /90W system, 2S/3S/4S battery

3
Close to Vsys current source. 2 PQ315
Maximum Charging current 3.5A EC.
VF = 0.38V BA

2
FSET_CHG

PC318
Base on CPU Core VR design.

1U_0603_25V6
Maximum Battery discharge power 55W The resistor is pop on CPU VR schematic. LRB715FT1G_SOT323-3 LMUN5113T1G_SOT323-3
1

#Register Setting 2

1
1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function PR325

2. Disable turbo when AC only 10K_0402_1% A31 connect to BA

VDD=5V VDD_CHG

1
#Circuit Design Other team connect to bat t conn
2

1. ACLIM and CCLIM are devider voltage control.

1
CCLIM_CHG
2.Use 7X7 choke and 3X3 H/L side MOSFET [10,33,45] PM_SLP_S4# 2
200K_0402_1%

Charge current 3A ACLIM_CHG

1

Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W)

PR326

PR327
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R PQ316
200K_0402_1%
Power density : 0.61 (23X16)

BA
3
COMP_CHG
#Protect function PR328 2_0402_5% LTC015EUBFS8TL_UMT3F
1. ACOVP : VCC voltage > 24V
2

1
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default). Fs=729KHZ ~ +/- 15%
100_0402_1

PC319 BA
38.3K_0402_1%
1

3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable). 0.1U_0402_25V6

2
2 PR331 1
PR330

4. CHGOCP : based on charge current setting CSON_CHG CSON_CHG_R

1

1 2
150K_0402_1%

560P_0402_50V7

5. BATOVP : 4.6V/Cell
PR333

6. BATLOWV : No.
PC320

@ PR332
2
2 1
1

% 0.033U_0402_25V7K

0_0402_5%
76.8K_0402_1%

7. TSHUT : 150C
4
1

PR335 For A31 only.

2

348K_0402_1% Turn off Charger IC on battery only.

1

VCIN1_BATT_TEMP [33,41] Depend on customer design for

PC321
PR334

BATGONE(BATT_TEMP) system power consumption.

K
2

logic high: above 2.4V

2

Hybrid boost power mode logic low: under 0.8V

Cell = 4s
(Rs1 = 10mΩ and Rs2 = 5mΩ or Rs 1 = 20m Ω and Rs2 = 10mΩ).
CC_LIM = VccLIM / 64 x Rs2
=============================================================
(Rs1 = 10mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω and Rs2 = 20mΩ).
Securiiity Clllassiiifiiicatiiion Compal Secret Data Compal Electronics, Inc.
2014/11/05 2014/12/15 Tiiitttlle
CC_LIM = VccLIM / 32 x Rs2
=============================================================
Battery current limimed by CCLIm ~ 3.89A.
Issued Date Decipherii ed Dae
t
PWR_CHARGER
AC_LIM = Vac_LIM / 32 x Rs1 Adapter current limimed by ACLIm ~ 4.33A.
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL
Siiize DocumentttNumber Re v
AND TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
(PR779 and PQ741 are for change ACLIm when AC in) DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS 0..1
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Dattte::: Monday,,, Octttober 22,,, 2018 Sheett 42 o ff 53
A B C D
 A B C D E

Module model information

SY8286B_V3_single.mdd B+
EMI@ PL401 keep short pad,
SY8286B_V3_dual.mdd 5A_Z80_0805_2P snubber is for EMI only.
+19VB_3V

2200P_0402_50V7K
1 2

10U_0603_25V6M
@EMI@ PC402
0.1U_0402_25V6
1

1
EMI@ PC403
@ PR401 PC401

PC404
0_0402_5% 0.1U_0402_25V6
BST_3V 1 2 BST_3V_R 1 2

2
Use 7x7x3 size when the layout space is enough.
1 1

1
BS
IN3

IN2

IN1
+3VL
LX_3V 5 17 PL402
LX EP 1.5UH_6A_20%_5X5X3_M
Check pull up resistor of SPOK at HW side PU401

1
SY8386BRHC_QFN16_2P5X2P5 16 LX_3V 1 4
6
LX2 +3VALWP
PR403 GND 2 3
100K_0402_5% 15

4.7_1206_5%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
LX1

1
RF@
PR402
2
7

PC405

PC406

PC407

PC408
[33,36,39,45] 3V/5VALW_PG PG 14

2
GND1

SN
3V_2
Fsw : 600K Hz EN1 and EN2 dont't be floating. ENLDO_3V5V 8 13

4.7U_0402_6.3V6M
EN2 LDO +3VLP
EN :H>0.8V ; L<0.4V

1
PC409
TEST
OUT
EN1

1
@ PC410

FF
4.7U_0402_6.3V6M PC411 RF@ Vout is 3.234V~3.366V

2
2

1
680P_0402_50V7K

2
10

11

12
Iocp=10A
TDC=6A
3.3V LDO 150mA~300mA

2 PC412 PR404 2
1000P_0402_50V7K 1K_0402_1%
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

@PJ401
1 2
+3VALWP 1 2 +3VALW

www.teknisi-indonesia.com
keep short pad, JUMP_43X118
snubber is for EMI only.
@PJP401
JUMP_43X39
B+ EMI@ PL403 +19VB_5V @ PR405 PC413 1 2
5A_Z80_0805_2P 0_0402_5% 0.1U_0402_25V6 +3VLP 1 2 +3VL
+19VB_5V BST_5V1 2 BST_5V_R 1 2
1 2
PU402
5

1
SY8288CRAC_QFN20_3X3
IN

IN

IN

IN

BS
PL404
LX_5V 6 20
10U_0603_25V6M

10U_0603_25V6M

2200P_0402_50V7K

2.2UH_7.8A_20%_7X7X3_M
0.1U_0402_25V6

LX LX
7 19 LX_5V
GND LX
1 4 +5VALWP
1

1
PC414

PC415

EMI@ PC416

@EMI@ PC417

8 18 2 3 @
GND GND PC418

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

1
1

1
3 @ 9 17 VCC_5V1 2 3
PG VCC

1
2SPOK_5V

PC9174

PC9183

PC9173

PC9175

PC9186

PC9176
4.7_1206_5%
RF@ PR409
10 16

2
2

2
NC NC 2.2U_0402_6.3V6M
OUT

LDO
EN2

EN1

21
FF

GND

2
11

12

13

14

15
@

PR407
Module model information 0_0402_5%

15V_SN
1

3V/5VALW_PG
SY8286C_V3_single.mdd +5VLP
SY8286C_V3_dual.mdd ENLDO_3V5V 5V LDO 150mA~300mA PC9177 RF@
4.7U_0402_6.3V6M

680P_0402_50V7K

2
Vout is 4.998V~5.202V
1

PC425

5V_3V_EN
2

PR410
499K_0402_1%
TDC=8A
1 2 ENLDO_3V5V
B+ EN1 and EN2 dont't be floating.
1

EN :H>0.8V ; L<0.4V PC427 PR408

1

PR411 1000P_0402_25V8J 1K_0402_1%

150K_0402_1% PC434 Fsw : 600K Hz 5V_FB 1 2 5V_FB_1 1 2
1U_0201_6.3V6M
2
2

@ PJ402
1 2
PR412 +5VALWP 12 +5VALW
2.2K_0402_5% JUMP_43X118
1 2
4 [33] EC_ON @PJP402 4
JUMP_43X39
1 2 1 2
[33] VCOUT0_MAIN_PWR_ON +5VLP 1 2 +VL
@

PR413
5V_3V_EN
0_0402_5%
1M_0402_1%

4.7U_0402_6.3V6M

Security Classification Compal Secret Data Compal Electronics, Inc.

1

1
PR415

PC438

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiitlle

+3VALW/+5VALW
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Siiize Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 22, 2018 Sheet 43 o f 53
A B C D E
 5 4 3 2 1

Module model information

RT8207P_single_V3.mdd For Single layer
RT8207P_dual_V3.mdd For Dual layer

D D

Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
B+ 5A_Z80_0805_2P
+12.6VB_DDR Peak Current 1A
1 2 PR501
2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
+1.2VP

0.1U_0402_25V

2200P_0402_50V7

10U_0603_25V6

10U_0603_25V6
M PC503

M PC504
1

1
@EMI@PC501

EMI@PC502
UG_DDR +0.6VSP
2

2
6
LX_DDR

10U_0402_6.3V6

10U_0402_6.3V6

10U_0402_6.3V6
1

1
PC505

5
0.1U_0402_25V6

PC506

PC507

PC508
16

17

18

19

20
2
C PU501 C

2
PQ501

BOOT

VLDOIN

VTT
UGATE
PHASE
21 @
AON7408L_DFN8-5 PAD

M
4 LG_DDR 15 1
LGATE VTTGND

PL502 14 2
1UH_11A_20%_7X7X3_M PR502 PGND VTTSNS

1
2
3
14.7K_0402_1%
1 4 1 2 CS_DDR 13 3
+1.2VP PC509 CS RT8207PGQW_WQFN20_3X3 GND

www.teknisi-indonesia.com
1

2 3 1U_0201_6.3V6K

5
1 2 12 4 VTTREF_DDR
VDDP VTTREF
22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

RF@ PR503 30MA_30V_0.5UA_0.4V_SOD323-2 PD501

1

4.7_1206_5% PR504 2 1
PC512

PC510

PC513

PC514

PC511

PC515

5.1_0603_5% 11 5
+1.2VP
2

VDD VDDQ

1
1 2 VDD_DDR

PGOOD
+5VALW
2

4 PC516
+5VALW PR505

TON
1

1
0.033U_0402_16V7K

FB
S5

S3

2
M

RF@ PC518 PQ502 PC517 1 2

680P_0402_50V7K 1U_0201_6.3V6K 2.2_0603_5%
2

10

6
1
2
3

AON7506_DFN3X3-8-5

EN_DDR

FB_DDR
EN_0.675VSP
TON_DDR
PR506
1 2 +1.2VP
PR507 470K_0402_1%
B +12.6VB_DDR1 2 B
6.04K_0402_1%

1
@
PR508
0_0402_5%
Choke: 7x7x3 1 2 PR509
[13,33] SYSON
Rdc=6.7mohm(Typ), 7.4mohm(Max) 10K_0402_1%

2
Mode Level +0.675VSP VTTREF_1.35V

1
@ PC519
Switching Frequency:540kHz
S5 L off off 0.1U_0402_10V7K
Ipeak=8A
S3 L off on

2
Iocp~9.6A
S0 H on on OVP: 113%~120% @ PR510
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.3545V 0_0402_5%
1 2
[13,33,39] SUSP#
@PJ501
1 2

@
PR511 +1.2VP +1.2V
1 2
0_0402_5%
1 2 JUMP_43X118
[7] DDR_VTT_PG_CTRL

1
@ PC520
0.1U_0402_10V7K

2
PJ50@2
1 2
+0.6VSP 1 2 +0.6VS
A
JUMP_43X39 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/04/09 Tiiitllle
2018/04/09 Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
RT8207P
SiiizeDocument Number Re v
LA-H082P
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 22, 2018 Sheet 44 of 53
5 4 3 2 1
 5 4 3 2 1

Module model information

APL5930_V2.mdd

D D

+3VALW +5VALW

Ultra Low Dropout 0.23V(typical) at 3A Output Current

2
1
PC601
JUMP_43X79
2.2U_0201_6.3V6M

1
@ PJ601

2
2

11
PU601 G9661MRE1U_TDFN10_3X3

10U_0402_6.3V6M
1
1
C @ PC602 10 1 C

GND
9 VPP NC 2

PC603
4.7U_0402_6.3V6M PJ602
NC VO 3
+1.8VALWP
@

PR601 8 @

2
2
VIN VO 4

1
0_0402_5% 7 +1.8VALWP 1 2 +1.8VALW

12.7K_0402_1%

0.01U_0402_16V7K
VIN ADJ 5 1 2

1
1 2 6
[33,36,39,43] 3V/5VALW_PG VEN POK JUMP_43X79

PR602

PC604

22U_0603_6.3V6M
Rup

2
1

1
0.1U_0402_16V7K

2
PR603

PC605

PC606
1M_0402_5%

2
@
2

1
PGOOD [46]

10K_0402_1%
PR605
Rdown

2
100K_0402_5%

2
www.teknisi-indonesia.com

PR604

1
Vout=0.8V* (1+Rup/Rdown)

+3VALW +5VALW +3VALW

B B
1

2
1

PC607
JUMP_43X79
2.2U_0201_6.3V6M
1

@ PJ603
2

Vout=0.8V* (1+Rup/Rdown)
2

PU602
G9661MF11U_SO8
10U_0402_6.3V6M
1

@ PC608 4 5
3 VPP NC 6
PC609

4.7U_0402_6.3V6M
VIN VO
+2.5VP
@

PR606 2 7
GND
2

VEN ADJ

1
0_0402_5% 1 8

3.4K_0402_1%

0.01U_0402_16V7K
POK GND

1
1 2
[10,33,42] PM_SLP_S4#

PR607

PC610

22U_0603_6.3V6M
9

Rup

2
1

1
1

0.1U_0402_16V7K

2
PC611

PC612
PR608
47K_0402_5% PJ604 @
2

2
1 2
+2.5VP +2.5V
2

1 2
1

1.6K_0402_1%
JUMP_43X79
PR609

Rdown
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle
APL5930
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

LA-H082P
Siiize Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KBL 0.1

Date: Monday, October 22, 2018 Sheet 45 of 53

5 4 3 2 1
 A B C D E

Module model information

SY8286_V2_single.mdd
SY8286_V2_dual.mdd

keep short pad,

+19VB_1V snubber is for EMI only.

1 1
@PR703 PC704
@PJ701 0_0402_5% 0.1U_0402_25V6
1 2 +19VB_1V BST_1V 1 2 BST_1V_R 1 2
+19VB_CPU 12

0.1U_0402_25V

10U_0603_25V6
JUMP_43X79

1
1
2200P_0402_50V
EMI@ PC701

@EMI@ PC703
RF@ PR702 RF@ PC702

PC705
2 1
4.7_1206_5% 680P_0402_50V7K

1
PU701 1 2 SNUB_1V 12

IN3

IN2

IN1

BS
6

M
Use 7x7x3 size when the layout space is enough.

7K
+3VALW LX_1V 5 17
LX EP
Confirm HW side PL701

+1.05VALWP
1

SY8386RHC_QFN16_2P5X2P5 16 LX_1V 1 2
@ PR701 6 LX2
GND 1UH_6.6A_20%_5X5X3_M
100K_0402_5%

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6

22U_0603_6.3V6
15
LX1

PC707

PC708

PC709

PC710
2

7
PG

2 1

2 1

2 1

2 1
14
GND1

330P_0402_50V
LDO_3V

M
8 13

PC706
TEST VCC

2 1
ILMT

BYP
PC711

EN

FB

1 2
4.7U_0402_6.3V6M
+3VALW

7K
10

11

12
9

16.5K_0402_1
@

PR705
0_0402_5% R1

PR704

1
2 EN_1V
[45] PGOOD 1
Vout=0.6V* (1+R1/R2)

1
PR706
=0.6*(1+(16.5/22))

2
1

%
@PC712 PC713 1K_0402_1%
PR707 0.1U_0402_25V6 2.2U_0201_6.3V6M

2
2 1

2 1M_0402_1% Vout=1.05V 2

+3VALW
2

EN :H>0.8V ; L<0.4V
FB_1V @ PJ702
EN pin don't floating
1

JUMP_43X118
If have pull down resistor at HW side, FB=0.6V
@

PR709 1 2
+1.05VALWP 12 +1.05VALW
0_0402_5%
please delete PR601.

1
2

ILMT_1V
R2 PR708
1

22K_0402_1%
@ PR710

2
www.teknisi-indonesia.com
0_0402_5%
2

The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high.

+1.2V +5VALW
3 3

Ultra Low Dropout 0.23V(typical) at 3A Output Current

1

2.2U_0201_6.3V6

@ PJ703
2 1
VGA@ PC714
21

JUMP_43X39
2

VGA@
11

PU702 G9661MRE1U_TDFN10_3X3
1

VGA@ PC715 10 1
GND

10U_0402_6.3V6M 9 VPP NC 2
@VGA@ PR711 8 NC VO 3
2

0_0402_5% 7 VIN VO 4 +1.0VS

6 VIN ADJ 5
1

1 2
[26] 1.0VS_DGPU_EN VEN POK
VGA@ PR713

10K_0402_1

0.01U_0402_25V

22U_0603_6.3V6M
2 1
1

Rup
VGA@ PC717

VGA@ PR712
0.1U_0402_25
@ PC716

@PJ704
2
2 1

PC718

1M_0402_5%
2 1

+1.0VS 1 2 +1.0VS_DGPU
7K

12
2

JUMP_43X39
1
V6

VGA@
38.3K_0402_1%
VGA@ PR714

Rdown
2

4 4

Vout=0.8V* (1+Rup/Rdown)
=0.8*(1+(10/38.3))
Vout=1.008V

Securiiity Clllassiiifiiicatiiion
2018/04/09
Compal Secret Data
2019/04/09 Tiiitttllle
Compal Electronics, Inc.
Issued Date Decipherii ed Dae
t
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
SY8286
LA-H082P
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT Siiize Documenttt Number Rev
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS C 0..1
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
Dattte::: Monday,,, Octttober 22,,, 2018 Sheettt 46 o ff 53
A B C D E
 1 2 3 4 5

Module model information

Close IC
PRZ1 and PRZ22 are for debug only. RT3602AE_U22_RU42_colay_V1A.mdd for IC portion
VCCSSA_SENSE and VSSSA_SENSE need other resistor at HW side.
RT3602AE_U22_RU42_colay_V1B.mdd for SW portion
RT3602_VREF Vref=0.6V +VCCSA PRZ1 PRZ8 PRZ10
100_0402_1% VCCSA_SENSE_R 10K_0402_1% 54.9K_0402_1% PCZ3
1 2 1 2 1 2 0.1U_0402_25V6

1
953_0402_1%

15K_0402_1%

6.8K_04 02_1%
PRZ15 1 2 12

2
1

1
1

1
1 2
[13] VCCSA_SENSE [48] AVCCSA AISPVCCSA [48]
@PCZ200 PCZ5 390P_0402_50V7K PCZ6 68P_0402_50V8J
PRZ2

PRZ3

PRZ4
0_0402_5% 0.1U_0402_25V6

2
A @ PCZ1 @PRZ16 A

FB_SA FB_SA
0.1U_0402_10V6K 10K_0402_1% @ PCZ4
2

1
1 2 1 2 0.47U_0402_25V6K
1 2

1 2
@PCZ203 1 2
1

11K_0402_1%

0.1U_0402_25V6

10_0402_1%
5K_0402_1%

Close IC RT3602_VREF

0.47U_0402_25V6K
PRZ94
PRZ6

PRZ11

PCZ208
1
0_0402_5% 1 2 1 2
PRZ5

1 2
[13] VSSSA_SENSE PRZ14
PRZ13
RT3602_SET1
2

2
1
PRZ22 29.4K_0402_1% 21K_0402_1%
RT3602_SET2
RT3602_SET3
1 2 @PCZ199 Close IC
0.1U_0402_25V6

1
100_0402_1% PRZ95

PRZ24
RT3602_VREF 3.9_0402_1%
VR_PSYS 0_0402_5%
PRZ23 +3VS
1

[15] VSSCORE_SENSE 1 2 100K_0402_1%

Close CORE1 choke
10K_0402_1

1 2
PRZ20
499_0402_1% 5.23K_0402_1%

PRZ19
PRZ18

2.1K_0402_1% 1.1K_0402_1%

2
PRZ17

EN
3K_0402_1% 464_0402_1%

PRZ21 VR_PWRGD [33]

@ PRZ107 PHZ1 PRZ26 1 2
High: > 0.7V
2
2

0_0402_5% 100K_0402_1%_B25/50 4250K 40.2K_0402_1%

%

PRZ25
2PHZ1_R1 1 2 PHZ1_R 1
@ PCZ7
RGND_MAIN
1 2 100_0402_1% 0_0402_5%
Low: < 0.3V
12

12

0.1U_0402_25V6 1 2 VR_ON [33]

RT3602_VREF
2
1

+1.05V_VCCST

IMON_SA
PRZ30
PRZ29

1 2 IMON_CORE_R 1 2

RT3602_EN
PRZ28

VSEN_CORE
PRZ33 RGND_MAIN

FB_SA

COMP_SA
RGND_SA
VR_PSYS
26.7K_0402_1% PRZ35 @ PCZ206
2

@ PCZ204 2.8K_0402_1% @ PCZ201 0.1U_0402_25V6

PCZ194
0.1U_0402_25V6
1
1

1
110_0402_1
0.1U_0402_25V6 0.1U_0402_25V6 1 2

2 1

2 1
75_0402_1
45.3_0402_1

100_0402_1
U22@ PRZ45 @ PCZ9

PRZ37

PRZ39
2 1

@ PCZ8 @PRZ40 46.4K_0402_1% 0.1U_0402_10V6K

0.1U_0402_10V6K 10K_0402_1% PUZ1

40
48

39
1 2

47
46
45
44
43
42
41
49

PRZ36

PRZ38
IMON_SA 38
Close IC

%
1 2 1 2 RT3602AJGQW_WQFN48_6X6 @ @

VR_READY 37

%
2

2
%
U42@ PRZ45

FB_SA

VREF06/PSET
PRZ43

PSYS
VSEN_MAIN

RGND_SA
COMP_SA
RGND_MAIN

%
EN
GND

ISENP_SA
ISENN_SA
10K_0402_1% 61.9K_0402_1% VR_SVID_CLK [15]
VSEN_CORE 1 2 1 2 VR_ALERT# [15]
+VCC_CORE PRZ41
VR_SVID_DATA [15]
100_0402_1% PCZ12 82P_0402_50V8J IMON_CORE 1 36
RT3602_SET12 IMON_MAIN PW M_SA 35 PWM_SA [48]
1 2 1 2 1 2 VR_HOT# [33]
FB_CORE SET1 DRVEN DRVEN [48]
PRZ47 3 34 1 2
0_0402_5% PCZ13 COMP_CORE 4 FB_MAIN VCLK 33 PRZ98
49.9_0402_1% RT3602_VREF
PCZ11 330P_0402_50V8J [48] AVCORE1 RT3602_SET2 5 COMP_MAIN ALERT
[15] VCCCORE_SENSE
1 2 0.1U_0402_25V6
1 2
Ra RT3602_SET3 6 SET2
32
VDIO 31
PRZ991 210_0402_1%
PR1Z100 100_20402_1%
PRZ48
28K_0402_1% PRZ49 7.68K_0402_1%
IMON_GT
7 SET3 VR_HOT 30
Close IC
1

U42@ PRZ106 1 21 2
@ PCZ196 1 2 1 2 ISEN1N_MAIN 8 ISEN1N_MAIN IMON_AUXI 29 @ PCZ15 0.47U_0402_25V6K
0.1U_0402_25V6 0_0402_5% 9 ISEN2N_MAIN ISENP_AUXI 28 12
10 ISEN2P_MAIN ISENN_AUXI 27 VSEN_GT
2

[48] AVCORE2 U42@ PCZ16 0.1U_0402_25V6

TSEN_CORE 11 ISEN1P_MAIN VSEN_AUXI 26 COMP_GT PRZ50
RT3602_VIN12 TSEN_MAIN COMP_AUXI 25 AISP1 [48]
Rb VIN RGND_AUXI AVGT1 [48] 0_0402_5%

19 DRVEN_SET
B 1 2 B

DRVEN_SET 18 PW M1_MAIN
+5VALW

17 PW M2_MAIN
VSEN_GT

RGND_AUXI
U22@ PRZ105 10K_0402_1% 12 1 2
VCCGT_SENSE [15]

0.22U_0402_25V6K

FB_AUXI
1

1
PCZ18

PW M_AUXI
24 TSEN_AUXI
[48] AISPCORE2
PRZ41 and PRZ21 are for debug only. PRZ59

2.2_0805_1
0.1U_0402_25V6 PRZ54 PRZ56
100_0402_1% +VCC_GT

VCC
Rc 24.3K_0402_1% 10K_0402_1%

NC
16 NC

20 NC
VCCCORE_SENSE and VSSCORE_SENSE need other resistor

PRZ53

PCZ19
2
1 2

21 CN
22 N
C
1 2 1 2 1 2
+5VALW
at HW side. U22@ PRZ104 10K_0402_1%

15
14
2

13
%

TSEN_GT23
[48] AISPCORE1
1 2 12 @ PCZ198
RT3602_VREF

2 1
Ra Rb/Rc PRZ51 PRZ52

FB_GT
0.1U_0402_25V6

RT3602_VCC
TSEN_CORE_R 110K_0402_1% 1.65K_0402_1% PCZ20 82P_0402_50V8J PCZ21 270P_0402_50V7K
1 2 1 2
+19VB_CPU
PHZ2
U22 N/A Stuff

1
1 2 1 2 12
@ PCZ202
1

FB_GT
@ PRZ61 @PCZ22 0.1U_0402_25V6
100K_0402_1%_B25/50 4250K
Stuff N/A

2
U42 10K_0402_1% 0.1U_0402_10V6K
PRZ64

Close CORE1 MOSFET

[48]
PRZ63

PWM_G
T [48]
+5VALW PRZ65 Close IC

[48]
PWM_CORE2
PWM_CORE1
2

8.2_0402_1%

www.teknisi-indonesia.com
4.02K_0402_1% 19.1K_0402_1% 4.64K_0402_1% 8.25K_0402_1%
1 2
11.5K_0402_1% 5.62K_0402_1% 7.68K_0402_1% 8.25K_0402_1%

1 2
PRZ93
1

U22@ PRZ68 1 2
VSSGT_SENSE [15]
U42@ PRZ68

1K_0402_1%
PRZ67

+5VALW 0_0402_5%

1
PCZ207

2 1
2

4.7U_0402_6.3V6M PRZ66
TSEN_CORE_R TSEN_GT_R
110K_0402_1% @ PCZ197 PRZ60

2 1
1
0.1U_0402_25V6 100_0402_1%

100K_0402_1%_B25/504250K
1

2
1

@ PRZ72
U42@ PRZ71

10K_0402_5%

12
U22@ PRZ71
PRZ70

2
71.5K_0402_1%

PHZ3
DRVEN_SET PRZ69
1.65K_0402_1%
12
12

12

2
PRZ108
10K_0402_5%
PRZ109

Close GT MOSFET
PRZ73

PRZ59 and PRZ60 are for debug only.

TSEN_GT_R
2

VCCGT_SENSE and VSSGT_SENSE need other resistor

2

at HW side.
C
Set DRVEN output function at PS4. Set to 5V DRVEN C
is floating, and set to GND DRVEN is low at PS4.

D D

Securiiittty Clllassifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

2016/09/01 2019/09/01 Tiittle
IIIssued Dattte Deciiiphererr d Dattte
CPU_CORE
THISII SHEET OF ENGINII EERINII G DRAWINIIG ISITHE PROPRIETII ARY PROPERTY OF COMPAL ELECTRONICS,,,II INIC...AND CONTAINSII CONFIDENTIIALIIAND TRADE SECRET INFII
Siiize Documenttt Numberrr Re v
LA-H082P
ORMATION...II THISII SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONIIIIIIOF R&D DEPARTMENT EXCEPT AS AUTHORIZII ED
BY COMPAL ELECTRONICII S,,,INCI...NEITIIHER THISII SHEET NOR THE INIFORMATIONII ITICONTAINII S
MAY BE USED BY OR DISCIILOSED TO ANY THIRDII PARTY WITIIHOUT PRIORII WRITIITEN CONSENT OF COMPAL ELECTRONICII S,,,INC I ... 0...2
Dattte::: Monday,,, Octttoberrr 22,,, 2018 Sheettt 47 o ff 53
1 2 3 4 5
 5 4 3 2 1

PUZ4 U42@
11 10 +19VB_CPU
PUZ2 EMI@ PLZ1 5A_Z80_0805_2P B+ 12 SW PGND 9
11 10 +19VB_CPU SW VIN U42@
12 SW PGND 9 13 8 PCZ29
SW VIN 1 2 GL VIN
PCZ23 U42@ 0.1U_0402_25V6
13 8 +5VALW PRZ77 14 7 1 2

2200P_0402_50V7K
GL VIN 0.1U_0402_25V6 15 PGND PHASE 6
1 2

EMIU42@ PCZ31

10U_0603_25V6M

10U_0603_25V6M
PVCC N/C

@EMIU42@ PCZ30
+5VALW

0.1U_0402_25V6
PRZ76 14 7 1 2 CORE1_BST_R 1 2

10U_0603_25V6

10U_0603_25V6
2200P_0402_50V7K
1 2 15 PGND PHASE 6 16 5 CORE2_BST 2 1CORE2_BST_R
5.1_0402_1%

PCZ34

PCZ35
1 1 1

10U_0603_25V6M

U42@ PCZ32

U42@ PCZ33
PVCC N/C 17 N/C BOOT 4

33U_D2_25VM_R60M

33U_D2_25VM_R60M

33U_D2_25VM_R60M
0.1U_0402_25V6
@EMI@ PCZ28
EMI@ PLZ2 5A_Z80_0805_2P

10U_0603_25V6
EMI@ PCZ24
CORE1_BST N/C AGND

2 1
+ + +

21

21

21

21
5.1_0402_1% 16 5 21 U42@ PRZ75 2.2_0603_5%

2
PCZ25

PCZ26

PCZ51

PCZ52

PCZ53
17 N/C BOOT 4

2 1
PCZ37 3

2 1
N/C AGND VCC 2 DRVEN U42@

2 1

21

21
PRZ74 2.2_0603_5% 18 @ @
1U_0402_10V6K 19 GL FCCM 1

M
3 2 2 2
PCZ36 18 VCC 2 AGND PW M
2 1

19 GL FCCM 1

M
1U_0402_10V6K AOZ5038QI-05 QFN 31P_5X5
AGND PW M
D D
AOZ5038QI-05 QFN 31P_5X5

Rdc=0.9mohm +VCC_CORE
[47] PWM_CORE2
[47] PWM_CORE1 Rdc=0.9 mohm +VCC_CORE CORE2_LX 1
PLZ4
4
[47] DRVEN PLZ3
CORE1_LX 1 4 2 3
+5VALW
2 3
PRZ88 1 PRZ89 2 0.15UH_NA 35A_20%

AISPCORE2_R
4.7_1206_5%
RF@ PRZ78
+5VALW

1
U42@
1 2 5.1_0402_1%

4.7_1206_5%
0.15UH_NA 35A_20%

1
U42RF@ PRZ80
U42@

AISPCORE1_R
U42@
5.1_0402_1%
PCZ61 U42@ PCZ39
0.1U_0402_25V6K

1CORE2_S2NUB
2 1
PCZ38 1U_0402_10V6K 12 1 2 12

1CORE1_SNUB 2
PCZ50
0.1U_0402_25V6K
2 1
1U_0402_10V6K 1 2 1 2 1 2 PRZ82 PRZ83 PRZ85
750_0402_1% 750_0402_1% 10_0402_1%
PRZ79 PRZ81 @ PRZ84 U42@ U42@ 1 2
750_0402_1% 750_0402_1% 560_0402_1%
1 2 PCZ41 U42RF@ @U42@
680P_0402_50V7K

2
PCZ40 RF@
680P_0402_50V7K

2
AVCORE2 [47]

AVCORE1 [47]
AISPCORE2 [47]

AISPCORE1 [47]

H/S AON6280:
R DS(ON) (at V GS =10V) < 6.8m
R DS(ON) (at V GS =4.5V) < 10.5m

L/S AON6214:
R DS(ON) (at V GS =10V) < 2.8m?
R DS(ON) (at V GS =4.5V) < 3.5m?
C C

+19VB_CPU
VCC_CORE VCC_GT VCC_SA
FSW=450kHz FSW=450kHz FSW=600kHz
Choke=0.15uH Choke=0.15uH DCR=6.2 mohm +/- 5%
PRG1 DCR=0.9 mohm +/- 5% DCR=0.9 mohm +/- 5%

2200P_0402_50V7K
2.2_0603_5%
U22

10U_0603_25V6M
GT_BST GT_BST_R

0.1U_0402_25V6
@EMI@ PCG2
1 2

10U_0603_25V6
EMI@ PCG3
U22 U22

PCG4

PCG5
LL=10.3 mohm

2 1
1

PUG1
LL=2.4 mohm LL=3.1 mohm

2 1

21

21
RT9610CGQW_WDFN8_2X2 PCG1
TDC=4A
0.1U_0402_25V6 TDC=21A TDC=18A ICCMAX=5A
2

GT_UG

M
4
BOOT UGATE
3 PQG1 ICCMAX=32A ICCMAX=31A OCP=10A

www.teknisi-indonesia.com
[47] PWM_GT
5
PW M PHASE
2 GT_LX OCP=40A OCP=39A
2

+5VALW DRVEN 1 6
Rdc=0.9 mohm U42
EN PGND
U42 U42
D1

G1

+VCC_GT
1 PRG2 2 VCC_GT PLG1 LL=10.3 mohm
8
VCC LGATE 9
7
7 GT_LX 1 4
LL=2.4 mohm LL=3.1 mohm TDC=4A
1_0402_5% GND D2/S1
TDC=42A TDC=12A ICCMAX=5A
2 3
ICCMAX=64A ICCMAX=28A OCP=10A
G2
S2

S2

S2

4.7_1206_5%
RF@ PRG3

PCG6
0.15UH_NA 35A_20% OCP=70A OCP=39A
2 1

4.7U_0402_6.3V6M AON6962_DFN5X6D-8-7
3

AISP1_R
2

PRG4 PRG5 PCG7

1K_0402_1% 1K_0402_1% 0.1U_0402_25V6K
1 2 1 2 1 2
1GT_SNUB

PRG6 PRG7
2.61K_0402_1% 10K_0402_1%
GT_LG
1 2 1 2

AVGT1_R
PCG8 RF@
680P_0402_50V7K
2

1 2

PHG1
10K_0402_1%_B25/50 3370K
B AVGT1 [47] B

AISP1 [47]

+19VB_CPU
2200P_0402_50V7K

PRA1
10U_0603_25V6M

@EMI@ PCA3
0.1U_0402_25V6

2.2_0603_5%
10U_0603_25V6

SA_BST SA_BST_R
EMI@ PCA5

1 2
PCA1

PCA2
1

2 1

2 1
21

21

PUA1
RT9610CGQW_WDFN8_2X2 PCA4
0.1U_0402_25V6
2

4 3 SA_UG SA_UG_R
BOOT UGATE
5 2 SA_LX
[47] PWM_SA PW M PHASE
Rdc=0.98 mohm
1

+5VALW DRVEN 1 6 PQA1

D1

D1

D1
G1

EN PGND +VCCSA
AONH36334_DFN3X3A8-10
1 2 VCC_SA 8 7 PLA1
VCC LGATE 9 9 10 1 4
PRA2 1_0402_5% GND D2/S1 D1
2 3
G2

S2

S2

S2

4.7_1206_5%
1
RF@ PRA3

PCA6
2 1

0.47UH_NA 12.2A_20%
4.7U_0402_6.3V6M
8

AISPVCCSA_R

SA_LG
2

PCA7
0.1U_0402_25V6K
SA_SNUB

1 2 1 2 1 2

PRA4 PRA5 PRA6 PRA7

A 787_0402_1% 787_0402_1% 825_0402_1% 1K_0402_1% A
1 2 1 2
AVCCSA_R
1

PCA8 RF@
680P_0402_50V7K
2

1 2

PHA1
1K_0402_5%_TSM0B102J3652RE

AVCCSA [47]

SecuriiitttyClllassifffiiicatttiiion Compalll Secret Data Compal Electronics, Inc.

AISPVCCSA [47] Tiitttlle
IIIssued Dattte 2018/04/09 Deciphered Datett 2019/04/09
CPU Power stage

LA-H082P
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIISTHE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC...AND CONTAIIINS CONFIIIDENTIIIAL AND
TRAD E SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETEN T DIIIVIIISIIION OF R&D
Siiize Documenttt Numberrr Rev
DEPARTMEN T EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS 0...1
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
Dattte::: Monday,,, Octttoberrr 22,,,2018 Sheettt 48 offf 53
5 4 3 2 1
 1

0..1
Rev

49 o ff53
Compal Electronics, Inc.

Sheett
LA-H082P
E

E
PowerTrain

Dattte::: Monday,,, Octttober 22,,, 2018

Siiize Documenttt Number
+VCCSA

PC9079
1U_0201_4V6
M
1 2
PC9078
Tiiitttllle

PC9164 PC9052 1U_0201_4V6

22U_0603_6.3V6 22U_0603_6.3V6 M
C

M M 1 2
1 2 1 2 PC9077
PC9165 PC9051 1U_0201_4V6
22uF_0603*10

22U_0603_6.3V6 22U_0603_6.3V6 M
22uF_0603*2

M M 1 2
1 2 1 2 PC9076
1uF_0201*7

PC9162 PC9050 1U_0201_4V6

TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIIISIIION OF R&D DEPARTMENT
@

22U_0603_6.3V6 22U_0603_6.3V6 M
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IINC... AND CONTAIIINS CONFIIIDENTIIIAL AND

M M 1 2
1 2 1 2 PC9075
2018/11/04

PC9163 PC9049 1U_0201_4V6

unpop:

22U_0603_6.3V6 22U_0603_6.3V6 M
M M 1 2
1 2 1 2 PC9074
pop:

MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIOR WRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IINC...
PC9022 PC9048 1U_0201_4V6
@

22U_0603_6.3V6 22U_0603_6.3V6 M
M M 1 2
SA

PC9073
EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IINC...NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIT CONTAIIINS
1 2 1 2
PC9021 PC9047 1U_0201_4V6
www.teknisi-indonesia.com

22U_0603_6.3V6 22U_0603_6.3V6 M
M M 1 2
1 2 1 2 Compal Secret Data
Decipherii ed Dae
t
D

D
0.47uF*4
330uF*1
22uF*37

22uF *7
unpop:
1uF*9

1uF*1

2018/10/10
+VCC_GT

+VCC_GT

PC9020 PC9046 PC9072 PC9095 @ PC9109 PC9129 PC9153

@

22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 0.47U_0201_6.3V6K 1U_0201_4V6

M M M M M M

Securiiity Clllassiiifiiicatiiion
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9019 PC9045 PC9071 PC9094 @ PC9108 PC9128 PC9152

Issued Date
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9018 PC9044 PC9070 PC9093 @ PC9107 PC9127 PC9151
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 0.47U_0201_6.3V6K 1U_0201_4V6
M M M M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9017 PC9043 PC9069 PC9092 @ PC9106 PC9126 PC9150
@

22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 0.47U_0201_6.3V6K 1U_0201_4V6

M M M M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9042 PC9063 PC9091 PC9125
@
C

C
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6
M M M M M
1 2 1 2 1 2 1 2 1 2
PC9015 PC9041 PC9062 PC9090 PC9124
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6
M M M M M
1 2 1 2 1 2 1 2 1 2
PC9014 PC9040 PC9061 PC9089 PC9123
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6
M M M M M
1 2 1 2 1 2 1 2 1 2
PC9013 PC9039 PC9060 PC9088 PC9122
@
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6
M M M M M
1 2 1 2 1 2 1 2 1 2
PC9012 PC9038 PC9059 PC9087 PC9121
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6
M M M M M
1 2 1 2 1 2 1 2 1 2
PC9011 PC9037 PC9058 PC9086 PC9120
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 0.47U_0201_6.3V6K
M M M M
+
1

1 2 1 2 1 2 1 2 M 1 2
330U_B2_2.5VM_R9
PC9105
SGA00007Z00
+VCC_CORE
B

B
PC9001 PC9036 PC9068 U42@ PC9099 PC9104 PC9119 PC9139 PC9149 PC9158

+VCC_CORE
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M M M
1 2 1 2 1 2 1 2 2 1 1 2 1 2 1 2 1 2
PC9010 PC9035 PC9067 PC9098 PC9103 U42@ PC9118 PC9138 PC9148 PC9157
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M M M
1 2 1 2 1 2 1 2 2 1 1 2 1 2 1 2 1 2
PC9009 PC9034 U42@ PC9066 PC9080 U42@ PC9117 PC9137 PC9147 PC9159
22U_0603_6.3V6 22U_0603_6.3V6M 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M

+
1

2
1 2 1 2 1 2 1 2 M 1 2 1 2 1 2 1 2
PC9008 PC9033 PC9065 PC9097 330U_B2_2.5VM_R9 PC9116 PC9136 PC9146 PC9160
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 U42@ PC9101 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9032 PC9064 PC9166 U42@ PC9115 PC9135 PC9145 PC9161
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M M

+
1

2
1 2 1 2 1 2 1 2 M 1 2 1 2 1 2 1 2
PC9006 PC9031 PC9057 PC9169 U42@ 330U_B2_2.5VM_R9 PC9114 PC9134 PC9144

VCORE Output Capacitor:

22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 PC9100 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M
SGA00007Z00 M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9005 PC9030 PC9056 PC9168 U42@ PC9113 PC9133 PC9143
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M M M M
1 2 1 2 1 2 1 2 PC9187 U42@ 1 2 1 2 1 2
PC9004 PC9029 PC9055 PC9167 U42@ 22U_0603_6.3V6 PC9112 PC9132 PC9142
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 M 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M 1 2 M M M
1 2 1 2 1 2 1 2 PC9189 U42@ 1 2 1 2 1 2
PC9003 U42@ PC9028 PC9054 PC9171 U42@ 22U_0603_6.3V6 PC9111 PC9131 PC9141
A

A
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 M 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M 1 2 M M M
1 2 1 2 1 2 1 2 PC9188 U42@ 1 2 1 2 1 2

22uF_0603*41
PC9002 U42@ PC9027 U42@ PC9053 PC9170 U42@ 22U_0603_6.3V6 PC9110 PC9130 PC9140

1uF_0201*35
22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 22U_0603_6.3V6 M 1U_0201_4V6 1U_0201_4V6 1U_0201_4V6
M M M M 1 2 M M M
1 2 1 2 1 2 1 2 1 2 1 2 1 2

2017/06/06

22_0603*1
330uF *2
UNPOP
U42
1

4
 5 4 3 2 1

OpenVReg Configurations:(PSI pin)

Operation phase Number PSI Voltage setting Module model information:
R1, R2, R3, R4, R5, C are 1 phase with DEM 0V to 0.4V RT8816A-2P_NVVDDS_V2A.mdd for IC portion
VGA_B+
PL801 VGA_EMI@
based on VGA type to set. 1 phase with CCM 0.7V to 0.88V RT8816A-2P_NVVDDS_V2B.mdd for SW portion
VGA_B+
S SUPPRE_ 5A Z80 20M 0805
2 1
B+
2 phase with DEM 1.08V to 1.35V

PC804
2200P_0402_50V7K

0.1U_0402_25V
10U_0603_25V6

10U_0603_25V6
2 phase with CCM 1.6V to 5.5V

PC805
1
1

1
PC802

PC803
DH1_VGA VGA_EMI@
D D
@VGA_EMI@
Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot)

2
2

2
PWM VID and Output voltage control
Rt=Rrefadj // (Rboot+Rref2)

6
1.Boot mode

M
PQ801
PSI pull up on HW side
AON6962_DFN5XV6GDA-8@-7VGA@

1
Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] 2. Standby mode (don't support)
+1.8VGS_+3VGS_AON 3. Normal mode

G1
D1
Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2] PL802 0.24UH_22A_20%_ 7X7X3_M
+VGA_CORE

1
Vout=Vmin+N*Vstep 7 LX1_VGA 1 4
+1.8VGS_+3VGS_AON D2/S1
@VGA@
Vstep=(Vmax-Vmin)/Nmax PR801 2 3

1
10K_0402_1%

G2
S2

S2

S2
VGA_RF@

1SNU2B_VGA1
2

330U_B2_2.5VM_R9

330U_B2_2.5VM_R9

330U_B2_2.5VM_R9
VGA@ PR803 1 1 1
PR802

5
[24] PSI 1 2 VGA@

1 DL1_VGA 6
@VGA@
4.7_1206_5% + + +
PR833

PC806

PC807

PC808
1
0_0402_5% @ PR804 10K_0402_1%
VGA@
N16_VGA@ PR809 N17_VGA@
VGA_B+

2
20K_0402_1% PR809 10K_0402_1% PR805 PC809 VGA_RF@ 2 2 2
20.5K_0402_1% 0_0402_5% 680P_0402_50V7K

10.7K_0402_1%
N16_VGA@PR813 1 2 VGA_CORE_EN [26]

M
@ PR807
N16_VGA
2

2
N16_VGA@PR812 20K_0402_1% VGA@ VGA@ VGA@
1

1
2K_0402_1% VGA@ VGA_B+
R2 @PR810 @PC801 High: >1.2V

10U_0603_25V6

10U_0603_25V6
[24] GPU_VID0 1 2 .1U_0402_16V7K
Low: <0.55V

2
PC810
N16_VGA@PR814

PC811
NVVDDS_PSI_R
R3

1
DH2_VGA
18K_0402_1% PR812 R1 0_0402_5% N16S-GTR

NVVDDS_EN
NVVDDS_VID
2

4.32K_0402_1%
C 1 2 1 2 DH1_VGA N16_VGA@PU801 Rocset +VGA_CORE C

M 2
N17_VGA@ RT8812AGQW_WQFN20_3X3
EDP-Continuous 26.5A

M
PQ802
1

N17_VGA@ N17_VGA@PR813
AON6962_DFN5X6VDG-A8@-7VGA@
PR816 16.5K_0402_1%

BST1_VGA1 PR815 2BST1_VGA-R

0.01U_0402_16V7

1
6.19K_0402_1% EDP-Peak 53A
PR814

R4
4700P_0402_50V7K

2.2_0603_5%
1 OCP min 63.6A

G1
D1
1

PL803 0.24UH_22A_20%_ 7X7X3_M

PC812

PC813

REFADJ_NVVDDS

VGA@
+VGA_CORE

1
5

1
1 2

N17_VGA@ PC816 7 LX2_VGA 1 4

2

N17_VGA@ 2@ D2/S1
C 0.1U_0402_25V6
309_0402_1%

EN
VID

BOOT1
PSI

UGATE1

1
N16_VGA@PC813 2 3
N17S-G1
K

VGA@ VGA_RF@
2700P_0402_50V7K

G2
S2

S2

S2

SNU2B_VGA2
6 20 LX1_VGA PR817
R5 REFADJ PHASE1 +VGA_CORE

www.teknisi-indonesia.com
4.7_1206_5% EDP-Continuous 29.7A
2

6
RGND_NVVDDS RT8816BGQW_WQFN20_3X3 VGA@
REFIN_NVVDDS 7 19 DL1_VGA EDP-Peak 59.2A
N16_VGA@PR816 REFIN LGATE1 PR819
0_0402_5%
VGA@ OCP min 71.1A
1_0402_1% 4.7U_0402_6.3V 4pcs

DL2_VGA

1
VREF_NVVDDS 8 PU801 18 PVCC_NVVDDS 1 2 PC817 VGA_RF@
VREF N17_VGA@ PVCC +5VALW 680P_0402_50V7K 10U_0603_6.3V 13pcs
1

1
PC818 Close Vref pin N17_VGA@PR820 VGA@
+VGA_CORE Near GPU Core

2
0.1U_0402_25V6 1 2 TON_NVVDDS9 17 DL2_VGA PC819
N17_VGA@ PR821 TON LGATE2
2.2U_0603_16V6K
2

2
VGA_B+ 1 2 432K_0402_1% Rton LX2_VGA VGA@
OCSET/SS

2.2_0805_5% 10 16
RGND PHASE2
1

UGATE2

PC826
N16_VGA@PC818
PGOOD

VGA@ N16_VGA@PR820

10U_0402_6.3V6M
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0402_6.3V6M
PC82

PC82

PC82

PC82
RGND_NVVDDS

BOOT2

PC82
10U_0402_6.3V6M

10U_0402_6.3V6M
PC83

10U_0402_6.3V6M

PC83
PC82
PC820
VSNS

1U_0402_6.3V6K 499K_0402_1%
GND

1
1
1

1
1U_0603_25V6K

1
@PR823
2

0_0402_1% PC822
VGA@
[21] GND_SENSE_GPU 1 2 0.1U_0402_25V6

2
2

2
21

11

12

13

14

15

2
2

2
2
B B
VGA@ 4.7U_0402_6.3V 12pcs
PR825
1 PR8242 BST2_VGA1 2BST2_VGA-R

7
Remark: 1U_0402_16V 5pcs

0
3

1
5
DH2_VGA

2.2_0603_5% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1. Switching frequency setting:(Ton pin) 10_0402_5% VGA@
1000P_0402_50V7

Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p) VGA@ +VGA_CORE

GB4-128 package

PC841

PC842

PC843

PC844
=352Khz Current Limit threshold setting

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

.3V6M
1

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
0.01U_0402_16V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M
PC83

PC83

PC83

PC83

PC84
PC83

PC83

PC84
1

PC832

Rocset= (Ivalley * Rds(on) * 12) / Icoset

10U_0402_6 1
1

1
1

1
For debug only,
PC833

VGA@ PR826
HW side need other resister 10K_0402_5%
NVVDDS_VSENS2E

1U_0402_16V6

1U_0402_16V6

1U_0402_16V6

1U_0402_16V6
2

1U_0402_16V6
@VGA@ 1 2

PC846

PC847

PC848

PC849

PC850
OCSET_NVVDDS

2
2

2
2

2
VGA@ @VGA@ +3VS
K

1
1 PR8272 PR829
+VGA_CORE 0_0402_5%

5
6

0
DGPU_PWROK [21,25,26]
10_0402_5% N16_VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2

2
1 2 1 2 N17_VGA@PC851

K
[21] VDD_SENSE_GPU
0.01U_0402_16V7K VGA@ VGA@ VGA@ VGA@ VGA@
Css

@PR828 1 2
0_0402_1% 1
PR830
2
1 2 Under GPU Core
0_0402_5%
N17_VGA@ N17_VGA@PR831

4.7U_0402_6.3V6

4.7U_0402_6.3V6

4.7U_0402_6.3V6

4.7U_0402_6.3V6
90.9K_0402_1%

PC859

PC861

PC862

PC863
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
PC85

PC85

PC85

PC85

PC85

PC85

PC85

PC86
1

1
1

1
2

2
2

2
M

M
A A
VGA@ VGA@ VGA@ VGA@
2

0
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/19 Tiitlle
2012/04/19 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
VGA_CORE
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D SiiizeDocument Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. VGA_CORE
Date: Monday, October 22, 2018 Sheet 50 of 53
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 5 4 3 2 1

D D

Module model information

SY8286_V1_single.mdd
SY8286_V1_dual.mdd keep short pad,
snubber is for EMI only.

B+_1.35V
@VGA@
PR1203 VGA@ PC1204
@ PJ1201
0_0402_5% 0.1U_0402_25V6
VGA_B+ 1
1 2
2 BST_1.35V 1 2 BST_1.351V_R 2

10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
JUMP_43X79

1
1
VGA_EMI@PC1201

@VGA_EMI@PC1203

VGA@ PC1205
2 1
2

2
VGA@ VGA_RF@ PR1202 VGA_RF@ PC1202
4.7_1206_5% 680P_0402_50V7K
2 SNUB_1.35V

1
PU1201 1 1 2

BS
IN3

IN2

IN1
+3VS Use 7x7x3 size when the layout space is enough.
LX_1.35V 5 17
LX EP
PL1201VGA@
Confirm HW side
1

LX_1.35V
PR1201@VGA@
100K_0402_5% 6
SY8386RHC_QFN16_2P5X2P5
LX2
16 1 4
+1.35VGSP
GND 2 3

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
15
2

LX1 1UH_6.6A_20%_5X5X3_M

VGA@PC1207

VGA@PC1208

VGA@PC1209

VGA@PC1210
VGA@PC1206
7
[26] +1.35VGS_PGOOD

2 1

2 1

2 1

2 1

2 1
PG 14
C GND1 C

8 13 LDO_3V_1.35V
VGA@ PD1201 TEST VCC VGA@
1 2 PC1211

ILMT

2 1
BYP
4.7U_0402_6.3V6M

EN

FB
RB751V-40_SOD323-2
+3VALW

10

11

12

1
VGA@

1
[email protected]_0402_5% PR1209
1 2 EN_1.35V
[25] 1.35V_PWR_EN 1K_0402_1%
VGA@ R1

2.2U_0201_6.3V6

2
1

PR1204

VGA@PC1213
2 1

2
VGA@ PR1206 PC1212 VGA@ 12.7K_0402_1%
2 1

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1M_0402_1% 0.22U_0402_16V7K @ PJ1202
JUMP_43X118
1 2
LDO_3V_1.35V +1.35VGSP +1.35VS_VRAM
2

1 2

M
EN :H>0.8V ; L<0.4V FB_1.35V
1

@VGA@
EN pin don't floating PR1208
If have pull down resistor at HW side, 0_0402_5%
please delete PR601.
FB=0.6V
2

ILMT_1.35V

1
EN pin don't floating PR1207VGA@
If have pull down resistor at HW side, pls delete PR702 Vout=0.6V* (1+R1/R2) R2 10K_0402_1%

=0.6*(1+(12.7/10))

2
Vout=1.362V

B B

A A

Securiiity Clllassiiifiiicatiiion Compalll Secret Data Compal Electronics, Inc.

Issued Date 2016/6/2 Deciiiphered Date 2017/6/2 Tiitttlle
VRAM-SY8286RAC
THIIIS SHEET OF ENGIIINEERIIING DRAWIIING IIIS THE PROPRIIIETARY PROPERTY OF COMPAL ELECTRONIIICS,,, IIINC... AND CONTAIIINS CONFIIIDENTIIIAL AND
Siiize Documenttt Numberrr Rev
TRADE SECRET IIINFORMATIIION... THIIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIIVIIISIIION OF R&D
Custttom
DEPARTMENT EXCEPT AS AUTHORIIIZED BY COMPAL ELECTRONIIICS,,, IIINC... NEIIITHER THIIIS SHEET NOR THE IIINFORMATIIION IIITCONTAIIINS
MAY BE USED BY OR DIIISCLOSED TO ANY THIIIRD PARTY WIIITHOUT PRIIIORWRIIITTEN CONSENT OF COMPAL ELECTRONIIICS,,, IIINC...
ISL62771 Module 0..1

Dattte::: Monday,,, Octttoberrr 22,,, 2018 Sheettt 51 o ff53

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Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
Add PR407(SD028000080,S RES 1/16W 0 +-5% 0402)
1 To avoid shortage issue and fix BOM error 2018/07/31 EVT
Change PQ1661 PN from SB000012900 to SB000011Z00
Modify BOM for X1 code Change PQ314 from SB00000ST00 to SB000009Q80 2018/08/10 DVT
D D

3 Modify BOM for X1 code Change PC315,PC411,PC702,PC1202 from 680P_0603_50V7K to 680P_0402_50V7K 2018/08/10 DVT

4 Modify Vin detector setting for 4 cell battery Change PR306 from 287K_0402_1% to 392K_0402_1% 2018/08/16 DVT

5 Change Battery connector P/N Change JBATT1 to ACES 60757-00802-001 2018/08/16 DVT

6 Change +3VALWP IC solution Change PU401 from SY8286BRAC to SY8386BRHC 2018/08/16 DVT

7 Change +1.05VALWP & +1.35VGSP IC solution

Add PR1209(SD034100180,S RES 1/16W 1K +-1% 0402) 2018/08/16 DVT
Change PU701 & PU1201 from SY8286RAC to SY8386RHC
Change PR330 from 349_0402_1% to 100_0402_1%
8 Charger IC Vendor suggestion Change PC321 from 0.015U_0402_25V7K to 0.033U_0402_25V7K 2018/08/27 DVT
C
Change PR333 from 182K_0402_1% to 150K_0402_1% C

9 Change PC9120,PC9126,PC9127,PC9129 from 0.47U_0201_4V6M to

Follow cost down action 0.47U_0201_6.3V6K 2018/08/27 DVT

10 Change PQ311 P/N Change PQ311 P/N from SB00001IL00 to SB00001C500 2018/08/27 DVT

PC307 & PC309 change from SE000005Z80(S CER CAP 0.22U 25V K X7R 0603) to 2018/08/27 DVT

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11 Charger IC Vendor suggestion SE00000WA00(S CER CAP 0.47U 25V K X5R 0402)

PCZ19 change from SE000013J00(S CER CAP 0.22U 25V K X6S 0402) to
12 Follow cost down action SE000015W00(S CER CAP 0.22U 25V K X5R 0402) 2018/08/27 DVT

PCZ3,PCZ13,PCZ16 change from SE074104K80(S CER CAP 0.1U 50V K X7R 0402) 2018/08/27
Follow cost down action to SE00000G880(S CER CAP 0.1U 25V K X5R 0402) DVT
13
PC505 , PC1204 change from SE00000W210(S CER CAP 0.1U 25V K X7R 0402) to
Follow cost down action SE00000G880(S CER CAP 0.1U 25V K X5R 0402) 2018/08/27 DVT
14
B B

15 Fine tune for U42 CPU transent test result Add PC9103, PC9187 ,PC9188 ,PC9189(22U_0603_6.3V6M) 2018/08/29 DVT

16 Follow HW request Change PR826 from 100K to 10K 2018/08/29 DVT

Change PRZ35 from 4.22K to 2.8K Change PRZ71 from 182K to 19.1K
17 Change PCZ11 from 150p to 330p Change PRZ48 from 30K to 28K
Fine tune for U42 CPU transent test result 2018/08/30 DVT
Change PRZ67 from 115 to 7.68K Change PRZ54 from 22.1K to 24.3K
Change PRZ70 from 549K to 5.62K
Change PRZ68 from 374 to 4.64K
Delete PC9101,PC9166,PC9167,PC9168,PC9169,PC9170,PC9171,PC9068,PC9080,
18 Fine tune for U22 CPU transent test result PC9002,PC9003,PC9027,PC9034 for U22 CPU SKU 2018/09/05 DVT
Delete PR1(45.3K_0603_1%)
19 To avoid RTC loos issue 2018/09/06 DVT
Change PR2 from 1.5K_0603_1% to 0_0603_5%
Change PR304,PR305,PR332,PR407,PR413,PR508,PR511,PR709, PR601,
20 0 ohm change to short pad PR606,PR705, PR711,PR803 to short pad 2018/10/11 PVT
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiiitllle

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PIR (PWR)
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
Z_BDW 0.1

Date: Monday, October 22, 2018 Sheet 52 of 53

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 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1 for EE

Item Reason for change PG# Modify List Date Phase

1 Audio Vendor request for hum noise issue Reserved +5VALW for AVDD5 (pin29) 2018/10/17 PVT
D D

C C

www.teknisi-indonesia.com

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/04/09 Deciphered Date 2019/04/09 Tiitlle

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
EE (PWR)
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Siiize Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-H082P 0.3

Date: Monday, October 22, 2018 Sheet 53 o f 53

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