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Contents
Preface to the first edition vi
Preface to the second edition vii
Syllabus viii

Chapter-1 Introduction to Modern Electronics 1-12

1.1 INTRODUCTION 1
1.2 WHAT IS ELECTRONICS ? 1
1.3 APPLICATIONS OF ELECTRONICS 2
1.4 SIGNAL 3
1.5 OTHER CLASSIFICATION OF SIGNAL 5
1.5.1 Deterministic and Non-deterministic Signals 5
1.5.2 Periodic and Aperiodic Signals 5
1.5.3 Even and Odd Signals 6
1.5.4 Energy and Power Signals 7
1.6 FREQUENCY SPECTRUM OF SIGNAL 8
1.7 ANALOG AND DIGITAL SIGNALS 9
1.8 SYSTEM 9
1.9 AMPLIFIER 10
1.9.1 Classification of amplifier 10
1.10 DIGITAL LOGIC INVERTERS 11
Short Questions & Answers 11
Chapter-2 Operational Amplifiers 13-38
2.1 INTRODUCTION 13
2.2 CHARACTERISTICS OF OP-AMP 13
2.3 BLOCK DIAGRAM OF A TYPICAL OPERATIONAL AMPLIFIER 13
2.4 SCHEMATIC SYMBOL OF AN OP-AMP 15
2.5 IDEAL OP-AMP 16
2.6 EQUIVALENT CIRCUIT OF AN OP-AMP 17
2.7 IDEAL VOLTAGE TRANSFER CURVE 17
2.8 BASIC OP-AMP CIRCUIT 18
2.9 COMMON-MODE REJECTION RATIO (CMRR) 19
2.10 VIRTUAL GROUND CONCEPT 22
2.11 SLEW RATE (SR) 22
2.12 OPEN-LOOP OP-AMP CONFIGURATIONS 22
2.13 CLOSED-LOOP OP-AMP CONFIGURATIONS 23
 2.14 OP-AMP AS INVERTING AMPLIFIER 23
2.15 OP-AMP AS NON-INVERTING AMPLIFIER 24
2.16 VOLTAGE FOLLOWER / VOLTAGE BUFFER / UNITY FOLLOWER 25
2.17 ADDER OR SUMMING AMPLIFIER 26
2.18 SUBTRACTER 27
2.19 INTEGRATOR / LOW PASS FILTER 28
2.20 SUMMING INTEGRATOR CIRCUIT 29
2.21 DIFFERENTIATOR / HIGH PASS FILTER 30
2.22 INSTRUMENTATION AMPLIFIER 33
2.23 OP-AMP SPECIFICATIONS 35
2.23.1 Gain-Bandwidth 35
2.23.2 Maximum Signal Frequency 35
Short Questions & Answers 36
Exercise 38

Chapter-3 Concepts Of Semiconductors 39-59

3.1 INTRODUCTION 39
3.2 ATOMIC STRUCTURE 39
3.2.1 Valence Electrons 40
3.2.2 Free Electrons 40
3.3 ENERGY LEVELS 41
3.4 ENERGY BANDS 41
3.4.1 Classification of solids on the basis of Energy Band Theory 42
3.5 TEMPERATURE COEFFICIENT OF RESISTANCE (α ) 43
3.6 DIFFERENT TERMS RELATED WITH SEMICONDUCTORS
AND CONDUCTORS 44
r
3.6.1 Relationship between vd, σ, I, E 44
3.7 HOLE 45
3.8 ELECTRON-HOLE PAIRS 45
3.9 TYPES OF SEMICONDUCTORS 45
3.9.1 Intrinsic Semiconductors 46
3.9.2 Extrinsic Semiconductor 46
3.10 n-TYPE SEMICONDUCTOR 46
3.11 p-TYPE SEMICONDUCTOR 47
3.12 DISTINGUISH BETWEEN P-TYPE AND N-TYPE 49
Short Questions & Answers 54
Exercise 58

Chapter-4 Semiconductor Diode 60-75

4.1 INTRODUCTION 60
4.2 DEFINITION 60
4.3 p-n JUNCTION DIODE 60
4.3.1 Fabrication of diode 60
4.3.2 Mechanism in diode 61
4.4 BIASING 62
4.4.1 Forward Biasing 62
4.4.2 Reverse Biasing 63
4.4.3 V - I characteristic 63
4.5 DIODE CURRENT EQUATION 63
4.6 BREAKDOWN 64
4.6.1 Comparison between Avalanche Breakdown and Zener Breakdown 64
4.6.2 PIV / PRV 65
 4.7 ZENER DIODE 65
4.8 RESISTANCES IN DIODE 67
4.8.1 Graphical Determination 67
4.8.2 Mathematical determination of AC resistance 68
4.9 CAPACITANCE IN DIODE / CAPACITIVE EFFECT OF DIODE 69
4.10 DIODE EQUIVALENT MODELS 69
4.10.1 Piece wise linear equivalent model 69
4.10.2 Simplified equivalent model 70
4.10.3 Ideal equivalent model 71
4.11 DIODE SPECIFICATIONS 71
4.12 DIODE APPLICATIONS 72
Short Questions & Answers 72
Exercise 74

Chapter-5 Application of Diode 76-101

5.1 INTRODUCTION 76
5.2 RECTIFIER 77
5.2.1 Half wave rectifier 77
5.2.2 Full-wave Rectifier 81
5.2.3 Comparison of different typesof rectifiers 84
5.3 CLIPPER 87
5.3.1 Steps for solving clipper problem 87
5.4 CLAMPER 92
5.4.1 Steps for solving clamper problem 92
5.5 EXAMPLES OF SERIES & PARALLEL CONFIGURATION OF DIODE 95
Short Questions & Answers 98
Exercise 100

Chapter-6 Bipolar Junction Transistor (BJT) 102-152

6.1 INTRODUCTION 102
6.2 BJT (BIPOLAR JUNCTION TRANSISTOR) 102
6.3 TRANSISTOR TERMINALS 102
6.4 BJT SYMBOLS 103
6.5 TRANSISTOR CURRENTS 104
6.6 IMPORTANT POINTS REGARDING WORKING OF TRANSISTORS 104
6.7 TRANSISTOR AS AN AMPLIFIER 105
6.8 TRANSISTOR AS A SWITCH 106
6.9 EBERS-MOLL MODEL 107
6.10 TRANSISTOR CONFIGURATION 108
6.11 CHARACTERISTICS OF TRANSISTOR CONFIGURATION 108
6.11.1 Input characteristics 108
6.11.2 Output characteristics 108
6.12 COMMON BASE (CB) CONFIGURATION 109
6.12.1 Input Characteristic 109
6.12.2 Output Characteristic 110
6.12.3 Current Amplification factor (α) 111
6.13 COMMON - EMITTER CONFIGURATION (CE) 113
6.13.1 Input Characteristic 113
6.13.2 Output characteristics 114
6.13.3 Current amplification factor (β) 115
6.13.4 Relation between α, β and ICEO, ICBO 115
6.14 COMMON COLLECTOR CONFIGURATION 118
 6.15 RELATION BETWEEN α, β & γ 118
6.16 TRANSISTOR LOAD LINES 118
6.16.1 DC load line 118
6.16.2 Operating Point (Q-point) 119
6.16.3 AC load line 119
6.17 BIASING 120
6.17.1 Transistor Biasing 120
6.18 NECESSITY OF BIASING 120
6.19 TRANSISTOR BIASING CIRCUITS 120
6.19.1 Fixed bias circuit 120
6.19.2 Self / Emitter-Stabilized bias circuit 123
6.19.3 Voltage - Divider biasing 125
6.19.4 DC feedback biasing 128
6.20 BIAS STABILIZATION 140
6.21 NEED FOR BIAS STABILIZATION 140
6.22 STABILITY FACTOR 141
6.22.1 General Expression for SI CO 142
6.22.2 General Expression for Sβ 142
6.22.3 Stability factors in different Bias Circuit 142
Short Questions & Answers 146
Exercise 150

Chapter-7 Small Signal Operation of BJT 153-175

7.1 INTRODUCTION 153
7.2 TWO PORT NETWORK 153
7.3 HYBRID MODEL OR H-PARAMETER MODEL 153
7.3.1 Approximate hybrid model for CE & CB, configuration of BJT. 156
7.4 ANALYSIS OF A TRANSISTOR AMPLIFIER
CIRCUIT USING h PARAMETERS 157
7.5 STEPS FOR DRAWING SMALL SIGNAL MODEL 161
7.6 STEPS FOR ANALYSIS OF TRANSISTOR CIRCUIT 161
7.7 re - TRANSISTOR MODEL 161
7.7.1 Common base configuration 162
7.7.2 Common emitter configuration 163
7.8 COMPARISON BETWEEN HYBRID MODEL & re - MODEL 164
7.9 BJT SMALL-SIGNAL ANALYSIS 164
7.10 VOLTAGE-DIVIDER BIAS 168
7.11 FREQUENCY RESPONSE OF BJT 172
Short Questions And Answers 173
Exercise 174

Chapter-8 Field Effect Transistor (FET) 176-211

8.1 INTRODUCTION 176
8.2 DIFFERENCE BETWEEN BJT & FET 176
8.3 POINTS ABOUT FETs 177
8.4 CLASSIFICATION OF FETs 177
8.5 JFETs 178
8.5.1 Standard notations 178
8.5.2 Operation 178
8.6 CHARACTERISTICS OF JFETS 180
8.6.1 Output or Drain Characteristic 180
8.6.2 Transfer Characteristic 183
8.7 MERITS AND DEMERITS OF JFETS 184
8.8 JFET AS AN AMPLIFIER 185
 8.9 JFET PARAMETERS 185
8.10 JFET BIASING 189
8.10.1 Fixed biasing :- (Rs = 0) 189
8.10.2 Self / Source Stabilized biasing 191
8.10.3 Voltage divider biasing 192
8.11 FET SMALL SIGNAL MODEL 205
8.12 COMPARISON OF LOW FREQUENCY MODELS OF FET AND BJT 206
8.13 COMMON SOURCE JFET AMPLIFIER 206
Short questions and answers 209
Exercise 211

Chapter-9 Metal-Oxide-Semiconductor Field Effect

Transistors (MOSFET) 212-226
9.1 INTRODUCTION 212
9.2 MOSFET 212
9.3 D-MOSFET (Depletion MOSFET) 213
9.4 E-MOSFET (ENHANCEMENT - MOSEFET) 215
9.5 CMOSFET 217
9.6. COMPARISON OF JFETS AND MOSFETS 225
Short Questions And Answers 225
Exercise 226

Chapter-10 Feedback Amplifiers and Oscillators 227-247

10.1 INTRODUCTION 227
10.2 THE FEEDBACK CONCEPT 227
10.3 TYPES OF FEEDBACK 229
10.4 PRINCIPLE OF FEEDBACK IN AMPLIFIERS 229
10.5 ADVANTAGES OF NEGATIVE FEEDBACK 233
10.6 TYPES OF NEGATIVE FEEDBACK CONNECTIONS 233
10.7 EFFECT OF NEGATIVE FEEDBACK ON INPUT IMPEDANCE 234
10.8 EFFECT OF NEGATIVE FEEDBACK ON OUTPUT IMPEDANCE 235
10.9 EFFECTS OF NEGATIVE FEEDBACK ON AMPLIFIER CHARACTERISTICS 237
10.10 INTRODUCTION TO OSCILLATOR 237
10.11 CONDITION FOR OSCILLATOR OPERATION /
BARKHAUSEN CRITERION 238
10.12 ESSENTIALS OF TRANSISTOR OSCILLATOR 239
10.13 TYPES OF TRANSISTOR OSCILLATORS 239
10.14 OP-AMP OSCILLATOR CIRCUITS 240
10.14.1 RC Phase-Shift Oscillator 240
10.14.2 Wein-Bridge Oscillator 241
10.14.3 Crystal Oscillators 242
Short Questions 246
Exercise 247

Chapter-11 Electronic Instruments 248-271

11.1 INTRODUCTION 248
11.2 CATHODE RAY OSCILLOSCOPE 248
11.3 CATHODE RAY TUBE (CRT) 249
11.3.1 Electron Gun 250
11.3.2 Deflection System 250
11.3.3 Fluorescent Screen 251
11.3.4 Glass Envelope 251
11.3.5 Time Base (Waveform display) 252
 11.4 BLOCK DIAGRAM OF CRO 253
11.5 FRONT PANEL CONTROLS OF CRO 254
11.5.1 Cathode Ray Tube Controls 254
11.5.2 Vertical Section 254
11.5.3 Horizontal Section 255
11.6 LISSAJOUS FIGURES 256
11.7 CRO MEASURMENTS 257
11.7.1 Study or Examination of waveforms 257
11.7.2 Measurement of amplitude of AC / DC voltage 257
11.7.3 Measurement of Time Period 258
11.7.4 Measurement of Frequency 259
11.7.5 Measurement of Phase angle 260
11.7.6 Current Measurement 260
11.8 APPLICATIONS OF CRO 260
11.9 SWEEP-FREQUENCY GENERATORS 261
11.10 BLOCK DIAGRAM OF STANDARD SIGNAL GENERATORS 263
11.11 PULSE AND SQUARE-WAVE GENERATORS 264
11.12 FUNCTION GENERATORS 268
11.13 DIGITAL MULTIMETERS 270
Short Questions And Answers 271

Chapter-12 Digital Electronics Principles 272-288

12.1 INTRODUCTION 272
12.2 NUMBER SYSTEM 272
12.3 DECIMAL NUMBER SYSTEM 273
12.4 BINARY NUMBER SYSTEM 273
12.4.1. Counting in Binary 273
12.4.2 Binary-To-Decimal Conversion 274
12.4.3 Binary Fractions 274
12.4.4 Decimal to Binary Conversion 275
12.4.5 Decimal Fraction to Binary 276
12.5 OCTAL NUMBER SYSTEM 277
12.5.1 Octal-To-Decimal Conversion 278
12.5.2 Decimal-To-Octal Conversion 278
12.5.3 Octal-To-Binary Conversion 279
12.5.4 Binary-To-Octal Conversion 279
12.5.5 Octal Arithmetic 280
12.6 HEXADECIMAL NUMBER SYSTEM 280
12.6.1 Counting in Hexadecimal 281
12.6.2 Hexadecimal-To-Decimal Conversion 281
12.6.3 Decimal-To-Hexadecimal Conversion 282
12.6.4 Hexadecimal-To-Binary Conversion 283
12.6.5 Binary-To-Hexadecimal Conversion 283
12.6.6 Conversion From Hex-To-Octal and Vice-versa 284
12.6.7 Hexadecimal Arithmetic 284
12.7 BINARY OPERATIONS 285
12.7.1 Binary Addition 285
12.7.2 Binary Subtraction 285
12.7.3 Binary Multiplication 286
12.7.4 Binary Division 286
12.8 1’s COMPLEMENT REPRESENTATION 287
12.8.1 1’s Complement Subtraction 287
12.9 2’s COMPLEMENT REPRESENTATION 287
12.9.1 2’s Complement Subtraction 288
Chapter-13 Boolean Algebra & Logic Gates 289-310
13.1 INTRODUCTION 289
13.2 BOOLEAN ALGEBRA 289
13.2.1 Boolean Algebra Laws 289
13.2.2 Boolean Algebra Rules 290
13.2.3 Proof of Boolean Rules 291
13.2.4 Boolean Postulates 292
13.3 DE-MORGAN’S THEOREMS 292
13.4 DUALITY THEOREM 293
13.5 STANDARD REPRESENTATIONS FOR LOGICAL FUNCTIONS 293
13.5.1 Sum-of-Products (SOP) Form 293
13.5.2 Product-of-Sums (POS) Form 294
13.6 LOGIC GATES 294
13.6.1 NOT Gate 295
13.6.2 AND Gate 295
13.6.3 OR Gate 295
13.6.4 NAND Gate 296
13.6.5 NOR Gate 296
13.6.6 Exclusive - OR (X - OR) Gate 297
13.6.7 Exclusive-NOR (X-NOR) Gate 298
13.7 UNIVERSAL GATES 298
13.7.1 NAND as Universal Gate 298
13.7.2 NOR as Universal gate 300
Short Questions and Answers 309

Chapter-14 Digital Circuits & Design 311-359

14.1 COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS 311
14.2 COMPARISON OF COMBINATIONAL AND
SEQUENTIAL LOGIC CIRCUITS 311
14.3 DESIGN PROCEDURE 312
14.4 HALF ADDER 316
14.5 FULL ADDER 317
14.6 HALF SUBTRACTOR 318
14.7 FULL SUBTRACTOR 319
14.8 2-BIT BINARY MULTIPLIER 320
14.9 MULTIPLEXER (MUX) 320
14.10 DEMULTIPLEXER (D-MUX) 323
14.11 SEQUENTIAL DIGITAL CIRCUITS 324
14.12 SYNCHRONOUS SYSTEM, EDGE TRIGGERING 324
14.13 LATCHES AND FLIP FLOPS 325
14.14 FLIP FLOPS (F/F) 325
14.14.1 Types of Flip Flops 326
14.14.2 S-R Flip Flop 326
14.14.3 J-K Flip Flop 327
14.14.4 D Flip-Flop 328
14.14.5 JK Master Slave Flip Flop 329
14.15 BASIC CONCEPTS OF MEMORY (RAMs) 331
14.16 TYPES OF MEMORIES 331
14.17 MEMORY DEVICE PARAMETERS OR CHARACTERISTICS 332
14.18 COUNTER 334
14.19 CLASSIFICATION OF COUNTER 334
14.20 STEPS FOR DESIGNING ASYNCHRONOUS COUNTER 335
14.21 NATURAL ASYNCHRONOUS COUNTER DESIGNS 335
14.22 UN-NATURAL ASYNCHRONOUS COUNTER DESIGNS 337
14.23 SHIFT REGISTER 339
 14.24BUFFER REGISTER 340
14.25BASIC SHIFT OPERATIONS 340
14.26SHIFT LEFT REGISTER 341
14.27SHIFT RIGHT REGISTER 342
14.28SHIFT REGISTER OPERATIONS 342
14.29SERIAL IN - SERIAL OUT SHIFT REGISTER 343
14.30SERIAL IN-PARALLEL OUT SHIFT REGISTER 344
14.31PARALLEL IN - PARALLEL OUT SHIFT REGISTER 345
14.32PARALLEL IN-SERIAL OUT SHIFT REGISTER 346
14.33CIRCULAR SHIFT REGISTER 347
14.34DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSION 347
14.34.1 Digital-To-Analog (D/A) Conversion 347
14.34.2 Analog-To-Digital (A/D) Conversion 353
IMPORTANT NOTES 358
Chapter-15 Communication Systems 360-386
15.1 INTRODUCTION 360
15.2 BASIC BLOCK DIAGRAM OF A COMMUNICATION SYSTEM 360
15.3 PRINCIPLE OF COMMUNICATION 362
15.4 MODULATION 363
15.5 AMPLITUDE MODULATION 363
15.6 MODULATION INDEX 364
15.7 POWER CONTENT IN AM WAVE 365
15.8 GENERATION OF AM WAVE 366
15.9 DEMODULATION OF AM WAVE 369
15.10 NEED OF MODULATION 370
15.11 LIMITATIONS OF AMPLITUDE MODULATION 370
15.12 FREQUENCY MODULATION 370
15.13 COMPARISON BETWEEN AM AND FM 371
15.14 DIGITAL COMMUNICATION TECHNIQUES 374
15.14.1 Sampling 374
15.14.2 Sampling theorem 374
15.14.3 Quantization 375
15.15 PULSE CODE MODULATION (PCM) 376
15.16 PCM SYSTEM 378
15.17 FIBRE OPTIC COMMUNICATION 379
15.17.1 Structure of Optical Fibre 380
15.17.2 Principle of Optical Fibre 380
15.17.3 Types of optical fibre 381
15.17.4 Application of Fibre Optics 382
15.17.5 Advantages of Fibre Optics 382
15.18 NOISE 382
15.18.1 External Noise 383
15.18.2 Internal Noise 383
Short Questions And Answers 384
Exercise 385
PREVIOUS QUESTIONS WITH SOLUTIONS
Second Semester Examination-2010 387
First Semester Examination-2009 400
Second Semester Examination-2009 419
First Semester Examination-2008 435
Second Semester Examination-2008 451
First Semester (Special) Examination-2007 471
Second Semester Examination-2007 485
Bibliography 498
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Introduction to Electronics CHAPTER

1.1 INTRODUCTION
It can be said that ‘Electronics’ took birth in 1897, when a vacuum diode was developed
by J.A. Fleming. However, the real beginning was made in 1906, when Lee De Forest
developed the vacuum triode. Without this device, the amplifiers i.e. the heart of all intricate
and complex electronic gadgets, would not have been made possible. The vacuum tube
devices dominated the field of electronics until the end of World War II.
In 1948; transistor was invented by the three Nobel laureates - John Bardeen, Walter
Brattain and William Shockley at Bell Laboratory. This invention completely
revolutionalized the electronics industry and opened the floodgates to further develop-
ments in electronics. Within a decade, a large number of such devices were produced
which exceeded the total number of vacuum based devices produced prior to 1948.
The development in electronic devices goes further and the first integrated circuit
(1C) was appeared in the market during early sixties. The stringent demand of space
electronics resulted in further development in integrated circuit technology starting from
small scale integrated (SSI) circuits, then medium scale integrated (MSI) circuits, large
scale integrated (LSI) circuits and now recently very large scale integrated (VLSI) circuits
have been developed.
The technology of ICs is seemingly perfected to its maximum. But are we sure ?
No ! The electronic field in general and the semiconductor device field in particular are so
dynamic and so fast changing that today’s concepts may be obsolete tomorrow.
1.2 WHAT IS ELECTRONICS ?
The word Electronics is derived from electron which is present in all materials. The
behaviour of an electron under different conditions of externally applied fields is studied
under electron mechanics.
The branch of science and engineering which deals with the flow of electrons through
vacuum or gas or semiconductor is known as electronics.
 2 Basic Electronics
In fact, electronics is a branch which essentially deals with electronic devices
and their utilization. An electron device is a device in which conduction (electrons
flow) takes place through a vacuum, a gas or a semiconductor.
Electronics is a newcomer in the field of engineering as compared to the other
established branches such as civil, electrical, mechanical etc. Previously, it was con-
sidered an integral part of electrical engineering, but due to tremendous development
in this field during the last few decades, it has now established as a separate branch
of engineering.
1.3 APPLICATIONS OF ELECTRONICS
The electronics plays an important role in almost every sphere of our life. It has
penetrated in every field e.g. from an ordinary wrist watch to super computers ; from
telephone repeaters buried deep under sea to the spaceships far out in space ; from
the control of modern household appliances to the control of 400000 tonne supertanker
carrying cargo across the sea.
Electronics deals in the micro and milli range of voltage, current and power, but
it controls kilo and mega volts, amperes and watts. Some of the important applications
of electronics in various fields are given below :
1. Communications and Entertainments : In earlier stages, the main application
of electronics was in the field of telegraphy and telephony. This utilizes a pair of
wires. The start of wireless transmission for radio communication can be taken from
the work of Heinricb Hertz, a German physicist. In 1887, first of all, he demonstrated
the effect of electromagnetic radiations through space. With the development in this
field, it is now possible to transmit any message from one place to another, thousands
of kilometres away. People living in any part of the world can know what is happening
in other parts by radio broadcasting. The messages can be typed on a typewriter kept
in another city with the help 01 a teleprinter. The photographs of various events
occurring in different parts of the world can be transmitted on fascimile (radiophoto)
and then can be printed in the newspapers all over the world.
Radio and TV broadcasting not only provides the latest information but also
provides entertainment to the audians and viewers. The other electronic gadgets like
tape recorders, record players, stero systems etc. are also widely used for
entertainment.
2. Industrial Applications : The automatic control circuits (electronic circuits)
are used invariably in the industries now-a-days. These are used to control quality,
thickness of job, cutting of job, moisture contents in a material, lighting system,
sound system, automatic door-openers, power system and safety devices etc. Similarly,
there are so many other operations in the industry which are automatically controlled
by electronic circuits.
3. Defence Applications : The communication system plays an important role
during the war days. The success or defeat of a nation largly depends upon the
 Introduction to Electronics 3

reliability of its communication system. All the messages are conveyed through
communication system.
The other important electronic equipment, used during war days is RADAR (Radio
Detection and Ranging). With the help of RADAR, the exact location of enemy’s
aircraft is determined. The anti-aircraft guns are then accurately directed to shoot
down the aircraft. In fact, RADAR and anti-aircraft guns are linked by an automatic
control system to form a complete unit. Similarly, guided missiles are also used during
war which are completely controlled by electronic circuits.
4. Applications in Medical Sciences : Various electronic machines/equipment are
used by the doctors in diagnosis and treatment of various diseases. Some of the
machines/equipment are given below :
(i) Electron microscope to analyse blood etc. (ii) X-rays for taking pictures of bone
structure. (iii) Electro-cardiographs (ECG) to study the condition of heart. (iv)
Oscilloscopes are used as the display to monitor the heartbeats of the patient, (v)
Short-wave diathermy units for healing sprains and fractures etc.
There are so many other electronic instruments which are used by doctors. In
fact, the use of electronics in medical sciences has expanded to such an extant that a
new branch in medical sciences has been started called bioelectronics.
5. Applications in Automobiles : More and more electronic equipment are used in
cars for charging of battery, power-assist functions, me,asuring gauges and monitoring
and control of engine performance. The most important application in automobiles is
electronic ignition, which provides better timing of the ignition spark, especially at
high speeds.
6. Digital Electronics : The circuits for digital applications operate with pulses of
voltage or current. A pulse wave form is either completely ON or OFF because of the
sudden changes in amplitude. In between values have no function. All the digital
clocks, counters, calculators, computers etc. are operated by these pulses.
7. Instrumentation : Electronic instruments like VTVM, cathode-ray oscilloscope,
frequency counter, signal generator, p-H meters, strain-gauges etc. are much more
accurate than the ordinary instruments. Without these instruments no research laboratory
is complete.
1.4 SIGNAL
It is physical quantity that varies with time, space or any other independent variables
like temperature, position, pressure, distance etc.
In electrical sense, the signal can be voltage or current. Both can be ‘ac’ or ‘dc’.
Again ‘dc’ may be
i) variable/pulsating dc
ii) static dc.
4 Basic Electronics

Fig. 1.1
In electronic sense, the signal can be analog or digital.
The signal is said to be analog if there are infinite no. of amplitude levels. i.e signal
amplitude is continuously changing.
The signal is said to be digital if there are finite no. of amplitude level i.e signal
amplitude is discrete or not continuously changing.

Fig. 1.2
 Introduction to Electronics 5

1.5 OTHER CLASSIFICATION OF SIGNAL

1) Deterministic and random signal
2) Periodic and aperiodic signal
3) Even and odd signal
4) Energy and power signal
1.5.1 Deterministic and Non-deterministic Signals
Deterministic signals are those signals which can be completely specified in time.
The pattern of this type of signal is regular and can be characterized mathematically.
Also, the nature and amplitude of such a signal at any time can be predicted. Few
examples of deterministic signals are :
(i) x(t) = bt
This is a ramp signal whose amplitude increases linearly with time and the slope is b.
(ii) x(t) = a sin ωt
For this signal, the amplitude varies sinusoidally with time and its maximum amplitude
is A.

(iii) x(n) =
RS2 n ≥ 0
T0 otherwise
This is a discrete-time signal whose amplitude is 2 for the sampling instants n > 0 and
for all other samples, the amplitude is zero.
Hence, for all the above signals, it is clear that the amplitude at any time instant can
be predicted in advance. Therefore, all the above signals are deterministic signals.
On the other hand, a non-deterministic signal is one whose occurrence is always
random in nature. The pattern of such a signal is quite irregular. Non-deterministic signals
are called random signals.
A typical example of non-deterministic signals is thermal noise generated in an electric
circuit. Such a noise signal has probabilistic behaviour.
1.5.2 Periodic and Aperiodic Signals
A periodic signal is that type of signal which has a definite pattern and repeats over
and over with a repetition period of T. In other words, a continuous-time signal is called
periodic if it exhibits periodicity as follow :
x(t + T) = x(t), –∞ < t < ∞
T is the period of the signal. The smallest value of period T which satisfies above equation
is called the fundamental period T0. Figure 1.3 shows a continuous-time periodic signal.

Fig. 1.3 : A continuous-time periodic signal

 6 Basic Electronics
Similarly, for a discrete-time signal, the condition of periodicity may be written as :
x(n + N0) = x(n), – ∞ < n < ∞
Here, N0 is called the sampling period of discrete-time signal. Figure 1.4. shows a dis-
crete-time periodic signal.

Fig. 1.4. A discrete-time periodic signal

A signal is said to be Aperiodic if it does not repeat. Sometimes aperiodic signals

are said to have a period equal to infinity. Figure 1.5 shows an aperiodic signal. This is a
decaying exponential pulse given by the equation :
x(t) = e–at
Now, x(t + T0) = e–a(t+T0) ∞
= e–a (t+∞)
or x(t + T0) = e–at.e–∞
=e–at.0
x (t + T0) = 0
Fig. 1.5 An aperiodic signal
which is not equal to x(t).
Thisshowsthatthesignalhaving period T0 = ∞ is nothing but aperiodic signal.
1.5.3 Even and Odd Signals
An even signal is that type of signal which exhibits symmetry in the time domain. This
type of signal is identical about the origin. Mathematically, an even signal must satisfy the
following condition.
For a continuous-time signal, x(t) = x(-t)
For a discrete-time signal, x(n) = x(-n)
Similarly, an odd signal is that type of signal which exhibits anti-symmetry. This type
of signal is not identical about the origin. Actually, the signal is identical to its negative.
Mathematically, an odd signal must satisfy the following condition.
 Introduction to Electronics 7

(a) Continuous-time even signal (b) Discrete-time even signal

Fig. 1.6. Even signal.

For a continuous-time signal, x(t) = –x (–t)

For a discrete-time signal, x(n) = –x (–n)
Figure 1.7 shows continuous-time and discrete-time odd signals.

(a) Continuous-time odd signal (b) Discrete-time odd signal

Fig. 1.7. Odd Signals
1.5.4 Energy and Power Signals
Signals may also be classified as energy and power signals. However, there are
some signals which can neither be classified as energy signals nor power signals.
The energy signal is one which has finite energy and zero average power.
Hence, x(t) is an energy signal, if :
0 < E < ∞ and P = 0
where, E is the energy and P is the power of the signal x(t).
The power signal, is one which has finite average power and infinite energy.
Hence, x(t) is a power signal, if:
0 < P < ∞ and E = ∞
However, if the signal does not satisfy any of the above two conditions, then it is neither
an energy signal nor a power signal.
 8 Basic Electronics
1.6 FREQUENCY SPECTRUM OF SIGNAL
Ø Frequency spectrum is the arrangement of different frequency components of a
signal.
Ø This can be obtained through fourier series and fourier transform. With the help of
fourier series, avoltage or current signal can be expressed as the sum of sine wave
signals of fundamental frequencies and its harmonics.
Ø Let a voltage signal v(t)
The fourier series can be obtained as,

a0 =
1
T z
x( t )dt

an =
2
T z
x( t ) cos n ω 0 t dt

and bn =
2
T z
x( t ) sin n ω 0 t dt

∞
Then v( t ) = a 0 + ∑ (a
n =1
n cos n ω 0 t + b n sin n ω 0 t ) ( −∞ < t < ∞ )

If we will consider a square wave as v(t)

Its fourier series will be

4v 1 1 Fig. 1.8
v( t ) =(sin ω 0 t + sin 3ω 0 t + sin 5 ω 0 t +...)
π 3 5
where V = amplitude of square wave
T = Time period
2π
ω0 = = Fundamental Frequency
T
Here voltage signal is expressed as
infinite series of sine waves of fundamental
and its harmonic frequencies.
Here is the frequency spectrum of
the square wave is
Fig. 1.9
Ø The frequency spectrum provides an easier way to analyse a signal.
 Introduction to Electronics 9

1.7 ANALOG AND DIGITAL SIGNALS

Analog Signals. Analog signals are signals whose both dependent variable and independent
variable(s) are continuous in nature. Analog signals arise when a physical waveform is
converted into an electrical signal. This conversion is performed by means of a transducer.
For example : Telephone speech signals, TV signals etc., are very common types of analog
signal.
Telephone Speech Signals. A
telephone message comprises of
speech sounds having vowels and
consonants. These sounds produce an
audio signal. These sound waves are
converted into analog electrical
signals by means of a transducer 1.10 Telegraph signal (Digital signal).
(microphone). Transducer is a device
which converts non-electrical quantity into electrical signals. Example: Microphone.
Continuous-amplitude, continuous-time signals are called analog signals.
Digital Signals. Digital signals are signals whose both dependent variable and independent
variables are discrete in nature. Digital signals comprise of pulses occuring at discrete
intervals of time. Telegraph and teleprinter signals are the example of digital signals. Fig.1.10
illustrates a telegraph signal.
1.8 SYSTEM
It is a set of elements or functional blocks which are connected to produce output
in response to input signal.

Fig. 1.11
Gain of a system (A)
It is defined as output to the input of the system. Mainly it is three types :-
Voltage gain (AV)
Current gain (AI)
Power gain (AP)

AV =
output Voltage V0b g
b g
input Voltage Vi

output current bI g
= 0

input Current bI g
AI
i

output power b P g
= 0

input power b P g
AP
i
 10 Basic Electronics
P0 V0 I 0
AP = =
Pi V1 I1

⇒ A P = A V .A I
Example 1.1 :
An amplifier have power gain, 20. The input voltage is 5 volt while output voltage is
10 volt. Find the input current for which output current will be 20 amp.
Solution : Given AP = 20 Vin = 5 Volt, V0 = 10 Volt.
& I0 = 20
V0 10
AV = = =2
Vin 5
A P 20 I 10
A P = A V .A I ⇒ A I = = = 10 ⇒ 0 = 10 ⇒ I in = = 0.5 Amp Ans.
AV 2 I in 20
1.9 AMPLIFIER
It is an electronic device that increases the strength of an weak signal.
The strength of a signal is directly proportional to Amplitude of the signal. So amplifier
can also be defined as the device that increases the amplitude of the input signal.
1.9.1 Classification of amplifier
The amplifier is mainly divided in to two categories :-
Voltageamplifier
i) Small signal amplifier
Current amplifier
ii) Large signal amplifier / Power amplifier
Small signal amplifier
The signal having lower amplitude / strength is known as small signal.
The amplifier that amplifies the small signal, known as small signal amplifier.
a) Voltage amplifier
The amplifier whose voltage gain is greater than unity.
i.e. A V >1
Ex :- CB & CE configuration of BJT amplifier.
b) Current amplifier
The amplifier whose current gain is greater than unity i.e. A V >1 .
Ex :- CC & CE configuration of BJT amplifier.
Large signal / power amplifier
The signal having larger amplitude / strength is known as large signal.
The power amplifier does the conversion of dc biasing i/p energy to ac o/p energy without
any change in input ac signal.
There are six types of power amplifier.
(a) Class A (b) Class B (c) Class AB (d) Class C (e) Class D (f) Class E
 Introduction to Electronics 11

1.10 DIGITAL LOGIC INVERTERS

The logic inverter is the most basic element in digital circuit design; it plays a role
parallel to that of the amplifier in analog circuits.
As its name implies, the logic inverter inverts the logic value of its input signal.
Thus for a logic 0 input, the output will be a logic 1, and vice versa. In terms of voltage
levels, consider the inverter shown in block form in Fig. 1.12 When vI is low (close to
0 V), the output v0 will be high (close to VDD), and vice versa.

Fig : 1.12 A logic inverter operating from a dc supply VDD.

SHORT QUESTIONS & ANSWERS

Q.1. What is signal?
Ans. Signal is the representation of a physical quantity w.r.t. time, space or any other independent
variable. It is an electrical or electromagnetic wave that contains some information. It has
amplitude, frequency etc. Eg. Traffic signal, it contains the information to control the traffic.
Q.2 What are the different types of signal?
Ans. Signal can be classified in two ways.
It may be alternating & direct signal. Alternating signal is a type of signal of which the
amplitude as well as the direction ( means +Ve or –Ve) is varying . eg. Sine wave.
Direct signal is a signal of which amplitude may or may not vary but the direction remains
constant.
Again the signal may be classified as analog & digital signal. Each may be continuous or
discrete.
Continuous analog is a signal which has infinite no. of amplitude levels but continuous
occurrence with time. But discrete analog signal has infinite no. of amplitude levels but
discrete occurrence with time.
Continuous digital is a signal which has finite no. of amplitude levels & continuous over
time. But discrete digital signal has finite no. of amplitude levels but discrete occurrence
with time.
Q.3. What is a electromagnetic spectrum?
Ans. Electromagnetic spectrum means a definite arrangement of different electromagnetic signals
as per their frequency or wavelength. Eg. Solar spectrum, Hydrogen spectrum.
 12 Basic Electronics
Q.4. What is an amplifier?
Ans. An amplifier is an electronic device which increases the strength of the input signal.
There are different types of amplifier- Voltage amplifier, Current amplifier, Power amplifier,
buffer amplifier etc.
When an input signal is given the amplifier gives the output signal which is of more strength
than input, in other sense the amplitude of input signal increases. So the name is given as
amplifier.
Q.5. What is IC?
Ans. IC is the abbreviation of Integrated circuit. It means fabrication of large no. of electronic
components in a single chip using LSI / VLSI technology.
It may be fabricated using TTL logic, DTL logic, CMOS etc.
Eg. IC 74LS00 for NAND gate
IC 74LS02 for NOR gate
IC 74LS04 for NOT gate
IC 74LS08 for AND gate etc.

ppp
Operational Amplifiers CHAPTER
2.1 INTRODUCTION

An operational amplifier (Op-amp), is a multistage, very high gain, direct coupled

differential amplifier.
The word “operational” stands for various mathematical operations like addition,
subtraction, multiplication, differentiation, integration etc, and amplifier is one that
boosts the input signal.
As this circuit performs both mathematical operations and amplifications, it is named
as op-amp.
This circuit can be used for designing filters and oscillator circuits.
It can amplify ac signal as well as dc signal.
It can also be designed to use as active filters, oscillators, comparators etc.

2.2 CHARACTERISTICS OF OP-AMP

(i) High input impedance (Ideally ∞ )
(ii) Low output impedance (Ideally 0)
(iii) Can amplify dc as well as ac input signals
(iv) High bandwidth (Ideally ∞ )
(v) High value of differential gain (Ideally ∞ )
(vi) High value of CMRR (Common made rejection ratio)
(vii) High slew rate,
(viii) Stabilized output.
(ix) Unity gain band-width.
2.3 BLOCK DIAGRAM OF A TYPICAL OPERATIONAL AMPLIFIER
An operational amplifier being a multistage amplifier, consists of some basic building
blocks as shown in block diagram (fig 2.1).
14 Basic Electronics

Fig. 2.1 : Block Diagram of a Typical Op-amp

The block diagram of an op-amp shown in fig 2.1 consists of a four stage direct coupled
amplifier in cascade. In summarized form, it can be explained as below.
The first stage/input stage is double-ended high-gain (60 db) differential amplifier
i.e. dual-input balanced output differential amplifier with a constant current source (in order
to increase CMRR). In this stage high gain is desirable so that there would be a negligible
effect on the output of any short-coming in the following stages. This is the reason why this
stage is generally responsible for most of the gain of op-amp. Also this stage determines the
input resistance of the op-amp. Output of this stage is taken between collectors of two
emitter biased circuits so that output remains balanced and the dc voltage at output in quiescent
condition maintains zero level.
The second stage, called the intermediate stage, is usually another differential amplifier,
which is driven by the output of first stage. In most amplifiers the intermediate stage is dual
input, unbalanced (single-ended) output differential amplifier in order to increase the gain.
The differential mode voltage gain of such an amplifier is half of the gain of the dual-input
balance output type differential amplifier. In this amplifier output is measured at the collector
of only one of the two transistors w.r.t. ground. In the quiescent condition some dc voltage
exists at the output terminal and there is no other collector voltage at output to balance or
nullify this output dc voltage. This is the reason why this type of amplifier is called unbalanced
output type differential amplifier. This unbalanced dc voltage present at the output acts as
an error voltage in the desired output signal.
The third stage, known as level shifting stage, is usually an emitter follower circuit in
order to shift the dc level at the output of the intermediate stage downward to zero volt with
respect to ground. It is worthmentioning here that error signal is developed in the intermediate
stage due to direct coupling and gets amplified in the succeeding stages. This increase in dc
level tends to shift the operating point of the succeeding stages which also limits the output
voltage swing or may distort the output signal. To overcome these problems, use of a level
translator (shifter) circuit becomes necessary to bring this dc level to zero voltage (ground
potential).
The final stage, called output stage, is usually a push-pull complementary amplifier.
This stage increases the output voltage swing and the current supplying capability of the
amplifier. A well designed output stage also provides low output resistance. The output of
 Operational Amplifiers 15

the op-amp is the voltage measured at output of this final stage push-pull amplifier with
respect to ground.
2.4 SCHEMATIC SYMBOL OF AN OP-AMP
The schematic symbol of an op-amp is shown in fig 2.2 (a). A is the voltage gain, v1 is
non-inverting input and v2 is inverting input. The differential input is
vin or vd = v1 – v2
and output voltage, vout = A vin = A (v1 - v2)
Note that voltages VI, v2 and vout are node voltages. This means that they are always
measured with respect to ground. The differential input vin is the difference of two node
voltages v1 and v2.

fig 2.2
Often, the common ground line is omitted and the schematic symbol becomes, as illustrated
in fig. 2.2(b).
Most widely used circuit symbol for an op-amp is shown in fig. 2.2(c). It essentially
consists of two input terminals and one output terminal. Here the inputs are marked with
plus (+) and minus (-) to indicate non-inverting and inverting inputs, respectively. A signal
applied to the plus input appears with the same polarity and amplified at the output, while
an input applied to the minus terminal appears amplified but inverted at the output.
It should be clearly understood that plus and minus signs never mean that the voltages
v1 and v2 are positive and negative respectively. It also does not imply that positive voltage
is to be applied to the terminal marked positive and negative voltage to the terminal marked
negative.
The output voltage is directly proportional to the input voltage which is the difference
of vl and v2 (i.e. vin = v – v2). The constant of proportionality is the voltage gain of the
amplifier and is denoted by English letter A.
The op-amp’s input can be single-ended or double-ended or differential input depending
whether the input voltage is applied to one input terminal only or to both. Similarly output
can also be either single- ended or double-ended. Most commonly used configuration is two
input terminals and one output terminal.
Op-amps have five basic terminals namely two input terminals (non-inverting input
terminal and inverting input terminal), one output terminal and two power supply terminals
16 Basic Electronics
(–ve bias supply terminal and + ve bias supply terminal). The significance of other terminals
varies with the type of the op-amp.
2.5 IDEAL OP-AMP
The op-amp is said to be ideal if it has the following characteristics.
1. Its open-loop gain A is infinite. When an op-amp is operated without any connection
between the output and any of the inputs (i.e. without feedback), it is said to be in the
open-loop condition. Infinite voltage gain means the voltage difference required between
the two inputs to produce any output voltage is zero.
2. Its input resistance (i.e. the resistance measured between inverting and non-inverting
terminals) Rin is infinite. It means that the input current (current drawn from the source)
is zero and so it does not load the source. It also means that an ideal op-amp is a
voltage controlled device.
3. Its output impedance Rout is zero i.e. the output voltage Vout does not depend on the load
resistance connected between the output terminals i.e. output voltage Vout is independent
of the current drawn by the load. The output thus can drive an infinite number of other
devices.
4. Perfect balance. Because of infinite voltage gain, the voltage between the inverting
and non-inverting terminals of input i.e. differential input voltage Vd = V2 - Vl is
essentially zero (i.e. Vx = V2) for infinite output voltage Vout. This implies that Vl and
V2 track each other i.e. a virtual short-circuit exist between the two input terminals but
with no current flowing between the two terminals, as Rin is infinite.
5. Infinite frequency bandwidth i.e. it has flat frequency response from dc to infinity so
that any frequency signal from zero to infinity Hz can be amplified without attenuation.
6. Drift of characteristics with temperature is nil.
7. Common mode rejection ratio (CMRR) is infinite so that amplifier is free from undesired
common-mode signals such as pickups, thermal noise etc
8. Slew rate is infinite so that output voltage changes occur simultaneously with input
voltage changes.
9. Output voltage is zero when input voltage is zero i.e. offset voltage is zero.
Because of having infinite input resistance and zero output resistance, ideal op-amp behaves
as an ideal voltage controlled voltage source (VCVS).
Table : 2.1
Quantity Symbol Ideal LM741C LF157A
Open-loop voltage gain AVOL Infinute 100,000 200,000
Unity-gain frequency funity Infinite 1 MHz 20 MHz
Input resistance Rin Infinite 2MΩ 1012 Ω
Output resistance Rout Zero 75 Ω 100 Ω
Input bias current Iin(bias) Zero 80 nA 30 pA
Input offset current Iin(off) Zero 20 nA 3 pA
Input offset voltage Vin(off) Zero 2 mV 1 mV
Common-mode CMRR Infinite 90 dB 100 dB
rejection ratio
 Operational Amplifiers 17

2.6 EQUIVALENT CIRCUIT OF AN OP-AMP

Fig 2.3 shows an op-amp equivalent
circuit, which is useful in analyzing the
basic operating principles of op-amps
and in observing the effects of feedback
arrangements.
The voltage source A v d is an
equivalent. Thevenin voltage source,
and Rout is the Thevenin equivalent
resistance looking back into the output
terminal of the op-amp. Fig. 2.3
The output voltage of the circuit shown in fig 2.3 is given as
vout = A vd = A (v1 – v2)
where A is large signal voltage gain, vd is differential input voltage, v1 and v2 are the input
voltages at non-inverting and inverting terminals respectively with respect to ground.
Here output voltage is directly proportional to the algebraic difference of the two input
voltages which means the op-amp amplifies the difference between the two input voltages,
not the input voltages themselves. For this reason the polarity of the output voltage depends
on the polarity of the difference voltage vd .
2.7 IDEAL VOLTAGE TRANSFER CURVE
The curve drawn between output
voltage vout and input differential voltage
v d keeping gain A constant (fig 2.4)
represents the equation
vout = A vd = A (v1 – v2)
graphically. The curve shown in fig 2.4 is
known as an ideal voltage transfer curve,
ideal because in drawing this curve output
offset voltage is assumed to be zero. In
normal op-amp use (with negative
feedback), the output offset voltage is
nearly zero and is ignored for simplifying
the calculations.
The curve shown in fig 2.4 reveals that
the output voltage uout cannot exceed the Fig. 2.4
positive and negative saturation voltages.
Positive and negative saturation voltages are specified by an output voltage swing rating of
the op-amp for given values of supply voltages. In other words it can be stated that the
output voltage uout increases in direct proportion to the input differential voltage vd only
until it attains the saturation value and then it becomes constant, as shown in fig 2.4.
18 Basic Electronics
2.8 BASIC OP-AMP CIRCUIT
The basic circuit of an op-amp is shown in fig. 2.5. An input signal V2 is applied through a
resistor R1 to the inverting or minus input terminal. The output voltage is fedback through
resistor R, to the same input terminal. The non-inverting or plus input terminal is connected
to earth. For determination of overall gain of the circuit i.e. some more details of the op-amp
unit will have to be considered.
Fig. 2.5 (b) shows the op-amp replaced by an equivalent circuit having input resistance
Rin and output voltage source and resistance. As an ideal op-amp has infinite input resistance
(i.e. Rin = ∞), zero output resistance (i.e. Rout = 0) and infinite voltage gain (i.e. A = ∞), the
connection for the ideal amplifier is illustrated redrawn in figs 2.5 (c) and 2.5 (d).
Using superposition theorem we can solve for the input voltage Vin in terms of the components
due to each of the sources.
For source V2 only (assuming – A Vin to be zero)
Rf
V1in = V2
R1 + R f
For source – A Vin only (assuming V1 to be zero)

Fig. 2.5
 Operational Amplifiers 19

V2 in =
R1
R1 + R f
b− AVin g
R f V2 A R1Vin
Total input voltage Vin = V1in + V2 in = −
R1 + R f R1 + R f

R f V2
or Vin = R + R (1 + A )
f 1

If A >> 1 and A R1 >> Rf as is usually true, then

Rf
Vin ~ V2
A R1

Vout −A Vin −A R f V2 − R f
= = =
V2 V2 V2 A R1 R1
It is obvious that the ratio of overall output to the input voltage is dependent only on the
values of resistors R1 and R, provided A is very large.
2.9 COMMON-MODE REJECTION RATIO (CMRR)
Ad
CMRR is defined as the ratio of differential voltage gain to common-mode voltage
A A CM
gain and it is given as CMRR = d
AC

Fig 2.6

If a differential amplifier is perfect, CMRR would be infinite because in that case common-
mode voltage gain AC would be zero.
Fig. 2.6 represents a linear active device with two input signals V1 and V2 and one output
signal Vout , each measured with respect to ground. In an ideal differential amplifier the
output signal Vout should be given as
Vout = A (V1 – V2)
where A is the gain of the differential amplifier.
Common to both the inputs will have no effect on the output voltage. However, in a practical
differential amplifier, the output not only depends upon the difference signal Vd of the two
input signals, but also upon the average level, called the common-mode signal VC where
V1 + V2
Vd = V1 - V2 and VC =
2
Now let the output voltage Vout in fig 2.6 be expressed as a linear combination of two
input voltages as below
20 Basic Electronics
Vout =A1V1 + A2V2
where A1 is the voltage gain for input Vl with V2 grounded and A2 is the voltage gain for
the input V2 with V1 grounded.
Here

V1 = VC +
1
Vd
U|
V1 + V2
2
V by solving V = V1 − V2 and VC =
− V |
d
1 2
2 |W
and V2 = VC d

Substituting the values of V1 and V2 from above equation in Vout =A1V1 + A2V2 ,
FG 1 1
Vout = A 1 VC + Vd + A 2 VC − Vd
IJ FG IJ
H 2 2 K H K
=
1
2
b g
A 1 − A 2 Vd + (A 1 + A 2 VC )

= A d Vd + A C VC
A1 − A 2
where A d =
2

b
and A C = A1 + A 2 g
and AC = (A1 + A2)
Here Ad is the voltage gain for the difference signal while AC is the voltage gain for the
common-mode signal.
Having measured Ad and AC for the amplifier, CMRR can be determined from the following
relation.
Ad
CMRR =
AC
The value of CMRR can also be expressed in logarithmic terms as
Ad
CMRR (log) = 20 log
AC
The expression for the output voltage can be given as
VO = A d Vd + A C VC

FG
A C VC IJ
H
= A d Vd 1+ A . V
d d K
⇒ Vout = A d Vd 1 +
FG 1 VC IJ
H CMRR Vd K
 Operational Amplifiers 21

Example 2.1 :
A differential dc amplifier has a differential mode gain of 100 and a common mode
gain 0.01. What is its CMRR in db ?
Solution: Differential mode gain, Ad = 100
Common-mode gain, AC = 0.01
A d 100
CMRR = A = 0.01 = 10
4

CMRR in db, CMRR = 201og10 CMRR = 20 Iog10 104 = 20 × 4 = 80 db Ans

Example 2.2 :
For a given op-amp, CMRR = 105 and differential gain Ad = 105. Determine the
common-mode gain, AC of the op-amp. Solution: Differential voltage gain, Ad = 105
Solution : Differential voltage gain, Ad = 105
CMRR = 105
Ad
Q CMRR = A
C

Ad 105
Q Common-mode gain AC = = 5 =1 Ans
CMRR 10
Example 2.3 :

A differential amplifier has inputs VS1 = 10 mV and VS2 = 9 mV. It has a differential
mode gain of 60 db and a CMRR of 80 db. Find the percentage error in the output
voltage and the error voltage. Derive the formula used in your calculations.
Solution : Inputs V1 = 10 m V and V2 = 9 mV
Difference signal Vd = V1 – V2 = 10 – 9 = 1 mV
V1 + V2 10 + 9
Common mode signal VC = = = 9.5 m V
2 2
60
Difference voltage gain Ad = 60 db or antilog = 1,000
20
80
CMRR = 80 db or antilog = 10,000
20
FG 1 . V IJ
Output voltage, Vout = A d Vd 1 +
H CMRR V K
c

L 1 × 9.5OP = 100095
= 1,000 × 1 mv M1 +
N 10,000 1 Q . V
 22 Basic Electronics
Ad Vd = 1,000 × 1 m V = 1 V
So error voltage = Vout – Ad Vd = 1.00095 – 1.0 = 0.00095 V or 0.95 m V

% error = Error voltage × 100 = 0.00095 × 100 = 0.095%

Vout 100095
.
2.10 VIRTUAL GROUND CONCEPT
This is a concept which is practically not possible in an op-amp. So this concept is
applicable for ideal ap-amp.
In an ideal op-amp, the input impedance is infinite, So there is no current to the
op-amp. i.e Ii = 0
Again there is infinite differential gain in an ideal op-amp. It happens when there is
no difference between the inputs at two terminal. i.e Vid = 0. So the two i/p terminal are
virtually grounded.
So according to this
concept there is no input Ii = 0
V1 –
current and no input
differential voltage to the op- output
amp Vid = 0

+
V2

Fig. 2.7
2.11 SLEW RATE (SR)
It is the rate which output of op-amp changes in volts per time change in micro second.

∆VO
SR = V µs
∆t
Normally for an op-amp high value of Slew Rate is desirable.
2.12 OPEN-LOOP OP-AMP CONFIGURATIONS
Open-loop means that there is no connection between input and output terminals either
direct or via another network. It means that output signal is not fedback in any form as
part of the input signal, and the loop that would have been formed with feedback is open.
An op-amp in open-loop configuration acts as a high-gain amplifier. The three open-loop
op-amp configurations are:
1. Differential amplifier
2. Inverting amplifier
3. Non-inverting amplifier
Ø Here output can be only positive saturation or negative saturation, not in between.
So its output is always a square / rectangular wave.
 Operational Amplifiers 23

2.13 CLOSED-LOOP OP-AMP CONFIGURATIONS

An op-amp that uses feedback is called a feedback amplifier and sometimes referred
to as a closed-loop-amplifier because the feedback forms a closed loop between the input
and the output. The feedback may be positive or negative. Negative feedback is of four
types viz voltage-series feedback, voltage shunt feedback, current series feedback and
current shunt feedback. Voltage-series feedback and voltage-shunt feedback are most
important and are widely used in amplifiers while current-series and current-shunt
feedbacks are seldom used.
For most practical applications op-amp is used in closed loop configurations. The
most widely used closed configurations are
1. Voltage-series feedback amplifier or closed-loop non-inverting amplifier.
2. Voltage-shunt feedback amplifier or closed-loop inverting amplifier. The most basic
type is non-inverting voltage feedback. With this type of feedback, the input signal drives
the non-inverting input of an amplifier. A fraction of the output voltage is then fedback to
the inverting input. An amplifier with non-inverting voltage feedback tends to act like an
ideal voltage amplifier one with infinite input impedance, zero output impedance and
constant voltage gain.
2.14 OP-AMP AS INVERTING AMPLIFIER

Fig. 2.8
Here the input is given to the inverting terminal, while non-inverting terminal is grounded.
By Virtual ground concept, two terminals are at same potential, So VA = 0.
Now I1 = If
Vi − 0 0 − V0
⇒ =
R1 Rf
24 Basic Electronics

⇒ V0 = −
FG R IJ V
HR K
f
i
1

V0 R
⇒ AV = =− f
Vi R1
If Rf = R1 then V0 = – Vi i.e the invert of the input is obtained at the output.
u In a closed loop configuration, If feedback is given to same terminal where source is
connected then that one behave as inverting amplifier.
2.15 OP-AMP AS NON-INVERTING AMPLIFIER
If

I1
A RF
0V –
R1
I=0
V0
Vid=0
+

~ Vi
Fig. 2.9

Here the input is given to non-inverting terminal and inverting terminal is grounded.
By virtual ground concept, VA = Vi
Now I1 = If
0 − Vi Vi − V0
⇒ =
Ri RF

⇒
V0 V V
= i + i = Vi
LM 1 +
1 OP
R F R F R1 NRF R1 Q
⇒ V0 = Vi 1 +
LM RF OP ⇒ AV =
V0 R
= 1+ F
N R1 Q Vi R1

If RF = 0Ω, i.e then V0 = Vi, i.e whatever the input, same appears at the output.
u In a cosed loop configuration, if the feedback is given to one terminal and source is
connected to the other terminal then it is an inverting amplifier.
 Operational Amplifiers 25

2.16 VOLTAGE FOLLOWER / VOLTAGE BUFFER / UNITY FOLLOWER

Here RF = 0Ω

Fig. 2.10
Now V0 = AVid
where A = Gain of op-amp.
⇒ V0 = A (V1 – V2) V1 = Voltage at +ve terminal
= A (Vi – V0) V2 = Voltage at –ve terminal.
= AVi – AV0
⇒ V0 (1+A) = AVi
V0 A A
⇒ = ~ {Q A > > 1 }
Vi 1 + A A

V0
⇒ =~1
Vi
⇒ V0 ~ Vi
As output voltage is same as input voltage, So it is buffer circuit.
Example 2.4 :
Design a non-inverting amplifier circuit that is capable of providing a voltage gain
of 10. Assume an ideal operational amplifier. (Resistor should not exceed
30 k Ω ).

Rf
Solution: It is known that Af = 1+
R1

Rf
Given that Af = 10 ∴ 1+ = 10
R1
or Rf = 9 R1
R1 may be taken as 3 k Ω so that Rf comes out to be 9 × 3 i.e. 27 k Ω, less than 30 k Ω Ans
Example 2.5 :
The variable resistance varies from 0 to 100 kΩ. Find out the maximum and the
minimum closed-loop voltage gains
 26 Basic Electronics
Solution : From fig 2.11 R1. = 2 k Ω
Rf(min) = 0 and Rf(min) =100 kΩ
Rf FG IJ
Closed-loop voltage gain, A f = 1 + R
1 H K
R f (max) 100
So A f (max) = 1 + = 1+ = 51 Ans.
R1 2

R f (max)
and A f (max) = 1 + = 1 + 0 = 1 Ans.
R1
Fig. 2.11
Example 2.6 :
An inverting amplifier has Rf = 500 kΩ and R1 = 5 kΩ. Determine the amplifier
circuit voltage gain, input resistance and output resistance. Determine also the output
voltage and input current if the input voltage is 0.1 V. Assume op-amp to be ideal
one.
Solution : Resistance R1 = 5 k Ω
Feedback resistance, Rf = 500 k Ω
Input voltage, Vin = 0.1 V
Rf 500k Ω
Amplifier circuit voltage gain, A f = − R = − 5k Ω = −100
1

Amplifier circuit input resistance, Rin = R1 = 5 kΩ Ans

Amplifier circuit output resistance, Rout = Output resistance of op-amp = 0Ω Ans
Output voltage, Vout = Af Vin = - 100 x 0.l = 10 V Ans
Vin 01.
Input current, Iin = R = 5 × 1,000 = 0.02 mA Ans.
1

2.17 ADDER OR SUMMING AMPLIFIER

IF

V1
I1 R1 RF
I A
V2 –
I2 R2 0V Ii=0
Vid=0 V0
V3
I3 R3 +
0V
Fig. 2.12
 Operational Amplifiers 27

Summing means the output is in the form of sum of its inputs.

Here there inputs are considered.
By Virtual ground concept VA = 0V.
Now If = I1 + I2 + I3

0 − V0 V1 − 0 V2 − 0 V3 − 0
⇒ = + +
RF R1 R2 R3

V0 = − R F
LM V + V
1 2
+
V3 OP
⇒
NR R
1 2 R3 Q
If RF = R1 = R2 = R3, then

V0 = − V1 + V2 + V3
2.18 SUBTRACTER
Here the two input signals are subtracted and is provided at the output.
This circuit can be designed in several ways. Two of them are explained here.
RF
1
RF
2
R1
– V R3
–
+ V0
~ V1 +
~ V2 R2

Stage - I Fig. 2.13 Stage - II

The stage - I is an inverting amplifier circuit.
R F1
Here V = − V1
R1
The 2nd stage is a summing amplifier circuit.

So V0 = − R F2
LM V + V OP 2

NR R Q 3 2

= − R F2
LM V 2
−
R F1
V1
OP
NR 2 R3 Q
28 Basic Electronics

V0 = −
LM R F
V2 −
R F1 R F2
V1
OP
NR 2 R3 Q
I
ii) Here VB =
R3
V1
R1 + R 3 I1
R4
A
By virtual ground concept, V2 –
R2 V0
VA = VB Vid=0 I=0
V1 +
Now I1 = I B
R1
R3 Fig. 2.14

⇒
V2 − VA VA − V0
=
V
⇒ 0 = VA
1
+
1 V
− 2
LM OP
R2 R4 R4 R4 R2 R2 N Q
⇒ V0 = VA 1 +
LM R4 R OP
− 4 V2
N R2 R2 Q
R2 + R4 R3 R
⇒ V0 = R2
.
R1 + R 3
V1 − 4 V2
R2
If R1 = R2 = R3 = R4 then
V0 = V1 – V2
If R1/R3 = R2/R4, then V0 = V1 – V2

2.19 INTEGRATOR / LOW PASS FILTER

Here output is the integration of input. Here the capacitor replaces the feedback
resistor.
If

I1
C
A
–
R Ii=0 V0
Vid=0
+
~ Vi 0V

Fig. 2.15
 Operational Amplifiers 29

The current through a capacitor is

dQ d dv
I= = CV = C
dt dt dt
V is the potential difference across capacitor By virtual ground concept V A = 0V
Now I1 = If
Vi − 0
⇒
R1
d
= C 0 − V0
dt
b g
CdV0
=−
dt
−1
⇒ dV0 = Vi dt
R1C

−1
⇒ V0 ( t ) = R C Vi ( t ) dt
1
z
−1
By Laplace transform, V0 (S) = Vi (S)
R1CS

V0 (S) −1
⇒ =
Vi (S) R 1CS

2.20 SUMMING INTEGRATOR CIRCUIT

R1
V1

R2 C
V2 –

R3 V0
V3
+

Fig. 2.16

Here V0 ( t ) = −
1
C z FGH R1
+
R2
+
R3
IJ
V1 ( t ) V2 ( t ) V3 ( t )
Kdt
 30 Basic Electronics
2.21 DIFFERENTIATOR / HIGH PASS FILTER
Here the output is the derivative of the input signal.
I1

I
R
A
Vi –
C Ii = 0 V0
Vid = 0
+

Fig. 2.17

By virtual ground concept, VA = 0.

Now I = I1
0 − V0
⇒ C
d
dt
b
Vi − 0 = gR
dVi ( t )
⇒ V0 ( t ) = − RC
dt
By Laplace transform,
V0 (S) = − RCS Vi (S)

V0 (S)
⇒ = − RCS
Vi (S)

Example 2.7 :
The following circuit of fig 2.18, shows a controlled gain amplifier. What is the gain
of the amplifier circuit when (i) switch S is off (ii) when switch S is on ?
Solution:
(i) When switch S is off, the circuit is
reduced to that of differential amplifier, as
illustrated in fig 2.19.
For determination of gain of the non-
inverting mode, inverting input is assumed
to be zero and point 2 is grounded. Now
Amplifier circuit gain,
Rf 20k
A off non −inv = 1 + = 1+ =3
R1 10K Fig. 2.18
 Operational Amplifiers 31

The amplifier circuit gain,

d
A off = A off non − inv + A off inv i
= (3 – 2) = 1 Ans

Fig. 2.19

(ii) When switch S is on the circuit becomes an inverting amplifier, as shown in fig.2.20

− R f −20
Amplifier circuit gain, A on = = = −2 Ans
R1 10

Fig. 2.20
Example 2.8 :
Design an adder circuit using an op-amp to get the output expression as
Vout = – (V1 + 10 V2 + 100V3)
where V1, V2 and V3 are the inputs, Given that Rf = 100 kW .
Solution : The output of a summing circuit is,

Vout = − R f
LM V + V
1 2
+
V2OP LM
R R R
= − f V1 + f V2 + f V3
OP
NR R
1 2 R3 Q N R1 R2 R3 Q
Comparing the above expression with the given expression for the output
i.e. - (V1 + 10V2 + 100 V3)
we get R1 = Rf = 100 kΩ Ans.
R f 100
R2 = = = 10 kΩ
10 10
R f 100
and R3 = = = 1 kΩ Ans.
100 100
 32 Basic Electronics
Example 2.9 :
An op-amp as summing circuit has feedback resistor Rf =12 kΩ and the resistances
on the input sides are R 1 = 12 kΩ, R 2 = 2 kΩ and R 3 = 3 kΩ. The corresponding
inputs are V1 = + 9 V, V2 = –3 V and V3 = 1 V. Non-inverting terminal is grounded.
Calculate the output voltage.
Solution : Here Rf = 12 kΩ; R1 = 12 kΩ; R2 = 2kΩ and R3 = 3 kΩ,
V1 = 9 V; V2 = – 3 V and V3 = –1 V
V1 V2 V3 LM OP
Output voltage Vout = − R f R + R + R
1 2 3 N Q
= −12 k Ω
LM 9 + −3 + 1 OP
N12 kΩ 2k Ω 3 kΩ Q = – 9 + 18 + 4 = 13 V Ans.

Example 2.10 : Sketch the circuit of summing circuit using op-amp to get
V0 = – V1 + 2V2 – 3 V3.
Solution : In a summing circuit output is given by

Vout = −
LM R f
V1 +
Rf R
V2 + f V3
OP
NR 1 R2 R3 Q
Comparing the above expression with the given expression for the output
i.e Vout = – V1 + 2 V2 – 3 V3 = – [V1 – 2 V2 + 3 V3]
Rf Rf Rf
we have = R = 1, R = 2, R = 3
1 2 3

Taking Rf = 6 kΩ we have
R1 = Rf = 6 kΩ 6 kΩ
V1
Rf 6 kΩ
R2 = = 3 kΩ -V 2
3 kΩ
2 – V0
2 kΩ
Rf +
R3 = = 2 kΩ V3
3
The circuit is shown in fig 2.21 Fig. 2.21

Example 2.11 :
The input to an op-amp differentiator circuit shown in fig. 2.22 is a sinusoidal voltage
of peak value of 10 µV and frequency 2 kHz. Determine the output voltage if R = 50
kΩ and C = 2 µF.
Solution : The equation for the sinusoidal signal of peak value of 10 µV and frequency 2
kHz is given as
 Operational Amplifiers 33

vin = Vmax sin 2 π f t = 10 sin 2 × 2,000 π t

= 10 sin 4,000 π t µV C R
–6 3
Scale factor C R = 2 × 10 × 50 × 10 = 0.1 Vi –
V0
So output voltage,
+
dv d
v out = −CR c = −01
. (10 sin 4,000 π t) µV
dt dt
Fig. 2.22
d
= – 0.1 × 10 (sin 4,000 πt) µV
dt
= 4,000 π cos 4,000 πt µV or 12.56 cos 4,000 π t µV Ans.
2.22 INSTRUMENTATION AMPLIFIER
This is a circuit that provides an output based on the difference between two inputs
(times scale facter). To permit the adjustment of scale factor of the circuit, a potentiameter
is provided.
The circuit of an instrumentation amplifier is given by,

Fig. 2.23
Here three op-amps are used. So a single quad op-amp IC is required other than resistors.
Let V1′ & V2′ are the output voltages of the opamps having the inputs V1 & V2
respectively.
By vrtual ground concept, VA = V2 & VB = V1
Applying KCL at A,
V2′ − V2 V2 − V1
=
R1 RP
34 Basic Electronics

V2′ V2 V2 V1
⇒ − = −
R1 R1 R P R P

V2′
=
1
+
FG
1 V RIJ
V2 − 1 ⇒ V2′ = 1 + 1 V2 −
1 FG IJ FG IJ
⇒ R1 H
R1 R P RP RPK R1
V1
H K H K
Similarly by applying KCL at point ‘B’,

V1′ = 1 +
FG R1 IJ
V1 −
1 FG IJ
H RP KR2
V2
H K
The Final stage op-amp configuration is nothing but a differential amplifier.
R6 R + R4 R
So V0 = . 3 V1′ − 4 V2′
R5 + R6 R3 R3
IF R1 = R 2 = R 3 = R 4 = R 5 = R 6 = R

F R I V − FG 1 IJ V
Then GH R JK H R K
V1′ = 1 +
p
1 2

F R I V − FG 1 IJ V
V ′ = G1 +
2
H R JK H R K p
2 1

F 2R I bV − V g
V = G1 +
and 0
H R JK p
1 2

⇒ V = Kb V − V g
0 1 2

2R
Here scale factor, K = 1 +
Rp

Ø An instrumentation amplifier is a differential amplifier optimized for high input

impedance and high CMRR.
Ø It is typically used in applications in which a small differential voltage & a large
common mode voltage are the inputs.
Application
i) Temperature indicator
ii) Temperature Controllor
iii) Light intensity meter
iv) Analog weight scale.
 Operational Amplifiers 35

2.23 OP-AMP SPECIFICATIONS

2.23.1 Gain-Bandwidth
Because OP-AMP is a direct coupled differential amplifier it has absence of low
frequency response as compare to that of RC coupled amplifier. It is given by

Av

AVD
0.707AVD

Frequency
0 (log scale)
fC f1

B1
Fig. 2.24
Here fC is the cut-off frequency, f1 is the unity gain frequency, B1 is the unity gain bandwidth
and AVD is the differential voltage gain.
The relation between f1, AVD and fC is
f1 = AVD × fC
2.23.2 Maximum Signal Frequency :
The Maximum frequency that an op-amp may operate at depends on both the band-width
(BW) and slew rate (SR) parameters of the op-amp. For a sinusoidal signal of general
form. v 0 = K sin ( 2 πft )
the maximum voltage rate of change can be shown to be
signal maximum rate of change = 2πfK V/s

To prevent distortion at the output, the rate of change must also be less than the slew rate,
that is, 2πfK ≤ SR
ωK ≤ SR
SR
so that ω≤ rad / s
K
SR
f≤ Hz
2πK
 36 Basic Electronics

SHORT QUESTIONS & ANSWERS

Q.1 What is an operational amplifier ?
Ans. An operational amplifier, abbreviated as op-amp, is basically a multistage, very high gain,
direct-coupled negative feedback amplifier that uses voltage shunt feedback to provide a
stabilized voltage gain.
Q.2. What is voltage gain of a practical op-amp ?
Ans. Voltage gain of a practical op-amp is of the order of 105.
Q.3. State assumptions made for analyzing ideal op-amp.
Ans. Assumptions made for analyzing ideal op-amp are (i) infinite open-loop gain (ii) infinite
input impedance (iii) zero output impedance (iv) perfect balance (v) infinite frequency
bandwidth, (vi) infinite slew rate (vii) infinite common mode rejection ratio and (viii) nil
drift of characteristics with temperature.
Q.4. What is a voltage transfer curve of an op-amp ?
Ans. The curve drawn between output voltage and input differential voltage, for an op-amp,
keeping gain A constant is known as voltage transfer curve.
Q.5. What are differential gain and common mode gain of a differential amplifier?
Ans. When the difference of the two inputs applied to the two terminals of a differential amplifier
is amplified, the resultant gain is termed as differential gain. But when the two input
terminals are connected to the same input source then the gain established by the differential
amplifier is called the common mode gain.
Q.6. What is differential amplifier? Why is it needed?
Ans. The differential amplifier, as its name signifies, amplifies the difference between two input
signals. The need for differential amplifier arises in many physical measurements where
response from dc to many MHz is required. It is also the basic stage of an integrated op-
amp with difference input.
Q.7. Define CMRR.
Ans. CMRR is defined as the ratio of differential voltage gain to common-mode voltage gain
and it is given as CMRR = Ad/AC.
Q.8. A differential amplifier has differential mode gain of 100 and a common-mode gain of
0.01. Calculate its CMRR in db.
Ad 100
Ans. CMRR = 20 log10 = 20 log10 = 20 log10 104 = 20 × 4 = 80
AC 0.01
Q.9. Why open-loop op-amp configurations are not used in linear applications ?
Ans. When an op-amp is operated in the open-loop configuration, the output either goes to
positive saturation or negative saturation levels or switches between positive and negative
saturation levels and thus clips the output above these levels. So open-loop op-amp
configurations are not used in linear applications.
Q.10. What measure(s) is/are taken against dc saturation of an op-amp?
Ans. Negative feedback is introduced to avoid dc saturation of op-amp.
Q.11. What kind of negative feedback is present in a non-inverting op-amp ?
 Operational Amplifiers 37

Ans. Negative voltage series feedback.

Q.13. Why voltage follower circuit is an ideal device to serve as a buffer amplifier?
Ans. Voltage follower, because of its three unique characteristics of extremely high input
impedance, unity transmission gain and extremely low output impedance, is an ideal device
to serve as a buffer amplifier.
Q.14. What is an voltage follower?
Ans. Voltage follower is an electronic circuit in which output voltage tracks the input voltage
both in sign and magnitude.
Q.15. What are the advantages of using a voltage follower amplifier?
Ans. Voltage follower has three unique characteristics viz extremely high input impedance,
extremely low output impedance and unity transmission gain and is, therefore, an ideal
circuit device for use as a buffer amplifier.
Q.16. In what way is the voltage follower a special case of the non-inverting amplifier ?
Ans. If feedback resistor is made zero or R1 is made ∞ (by keeping it open-circuited) in a non-
inverting amplifier circuit, voltage follower is obtained.
Q.17. What is an inverting amplifier?
Ans. In an inverting amplifier, the input is connected to the minus or inverting terminal of op-
amp.
Q.18. What are the applications of an inverting amplifier?
Ans. Inverting amplifier is a very versatile component and can be used for performing number
of mathematical stimulations such as analog inverter, paraphase amplifier, phase shifter,
adder, integrator, differentiator.
Q.19. Op-amp is used mostly as an integrator than a differentiator ?
Ans. Op-amp is mostly used as an integrator rather as a differentiator, because in differentiator
at high frequency, gain is high and so high frequency noise is also amplified which absolutely
abstract the differentiated signal.
Q.20. What will be the output waveshape of an op-amp integrator with a square-wave input?
Ans. The output voltage of an op-amp integrator with a square-wave input will be a ramp or
linearly changing voltage.
Q.21 What is instrumentation amplifier ?
Ans : The circuit that provides an output based on the difference between two inputs (times
scale factor)
Q.22 What are basic building blocks of Op-amp ?
Ans : Refer Sec.2.3
Q.23 List three applications of Op-amp.
Ans : (i) As temp. indicator (ii) As temp. controller (iii) As analog weight scale
Q.24 What is slew rate ? What are the causes of slew rate ?
Ans : Slew rate is the rate at which the output voltage change w.r.t. time in micro volts per
second.
Causes : By current limiting and the saturation of internal stages of the op-amp when a
high Frequency, large amplitude signal is applied.
 38 Basic Electronics

EXERCISE
1. Calculate the voltage gain of an inverting amplifier, given that R1 = 8 kΩ and Rf = 56 kΩ.
[Ans : - 7]
2. For the inverting amplifier, R1 = 2 kΩ and Rf = 1 MΩ. Determine the following circuit
values: (i) Av (ii) R1 and (iii) R0. [Ans (i) -1000 (ii) 1 kΩ (iii) 0 Ω]
3. For inverting amplifier, let Rf = 250 kΩ, Rl = 10 kΩ and Vf = 0.5 V. Calculate (a) I, (b) the
voltage across Rf and (c) V0. [Ans : a) -0.5 mA, b) 12.5 V , c) +12.5 V]
4. Design an inverting amplifier with a gain of –5 and an input resistance of 10 kΩ.
[Ans: R1 = 10 kΩ and Rf = 50 kΩ]
5. Calculate the output voltage of an inverting amplifier, if R1 =50 kΩ, Rf = 500 kΩ and
V1 = 20.4 V. [Ans: 4 V]
6. Calculate the output voltage of non-inverting amplifier, if R1 = 50 kΩ, Rf = 500 kΩ and
Vi = 0.4 V. [Ans: 4.4 V]
7. Calculate the value of the feedback resistor given that Av = – 100 and R1 = 1 kΩ in the case
of an inverting amplifier. [Ans : 100]
8. Design an amplifier with a gain of + 10.
[Ans: Non inverting amplifier, choose R1 = 10 kΩ and Rf = 90 kΩ]
9. Calculate the voltage gain of non-inverting amplifier op-amp with R1 = 10 kΩ and
R2 = 2 kΩ. Find the output voltage when input is 200 mV. [Ans: 6 and 1.2 V]
10. Calculate the output voltage of a three input adder for the following values: R1 = 20 kΩ,
R2 = 40 kΩ, R3 = 60 kΩ and Rf = 100 kΩ, V1 = 20 mV, V2 = 40 mV and V3 = 60 mV.
[Ans: 0.2 V]
11. Calculate the output voltage of an adder for the following values: R1 = 250 kΩ, R2 = 500
kΩ, R3 = 1 MΩ, V1 = – 3 V, V2 = 3 V and V3 = 2 V. [Ans: 4 V]
12. In the subtracter circuit R1 = 5 kΩ , Rf = 10 kΩ , Vl = 4 V and V2 = 5 V. Find the value of
output voltage. [Ans: 2 V]
13. Calculate the output voltage of subtracter circuit if R1 = 2 kΩ, Rf = 10 kΩ, Vl = 3 V and
V2 = 6 V. [Ans: 15V]
14. The input of the differentiator is a sinusoidal voltage of peak value 5 mV and frequency
1 kHz. Find the output if R = 100 kΩ and C = 1 µF. [Ans: - π cos 2000 πt V]
15. A 10 mV, 5 kHz sinusoidal signal applied to the input of an op-amp integrator for which
R = 100 kΩ and C = 1µF. Find the output voltage. [Ans: (10 2 / π ) cos 104 πt V]
16. Design an adder using an op-amp to get the output expression as V0 = - (0.1 V1 + V2+ 20V3),
where Vl ,V2 and V3 are the inputs.
[Ans : Rf = 10 kΩ, R1 = 100 kΩ, R2 = 10 kΩ and R3 = 0.5 kΩ]

ppp
Concepts Of Semiconductors CH AP TE R

3.1 INTRODUCTION
In order to explain the phenomena associated with conduction in gases, metals and
semiconductors, it is necessary to assume that the atom has loosely bound electrons which
can be dislodged from it; the most fundamental unit of a solid can be considered to be an
atom. Hence the study of the atomic structure is important.
3.2 ATOMIC STRUCTURE
Neils Bohr, a Danish Physicist, idealised a clear picture of atomic structure. He stated that
(i) An atom consists of a nucleus which contains neutrons (neutral particles) and protons
(positively charged particles).
(ii) The electrons (negatively charged particles) revolve around the nucleus in different
orbits.
(iii) The nucleus has a positive charge which attracts the electrons. The electrons would
fall into the nucleus if they do not have the required centrifugal force of their motion.
Therefore, an electron travels in a stable orbit and moves at a right velocity for
centrifugal lorce to balance the nucleus attraction.
(iv) The electrons in each permitted orbit have a certain fixed amount of energy. The
larger the orbit (i.e. larger radius of orbit), the greater is the energy of electron.

Fig. 3.1
 40 Basic Electronics
(v) An electron is lifted to the higher orbit if some additional energy (e.g. heat, light or
other radiations) is given to it. Then the atom is said to be in a state of excitation.
This state does not last long since the electron soon falls back to the original (lower)
orbit. As it falls back, it radiates the acquired energy in the form of heat, light etc.
A simple two-dimensional structure of a silicon atom is shown in Fig. 3.1(a). It has
14 electrons, equal to number of protons in the nucleus. The 14 electrons are revolving
around the nucleus only in their permitted orbits i.e. first, second and third having radii r1,
r2 and r3 respectively. Two electrons revolve in the first orbit, 8 in the second and 4 in the
third orbit.
The silicon atonf contains 4 electrons in the outermost orbit called valence electrons.
Therefore, silicon atom is called tetravalent atom. The nucleus and inner electrons are
called core of the atom. However, we are more interested in the valence orbit, since this is
the place where all the action exists in a semiconductor,
3.2.1 Valence Electrons
The electrons which revolve in the outermost orbit of an atom are called valence
electrons.
Most of the atoms of different elements do not have their outermost orbits completely
filled. For example, Fig. 3.2 shows that silicon and germanium atoms have four valence
electrons. The outermost orbit can have a maximum of 8 electrons. Valence electrons
actually determine the physical and chemical properties of a metal. Valence electrons
have more orbital energy and least binding energy. Consequently, very little energy is
required to detach them from their parent atom and make them conduct electric current.
Elements that have one or two valence electrons are good conductors of electricity and
heat. These valence electrons take part in chemical bonding and also determine the valency
of the element.

(a) Silicon atom (b) Germanium atom

Fig. 3.2 Distribution of electrons in Si and Ge atoms
3.2.2 Free Electrons
Valence electrons are loosely bound to the nucleus and can be easily detached from
the parent atom. In a metal the atoms are closely packed and hence the energy levels of
the neighbouring atoms overlap each other. This results in the release of valence electrons
from their parent atoms. As these electrons are no longer attached to any particular atom,
they are called free electrons which move randomly in the metal like molecules of a gas.
The drift of these free electrons in one direction constitutes electric current. Electrons
 41

which are detached from the parent atoms and move randomly in the lattice of a metal
are called free electrons.
3.3 ENERGY LEVELS
It has already been discussed that the electrons can revolve only in the permitted
orbits (i.e. orbits of radii r1, r2 and r3) and not in any intermediate orbit. Thus, all the radii
between r1 and r2 or between r2 and r3 are forbidden (for explanation refer to quantum
physics). Each orbit has fixed amount of energy associated with it and the electrons moving
in a particular orbit possess the energy of that orbit. The larger the orbit, the greater is its
energy. Thus, an electron in the outer orbit possesses more energy than the electron in the
inner orbit.
The level of energy obtained by different orbits is conveniently represented by the
energy level diagram (horizontal lines) shown in Fig. 3.3 (b). The first orbit represents the
first energy level, the second orbit represents the second energy level, and so on. The
larger the orbit of an electron, the greater is its energy and higher in the energy level.
Thus, energy level is just another way of representing the orbital radius.

(a) Fig. 3.3 (b)

3.4 ENERGY BANDS
As discussed earlier, in case of a single isolated atom, the electrons revolving in any
c a definite energy. However, in a solid, an atom is greatly influenced by the closely-
packed n atoms. Because of this the electrons in the same orbit have a range of energies
rather than a si

(a) (b) (c)

Fig. 3.4
 42 Basic Electronics
The range of energies possessed by electrons of the same orbit in a solid is
known as energy band.
Fig. 3.4 shows how energy levels are changed into energy bands. All the electrons
moving in the first orbit have slightly different energy levels because no two electrons’see
exactly the same charge environment. As there are billions of first-orbit electrons in the
solid with slightly different energy levels which form a cluster or band called energy
band. Similarly, the billions of second-orbit electrons with slightly different energy levels
form the second energy band and so on.
3.4.1 Classification of solids on the basis of Energy Band Theory
Amount of forbidden gap make a difference between the solids as
i) Conductor
ii) Semiconductor
iii) Insulator.
i) Conductor
Conductors are substances which allow the easy flow of electric charges.
Example : All most all metals, Salt solutions and human body.
There may be two types of energy band diagrams.

CB VB-Valence Band
CB CB-Conduction Band
FG
FG-Forbidden gap
VB
VB

(a) Fig 3.5 (b)

In Fig 3.5 (a) i) The VB is full-filled.

ii) Due to overlapping of VB & CB, the F.G. = 0.
So at room temperature also, there is presence of free electrons in CB. So
conductivity is more.
iii) It is found in most of conductors.
In Fig 3.5 (b) i) The VB is half-filled and CB is empty.
ii) The electrons present in one half, have a tendency to move to the
other half, i.e electrons have unidirectional flow i.e current flow is possible at room
temperature.
iii) It is found in few conductors like Na.
 43

ii) Semi conductor

Semiconductors are those substances whose electrical properties lie between those
of conductors and insulators.
Gallium arsenide and lead sulphide are other examples of semiconductors. Germanium
and silicon are the most commonly used semiconductors.
Here (i) VB is fullfilled and CB is empty.
(ii) Due to very less FG, it is
possible to make current flow by CB
applying some energy
FG
(iii) FG = 0.67 eV in Ge
= 1.1 eV in Si
VB
= 1.21 eV in GaAs
Properties of Semiconductors Fig 3.6
1. Semiconductors are crystalline in structure.
2. Resistivity of a semiconductor is less than that of an insulator and more than that
of a conductor.
3. Resistivity of a semiconductor decreases rapidly with the increase in temperature.
4. Semiconductors are good conductors at high temperatures; they are insulators at
low temperatures.
5. The distinctive feature of a semiconductor is the type and the degree of binding
between atoms.
6. Conductivity of a semiconductor is generally sensitive to temperature, illumination,
magnetic field and the impurity added.
iii) Insulator
These are the substances that never allow electric
CB
charges to flow.
Example : Wood, Sand, Paper etc.
FG > 5eV
Here (i) VB is Fulfilled & CB is empty.
(ii) Due to very large gap, It is
impossible to mate current flow. VB
(iii) FG > 5eV Fig 3.7
3.5 TEMPERATURE COEFFICIENT OF RESISTANCE (α ) :
It is the change in resistance per initial resistance per degree rise in temperature.
R 2 − R1
α=
R1 ∆t
R2 → Resistance a t20C
R1 → Resistance at T10C
 44 Basic Electronics

∆t = t 2 − t 1
α = +ve means, resistance increase with increase in temperature.
= –ve means resistance decreases with increase in temperature
3.6 DIFFERENT TERMS RELATED WITH SEMICONDUCTORS AND CONDUCTORS
Mobility (µ)
It is the ability of movement of carriers, like electrons & holes.
If µn / µe → mobility of electron
µp / µh → mobility of holes
Then µn > µp
µn is atleast 2.5 times of µp.
r r
Also v d α E (Q Vd = Drift vel.
r r r
⇒ v d = µE E = Electric field)
r
vd
⇒ µ= r
E
So it can be also defined as the drift velocity per unit electric field strength.
Its unit is m2/Volt. sec.
Conductivity (σ)
It is the ability of conduction of carriers. It is also defined as reciprocal of resistivity. It is
unit is mho/m.
Drift velocity (vd )
It is the small average velocity with which the carriers get drifted from one to other
terminal of supply.

l
Unit :- m/s or Cm/s
r
3.6.1 Relationship between vd, σ, I, E A e e
Consider a conductor of length ‘l’ e
e e
and area of cross-section ‘A’. A
voltage ‘V’ is supplied due to which I
r
an electric field ' E' is generated.
Q
I= V
t Fig 3.8
Q = Total charge
= Total no. of carriers (N) × charge of each carrier (e).
= Carrier density (n) × Vol. (A l ) × e
= n Ae l
 45

l
So, I = n Ae
t
= n Aev d
I
⇒ J= = nev d
A
= µneE
⇒ J = σE
So σ = neµ & ρ = charge density
= ne.
For electrons σ n = neµ n n = electron concentration
For holes σ p = Peµ p P = hole concentration
So total conductivity,
σ = σn + σp

d
⇒ σ = e nµ n + pµ p i
3.7 HOLE
When an energy is supplied to a semiconductor, a valence electron is lifted to a
higher energy level, the departing electron leaves a vacancy in the valence band. This
vacancy is called a hole.
Thus, a vacancy left in the valence band because of lifting of an electron from
valence band to conduction band is known as hole.
3.8 ELECTRON-HOLE PAIRS
Whenever, some external (heat) energy is supplied to a semiconductor, the valence
electrons are lifted-up to the conduction band one after the other leaving behind a vacancy
in the valence band called hole. The number of electrons to be lifted from valence band
to the conduction band depends upon the quantity of external energy supplied to the
semiconductor. If only one electron is lifted to the conduction band, then one hole is
created in the valence band. Thus, each time an electron-hole pair is formed.
It is important to note the hole (i.e. vacancy created by the electron in the valence
band) acts as a positive charge. It has strong tendency to attract the electrons from the
nearby co-valent bonds.
3.9 TYPES OF SEMICONDUCTORS
These are the materials whose conductivity lies between conductor and insulator.
There are mainly two types of semiconductor.
1) Intrinsic
2) Extrinsic
 46 Basic Electronics
3.9.1 Intrinsic Semiconductors
i) It is the semiconductor in pure form.
ii) It has no conductive power at room temperature.
iii) Eg :- Si, Ge, GaAS etc.
iv) Here no. of electrons are same as no. of holes.
If n = Electron concentration
& P = hole concentration
then n = P = ni (intrinsic carrier conc.)
So np = n 2i → Law of mass action

v) So σ n = n i eµ n
& σ p = n i eµ p

So σ i = n i e( µ n + µ p )

Si Ge
1) It is largely available in nature 1) It’s amount is small in nature.
2) It’s extraction is easier 2) It’s extraction is complex.
3) It is cheaper 3) It is costly.
4) It is more temp. stable 4) Comparatively less stability.

3.9.2 Extrinsic Semiconductor

To increase the conductivity of intrinsic semiconductor, Some suitable impurity is added.
The process of adding impurity is known as doping.
So the semiconductor in impure from is known as extrinsic semiconductor.
Intrinsic + Impurity = Extrinsic
There are mainly two types of extrinsic semiconductor.
I) P - Type II) N - Type
3.10 n-TYPE SEMICONDUCTOR
When a small amount of pentavalent impurity is added to a pure semiconductor
providing a large number of free electrons in it, the extrinsic semiconductor thus formed
is known as n-type semiconductor.
The addition of pentavalent impurities such as arsenic (atomic number 33) and
antimony (atomic number 51) provide a large number of free electrons in the semiconductor
crystal. Such impurities which produce n-type semiconductors are known as donor
impurities because each atom of them donate one free electron to the semiconductor crystal
as explained below :
W hen a sm allam ountofpentavalentimpurity like arsenic (AtNo.33 → 2,8,18, 5)
having five valence electrons is added to germanium crystal, each atom of the impurity
fits in the germanium crystal in such a way that its four valence electrons form covalent
 47

bonds with four germanium atoms as shown in Fig. 3.9. Whereas, the fifth electron of the
impurity (arsenic) atom finds no place in covalent bonds and is thus free. Hence, each
arsenic atom provides one free electron in the germanium crystal. Since, an extremely
small amount of arsenic impurity has a large number of atoms, therefore, it provides
millions of free electrons for conduction.
The energy band diagram of n-type semiconductor is shown in Fig. 3.10. With the
addition of pentavalent impurity, a large number of free electrons are made available in
the conduction band. These electrons are the free electrons which did not fit in the convalent

Fig. 3.9 Fig. 3.10

bonds of the crystal i.e. fifth electron of each arsenic atom. However, a minute quantity of
free electrons arc also available in the conduction band which are produced when thermal
energy at room temperature is imparted to the germanium crystal forming hole-electron
pairs. The following points are worth noting :
(i) A large number of free electrons are made available by the addition of pentavalent
impurity.
(i) A minute quantity of free electrons are made available by the generation of hole-
electron pair when thermal energy at room temperature is imparted to the
semiconductor crystal. These electrons leave behind holes in the valence band
(iii) The number of free electrons provided by Uie pentavalent impurity is far exceeding
the number of holes. It is due to this predominance of electrons over holes that the
material is called n-type semiconductor (n-stands for negative) material.
3.11 p-TYPE SEMICONDUCTOR
When a small amount oftrivalent impurity is added to a pure semiconductor providing
a large number of holes in it, the extrinsic semiconductor thus formed is krtown as p-type
semiconductor.
The addition of trivalent impurities such as gallium (atomic number 31) and indium
(atomic number 49) provide a large number of holes in the semiconductor crystal. Such
48 Basic Electronics
impurities which produce p-type semiconductors are known as acceptor impurities because
each atom of them create one hole which can accept one electron. This is explained below :

Fig. 3.11
When a small amount oftrivalent impurity like gallium (At. No. 31 → 2,8,18,3) having
three valence electrons is added to germanium crystal, each atom of the impurity fits in
the germanium crystal in such a way that its three valence elections form covalent bonds
with three surrounding germanium atoms as shown in Fig. 3.11. In the fourth covalent
bond, only germanium atom contributes one valence electron while gallium atom has no
valence electron to contribute, as all its three valence electrons are already engaged in the
covalent bonds. Hence, the fourth covalent bond is incomplete having one electron short.
This missing electron is called a hole. Thus, each gallium atom provides one hole in the
germanium crystal. Since an extremely small amount of gallium impurity has a large
number of atoms, therefore, it provides millions of holes in the semiconductor.
The energy band diagram of
p-type semiconductor is shown in Fig.
3.12. With the addition of trivalent
impurity, a large number of holes (the
vacant spaces in the covalent bonds
which can accept electrons) are made
available in the crystal. However, a
minute quantity of free electrons are
also available in the conduction band
which are produced when thermal
energy at room temperature is
imparted to the germanium crystal
Fig. 3.12
 49

forming hole-electron pairs. But the holes are much more in number than the conduction
band electrons. The following points may be noted carefully :
(i) A large number of holes are made available by the addition of trivalent impurity.
(ii) A minute quantity of hole-electron pairs are formed at room temperature because of
heat energy imparted to the semiconductor crystal. The free electrons (minute quantity)
thus formed are lifted to conduction band leaving behind holes in the valence band.
(iii) The number of holes provided by the trivalent impurity is far exceeding the number
of free electrons. It is due to this predominance of holes over electrons that the material
is called p-type semiconductor (p-stands for positive) material.
3.12 DISTINGUISH BETWEEN P-TYPE AND N-TYPE
P - Type N- Type
1) It is formed by adding trivalent impurity 1) It is formed by adding pentavalent impurity
to intrinsic semiconductor.The trivalent to intrinsic semiconductor The pentavalent
impurities are B, Al, In impurity are : N, As, Sb.
2) When trivalent impurity is added, all 2) When pentavalent impurity is added, 4 of
three electrons take part in bonding, but its outermost electrons take part in bonding
4th bond remain incomplete. To complete while one electron remain free.
the bond, an electron is borrowed from
neighbour creating a hole.
3) Here majority carriers are holes wile 3) Here majority are electrons & minority are
minority are electrons holes.
4) As majority carriers are produced by 4) As majority carriers are produced by the
accepting an electron, so the impurity is impurity, so known as donor type impurity.
also known as acceptor type impurity.
5) It has comparatively less conductivity 5) It has comparatively better conductivity.
6) As majority carriers are +vely charged, 6) As majority carriers are –vely charged, so
so it is P-type it is N-type.
Ø Both are electrically neutral.
Let ND → Donor ion concentration
NA → acceptor ion concentration

Then n + N A = p + N D → Law of neutrality..

For n - type
NA ≅ 0
& n>>p
so n + 0 = p + ND

⇒ n ; ND
 50 Basic Electronics

n 2i n2
⇒ p= ⇒ n= i
n ND
For P-type
ND ≅0
& p>>n
So n + NA = p + 0

n 2i
⇒ p ; NA ⇒ n=
NA

Example 3.1 :
In a certain copper conductor, the current density is 2.4 A/mm2 and electron density
is 5 × 1028 free electrons per m3 of the copper. Determine the drift velocity of the
electrons.
Solution : Current density, J= 2.4 A/mm 2 = 2.4 × 106 A/m2
Electron density, n = 5 x 1028
Electron charge, e = 1.6 × 10–19 coulomb
Since from expression (4.20) J = e.n.v

J 2.4 × 106
∴ drift velocity, υ = = = 0.3 × 10–3 m/s or 0.3 mm/s
en 1.6 × 10 −19 × 5 × 1028
Example 3.2 :
A conductor material has a free electron density of 1024 electrons per m3. When a
voltage is/applied, a constant drift velocity of 1.5 × 10–2 m/s is attained by the
electrons. If the x-sectorial area of the material is 1 cm2 calculate the magnitude of
current. Electronic charge is 1.6 × 10–19 coulomb.
Solution : Electron density, n = 1024
Electron charge, e = 1.6 × 10–19 C
Drift velocity, v = 1.5 × 10–2 m/s = 0.015 m/s
Cross-sectional area, a = 1 cm2 = 1 × 10–4 m2
Magnitude of current, I = n aev = 1.6 × 10–19 × 1024 × 0.015 × 1 x 10–4= 0.24 A
Example 3.3 :
A specimen of germanium at 300° K for which the density of carriers is
2.5 × 1013/ cm3, is dopped with impurity atoms such that there is one impurity atom
for 106 germanium atoms. All the impurity atoms may be assumed ionized. The
resistivity of doped material is 0.039 Q-cm./Carrier mobility for germanium at
300° K is 3,600. For the doped material, find the electron and/hole densities, e =
1.602 × 10–19 C.
 51

Solution: Resistivity of doped material, ρ = 0.039 Ω-cm

1 1
Conductivity of doped material, σ n = =
ρ 0.039 = 25.64 S/cm
Electron charge, e = 1.602 × 10–19 C
Carrier mobility, µe = 3,600 cm2 / V-s
Since σn = n e µe = ND e µe
σn 25.64
So concentration of donor atoms, ND = eµ = 16 3
e 1602
. × 10 −19 × 3,600 = 4.45 x 10 /cm
Concentration of electrons n ~ ND = 4.45 × 1016/cm3 Ans.

Concentration of holes, p =
n 2i
=
d
2.5 × 10 i
13 2
= 1.4 x 1010/cm3 Ans.
n 4.45 × 1016
Example 3.4 :
A donor type impurity is added to the extent of 1 atom per 106 atoms of an intrinsic
semiconductor (silicon). Calculate:
(i) Resulting donor atom concentration,
(ii) Resulting mobile electron concentration.
(iii) Resulting hole concentration.
(iv) Conductivity of doped silicon sample.
(v) If silicon bar is 0.5 cm long, cross-sectional area of (50 × 10–4)2 cm2. Find
its resistivity. The concentration of silicon atoms = 5 ×1022 cm–3 and
ni = 1.45 × 1010 cm–3
Solution: (i) Donor atom concentration, ND = Number of silicon atoms/cm3 × donor impurity
1
= 5 × 10 × = 5 × 1016 per cm3
22
Ans.
106
(ii) Mobile electron concentration, n ~ ND = 5 × 1016 cm2 Ans.

n 2i . × 1010 ) 2
(145
(iii) Hole concentration, p = = = 4.205 × 103 / cm3 Ans.
ND 5 × 1016
(iv) Conductivity of doped silicon sample,
σ = ne µ e = 5 × 1016 × 1.602 × 10 −19 × 1,300 = 10.413 S/cm Ans.
Taking µe for Si as 1,300 cm2/Vs
1 1
Resistivity, ρ = = − 0.096 Ω cm
σ 10.413
ρl 0.096 × 0.5
Resistance of given semiconductor, R = ρ = = − 1920
. Ω Ans.
a (50 × 10−4 ) 2
 52 Basic Electronics
Example 3.5 :
What is the concentration of holes in Si crystals having donor concentration of 1.4
x 1024/cm3 when the intrinsic carrier concentration is 1.4 x I018/m3 ? Find the ratio
of electron hole concentration.
Solution: Intrinsic carrier concentration, ni - 1.4 x 1018/m3
Donor concentration, ND = 1.4 x 1024/m3
Concentration of electrons, n ~ ND = 1.4 x 1024/m3
. × 1018 ) 2
n 2i (14
Concentration of holes p = = = 14
. × 1012 / m 3
n 14. × 1024
. × 1024
n 14
Ratio of electron to hole concentration = = = 1 × 1012 Ans.
. × 1012
p 14
Example 3.6 :
Find the conductivity and resistivity of an intrinsic semiconductor at temperature
of 300°K. It is given that
ni = 2.5 × 1013/cm3, µn = 3,800 cm2/sV; µp = 1,800 cm2/sV, q = 1.6 × 10–19 C.
Solution: Intrinsic concentration, ni = 2.5 × 1013/cm3
Electron charge, e = 1.6 × 10–19 coulomb
Hole mobility, µh = 1,800 cm2/sV
Electron mobility, µe = 3,800 cm2/sV
Intrinsic conductivity, σi = ni e (µe + µh)
= 2.5 × 1013 × 1.6 × 10–19 (3,800 + 1,800)
= 0.0224 S/cm Ans.
1 1
Intrinsic resistivity, pi = = = 44.64 Ω − cm Ans.
σ i 0.0224
Example 3.7 :
The intrinsic resistivity of germanium at 300° K is 0.47 ohm-m. The electron mobility
(µe) at 300 K in germanium is 0.39 m2/Vs. The hole mobility µh at 300° K in
o

germanium is 0.19 m2/Vs. The electronic charge (e) is 1.6 × 10–19 C. Calculate the
density of electrons in the intrinsic material. Also calculate the drift velocity of
holes and electrons for an electric field (E) = 104 V/m.
Solution : Intrinsic resistivity, ρi = 0.47 Ω-m
1 1
Intrinsic conductivity, σi = = = 2.12766 S/m
ρi 0.47
Electron mobility, µe = 0.39 m2/Vs
Hole mobility, µh = 0.19 m2/Vs
 53
–19
Electron charge, e = 1.6 × 10 C
Since or. σi = nie (µe + µh)
∴ Density of electrons = Intrinsic concentration ni
σi 2.12766
= = − 2.293 × 1019 / m3
b
e µe + µhg −19
. × 10 (0.39 + 019
16 . ) Ans.

Electric field, E = 104 V/m

Drift velocity for electrons, υn - µe E = 0.39 × 104 = 3,900 m/s Ans.
Drift velocity for holes, υh = µh E = 0.19 × 104 = 1,900 m/s Ans.
Example 3.8 :
The intrinsic carrier concentration for silicon at room temperature
(300° K) is 1.5 × 1010/cm3. If the mobilities of electrons and holes are 1,300 cm2/Vs
and 450 cm2/Vs respectively, what is the conductivity of silicon (intrinsic) at
300° K ? If silicon is doped with 1018 boron atoms per cc, what is its conductivity ?
Solution: Intrinsic carrier concentration of silicon,
ni = 1.5 x 1010/cm3
Hole mobility, µh = 450 cm2/Vs
Electron mobility, µe =1,300 cm2/ Vs
Conductivity of silicon (intrinsic),
σi = nie (µe + µh) = 1.5 × 1010 × 1.6 × 10–9 × (1,300 + 450)
= 4.2 × 10–6 S/cm Ans.
Doping level, NA = 1018/cm3
Conductivity of the resulting P-type silicon semiconductor,
σp = eNAµh (µe + µh) = 1.5 × 1010 × 1.6 × 10–9 × (1,300 + 450)
= 1.6 x 10"19 x 1018 x 450 = 72 S/cm Ans.
Example 3.9 :
Find the conductivity of intrinsic germanium at 300° K. If donor type impurity is
added to the extent of 1 impurity atom in 107 germanium atoms, find the conductivity.
Give that ni at 300° K is 2.5 × 1013/cm3 and µn and µp in germanium are 3,800 and
1,800 cm2/Vs respectively
Solution : Intrinsic conductivity, σp = ni e (µe + µh)
= 2.5 × 1013 × 1.6 × l0–19 (3,800 + 1,800)
= 0.0224 S/cm Ans.
3 22
Number of germanium atoms/cm = 4.41 × 10
Donor impurity = 1 donor atom/107 germanium atoms
Concentration of donor atoms, ND= 4.41 × 1022 × 10–7 = 4.41 × 1015/cm3
Concentration of electrons, n ~ ND = 4.41 × 1015/cm3
n 2i ( 2.5 × 1013 ) 2
Concentration of holes, p = = = 1417
. × 1011 holes/cm3
ND 4.41 × 1015
 54 Basic Electronics
So conductivity in N-type germanium semiconductor
σn = eND µe = 1.6 × 10–19 × 4.41 × 1015 × 3,800 = 2.68 S/cm Ans.
Example 3.10 :
A p.d of 10 V is applied longitudinally to a rectangular specimen of intrinsic
germanium of length 25 mm, width 4 mm and thickness 1.5 mm. Determine at
room temperature (i) electron and hole drift velocities (ii) the conductivity of intrinsic
germanium if intrinsic carrier density is 2.5 × 1019/m2 and (iii) the total current.
Given that e - 1.6 × l0–19 C, µe = 0.38 m2 V–1 s–1. µh = 0.18 m2 V–1 s–1
10
Solution: Applied electric field, E = V/l = = 400 V / m
0.025
(i) Electron drift velocity, υe = µe × E = 0.38 × 400 = 152 m/s Ans.
Hole drift velocity, υh = µh x E = 0.18 × 400 = 72 m/s Ans.
19 2
Intrinsic carrier concentration, ni = 2.5 × 10 /m
(ii) Intrinsic conductivity of Ge,σi = ni e (µe + µh)
= 2.5 × 1019×1.6 ×10–19(0.38 + 0.18) = 2.24 S/m Ans.
(iii) Total current, I = σi E a = 2.24 × 400 × 4 × 10–3 × 1.5 × 10–3
= 5.376 mA Ans.

SHORT QUESTIONS & ANSWERS

Q.1 Why electronic devices are made up of semiconductors not conductors ?

Ans : i) Because α = +ve for conductors, gradually conductivity decreases with rise in temp.,
so can’t be used for electronic devices.
But α = –ve for semiconductors, so conductivity increase with size in temp.
ii) Also semiconductor is more temperature stable than conductor.
Q.2. Energy band gap of some unknown materials is given below :
(1) 15 eV (2) 0.6 eV (3) Overlapping.
Distinguish their respective class as metal, semiconductor and insulator.
Ans. Energy band gap Class
(1) 15 eV Insulator.
(2) 0.6 eV Semiconductor.
(3) Overlapping Conductor.
Q.3 Why the energy levels of an atom become energy bands in a solid.
Ans. For the single isolated atom, there are discrete energy levels, Is, 2s, 2p, 3s, that will be
occupied by the electrons of atom. All the atoms of a solid can have identical electronic
schemes for their energy levels. If atoms are isolated from one another then the electrons
 55

fill the levels in each atom independently but when isolated atoms are brought together to
form a solid, the energy levels are considerably affected because of interaction between
nearer atoms. There will be a coupling between the outer-shell electrons of the atoms
resulting in a band of closely spaced energy states, instead of widely separated energy
levels of the isolated atom.
Q.4 What is the importance of valence shell and valence electrons?
Ans. The outermost shell of an atom is called the valence shell and electrons in this shell are
called the valence electrons. Formation of energy bands occur owing to overlapping of
energy levels of these valence electrons in valence shells. With the decrease in interatomic
distance between the atoms in a crystal, the energy levels of electrons in outermost shells
of atoms overlap to form energy bands.
Q.5 What is the forbidden energy gap? How does it occur? What is its magnitude for Ge and
Si?
Ans. The energy gap between the valence band and conduction band is known as forbidden
energy gap. It is a region in which no electron can stay as there is no allowed energy state.
Magnitude of forbidden energy gap in germanium and silicon is 0.72 eV and 1.12 eV
respectively at 300 K and 0.785 eV and 1.21 eV respectively at absolute zero temperature.
Q.6 Is hole a fundamental particle in an atom?
Ans. Hole is not a fundamental particle in an atom. Holes may be thought of as positive particles,
and as such, they move through an electric field in a direction opposite to that of electrons.
Q.7 Define a hole in a semiconductor.
Ans. When an energy is supplied to a semiconductor, a valence electron is lifted to a higher
energy level, the departing electron leaves a vacancy in the valence band. This vacancy is
called a hole. Thus, a vacancy left in the valence band because of lifting of an electron
from valence band to conduction band is known as hole.
Q.8 What is hole current?
Ans. The movement of the hole (positively charged vacancy in the valence band) from positive
terminal of the supply to the negative terminal through semiconductor constitutes hole
current.
Q.9 What is intrinsic semiconductor?
Ans. An intrinsic semiconductor is one which is made of the semiconductor material in the
extremely purely form (impurity content not exceeding one part in 100 million parts of
semiconductors).
Q.10 Why silicon and germanium are the two widely used semiconductor materials?
Ans. Because the energy required to release an electron from their valence band (i.e., to break
their covalent bonds) is very small (1.12 eV for Si and 0.72 eV for Ge).
Q.l1 Which of the two semiconductor materials Si or Ge has larger conductivity at room
temperature? Why ?
Ans. Since energy required in transferring electrons from valence band to conduction band is
more in case of silicon than that in case of germanium, the conductivity of Ge will be
 56 Basic Electronics
more than that of Si at room temperature.
Q.12 Why does a pure semiconductor behave like an insulator at absolute zero temperature?
Ans. For a pure semiconductor at a temperature of absolute zero (– 273.15°C) the valence
band is usually full and there may be no electron in the conduction band and it is difficult to
provide additional energy required for lifting electron from valence band to conduction
band by applying electric field. Hence the conductivity for a pure semiconductor at absolute
zero temperature is zero and it behaves like an insulator.
Q.13 What is the main factor for controlling the thermal generation and recombination?
Ans. Temperature, because with the increase in temperature, concentrations of free electrons
and holes increase and the rate of recombination is proportional to the product of
concentrations of free electrons and holes and also the rate of production of electron-hole
pairs (thermal generation) increases with the rise in temperature.
Q.14 Define mean life time of a carrier.
Ans. The amount of time between the creation and disappearance of a free electron is called the
life time. It varies from a few nanoseconds to several micro-seconds depending how perfect
the crystal is and other factors.
Q.15 In which bands do the movement of electrons and holes take place ?
Ans. Free electrons move in conduction band while holes in valence bands.
Q.16 What is the mechanism by which conduction takes place inside the semiconductor.
Ans. Conduction occurs in any give material when an applied electric field causes electrons to
move in a desired direction within the material. This may be due to one or both of two
processes, electron motion and hole transfer. In case of former process, free electrons in
the conduction band move under the influence of the applied electric field.
Q.17 Define mobility of a carrier. Show that the mobility constant of electron is larger than that
of a hole.
Ans. Mobility is defined us the average particle drift velocity per unit electric field.
The mobility of electrons is more than that of holes because the probability of an electron
having the energy required to move to an empty state in the conduction band is much
greater than the probability of an electron having the energy required to move to the
empty state in valence band. The mobility of electron is about double that of an hole.
Q.18 What are the two conduction processes in semiconductor?
Ans. Conduction through a semiconductor is due to two processes, viz., drift and diffusion.
Flow of drift current is due to the potential gradient that is the result of external applied
field to the semiconductor while diffusion current is caused due to concentration gradient
of the charge carriers that is the result of non-uniform concentration of charge carriers in
the semiconductor.
Q.19 Define diffusion current in a semiconductor.
Ans. The diffusion of charge carriers is as a result of a gradient of carrier concentration (i.e.,
the difference of carrier concentration from one region to another). In this case
 57

concentrations of charge carriers (either electrons or holes) tend to distribute themselves

uniformly throughout the semiconductor crystal. This movement continues until all the
carriers are evenly distributed throughout the material. This type of movement of charge
carriers is called the diffusion current.
Q.20 Define drift current in a semiconductor.
Ans. The steady flow of electrons in one direction caused by applied electric field constitutes
an electric current, called the drift current.
Q.21 What happens to the conductivity of the semiconductor with the rise in temperature?
Compare with the conductivity of metals.
Ans. With the increase in temperature, the concentration of charge carriers increases resulting
in increase of conductivity of semiconductors. The conductivity of metal decreases with
the increase in temperature.
Q.22 Why the temperature coefficient of resistance of a semiconductor is negative?
Ans. With the increase in temperature, the concentration of charge carriers (electrons and holes)
increases. As more charge carriers are made available, the conductivity of a pure
semiconductor increases i.e. resistivity of a pure semiconductor decreases with the rise in
temperature i.e. semiconductors have negative temperature coefficient of resistance
Q.23 What are P- and N-type semiconductors ?
Ans. When a small amount of trivalent impurity (such as boron, gallium, indium or aluminium)
is added to a pure semiconductor crystal during crystal growth, the resulting crystal is
called the P-type semiconductor.
When a small amount of pentavalent impurity (such as arsenic, antimony, bismuth or
phosphorus) is added to a pure semiconductor crystal during crystal growth, the resulting
crystal is called the N-type semiconductor.
Q.24 What do you mean by donor and acceptor impurities?
Ans. Donor impurities (such as arsenic, antimony, bismuth or phosphorus) when added to a
pure semiconductor lattice, form N-type extrinsic semiconductor. The pentavalent
impurities are called the donor type impurities as such impurities donate electrons to the
lattice.
Acceptor impurities (such as boron, gallium, indium or aluminium) when added to a pure
semiconductor lattice form p-type intrinsic semiconductor. The trivalent impurities are
called the acceptor type impurities because such impurities accept electrons from the
lattice.
Q.25 Name the three elements which are used as N-type and P-type impurities.
Ans. N-type impurities — arsenic, antimony, bismuth.
P-type-impurities — boron, gallium, indium.
Q.26 Explain the term doping and its need.
Ans. The electrical conductivity of intrinsic semiconductor, which has little current conduction
capability at ordinary room temperature and so is of little use, can be increased many
 58 Basic Electronics
times by adding very small amount of impurity (of the order of one atom per million atoms
of pure semiconductor) to it in the process of crystallization. This process is called the
doping.
Q.27 What type of impurities make a semiconductor N-type ?
Ans. The pentavalent, donor or N-type impurities such as arsenic, antimony, bismuth, phosphorus
make N-type semiconductor.
Q.28 What are the impurities which make a semiconductor P-type?
Ans. The trivalent, acceptor or P-type impurities such as boron, gallium, indium, aluminium,
make P-type semiconductor.
Q.29 Are N-type and P-type semiconductor materials neutral?
Ans. N-type and P-type semiconductor materials are neutral.
Q.30 What are the minority carriers in N-type and P-type ?
Ans. Holes and electrons are the Minority Carriers in N-type and P-type respectively.
Q.31 What are the majority and minority carriers in P-type semiconductor materials?
Ans. Holes are majority carriers and free electrons are minority carriers in P-type semiconductor
materials.
Q.32 What is the effect of temperature on extrinsic semiconductors?
Ans. With the increase in temperature of an extrinsic semiconductor, the number of thermally
generated carriers is increased resulting in increase of concentration of minority carriers.
At temperature exceeding critical temperature the extrinsic semiconductor behaves like
an intrinsic semiconductor but with higher conductivity.
Q.33 What are the charge carriers in N-type and P-type semiconductors ?
Ans. Free electrons in N-type semiconductors ani holes in P-type semiconductors are the charge
carriers.
Q.34 For the same order of doping, why does N-type semiconductor exhibit larger conductivity
than P-type semiconductor ?
Ans. Since the mobility of electrons is greater than that of holes, for same level of doping,
N-type semiconductor exhibits larger conductivity.

EXERCISE
1. Find the resistivity of intrinsic Ge at 313 K. Given nn = 0.39 m2/Vs, np = 0.19 m2/Vs and
intrinsic carrier density, ni = 2 × l019/m3 at 313 K. [Ans. 53.88 × 10–2 Ω- m]
2. The effective masses of hole and electron in GaAs semiconductor are 0.48 mg and 0.067 m0
respectively, where m0 is the free electron rest mass. Its band gap energy is 1.43 eV. Calculate
its Fermi energy in eV at 300 K. [Ans. 0.75 eV]
3. Calculate the mobility of electrons in iron whose resistivity is 10 × 10–8Ωm. Atomic weight
of iron is 55.85 × 10–3 kg/mol and its density is 7870 kg/m3. Avogadro’s number = 26.02 ×
1023. [Ans. 7.367 × 10–4 m2/V]
 59

4. An n-type semiconductor has a resistivity of 20 × 10 Ωm. The mobility of the electrons

–2

through a separate experiment was found to be 100 ×10–4 m2/Vs. Find the number of electron
carriers per m3. [Ans. 0.44 × 10–3 Sm–1; 0.75 × 10–3 Sm–1]
5. At room temperature, electron mobility in gallium arsenide is 8000 cm2/Vs. Calculate the
diffusion constant for electrons. [Ans : 208 cm2 s–1]
6. Assuming that each atom contributes one conduction electron in copper, calculate the number
of charge carriers per m3. The conductivity of copper is 5.8 × 107 S/m. Also compute the
electron mobility. Given atomic weight of copper = 63.5, density = 8.94 gm/cc, Avogadro’s
number = 6.023 x 1023. [Ans : 8.5 × 1028/m3, 4.26 × 10–3 m2/Ns]
7. Determine the conductivity and resistivity of intrinsic silicon at 200 K, 300 K and 500 K.
The electron and hole mobilities of silicon are given by µp = 4 x 105 T–26 m2/Vs and µn = 2.5
× 104 T–23 m2/Vs. Assume that the carrier densities of pure silicon are ni = 3.8 × 105/cm3 at
200 K and ni = 2 × 1010/cm3 at 300 K. [Ans : 3 × 107 Ωm; 1.6 × 103 Ωm]
8. The intrinsic carrier density of Ge at 27° C is 2.40 × 109/m3. Calculate its intrinsic resistivity
if the electron and the hole mobilities are 0.38 m2 V–1 s–1 and 0.18 m2 V–1 s–1 respectively.
[Ans : 0.46 Ωm]
9. Calculate the drift velocity of free electrons in a copper conductor of cross-sectional area
10–4 m2 and in which there is a current of 200 A, assuming the free electron density of
copper to be 8.5 × 1028 m–3. [Ans : 1.47 × 10–4 ms–1]
10. The intrinsic resistivity of Ge at 27° C is 0.47 Ω m and the electron and hole mobilities are
0.38 and 0.18 m2/Vs. Calculate the intrinsic carrier density at the given temperature.
[Ans : 2.37 × 1019 m–3]
11. Find the density of impurity atoms that must be added to an intrinsic silicon crystal to
convert it to (a) 10–1 Ω m p-type silicon and, (b) 10–1 n-type silicon. For Si, µn = 0.135 m2/
V.s and µp = 0.048 m2/V.s. [Ans : 1.3 × 1021 m–3, 4.63 × 1020 m–3]
12. An n-type semiconductor has a resistivity of 20 × 10–2 Ωm. The mobility of the electrons
through a separate experiment was found to be 100 × 10–4 m2 V–1 s–1. Find the number of
electrons per m3. [Ans : 3.1 × 1021]

ppp
 60 Basic Electronics

Semiconductor Diode CHAPTER

4.1 INTRODUCTION
When a germanium or silicon crystal contains donor impurities on one side and
acceptor impurities on the other side, a p-n junction is formed.
The p-n junction is a very important device. The most remarkable property of the
p-n junction is that, it allows current in one direction and opposes in the opposite direction.
Practically all semiconductor devices contain at least one p-n junction. The production
techniques enable the fabrication of p-n junctions to suit specific purposes. Thus, a varicap
which acts as a variable capacitor, a tunnel diode and a gunn diode as oscillator, a Zener
diode as a voltage regulator, a photodiode as a light detector, solar cell as a voltage
source, an LED (Light Emitting Diode) and a laser as light sources are all p-n junctions.
Thus, the p-n junction has led to all kinds of inventions including diodes, transistors and
integrated circuits.
4.2 DEFINITION
It is a two terminal unidirectional device. i.e. it allows current to flow only in one direction.
It is an active device. e.g. vaccum diode, p-n junction diode etc.
4.3 p-n JUNCTION DIODE
This is a type of diode that is made up of a p-type and n - type semiconductor superimposed
on each other.
4.3.1 Fabrication of diode

1) pure semiconductor crystal is taken. Si

2) Trivalent impurity is added to form P-type semiconductor.

UV
Si + ln ⇒ P − type ray
3) A region is defined with the help of UV ray

P-type
 61

4) To the defined region, pentavalent impurity is added to form n-type.

n-type
+ As
P-type p type Fig. 4.1
5) There is an interface created that separates P type and n type semiconductor, known
as junction.

P n

Fig. 4.2
(Diode Symbol)

6) The techniques used for formation of diode are growing, alloying and diffusion
method.
4.3.2 Mechanism in diode
P N
1) P-type has majority carriers as holes,
& minority carriers as electrons.
2) N-type has majority electrons while
minority carriers are holes.
3) So there is a concentration difference
of carriers on either side of junction.
Due to this, electrons on N-side have
a tendency to move to P-side & holes
on P-side have tendency to move to Fig. 4.3
Depletion Region
n-side.
4) By this process, +ve ions are generated on N-side & –ve ions are generated on
P-side, near the junction.
5) So there is a region created near the junction, only consisting of immovable ions
i.e. depleted or absence of movable carriers. So this region is known as depletion
region.
6) The +ve ions on n-side restrict the holes on p-side to cross the junction. Similar is
the case for electrons.
7) So this region acting like a barrier by creating a potential difference across the
junction. So this region is also known as Potential barrier.
 62 Basic Electronics
4.4 BIASING
It means to give external ‘dc’ to an electronic device for a defined operation. So it is also
known as dc analysis. It provides the operating point of the device.
In case of diode there are two types of biasing -
1) Forward Biasing ( Vdiode > 0 )
2) Reverse Biasing ( Vdiode < 0 )

4.4.1 Forward Biasing

P N

e e
Fig. 4.4
VD
Ø The diode is said to be forward-biased if p-type is connected to +ve terminal and
n-type is connected to -ve terminal of the supply.
Ø The +ve terminal of supply attract the electrons there by creating +ve ions and
neutralizes –ve ions on p-side near the junction.;
Ø The –ve terminal of supply repel the electrons & pour –ve ions that neutralizes
+ve ions on n-side near the junction.
Ø So the width of depletion region decreases and at a particular voltage, the depletion
region vanishes and there is sharp rise in current.
This voltage is known as threshold / knee voltage.
Ø The current is in range of mA. ID

The point on the curve after which

there is appreciable rise in current,
known as knee point. Knee point
VTh = Vk = 0.3V Ge b g VTh VD
= 0.7V (Si)
= 1.1 V (GaAs)
Fig. 4.5
 63

4.4.2 Reverse Biasing P N

Ø The diode is said to be reverse
biased, if p-type is connected to
–ve terminal & n-type is
connected to +ve terminal of the
supply.
Ø The –ve terminal pour –ve ions
on p-side and the +ve terminal
pour +ve ions on n side. So the Fig. 4.6
width of depletion region VD
increases. ID
(mA)
Ø So there is no current due to
majority carriers & current flow VBr VD
occurs due to minority carriers IO
only. This current is known as
reverse saturation current /
leakage current (IO). Zener
(µA)
Ø The current is in the range of µA. region
4.4.3 V - I characteristic
Fig. 4.7

ID
(mA)

VBr Knee point

IO VTh VD

Zener
region (µA)

Fig. 4.8

4.5 DIODE CURRENT EQUATION

Let ID = Current Flowing through the diode
I0 = Reverse Saturation current
VD = Voltage across diode
T = absolute temperature
Then the current equation is given by
 64 Basic Electronics

I D = I0  e T − 1
KVD

 
Here k = constant
11,600
=
r
n = 1 for Ge, Si at higher temp.
= 1 for Ge
& 2 for Si at very low temp.
In reverse biasing condition VD is of higher –ve value, so
ID = I0 (0 – 1)
= I0
4.6 BREAKDOWN
The phenomenon in reverse biasing where the diode is no more behaving like a
diode and there is sudden rise in current.
The region where this occur, is known as Break down region.
The voltage at which this occur is known as breakdown voltage (VBr).
There are two types of breakdowns :-
1) Avalanche Breakdown
2) Zener Breakdown
4.6.1 Comparison between Avalanche Breakdown and Zener Breakdown
Avalanche Breakdown Zener Breakdown
1) This breakdown occurs due to higher 1) This occurs due to stronger electric field
velocity of minority carriers. across the diode.
2) This occurs in a diode with lower 2) It occurs in a heavily doped diode.
doping level.
3) Due to less doping, the width of 3) Due to heavily doped, the width of depletion
depletion region is more. region is less.
So when a higher voltage is given, So when a comparatively lower voltage is
then velocity of minority carriers r V
increases towards opposite type given, then as E = , higher electric field
semiconductor. When they collide d
with walls of semiconductor, free is generated. Due to strong electric field, the
electrons are generated. When free covalent bonds breakdown and free
electrons are sufficient, then there is electrons are generated. when they are
sharp rise in currents & breakdown
sufficient, there is sharp rise in current
occurs.
& breakdown occurs.
4) It occurs at higher voltage.
4) It occurs at lower voltage.
 65

5) The characteristic graph after breakdown 5) The graph after breakdown is sharper.
is not so sharper.
6) The diode where this breakdown occur is 6) the diode where this breakdown occur is
known as avalanche / general diode. known as zener diode.
7) This type of diode is used in rectifier, 7) This type of diode is used in voltage
clipper clamper etc. regulator / stabilizer.
ID
ID
VD
VD

4.6.2 PIV / PRV

Ø It stands for peak Inverse Voltage / Peak Reverse voltage. It is the maximum
reverse bias voltage that can be given to a diode just before entering to the
breakdown region.
Ø It is the maximum safe operating voltage of diode.
4.7 ZENER DIODE
Ø It is like an ordinary P-N junction diode except that it is properly doped so as to
have sharp breakdown voltage.
Ø It is also sometimes called as breakdown diode because it is specially designed to
operate in breakdown region in reverse bias condition.
Ø It operates as normal diode in forward bias condition but in reverse bias condition,
It has sharp breakdown region.
Ø The symbol of zener diode is similar to that of a normal diode except that the line
representing cathode is bent at both ends i.e. z-shape; stands for zener.

Fig. 4.9
Ø The V.I characteristics of zener diode is :
66 Basic Electronics

Fig.4.10
VK = Knee voltage
I0 = Reverse Saturation current
VZ = Zener Voltage
Ø Zener diode has two equivalent circuits, given below.

(a) Zener diode symbol (b) complete (c) Approximate

equivalent circuit equivalent circuit
Fig. 4.11
Ø Zener voltage may be affected by change in the ambient temperature. The effect
of temperature an zener voltage is given in terms of temperature coefficient which
is defined as percentage change in nominal zener voltage for each degree centigrade
change in junction temperature.
∆VZ
Mathematically it is given by × 100
V2 ( t − t 0 )

Here ∆VZ = Change in zener voltage.

t – t0 = temperature variation.
Temperature coefficient is –ve for VZ < 5 Volt.
 67

Temperature coefficient is +ve for VZ < 6 Volt.

Between 5 to 6 volt; there is a point where temperaure coefficient will be zero,
which is important feature for some application where zener diode has to operate
over a wide range of temperature.
Ø Due to heavily doping, the depletion region is very thin, so reverse voltage or
zener voltage will be very low.
Because zener diode operates in breakdown region, It does not burn out
immediately.
Ø Application :
l Voltage regulation
l Meter protection
l Peak Clipper
l as a reference
l Voltage regulation element.
l Switching operation
4.8 RESISTANCES IN DIODE
Resistance is the opposition offered to the current flow.
The resistance can be determined where ohm’s law is satisfied. It occurs after
knee point in forward biasing graph of diode.
There are three types of resistances :-
i) Static or DC resistance
ii) Dynamic or AC resistance.
iii) Average AC resistance ID
4.8.1 Graphical Determination
(i) Static / DC resistance (RDC) IP P
Ø A point is taken where DC resistance
is to be determined.
Ø At that point, corresponding voltage
VD
& current is determined. Fig. 4.12 V P
Vp
Ø Then R DC = ID
Ip
ii) Dynamic / AC resistance (rac) IA A
Ø A point (p) is taken where ac P
resistance is to be determined. IB B
Ø A tangent is drawn to the curve at V B VA VD
point ‘p’. Fig. 4.13
 68 Basic Electronics
Ø Two points (A & B) on the tangent are taken symmetrically about the point ‘p’.
Ø Voltage & current at A & B are determined.
∆VD VA − VB
Ø Then rac = =
∆I D IA − I B
iii) Average ac resistance
ID
Ø A point ‘P’ is taken on the curve where
average ac resistance is determined.
IA’ A’
Ø Two points (A’ & B’) are taken on the curve,
symmetrically about the point ‘p’. P
Ø Voltage & current at A’ & B’ are determined. IB’ B’
∆VD VA ' − VB'
Ø Then R avg = = V B’ VA’
∆I D I A ' − I B' VD
4.8.2 Mathematical determination of AC resistance Fig. 4.14

d
Know that I D = I O e D − 1
KV / T
i
Differentiating w.r.t. VD,
dI D K
= I 0 . . e KVD T

dVD T

= dK
T
I 0e KVD T
i
= bI g
K
D + I0
T

~
K
T
b
ID Q I D> > IO g
dV T
⇒ dI = KI
D

D D

T
⇒ rac =
KI D
At room temperature (270C), T = 273 + 27 = 300 K
11600
K= = 11600
η

lQ η = 1q
 69

300
So rac = ID
11600

bQ I g
26mV
rac ~ in mA
ID D

4.9 CAPACITANCE IN DIODE / CAPACITIVE EFFECT OF DIODE

The diode is the super impose of P-type & n-type P N
semiconductor. The region ‘I’ can be considered
as +ve charged plate as majority are holes.
The region II can be considered as –ve
charged plate as majority carriers are electrons.
The region III is considered as dielectric
because of depletion region.
I III II
So it is equivalent to a parallel plate capacitor.
Fig. 4.15
There are two types of capacitance :-
i) Diffusion / Storage capacitance (CD)
ii) Transition / space-charge capacitance (CT)
‘CD’ is present in forward biasing configuration, &
CT is present in Reverse biasing configuration
εA
As C= ε → permittivity of dielectric
d
A → Area of semiconductor
d → width of depletion region

Now as, dforward < < dreverse ⇒ C D >> CT

4.10 DIODE EQUIVALENT MODELS

Ø These are the models whose characteristic is close to diode characteristic.
Ø These are the approximation to the diode. These models makes the diode analysis,
simpler.
There are three equivalent circuits :-
4.10.1 Piece wise linear equivalent model
Practical diode contains, as barrier dc voltage or threshold voltage (V T), ac resistance(r),
capacitance (c) & an ideal diode.
The capacitance is non-linear component, & this model shows every piece of diode that
are linear.
 70 Basic Electronics
The model is →

r Ideal
VT
diode Fig. 4.16

ID

VT VD
4.10.2 Simplified equivalent model
Here apart from capacitor, resistance is neglected.

ID

VT Ideal
diode
VT VD
Fig. 4.17
Load - Line analysis
Ø This is the analysis where the point of operation of the device can be obtained.
Ø This point is known as operating point or Quioscent point.
Ø It can be obtained by intersection of device characteristic graph and load line.
Ø The graph that represents the characteristic of load is known as load line.
Ø Consider a diode circuit :-
IB
Now applying KVL,
E – VD – IDR = 0 VD
⇒ E = VD + IDR R
⇒ VD = E – IDR → load-line equation
E

When ID = 0, VD = E ⇒ a point (E, 0)

E FG E IJ
When VD = 0, ID =
R
⇒ another point 0, H RK Fig. 4.18
 71

The line joining two points is Load line.

ID

E Characteristics (device)
R

IDQ Q-Point

Load Line (network)

0 VD
VDQ E
Fig. 4.19
4.10.3 Ideal equivalent model
Here the diode is only replaced by ideal diode.

ID

Ideal diode
Fig. 4.20 VD
4.11 DIODE SPECIFICATIONS
1. Peak Inverse Voltage (PIV): It is the maximum reverse voltage that can be applied
to the diode without destruction.
2. Average Forward Current [IF(av)] : It is the continuous forward current which the
diode can pass at the normal temperature.
3. Forward Surge Current (IFS): It is defined as that large current which a diode can
safely take for a very short time (say, upto one” second).
4. Maximum Forward Voltage (VF): It is the maximum forward voltage that the diode
can have without burnout.
5. Forward Voltage (VF): It is the forward voltage of the diode at a given temperature
and for a specific value of forward current.
6. Reverse Current (IR) : It is the maximum reverse saturation current at the maximum
reverse voltage at a given temperature.
7. Reverse Recovery Time (trr): It is the maximum time taken by the device to switch
from ON to OFF state.
8. Power Dissipation (PD) : Power dissipation of the diode is the value of power that
 72 Basic Electronics
can be dissipated by the device under specified temperature and normal operation of
the device. The maximum value of power, which a diode can dissipate without failure
is called power rating.
The power dissipation for a forward biased diode is given by PD = Vf × JF
Similarly, power dissipation for a reverse biased diode is PD = VR × IR If the power
dissipation exceeds the power rating, the diode gets destroyed.
4.12 DIODE APPLICATIONS
1. Rectifiers (power diodes in dc power supplies).
2. Zener diode in voltage stabilizing circuits.
3. Varactor diodes in voltage and TV receivers.
4. A switch in logic circuits in computers.
5. Signal diodes in communication circuits.

SHORT QUESTIONS & ANSWERS

Q. 1. Why is silicon preferred over germanium in the manufacture of semiconductor devices ?
Ans. The silicon semiconductor devices have, in general, higher PIV and current ratings and
wider temperature range than germanium semiconductor devices and, therefore, silicon is
preferred over germanium in the manufacture of semiconductor devices.
Q. 2. What does the arrow head represent in a schematic symbol of a P-N junction ?
Ans. The arrow head in the schematic symbol of a P-N junction indicates the direction of
conventional current flow when the diode is forward biased.
Q. 3. What are the two mechanisms of breakdown in a P-N junction ?
Ans. Avalanche and Zener breakdowns.
Q. 4. Name the breakdown mechanism in a lightly doped P-N junction under reverse biased
condition.
Ans. Avalanche breakdown.
Q. 5. Name the breakdown mechanism in a heavily doped P-N junction under reverse biased
condition.
Ans. Zener breakdown.
Q. 6. What is an ideal diode ?
Ans. A two terminal device, called the diode, if acts as a perfect conductor (with zero resistance
or zero voltage drop across it) when forward biased and as perfect insulator (with an infinite
resistance or with no current through it) when reverse biased, is an ideal diode.
Q. 7. Is reverse saturation current of a junction diode independent of reverse bias voltage ?
Ans. Yes.
Q. 8. Germanium is more temperature dependent than silicon. Why ?
Ans. Because the reverse saturation current in case of a germanium diode is approximately 1,000
times larger.
 73

Q. 9. What is the effect of temperature on the reverse saturation current of a diode?

Ans. Reverse saturation current, theoretically, increases by 8 percent per °C for silicon and 11
per cent per “C for germanium. But from experimental data it is found that the reverse
saturation current increases 7 percent per °C for both silicon and germanium. This is because
a surface leakage current component of reverse saturation current is independent of
temperature. Since (1.07)10 ~ 2.0, the reverse saturation current approximately doubles for
every 10°C rise in temperature.
Q.10. Explain the effect of temperature on the V-I characteristics of the diode. :
Ans. Reverse saturation current IO and volt-equivalent of temperature VT increase with the increase
in temperature. I0 doubles for every 10°C rise in temperature. This causes lowering of
threshold or cut-in voltages. With the increase in temperature, forward characteristic become
more ideal. In reverse-bias, the breakdown voltage increases with the increase in temperature.
Q. 11. What is static resistance of diode?
Ans. DC or static resistance of a diode is the resistance offered by it to the direct current. It is
simply the ratio of the dc voltage applied across the diode to the direct current flowing
through it.
Q. 12. Define dynamic resistance of a P-N junction diode in forward biased condition.
Ans. The resistance offered by a P-N junction diode to the changing forward current is defined
as the dynamic resistance.
It may be given as
Small change in forward voltage
AC or dynamic resistance, r =
Small change in forward current
Q. 13. Define diffusion capacitance of a P-N junction diode.
Ans. When a P-N junction is forward biased, a capacitance which is much larger than the transition
capacitance, comes into play. This type of capacitance is called the diffusion capacitance
CD.
Q. 14. How does transition capacitance vary with junction voltage in a P-N junction diode ?
Ans. Transition capacitance is inversely proportional to the square root of the junction voltage.
Q.15. How does diffusion capacitance vary with diode forward current ?
Ans. In a P-N junction diode, the diffusion capacitance is directly proportional to the diode
forward current.
Q.16. Define breakdown voltage.
Ans. The voltage where the magnitude of diode current takes a sharp turn and increases rapidly
on a small increase of reverse voltage magnitude, is known as breakdown voltage.
Q. 17. What is a Zener diode ?
Ans. Zener diode is a P-N junction diode specially designed for operation in its breakdown
region.
Q. 18. What is Zener voltage ?
Ans. The voltage at which the Zener diode breaks down is called the Zener voltage.
 74 Basic Electronics
Q.19. What happens to the series current, load current and Zener current when the dc input
voltage of a Zener regulator increases ?
Ans. Zener current and series current increase while the load current remains unchanged.
Q.20. Why is Zener diode used as voltage regulator?
Ans. Zener diode has the property of behaving like a dc battery in ‘on’ state (i.e. when the
voltage across Zener diode exceeds its Zener voltage rating V z). In ‘on state’, the voltage
across Zener diode remains constant until the voltage across it drops less than V z. This
property of Zener diode makes its use as voltage regulator.
Q.21. Explain how Zener diode maintains constant voltage across the load ?
Ans. Zener diode has the property of behaving like a dc battery in ‘on’ state. If the Zener diode
is shunted across the load RL and the voltage across Zener diode is more than Zener voltage
Vz then Zener diode is in ‘on’ state, and any variation in voltage across the zener diode due
to variations either in supply voltage or in load resistance is not able to change the output
voltage. Thus Zener diode maintains voltage constant across the load.

EXERCISE
1. For a silicon diode at a working temperature of 25° C, the forward voltage applied across
the diode is 0.5 V. Determine its forward current if the reverse saturation current is 10 nA.
[Ans. 0.169 mA]
2. Find the value of p-n junction diode current in the forward bias condition, when the applied
voltage across it is 0.05 V and I0 = 50 µA. Given e/kT - 40/V. [Ans: 0.319 µA]
3. A certain diode has reverse saturation current of 15 µA at 25°C for a reverse voltage of 20
V. Calculate its reverse resistance. [Ans: 4 MΩ]
4. Calculate the dynamic resistance of an ideal p-n junction diode at 17° C, when a current of
1 mA flows through the diode. Given I0 = 5 µA. [Ans : 25 Ω]
5. A germanium p-n junction diode has reverse saturation current of 4µA at 25° C. If a sine
wave having peak value of 0.15 V is applied across the junction, what is the rectification
i.e., ratio of forward to reverse peak currents. [Ans: 330]
6. A silicon diode has a saturation current of 0.01 µA at room temperature 300 K. Find the
saturation current at 400 K. [Ans: 10.24 µA]
7. For what voltage will the reverse current in a p-n junction germanium diode attain a value
of 90% of its saturation value at room temperature ? [Ans: 0.06 V]
8. When forward biased in a particular circuit, a diode has a current of 50 mA, when reverse
biased, the current drops to 20 nA. What is the ratio of forward to reverse current ?
[Ans: 2.6 × 106]
9. A diode has maximum power dissipation of 0.5 W. (a) What is the maximum dc current
allowed in the forward direction, if we allow and approximate forward voltage drop of one
volt ? (b) What is the approximate breakdown current that burns out the diode, if it has a
breakdown voltage of 150 V ? [Ans: 0.5 A, 3.33 mA]
 75

10. The current voltage characteristic of a p-n junction diode is given by the relation, I = I0
[eVF/ηkT – 1] The diode current is 0.5 mA at VF = 340 mV and 15 mA at VF = 440 mV.
Calculate η. Assume kT/e = 25 mV. [Ans : 1.18]
11. (a) Determine the applied voltage to achieve a forward current of 0.45 µA in a p-n junction
silicon diode at T = 330 K, if the reverse saturation current is 1.0 nA. (b) If the reverse
saturation current in a germanium diode is 10 µA, what current would result if the voltage
in part (a) is applied in the forward direction ? [Ans: 0.3 V and 1.63 mA]
12. The reverse saturation current of a silicon diode is 5 µ A at room at room temperature. Find
the diode current [Ans : (i) 1.287 mA (ii) 30.265 mA]
(i) 40° C and a forward voltage of 0.3 V.
(ii) 60° C and a forward voltage of 0.5 V.

ppp
76 Basic Electronics

Application of Diode CHAPTER

5.1. INTRODUCTION
The electrical power is almost exclusively generated, transmitted and distributed
in the form of ac because of economical consideration but for operation of most of the
electronic devices and circuits, dc supply is required. Dry cells and batteries can be used
for this purpose. No doubt, they have the advantages of being portable and ripple free but
their voltages are low, they need frequent replacement and are expensive in comparison to
conventional dc power supplies. Now-a-days, almost all electronic equipment include a
circuit that converts ac supply into dc supply. The part of equipment that converts ac into
dc is called the dc power supply. In general, at the input of the power supply, there is a
power transformer. It is followed by a rectifier (a diode circuit), a smoothing filter and
then by a voltage regulator circuit. A block diagram of such a power supply is given in fig.
5.1.

VOLTAGE
TRANSFORMER RECTIFIER FILTER REGULATOR

REGULATED DC
AC INPUT SIGNAL OUTPUT VOLTAGE
Fig. 5.1 : Block Diagram of a DC Power Supply
As obvious from the block diagram shown in fig. 5.1, the basic power supply is
constituted by four elements viz a transformer, a rectifier, a filter, and a regulator put
together. The output of the dc power supply is used to provide a constant dc voltage across
the load. Let us briefly outline the function of each of the elements of the dc power supply.
Transformer is used to step-up or step-down (usually to step-down) the supply voltage
as per need of the solid-state electronic devices and circuits to be supplied by the dc
power supply. It can provide isolation from the supply line-an important safety
consideration. It may also include internal shielding to prevent unwanted electrical noise
signal on the power line from getting into the power supply and possibly disturbing the
load.
 77

Rectifier is a device which converts the sinusoidal ac voltage into either positive or
negative pulsating dc. p-n junction diode, which conducts when forward biased and
practically does not conduct when reverse biased, can be used for rectification i.e. for
conversion of ac into dc. The rectifier typically needs one, two or four diodes. Rectifiers
may be either half-wave or full-wave (centre-tap or bridge) type.
The output voltage from a rectifier circuit has a pulsating character i.e., it contains
unwanted ac components (components of supply frequency / and its harmonics) along
with dc component. For most supply purposes, constant direct voltage is required than
that furnished by a rectifier. To reduce ac components from the rectifier output voltage a
filter circuit is required. Thus filter is a device which passes dc component to the load and
blocks ac components of the rectifier output. Filter is typically constructed from reactive
circuit elements such as capacitors and/or inductors and resistors.
The magnitude of output dc voltage may vary with the variation of either the input
ac voltage or the magnitude of load current. So at the output of a rectifier-filter combination
a voltage regulator is required, as shown in fig. 5.1, to provide an almost constant dc
voltage at the output of the regulator. The voltage regulator may be constructed from a
Zener diode, and/or discrete transistors, and/or integrated circuits (ICs). Its main function
is to maintain a constant dc output voltage. However, it also rejects any ac ripple voltage
that is not removed by the filter. The regulator may also include protective devices such as
short-circuit protection, current limiting, thermal shutdown, or over-voltage protection.
5.2 RECTIFIER
Ø It is an electronic circuit that converts ac to pulsating dc or variable dc or it converts
the bi-directional current to unindirectional current.
The pure dc can be obtained by filtering it.
Ø There are two types of rectifier :-
I) Half wave Rectifier (HWR)
II) Full wave Rectifier (FWR)
Ø Full wave rectifier is again of two types :-
a) Center - tapped full wave rectifier type.
b) Bridge type full wave rectifier type.
5.2.1 Half wave rectifier 1: 1 A
Ø It gives output for only one half + +
cycle of input Ideal
Ø It consists of a diode, a load diode
~ VS V0
resistor & source signal is given RL
by a transformer of turn ratio 1:1.
–
Ø During +ve half cycle or input, –
end A is +ve & end B is –ve. So the B Fig. 5.2
diode is forward biased or “ON’. So
current will flow and output is obtained. During –ve half cycle, end A is –ve & end B is
+ve. So diode will reverse bias i.e. ‘Off’. So no current will flow ⇒ no O/P will be obtained.
78 Basic Electronics

Vm
(input source signal)

0
T/2 T
–Vm
Vm

(output when diode is Ideal)

0
T/2 T

Vm–VT

(output when diode is not ideal)

VT VT VT
Fig. 5.3
Analysis
Ø Vavg or Vdc

z
T
I
Vavg = V0dt
T0

LM V OP
MN z z
T/ 2 T
I
= sin wt dt +
T 0
m
T/ 2
0
PQ
−Vm
=
T/ 2
cos wt 0
wT
− Vm
= cos π − cos 0
2π
− Vm
= −1 − 1
2π

Vm
⇒ Vavg or Vdc =
π
 79

Im
Similarly Iavg or Idc =
π
Ø Vrms or Vac

z z
T T/ 2
I I
Vrms = V02 dt = Vm2 sin 2 wt dt
T0 T 0

zb
T/ 2
=
Vm2
2T
1 − cos 2 wt dt g
0

Vm2 V
⇒ ⇒ Vrms or Vac = m
4 2

Im
Similarly I rms or I ac =
2
Ø Form Factor (F)
It is the ratio of rms value of output voltage or output current to the average value
of output voltage or output current respectively.
Vrms I
F= or rms
Vavg I avg

Vm / 2
For HWR, F =
Vm / π
⇒ F = 1.57
Ø Ripples
It is the ac components present in rectifier output.
Ø Ripple Frequency
It is the frequency of the ripples present in rectifier output.
I
If fs = source signal freq. = .
T
fr = ripple freq.
I
In HWR, fr = .
T
⇒ fr = f s
Ø Ripple factor (r.f)
It is the ratio of rms value of ac component to the average or dc value of rectifier
output.
80 Basic Electronics

r.f. =
bV grms
r

Vavg

2
Vrms − Vavg
2
=
Vavg

FV I 2

= GH V JK rms

avg
−1

⇒ r. f = F 2 − 1

For HWR, r.f. = . 2 − 1 = 121

157 .
Ø Efficiency (η)
It is the ratio of dc power output to the ac power input.
Pdc
η=
Pac

I 2avg . R L
=
b
I 2rms R L + rf g rf → forward biasing resistance.

I RL
=
F R L + rf
2

1 1
η=
⇒ F2 FG1 + r IJ
H RK
f

0.406 40.6%
For HWR, η =
FG1 + r IJ = FG1 + r IJ
H RK H RK
f f

L L

⇒ ηmax = 40.6%
– PIV +
Ø PIV rating
Applying KVL, –

− Vm + PIV = 0
Vm RL
⇒ PIV = Vm
So rating is PIV ≥ Vm + Fig. 5.4
 81

5.2.2 Full-wave Rectifier

It is the rectifier that gives output for both half cycles of input.
(a) Full-wave (center tapped) Rectifier
1:2 A ( ––) - in +ve 1/2
D1 cycle

B – V0 + (----) - in -ve 1/2

~ Vs
cycle.
RL
D2
C Fig. 5.5

Ø It consists of two diodes, a load

resistor and the source signal is Vm
given with the help of (input)
transformer of turn ratio 1 : 2.
Ø The transformer generates twice
0
of input but is equally divided T/2 T t
& given to the diodes because
of center-tapping.
Ø During +ve half cycle of input,
Vm (output)
diode D1 is ‘ON’ & diode D2 is
‘OFF’. So output is obtained. D1 D2 D1
Ø During –ve half cycle of input,
diode D1 is ‘Off’ & diode D2 is 0 T/2 T t
‘ON’. So output is also obtained.
Fig. 5.6
(b) Full wave (Bridge) rectifier

1:1
D1 D 1 (––) - in +ve 1/2
cycle
– V0 +
~ Vs
RL (----) - in –ve
1/2 cycle
D3 D2
Fig. 5.7
82 Basic Electronics
Ø It consists of four diodes which increases cost but it overcomes the difficulty of
finding center point of transformer.
Ø During +ve half cycle, D1 & D3 are ‘ON’ while D2 & D4 are off. So output is obtained
across RL.
Ø During –ve half cycle, D2 & D4 are ON while D1 & D3 are off. So output is obtained
across RL.

[Time period = T] ⇔

(input)
0
T/2 T

[Time period = T/2] ⇔

D1,D3 D2,D4 D1, D3
(output)
0 T/2 T
Fig. 5.8

Analysis of FWR

Ø Vavg or Vdc

z
T/ 2
1 2 Vm
Vavg = Vm sin wt dt =
T2 0
π

2 Vm
⇒ Vavg =
π

2I m
Similarly I avg or I dc =
π
Ø Vrms or Vac

z
T/2
1
Vrms = Vm2 sin 2 wt dt
T 2 0

Vm2
=
2
 83

Vm
⇒ Vrms or Vac =
2
Im
Similarly I rms or I ac =
2
Ø Form Factor
Vrms
F= V
avg

For FWR,
Vm / 2
F=
2 Vm / π
⇒ F = 1.11
Ø Ripple frequency
1 1
fr = = 2.
T/2 T
⇒ fr = 2fs

Ø Ripple factor
r.f. = F2 − 1
For FWR,
. 2 −1
r.f. = 111
⇒ r.f = 0.48
Ø Efficiency
1 1
η= 2
F 1 + rf
RL

0.812
For FWR, η = r
1+ f
RL

81.2%
⇒ η=
r
1+ f
RL
η max = 81.2%
 84 Basic Electronics
Ø PIV
In center - tapped, it is PIV > 2Vm
In Bridge type, it is PIV > Vm
5.2.3 Comparison of different typesof rectifiers
Factors HWR Center-tapped Bridge type
FWR FWR

Vm 2Vm 2Vm
Vavg
π π π
Vm Vm Vm
Vrms
2 2 2
F 1.57 1.11 1.11
r.f 1.21 0.48 0.48
fr fs 2fs 2fs
η max 40.6% 81.2% 81.2%
PIV > Vm > 2Vm > Vm

Example 5.1 :
A half-wave rectifier uses a diode with an equivalent forward resistance of 0.3Ω . If
the input ac voltage is 10 V (rms) and the load is a resistance of 2.0Ω, calculate Idc
and Irms in the load.
Solution : Supply voltage, VSrms = 10V
Peak value of supply voltage, VSmax = 10 2 V
Forward resistance, RF = 0.3Ω
Load resistance, RL = 2Ω

VS max 10 2
Peak value of current in load, I max = = = 6.15 A
R L + R F 2 + 0.3

I max 615
.
DC output current, I dc = = = 1.958 A Ans.
π π

RMS value of output current, I rms = I max = 615

.
= 3.075 A Ans.
2 2
Example 5.2 :
An a.c. supply of 230 V is applied to a half-wave rectifier circuit through a
transformer of turn ratio 10 : 1. Determine
 85

(i) Im, Idc and Irms (ii) d.c. power output

(iii) a.c. power input (iv) efficiency of rectification
(v) d.c. output voltage (vi) peak inverse voltage.
Assume the crystal diode has a forward resistance of 20 ohm and the load resistance is 1
k ohm.
Solution : The circuit is shown in the Figure below.

R.M.S. value of the voltage applied to the rectifier cricuit,

N2 1  N1 10 
V= × V1 = × 230 Q turn ratio = 
N1 10  N2 1 
= 23 V
Maximum value of the voltage applied to the rectifier circuit.
Vm = 2V = 2 × 23 = 32.53 V
Vm 32.53
(i) ∴ Im = = = 31.89 ma (Ans)
rf + R L 20 + 1000

I m 31.89
Idc = Iav = = = 10.15 mA (Ans)
π π
i m 31.89
I rms = = = 15.94 mA (Ans)
2 2
(ii) d.c. power output, Pdc = I2dc R L = (10.15 × 10−3 ) 2 × 1× 103 = 103.02 mW (Ans)
(iii) a.c. power input, Pac = Irms
2
(rf + R L ) = (15.94 × 10−3 )2 (20 + 1000)
= 259.16 mW (Ans)
Pdc 103.02
(iv) rectification efficiency, η = × 100 = × 100 = 39.75% (Ans)
Pac 259.16
(v) d.c. output voltage, Vdc = Idc × R L = 10.15 × 10−3 × 1000 = 10.15V (Ans)
(vi) Peak inverse voltage i.e. voltage coming across the crystal diode under revese biasing :
PIV = Vm = 32.53 V (Ans)
 86 Basic Electronics
Example 5.3 :
The load resistance of a centre-tapped full-wave rectifier is 500Ω and the necessary
V voltage (end to end) is 60 sin (100 πt). Calculate (i) peak, average and rms values of
current; (ii) ripple factor and (iii) efficiency of the rectifier. Each diode has an idealised
I-V characteristics having slope corresponding to a resistance of 50Ω.
Solution: Maximum value of supply voltage, VSmax = 60 V
Forward resistance, RF = 50Ω
Load resistance, RL = 500Ω
VS max 60
(i) Peak current, I max = = = 0109
. A Ans.
R L + R F 500 + 50

2I max 2 × 0109
.
Average current, Idc = = = 0.0695 A Ans.
π π
I max 0.109
RMS value of current, I rms = = = 0.077 A Ans.
2 2

(ii) Ripple factor, r =

FG I IJ 2

−1 =
FG 0.077 IJ 2

HI K H 0.0695K − 1 = 0.482
rms
Ans.
dc

0.812 0.812 × 100

(iii) Efficiency of rectifier η = × 100 = = 7382%
. Ans.
RF 50
1+ 1+
RL 500
Example 5.4 :
A centre-tapped transformer has a 220 V primary winding and a secondary winding
i rated at 12-0-12 V and is used in a full-wave rectifier circuit with a load of 100 Ω.
What is the i dc output voltage, dc load current and the PIV rating required for
diodes ?
Solution : Peak value of supply voltage, VS max = 12 2V
Load resistance, RL = 100Ω
2 2 VS max 2 12 2
DC load current, I dc = I max = = × = 108 mA
π π RL π 100

DC output voltage, Vdc = I dc R L = 108 × 10 −3 × 100 = 10.8 V Ans.

PIV rating of diodes = 2 VS max = 2 × 12 2 = 33.94 V Ans.
 87

5.3 CLIPPER
Ø It is the diode circuit that clips off or cuts away some portion of the input without
distorting the rest part of input.
Ø The clipper is of two categories : Series & parallel, depending on diode cofiguration.
If the diode is series with the load then it is series cliper.
If the diode is connected parallel with the load i.e. output is taken across diode then
it is parallel clipper.
Ø The clipper is of three types depending on the output wave form,
→ +ve clipper
→ –ve clipper
→ combined clipper
If some portion from +ve peak is clipped off hen it is +ve clipper i.e in simple, there is
absence of +ve peak.
If some portion from –ve peak is clipped off then it is –ve clipper i.e here –ve peak is
absent.
If both +ve & –ve peaks are absent, then it is combined clipper.
Combined clipping is possible in parallel clipper only.
5.3.1 Steps for solving clipper problem
i) First replace the diode by its equivalent model & do the necessary configuation.
ii) The find the condition for forward biaging / ‘ON’ and Reverse baising / ‘Off’ of the
diode.
iii) Then find the output for ‘ON’ & ‘OFF’ state of diode.
iv) Then plot the output wave form.
Examples 5.5
Vi
–20V
+ +
5V Si
0
V2 Vi 2KΩ V0
t
– –
–20V
Find output wave form
Solution :
A
+ 5V 0.7 Ideal +
Vi 2KΩ V0

– –
88 Basic Electronics
Applying KVL, upto the point ‘A’,
VA = Vi + 5 − 0.7
= Vi + 4.3
Condition for forward biasing of diote
VA ≥ 0
⇒ Vi + 4.3 ≥ 0 ⇒ Vi ≥ − 4.3V
O/P, when diode is forward biased / ON
+ 5 0.7 +
Vi + 5 − 0.7 − V0 = 0
Vi V0
⇒ V0 = Vi + 4.3, So when
Vi = 20V, V0 = 25.3V – –
O/P when diode is Reverse biased / Off
Here I = 0 ⇒ V0 = 0

Vi 20

t
–4.3
off
–2d
This is –ve clipper of series type V0
24.3

4.3
t
Ans
Example 5.6

Vi 10
Vi V0
Si 3V
R
t

–10
Draw output waveform.
 89

Solution :
Applying KVL upto the point ‘A’,
A V0
Vi
VA = Vi + 3 + 0.7 = Vi + 3.7 0.7V
3V Ideal
Condition for forward bias of diode
R
VA = Vi + 3 + 0.7 = Vi + 3.7 , VA < 0
⇒ Vi < 3.7
V0 , when diode is ON-
applying KVL,
+ 3V 0.7 +
− Vi + V0 − 0.7 − 3 = 0
⇒ V0 = Vi +3.7, so Vi V0
when Vi = –10V, V0 = – 6.3V
V0 , when diode is OFF-
– –
I=0
⇒ V0 = 0 Vi 10

-3.7 t
ON

This is + ve clipper of series type –1

ON

Example 5.7 –6.3V Ans

Vi 8V

+ +
2.2KΩ
t Ge
V0
3.3V
–8V – –

Draw the output wave form

90 Basic Electronics
Solution
+ 2.2KΩ +
Applying KVL up to point ‘A’, Ideas
A
0.3V
VA − Vi − 3.3 − 0.3 Vi V0
= – Vi – 3 3.3V
– –

Condition for forward bias / ON -

VA < 0 ⇒ – Vi – 3 < 0 +
⇒ Vi > –3 2.2KΩ +

V0 , when diode is ON : Vi 0.3V V0

V0 = 0.3 − 3.3 = −3V 3.3V
– –

I=0

+ 2.2K +

V0, when diode is OFF : Vi 0.3V V0

V0 = Vi – 3.3V
–

Vi 10

This is –ve clipper of parallel type

Off t
-3V

-10
V0

-3V A

-10v Ans
 91

Example 5.8
Vi 10k
10
+ +
IR Si
Si
Vi V0
t
5.3V 6.3V
– –
-10
Sketch V0 & IR

Solution :
10k
+
IR D1 Ideal D Ideal
2
A B
0.7V
Vi 0.7V V0

5.3V 6.3V
–

VA = –Vi + 6
VB = –Vi –7
Condition for D1 to be ON → –Vi + 6 < 0 ⇒ Vi > 6V
Condition for D2 to be ON → –Vi – 7 > 0 ⇒ Vi > –7V

V0 IR
Vi − 6
When D1 ON, 6V , So when Vi = 10, iR = 0.4 mA
10KΩ
D2 Off
Vi + 7
When D2 ON, –7V , So when Vi = –10, iR = – 0.3 mA
10KΩ
D1 Off

When D1 & D2 Vi 0
are Off
 92 Basic Electronics

Vi
10

6
D1
ON t
D 2ON
This is a case of combined -7
clipper 10

V0
6
t

-7

iR
In(mA)
0.4
t
-0.3
Ans
5.4 CLAMPER
Ø It is a diode network that clamps / holds the input signal and shifts it to a different dc
level.
Ø This network must have a diode, capacitor & resistor.
Ø The magnitude of R & C are so choosen that the time constant τ = RC should be large
enough to ensure that the voltage across capacitor does not discharge significantly
during the interval, diode is non-conducting.
5.4.1 Steps for solving clamper problem
Ø The analysis is started regarding in which cycle, the capacitor will charge.
The capacitor will charge, when diode will ‘ON’ & the capacitor will discharge when
diode will “Off”.
Ø Considering the charging time is very fast, the output and the voltage across capacitor
is determined in that half cycle where diode is “ON”.
Ø Then in next half cycle i.e diode is “OFF”, the output is obtained.
Ø The capacitor will have the polarity during charging and keep it though out discharging.
Ø Note down that the total output swing should be equal to total input swing.
 93

Examples 5.9
Vi
20 + +
C
Ideal
t Vi R V0
-10 5V
– –

Sketch V0 for this network

Solution :
The capacitor will charge during ‘ON’ state of diode i.e. in –ve half cycle of input.
And capacitor will discharge through resistor in +ve half cycle of input.
V
During –ve half cycle of i/p - – C +
– +
Here V0 = –5V
And applying KVL,
10 R V0
10 – 5 – VC = 0 ⇒ VC = 5V
5V
+ IR=0 –

VC
– +
+ +

During +ve half cycle of i/p - 20 V0

R
– –

Now by applying KVL,

Vi(Volt)
20 + VC – V0 = 0 20
⇒ V0 = 20 + VC
t (Sec)
= 25V
–10

25
V0
(Volt)
t (Sec)
Ans
– 5V
 94 Basic Electronics
Example 5.10
Vi
50V
+ C +
Si
t Vi R V0
19.3V
– –
-50V

Sketch the output wave form

Solution :
+ +
VA = − Vi + 20V
Diode will ON, A
Vi R V0
If VA < 0 0.7
1 19.3V
⇒ Vi ≥ 20 i.e in +ve . – –
2
When Vi = +50V i.e. Vi max VC
+ –
Here diode is on & capacitor is fully charged + +
By applying KVL,
50 R V0
50 − VC − 20 = 0 0.7
⇒ VC max = 30V – 19.3
–
& V0 max = 20V
VC
+ –
When Vi = 0V +
+
Here diode is off
Here By applying KVL,
OV
0.7 R V0
V0 = –30V
19.3
– –

When Vi = – 50 V i.e. Vi min + VC –

Here also diode is Off – +

50 0.7 R V0
By applying KVL,
50 + V0 + 30 = 0 19.3
+ –
⇒ V0 = – 80V
 95

Vi

50
V0

20
t
-30
-80

Ans
5.5 EXAMPLES OF SERIES & PARALLEL CONFIGURATION OF DIODE
Example - 5.11
Find VD, VR & ID
Si
+

3V R-1.2
Soluiton : By applying KVL, VR
3 –0.7 – VR + 2 = 0 ID –
⇒ VR = 4.3 V
2V
VD = 0.7 V

VR 4.3
ID = = mA ≅ 3583
. mA Ans
R 12.
Example - 5.12
Si +
Find VD, VR, ID.
1.2KΩ
VR
0.5V

ID –
Solution :
The Si diode will forward bias if supply is more than or equal to 0.7V.
Now Si diode will be off.
So ID = 0, VD = 0.5V, VR = IDR = 0 Ans
 96 Basic Electronics

Si +V D2
Example- 5.13 12V V0
Find ID, V0 & VD 2 . ID D1 D2

5.6KΩ

Off
Solution : Here D1 is ON but D2 is Off.
So ID = 0
⇒ V0 = ID × 5.6 = 0

As there is no current so there is no voltage drop across D1, So V D 2 = 1 2 V Ans

Example- 5.14

Find I1 , I D1 , I D 2 & V0 I1
0.33KΩ I D1 I D2 +

10V Si V0
–

Solution : Both the diodes are forward biased.

So V0 = 0.7
And the voltage across resistor is 10 – 0.7 = 9.3V
9.3
So I1 = = 2818
. mA
0.33
Now as both parallel diodes is of same material, current will be equally divided.
I1
So I D1 = I D2 = = 14.09 mA Ans
2

Example- 5.15 Find I1, I2 ?

20V
Si
10Ω
I2 I1
20Ω
 97

Solution : The diode is forward biased.

20 − 0.7 0.7 20V

I1 = = 0.965 mA
20 I1

I2 =
20
= 2A 10Ω I 2 20Ω
10
Ans

Example- 5.16 Determine V01 & V02 +12V V 01 4.7KΩ V 02

Si
Ge
Solution : Both diodies will forward bias.
Applying KVL, 12 – 0.7 – 4.7I – 0.3 = 0 I
11
⇒ I= = 2.34 mA
4.7
V02 = 0.3 V
V01 = 4.7 × I + 0.3
= 11.3 V
1.2KΩ
Example 5.17 V 02
–10V
+
Find V01 & V02 Ge Si V 01– –
3.3KΩ
I +
Solution : 10 – 3.3I – 1.2I – 0.7 – 0.3 = 0
9
⇒ 4.5I = 9 ⇒ I = mA = 2 mA
4.5
V02 = – 3.3 × I = – 6.6 V
V01 = – (1.2I + 3.3I) = – 4.5 × I = –9V 15V

Example- 5.18 Find V0. Si

Si Ge

V0
1KΩ

2V
 98 Basic Electronics
Solution : 15V
Out of si & Ge diodes connected parallel,
Ge diode will be ON as the thresold voltage 0.7V
of Ge is less.
0.3V
Applying KVL,
15 – 0.7 – 0.3 – I × 1 + 2 = 0 V0
⇒ I = 16 mA I 1K
So V0 = I × 1 + 2
= 18V 2V

2KΩ
Si
Example- 5.19 Find V0 V0
10V ID

Si 2KΩ 2KΩ
Solution : Both diodes will forward bias.
Applying KVL in indicated loop,
10 – 0.7 – 2ID – 2 × 2ID = 0
9.3
⇒ 6I D = 9.3 ⇒ ID = mA
6
9.3
V0 = 2 × 2I D = 4 × = 6.2 Volt
6

SHORT QUESTIONS & ANSWERS

Q. 1. What is a dc power supply ?
Ans. The part of the equipment that converts ac into dc is called the dc power supply.
Q.2. What is a rectifier?
Ans. A rectifier is a device which converts alternating current (or voltage) into unidirectional
current (or voltage).
Q. 3. What is PIV of a diode in a rectifier circuit ? Ans. Peak inverse voltage (PIV) is the
maximum possible voltage that occurs across a diode when it is reverse biased.
Q. 4. What is the importance of peak inverse voltage ?
Ans. If the applied voltage in reverse biased condition exceeds peak inverse voltage (PIV) rating
of the diode, then the diode may get damaged.
 99

Q. 5. Why half-wave rectifiers are generally not used in dc power supply?

Ans. The type of supply available from half-wave rectifier is not satisfactory for general power
supply. That is why it is generally not used in dc power supply.
Q. 6. What is PIV of the diodes employed in a bridge rectifier ?
Ans. PIV of the diodes in a bridge rectifier is equal to the maximum value of transformer
secondary i.e. PIV = Vmax.
Q. 7. What is PIV in case of half-wave, full-wave rectifier (using centre-tapped transformer)
and bridge rectifier ?
Ans. For half-wave rectifier, PIV = Vmax, maximum voltage across the secondary.
For centre-tapped rectifier, PIV = 2 Vmax
For bridge rectifier, PIV = Vmax
Q.8. Why diodes are not operated in the breakdown region in rectifiers?
Ans. In breakdown region, a diode has a risk of getting damaged or burnt because the magnitude
of current flowing through it increases in an uncontrollable manner. That is why diodes are
not operated in the breakdown region in rectifiers.
Q.9. Define ripple as referred to in a rectifier circuit.
Ans. The ac component contained in the pulsating output of a rectifier is known as ripple.
Q.10. What is the value of ripple factor for half-wave and full-wave rectifiers ?
Ans. For half- wave rectifier, y = 1.21
For full-wave rectifier, y = 0.482
Q.11. What is transformer utilisation factor?
Ans. Transformer utilisation factor is defined as the ratio of power delivered to the load and ac
rating of secondary of supply power transformer.
Q.12. What is the difference between clipping circuits and clamping circuits?
Ans. The clipping circuit removes some portion of an input signal whereas the clamping circuit
places either the positive or negative peak of a signal at a desired level.
Q.13. A clamper circuit sometimes uses a dc battery in addition to a diode, a capacitor and a
resistor, why ?
Ans. A clamper circuit uses sometimes a dc battery in addition to a diode, a capacitor and a
resistor to cause an additional shift of voltage level.
Q.14. How does a clamper circuit affect the peak-to-peak and rms values of a waveform ?
Ans. No change.
Q.15. How does a clamper circuit affect the peak and average values of the waveform ?
Ans. The peak and average values of a waveform are changed by a clamper circuit.
Q.16. What do you understand by (i) depletion region (ii) potential barrier.
Ans : Depletion region is the region around the junction that is depleted of movable carriers and
only consisting of un-movable ions.
These accumlated ions on eitherside of the junctions acts like a barrier to the flow of
majority carriers by creating a potential difference across the junction. It is known as
potential barrier.
100 Basic Electronics

EXERCISE
1. The rms ripple voltage is 20 mV for a 15 V dc output. Calculate the ripple factor, in percent.
[Ans: 0.13%]
2. The dc output voltage is 40 V at full-load and 41 V without any load. Calculate the load
LMH int: V. R.= V − V OP
NL FL
regulation factor in percent.
N V Q
FL
[Ans : 2.4%]

3. A half-wave rectifier is used to supply 20 V dc to a resistance load of 400 Ω. The forward

resistance of the diode is 20 Ω. Calculate the ac voltage required. [Ans : 65.94 V]
4. A half-wave rectifier uses a transformer of turn ratio 4:1. If the primary voltage is 240 V,
find (a) the dc output voltage (b) the peak inverse voltage. Assume the diode to be ideal.
[Ans: (a) 27V, (b) 84.84 V]
5. Determine the rating of a transformer in order to supply 10 W of dc power to a load for the
following circuits : (a) Half-wave rectifier, (b) Full-wave rectifier and (c) Bridge rectifier.
[Ans : (a) 34.84 VA, (b) 14.43 VA, (c) 12.32 VA]
6. (a) What is the necessary ac input power from the transformer secondary used in a half-
wave rectifier to deliver 500 W of dc power to the load? (b) What would be the ac input
power for the same load in the case of a full-wave rectifier ?[Ans : (a) 1232 W, (b) 616 W]
7. Calculate the maximum dc voltage available from a half-wave rectifier which uses a
transformer of turns ratio 20:1. The primary voltage is 220 V, 50 Hz and load resistor value
is 1 kΩ. [Ans : 4.95 V, 4.95 mA]
8. A half-wave rectifier uses a transformer of turn ratio 2:1. The load resistance is 500 Ω. If
the primary voltage is 240 V, 50 Hz, calculate (a) peak inverse voltage and (b) dc output
voltage. [Ans : (a) 54 V (b) 170 V]
9. A single-phase half-wave rectifier supplies power to a 1 kΩ load. The input supply voltage
is 200 Vrms. Neglecting forward resistance of the diode, calculate (a) V dc (b) Idc (c) ripple
rms voltage. [Ans : (a) 90 V (b) 90 mA and (c) 1.09 V]
10. A full-wave rectifier supplies a load of 10 kΩ. The ac voltage applied to the diode is 300-0-
300 Vrms. If the diode resistance is neglected, calculate (a) V dc (b) Idc (c) ripple voltage.
[Ans : (a) 270 V, (b) 27 mA, (c) 130.1 V]
11. Two semiconductor diodes used in a full-wave rectifier circuit have forward resistances
which will be considered constant at 1.0 Ω and infinite reverse resistances. The circuit is
supplied from a 300-0-300 Vrms secondary winding of a transformer and the mean current in
the resistive load is 10 A. Determine the resistance of the load, the maximum value of the
voltage which appears across the diodes in reverse bias and the efficiency of the circuit.
[Ans : 26 Ω, 833 V, 0.78]
 101

12. A full-wave rectifier circuit has a 2 kΩ resistive load. The characteristics of the diodes used
can be considered ideal and each half of the secondary winding of the transformer develops
an output voltage of 250 V. If the mean current in the load is to be limited to 100 mA by the
connection of equal resistors in series with the diodes determine the value of the these
resistors and the power dissipated in them. [Ans : 250 Ω and 1.54 W]
13. The four semiconductor diodes used in a bridge rectifier circuit have forward resistances
which can be considered constant at 0.1 Ω and infinite reverse resistances. They supply a
mean current of 10 A to a resistive load from a sinusoidal varying alternating supply of 20
Vrms. Determine the resistance of the load and efficiency of the circuit.
[Ans : 1.6 Ω and 0.72]
14. A shunt regulator circuit is to be designed to maintain a constant load current of 400 mA
and voltage of 40 V. The input voltage is 90 ± 5 V. The Zener diode voltage is 40 V and its
dynamic resistance is 2.5 Ω. Find (a) the series resistance, and output resistance.
[Ans: (a) 102.1 Ω and (b) 244 Ω]
15. The Zener diode has Vz = 18 V, the voltage across the load stays at 18 V as long as Iz is
maintained between 200 mA to 2 A. Find the value of series resistance so that output
remains at 18 V while input voltage is free to vary between 22 V to 28 V.[Ans : 3.33 Ω]
16. The Zener diode in regulator circuit has a Zener voltage of 15 V and a power rating of 0.5
W. If Vi = 40 V, what is the minimum value of RS that prevents Zener diode from being
destroyed? [Ans : 751 Ω]
17. The source voltage changes from 40 to 60 V. If the Zener voltage is 25 V and Zener resistance
is 10 Ω, what is the change in load voltage? (Given RS = 4 kΩ). [Ans : 0.05 V]
18. In a regulator circuit, Vi = 30 V, RS = 240 Ω, Vz = 12 V and RL = 500 Ω. Calculate (a) the
load voltage (b) voltage drop across the series resistance and (c) current though the Zener
diode. [Ans : 12 V, 18 V and 0.051 A]
19. For a Zener shunt regulator if Vz = 10 V, Rs = 1 kΩ, RL = 2 kΩ, and the input voltage varies
from 22 to 40 V, find the maximum and minimum values of Zener current.
[Ans : 25 mA and 7 mA]
20. Design a Zener diode shunt regulator to supply a load of 0-100 mA at 15 V. The input dc
voltage varies from 20 to 30 V. Assume minimum Zener current is 10 mA for stable operation.
[Ans : Rs = 40 Ω, 0.5 W, Pz = 5.625 W]

ppp
102 Basic Electronics

Bipolar Junction Transistor (BJT) CHAPTER

6.1 INTRODUCTION
It is a solid state device whose operation depends upon the flow of electric charge
carriers within the solid.
It is the electronic device that transfers the input signal from one resistance circuit to
other resistance circuit. So it is called transfer resistor or transistor.
The transistors are the current device that may be current or voltage controlled.
The transistors can be used as amplifier or as switch.
There are mainly two types of transistor.
1) BJT (Bipolar Junction Transistor)
2) FET (Field Effect Transistor)
6.2 BJT (BIPOLAR JUNCTION TRANSISTOR)
It is the type of transistor where a p-type semiconductor is sandwiched between two
n-type semiconductor or a n-type is sandwiched between two p-type semiconductor.
It has two PN junctions.
It is named as bipolar as both majority and minority carriers take part in current flow.
It has three terminals :- emitter, base & collector.
Emitter-base junction is treated as i/p junction & collector-base junction is treated as
output junction.
Generally input junction is forward biased and output junction is reverse biased.
It is of two types n-p-n & p-n-p.
6.3 TRANSISTOR TERMINALS
Every transistor has three terminals called emitter, collector and base.
Emitter : The section on one side of the transistor that supplies a large number of “‘majority
carriers is called emitter. The emitter is always forward biased w.r.t. base so that it can
supply a large number of majority carriers to its junction with the base. The biasing of
emitter-base junction of npn transistor and pnp transistor is shown in Fig. 6.1 and 6.2
respectively. Since emitter is to supply or inject a large amount of majority carriers into
the base, it is heavily doped but moderate in size.
 103

Fig. 6.1 Biasing of npn transistor Fig. 6.2 Biasing of pnp transistor
Collector : The section on the other side of the transistor that collects the major portion of
the majority carriers supplied by the emitter is called collector. The collector-base junc-
tion is always reverse biased. Its main function is to remove majority carriers (or charges)
from its junction with base. The biasing of collector-base junction of npn transistor and
pnp transistor is shown in Fig. 6.1 and 6.2 respectively. The collector is moderately doped
but larger is size so that it can collect most of the majority carriers supplied by the emitter.
Base : The middle section which forms two/w junctions between emitter and collector is
called base. The base forms two circuits, one input circuit with emitter and the other
output circuit with collector. The base-emitter junction is forward biased, providing low
resistance for the emitter circuit. The base-collector junction is reversed biased, offering
high resistance path to the collector circuit. The base is lightly doped and very thin so that
it can pass on most of the majority carriers supplied by the emitter to the collector.
As per width, collector > emitter > Base.
As per doping, Emitter > Base > Collector
The collector is made large to dissipate much power. So collector and emitter are not
interchanged due to width difference. But if widths are made equal then they can be
interchanged.
The emitter base junction offers less resistance & collector base junction offers high
resistance. So forward bias supply is small and reverse bias supply is large.
6.4 BJT SYMBOLS

C(n) C(p)

B(p) B(n)

E(n) Fig. 6.3 E(p) Fig. 6.4

(n-p-n) (p-n-p)
Ø The arrow mark is given on the basis of direction of conventional current flow which
is opposite to electron flow & same as hole flow.
Ø Generally n-p-n transistors are widely used because electrons have greater mobility
than holes.
104 Basic Electronics
6.5 TRANSISTOR CURRENTS
The emitter supplies the majority carriers, giving rise emitter current, IE.
Few of majority carriers are neutralized in base region, giving base current, IB.
The rest are collected at collector region, giving rise to collector current IC.
So IE = IC + IB
But I C = I C maj + I C min
The minority collector current is due to reverse biasing between collector & base
junction. The minority current is also known as collector leakage current
So I C = I C maj + I CO .
6.6 IMPORTANT POINTS REGARDING WORKING OF TRANSISTORS
The worthnoting points regarding working of transistors are summarized below.
1. Current conduction in N-P-N transistor is by electrons and the conventional current
flow will be in the opposite direction. Current conduction in P-N-P transistor is by
holes but in external leads, the current will be by flow of electrons.
2. The collector current IC is always less than emitter current IE, being the difference of
emitter current IE and base current IB.
3. The base current is only a small fraction (usually 5%) of emitter current.
4. As a standard convention, all the currents entering into the transistor are considered
to be positive. Conversely currents that flow out of the transistor are taken to be
negative. It means that if the actual conventional current flows in the outward direction,
a negative sign is included along with its magnitude. Thus in an N-P-N transistor, the
emitter current IE is to be taken negative because it flows out of the transistor while
both the base current IB and collector current IC are to be taken a positive because
they flow into the transistor. Similarly in a P-N-P transistor IE is to be taken positive
and both base current IB and collector current Ic are to be taken negative. However, to
avoid confusion, the actual direction of flow of current is indicated in the diagrams.
5. Emitter-base junction is always forward-biased and collector-base junction is always
reverse-biased.
6. The input circuit (i.e. emitter-base junction), because of forward bias, offers low
resistance and so needs usually very small bias (approximately 0.7 V for Si and 0.3
V for Ge). The output circuit (i.e. collector-base junction), because of reverse bias,
offers high resistance and, therefore, needs much higher bias (3 to 20 V).
7. Transistor transfers the input signal from a low resistance circuit to a high resistance
circuit, therefore, it is called the TRANSFER RESISTOR (TRANS-ISTOR).
8. Since both of the charge carriers (holes as well as electrons) are involved in current
flow through a transistor (may be either P-N-P or N-P-N), so these devices are
sometimes called the bipolar junction transistors (BJTs).
 105

9. Although, it is said that a D1 D2

transistor is a device with two
PN diodes connected back-to- +
back, but it does not mean that –
VCB VEB
two discrete diodes connected
back-to-back, as shown in fig +
–
6.5, can work as a transistor. In
such a case, each diode has two Two Diodes Connected Back-To-Back
equally doped regions, so that
the overall circuit has four Fig-6.5

equally doped regions. This would not work as base region is not the same as in a transistor.
The key to the transistor action is the lightly doped thin base between the heavily
doped emitter and moderately doped collector.
In an N-P-N transistor, the free electrons passing through the base to the collector
region have a short life time. As long as the base is thin, the free electrons can reach the
collector. But in case of two discrete back-to-back connected diodes there are four doped
regions instead of three and there is nothing that resembles a thin base region between an
emitter and a collector. Hence two discrete diodes connected back-to-back can never
work as a transistor.
10. The choice of N-P-N transistor is made more often because majority charge carriers
are electrons whose mobility is much more than that of holes.
6.7 TRANSISTOR AS AN AMPLIFIER
Ø The input and output loops of E B C
transistor are completely isolated. n p n

Ø The input junction of transistor is Source

forward biased, there by offers very ~ V0
low impedance.
So for a given source voltage, the
current becomes more because of
low impedance.
E B C
Ø The output current is directly
proportional to input current. So it
increases accordingly to input V0
Source ~
current
Ø The output junction is reverse biased,
so offers high output impedance. Fig. 6.6
As output current & output resistance, both are high, the output voltage becomes very
high, so output voltage is more than input voltage, i.e. amplification occurs.
106 Basic Electronics
6.8 TRANSISTOR AS A SWITCH
The switching action of a
transistor can be explained with
the help of its output
characteristics. Fig. 6.7 shows
the output characteristics of a
typical transistor for a CE
configuration. The dc load line
for a given collector supply
voltage V C and collector
resistance RC is drawn on the
output chraceristics. The three
regions viz. cut-off region,
active region and saturation
region are clearly marked on
the output characteristics.
Fig. 6.7
When a the transistor is working as a switch, the cut-off (off) and saturation (on)
regions are the stable regions of its operation, while active region is the unstable (or
transient) region of its operation. The operation of transistor passes through the active
region when its condition is changed from one state to another (i.e. from off state to on
state or vice-versa). In fig 6.7 the DC is the active region. The collector current IC increases
from ICEO to IC(sat) along the path DC as the transistor is switched on. When the transistor is
switched off, IC decreases from IC(sat) to ICEO along path CD.
In the ‘off state’ of a transistor swtich, as discussed above, the collector current is
not absolutely zero but some leakage current (current due to minority carriers) does flow

(a) Transistor Switching Circuit (b) Load Line

Fig. 6.8
and as such the resitrance between its collector-emitter terminals is not infinite, though it is
very high. Similarly in the ‘on state’ of a transistor switch the voltage across its collector-
emitter terminals is not zero, though it is very small (less than 1 V) and as such the
 107

resistance between its collector-emitter terminals is not absolutely zero. Thus the transistor
does not behave as an ideal switch, but in other respects it is superior to switches of other
types, particularly from the point of view of operating speed. For high speed switching,
transistor is the only device.
6.9 EBERS-MOLL MODEL
The dependence of the currents in a transistor upon the junction voltages, or vice-versa
may be represented here.
i.e I C = −α n I E + I CO 1 − e C T
V /V

or I C = −α n I E − I CO e VC / VT − 1
Subscript n to a has been added in order to indicate the normal operation of the transistor.
Minus sign has been introduced with αn IE to take into account its direction.
With inverted mode of operation in mind, equation may be written as -

i.e. I E = −α i I C − I EO e VE / VT − 1
Here αi is the inverted common-base current gain, just as αn is the current gain in
normal operation. IEO is the emitter- junction reverse saturation current, and VE is the voltage
drop from P-side to N-side at the emitter junction and is positive for a forward-biased
emitter.
αiI C αnIE

IE IC
N N
C
E P P
(–IEO) (–ICO)
I’ N
IB
VE B VC
+ – – +
Ebers-Moll Model For a PNP Transistor
Fig - 6.9
Ebers-Moll model in terms of a circuit is given in fig. 6.9 for a P-N-P transistor. It
involves two ideal diodes placed back-to-back with reverse saturation currents – IEO and –
ICO and two dependent current-controlled current sources shunting the ideal diodes. This
model is valid for both forward-and reverse-biased static voltages applied across the
transistor junctions.
From fig. 6.9 it is evident that dependent current sources can be eliminated from the
figure provided an = ai = 0. For example by making the width of the base much larger than
the diffusion length of the minority carriers in the base, all the minority carriers will recombine
in the base and none will survive to reach the collector. In such a condition transport factor
β and hence also current gain factor a will be zero. Thus under these conditions, the
transistor action ceases, and we simply have two diodes placed back-to-back.
108 Basic Electronics
From the above discussion it is obvious that a transistor cannot be constructed by
simply connecting two separate (isolated) diodes back-to-back.
6.10 TRANSISTOR CONFIGURATION
Ø Transistor has three terminals. But we require four terminals - two for input & two
for output for connecting it in a two port network.
Ø So one of the terminals is made common to input as well as output of the circuit.
So there are three types of configurations
Common Base (CB)
Common Emitter (CE)
Common Collector (CC)
Ø Generally common end is grounded but not always.
6.11 CHARACTERISTICS OF TRANSISTOR CONFIGURATION
There are mainly two types of characteristics,
1) Input characteristics
2) Output characteristics
6.11.1 Input characteristics
This graph is plotted between input voltage and input current at constant output voltage.
Because input junction is forward biased, the input characteristics is similar to diode
forward bias characteristics.
This characteristics is used to determine input impedance of transistor.
6.11.2 Output characteristics
This graph is plotted between output voltage and output current at constant input current.
Because output junction is reverse biased, so the curve is analogue to diode reverse bias
characteristic.
There are three regions of transistor operation in output characteristic curve.
a) Active region
b) Saturation region
c) Cut-off region
a) Active Region
This is the region where input junction is forward and output junction is reverse
biased.
Here the transistor is used as an amplifier.
b) Saturation region
Here both the junctions are forward biased. So it is like a closed switch.
Here output current becomes independent of input current.
c) Cut-off region
Here both the junctions are reverse biased. So it is like an open switch.
Here very few current will flow, due to minority carriers.
 109

6.12 COMMON BASE (CB) CONFIGURATION

In this type of configuration, input is
connected between base & emitter and E C IC
output is collected between collector IE
and emitter.
So in common base, input is at emitter
and output is at collector. IB B V CB
Here Input current = IE
Output current = IC
input voltage = VBE V BE
Fig. 6.10
Output voltage = VCB

6.12.1 Input Characteristic

Ø It is plotted between VBE & IE at constant VCB.

B 6V

=1 V

V
=0
VC =

CB

CB
V

V
10
EMITTER CURRENT, IE IN

8
mA

0.5 1.0 1.5

EMITTER-BASE VOLTAGE,
VBE IN VOLTS
Fig. 6.11
Input Characteristics For common Base NPN Transistor
Ø Here with increase in base to emitter voltage, emitter current increases. It
resembles to diode characteristics.
Ø Here by increasing the collector to base voltage, the input graph bends towards
current axis i.e slope increases i.e. input resistance decreases.
110 Basic Electronics
6.12.2 Output Characteristic

SATURATION ACTIVE REGION

REGION
4 IE= 4 m A

COLLNECTOR CURRENT
ICIN mA
3 IE= 3 m A

2 IE= 2 m A

1 IE= 1 m A
CUT-OFF
IE= 0 m A REGION
ICBO
–1 1 2 3 4

COLLECTOR BASE VOLTAGE, V CB IN VOLTS

Fig. 6.12
Output Characteristics For common Base NPN Transistor

The curve drawn between collector current IC and collector-base voltage VCB for
a given value of emitter current IE is known as output characteristic,
(i) The collector current IC varies with VCB only for very low voltage (below 1 V) but
transistor is never operated in this region.
(it) In active region emitter forward biased and collector reverse biased) collector current
IC is almost equal to IE and appears to remain constant when VCB is increased. In
fact, there is very small increase in IC with increase in VCB. This is because the
increase in VCB expands the collector-base depletion region and thus shortens the
distance between the two depletion regions. With emitter current IE held constant
however, the increase in Ic is so small that it is usually noticeable only for large
variations in VCB. IC is slightly lesser than IE in magnitude. Transistor is normally
operated in active region.
(iii) Although the collector current Ic is practically independent of VCB over the transistor
operating range. However if VCB is increased beyond a certain value, IC eventually
increases rapidly because of avalanche or Zener (or both ) effects. This condition is
known as punch-through or reach-through. When it occurs large currents can flow,
possibly destroying the device. The extension of the depletion region is, of course,
the direct consequence of the increase in VCB. Thus it is very essential to maintain
VCB below the maximum safe limit specified by the manufacturer of the device.
(iv) A very large change in collector voltage causes a very small change in collector
current i.e. output resistance of CB configuration is very high (of the order of few
hundred kΩ)-the dynamic output resistance r0 being given as the ratio of ∆VCB and
∆lC for a given value of IE.
 111

(v) In cut-off region (emitter and collector junctions both reverse-biased) small collector
current IC flows even when emitter current IE = 0. This is the collector leakage
current ICBO or IC0.
(vi) In saturation region ( both emitter and collector junctions forward-biased) collector
current Ic flows even when VCB ~ 0. Even when the externally applied bias voltage
is reduced to zero, there is still a barrier potential existing at the collector-base
junction, and this assists in the flow of IC. To stop it the collector-base junction has
to be forward biased. Consequently, collector current IC is reduced to zero when
VCB is increased negatively.
CB configuration is rarely used in audio-frequency (AF) circuits because its
current gain is less than unity and its input and output resistances are quite different.
6.12.3 Current Amplification factor (α)
It is the ratio of output majority collector current to the input emitter current.
I C maj
α=
IE
⇒ I C maj = αI C
Due to output junction is reverse biased, there is some minority collector current flows.
Here I C min = I CBO (Collector to base minority current when emitter is open)
so I C = I C maj + I C min
⇒ I C = αI E + I C BO ---- (1)
Example 6.1 :
In a P-N-P transistor operating in the active region, the collector current equals 6.4
mA and the emitter current equals to 6.6 mA. Compute the value of α, Neglect ICO.
Solution : Collector current, IC = 6.4 m A
Emitter current, IE = 6.6 m A
I C (6.4)
Current gain, α = = = 0.9697 Ans.
IE 6.6
Example 6.2 :
A transistor is connected in CB configuration. When the emitter voltage is changed
by 200 mV, the emitter current changes by 5 mA. During this variation, the collector
to base voltage is kept fixed. Calculate the dynamic input resistance of transistor.
Solution : The dynamic input resistance for CB configuration is gives as
∆VEB 200mV
ri = = 40Ω Ans.
∆I E VCB = Cons tan t
5mA
112 Basic Electronics
Example 6.3 :
The current gain of an N-P-N transistor α0 = 0.98. It is connected in the CB
configuration and gives reverse saturation current ICO = 10µA. Find the base and
collector currents for an emitter current of 2 mA.
Solution : Reverse saturation current, ICO = 10µA = 0.01 mA
Emitter current, IE = 2 m A
α0 = 0.98
Total collector current, IC = α IE + ICO = 0.98 × 2 + 0.01 = 1.97 m A
Base current, IB = IE – IC = 2 – 1.97 = 0.03 m A or 30 m A Ans.
Example 6.4 :
The reverse saturation current of an N-P-N transistor in common base circuit is
12.5µA. For an emitter current of 2 m A, collector Current is 1.97 m A. Determine
the current gain and base current.
Solution : Emitter current IE = 2 mA
Collector current, IC = 1.97 m A
Collector-to-base leakage current, ICBO = 12.5 µA = 0.0125 m A
Since IC = αIE + ICBO

I C − I CBO 197
. − 0.0125
∴Current gain, α = = = 0.979 Ans.
IE 2
Base current IB = IE – IC = 2 – 1.97 = 0.03 m A Ans
Example 6.5 :
In a grounded base configuration, the voltage drop across load resistance of 4 kΩ is
3 V. Determine base current. α = 0.96.
Solution : Load resistance RL = 4 k Ω
Voltage drop across load resistance, ICRL = 3 V

ICR L 3V
Collector current, I C = R = 4 kΩ = 0.75 mA
L

I C 0.75
Emitter current I E = = = 0.78 mA
α 0.96
Base current, IB = IE – IC = 0.78 – 0.75 = 0.03 m A Ans
 113

6.13 COMMON - EMITTER CONFIGURATION (CE)

IC
C

B
IB V CE
V BE E
Fig. 6.13
IE

In common emitter configuration, input is given at base w.r.t emitter and output is
collected at collector w.r.t. emitter.
So emitter is common to input as well as to the output.
6.13.1 Input Characteristic
It is plotted between input voltage VBE & input current IB at constant output voltage
VCE.
(i) The input characteristics of CE

2V
transistors are quite similar to those of

= 6V
200

VC =
E

CE
a forward biased diode because the

V
BASE CURRENT IB IN µA

base-emitter region of the transistor is

150
a diode and it is forward biased.
(ii) In comparison to common base (CB)
100
arrangement base (or input) current
increases less rapidly with the increase
in base-emitter voltage, V BE. This 50
indicates that input resistance is larger
in common emitter configuration than
that in common base configuration. 0.5 10 15
BASE EMITTER VOLTAGE VBE IN VOLTS
Due to initial non-linearity of the Fig. 6.14 : Input Characterestics For Common
curve, input resistance varies from Emitter NPN Transistor
point-to-point in the initial part of the
characteristic. Its value over the linear part of the curve is of the order of few hundred
ohms.
(iii) An increment in value of VCE causes the input current IB to be lower for a given level
of VBE. This is because the higher levels of VCE provide greater collector-base junction
reverse bias, causing greater depletion region penetration into the base and thus
reducing the distance between the collector-base and emitter-base regions. As a
114 Basic Electronics
result more of the charge carriers from the emitter flows across the collector-base
junction, and few flow out through the base lead. Usually effect of change in V CE on
the input characteristic is ignored.
The ratio of change in base-emitter voltage (∆VBE) to the resulting change in base
current (∆IB) at constant collector-emitter voltage (VCE) is known as dynamic input
resistance (ri). It is calculated as the reciprocal of the slope of the input characteristic
at a given VBE.
∆VBE
ri =
∆I E VCE = Cons tan t

6.13.2 Output characteristics

Output characteristic for a common emitter transistor is the curve drawn between
collector current Ic and collector-emitter voltage VCE for a given value of base current
IB.
(i) The collector current Ic varies with VCE for VCE between 0 and 1 V and then becomes
almost constant and independent of VCE. The transistors are always operated above
1 V.
(ii) Output characteristic in CE configuration has some slope while CB configuration
has almost horizontal characteristics. This indicates that output resistance in case
of CE configuration is less than that in CB configuration.
(iii) In active region (collector junction 00 µA
iB = 1
reverse biased and emitter junction
forward biased), for small values of G IO N
SATURATION REGION

6 E RE
AC TIV
base current IB the effect of collector iB = 80 µA
COLLECTOR CURRENT IC IN mA

voltage VC over IC is small but for 5

large values of IB this effect increases. 4

iB = 60 µA

The shape of the characteristic is same

3 iB = 40 µA
as in CB configuration but with the BREAK
DOWN
difference that collector current IC is 2
iB = 20 µA
larger than input current (base current
1
IB). Thus the current gain for this iB = 0 µA
configuration is larger than unity. The 1 2 3
CUT-OFF REGION
4 5 6
transistor must always be operated in COLLECTOR-EMITTER VOLTAGE VCE IN VOLTS

the active region, when employed as Fig. 6.15

an amplifying device. Output Characterestics For Common
(iv) With low values (ideally zero) of VCE Emitter NPN Transistor
the transistor is said to be operated in
saturation region and in this region base current IB does not cause a corresponding
change in collector current IC.
 115

(v) With much higher VCE, the collector-base junction completely breaks down and
because of this avalanche breakdown collector current IC increases rapidly and the
transistor gets damaged.
(vi) In cut-off region, small amount of collector current IC flows even when base current
IB = 0. This is called ICEO. Since main current IC is zero so the transistor is said to be
cut-off. (vii) Moderate output to input impedance ratio makes this configuration an
ideal one for coupling between various transistor stages.
The ratio of change in collector-emitter voltage (∆VCE) to the change in collector
current (∆IC) at constant base current is known as dynamic ouput resistance.
It is calculated as the reciprocal of the slope of output characteristic at a given VCE.
∆VCE
i. e., r0 =
∆I C I B = Cons tan t

The output resistance of CE configuration is less than that of CB configuration as the

slope of the ouput characteristic is more in this case. Its value is of the order of 50 kΩ.
The output characteristics may also be used to determine the dc current gain p and ac
current gain β 0 as follows
IC
DC current gain, β DC =
IB

∆I C
AC current gain, β ac =
∆I B VCE = cons tan t

6.13.3 Current amplification factor (β)

It is the ratio of Majority Collector current to the input base current.
I C maj
So β=
IB
⇒ I C maj = β I B
Due to reverse biasing of collector & base, there is minority collector current.
I C min = I CEO = Collector to emitter minority- Current when base is open.
So I C + I C maj + I C min = βI B + I CEO
6.13.4 Relation between α, β and ICEO, ICBO
It is known that, I C = αI E + I CBO I C = αI E + I CBO
b g
= α I C + I B + I CBO
b g
⇒ I C 1− α = αI B + I CBO
116 Basic Electronics

FG α IJ I I CBO
⇒ IC = H1− αK I−α
B +

Comparing it with equation IC = βIB + ICEO

α β
β= or α = i.e. α < < β
1− α 1+ β

& I CEO =
I CBO
1− α
b g
= β + 1 I CBO i.e. I CBO > I CBO
Example 6.6 :
A certain transistor has a current gain of 0.99 in common base configuration.
Calculate its current gain in the common emitter configuration. Another transistor
has β = 80, determine its α.
Solution: Current gain in common base configuration for transistor A, α = 0.9
Current gain in common emitter configuration for transistor A,
α 0.99
β= = = 99 Ans.
1 − α 1 − 0.99
Current gain in common base configuration for transistor B having β = 80
β 80 80
α= = = = 0.988 Ans.
1 + β 1 + 80 81
Example 6.7 :
In common emitter configuration the voltage drop across load resistance of 1 k Ω is
1.2 V . Determine the base current. Given that β = 60
Solution: Load resistance, RL = 1.0 kΩ
Voltage drop across load resistance, IC RL = 1.2 V
ICR L 12. V
Collector current, I C = = = 12
. mA
RL . kΩ
10
Current gain factor, β = 60
I C 1.2 mA
Base current, IB = = = 20µ A Ans.
β 60
Example 6.8 :
A transistor is connected in common emitter configuration . Collector supply voltage
VCC is 10 volts, load resistance RL is 800 Ω, voltage drop across load resistance is 0.8
V and current gain α = 0.96. Determine collector-emitter voltage and base current.
Solution : Collector supply voltage, VCC = 10 V
Voltage drop across load resistance, IC RL = 0.8 V
Collector-emitter voltage, VCE = VCC – ICRL = 10 – 0.8 = 9.2 Ans.
 117

I C R L 0.8
Collector current, IC = = = 10
. mA
RL 800

α 0.96
Current gain factor, β = = = 24
1 − α 1 − 0.96

I C 1.0 mA
Base current, IB = = = 41.67 µ A Ans.
β 24
Example 6.9 :
A germanium transistor with ct0 =0.98 gives a reverse saturation current ICO= 10
µA is CB configuration. When transistor is used in CE configuration with a base
current of 0.22 µA, calculate the collector current. Derive the formula used.
Solution: Collector-to-base leakage current, ICO = 10 µA = 0.01 m A
AC current gain, α0 = 0.98
Base current, IB = 0.22 µA = 0.22 × 10–3 m A

α 1
collector current, I C = . I B + CO
1− α 1− α
= 0.01078 + 0.5 = 0.51078 mA Ans.
Example 6.10 :
A change of 250 mV in base-emitter voltage causes a change of 100 µA in the
base current. Determine the dynamic input resistance.
Solution : Change in base-emitter voltage, ∆VBE = 250 m V
Change in base current, ∆IB = 100 µA

∆VBE 250 × 10 −3
Dynamic input resistance, ri = = = 2.5kΩ Ans
∆I B 100 × 10 −6
Example 6.11 :
Increase in collector-emitter voltage from 5 V to 10 V causes increase in collector,
current from 5 mA to 5.8 mA. Determine the dynamic output resistance.
Solution: Change in collector-emitter voltage, ∆VCE = 10 – 5 = 5 V
Change in collector current, ∆lC = 5.8 – 5.0 = 0.8 m A

∆VCE 5
Dynamic output resistance, r0 = = = 6.25 k Ω Ans
∆I C 0.8 × 10 −3
118 Basic Electronics
6.14 COMMON COLLECTOR CONFIGURATION
Here collector is common to both input and output circuit. IE
Here input current = IB
E
input voltage = VBC
output voltage = VBC B
output current = IC
IB V EC
So here current amplification factor is γ.
IC C
I VBC
γ = E ⇒ I E = γI B
IB
Fig. 6.16
6.15 RELATION BETWEEN α, β & γ
I E = γI B
Also b g
I E = I C + I B = βI B + I B = β + 1 I B
So γ = β + 1
α 1
Also β = ⇒ β + 1=
1− α 1− α
1
So γ = β + 1 =
1− α
6.16 TRANSISTOR LOAD LINES
Ø Load line is defined as the locus of operating point on the output characteristic of the
transistor.
Ø It is the line on which the operating point moves when ac signal is applied to a transistor.
Ø It also represents the characteristic of load.
In transistor there are two types of load line
- DC load line.
- AC load line.
6.16.1 DC load line IC
C
During no ac signal supply, when only RC
dc supply are considered, then from B
output KVL, we will get :-
RB
E V CC
VCC − I C R C − VCE = 0 V BB

⇒ VCE = VCC − I C R C
Fig. 6.17
 119

It is the Load line equation.

Here if IC = 0, VCE = VCC IC

& If VCE = 0, IC =
VCC FG 0, V IJ
H R K
CC
RC
C

So joining these two points we will get DC load line.

FG −1 IJ
It has a slope of
HR K
C (VCC,0)
V CE

6.16.2 Operating Point (Q-point) Fig. 6.18

Ø The point that corresponds to collector current & collector to emitter voltage in the
absence of signal is known as operating point / Quioscent point / Q - Point.

Ø Generally Q - point is chosen in the IC

middle of active region where V CC
1 RC
VCE = VCC .
2 Q
I CQ I BQ
Ø It is obtained by intersection of dc load
line with the transistor output
characteristic graph. V CE
V CEQ V CC
Fig. 6.19
6.16.3 AC load line
Ø When an ac signal is applied, the transistor collector to emitter voltage VCE & collector
current IC, vary above & below the operating point.
Ø It gives the values of VCE & IC when an ac signal is applied.
Ø Due to input ac signal, maximum current
VCE Q
= I CQ + IC
RL
FG I +
VCE Q IJ
& maximum voltage = VCE Q + I CQ R L H CQ
RL K
VCC
RC
Ø It is more steeper than dc load line. Q
I CQ
Ø Two load lines intersect at Q-point.
Q
V CEQ V CC dV
CE Q + I CQ R L i Fig. 6.20
120 Basic Electronics
6.17 BIASING
Ø It means to give external dc to a device for a specific operation.
Ø It is also known as dc analysis.
Ø During this analysis all ac sources are made zero.
Ø It is needed to set a proper operating point of the device.
6.17.1 Transistor Biasing
It means proper flow of zero signal collector current and maintenance of proper collector
to emitter voltage during the passage of signal.
6.18 NECESSITY OF BIASING
For most of the applications, transistors are required to operate as linear amplifiers
(i.e. to amplify output voltage as a linear function of the input voltage). To achieve this, it
is necessary to operate the transistor over region of its characteristic curves which are
linear, parallel and equi-spaced for equal increments of the parameter. Such an operation
can be ensured by proper selection of zero signal operating point and limiting the operation
of the transistor over the linear portion of the characteristics. For proper selection of zero
signal operating point, proper biasing i.e. application of dc voltages at emitter-to-base
junction and collector-to-base junction is required.
If the transistor is not biased properly, it would work inefficiently and produce distortion
in the output signal.
So the biasing in the BJT device is needed to have faithful amplification which can be
achieved by
i) Zero signal collector current
ii) Minimum base-emitter voltage
iii) Minimum collector - emitter voltage
The first two conditions ensure that emitter - base junction is forward biased
whereas third condition ensures that collector-base junction is reverse biased.
6.19 TRANSISTOR BIASING CIRCUITS
There are four types of transistor biasing circuit :-
I) Fixed bias circuit
II) Self / emitter - stabilized bias circuit.
III) Voltage divider bias circuit
IV) DC feedback bias circuit.
6.19.1 Fixed bias circuit
Here the emitter resistance must be zero
i.e. RE = 0
Biasing analysis means
dc analysis. So f = 0
 121

VCC
1
⇒ XC = →∞
2πfc
Thus capacitors can be replaced by RB RC
open circuit.
C ac o/p
CO signal

i/p B
signal Ci
E

Fig. 6.21
VCC
So the circuit becomes →
Ib
RB RC
o/p loop
C
B +
VCE
+
VBE –
i/p loop – E

Fig. 6.22

The loop that covers, input junction is known as input loop & The loop that covers
output junction, know as output loop.
Input loop

Applying KVL in input loop, IB

VCC − I B R B − VBE = 0 RB +
–
VCC − VBE V BE
⇒ IB = V CC
RB

Fig. 6.23
Because VCC, VBE & RB are constant for a circuit, so IB is fixed. So it is fixed biasing.

Output loop
Here IC = βIB
Apply KVL in output loop,
122 Basic Electronics

VCC − I C R C − VCE = 0 IC

⇒ VCE = VCC − I C R C +
RC
This is known as load line equation V CE
Here VE = 0V – V CC
Now VCE = VC − VE
⇒ VC = VCC – ICRC
VBE = VB – VE
= VB.
Fig. 6.24
Advantage
Ø It is very simple.
Ø Circuit, has simple calculation and there is no loading of source, as no emitter
resistor.
Disadvantage :
Ø This method provides poor stability
Ø There is good chances of thermal runaway.
Example 6.12 : Determine the following for the fixed-bias configuration of Fig.6.25
(a) I BQ and I C Q VCC=+12V

(b) VCE Q
(c) VB and VC
(d) VBC.
RC
2.2 kΩ
RB
240 kΩ C2
ac
10µF
output
C1
ac VCE
input
10µF
Fig. 6.25

Solution :
VCC − VBE 12 V − 0.7 V
(a) I BQ = RB
=
240kΩ
= 47.08µA

I C Q = βI BQ = (50)( 47.08µA ) = 2.35mA

(b) VCE Q = VCC − I C R C

= 12 V – (2.35 mA) (2.2 kΩ)
= 6.83 V
 123

(c) VB = VBE = 0.7 V

VC = VCE = 6.83 V
(d) Using double-subscript notation yields
VBC = VB − VC = 0.7 V − 6.83 V
= – 6.13 V
with the negative sign revealing that the junction is reversed-biased, as it should be for
linear amplification.
6.19.2 Self / Emitter-Stabilized bias circuit V CC
This circuit contains an emitter
resistor to improve the stability level.
So this is known as emitter-stabilized RB RC
bias circuit.
IE C V0
IB + C0
Vi V CE
Ci B + –
Input loop
V BE– E
Applying KVL, IE
VCC – IBRB – VBE – IERE = 0 RE
Now IE = IC + IB Fig. 6.26
= βIB + IB
= (β + 1) IB
So VCC – IBRB – VBE – (β + 1) IBRE = 0

VCC − VBE
IB =
⇒ b g
RB + β + 1 RE

Here input loading effect due to RE is

Ri = (β +1) RE
Output loop IB RB
IE
IC = βIB ~ IE
V CC RE
Applying KVL in output loop,
VCC – ICRC – VCE – ICRE = 0 Fig. 6.27

⇒ VCE = VCC – IC (RC + RE) → Load line equation

Here VE = IERE
VCE = VC – VE ⇒ VC = VCE + VE = VCC – ICRC
124 Basic Electronics

RC
+
VBE = VB – VE ⇒ VB = VBE + VE V CE IC
V CC
VCC –
The saturation current ICsat = IE
RC + RE
RE
Example 6.13
Fig. 6.28
For the emitter bias network of Fig. 6.29, determine.
(a) IB .
+20 V
(b) IC.
(c) V CE
(d) V C
(e) V E
2 kΩ
(f) V B
430 kΩ 10 µF
(g) V BC v0

10 µF β = 50
vi

1kΩ 40 µF
Fig. 6.29
Solution

VCC − VBE 20V − 0.7 V

(a) I B = R + (β + 1) R = 430 kΩ + (51)(1kΩ)
B E

19.3 V
= = 401
. µA
481 kΩ
(b) IC = βIB
= (50) (4.1 µA)
≅ 2.01 mA
(c) VCE = VCC – IC (RC + RE)
= 20 V – (2.01 mA)(2kΩ + 1kΩ) = 20 V – 6.03 V
= 13.97 V
 125

(d) V C = VCC – ICRC

= 20 V – (2.01 mA)(2kΩ) = 20 V – 4.02 V
= 15.98 V
(e) VE = VC – VCE
= 15.98 V – 13.97 V
= 2.01 V
or VE = IERE ≅ ICRE
= (2.01 mA)(1 kΩ)
= 2.01 V
(f) VB = VBE + VE
= 0.7 V + 2.01 V
= 2.71 V
(g) VBC = VB – VC
= 2.71 V – 15.98 V
= – 13.27 V (reverse-biased as required)
VCC
6.19.3 Voltage - Divider biasing
Since β is temperature sensitive, the RC
R1
Q-point is not stable. So a bias circuit is
designed so that Q-point will be V0
independent of β. C0
Vi
Here two resistors are used at input Ci
side so whole dc supply is not given to
input, rather a part of it is given. So it is R2
RE CE
voltage divider - bias. Circuit.
There are two types of analysis =
1) Exact analysis Fig. 6.30
II) Approximate analysis. VCC
Exact analysis RC
First using Thivenin’s theorem, the input
circuit connected between base to emitter
can be replaced by single voltage VTh, R1
series with RTh,
VCC R2 RE

Fig. 6.31
126 Basic Electronics

R1 +
VTh = Voltage across R2 i.e at open end.
V CC VTh
R2
= VCC R2
R1 + R 2
–
Fig. 6.32

RTh = Resistance observed from open R1

end with dc sources = 0.

R 1R 2 R2
=
R1 + R 2 RTh
Input loop
Fig. 6.33
By KVL

b g
TTh − I B R Th − VBE − β + 1 I B R E = 0
IB B
VTh − VBE
⇒ IB = R + β + 1 R
+
Th b g
E
RTh V BE
– IE
E
VTh
RE

Fig. 6.34
Output loop
Here IC = βIB ~ IE IC
RC
So by applying KVL,
VCC – ICRC – VCE – ICRE = 0 +
⇒ VCE = VCC – IC (RC + RE) V CE
V CC
V E = IERE = Voltage at emitter terminal. –
IE
VCE= VC – VE ⇒ VC = VCE + VE = VCC – ICRC
VBE= VB – VE ⇒ VB = VBE + VE RE

Approximate analysis : Fig. 6.35

This analysis is applicable if it satisfies following condition :-
βR E ≥ 10R 2 i. e R i ≥ 10R 2
 127

Under this condition there will be V CC

approximately no base current to the
transistor.
RC
Now VB = VTh
C +
Then VE = VB – VBE IB~ 0 RTh
B
V CE
VE
and IE = ~ IC +
RE –
V BE – E
So VC = VCC – ICRC
VTh RE
& VCE = VC – VE
This makes analysis easier
Fig. 6.36

Example 6.13 : 18 V

Determine the levels of I C Q and

VCE Q for the voltage-divider 5.6 kΩ

82 kΩ I CQ
configuration of Fig. 6.37 using the
10 µF
exact and approximate techniques v0
+
and compare solutions. vi VCEQ β = 50
10 µF –

Solution : 22 kΩ 1.2 kΩ
Exact Analysis
βRE > 10R2 Fig. 6.37
(50)(1.2 kΩ) > 10 (22 kΩ)
60 kΩ ≥/ 220 kΩ (not satisfied)
RTh R1|| R2 = 82 kΩ || 22 kΩ = 17.35 kΩ

R 2 VCC 22 kΩ (18 V)
E Th = = = 381
. V
R1 + R 2 82 kΩ + 22 kΩ

E Th − VBE . V − 0.7 V
381 311
. V
IB = = = = 39.6 µA
b g
R Th + β + 1 R E 17.35 kΩ + (51)(12
. kΩ) 78.55 kΩ

I C Q = βI B = (50)( 39.6 µA ) = 1.98 mA

b
VCE Q = VCC − I C R C + R E g
128 Basic Electronics
= 18 V – (1.98 mA)(5.6 kΩ + 1.2 kΩ)
= 4.54 V
Approximate Analysis
VB = ETh = 3.81 V
VE = VB – VBE = 3.81 V – 0.7 V = 3.11 V

VE 311. V
I CQ ≅ I E = = = 2.59 mA
. kΩ
R E 12

b
VCE Q = VCC − I C R C + R E g
= 18 V – (2.59 mA)(5.6 kΩ + 1.2 kΩ)
= 3.88 V
Tabulating the results, we have :

I CQ ( mA ) VCE Q ( V)
Exact 198
. 4.54
Approximate 2.59 388
.

6.19.4 DC feedback biasing

Feedback means to give some part of output to the input of same circuit. It is given to
increase the stability.
V CC
Here RB is feedback component. This is a
case of current - shunt feedback. RC
i/p
IC+IB=IE
loop I
IB C
RB C V0
Input loop V CE C 0
Vi B
V BE O/p
Applying KVL, E loop
VCC – IERC – IBRB – VBE – IERE = 0 RE
b g b g
⇒ VCC − β + 1 I B R C − I B R B − VBE − β + 1 I B R E = 0 I
E
Fig. 6.38
VCC − VBE
⇒ IB = R + β + 1 R + R
B b gb
C E g
⇒ IB ~ IB = VCC − VBE
b
R B + β RC + R E g
 129

Output loop
IC ~ IE ≅ βI B
Applying KVL,
VCC – ICRC – VCE – ICRE = 0
⇒ VCE = VCC – IC (RC + RE)

Here VE = IERE
VC = VCE + VE
VB = VBE +VE
18 V
Example 6.14 :
Determine the dc level of IB and 3.3 kΩ
91 kΩ 110 kΩ 10 µF
VC for the network of Fig. 6.39.
v0
R1 R2
10 µF 10 µF
vi β = 75

510 Ω 50 µF

Fig. 6.39
Solution :
In this case, the base resistance for the dc analysis is composed of two resistors with a
capacitor connected from their junction to ground. For the dc mode, the capacitor assumes
the open-circuit equivalence and RB = R1 + R2.
Solving for IB gives

VCC − VBE
IB =
b
R B + β RC + R E g
18V − 0.7 V
=
(91kΩ + 110kΩ) + (75)(3.3kΩ + 0.51kΩ)

17.3 V 17.3 V
= =
201 kΩ + 285.75 kΩ 486.75 kΩ
= 35.5 µA
IC = βIB
= (75)(35.5 µA)
= 2.66 mA
130 Basic Electronics

VC = VCC – I'C R C ≅ VCC − I C R C

= 18 V – (2.66 mA)(3.3 kΩ)
= 18 V – 8.78 V
= 9.22 V
Example 6.15 : For the network of Fig. 6.40 : VCC = 20 V

(a) Determine I C Q and VCE Q .

(b) Find VB, VC, VE, and VBC.
RC 4.7 kΩ

RB 10 µF
v0
680 kΩ C2

10 µF
vi
β = 120
C1

Fig. 6.40
Solution :
(a) The absence of RE reduces the reflection of resistive levels to simply that of RC and
the equation for IB reduces to

VCC − VBE
IB =
R B − βR C

20 V − 0.7 V 19.3 V
= =
680 kΩ + (120)(4.7 kΩ) 1244
. MΩ
= 15.51 µA
I C Q = βI B = (120)(15.51µA )

= 1.86 mA
VCE Q = VCC − I C R C

= 20 V – (1.86 mA)(4.7 kΩ)

= 11.26 V
VB = VBE = 0.7 V
VC = VCE = 11.26 V
VE = 0 V
VBC = VB – VC = 0.7 V – 11.26 V
= – 10.56 V
 131

Example 6.16 : 12V IC=2mA

Determine
RC, RE, RB, VCE, VB RC
RB
7.6V

B β = 80

E 2.4V
Solution :
RE
Here VE = 2.4 V
Fig. 6.41
⇒ ICRE = 2.4 ⇒ 2.RE = 2.4 ⇒ RE = 1.2 KΩ
VC = 7.6 V ⇒ VCC– ICRC = 7.6
⇒ 12 – 2RC = 7.6

12 − 7.6
⇒ RC = = 2.2 KΩ
2
By input KVL
12 – IBRB – VBE – ICRE = 0
2
⇒ 12 − RB − 0⋅7 − 2 × 4 = 0
80

8 ⋅ 9 × 80
⇒ RB = = 356 KΩ
2
VCE = VC – VE = 7 ⋅ 6 – 2 ⋅ 4 = 5 ⋅ 2 V
VBE = VB – VE ⇒ VB = VBE + VE = 0 ⋅ 7 + 2 ⋅ 7 = 3 ⋅ 1 V
VCC
Example 6.17 :
In a voltage divider bias circuit R1 RC
RC = 2 ⋅ 7 KΩ, RE = 1 ⋅ 2 KΩ, R2= 8 ⋅ 2 KΩ, VC=10 ⋅ 6V,,
IB = 20 µA & B = 180. Then Find VCC, VB, R1.
β = 100

R2
RE

Fig. 6.42
132 Basic Electronics

Solution : VCC

VC = VCC – ICRC = 10.6 RC = 2.7KΩ

⇒ VCC – βIBRC = 10.6 IC
VC=10.6V
⇒ VCC = (100 × 20 × 10–3 × 2.7) + 10.6 IB +
= 5.4 + 10.6 VCE
RTh +
⇒ VCC = 16 V. –
–
So VE = ICRE = βIBRE
VTh
= 2 × 1.2 RE=12KΩ
= 2.4 V
Fig. 6.43
⇒ VB = VBE + VE
= 0.7 + 2.4
VB = 3.1V
⇒ VTh – IBRTh = 3.1

R 2 VCC R 1R 2
⇒ R + R − I B R + R = 31.
1 2 1 2

8.2 × 16 R × 8.2
⇒ − 0.02 1 = 31
. ⇒ 131.2 – 0.164 R = 25.42 + 3.1R
8.2 + R1 8.2 + R1 1 1

⇒ 3.264 R1 = 105.78
⇒ R1 = 32.4 KΩ Ans.

Example 6.18 : 12V

Find the range of VC due to potentiometer
of 1MΩ. 1MΩ 4.7KΩ
150KΩ

β= 180
Solution : There is a potentiometer of 1µΩ i.e it can
vary from 0 to 1MΩ.
When potentiometer is at 0Ω −
Now by input KVL, 3.3K Ω

12 − I C ( 4.7) − 150 I B − 0.7 − I C (33) = 0 Fig. 6.44

 133

⇒ 12 – 180 IB × 4.7 – 150 IB – 0.7 – 180 IB × 33 = 0 12V

⇒ 12 – 846IB – 150 IB – 0.7 – 594 IB = 0
IE ~ IC
13
.
⇒ IB = = 6.92 µA 4.7KΩ
1590
IC = βIB = 1.245 mA VC
150KΩ
So VC = 12 – ICRC
= 12 – 1.248 × 4.7 IB
IE ~ IC
= 6.15 V
3.3KΩ

Fig. 6.45
When potentiometer is at 1MΩ = 1000 KΩ

12 − 0.7
IB = 12V
1180 + 180 (4.7 + 3.3)
= 4.36 µA 4.7KΩ
I C = βIB = 180 × 4.36 µA
VC
= 0.785 mA 1150KΩ
V C = VCC – ICRC
= 12 – 0.785 × 4.7
= 8.3 V
So range of VC is 6.15 V to 8.3V
3.3KΩ
Fig. 6.46

18V
Example 6.19 : Find IB, IC, VE, VCE
9.1KΩ
510KΩ

β = 130

510KΩ 7.5KΩ

– 18V Fig. 6.47

134 Basic Electronics

18V
Solution :
The circuit can be redrawn as :- 9.1K Ω

510KΩ

510KΩ 7.5KΩ
18V
18V 18V

Fig. 6.48

The Circuit connected to transistor i/p junction is.

510 × 510
Here RTh = 510 || 510 =
510 + 510 510KΩ
510KΩ
= 275 KΩ
18V
FG
510
b g IJK − 18
18V
VTh =
H
510 + 510
18 + 18 Fig. 6.49

= OV
So the circuit becomes :-
By i/p KVL, 18V
– 275 IB – 0.7 –7.5 (130 IB) + 18 = 0 9.1KΩ
17.3 C
⇒ IB = = 0.01384 mA B +
1250 V CE
IC = βIB = 130 × 0.01384 275KΩ –
V BE E
= 1.8 mA
VE = IC × 7.5 – 18 = – 4.8V 7.5KΩ

– 18V Fig. 6.50

By output KVL, 18 – 1.8 × 9.1 – VCE – 1.8 × 7.5 + 18 = 0
⇒ VCE = 6.12 V
 135

–8V

Example 6.20 : Find IE, VC & VCE 2.2KΩ (β = 100)

for Figure 6.51, where β = 100

1.8KΩ

Fig. 6.51 10V

Solution :
The Circuit can be redrawn as - 10V

1.8KΩ
By input KVL,
–VBE – 2.2 × BIB + 8 = 0 C
B +
V CE β=100
73
. +
⇒ IB = =0.03318 mA
. ×100
22 V BE –
–
7.3 2.2KΩ
IC ~ βIB = = 3.318 mA
2.2
IE = IC + IB = 3.65 mA –8V
VCC – ICRC = 10 – 3.318 × 1.8 ~ 4V Fig. 6.52

By output KVL, 10 – 1.8 × 3.18 – VCE – 2.2 × 3.18 + 8 =0

⇒ VCE = 18 – 12.72 = 5.28 V
–18 V
Example 6.21 : Determine VCE for the
2.4 kΩ
voltage-divider bias configuration 47 kΩ 10 µF
of Fig. 6.53 v0
10 µF B
C
+
vi VCE β = 120
E –
10 kΩ
1.1 kΩ

Fig. 6.53
Solution
Testing the condition
βRE > 10R2
136 Basic Electronics
results in (120)(1.1kΩ) > 10(10 kΩ)
132 kΩ > 100 kΩ (satisfied)
Solving for VB, we have
R 2 VCC (10kΩ)( −18V)
VB = = = −316
. V
R1 + R 2 47 kΩ + 10kΩ
Applying Kirchhoff’s voltage law around the base-emitter loop yields
+VB – VBE – VE = 0
VE = VB – VBE
and
Substituting values, we obtain
VE = – 3.16 V – ( 0.7 V)
= – 3.16 V + 0.7 V
= – 2.46 V
The current
VE 2.46 V
IE = = = 2.24 mA
. kΩ
R E 11
For the collector-emitter loop :
–IERE + VCE – ICRC + VCC = 0
Substituting IE ≅ IC and gathering terms, we have
VCE = – VCC + IC (RC + RE)
Substituting values gives
VCE = – 18 V + (2.24 mA) (2.4 kΩ + 1.1 kΩ)
= – 18 V + 7.84 V
= – 19.16 V
Example 6.22 : Determine VC and VB for the network of Fig. 6.54

RC 1.2 kΩ
C2
v0
10 µF
C1
Vi
β = 45
10 µF
RB 100 kΩ

VEE= –9V Fig. 6.54

 137

Solution :
Applying Kirchhoff’s voltage law in the clockwise direction for the base-emitter loop
will result in
− I B R B − VBE + VEE = 0
VEE − VBE
and IB =
RB
Substitution yields
9 V − 0.7 V
IB =
100 kΩ

8.3 V
=
100 kΩ
= 83 µA
IC = βIB
= (45) (83 µA)
= 3.735 mA
VC= ICRC
= – (3.735 mA)(1.2 kΩ)
= – 4.48 V
VB = –IBRB
= – (83 µA) (100 kΩ)
= – 8.3 V

Example 6.23 : Determine VCE Q and IE for the network of Fig. 6.55.

C1
vi β = 90

10µF C2
RB 240 kΩ v0
10 µF
RE 2 kΩ
VEE –20 V Fig. 6.55

Solution :
Applying Krichhoff’s voltage law to the input circuit will result in
138 Basic Electronics

− I B R B − VBE − I E R E + VEE = 0
but I E = (β + 1) I B
and VEE – VBE – (β + 1) IBRE – IBRB = 0
VEE − VBE
IB =
with b g
RB + β + 1 RE
Substituting values yields
20V − 0.7 V
IB =
240kΩ + (91)(2 kΩ)

19.3 V 19.3V
= =
240 kΩ + 182 kΩ 422 kΩ
= 45.73 µA
IC = βIB
= (90) (45.73 µA)
= 4.12 mA
Applying Kirchoff’s voltage law to the output circuit, we have
– VEE + IERE + VCE = 0
but IE = (β + 1)IB
and VCE Q = VEE − (β + 1) I B R E
= 20 V – (91)(45.73 µA)(2 kΩ)
= 11.68 V
IE = 4.16 mA
Example 6.24 : Determine VC and VB for the network of Fig. 6.56
VCC = +20V

RC 2.7 kΩ
R1 8.2kΩ
C C2
C1 v0
10µF
vi
10 µF
E
R2 2.2 kΩ RE 1.8 kΩ

VEE = – 20V Fig. 6.56

 139

Solution :
The Thevenin resistance and voltage are determined for the network to the left of the base
terminal as shown in Figs. 6.57 and 6.58.

R1 8.2 kΩ
B B
8.2 kΩ +

R2 2.2 kΩ R2 22.kΩ
VCC ETh
20 V
RTh VEE 20 V –

Fig. 6.57 Determining RTh. Fig. 6.58 Determining E Th

RTh :
RTh = 8.2 kΩ || 2.2 kΩ = 1.73 kΩ
ETh :

VCC + VEE 20V + 20V 40V

I= = =
R1 + R 2 8.2 kΩ + 2.2 kΩ 10.4 kΩ
= 3.85 mA
ETh = IR2 – VEE
= (3.85 mA)(2.2 kΩ) – 20 V
= – 11.53 V
The network can then be redrawn as shown in Fig. 6.59, where the application of
Kirchooff’s voltage law will result in
– ETh – IBRTh – VBE – IERE + VEE = 0

+ RTh VB
–
β = 120
1.73 kΩ +
IB VBE
– E
ETh 11.53 V +
RE 1.8 kΩ
–

VEE = – 20V
Fig. 6.59
140 Basic Electronics
Substituting IE = (β + 1) IB gives
VEE – ETh – VBE – (β + 1) IBRE – IBRTh = 0

VEE − E Th − VBE
and IB =
R Th + ( β + 1) R E

20V − 1153
. V − 0.7 V
=
. kΩ + (121)(18
173 . kΩ)

7.77 V
=
219.53 Ω
= 35.39 µA
IC = βIB
= (120)(35.39µA)
= 4.25 mA
VC = VCC – ICRC
= 20 V – (4.25 mA)(2.7 Ωk)
= 8.53 V
VB = –ETh – IBRTh
= – (11.53 V) – (36.39µA)(1.73 Ωk)
= – 11.59 V
6.20 BIAS STABILIZATION
Only the fixing of a suitable operating point is not sufficient but it is also to be
ensured that the operating point remains stable i.e. it does not shift due to change in
temperature or due to variations in transistor parameters (due to replacement of transistor).
Unfortunately it is not possible in practice unless special efforts are made to achieve it.
The maintenance of the operating point stable (independent of temperature variations
or variations in transistor parameters) is known as stabilization.
6.21 NEED FOR BIAS STABILIZATION
The stabilization of operating point is essential because of
(i) Temperature dependence of collector current IC
(ii) Individual variations and
(iii) Thermal runaway.
(i) Temperature Dependence of Collector Current IC. The instability of collector current
IC, being equal to β IB + (1 + β) ICO, due to variations in temperature, is caused because of
the three following main factors.
 141

(a) Reverse saturation current (leakage current), ICO, which doubles for every 10° C
rise in temperature.
(b) Transistor current gain p, which increases with the increase in temperature.
(c) Base-emitter voltage VBE, which decreases by 2.5 m V per0 C.
Any or all of the above factors can cause the bias point to shift from the values
originally fixed by the circuit because of a change in temperature.
Though with the change in temperature collector-emitter voltage V CE also changes
but the change is very small and collector current IC is not affected.
(ii) Individual Variations. The value of p and VBE are not exactly the same for any two
transistors even of the same type. For an example BC 147 is a silicon transistor with β
varying from 100 to 600 (for one transistor β may be 100 and for the other it may be 600).
The major reason for these variations is that transistor is a new device and manufacturing
techniques have not too much advanced. For an instance, it has not been possible to control
the base width and it may vary, although slightly, from one transistor to another one of the
same type. Such little variations result in a large change in the transistor parameters such
as β, VBE etc.
Thus when a transistor is replaced by another of the same type, the operating point
may shift. Such problems do not arise in case of vacuum tube circuits because it is possible
to manufacture vacuum tubes with identical characteristics.
(iii) Thermal Runaway. The collector current IC, being equal to β IB + (1 + β) ICO, increases
with the increase in temperature. This leads to increased power dissipation with further
increase in temperature. Being a cumulative process it can lead to thermal runaway resulting
in burn-out of the transistor. The self destruction of an unstabilized transistor is called the
thermal runaway.
However, if by some modification, IB is made to fall with increase in temperature
automatically, then decrease in the term β IB can be made to neutralize the increase in the
term (1 + β) ICO, thereby keeping IC almost constant. This will achieve thermal stability
resulting in bias stability.
6.22 STABILITY FACTOR
It is the ratio of change in collector current with change in any transistor constants.
It is of three types :-

S I CO = ∆I C ∆I CO VBE & β = Cons tan t

S V BE = ∆I C ∆VBE I CO & β = Cons tan t

Sβ = ∆I C ∆β I
CO & VBE = Cons tan t

Ø Higher is the stability factor, the more sensitive the network variations in that
parameter i.e. the circuit exhibits thermal instability.
142 Basic Electronics
Ø To be stable & relatively insensitive to temperature variation, the circuit should have
low value of stability factor.
6.22.1 General Expression for SI CO
IC = βIB + (β+1) ICO
Now differentiating expression w.r.t IC, considering β constant,
dI C
dI C
dI
b g
dI
= β B + β + 1 CO
dI C dI C
dI B β + 1
⇒ 1 = β dI + S
C I CO

dI B β + 1 β +1
⇒ 1 = β dI + S ⇒ SI CO =
dI
C I CO
1− β B
dI C
6.22.2 General Expression for Sβ
IC = βIB + (β+1) ICO
Differentiating the expression w.r.t IC considering ICO Constant ;

1= β
FG dI B
+ IB
dβ IJ
+ I CO
dβ
H di C dI C K dI C

dI B
b 1
β
g I + IB
⇒ 1 − β dI = I B + I CO S ⇒ Sβ = CO
dI
1− β B
C

dI C
6.22.3 Stability factors in different Bias Circuit
In Fixed bias :-

VCC − VBE
IB =
RB
∂E B
⇒ =0
∂I C
So SI CO = β + 1
Sβ = I CO + I B

Now I C = βI B = β
FG V − VBE IJ
H K
CC
RB
 143

∂I C −β
⇒∂ =
VBE R B
β
⇒ S VBE =
RB
As stability factors are dependent on β . So this circuit is least stable.
In Self / Emitter-Stabilized Circuit :
VCC − I B R B − VBE − I E R E = 0
⇒ VCC – IBRB – VBE – (IC + IB) RE = 0 --------- (1)
Differentiating w.r.t to IC, considering VBE Constant,

∂I B ∂I
0 − RB − 0 − RE − RE B = 0
∂I C ∂I C
∂I B −R E
⇒ =
∂I C R B + R E

β +1
So SI CO = RE
1+ β
RB + RE

FG1 + R IJ
H RK
B

SI CO = bβ + 1g E
⇒
bβ + 1g + RR B

I CO + I B
and Sβ =
RE
1+ β
RB + RE

I C = βI B = β
FG V − VBE IJ
HR K
CC
Here
B + βR E

∂I C −β
⇒ =
∂VBE R B + βR E
−β
⇒ S VBE =
R B + βR E
144 Basic Electronics
In voltage divider bias circuit :-
In self bias expressions, VCC is replaced by VTh & RB is replaced by RTh.
R Th
1+
So SI CO b g
= β +1
RE
R
β + 1 Th
RE
b g
R Th
1+
b
Sβ = I CO + I B g RE
b g R
β + 1 Th
RE

−β
S VBE =
R Th + βR E
R Th
Here as < <β + 1
RE
So SI CO ~ 1 i.e. independent of β.
So it is most stable.
In dc feedback bias circuit :-
The input KVL is

b g
VCC − I C + I B R C − I B R B − VBE − I C + I B R E = 0 b g
Differentiating w.r.t to IC with constant β & VBE,

0 − 1+
FG dI BIJ dI dI
RC − B RB − 1+ B RE = 0
FG IJ
H dI C K dI C dI C H K
⇒
dI B F R +R
= −G
IJ
HR +R +R K
C E
dI C B C E

β +1
SI CO =
So
1+ β
FG
RC + R E IJ
H
RB + RC + R E K
RB
1+
RC + R E
SI CO b g
= β +1
β +1 b g
RB
RC + RE
 145

RB
1+
RC + RE
b
Sβ = I CO + I B g
&
b g
β +1
RB
RC + R E

Example 6.25 : Fig 6.60 shows the circuit of fixed bias using a silicon transistor with
β = 100. Determine (i) base current, (ii) collector current (iii) VC, VB and VCB
(iv) operating point and (v) stability factor S.
Solution : VCC = 12V

IB IC

VCC − VBE 1,130 k RC = 4kΩ

Base current, IB= RB
Here VCC= 12 V, RB = 1, 130 × 103 Ω
B
VBE for silicon transistor = 0.7 V IE
12 − 0.7
(i) ΙΒ = − 10µ A Ans.
1,130 × 103 Fig. 6.60
(ii) Collector current, IC = βIB = 100 × 10 × 10–6 = 1 m A Ans.
(iii) Collector-emitter voltage,V CE = VCC – IC RC
= 12 – 1 × 10–3 × 4 × 103 = 8 V
Collector voltage, VC = VCE = 8 V Ans.
because VE = 0
Base voltage, VB = Base-emitter voltage, VBE = 0.7 V Ans
Collector-base voltage, VCB = VC – VB = 8 – 0.7 = 7.3 V Ans.
(iv) Operating point, Q = (VCE, IC) = (8 V, 1 m A) Ans.
(v) For fixed bias stability factor, S = β + 1 = 100 + 1 = 101 Ans.
Example 6.26 : In a fixed bias circuit using transistor with α = 0.97, the temperature changes
from 300C to 600C producing change in IC from 2.2 mA to 3.8 m A. Assume reverse
saturation current changes 1.7 µA/oC. What is stability factor ?
Solution :
Change in collector current, ∆IC = 3.8 – 2.2 = 1.6 m A or 1.6 × 10–3A
Change in temperature, ∆t = 60 – 30 = 30oC
Change in reverse saturation current for ∆t of 30oC
∆ICO = 30 × 1.7 × 10–6 = 51 × 10–6 A
∆I C 1.6 × 10 −3
Stability factor, S = = = 31.37 Ans.
∆I CO 51 × 10 −6
146 Basic Electronics
SHORT QUESTIONS & ANSWERS

Q.1 Explain why an ordinary junction transistor is called bipolar?

Ans. Because the transistor operation is carried out by two types of charge carriers (majority
and minority carriers), an ordinary transistor is called bipolar.
Q.2 What is done to the base region of a transistor to improve its operation ?
Ans. Base is made thin and very lightly doped in comparison to either emitter or collector so
that it may pass most of the injected charge carriers to the collector.
Q.3 Why transistor is called current controlled device ?
Ans. The output voltage, current or power is controlled by the input current in a transistor so it
is called the current controlled device.
Q.4 What is the significance of arrow head in the transistor symbol ?
Ans. Arrow head is always marked on the emitter. The direction indicates the conventional
direction of current flow (from emitter-to-base in case of P-N-P transistor and from base-
to-emitter in case of N-P-N transistor). Generally, no arrow head is marked for collector
since its reverse leakage current is always opposite to the direction of emitter current.
Q. 5. Why silicon type transistors are more often used than germanium type ?
Ans. Because silicon transistor has smaller cut-off current ICBO, small variations in ICBO due to
variations in temperature and high operating temperature as compared to those in case of
germanium type.
Q.6. Why collector is made larger than emitter and base ?
Ans. Collector is made physically larger than emitter and base because collector is to dissipate
much power.
Q. 7. Why the width of the base region of a transistor is kept very small compared to other
regions ?
Ans. Base region of a transistor is kept very small and very lightly doped so as to pass most of
the injected charge carriers to the collector..
Q.8 Why emitter is always forward biased ?
Ans. Emitter is always forward biased w.r.t. base so as to supply majority charge carriers to the
base.
Q.9 Why collector is always reverse-biased w.r.t. base ?
Ans. Collector is always reverse-biased w.r.t. base so as to remove the charge carriers away
from the base-collector junction.
Q.10 Can a transistor be obtained by connecting two semiconductor diodes back-to-back ?
Ans. No. Because in case of two discrete back-to-back connected diodes there are four doped
regions instead of three and there is nothing that resembles a thin base region between an
emitter and a collector.
 147

Q.11 What is αdc ?

Ans. αdc is the dc current gain and is equal -to the ratio of collector current to the emitter current.
Q.12 What is β ?
Ans. The beta factor (β) is the current gain factor of a common-emitter circuit and is defined as
the ratio of collector current and base current.
Q.13 How α and β are related to each other ?
Ans. α and β are related as below :

β α
α= or β =
1+ β 1− α
Q.14 Define beta of a transistor.
Ans. The β factor of a transistor is the common emitter current gain of that transistor and is
defined as the ratio of collector current to base current.
Q.15. What are the three configurations of a transistor amplifier?
Ans. The three configurations of a transistor amplifier are common-base, common-emitter and
common-collector configurations.
Q. 16. Why is there a maximum limit of collector supply voltage for a transistor ?
Ans. Although collector current is practically independent of collector supply voltage over the
transistor operating range, but if VCB is increased beyond a certain value collector current
Ic eventually increases rapidly and possibly destroys the device.
Q.17 For a PNP transistor in the active region what is the sign (positive or negative) of IE, Ic, IB,
VCB and VEB ?
Ans. Signs of IE, Ic, IB , VCB, and VEB for a PNP transistor are as follows :
Quantity Sign
IE Positive
IC Negative
IB Negative
VCB Negative
VEB Positive
Q.18 Explain why ICEO >> ICBO ?
Ans. The collector cut-off current denoted by ICEO is much larger than ICBO. ICEO is given as

1
I CEO = I CBO = (β + 1) I CBO
1− α
Because a is nearly equal to unity (slightly less than unity), ICBO >> ICBO .
Q.19 Why CE configuration is most popular in amplifier circuits ?
148 Basic Electronics
Ans. CE configuration is mainly used because its current, voltage and power gains are quite high
and the ratio of output impedance and input impedance arc quite moderate.
Q.20 Why is CC configuration seldom used ?
Ans. CC configuration is seldom used because its voltage gain is always less than unity.
Q.21 What are the main purposes for which a common collector amplifier may be used ?
Ans. For common collector configuration current gain is high (about 100) but voltage gain is less
than unity, input impedance is the highest and output impedance is the lowest. This circuit
finds wide application as a buffer amplifier between a high impedance source and a low
impedance load.
Q.22 Which configuration among CE, CB, CC gives highest input impedance and no voltage
gain ?
Ans. Common collector configuration has the highest input impedance and voltage gain less
than unity.
Q.23 Which of the configurations (CB, CE, CC) has the (i) highest Ri (ii) lowest Ri (iii) highest
R0 (iv) lowest R0 (v) lowest Ai
Ans. Characteristic Configuration
(i) Highest input resistance, Ri CC
(ii) lowest input resistance, Ri CB
(iii) Highest output resistance, R0 CB
(iv) Lowest output resistance, R0 CC
(v) Lowest current gain, Ai CB
Q.24 Explain base width modulation (Early effect).
Ans. The modulation of the effective base width by the collector voltage is known as Early
effect. An increase in collector voltage increases the space charge width at the ouput junction
diode and thus the effective base width Wb is reduced.
Q.25 What do you understand by collector reverse saturation ? In which configuration does it
have a greater value ?
Ans. When input current (IE in case of CB configuration and IB in case of CE configuration) is
zero, collector current Ic is not zero although it is very small. In fact this is the reverse
leakage current or collector reverse saturation current (ICBO or simply ICO in CB configuration
and ICEO in CE configuration). In case of CE configuration it is much more than that in
case of CB configuration.
Q.26 What is quiescent point ?
Ans. Quiescent point is a point on the dc load line which represents VCE and IC in the absence of
ac signal and variations in VCE and IC take place around this point when ac signal is applied.
Q. 27. What is transistor biasing ?
Ans. The proper flow of zero signal collector current and the maintenance of proper collector-
emitter voltage during the passage of signal is called the transistor biasing.
 149

Q.28 What is faithful amplification ?

Ans. The process of raising the strength of a weak signal without any change in its general
shape is referred to as faithful amplification.
Q.29. What is thermal runaway in transistor amplifier circuit?
Ans. The collector current Ic increases with the increase in temperature. This leads to increased
power dissipation. Being a cumulative process it can lead to thermal runaway resulting in
burn-out of the transistor.
Q.30. What is bias stabilization?
Ans. The maintenance of the operating or quiescent point stable (independent of temperature
variations or variations in transistor parameters) is known as bias stabilization.
Q.31. State the condition for thermal stability of operating point of a BJT amplifier.
Ans. The operating point should not shift with temperature variations.
Q. 32. What is meant by mid-point biasing ?
Ans. When an amplifier circuit is so designed that the operating point, Q lies at the centre of the
dc load line, the amplifier is said to be midpoint biased.
Q. 33. What is stability factor ?
Ans. Stability factor is defined as the rate of change of collector current Ic w.r.t. any one factor
of reverse saturation current Ico, VBE or β when other factors are constant.
Q. 34. Why a fixed bias circuit is not commonly used ?
Ans. Rise in temperature causes increase in leakage current Ico, increase in current amplification
factor β and decrease in base-emitter voltage VBE, so operating point is not stabilized. This
is the reason that fixed bias circuit is not commonly used.
Q. 35. Explain why collector-to/base bias circuit is seldom used?
Ans. The base resistor RB not only provides a dc feedback for the stabilization of the operating
point, but it also causes an ac feedback in a collector-to-base bias circuit. This is the reason
that this circuit is not much used.
Q. 36. What is an amplifier ?
Ans. The device that amplifies the amplitude of the input signal is called the amplifier. An
amplifier may be defined as a device that increases the current, voltage or power of an
input signal with the help of a transistor by furnishing the additional power from a separate
source of supply.
Q.37. What is meant by small signal amplifier ?
Ans. When the input signal is quite weak and produces small fluctuations in the output current
in comparison to its quiescent value, the amplifier is called the small signal or voltage
amplifier.
Q.38. What is meant by phase reversal ?
150 Basic Electronics
Ans. In a CE configuration, the output voltage increases in the negative direction when the input
signal voltage increases in the positive direction and vice-versa. This is called the phase
reversal and causes a phase difference of 180° between the input signal voltage and output
voltage.
Q.39 Explain how a BJT can be used as a switch.
Ans. A transistor can operate as a switch if it is simultaneously driven in saturation (closed
switch) and in cut-off (open switch) regions.

EXERCISE
1. The transistor has a collector current of 10 mA and a base current of 40 µA. What is the
current gain of the transistor ? [Ans: 250]
2. The transistor in C-E mode has a current gain of 175. If the base current is 0.1 mA, what is
the collector current ? [Ans: 17.5 mA]
3. The transistor in C-E mode has a collector current of 2 mA. If the current gain is 135, what
is the base current ? [Ans: 14.8 µA]
4. A transistor with α = 0.98 is operated in C-E mode. What is the maximum alternating
current gain ? [Ans: 49]
5. A given transistor has an α = 0.98. If the device is connected with its emitter grounded,
what will be the change in the collector current for a change of 0.2 mA in the base current?
[Ans: 9.8 mA]
6. A silicon n-p-n transistor with β = 100 and ICO 20 µA is connected in the C-E mode. Find
=

the collector current for a base current of 0.02 mA. [Ans: 2.002 mA]
7. In a transistor, β = 45, the voltage across RC = 5 kΩ is 5 V. Find the base current.
[Ans : 22 µA]
8. The C-E current gain of p-n-p transistor is 135. If reverse saturation current is 70 µA and
emitter collector current is 49.3 mA, calculate its base current and emitter current.
[Ans : 0.367 mA and 49.633 mA]
9. In a C-E configuration, the collector current increases from 4 mA to 4.02 mA when the
collector emitter voltage changes by 1 V. Calculate the output resistance. [Ans: 50 kΩ ]
10. In a C-E configuration the emitter current increases from 20 mA to 25 mA when base
emitter voltage changes by 0.2 V. Calculate the input resistance. [Ans: 40 Ω]
11. The cutoff current ICBO transistor is 14 µA at room temperature and its β = 50. Calculate the
collector current when base current is 0.2 mA. [ Ans 10.71 mA]
12. In C-B configuration using an n-p-n transistor base current is 100 µA and collector current
is 12.3 mA. Find the emitter current. [Ans: 12.4 mA]
 151

13. A transistor is connected in C-E configuration in which collector supply is 8 V and the
voltage drop across resistor RC = 800 Ω connected in the collector circuit is 0.5 V. If
α = 0.96, determine (a) collector-emitter voltage (b) base current.[Ans: 7.5 V, 0.026 mA]
14. A transistor has β =100 and ICBO = 5 µA. When it is connected in a circuit as a common-
emitter stage with zero load resistance, the collector current, IC = 1 mA. Calculate the values
of IB, IE, α and ICEO ? [Ans : 4.95 µA, 1.00475 mA, 0.99 and 500 µA]
15. In a C-E configuration the base current is 100 uA while the collector current is 20 mA.
Calculate the value of β. [Ans: 200]
16. The characteristics of a transistor indicate that with VCE = 5 V, the values of IC corresponding
to IB of 50 µA and 75 µA are 4.5 mA and 9.5 mA respectively. Calculate the values of a and
β. [Ans: 0.99 and 200]
17. In a C-C configuration, VBB = 10 V, RB = 100 kΩ What is the base current ? [Ans : 93 µA]
18. For a transistor IE = 1 mA, IB = 10 µA, determine α and β. [Ans : 0.99 and 99]
19. A transistor amplifier connected in C-E mode has β = 100, IB = 50 µA. Compute the values
of IC, IE and α. [Ans : 5 mA, 5.05 mA, 0.99]
20. A transistor has a = 0.9. If IE = 10 mA, find the values of β, γ, IB and IC.
[Ans : 9,10,1 mA, 9 mA]

21. In a fixed biasing circuit determine IB, IC and VCE if transistor

is of silicon, VCC = 10 V, RB = 2.5 Mn, RC = 15 kΩ and β = 90
[Ans. 3.72 µA; 0.335 m A; 4.978 V]

22. Design a self bias (emitter bias) circuit for a silicon transistor
having VBE = 0.6 V, β 0 = 99. Desired operating point VCB = 5 V
and IC = 1 mA. Assume VCC = 10 V, Rc = 3.0 kΩ and stability
factor S = 5.
[Ans. RE = 2 kΩ; R1 = 31.35 k Ω, R2 = 11.51 kΩ]
23. A CE amplifier with potential divider and emitter bias
arrangement employs an N-P-N transistor with p = 100. The
amplifier has the following specifications.
VBE = 500 mV,.VCC = 15 V, Rc = 4.5 kΩ.
It is required to have a stability factor of 4 at IC = 1.2 m A and VCE = 8 V. Calculate the values
of resistances RE, R1 and R2.
[Ans. RE =1.33 kΩ; R1 = 28.84 k Ω, R2 = 4.87 kΩ]
24. In a self bias circuit shown in fig. 1 a silicon transistor is used with β = 50, VBE = 0.6 V,
VCC=18 V and RC = 4.3 kΩ. It is desired to establish a quiescent point at IC = 1.5 m A, VCE =
10 V and a stability factor of S < 4. Find RE, R1 and R2.
[Ans. 1 kΩ; 26.3 kΩ; 3.7 kΩ]
25. Calculate the dc bias voltages and currents for the circuit
of fig 2.
[Ans. IB = 0.0204 mA; IC = 1.22 mA; IE = 1.243 mA;
VC = 5.888 V; VE = 1.243 V; VCE = 4.645 V]

26. Calculate the collector current and collector-to-emitter

voltage-of the circuit given in fig 3 assuming the following
circuit components and transistor specifications:
R1 = 40 kΩ, R2 = 4 kΩ, RC = 10 kΩ,
RE = 1.5 kΩ, VBE = 0.5 V, β = 40, VCC = 22V
[Ans. 0.92mA 11.39V]

27. A Ge transistor with β = 50 used in a self biasing circuit with VCC = 50 V, RC = 2 kΩ,
RE = 0.1kΩ, R1 = 100 kΩ, R2 = 100 kΩ. Find the quiescent current, the collector to emitter
voltage- and also the stability factor in this case.
[Ans. 22.4 mA, 2.96V, 46.4]
28. In a single stage CE amplifier, VCC = 20 V, β = 50, RE = 200 Ω, R1 = 60 kΩ, and R2 = 30 kΩ.
Determine the dc voltage across RE. [Ans. 2.02 V]
29. In a CE amplifier, the p-n-p transistor has the parameter β = 50 and V0 = 0.7 V. If the
collector load resistance is 10 kΩ, the emitter circuit resistance is 4.7 kΩ and the biasing
resistances are 27 kΩ and l0kΩ, determine the stability of the quiescent point. [Ans. 2.48]
30. For a collector feedback biasing circuit the collector resistance is 1 k Ω and the base resistance
is 90 kΩ. The transistor used is silicon one and has β = 90. If VCC is 15 V, determine Q-point.
[Ans. ICQ = 7.15 mA; VCEQ = 7.85 V]
ppp
Small Signal Operation of BJT
7
CHAPTER

7.1 INTRODUCTION
A model is the combination of circuit elements, properly chosen, that best approximates
the actual behaviour of transistor under specific operating conditions.
For the transistor, there are two types of models -
i) Hybrid model
ii) re-model
The detail will be discussed :-
7.2 TWO PORT NETWORK
A network that has two parts, input
& output port & current should enter I1 I2
to the network from both parts. It is + Two port +
specified by two voltages and two V1 Network V2
currents. – –
It has four terminals, one pair is used
for input & other pair is used for
output. Fig. 7.1
The transistor can be considered as two port network as it has one input port as well as one
output port.
The two port network can be represented in four ways :-
a) Z - Parameter model (Z → impedance)
b) Y - Parameter model (Y → Admittance)
c) ABCD or Transmission parameter model.
d) h - parameter mode (h → hybrid).
7.3 HYBRID MODEL OR H-PARAMETER MODEL
LMV OP = LMh
1 11 h12 OP LMI OP
1
In this model
NI Q N h
2 21 h 22 Q NV Q 2
154 Basic Electronics
Here V1 & I1 are input voltage & current,
and V2 & I2 are output voltage & current.
Now V1 = h11I1 + h12V2
& I2 = h21I1 + h22V2
V1
Here h11 = = Input impedance = hi
I1 V2 = 0

V1
h12 = = Reverse voltage gain = hr
I1 I1 = 0

I2
h 21 = = forward current gain = hf
I1 V2 = 0

I2
h 22 = = output admittance = h0
V2 V1 = 0

So V1 = hiI1 + hrV2
& I2 = hfI1 + h0V2
The model is -
I1 I2
+ hi +
+
V1 hr V 2 – 1/h0 V2
hfI1
– –

Fig. 7.2

In common base configuration

E C
+ Ie IC +
Veb V cb

– –
Hybrid model
Fig. 7.3
 155

e C
+ Ie h ib IC +
+
hrbV cb – 1/hob Vcb
– BfbIe
–
Ib b
Fig. 7.4

In common emitter configuration

b C IC
+ Ib hie IC + +
+ hfeIb
V be hreVce – 1/hoe V
ce

– – Ib Vce
e +
Fig. 7.5
(Hybrid model) V be
Ie
– –
Fig. 7.6
In common collector configuration

+
Ie b
Ib hic Ie +
Ib
+
Vec – 1/hoc
+ hrcVec
hfcIb
–
V bc C
IC
– –

Fig. 7.7 Fig. 7.8

156 Basic Electronics
Typical h - parameter values of BJT

Parameter CE CC CB
h11 = hi 1.1KΩ 1.1KΩ 21.6Ω
h12 = hr 2.5 × 10–4 ~1 2.9 × 10–4
h21 = hf 50 – 51 – 0.98

h 22 = h 0
1 1 40 KΩ 40KΩ 2MΩ

7.3.1 Approximate hybrid model for CE & CB, configuration of BJT.

For CE :
hre ~ 0
b C
+ Ib IC
So V be
hie hfeIb
– 1/hoe

Fig. 7.9

For CB :- hrb ~ 0 & 1/hob ~ ∞

+ Ie e C IC
Veb V cb +
– h ib hfb
So
–

Fig. 7.10
 157

7.4 ANALYSIS OF A TRANSISTOR AMPLIFIER CIRCUIT USING h

PARAMETERS
To form a transistor amplifier it is only necessary to connect an external load and signal
source as indicated in Fig. 7.11 and to bias the transistor properly. The two-port active
network of Fig. 7.11 represents a transistor in any one of the three possible configurations.
In Fig. 7.12 we treat the general case (connection not specified) by replacing the transistor
with its small-signal hybrid model. The circuit used in Fig. 7.12 is valid for any type of
load, whether it be a pure resistance, an impedance, or another transistor. This is true
because the transistor hybrid model was derived without, any regard to the external
I1 I2
RS 1 2
+
IL
+ Two-port
VS V1 active net- V2 ZL
– work
– (transistor)
1’ 2’
Zi Y0

Fig. 7.11 A basic amplifier circuit.

RS 1 I1 hi I2
2
+ + IL
+
VS hr V 2 h0 V2 ZL
– hfIi
– –
1’ 2’

Fig 7.12 the transistor in Fig. 7.11 is replaced by its h-parameter model.

circuit in which the transistor is incorporated. The only restriction is the requirement that
the h parameters remain substantially constant over the operating range.
Assuming sinusoidally varying voltages and currents, we can proceed with the analysis of
the circuit of Fig. 7.12, using the phasor (sinor) notation to represent the sinusoidally
varying quantities. The quantities of interest are the current gain, the input impedance,
the voltage gain, and the output impedance.
The Current Gain, or Current Amplification AI : For the transistor amplifier stage, AI
is defined as the ratio of output to input currents, or
158 Basic Electronics

IL I
AI = =− 2
I1 I1
From the circuit of Fig. 7.12, we have
I 2 = h f I1 + h 0 V2
Substituting V2 = – I2ZL , we obtain

I2 hf
AI = − =−
I1 1 + h0 ZL

The Input Impedance Zi : The resistance Rs in Figs. 7.11 and 7.12 represents the signal-
source resistance. The impedance we see looking into the amplifier input terminals (1, 1' )
is the amplifier input impedance Zi, or

V1
Zi ≡
I1
From the input circuit of Fig. 7.12, we have
V1 = h i I1 + h r V2
Hence

h i I1 + h r V2 V
Zi = = hi + hr 2
I1 I1
Substituting,

V2 = −I 2 Z L = A I I1Z L

we obtain

hf hr
Zi = h i + h r A I Z L = h i −
YL + h 0

The Voltage Gain, or Voltage Amplification AV : The ratio of output voltage V2 to input
voltage V1 gives the voltage gain of the transistor, or

V2
AV ≡
V1
we have
A I I1Z L A I Z L
AV = =
V1 Zi
 159

The Voltage Amplification A VS , Taking into Account the Resistance R8 of the Source :
This overall voltage gain A VS is defined by

V2 V2 V1 V
A VS ≡ = = AV 1
VS V1 VS VS

From the equivalent input circuit of the amplifier, shown in Fig. 7.13a,

VS Z i
V1 =
Zi + RS
Then

A V Zi A I ZL
A VS = =
Zi + R S Z i + R S

If RS = 0, then A VS = AV. Hence AV is the voltage gain for an ideal voltage source
(one with zero internal resistance). In practice, the quantity A VS is more meaningful than
AV since, usually, the source resistance as an appreciable effect on the overall voltage
amplification. For example, if Zi is resistive and equal in magnitude to RS, then A VS = 0.5
AV.

I1 I1
1 1

RS + +
+
VS Zi V1 IS RS Zi V1
–
– –
I’
(a) (b)
Fig 7.13 Input circuit of a transistor amplifier using (a) a Thevenin’s equivalent for the
source and (b) a Norton’s equivalent for the source.

The Current Amplification A IS Taking into Account the Source Resistance RS If the
input source is a current generator Is in parallel with a resistance RS, as indicated in
Fig. 7.13b, then this overall current gain A IS is defined by
160 Basic Electronics

− I 2 − I 2 I1 I
A IS = = = AI 1
Is I1 I s Is

From Fig. 7.13b

IsRs
I1 =
Zi + R s
and hence

AIRs
A Is =
Zi + R s

Note that, If Rs = ∞, then A I s = AI. Hence AI is the current gain for an ideal current
source (one with infinite source resistance).
Independent of the transistor characteristics, the voltage and current gains, taking
source impedance into account, are related by

ZL
A Vs = A IS
Rs
The Output Admittance : By Definition, the output impedance Z0 =1/Y0 is obtained by
setting the source voltage VS to zero and the load impedance ZL to infinity and by driving
the output terminals from a generator V2. If the current drawn fro V2 is I2, then

I2
Y0 =
V2 with Vs = 0 and RL = ∞
Using Equation I2 = hf I1 + hOV2

I1
Y0 = h f + h0
V2
From Fig. 7.12, with Vs = 0
RsI1 + hiI1 + hrV2 = 0
or

I1 hr
=−
V2 hi + R s
Substituting the expression for I1/V2, we obtain

hf hr
Y0 = h 0 −
hi + R s
 161

hf hf hr 1
AI = − Y0 = h 0 − =
1 + h0ZL h i + R s Z0
A V Zi A I ZL
Zi = h i + h r A I Z L A Vs = =
Zi + R s Zi + R s
A I ZL AIRs R
AV = A Is = = A Vs s
Zi Zi + R s ZL

7.5 STEPS FOR DRAWING SMALL SIGNAL MODEL

1) Setting all dc sources to zero and replacing them by a short-circuit equivalent

2) Replacing all capacitors by a short-circuit equivalent.

3) Removing all elements bypassed by the short-circuit equivalents introduced by steps

1 and 2.

4) Redrawing the network in a more convenient and logical form.

7.6 STEPS FOR ANALYSIS OF TRANSISTOR CIRCUIT

1) Draw the actual wiring diagram of the circuit neatly.

2) Mark the points B (base), C (collector), and E (emitter) on this circuit diagram. Locate
these points as the start of the equivalent circuit. Maintain the same relative positions
as in the original circuit.

3) Replace each transistor by its h-parameter model.

4) Transfer all circuit elements from the actual circuit to the equivalent circuit of the
amplifier.

5) Replace each independent dc source by its internal resistance. The ideal voltage source
is replaced by a short circuit, and the ideal current source by an open circuit.

6) Solve the resultant linear circuit for mesh or branch currents and node voltages by
applying Kirchhoff’s current and voltage laws (KCL and KVL).
7.7 re - TRANSISTOR MODEL
26mv
For any configuration re =
IE
162 Basic Electronics
7.7.1 Common base configuration

e c e Ie Ic c

IC= αIe

b b

Fig. 7.14 Fig. 7.15

The diode equivalent circuit consists of VT, re and an ideal diode.

For ac analysis dc source VT is made short circuited and as the diode is forward biased so
ideal diode is ON.
So the re model is,

e c

Ie IC

αI e
re
(For n-p-n Transistor)
b

Fig. 7.16

e c
Ie IC
re αI e
(For p-n-p Transistor)

Fig. 7.17
 163

7.7.2 Common emitter configuration

c c
Ic
c β Ib β Ib
b b b
Ib Ie
e re

e e
Fig. 7.18
Here Vbe = Iere = (β+ 1) Ibre

Zi =
Vbe
Ib
b g
= β + 1 re

~ βre
And Zo = ro (let)
So the re-model is :-

b c
Ib IC

βre
βI b ro

Ie (For n-p-n Transistor)

Fig. 7.19

b c
Ib Ic

βre β Ib r0

Ie
(For p-n-p Transistor)

Fig. 7.20
164 Basic Electronics
7.8 COMPARISON BETWEEN HYBRID MODEL & re - MODEL

h - parameter model re-model

I) It is the actual model I) It is the approximate model
II) It is identical for all types II) It is different for different
of configurations configurations.
III) Analysis is little bit complex III) It’s analysis is comparatively easier.
IV) It is useful at lower frequencies IV) It is useful for all frequencies.

7.9 BJT SMALL-SIGNAL ANALYSIS

Common-Emitter Fixed-Bias Configuration
VCC

RC C Vo
Io Ii Io
RB
Vo B
Ii Vi
B C2 RC
Vi Zo
C1 Zo Zi RB
E
Zi
E

Fig. 7.21 Fig 7.22

Ii Ib IC

+ Z C +
i Io
Vi
RB βre β Ib ro RC Vo
– –
Zo

Fig 7.23

Zi : Figure 7.23 clearly reveals that

Z i = R B ||βre ohms
 165

For the majority of situations RB is greater than βre by more than a factor of 10, it becomes
Z i ≅ βre ohms
R B ≥10βre

Z0: Recall that the output impedance of any

system is defined as the impedance Z0 determined Zo
when Vi = 0. For Fig 7.23, when Vi = 0, Ii = Ib = 0, ro RC
resulting in an open-circuit equivalence for the
current source. The result is the configuration of
Fig. 7.24
Fig. 7.24

Z o = R C || ro ohms
If r0 > 10 RC, the approximation RC || ro ≅ RC is frequently applied and
Zo ≅ R C
ro ≥10 R C

AV :The resistors r0 and RC are in parallel,

and V0 = – βIb (RC || r0)

Vi
but Ib =
βrC

V0 = −β
FG V IJ bR || r g
H βr K
i
so that C 0
e

and AV =
V
=−
0 bR || r g C 0
Vi re

If r0 > 10RC,

RC
AV = −
re r0 ≥10 R C

Ai : The current gain is determined in the following manner :

Applying the current-divider rule to the input and output circuits,

I0 =
br gbβI g
0 b
and
I0
=
r0β
r0 + R C I b r0 + R C
166 Basic Electronics

with Ib =
bR gbI g
B i
or
Ib
=
RB
R B + βre I i R B + βre

The result is

Ai =
Io I
= o
FG IJ FG I IJ = FG r β IJ FG R IJ
H K H I K H r + R K H R + βr K
b o B
Ii Ib i o C B e

Io βR B ro
Ai = =
and Ii b
ro + R C R B + βre gb g
which is certainly an unwidely, complex expression.
However, if r0 > 10RC and RB > 10βre, which is often the case,

I0 βR B r0
Ai = ≅
I i ( r0 )( R B )

and Ai ≅ β
r0 ≥10 R C , R B ≥10βre

Zi
and also Ai = AV
RC

Phase Relationship : The negative sign in the resulting equation for AV reveals that a
1800 phase shift occurs between the input and output signals, as shown in Fig. 7.25.

VCC
V0

Vi RC
RB
0 t
V0
0
t Vi

Figure 7.25 Demonstrating the 1800 phase shift between input and output waveforms
Example 7.1 : For the network of Fig. 7.26 :
(a) Determine re.
(b) Find Zi (with r0 = ∞Ω)
 167

(c) Calculate Z0 (with r0 = ∞Ω)

(d) Determine AV (with r0 = ∞Ω)
(e) Find Ai (with r0 = ∞Ω).
(f) Repeat parts (c) through (e) including r0 = 50 kΩ in all calculations and
compare results.

12 V
3 kΩ
I0
470 kΩ
V0
Ii
10 µF
Vi
10 µF Z0
β = 100
Zi r0 = 50 kΩ

Figure 7.26
Solution
(a) DC analysis :

VCC − VBE 12 V − 0.7 V

IB = = = 24.04 µA
RB 470 kΩ

b g b gb g
I E = β + 1 I B = 101 24.04 µA = 2.428 mA

26mV 26 mV
re = = = 10.71 kΩ
IE 2.428 mA
(b) βre = (100)(10.71Ω) = 1.071 kΩ
Zi = RB || βre = 470 kΩ || 1.071 kΩ = 1.069 kΩ
(c) Z0 = RC = 3kΩ

RC 3kΩ
(d) AV = − =− = −28011
.
re 10.71Ω
(e) Since RB > 10βre (470 kΩ >10.71 kΩ)
Ai ≅ β = 100
(f) Z0 = r0||RC = 50kΩ = 2.83 kΩ vs. 3kΩ

r0 || R C 2.83 kΩ
Av = − = = −264.24 , A VS = −28011
.
re 10.71Ω
168 Basic Electronics

βR B r0 (100)(470kΩ)(50kΩ)
Ai = =
b gb
r0 + R C R B + βre g
(50 kΩ + 3 kΩ)(470kΩ + 1071
. k Ω)

= 94.13 vs. 100

Z i −( −264.24)(1069
. kΩ)
Also A i = −A V = = 94.16
RC 3kΩ
which differs slightly only due to the accuracy carried through the calculations.
7.10 VOLTAGE-DIVIDER BIAS
VCC

I0

RC
R1
C V0
Ii
B C2
Vi
C1 Z0
E
Zi R2
RE CE

Fig. 7.27 Voltage-divider bias configuration

Substituting the re equivalent circuit will result in the network of Fig. 7.28. Note
the absence of RE due to the low-impedance shorting effect of the bypass capacitor, CE.
That is, at the frequency (or frequencies) of operation, the reactance of the capacitor is so
small compared to RE that it is treated as a short circuit across RE. When
Ii
b Ib c

+ +
I0
Zi
Vi R1 R2 βre β Ib r0 RC V0

– e e Z0 –

R’

Figure 7.28 Substituting the re equivalent circuit into the ac equivalent network of Fig. 7.27
 169

VCC is set to zero, it places one end of R1 and RC at ground potential as shown in Fig. 7.28.
In addition, note that R1 and R2 remain part of the input circuit while RC is part of the
output circuit. The parallel combination of R1 and R2 is defined by

R 1R 2
R ′ = R1 || R 2 =
R1 + R 2

Zi : From Fig. 7.28,

Z i = R ′||βre

Z0 : From Fig. 7.28 with Vi set to 0 V resulting in Ib = 0 µA and βIb = 0 mA,

Z 0 = R C || r0

If r0 > 10RC,

Z0 ≅ R C
r0 ≥10 R C

AV : Since RC and r0 are in parallel,

b gb
V0 = − βI b R C || r0 g
Vi
and Ib =
βre

V0 = −β
FG V IJ bR || r g
H βr K
i
so that C 0
e

V0 − R C || r0
and AV = =
Vi re

which is an exact duplicate of the equation obtained for the fixed-bias configuration.
For ro > 100RC.

V0 R C
AV = ≅
Vi re

Ai : Here
R ′ = R 1 || R 2 = R B , the equation for the current gain will be

I0 βR ′r0
Ai = =
Ii b
r0 + R C R ′ + βre gb g
170 Basic Electronics
For ro > 10RC.

I0 βR ′r0
Ai = ≅
b
I i r0 R ′ + βre g
I0 βR ′r0
Ai = ≅
and I i R ′ + βre r0 ≥10 R C

And if R ′ ≥ 10βre

I 0 βR ′
Ai = =
Ii R′

I0
and Ai = ≅β
Ii r0 ≥10 R C , R ′≥10βre

Again,

Zi
A i = −A v
RC

Phase relationship : The negative sign reveals a 1800 phase shift between V0 and Vi.
Example 7.2 :
For the network of Fig. 7.29 determine :
(a) re
(b) Zi
22V
(c) Z0 (r0 = ∞Ω).
(d) Av (r0 = ∞Ω).
I0
(e) Ai (r0 = ∞Ω).
6.8 kΩ
(f) The parameters of parts (b) through 56kΩ
V0
(e) if r0 = 1/hoe= 50kΩ and compare 10 µF 10 µF
Vi
results. β=90 Z0
Ii
8.2kΩ
Zi 1.5kΩ 20 µF

Fig. 7.29
 171

Solution :
(a) DC : Testing βRE > 10R2
(09)(1.5 kΩ) > 10 (8.2 kΩ)
135 kΩ > 82 kΩ (satisfied)
Using the approximate approach,

VB =
R2
VCC =
b g
(8.2 kΩ) 22. V
= 2.81 V
R1 + R 2 56kΩ + 8.2 kΩ
VE = VB – VBE = 2.81 V – 0.7 V = 2.11 V

VE 2.11 V
IE = = = 141
. mA
. kΩ
R E 15

26mV 26 mV
re = = = 18.44 Ω
IE 141
. mA

(b) b gb g
R ′ = R 1 || R 2 = 56kΩ || 8.2 kΩ = 7.15 kΩ

Z i = R ′||βre = 7.15k Ω + + ( 90)(18.14 Ω ) = 7.15 kΩ||1.66 kΩ

= 1.35Ω
(c) Z0 = RC = 6.8 kΩ

RC 6.8 kΩ
(d) AV = = = −368.76
re 18.44 Ω

(e) b
The condition R ′ ≥ 10βre 7.15kΩ ≥ 10 166 gb g
. kΩ = 16.6 kΩ is not satisfied.
Therefore,

Ai ≅
βR ′
=
b gb
90 7.15 kΩ g
= 73.04
R ′ + βre 7.15kΩ + 1.66 kΩ
(f) Zi = 1.35 kΩ
Z0 = RC || r0 = 6.8 kΩ || 50 kΩ = 5.98 kΩ vs. 6.8 kΩ
R C || r0 5.98 kΩ
Av = =− = −324.3 , A VS = −368.76
re 18.44 Ω

The condition
r0 > 10RC (50 kΩ > 10(6.8 kΩ) = 68 kΩ)
172 Basic Electronics
is not satisfied, Therefore,

Ai =
βR ′r0
=
b gb
90 7.15kΩ 50kΩ gb g
b gb g b
r0 + R C R ′ + βre gb
50 kΩ + 6.8 kΩ 7.15 kΩ + 166
. kΩ g
= 64.3 vs. 73.04
There was a measurable difference in the results for Z0, AV, and Ai because the
condition r0 > 10RC was not satisfied.
7.11 FREQUENCY RESPONSE OF BJT
Ø The plot of variation of gain w.r.t change in frequency is known as frequency response.
Ø The frequency response of RC coupled amplifier is as following -

| A V | A Vmax

A Vmax
2

Band Width

f1 f2
f
Low Mid frequences region High freq.
freq. region
region Fig. 7.30

Ø The gain increases as the frequency increases but after a particular frequency, gain
approximately remain constant for same range of frequency, after that, gain decreases
with increase in frequency.
Ø In a RC-coupled amplifier circuit, there are two types of capacitance :-
i) Visible capacitor (coupling & bypass capacitors)
ii) Invisible capacitors (wiring & parasitic or inter-junction capacitance)
Ø At lower frequency, the gain decreases as compared to mid-frequency gain because
of coupling & bypass capacitors.
Ø At higher frequency, the gain decreases as compared to mid frequency region because
of wiring and inter-junction - capacitance.
 173

Ø The frequency where the power is half of the maximum power is known as half
Power frequency or cut-off frequency.
Vmax 2
Let Pmax = maximum power =
R
V2
P = power of cut off freq =
R
At half power frequencies,

V 2 1 Vmax 2F I
Now =
R 2 R GH JK
Vmax
⇒ V=
2
Av max
⇒ AV = = 0.707 Av max
2
⇒ AV = 70.7% of maximum gain.
Ø The range of frequencies where gain is approximately remain constant i.e more than
70.7% of maximum gain is known as Band width (BW).
Here f1 = Lower cut off freq.
f2 = Higher cut off freq.
So BW = f2 – f1

SHORT QUESTIONS AND ANSWERS

Q. 1. What is the effect of source resistance on voltage gain of a common base transistor
amplifier ?
Ans. The voltage gain of a CB transistor amplifier will decrease if source resistance is considered
because in such a case there will be a voltage drop across the source resistance and output
voltage will decrease.
Q. 2. Explain what will happen to the voltage gain of an amplifier if the bypass capacitor is open-
circuited.
Ans. Removal of bypass capacitor causes excessive degeneration in the amplifier circuit i.e.
there is a voltage drop across RE and so the output is reduced. It means voltage gain will
reduce.
Q. 3. Why common-collector circuit is known as an emitter follower ?
Ans. The CC circuit amplifier is culled an emitter follower because in this circuit the output
voltage at the emitter terminal follows the input signal applied to the base terminal.
174 Basic Electronics
Q. 4. What are the main purposes for which a common-collector amplifier may be used ?
Ans. For a common collector amplifier, current gain is as high as for CE amplifier, voltage gain is
less than unity, input resistance is the highest and the output resistance is the lowest of all the
three (CE, CC and CB) configurations. This circuit finds wide application as a buffer
amplifier between a high impedance source and a low impedance load.
Q.5 What is bandwidth ?
Ans. It is the range of frequencies where gain of the amplifier remains above 70.7% of the
maximum gain.
If f1 = lower cut-off frequency &
f2 = higher cut-off frequency.
then Bandwidth = f2 – f1.

EXERCISE
1. The following test results were obtained in a CE amplifier circuit while measuring
h-parameters experimentally :
(i) With ac output shorted Ib = 25 µA, Ic = 1.2 mA, Vbe = 30 mV and Vce = 0
(ii) With ac input open-circuited Ib = 0, Ic = 32 µA, Vbe = 0.3 mV and Vce = 1.2 V
Determine hybrid parameters of the given transistor.
[Ans. hie = 1.2 kΩ; hfe = 48; hre = 2.5 × 10–4; hoe = 25 µS]
2. If hie = 1,500 Ω, hfe = 99, what is hib ? [Ans. 15 Ω]
3. If hie = 1,500 Ω, hfe = 99, what is hic? [Ans. 1,500 Ω]
4. Given hie = 2.4 kΩ, hfe = 100, hre = 4 × 10 and hoe = 25 µS. Sketch the common emitter
–4

equivalent model.

5. If hie = 2 kΩ, hfe = 80, hre = 10–4 and hoe = 10–5 mho, RS = RL = 1 kΩ. Calculate (i) Ai (int),
(ii) Ai (ext), (iii) Av (int), (iv) Av (ext) and (v) Ri.
[Ans. (i) – 79.2, (ii) 26.5, (iii) 39.76, (iv) 26.47, (v) 1.992Ω]
6. A BJT has the following h-parameters :
hie = 2,000Ω ; hre = 16 × l0–5; hfe = 49 and hoe = 50 µA/V.
Determine the current gain, voltage gain, input resistance and output resistance of the CE
amplifier if the load resistance is 30 k Ω. Neglect source resistance.
[Ans. Ai = –19.6, Av = – 308.5; Zin = 1,906 Ω; Zout = 21.7 kΩ]
 175

7. A common emitter transistor amplifier circuit has the following characteristics :

hie = 1,000 Ω ; hfe = 50, hre = 2.5 × 10–4, hoe = 25 × 10–6 A/V. If the load resistance RL = 10 kΩ
and source resistance is 100 Ω, find the input resistance, output resistance and the voltage,
current and power gains. [Ans. 10 kΩ; 73.33 kΩ; – 39.6, – 0.4, 1,600]
8. A transistor used in CE amplifier configuration has hie = 2 kΩ, hfe = 100, hre = 10–5 and
V0
hoe = 25 µ A/V. If Rs = 1 k Ω and RL = 1 k Ω, determine the voltage gain Avs = V current
S

10
gain Ais = 1 , input resistance Ri and output resistance, R0.
S

[Ans. Avs = – 32.5; Ais = – 32.5; 1.999 k Ω; 40.54 kΩ.]

9. A BJT having hie = 1,500 Ω, hfe = 100, hre = 2 × 10–5 and hoe = 25 × 10–6 A/V is used as an
emitter follower amplifier with Rs = 1,000 Ω and RL = 500 Ω. Determine for the amplifier
Vout V0 10
Avs = V , A vs = V , A is = 1 , R in and R out
in s s

[Ans. Av = 0.97, Avs = 0.952, Ais = 1.9, Rin = 51.376 kΩ, Rout = 24.74 kΩ]

ppp
176 Basic Electronics

Field Effect Transistor (FET)

8
CHAPTER

8.1 INTRODUCTION
So far we have discussed the circuit applications of ordinary transistors which are
also called bipolar junction transistor (BJT). These transistors are called bipolar junction
transistors because their operation relies on two types of charges i.e. holes and electrons.
The bipolar transistors are the backbone of linear electronics and are applied in most of
the linear applications. As bipolar transistors have low input impedance and considerable
noise level, therefore, in some of the applications unipolar transistors are better suited.
The operation of unipolar transistors depends upon only one type of charge i.e. either
holes or electrons.
There are two types of field-effect transistors namely the junction field effect transistors
(abbreviated as JFET or simply FET) and the insulated-gate field effect transistors (IGFET)
more commonly called the metal-oxide-semiconductor transistor (abbreviated MOST or
MOSFET). In this chapter, we shall focus our. attention on the construction, working and
circuit applications of these transistors.
8.2 DIFFERENCE BETWEEN BJT & FET
FET BJT
1) Voltage Controlled current source 1) Current controlled current source.
2) Unipolar device 2) Bipolar device
3) Requires less constructional area 3) Relatively larger area is required.
4) High input impedance 4) Low input impedance.
5) There is no offset voltage 5) It suffers from offset voltage problem.
6) Early effect and thermal run away 6) Early effect & thermal run away problems
problems are not observed are present.
7) Less noisy 7) more noisy.
8) Gain and width product is small 8) Gain bandwidth product is relatively more.
9) Less sensitive to the change in input 9) Highly sensitive to change in input signal.
signal
10) More temperature stability. 10) Less Temperature stability.
11) Low power rating 11) High power rating.
 177

8.3 POINTS ABOUT FETs

It is a type of transistor where current flow takes place due to strong electric field
created by a given supply.
It is a voltage controlled current device as the output current is controlled by input
supply voltage.
Ø Here current flow takes place due to majority carriers only (either electrons or holes).
So it is also known as unipolar transistor.
Ø Its input impedance is very high which is advantageous over BJT.
Ø It has more thermal stability as compared to BJT.
Ø It has three terminals like BJT :-
l Source analogous to emitter
l Gate analogous to base
l Drain analogous to collector.
Ø Between the gate regions and from source to drain, there is presence of channel.
Ø Depending on type of channel, FETs are of two types :-
n - channel & p - channel.
Ø In some FETs there is an extra terminal known as substrate.
Ø In n-channel type, source & drain are of n-type &
In p- channel type, source & drain are of p-type.
Ø Source & drain terminals are inter-changeable.
8.4 CLASSIFICATION OF FETs

FET

JFET MOSFET

n-channel DMOSFET
p-channel EMOSFET
D D
G G n-channel p-channel n-channel p-channel
S S D D D D
G ss G ss G ss G ss
S S S S

Here S → Source, G → Gate, D→ Drain, SS → Substrate.

178 Basic Electronics
8.5 JFETs
Ø It is a type of FET where junctions look like to be present.
Ø It may be of n-channel type or p-channel type.
Ø In n-channel, S & D are of n-type & G is of P-type.
Ø In p-channel, S & D are of p-type & G is of n-type.
8.5.1 Standard notations
Worthnoting FET notations are as follows :
1. Source. The terminal through which the majority carriers enter the channel, is called
the source terminal S and the conventional current entering the channel at S is
designated as IS.
2. Drain. The terminal, through which the majority carriers leave the channel, is called
the drain terminal D and the conventional current leaving the channel at D is designated
as ID.
The drain-to-source voltage is called VDS, and is positive if D is more positive than S.
3. Gate. There are two internally connected heavily doped impurity regions formed by
alloying, by diffusion, or by any other method available to create two P-N junctions.
These impurity regions are called the gate G. A voltage VGS is applied between the
gate and source in the direction to reverse-bias the P-N junction. Conventional current
entering the channel at G is designated as IG.
4. Channel. The region between the source and drain, sandwiched between-the two
gates is called the channel and the majority carriers move from source to drain through
this channel.
8.5.2 Operation
Ø For n-channel JFET, VDS is +v while VGS is +ve.
Ø For p-channel JFET, VDS is –ve while VGS is –ve.
Let us consider an N-channel JFET for discussing its operation.
(i) When neither any bias is applied to the gate (i.e. when VGS = 0) nor any voltage to the
drain w.r.t. source (i.e. when VDS = 0), the depletion regions around the P-N junctions
are of equal thickness and symmetrical.
D +VDD D +VDD
ID ID
N

G
G

N N

S S

JFET with No Bias Voltage JFET with Small Negative Gate

Fig. 8.1 Source Bias Fig. 8.2
 179

(ii) When positive voltage is applied to the drain terminal D w.r.t. source terminal S without
connecting gate terminal G to supply, as illustrated in fig. 8.1, the electrons (which are
the majority carriers) flow from terminal S to terminal D whereas conventional drain
current ID flows through the channel from D to S. Due to flow of this current, there is
a uniform voltage drop across the channel resistance as we move from terminal D to
terminal S. This voltage drop reverse biases the diode. The gate is more negative with
respect to those points in the channel which are nearer to D than to S. Hence, depletion
layers penetrate more deeply into the channel at points lying closer to D than to S.
Thus wedge-shaped depletion regions are formed, as shown in fig. 8.1, when VDS is
applied. The size of the depletion layer formed determines the width of the channel
and hence the magnitude of current ID flowing through the channel.
To see how the width of the channel varies with the variation in gate voltage, let
us consider the situation when the gate is biased negative with respect to the source while
the drain is applied with positive bias with respect to the source, as illustrated in fig. 8.2.
Now the P-N junctions are reverse biased and depletion regions are formed. P-regions are
heavily doped compared to the N-channel, so the depletion regions penetrate deeply into
the channel. Since a depletion region is a region depleted of the charge carriers, it behaves
as an insulator. The result is that the channel is narrowed, the resistance is increased and
drain current ID is reduced. If the negative voltage at the gate is further increased, depletion
layers meet at the centre and the drain current ID is cut-off completely. On the other hand,
if the negative bias to the gate is reduced, the width of the depletion layers gets reduced
causing decrease in resistance and, therefore, increase in drain current ID. The gate-source
voltage VGS at which drain current ID is cut-off completely (pinched off), is called the
pinch-off voltage VP. It is also to be noted that
1. The amount of reverse bias is not the same throughout the length of the P-N junction.
When the drain current flows through the channel, there is a voltage drop along its
length. The result is that the reverse bias at the drain end is more than that at the
source end making the width of depletion layer more at the drain end than that at the
source end. Thus the channel becomes narrower at the drain end in comparison to
that at source end, as shown in fig 8.2.
2. The channel is not completely closed at the drain end. Because in that case there will
be no drain current, so there will be no voltage drop along the channel length and
amount of reverse bias will become uniform and the wedge shaped depletion region
will become rectangular one. The channel will open and the drain current will flow.
However, at pinch-off voltage, the channel width is reduced to a constant minimum
value to allow the flow of drain current.
3. The N-channel JFET behaves as a vacuum tube triode. The drain and source perform
the same functions as the plate and cathode, respectively and, like the grid of a
triode, the JFET gate controls the drain current. As is also the case with a grid, gate
current is to be avoided, so the gate-channel junctions are normally never forward
biased.
180 Basic Electronics
The device is called the field-effect transistor (FET) because the drain current (output
current) is controlled by the effect of the extension of the field associated with the depletion
region developed by the reverse bias at the gate.
P-channel JFET operates in the same manner as an N-channel JFET except that
channel current carriers will be the holes in place of electrons and the polarities of V GS and
VDS are reversed.
8.6 CHARACTERISTICS OF JFETS
There are two types of static characteristics i.e
(1) Output or drain characteristic
(2) Transfer characteristic.
8.6.1 Output or Drain Characteristic
The curve drawn between drain current ID and drain-source voltage VDS with gate-to source
voltage Vgs as the parameter is called the drain or output characteristic. This characteristic
is analogous to collector characteristic of a BJT.
(a) Drain Characteristic With Shorted Gate. The circuit diagram for determining the
drain characteristic with shorted-gate for an N-channel JFET is given in fig. 8.3 (a) and
the drain characteristic with shorted-gate is shown in fig. 8.3 (b).
OHMIC REGION
CHANNEL

BREAK-
DOW N
PINCH-OFF OR REGION
ID
SATURATION REGION
DRAIN CURRENT ID IN mA

mA
IDSS B VGS = 0
PINCH-OFF POINT
D +
A KNEE POINT
C V DD
VDS V

VGS= 0 S –

VP VDS(MAX)

DRAIN-SOURCE VOLTAGE. VDS IN VOLTS

(a) Circuit Diagram For Determining
Drain Characteristics With Shorted Gate (b) JEFT Drain Characteristic With Shorted Gate
For An N-Channel JFET
Fig. 8.3
Initially when drain-source voltage VDS is zero, there is no attracting potential at
the drain, so no current flows inspite of the fact that the channel is fully open. This gives
drain current ID = 0. For small applied voltage VDS, the N-type bar acts as a simple
semiconductor resistor, and the drain current ID increases linearly with the increase in
VDS, upto the knee point. This region (to the left of the knee point) of the curve is called
the channel ohmic region, because in this region the FET behaves like an ordinary resistor.
With the increase in drain current ID, the ohmic voltage drop between the source
and channel region reverse-biases the gate junction. The reverse-biasing of the gate junction
 181

is not uniform throughout. The reverse-bias is more at the drain end than that at the source
end of the channel, so with the increase in the conducting portion of the channel begins to
construct more at the drain end. Eventually a voltage VDS is reached at which the channel
is pinched-off. The drain current ID no longer increases with the increase, in VDS. It
approaches a constant saturation value. The value of voltage V DS at which the channel is
pinched off (i.e. all the free charges from the channel get removed), is called the pinch-off
voltage VP. The pinch-off voltage VP, not too sharply defined on the curve, where the drain
current ID begins to level off and attains a constant value. From point A (knee point) to the
point B (pinch-off point) the drain current Ip increases with the increase in voltage V Dg
following a reverse square law. The region of the characteristic in which drain current ID
remains fairly constant is called the pinch-off region. It is also sometimes called the
saturation region or amplifier region. In this region the JFET operates as a constant current
device since drain current (or output current) remains almost constant. It is the normal
operating region of the JFET when used as an amplifier. The drain current in the pinch-off
region with VGS = 0 is referred to the drain-source saturation current, IDSS.
It is to be noted that in the pinch-off (or saturation) region the channel resistance
increases in proportion to increase in VDS and so keeps the drain current almost constant
and the reverse bias required by the gate-channel junction is supplied entirely by the
voltage drop across the channel resistance due to flow of IDSS and not by the external bias
because VGS = 0
Drain current in the pinch-of region is given by Shockley’s equation
FG1 − V IJ 2
F1 − V I 2

I D = I DSS
H VK
GS

P
= I DSS GH V JK
GS

GS ( OFF )

where ID is the drain current at a given gate-source voltage VGS, IDSS is the drain-current
with gate shorted to source and VGS (OFF) is gate-source cut-off voltage.
If drain-source voltage, VDS is continuously increased, a stage comes when the
gate-channel junction breaks down. At this point the drain current increases very rapidly,
and the JFET may be destroyed. This happens because the charge carriers making up the
saturation current at the gate channel junction accelerate to a high velocity and produce
an avalanche effect.
It will be very interesting to observe that JFET behaves as an ordinary resistor in
ohmic region, as a constant current source in pinch-off (or saturation) region and as a
constant voltage source in breakdown region Fig. 8.3(b).
(b) Drain Characteristics With External Bias. The circuit diagram for determining the
drain characteristics with different values of external bias is shown in Fig. 8.4(a) and a
family of drain characteristics for different values of gate-source voltage V GS is given in
Fig. 8.4(b).
182 Basic Electronics
It is observed that as the negative gate bias voltage is increased
(i) the maximum saturation drain current becomes smaller because the conducting
channel now becomes narrower.
(ii) Pinch-off voltage is reached at a lower value of drain current ID than when
VGS = 0.
When an external bias of say - 1 V is applied between the gate and the source, the
gate-channel junctions are reverse biased even when drain current, ID is zero. Hence the
depletion regions are already penetrating the channel to a certain extent when drain-source
voltage, VDS is zero. Due to this reason, a smaller voltage drop along the channel (i.e.
smaller than that for VGS = 0) will increase the depletion regions to the point where they
pinch-off the current. Consequently, the pinch-off voltage (Vp) is reached at a lower drain
current, ID when VGS = 0.
(iii) The ohmic region portion decreases.
(iv) Value of drain-source voltage VDS for the avalanche breakdown of the gate junction
is reduced.

GATE-CHANNEL
16 JUNCTION
ID BREAKDOW N
DRAIN CURRENT ID IN mA

PINCH-OFF
mA OR ACTIVE REGION
12
VGS = + 0.5 V
+
D VGS = 0 V
G 8
V DD
V DD V1
VGS = – 1 V
– 4
V2 VGS S VGS = 2 V
VGS = 3 V
VGS = VP = – 4V VDS (MAX)
4VP 8 12 16 20 24
DRAIN-SOURCE VOLTAGE, VDS, IN VOLTS
(a) Circuit Diagram For Determining Drain
(b) JFET Drain-Characteristics With External Bias
Characteristic With External Bias For An
N-Channel JFET Fig. 8.4

Value of drain-source voltage, VDS for breakdown with the increase in negative bias
voltage is reduced simply due to the fact that gate-source voltage, V GS keeps adding to the
reverse bias at the junction produced by current flow. Thus the maximum value of VDS that
can be applied to a FET is the lowest voltage which causes avalanche breakdown.
It is also observed that with VGS = 0, ID saturates at IDSS and the characteristic shows
Vp = 4 V. When an external bias of – 1 V is applied, the gate channel junctions still require
– 4 V to achieve pinch-off. It means that a 3 V drop is now required along the channel
instead of the previous 4.0 V. Obviously, this drop of 3 V can be achieved with a lower
 183

value of drain current. Similarly, when VGS = – 2 V and – 3 V, pinch-off is achieved with
2 V and 1 V respectively, along the channel. These drops of 2 V and 1 V are, of course,
achieved with further reduced values of drain current, ID. It is further observed that when
the gate-source bias is numerically equal to pinch-off voltage, V P (–4 V in this case), no
channel drop is required and, therefore, drain current, ID is zero. The gate-source bias
voltage required to reduce drain current, ID to zero is designated the gate-source cut-off
voltage, VGS (OFF) and as explained,
VGS(OFF) = VP
Hence for working of JFET in the pinch-off or active region it is necessary that the following
conditions be fulfilled.
VP < VDS < VDS ( MAX )
VGS( OFF ) < VGS < 0
0 < I D < I DSS
8.6.2 Transfer Characteristic
The transfer characteristic for a JFET can be determined experimentally, keeping drain-
source voltage, VDS constant and determining drain current, ID for various values of gate-
source voltage, VGS. The circuit diagram is shown in fig.8.4(a). The curve is plotted between
gate-source voltage, VGS and drain current, ID, as illustrated in fig. 8.5. It is similar to the
transconductance characteristic of a vacuum tube or a transistor. It is observed that
(i) drain current decreases with the

DRAIN CURRENT. ID IN mA
increase in - ve gate-source bias, IDSS 8

(ii) drain current, ID = IDSS when VGS = 0

6
(iii) drain current, ID = 0 when VGS = VP
The transfer characteristic follows the 4
equation

FG1 − V IJ 2
2

I D = I DSS
H VK
GS
VP
P
–4 –3 –2 –1
GATE-SOURCE VOLTAGE VGS IN VOLTS
JFET Transfer Characteristics
Fig. 8.5

The transfer characteristic can also be derived from the drain characteristic by
noting values of drain current, ID corresponding to various values of gate-source voltage,
VGS for a constant drain-source voltage and plotting them.
It may be noted that a P-channel JFET operates in the same way and have the
similar characteristics as an N-channel JFET except that channel carriers are holes instead
of electrons and the polarities of VGS and VDS are reversed.
184 Basic Electronics
8.7 MERITS AND DEMERITS OF JFETS
Junction field effect transistors combine several merits of both conventional (or bipolar)
transistors and vacuum tubes. Some of these are enumerated below :
1. Its operation depends upon the flow of majority carriers only. It is, therefore, a
unipolar (one type of carrier) device. On the other hand in an ordinary transistor
both majority and minority carriers take part in conduction and, therefore; ordinary
transistor is sometimes called the bipolar transistor. The vacuum tube is another
example of a unipolar device.
2. It is simpler to fabricate, smaller in size, rugged in construction and has longer life
and higher efficiency. Simpler to fabricate in IC form and space requirement is also
lesser.
3. It has high input impedance (of the order of 100 MΩ), because its input circuit (gate
to source) is reverse biased, and so permits high degree of isolation between the
input and output circuits. However, the input circuit of an ordinary transistor is
forward biased and, therefore, ordinary transistor has low input impedance.
4. It carries very small current because of reverse biased gate and, therefore, it operates
just like a vacuum tube where control grid (corresponding to gate in JFET) carries
extremely small current and input voltage controls the output current. This is the
reason that JFET is essentially a voltage driven device. Ordinary transistor is a
current operated device since input current controls the output current.
5. An ordinary transistor uses a current into its base for controlling a large current
between collector and emitter whereas in a JFET voltage on the gate (base) terminal
is used for controlling the drain current (current between drain and source). Thus an
ordinary transistor gain is characterised by current gain whereas the JFET gain is
characterised as the transconductance (the ratio of drain current and gate-source
voltage).
6. JFET has no junction like an ordinary transistor and the conduction is through bulk
material current carriers (N-type or P-type semiconductor material) that do not cross
junctions. Hence the inherent noise of tubes (owing to high temperature operation)
and that of ordinary transistors (owing to junction transitions) is not present in JFET.
7. It is relatively immune to radiation.
8. It has –ve temperature coefficient of resistance and, therefore, has better thermal
stability.
9. It has high power gain and, therefore, the necessity of employing driver stages is
eliminated.
10. It exhibits no offset voltage at zero drain current and, therefore, makes an excellent
signal chopper.
11. It has square-law characteristics and, therefore, it is very useful in the tuners of
radio and TV receivers.
12. It has got high frequency response.
 185

The main drawback of JFET is its relative small gain-bandwidth product in

comparison with that of a conventional transistor and greater susceptibility to damage
in its handling. Other disadvantages of JFET are low voltage gains because of small
transconductance and higher cost than that of BJTs.
8.8 JFET AS AN AMPLIFIER
One of the applications of JFET is an amplification of input signal.
In FET the weak signal is applied between gate arid source and an amplified output is
taken across the drain-source circuit having load, as shown in fig. 8.6, just as in a vacuum
tube where signal is connected between grid and cathode and output is taken across a load
connected in plate circuit.
For proper working of JFET it is necessary
that the gate is made negative w.r.t. source
(i.e. the input circuit is always reverse-
biased). This is achieved either by inserting
a battery VGS in the gate circuit with the
polarity shown in fig. 8.6 or by providing a
biasing circuit.

Fig. 8.6 JFET As An Amplifier

On application of an alternating weak signal, the fixed reverse bias of the gate changes
and a small change in reverse bias on the gate causes a large change in drain current owing
to change in width of the channel. This fact makes the JFET capable of amplifying the
strength of weak signals. During the positive half cycle of the input signal, the reverse
bias on the gate decreases causing increase in channel width and hence the drain current.
During the negative half cycle of the input signal, the reverse bias on the gate increases
causing drain current to decrease. The result is that the small change in voltage at the gate
produces a large change in the drain current. These large variations in drain current give
large output across the load RL and thus, JFET operates as an amplifier.
8.9 JFET PARAMETERS
JFET has certain parameters which determine the performance. Such parameters are
(i) ac drain resistance, (ii) transconductance, (iii) amplification factor, and (iv) dc drain
resistance, as explained below :
1. AC Drain Resistance. It is defined as the ratio of change in drain-source voltage to
change in drain current at constant gate-source voltage and is denoted by rd .

∆ VDS
i.e. AC drain resistance, rd = ∆ I at constant VGS
D

It is also called the dynamic drain resistance.

186 Basic Electronics
Referring to the output or drain characteristic shown in fig. 8.4(b), it is clear that in
the active region the change in drain current, ID is very small for change in drain-source
voltage, VDS because the characteristic curves are almost flat. Hence ac drain resistance of
a JFET is very large ranging from 10 kΩ to 1 MΩ.
2. Transconductance. The control that the gate-source voltage has over the drain current,
ID is measured by transconductance. It is denoted by gm. It may be defined as the ratio of
change in drain current to the change in gate-source voltage at constant drain-source voltage.

∆ ID
i.e. Transconductance, gm = ∆ I at constant VDS
GS

It is also called the forward transconductance (gfs ) or forward transadmittance (Yfs ).

It is measured in mA/volt or micro-siemens.
The transconductance measured at IDSS is denoted by gmo
Mathematical Expression For Transconductance.

Differentiating both sides of Shockley equation I D = I DSS

FG1 − V IJ 2

H VK
GS
, we get
P

d I D = 2 I DSS 1 −
FG VGSIJ FG − 1 IJ d V
H VP KH V K P
GS

d ID
= 2 I DSS
FG1 − V IJ FG − 1 IJ
H V KH V K
GS
or d VGS P P

gm = −
2 I DSS FG1 − V IJ
H VK
GS
or VP P

Substituting VGS = 0 in above expression, we get

2 I DSS
g mo = −
VP
So we have

FG
g m = g mo 1 −
VGS IJ
H VP K
3. Amplification Factor. It is defined as the ratio of change in drain-source voltage to the
change in gate-source voltage at constant drain current and is denoted by µ.

∆ VDS
i.e. Amplification factor, µ = ∆ V at constant ID
GS
 187

Amplification factor of a JFET indicates how much more control the gate-source
voltage has over drain current in comparison to the drain-source voltage.
∆ VDS ∆ VDS ∆ I D
Amplification factor, µ = ∆ V = ∆ I × ∆ V
GS D GS

⇒ µ = rd × g m = ac drain resistance × transconductance

Amplification factor µ of a FET may be as high as 100.
4. DC Drain Resistance. It is also called the static or ohmic resistance of the channel and
is defined as ratio of drain-source voltage and drain current. It is denoted by RDS
VDS
i.e., R D S = I
D

Example 8.1 : When a reverse voltage of 10 V is applied between gate and source of JFET the
gate current is 0.1 µA. Determine resistance between gate and source.
Solution : Gate-source voltage, VGS = 10.0 V
Gate current, IG = 0.1 µA = 1 × 10–7 A
VGS 10
Gate-to-source resistance, R GS = I = = 100 M Ω Ans.
G 1 × 10 −7
Example 8.2 : When drain-source voltage is changed by 1.5 volts, the change in drain current
is of 120 µA, the gate-source voltage remaining unchanged. Determine the ac drain
resistance of the JFET.
Solution :
Change in drain-source voltage, ∆ VDS = 1.5 V
–6
Change in drain-current, ∆ ID = 120 × 10 A
∆ VDS 15.
AC drain resistance of the JFET, rd = ∆ I = = 12.5 k Ω Ans
D 120 × 10 −6
Example 8.3 : In a JFET the drain current changes from 1.2 mA to 1.5 mA when the gate to
source voltage is varied from - 4.25 V to - 4.10 V, keeping the drain-source voltage
constant. Determine the transconductance for the given JFET.
Solution :
Change in drain current, ∆ ID = ID2 – ID1 = 1.5 – 1.2 = 0.3 m A
Change in gate-source voltage, ∆ VGS = VGS2 – VGSl = – 4.10 – (– 4.25) = 0.15 V
∆ ID 0.3 mA
Transconductance, gm = ∆ V = 015
. V
= 2 m A/V or 2,000 µ S Ans.
GS
188 Basic Electronics
Example 8.4 : A JFET has VP = – 4.5 V, IDSS = 10 m A and IDS = 2.5 m A. Determine the
transconductance.
Solution : Drain source saturation current, IDSS = 10 mA
Pinch-off voltage, VP = – 4.5 V
Drain-source current, IDS = 2.5 m A

From Shockley’s equation, drain-source current, I DS = I DSS

LM1 − V OP
GS
2

N VQ P

I DSLM 2.5 OP LM OP
or VGS = VP 1 − I = − 4.5 1 − = − 2.25 V
DSS MN 10 PQ N Q
So, transconductance,

gm =
−2I DSS VLM
1 − GS =
OP
−2 × 10 × 10 −3
1−
−2.25
= 2.22 m A/V
LM OP
VP N
VP −4.5 Q −4.5 N Q Ans.

Example 8.5 : For an N-channel JFET

IDSS = 8.7 mA; VP – 3 V; VGS = – 1 V
Find the values of (i) ID (ii) gmo (iii) gm
Solution : Drain-source saturation current,
IDSS = 8.7 m A = 0.0087 A
Pinch-off voltage, VP = – V
Gate-source voltage, VGS = – 1V

FG1 − V IJ 2
F −1I
= 0.0087 G 1 − J
2

H VK H −3K
GS
(i) Drain current, ID = IDSS = 3.8667 m.A Ans.
P

(ii) Transconductance for VGS = 0,

−2I DSS −2 × 8.7 mA

g mo = = = 5.8 m A/V or 5.8 m S Ans.
VP −3
(iii) Transconductance,

FG VGS IJ−1 FG IJ
g m = g mo 1 −
H VP
= 58
. 1−
K =
H K
−3 3.867 m A/V or 3.867 m S Ans.

Example 8.6 : An N-channel JFET has a pinch-off voltage of – 4.5 and IDSS = 9 m.A At what
value of VGS will IDS be equal to 3 mA ? What is its gm at this IDS ?
 189

Solution : Pinch-off voltage, VP = – 4.5 V

–3
Drain-source saturation current, IDSS = 9 m A = 9 × 10 A
–3
Drain-source current, IDS = 3 mA = 3 × 10 A
Using Shockley’s equation,

VGS = VP 1 −
LM I DS OP
= −4.5 × 1 −
LM
3 × 10 −3 OP
MN I DSS PQ MN
9 × 10 −3 PQ
= – 1.902 V Ans.
Transconductance gm for IDS = 3 mA for which VGS = – 1.902 V

gm =
−2 I DSS LM
V
1 − GS
OP
VP NVP Q
−2 × 9 × 10 −3 FG
−1902
. IJ
=
−4.5
1−
H
−4.5
= 2.31 m
K A/V or 2.31 m S Ans.

8.10 JFET BIASING

The input junction of JFET is reverse biased, so the input impedance is very high
b g
⇒ input or gate current I G ≅ 0 Amp .
So as compared to BJT, here is absence of feedback biasing but other three types of
biasings are present.
- Fixed biasing
- Self / source stabilized biasing
- Voltage divider biasing
8.10.1 Fixed biasing :- (Rs = 0)
V DD

RD

VO
CO
V1
I DSS
Ci RG given
VP
V GG

Fig. 8.7
190 Basic Electronics
V DD

During biasing analysis, the capacitors are RD

open circuited, in Fig. 8.7. D

So the circuit becomes as Fig. 8.8 IG ~ 0A +
By input KVL, V DS
RG +
− VGG − VGS = 0 V GS – –
V GG
S
⇒ VGS = − VGG

This equation is known as transfer line equation.

or Load line equation. Fig. 8.8
The value of ID can be determined by shockley’s equation :-

I D = I DSS
FG1 − V IJ 2

H VK
GS

= I DSS
FG1 − V IJ 2

H VK
GG

The Value of ID can also determined from graph by the intersection of transfer
characteristic curve and transfer line.
The transfer characteristic can be plotted by following table :-

b g
VGs Volt I D mAb g ID (mA)

0 I DSS IDSS
Device
0.3VP I DSS / 2 Network
0.5VP I DSS / 4
VP 0
Q-point
I DQ
The transfer line can be plotted using transfer
line equation,
VGS = –VGG
VP VGSQ = − VGG 0 VGS

Figure 8.9 Finding the solution for the

fixed-bias configuration
 191

By output KVL :
VDD – IDRD – VDS = 0
⇒ VDS = VDD – IDRD
Here VS = 0
VD = VDS + VS = VDD – IDRD
VG = VGS + VS = –VGG V DD
8.10.2 Self / Source Stabilized biasing
RD
Here RS is present. Even if not any
external biasing supply at input D
junction then also it is reverse biased. VO
So it is self biasing. CO
Vi
Ci G

RG S
RS

Fig. 8.10
VD

RD
Biasing analysis circuit is -
ID
+
+ V DS
V GS –
By input KVL, IG ~ OA – ID
RG
VGS = – IDRD RS
It is the transfer line/Load line equation.
Fig. 8.11
Analytical method :

The value of I D Q & VGSQ can be determined by putting value of VGS in shockley’ss
equation.

I D = I DSS
FG1 + I R IJ 2

H V K
D D

P
192 Basic Electronics

⇒ I 2D + K1ID + K2 = 0
Then by solving this equation, the value of ID ⇒ Value of VGS can be determined.
Graphical method :
Here transfer characteristic graph is first plotted by the table :-

b g
VGs Volt b g
I D mA
0 I DSS ID

0.3VP I DSS / 2 IDSS

0.5VP I DSS / 4
VP 0
Then transfer line is plotted by I DSS
transfer line VGS = –IDRD
2
Q-point

VGS ( V) I D ( mA ) 0
0 0
− I DSS R S / 2 I DSS / 2 Vp VGSQ 0 VGS
I D SS R S
VG S = −
2

Figure 8.12 Sketching the self-bias line.

By Output KVL

VDD – IDRD –VDS –IDRS = 0

⇒ VDS = VDD –ID (RD + RS)
Here VS = IDRS
V DD
VG = 0
VD = VDS + VS = VDD –IDRD
8.10.3 Voltage divider biasing : RD
R1
VO
Ø The capacitors Ci, Co and Cs CO
are open-circuited in biasing Vi
analysis. Ci
Ø It is called voltage divider
biasing, because the voltage R2
appeared across R 2 is the RS CS
voltage to the input of circuit.
Fig. 8.13
 193

Ø The biasing circuit becomes → VD

V DD
RD
RD
– R 2 VDD
IG ~ 0A RTh VTh =
R1 + R 2
R1 V DS
V CC R2
⇒ +
R Th = R 1 | | R 2
RS V GS –
VTh RS +

Fig. 8.14 Fig. 8.15

By input KVL :
VTh –VGS –IDRS = 0
⇒ VGS = VTh –IDRS
Transfer line equation
ID
VGS ( V) I D ( mA ) IDSS
VTh 0
0 VTh / R S

The transfer characteristic VGS=0V, ID=VG/RS

graph is plotted by the table- Q-Point
VGS=VG–IDRS
VGS ( V) I D ( mA )
0 I DSS
ID=0mA, VGS=VG
0.3Vp I D SS 2
0.5Vp I DSS 4 0
VP +VG VGS
Vp 0
Figure 8.16 Sketching the network equation for the
voltage-divider configuration.

From intersection point, I D Q & VGSQ are determined.

By output KVL
VDD – IDRD – VDS – IDRS = 0

⇒ VDS = VDD − I D (R D + R S )
194 Basic Electronics
Here VS = IDRS
VG = VGS + VS or VG = VTh – IGRS =VTh
VD = VDS + VS = VDD – IDRD
Example 8.7 :
Determine the following for the network of Fig. 8.17

(a) VGSQ
16 V
(b) I D Q
(c) VDS 2kΩ
(d) VD
(e) VG D

(f) VS G I DSS = 10mA

+
VGS
VP = 8A
1MΩ – S
–
2V
+

Figure 8.17
Solution :
Mathematical Approach :
(a) VGSQ = − VGG = −2 V

FG1 − V IJ 2
F −2V IJ
= 10 mA G1 −
2

(b) I DQ = I DSS
H VK H −8 V K
GS

= 10 mA (1– 0.25)2 = 10 mA (0.75)2 = 10 mA (0.5625)

= 5.625 mA
(c) VDS = VDD – IDRD = 16V – (5.625 mA)(2 kΩ)
= 16 V – 11.25 V = 4.75 V
(d) VD = VDS = 4.75 V
(e) VG = VGS = – 2 V
(f) VS = 0 V
 195

Graphical Approach
The resulting Shockley curve and the vertical line at VGS = – 2V are provided in Fig 8.18.
It is certainly difficult to read beyond the second place without significantly.

ID (mA)

IDSS =10 mA
9
8
7
6
Q-point ID = 5.6 mA
5 Q

4
3 I DSS
= 2.5 mA
2 4
1

–8 –7 –6 –5 –4 –3 –2 –1 VGS
Vp=–8V Vp
= −4 V V GS Q = − VGG = −2 V
2

Figure 8.18 Graphical solution for the network of Fig. 8.17

increasing the size of the figure, but a solution of 5.6 mA from the graph of Fig. 8.18 is
quite acceptable. Therefore
VGSQ = − VGG = −2 V

(b) I D Q = 5.6 mA
(c) VDS = VDD – IDRD = 16 V – (5.6 mA)(2 kΩ)
= 16 V – 11.2 V = 4.8 V
(d) VD = VDS = 4.8 V
(e) VG = VGS = – 2 V
(f) VS = 0V

The results clearly confirm the fact that the mathematical and graphical approaches
generate solutions that are quite close.
196 Basic Electronics
Example 8.8 :
Determine the following for the network of Fig. 8.19
20 V
(a) VGSQ

(b) I D Q ID
3.3 kΩ
(c)VDS
(d)VS D
(e)VG G
(f) VD IDSS= 8 mA
+ Vp = – 6 V
VGS
– S
1 MΩ
RS 1kΩ

Figure 8.19
(a) The gate-to-source voltage is determined by
VGS = – IDRS

VGS ( V) I D ( mA )
0 0 ID(mA)
4 4

The transfer characteristics curve can be plotted 8

by following table. 7
6
VGS ( V) I D ( mA )
5
0 8
4
−18
. 4
3
−3 2 Q-point IDQ =26
. mA
2
−6 0
1

–6 –5 –4 –3 –2 –1 VGS(V)
VGSQ = −2.6 V
Figure 8.20 Determining the Q-point for the
network for Fig. 8.19
 197

(b)At the quiescent point :

I D Q = 2.6 mA

(c) V DS = VDD – ID (RS + RD)

= 20 V – (2.6 mA)(1kΩ + 3.3 kΩ)
= 20 V – 11.18 V
= 8.82 V
(d) VS = IDRS
= (2.6 mA) (1kΩ)
= 2.6 V
(e) VG =0V
(f) VD = VDS + VS = 8.82 V + 2.6 V = 11.42 V
or VD = VDD – IDRD = 20 V – (2.6 mA)(3.3 kΩ) = 11.42 V
Example 8.9 :
Determine the following for the common-gate configuration of Fig. 8.21

(a) VGSQ . 12V

(b) I D Q .
(c) VD. 1.5Ω
(d) VG.
(e) VS. D V0
(f) VDS.
G I DSS = 12 mA
VP = −6 V 12 V
Vi ID
S

680Ω 1.5 kΩ

D
Fig. 8.21
G
Solution :
+
VGS
(a) The transfer characteristics and load – S
line appear in Fig. 8.23. In this case, the +
second point for the sketch of the load line VRS 680Ω
was determined by choosing (arbitrarily) ID –
= 6mA and solving for VGS. That is, Fig. 8.22
198 Basic Electronics
VGS = – IDRS = – (6 mA) (680 Ω) = – 4.08 V
as shown in Fig. 8.23. The device transfer curve was sketched using

I DSS 12 mA
ID = = = 3 mA
4 4
and the associated value of VGS.

VP 6V
VGS = =− = −3V
2 2
as shown on Fig 8.23 Using the resulting quiescent point of Fig. 8.23 results in
VGSQ ≅ −2.6 V

ID(mA)
12 IDSS
11
10
9
8
7
6
5
Q-point
4 I D Q ≅ 3.8 mA
3
2
1

–6 –5 –4 –3 –2 –1 0
VGSQ ≅ −2.6 V
Figure 8.23 Determining the Q-point for the network of Fig. 8.21
(b)From Fig. 8.23.
I D Q ≅ 3.8 mA

(c) VD = VDD – IDRD

= 12 V – (3.8 mA)(1.5 kΩ) = 12 V – 5.7 V
= 6.3 V
(d) VG =0V
(e) VS = IDRS = (3.8 mA)(680Ω)
= 2.58 V
 199

(f) V DS = VD – VS
= 6.3 V – 2.58 V
= 3.72 V
Example 8.10 :
Determine the following for the network of Fig. 8.24
(a)IDQ and VGS .
Q
(b)V D . +16 V

(c)V S.
(d)V DS . 2.1MΩ 2.4 kΩ
10 µF
(e)VDG. V0

Vi
5µF

270 kΩ
1.5 kΩ 20 µF

Solution Fig. 8.24

(a) For the transfer characteristics, if ID = IDSS/4 = 8 mA/4 = 2mA, then VGS = VP/2
= –4 V/2 = – 2V. The resulting curve representing shockley’s equation appears in
Fig. 8.25. The network equation in defined by I (mA) D

R 2 VDD 8 (IDSS)
VG =
R1 + R 2 7
6
(270 kΩ)(16 V)
= 5
2.1MΩ + 0.27 MΩ
4
= 1.82 V 3
IDQ = 2.4 mA
and VGS = VG − I D R S Q-point 2
ID = 1.21 mA (VGS = 0V)
= 1.82 V – ID (1.5 kΩ) 1

–4 –3 –2 –1 0 1 2 3
(VP) VGSQ=–1.8 V VG=1.82 V
(ID= 0 mA)

Figure 8.25 Determining the Q-point for the network of Fig.

200 Basic Electronics
8.24
When ID = 0 mA :
VGS = + 1.82 V
When VGS = 0 V;
182
. V
ID = = 121
. mA
. kΩ
15
The resulting bias line appears of Fig. 8.25 with quiescent values of
ID = 2.4 mA
Q
VGS = – 1.8 V
Q
and
(b) VD = VDD – 1DRD
= 16 V – (2.4 mA)(2.4 kΩ)
= 10.24 V
(c) VS = IDRS = (2.4mA)(1.5 kΩ)
= 3.6 V
(d) VDS= VDD – ID (RD + RS)
= 16 V – (2.4 mA)(2.4 kΩ + 1.5 kΩ)
= 6.64 V
or VDS = VD – VS = 10.24 V – 3.6 V
= 6.64 V
(e) Although seldom requested, the voltage VDG can easily be determined using
VDG = VD – VG
= 10.24 V – 1.82 V
= 8.42 V VDD=20V
Example 8.11 : Determine the following for ID
the network of Fig. 8.26. RD = 1.8 kΩ
(a) ID and VGS .
Q Q
(b) VDS.
IDSS = 9 mA
(c) VD.
VP = – 3V
(d) VS.
RS = 1.5 k

VSS = –10 V
Fig. 8.26
 201

Solution :
(a) An equation for VGS in terms of ID is obtained by applying Kirchhoff’s voltage law
to the input section of the network as redrawn in Fig. 8.27.
– VGS – ISRS + VSS = 0
or VGS = VSS – ISRS
G
but IS = ID
+ IS
and VGS = VSS − I D R S VGS
–
Here VGS = 10 V – ID (1.5 kΩ) +
RS = 1.5 k Ω
For ID = 0 mA –
–
VGS = VSS = 10 V VSS = 10 V
+
For VGS = 0 V
0 = 10 V – ID (1.5 kΩ)
Fig. 8.27 Determining the network
equation for the configuration of
Fig. 8.26.
10V
and ID = = 6.67 mA
. kΩ
15
The resulting plot points are identified on Fig. 8.28.

ID (mA)

9 (IDSS)
8
Q-point 7 ID = 6.9 mA
Q

6
5
4
3
2
1

VGS
–3 –2 –1 0 1 2 3 4 5 6 7 8 9 10
(VP) VGS = – 0.35 V VSS = 10V

Fig. 8.28
202 Basic Electronics
The transfer characteristics are sketched using the plot point established by V GS = VP/2 =
– 3 V/2 = – 1.5 V and ID = IDSS/4 = 9 mA/4 = 2.25 mA, as also appearing on Fg. 8.28. The
resulting operating point establishes the following quiescent levels.
ID = 6.9 mA
Q
VGSQ = – 0.35 V
(b)Applying Kirchhoff’s voltage law to the output side of Fig. 8.26 will result in
–VSS + ISRS + VDS + IDRD – VDD = 0
Substituting IS = ID and rearranging gives.
VDS = VDD + VSS − I D ( R D + R S )
In this case,
VDS = 20 V + 10 V – (6.9 mA)(1.8 kΩ + 1.5 kΩ)
= 30 V – 22.77 V
= 7.23 V
(c) VD = VDD – IDRD
= 20 V – (6.9 mA)(1.8 kΩ) = 20 V – 1.242 V
= 7.58 V
(d) VDS = VD – VS
or VS = VD – VDS
= 7.58 V – 7.23
= 0.35 V
Example 8.12 :
Determine IDQ, VGS , and VDS for he p-channel JFET of Fig. 8.29.
Q

–20 V
ID

68 k Ω 2.7 k Ω

D
+
G
IDSS = 9mA
VDS
+ VP = 4V
VGS –
–
S
20 k Ω
1.8 k Ω

– IS
+

Figure - 8.29
 203

Solution :

20kΩ( −20V)
VG = = −4.55 V
20kΩ + 68 kΩ
Applying Kirchhoff’s voltage law gives

VG – VGS + IDRS = 0
and VGS = VG + IDRS
Choosing ID = 0mA yields
VGS = VG = – 4.55 V
as appearing in Fig. 8.30 ID (mA)
Choosing VGS = 0 V, we obtain 8
7
V −4.55V
ID = G = − = 2.53 mA 6
RS . kΩ
18 5
as also appearing in Fig. 8.30. 4
ID =3.4 mA 3
The resulting quiescent point Q Q-point
2
from Fig. 8.30 :
1
IDQ = 3.4 mA
VGSQ = 1.4 V –5 –4 –3 –2 –1 0 1 2 3 4
VP VGS
VGSQ=1.4 V
For VDS, Kirchhoff’s voltage law will result in Fig. 8.30
– IDRS + VDS– IDRD + VDD = 0
and VDS = – VDD + ID (RD + RS)
20V
= –20V + (3.4 mA)(2.7 kΩ +1.8 kΩ)
= – 20 V + 15.3 V 2.2KΩ
= – 4.7 V
D
Example 8.13 :
G IDSS = 4.5 mA
1) Find ID, VDS, VD & VS, in this Fig.8.31
VP = –5V

Solution : VGS = VG – VS = 0 S
(Because of short circuit) 0.68 KΩ

FG1 − V IJ 2

H VK
GS
So ID = IDSS Fig. 8.31
P
204 Basic Electronics
= 4.5 (1 –0)
⇒ ID = 4.5 mA
VD = 20 – 2.2 × 4.5 = 10.1 V
VS = 0.68 × 2.5 = 3.06V
Example 8.14 : Define IDSS & VP ?
Solution :
IDSS is the maximum drain to source saturation current flows when gate to source
voltage is zero.
VP (Pinch-off voltage) is the value of gate to source voltage when drain current
becomes zero.
VP = +ve For p - channel FET 18V
VP = –ve For n-channel FET
2KΩ
750KΩ
D 9V
Example 8.15 : Find ID, VS, VG, VP in Fig.8.32 G
IDSS = 8mA

91 S
Solution : Here VTh = × 18 91KΩ
91 + 750 0.68 KΩ
= 1.95 V
VG = VTh (Q IG ~ 0 A)
⇒ VG = 1.95V Fig. 8.32
VD = 18 – 2ID
⇒ 9 = 18 – 2ID ⇒ ID = 4.5 mA 18V
VS = 0.68 × 4.5
= 3.06 V 2KΩ

I D = I DSS
FG1 − V IJ 2

⇒ 1−
VGS
=
ID IG ~ 0A
D
9V
H VK
GS

P
VP I DSS
RTh G
ID 4.5
⇒ VGS VP = 1 + = 1+ = 101236
. VTh S
I DSS 8
0.68kΩ
1.95 − 3.06
⇒ VP = VGS VP = = −0.9 Volt
1236
. Fig. 8.33
 205

8.11 FET SMALL SIGNAL MODEL

In a FET, instantaneous drain current iD is a function of the instantaneous gate-source
voltage VGS and instantaneous drain-source voltage VDS and is therefore, expressed as
iD = f (vGS , VDS )
If both the gate and drain voltages are varied, the change in drain current is given
approximately by the first two terms in the Taylor’s series expansion,

δ iD δ iD
∆ iD = ∆ v GS = ∆ v DS
δ v GS VDS
δ v DS VGS

Using the conventional small signal notations, ∆iD, ∆VGS and ∆ vDS may be replaced
respectively by time varying components id , vgs and vds. Now,

1
i d = g m v gs + v ds
rd

δ iD ∆ iD id
where g m = ~ =
δv GS VDS
∆ v GS VDS
v gs
VDS

Parameter gm is the mutual conductance, or transconductance

1 δ iD ∆ iD id
and r = δv ~
∆ v GS
=
v gs
d GS VDS VDS VDS

The reciprocal of rd is the drain conductance gd .

Circuit shown in fig. 8.34 shows drain current id in form of gm , rd , vgs and vds . This circuit
forms the low frequency small signal model for FET: This model consists of one dependent
current generator whose current gm vgs is proportional to the time varying gate source
voltage vgs and proportionality constant is the transconductance gm. Small signal model
for sinusoidal input voltage of rms value Vgs may be drawn, as shown in fig. 8.35 where vgs
, id , vds have been replaced respectively by rms values Vgs, Id and Vds.
GATE, G DRAIN
G Id
+D +D
id

Vgs rd v ds Vgs rd Vds

gmVgs
g mv gs

S S
SOURCE, S S
Low Frequency Small Signal Low Frequency Small Signal Model For
Model For FET Sinusoidal Input of FET
Fig. 8.34 Fig. 8.35
206 Basic Electronics
8.12 COMPARISON OF LOW FREQUENCY MODELS OF FET AND BJT
1. Both FET and BJT models have a dependent current generator in the output circuit.
2. In FET models, the generator current is proportional to the input voltage Vgs while in
BJT models, the generator current is proportional to the input current.
3. In FET models input impedance is very high (theoretically infinite at low frequencies)
while in common emitter BJT model the input impedance is of the order of 800 Ω.
4. In FET, there is no feedback from output (drain) to the input (source) while in BJT
models it is. Thus it can be safely said that at low frequencies, FET forms a more
ideal amplifier than BJT amplifier.
8.13 COMMON SOURCE JFET AMPLIFIER
The circuit of a common source
N-channel JFET amplifier using self I +V
d DD

bias is shown in fig 8.36. The signal

R
source, Vin is connected to JFET gate C
D

2
through coupling capacitor C1 and V out

external load RL is connected to the C

SIGNAL 1
G –
drain terminal D via coupling
capacitor C2. RG is used to provide V in V gs
S
R L
EXTERNAL
leakage path to the gate current, RS LOAD
for developing gate bias and CS for R G
R C
S S

providing ac ground to the input

signal. Note that the polarity of the
capacitors in fig.8.36 the negative Fig- 8.36 : Common Source Amplifier Circuit
terminal of each (polarized) capacitor
must always be at a lower dc potential than the positive terminal. Incorrectly connected
capacitors can affect the bias conditions and ac performance of the circuit.
For ac considerations, bypass capacitor CS effectively ties the FET source terminal
to the ground level. Thus, all of the input voltage Vin is developed across the gate source
terminals. With the increase or decrease in input voltage, gate-source voltage V gs changes
and corresponding change in Vgs makes the drain current Id to increase or decrease
correspondingly.
The phase relationship between G I Dd
the circuit input and output voltages
can be determined by considering the
effect of a positive going input signal, Vin RG rd RD RL Vout
When input voltage Vin increases in –gmViin

positive direction, it reduces the

negative gate-source voltage - Vgs. The S

reduction in –Vgs raises the level of Fig. 8.37 : AC Equivalent Circuit For Common
drain current Id and consequently Source JFET Amplifier
 207

increases the voltage drop across drain resistance RD Since Vd = VDD – Id RD, the increase
in Id results in a drop in drain (output) voltage Vd. Thus as Vin increases in a positive
direction, Vout goes in a negative direction, Similarly when Vin goes negative, the resultant
increase in - V reduces the drain current Id which, in turn, reduces the voltage drop across
Rp and develops a positive going output voltage Vout. Thus, the amplifier output voltage is
180° out of phase with the input voltage.
Analysis. The first step in ac analysis of the common source circuit is to draw the ac
equivalent circuit. This is done by replacing all the capacitors with short circuits and
reducing dc supply voltages to zero. AC equivalent circuit for common source amplifier
is given in fig 8.37.
Input Resistance. In an ideal JFET Rgs is infinite because IG = 0 However, in actual
device R is not infinite but extremely high (100 MW or so) in comparison to RG. Thus
input resistance
Rin ~ RG
Output Resistance. Looking into the drain and source terminals, the large drain
resistance rd is seen Thus, Zd ~ rd
Zd is the device output impedance; the circuit output impedance is RD in parallel with
Zd so
Zout = RD || Zd = RD || rd
Since usually rd >> RD, the circuit output impedance is taken to be RD.
Voltage Gain. Output voltage, Vout = Id (rd || RD || RL)
and voltage gain, Av= – gm Vin (rd || RD || RL)
usually rd >> RD || RL
So voltage gain, Ay = – gm (RD || RD)
The minus sign indicates that output voltage Vout is 180° out of phase with input
voltage Vin.
Example 8.16 : The transconductance of a FET used in a voltage-amplifier circuit is 2,500
micro-siemens and the load resistance is 12 k Ω. Determine the voltage gain of the
amplifier circuit. Assume rd and RD >> RL.
Solution : Transconductance, gm = 2,500 µ S = 2,500 × 10–6 S
Load resistance, RL = 12 k Ω = 12,000 Ω .
Voltage gain, Av = – gm × [rd || RD || RD]
Since rd and RD are very large in comparison to RL
∴ Voltage gain, Av = – gm RL = – 2,500 × 10–6 × 12,000 = – 30 Ans.
Example 8.17 : The transconductance of a FET used in a voltage circuit is 4,000 micro-
siemens. The load resistance is 15 kΩ and drain circuit resistance is 10 MΩ. Calculate
the voltage gain of the amplifier circuit.
208 Basic Electronics
Solution : Transconductance, gm = 4,000 S = 4 × 10–3 S
Load resistance, RL = 15 kΩ = 15,000 Ω
Drain circuit resistance, RD = 10 M Ω
Assuming ac drain resistance, rd > > RD || RL

RDRL 10 × 10 6 × 15,000
Voltage gain, A = − g m = −4 × 10 −3 × = −59.9 Ans.
RD + RL 10 × 10 6 + 15,000
Example 8.18 : It is desired to operate the JFET shown in fig. 8.38 at VGS = – 1.0 V, VDS = 4.0
V and IDS = 1 mA.
Determine for the circuit (i) the values of RD and RS; (ii) the voltage gain
Vo
AV = ; (iii) Ri and RO. Assume for JFET gm = 5 m mhos and Rds = 20 kΩ .
Vi
Solution : Capacitors act as short-circuited for ac signals in the given self bias FET amplifiers.
Current in 500 kΩ is insignificant in the input loop of the gate.
From the dc equivalent circuit,
VGS = IDS RS

VGS −10.
or R S = I = = 1k Ω Ans.
DS 1 × 10 −3
Applying Kirchoffs voltage law to the
output loop we have
VDD = IDSRD + VDS + IDSRS
= IDS (RS + RD) + VDS
Fig. 8.38
VDD − VDS 10 − 4
∴ R D + RS = = = 6 kΩ
I DS 1 × 10 −3
R = 6 – 1 = 5 kΩ Ans.
D

Vout
(ii) Voltage gain A V = V = – gm (rd || RD || RL ) = – gm (RD || Rds)
in

Q rd > > RD || Rds

–3 3
= – 5 × 10 × (5 || 20) × 10 = – 20 Ans.
(iii) Input impedance Rin = RG = kΩ Ans.

1
Output impedance, Rout = RG || Rds = 5 || 20 = = 4 kΩ
1 1
+ Fig. 8.39
5 20
 209

SHORT QUESTIONS AND ANSWERS

Q.1 Why are field-effect transistors called unipolar transistors ?

Ans. In field-effect transistors current conduction is by only one type of majority carriers (either
by electrons or by holes) and, therefore, these are called unipolar transistors.
Q.2 Why the channel of a JFET is never completely closed at the drain end ?
Ans. If the channel is completely closed in JFET, then there will be no drain current, so there
will be no voltage drop along the channel length and amount of reverse bias will become
uniform and wedge-shaped depletion region will become rectangular one.
Q.3 How is drain current controlled in a JFET ?
Ans. In a JFET drain current is controlled by controlling the reverse bias given to its gate (i.e.
VGS).
Q.4 What is meant by drain characteristic of FETs ?
Ans. The curve drawn between drain current and drain-source voltage with gate-to-source voltage
as the parameter is called the drain characteristic.
Q.5 What is meant by transfer characteristic of FETs ?
Ans. The curve drawn between drain current and gate-source voltage for a given value of drain-
source voltage is called the transfer characteristic.
Q.6 No current flows through the channel of a JFET when VGS = 0 and VDS = 0, though channel
is fully-open. Why ?
Ans. When drain-source voltage is zero, there is no attracting potential at the drain, so no current
flows inspite of the fact that the channel is fully open.
Q.7 Define pinch-off voltage for a JFET
Ans. The value of drain-source voltage at which channel is pinched-off (i.e. all the free charges
from the channel get removed) is called the pinch-off voltage.
Q.8 What are the parameters that control the pinch-off voltage of JFET ?
Ans. Parameters that control the pinch-off voltage of JFET are electron charge, donor/acceptor
concentration density, permittivity of channel material and half width of channel bar.
Q.9 Why FET is called a voltage controlled device ?
Ans. In a FET, drain current is controlled by the effect of the extension of the field associated
with the depletion region developed by the reverse bias on the gate, so it is called a voltage
controlled device.
Q.10 How does the FET behave (i) for small values of |VDS| and (ii) for large values of |VDS| ?
Ans. (i) FET behaves us an ordinary resistor for small value of |VDS| i.e. in ohmic region.
(ii) FET behaves as a constant current source for large values of |V DS| till breakdown
occurs.
210 Basic Electronics
Q.11. How does the current vary with the gate voltage in the saturation region ?
Ans. Drain current decreases with the increase in gate-source bias |V DS|. When VGS = 0; drain
current ID = IDSS, drain-source saturation current and when VGS = Vp; drain current ID = 0.
Q.12. How does the transconductance vary with drain current ?
Ans. Transconductance gm of a FET varies with the drain current ID as given by the following
equation.

2
gm = I DS.I DSS
| VP |
Q.13. What is meant by gate-source cut-off voltage ?
Ans. The gate-source bias voltage required to reduce the drain current to zero is designated
the gate-source cut-off voltage VGS (OFF) . It is equal to pinch-off voltage Vp.
Q.14 What is meant by saturation region ?
Ans. The region of drain characteristic of a FET in which, drain current remains fairly constant
is called the saturation or pinch-off region.
Q.15 What is meant by drain-source saturation current IDSS ?
Ans. The drain current in pinch-off or saturation region with zero gate-source voltage (V GS = 0)
is referred to the drain-source saturation current IDSS .
Q.16 Why is input impedance of the FET very high ?
Ans. FET has very high input impedance because its input circuit (gate-to-source) is reverse
biased and the input gate current is very small (of the order of few nano-amperes).
Q.17 What is the value of gate-source voltage VGS that gives drain current of both N-and P-
channel JFETs a zero temperature coefficient ?
Ans. |VGS| ~ |Vp| – 0.63 V.
Q.18 What is dynamic resistance of a JFET ?
Ans. The ratio of change in drain-source voltage to change in drain current at a given gate-
source voltage is known as ac drain resistance or dynamic resistance rd

∆ VDS
i. e. rd =
∆ I D at constant VGS.
Q.19 What is meant by transconductance with reference to JFET ?
Ans. The control that gate-source voltage has over the drain current is measured by the
transconductance of a JFET. It may be defined as the ratio of change in drain current to the
change in gate-source voltage for a given value of drain-source voltage i.e.

∆ ID
gm =
∆ VGS at constant VDS.
 211

Q.20 Name the factors which make the JFET superior to BJT ?
Ans. The high input impedance, low output impedance and low noise level make JFET far
superior to the BJT.
Q.21 In communication electronics, why JFET RF amplifier is used in a receiver instead of BJT
amplifier?
Ans. The reasons for using JFET RF amplifier in receiver instead of BJT amplifier are :
1) The noise level of JFET is very low.
2) The antenna of the receiver receives a very weak signal that has an extremely low
amount of current. Since JFET is a voltage controlled device, it will respond to low current
signal provided by the antenna.

EXERCISE
1. When gate-source voltage is – 12 V and gate current is 0.1 µA, determine the resistance
between the gate and source of a given JFET. [Ans. 120 MΩ]
2. In case of a JFET the variation in drain current is of 100 n A when drain-source voltage is
varied by 1.25 V, keeping gate-source voltage VGS constant, determine the dynamic resistance
of the JFET. [Ans. 12.5 kΩ]
3. In a JFET the drain current is changed by 0.25 m A when the gate-source voltage is changed
by 0.125V, keeping drain-source voltage constant. Calculate the transconductance of the
given JFET. [Ans. 2 m S]
4. For an N-channel JFET, IDSS = 8mA;Vp = – 4V; VGS = –1 V. Determine ID, gmo and gm.
[Ans. 4.5 mA; 4 mA/V; 3 mA/V]
5. In an N-channel JFET biased by voltage divider method, determine the value of Rs to give
operating point 1D = 3 m A and VDS = 10 V. Given that VDD = 30 V, RG1 = 1.5 M Ω, RG2 =
0.5 M Ω. JFET parameters are IDSS = 12 mA and Vp = – 4 V. [Ans. 1.833 kΩ]

ppp
212 Basic Electronics

Metal-Oxide-Semiconductor
Field Effect Transistors (MOSFET)
9
CHAPTER

9.1 INTRODUCTION
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSEFT) is an important
semiconductor device and is widely employed in many circuit applications. Since it is
constructed with the gate terminal insulated from the channel, it is sometimes called
insulated gate FET (IGFET). Like, a JFET, a MOSFET is also a three terminal (source,
gate and drain) device and drain current in it is also controlled by gate bias. The operation
of MOSFET is similar to that of JFET. It can be employed in any of the circuits covered
for the JFET and, therefore, all the equations apply equally well to the MOSFET and
JFET in amplifier connections. However, MOSFET has lower capacitance and input
impedance much more than that of a JFET owing to small leakage current. In case of a
MOSFET the positive voltage may be applied to the gate and still the gate current remains
zero.
MOSFETs are of two types namely (i) enhancement type MOSFET or E-MOSFET
and (ii) depletion enhancement MOSFET or DE-MOSFET. In the depletion-mode
construction a channel is physically constructed and a current between drain and source is
due to voltage applied across the drain-source terminals. The enhancement MOSFET
structure has no channel formed during its construction. Voltage is applied to the gate, in
this case, to develop a channel of charge carriers so that a current results when a voltage is
applied across the drain-source terminals.
9.2 MOSFET
Ø This is a type of FET, where gate is made up of SiO2 layer and metal is used to have
contacts. So it is named as metal oxide semi conductor FET (MOSFET).
Ø In MOSFET there are 4 terminals :
(a) Source (S) (b) Gate (G) (c) Drain (D) (d) Substate (SS)
Substate is a large block semiconductor on which source, gate & drain are created.
Ø It can be used as four terminal device or as three terminal device.
When used as three terminal device, then source is shorted with substrate.
Ø Between source to drain, there is presence of channel. The channel may be n-type or
p-type.
 213

In n - channel MOSFET :-
SS → p - type
S&D → n - type
In p-channel MOSFET :-
SS → n-type
S&D → p - type
Ø The channel may be initially present or may be later to be created by suitable supply.
If channel is initially present, then it is DMOSFET.
If channel is initially absent, then it is EMOSFET.
Ø Here also input junction is reverse biased, so input current (IG) = 0A.
9.3 D-MOSFET (Depletion MOSFET)
Ø In this type of MOSFET, the channel is initially present.
Construction
Ø A large block of semiconductor known as substrate, (n-type in p-mos & p-type in
n-mos) is taken.
Ø On the substrate, source and drain are formed.
Ø Source and drain are n-type in n-mos & p-type in p-mos.
Ø A silicon dioxide (SiO2) layer forms the gate region.
Ø The metal contacts are taken from each terminal.
Ø A channel (of n-type in n-mos or of p-type in p-mos) is formed between source to
drain.
(Drain)
D SiO2 n-channel

Metal contacts

(Gate) p
Substrate
G n substrate
SS

S n-doped regions
(Source)
Fig. 9.1
214 Basic Electronics
Operation :
Let us consider n-channel DMOSFET.
Substrate is shorted to source to use as three terminal device.
D

n
+
+
e SS
G e p VDS
n
e
VGS= 0 V e –
e
S – e
n

ID = IS = IDSS

Fig. 9.2
Case-I (VGS = 0, VDS > 0)
Ø Under this condition, –ve terminal of VDS connected to source will repel the electrons,
while +ve terminal connected to drain attracts the electrons.
Ø Due to presence of channel, current flow occurs.
Ø As VDS is increased then current increases to a certain value, after that saturates.
The maximum current of ID attained when VGS = 0V, is known as drain to source
saturation current (IDSS).
Ø This case is similar to JFET.
Case - II (VGS < 0, VDS > 0)
Ø When VDS is set at a +ve value, then maximum current is flowing for VGS = 0V.
Ø Now if VGS = –ve, then –ve terminal of VGS is connected to gate. It will repel electron
from channel, so channel width decreases.
Ø Due to decrease in channel, drain current decreases. At a particular value of V GS, ID
becomes zero, known as Pinch-off voltage.
Ø Here as channel gradually decreasing, it is known as depletion mode of operation
of DMOSFET which is same as that of JFET.
Case - III (VGS > 0 with VDS > 0)
Ø In this condition, the +ve terminal is connected to gate that will attract the electrons
and accumulate at channel by which channel width increase ⇒ ID increases.
Ø This is known as enhancement mode of operation
Ø It is violating the name so this mode is not used.
 215

ID(mA)
10.9 VGS= + 1V
Depletion Enhacement
mode mode
8 IDSS VGS= + 0 V

4 I DSS VGS= – 1 V
2
2 I DSS
VGS= – 2 V
4 VGS= VP/2=– 3 V
–4 V
–5 V
– 6 – 5 – 4 – 3 – 2 –1 0 VGS 0 VDS
VP VGS= VP= – 6 V
VP
2 0.3VP
Figure 9.3 Drain and transfer characteristics for an n-channel depletion-type MOSFET.
for VP= –6 V and IDSS = 8 mA
NOTE :
So depletion mode DMOSFET ≅ JFET.

F1 − V I 2

It also satisfied shockley’s equation : I D = I DSS GH V JK

GS

p
NOTE :
Ø In n-channel DMOS, VGS = –ve
Ø In p-channel DMOS, VGS = +ve
9.4 E-MOSFET (ENHANCEMENT - MOSEFET)
In this type of MOSFET, the channel is initially absent and it can be created by giving
suitable input supply. D SiO2 n-doped
Construction region
Ø A large block of n-channel
semiconductor known as
n
substrate, (n-type in p-mos Metal
& p-type in n-mos) is contacts
taken. p-type
G
Ø On the substrate, source substrate Substrate
and drain are formed. SS

Ø Source and drain are

n-type in n-mos & p-type n
in p-mos.
Ø A silicon dioxide (SiO2)
n-doped regions
layer forms the gate S
region. Fig. 9.4
216 Basic Electronics
Ø The metal contacts are taken from each terminal.
Ø The channel is initially absent and later will be created by suitable supply.
Operation
Let us consider n-channel EMOSFET.
Case -I : (VGS = 0, VDS > 0)
Ø Although, –ve terminal connected to source repels electrons & +ve terminal connected
to drain attracts electrons, due to absence of channel, no current will flow.
Ø To make the current flow, first the channel is to be created.
CASE - II : (VGS < 0, VDS > 0)
Ø The channel as is of n-type, channel can be created when electrons are deposited
near gate.
Ø Now by giving –ve supply to VGS, the electrons are repelled, not accumulated near
gate.
Ø So there can’t be current flow.
CASE-III : (VGS > 0, VDS > 0)
The +ve supply at gate accumulates electrons near gate, so channel will start to create.
Ø The channel is completely created at a particular value of V GS after which current
flow starts.
This voltage is known as threshold voltage.
Ø So out of total VGS supply, VTh amount is used to create the channel, rest is used to
drive the current.

D SiO2
n-doped
regions

n
Metal
contacts
p-type
G
substrate
Substrate
SS

n-doped region
S
Fig. 9.5
 217

So here equation is

b
I D = k VGS − VTh g 2

K = constant, cant be determined from given ID(ON) and as “ON” condition.

eV j
2
⇒ k = I D ( ON ) GS ( ON ) − VTh

Ø Here upto VTh, no current flow occurs.

Ø Here VDG = VDS – VGS & VDS = VGS – VTh

ID (mA)
ID(mA)

10 10 VGS= +8 V
9 9
8 8
7 7 VGS = + 7V
6 6
5 5 VGS = +6 V
4 4
3 3
VGS = + 5 V
2 2
VGS = +4 V
1 1
VGS = +3 V
0 1 2 3 4 5 6 7 8 VGS 0 5 10 15 20 25 VDS
VT VGS=VT=2 V
Fig. 9.6

NOTE :
Ø In n-channel EMOS, VGS = +ve
Ø In p-channel EMOS, VGS = –ve
9.5 CMOSFET
A very effective logic circuit can be established by constructing a p-channel and an n-
channel MOSFET on the same substrate as shown in Fig. 9.7. Note the induced
p-channel on the left and the induced n-channel on the right for the p-channel and
n-channel devices, respectively. The configuration is referred to as a complementary
MOSFET arrangement (CMOS) that has extensive applications in computer logic design.
The relatively high input impedance, fast switching speeds, and lower operating power
levels of the CMOS configuration have resulted in a whole new discipline referred to as
CMOS logic design.
218 Basic Electronics
One very effective use of the complementary arrangement is as an inverter, as shown
in Fig. 9.8. As introduced for switching transistors, an inverter is a logic element that
“inverts” the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5V
(1-state), an input level of 0 V will result in an output level of 5 V, and vice versa. Note in
Fig. 9.7 that both gates are connected to the applied signal and both drain to the output V 0.
The source of the p-channel MOSFET (Q2) is connected directly to the applied voltage
VSS, while the source of the n-channel MOSFET (Q1) is connected to ground. For the
logic levels defined above, the application of 5 V at
Vi

V0
VSS G2 G1

S2 D2 D1 S1

SiO2
p p+ n p+
n+ p+ n+ n+

When “on” When “on”

p
p-channel MOSFET n-channel MOSFET

n-type substrae

Fig. 9.7

the input should result in approximately 0 V at the output. With 5 V at V, (with respect to
ground), VGS = Vi and Q1 is “on,” resulting in a relatively low resistance between drain
1
and source as shown in Fig. 9.9. Since Vi and VSS are at 5 V, VGS = 0 V, which is less than
2
the required VT for the device, resulting in an “off” state. The resulting resistance level
between drain and source is quite high for Q2, as shown in Fig. 9.8. A simple application
of the voltage-divider rule will reveal that V0 is very close to 0 V or the 0-state, establishing
the desired inversion process. For an applied voltage Vi of 0 V (0-state), VGS = 0 V and
1
Q1 will be off with VSS = –5V, turning on the p-channel MOSFET. The result is that Q2 will
present a small resistance level, Q1 a high resistance, and V0 = VSS = 5 V (the 1-state).
Since the drain current that flows for either case is limited by the “off” transistor to the
leakage value, the power dissipated by the device in either state is very low.
 219

VSS=5 V
–
VGS2
+
p-channel VSS 5V
MOSFET Ileakage
Q2
Q2 off R2 (high)

Vi V0 = 0 V
(0-state) R1VSS
V0 = ≅ 0 V (0 − state)
R1 + R 2

n-channel
5V Q1 on
MOSFET R1 = (low)
(1-state) Q1
+ VGS1

Fig. 9.8 Fig. 9.9

Vi PMOS NMOS V0
LOW ON OFF HIGH ⇒ V0 = Vi
HIGH OFF ON LOW

Example 9.1 : For the n-channel depletion-type MOSFET of Fig. 9.10, determine :
(a) ID and VGS .
Q Q
(b) V DS .
18V

1.8 kΩ
110 MΩ
V0

I DSS 6 mA
Vi
VP = −3 V

10 MΩ 750 Ω

Fig. 9.10
220 Basic Electronics
Solution :
(a) For the transfer characteristics, a plot point is defined by ID = IDSS/4= 6 mA/4= 1.5
mA and VGS = VP/2 = – 3 V/2 = – 1.5 V. Considering the level of VP and the fact that
Shockley’s equation defines a curve that rises more rapidly as VGS becomes more positive,
a plot point will be defined at VGS = + 1 V. Substituting into shockley’s equation yields.

FG
I D = I DSS 1 −
VGS IJ 2

H VP K
F +1V IJ
= 6 mA G1 −
2
FG 1IJ 2

b g
H −3 V K H 3K
= 6 mA 1 + = 6 mA 1778
.

= 10.67 mA
The resulting transfer curve appears in Fig. 9.11. Proceeding as described for JFETs, we
have;
10M Ω (18V) ID (mA)
VG = = 15
. V
10M Ω + 110 MΩ
11
VGS = VG − I D R S = 15
. V − I D (750Ω)
10
9
8
7
6 ID (mA)

Setting ID = 0 mA results in 5
4
VGS = VG = 1.5 V Q-point IDQ = 3.1 mA
3
Setting VGS = 0 V yields 2
1
VG 15
. V
ID = = = 2 mA
R S 750 Ω –3 –2 –1 0 1 2
VGS
The plot points and resulting bias line VGSQ = – 0.8 V
appear in Fig. 9.11. The resulting Fig. 9.11 Determining the Q-point for the
operating point : network of Fig. 9.10
IDQ = 3.1 mA
VGSQ = – 0.8 V
(b) Now : VDS = VDS – ID (RD + RS)
= 18 V – (3.1 m A)(1.8 kΩ) + 750 Ω)
≅ 10.1 V
 221

Example 9.2 :
Determine the following for the network of Fig. 9.12
(a) ID and VGSQ. 20 V
Q
(b) V D .

6.2 kΩ

V0

Vi IDSS = 8 mA
VP = – 8V

1M Ω
2.4 kΩ

Solution : Fig. 9.12

(a) The self-bias configuration results in
VGS = – IDRS

The graph for transfer line equation can be obtained by following points, that satisfy
VGS = – IDRS

VGS ( V) I D ( mA )
0 0
ID(mA)
−4 2
The transfer characteristic graph can 12
be plotted by using following points 11
that satisfy Shockley’s equation. 10
9
VGS ( V) I D ( mA ) 8
7
0 8
6
−2.4 4 5
−4 2 4
−8 0 3
2 ID = 1.7 mA
Q
1
The resulting Q-point :
IDQ = 1.7 mA –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 VGS
VGSQ = – 4.3 V VP VGS = – 4.3 V
Q

(b) VD = VDD – IDRD Fig. 9.13 : Determining the Q-point for the
= 20 V – (1.7 mA) (6.2 kΩ) network of Fig. 9.12
= 9.46 V
222 Basic Electronics
Example 9.3 :
Determine IDQ and VDSQ for the enhancement-type MOSFET of Fig. 9.14

12 V

2 kΩ

V0
1 µF
10 MΩ
ID(on) = 6 mA
Vi VGS(on) = 8 V
VGS(Th) = 3 V
1 µF

Fig. 9.14
Solution :
Plotting the Transfer Curve :
Two points are defined immediately as shown in Fig. 9.15 Solving for k :

I D ( on )
k=
( VGS( on ) − VGS( Th ) ) 2

VGS = 10 V, ID = 11.76 mA
6 mA 6 × 10 −3 ID
= = A / V2
b8 V − 3 Vg 2
25 12
11
= 0.24 × 10–3 A/V2 10
For VGS = 6 V 9
8
ID = 0.24 × 10–3 (6 V – 3 V)2 7
= 0.24 × 10–3(9) ID(on) 6
5
= 2.16 mA
4
For VGS = 10 V 3 VGS = 6 V, ID
ID = 0.24 × 10–3 (10 V – 3 V)2 2 = 2.16 mA
1
= 0.24 × 10–3(49)
0 1 2 3 4 5 6 7 8 9 10
= 11.76 mA
VGS(Th) VGS(on)
as also appearing on Fig. 9.15. The
four points are sufficient to plot the
full curve for the range of interest as Fig. 9.15 Plotting the transfer curve for the
shown in Fig. 9.15. MOSFET of Fig. 9.14
 223

For the Network Bias Line :

VGS = VDD – IDRD
= 12 V – ID (2 kΩ)
ID = mA
VGS = VGS = VDD = 12 V |I D = 0 mA
12
VDD 12 V 11
ID = R = 2 kΩ = 6 mA|VGS = 0 V 10
D 9
8
The resulting bias line appears
VDD 7
6
in Fig. 9.16. RD 5
At the operating point : 4
IDQ = 2.75 mA 3
I D Q = 2.75 mA 2
1 Q-Point
and VGS Q = 6.4 V 0 1 2 3 4 5 6 7 8 9 10 11 12 VGS
VGSQ = 6.4 V
with VDSQ = G GSQ = 6.4 V
Figure 9.16 Determining the Q-point
for the network of Fig. 9.14
40 V
Example 9.4 :
Determine ID , VGSQ, and
Q 3 kΩ
VDS for the network of Fig. 9.17.
22 MΩ D ID Q

2N 4351
G VDS VGS(Th) = 5 V
ID(on) =3 mA
+ at VGS(on) = 10 V
VGSQ –

18 MΩ
0.82kΩ

Solution :
Figure 9.17
Network :
R 2 VDD (18 MΩ)(40 V)
VG = = = 18 V
R1 + R 2 22 MΩ + 18 MΩ
VGS = VG – IDRS = 18 V – ID(0.82 k Ω)

When ID = 0 mA
VGS = 18 V – (0 mA)(0.82 kΩ) = 18 V
224 Basic Electronics

as appearing on Fig. 9.18. ID(mA)

When VGS = 0 V,
VGS = 18 V – ID (0.82 kΩ)
30
0 = 18 V – ID (0.82 kΩ)

18 V
ID = = 21. 95 mA 20
0.82 kΩ
10 Q-point
IDQ ≅ 6.7 mA

0 5 10 15 20 25 VGS
VGS(Th) VGSQ=12.5 V VG = 18 V

Figure 9.18 Determining the Q-point for the

network of Example 9.4

Device :
VGS(Th) = 5 V, ID(on) = 3 mA with VGS(on) = 10 V
I D( on )
k=
dVGS ( on ) − VGS( Th ) h 2

3 mA
= . × 10 −3 A V 2
= 012
b10 V − 5 Vg 2

and ID = kd V − V
GS h GS ( Th )
2

= 0.12 × 10–3 (VGS – 5)2

which is plotted on the same graph.
From Fig. 9.18.
IDQ ≅ 6.7 mA
V GS Q = 12.5 V
V DS = VDD – ID (RS + RD)
= 40 V – (6.7 mA) (0.82 kΩ + 3.0kΩ)
= 40 V – 25.6 V
= 14.4 V
 225

9.6. COMPARISON OF JFETS AND MOSFETS

JFETs and MOSFETs are quite similar in their operating principles and in their electrical
characteristics. However, they differ in some aspects, as detailed below :
1. JFETs can only be operated in the depletion mode whereas MOSFETs can be operated
in either depletion or in enhancement mode. In a JFET, if the gate is forward biased,
excess- carrier injunction occurs and the gate current is substantial. Thug channel
conductance is enhanced to some degree due to excess carriers but the device is
never operated with gate forward biased because gate current is undesirable.
2. MOSFETs have input impedance much higher than that of JFETs. This is due to
negligibly small leakage current.
3. JFETs have characteristic curves more flatter than those of MOSFETs indicating a
higher drain resistance.
4. When JFET is operated with a reverse bias on the junction, the gate current IG is
larger than it would be in a comparable MOSFET. The current caused by minority
carrier extraction across a reverse-biased junction is greater, per unit area, than the
leakage current that is supported by the oxide layer in a MOSFET. Thus MOSFET
devices are more useful in electrometer applications than are the JFETs.
For the above reasons, and also because MOSFETs are somewhat easier to manufacture,
they are more widely used than are the JFETs

SHORT QUESTIONS AND ANSWERS

Q.1 Why is MOSFET called sometimes IGFET ?

Ans. MOSFET is constructed with the gate terminal insulated from the channel so it is sometimes
called insulated gate FET (or IGFET).
Q.2 What is the significant difference between the construction of an enhancement type
MOSFET and a depletion type MOSFET?
Ans. In the depletion type MOSFET a channel is physically constructed and a current between
drain and source is due to voltage applied across the drain-source terminals while in
enhancement type construction no channel is formed during its construction. Voltage is
applied to the gate in case of enhancement type MOSFET, to develop a channel of charge
carriers so that a current results when a voltage is applied across the drain-source terminals.
Q.3 Why E-MOSFET is called sometimes normally-off MOSFET ?
Ans. E-MOSFET operates with large positive gate voltages only and does not conduct when
gate-source voltage VGS = 0, so it is called normally-off MOSFET.
Q.4 What is meant by gate-to-source threshold voltage in E-MOSFET ?
Ans. The minimum value of gate-to-source voltage VGS that is required to form the inversion
layer is termed the gate-to-source threshold voltage VTh.
226 Basic Electronics
Q.5 Why MOSFETs are never connected or disconnected in the circuit when power is ON ?
Ans. If a MOSFET is connected or disconnected in circuit while the power is ON, transient
voltages caused by inductive kickback and other effects may exceed V GS(max) and thus wipe
out the MOSFET.

EXERCISE

1. In a MOSFET amplifier circuit, gm = 3,500 µ S, RL = 20 kΩ and RD = 5 M Ω. Determine

voltage gain. [Ans. 69.72]
2. The common drain circuit given in fig. 10.24 has R1 = 3.5 MΩ, R2 = 1.5 M Ω, Rs = 2 KΩ, RL
= 20 kΩ, gm is 2.5 m S. Determine input impedance, output impedance and voltage gain.
[Ans. 1.05 MΩ, 333.3 Ω; 0.82]
3. The N-channel E-MOSFET used in the common source amplifier, shown in fig., has the
following parameters :
ID(ON) = 4 mA at VGS = 10 V, VGST = 4 V and gm = 5,000 n S.
Calculate VGS, ID, VDS and v0.
[Ans. VGS = 6 V; ID = 0.44 mA; VDS = 13.78 V and v0 = 2.5 V]

16 V

5 KΩ
C2
R1 50 KΩ D V0
C1

100 mV R2 30 KΩ

4. Explain how C-MOS is used as logic invertor.

ppp
Feedback Amplifiers and Oscillators
10
CHAPTER
10.1 INTRODUCTION
While studying the amplifiers, we have given due consideration on their characteristics
such as voltage gain, input impedance, output impedance and bandwidth. All these
parameters are almost constant for a given amplifier i.e., an amplifier has more or less
fixed value of these parameters and the designer does not have any control over these
parameters. However, in general practice, the values of these parameters are required to
be changed as per the need. This can be done by different ways such as gain could be
reduced by using voltage divider network in the input or in the output circuit of the amplifier;
the input and output impedances could be controlled by connecting resistors in series or in
parallel with the terminals concerned. But all these methods result in wastage of signal
power. Therefore, these techniques are rarely employed in practice. A much more powerful
technique available with us for modifying amplifier characteristics is feedback technique.
The amplifiers in which feedback is employed are known as feedback amplifiers.
The feedback circuits not only modify the characteristics of the amplifier but they also
improve stability in gain, reduce phase and frequency distortion and reduce the noise level
at the output. In this chapter, we shall discuss the effects and methods of providing negative
feedback in the transistor amplifiers.
10.2 THE FEEDBACK CONCEPT
The process by which a fraction of output energy of a device (amplifier) is injected
back to its input is known as feedback.
In a feed back network the main parts are -
i) signal source
ii) Basic amplifier
iii) Sampler / sampling Network
iv) Feedback network
v) Mixer / mixing network
228 Basic Electronics

Fig. 10.1 Representation of any single-loop feedback connection around a basic

amplifier. The transfer gain A may represent Av, AI, GM or RM.
Signal Source :
This may be a voltage source or a current source, that supplies the signal to the basic
amplifier.
Basic amplifier :
This may be voltage amplifier, current amplifier, trans-conductance amplifier or a
trans-resistance amplifier. The ratio of output to the input of the basic amplifier is known
as gain (A).
Sampling network :
The output of the basic amplifier is given to the feedback network with the help of
sampling network or sampler. There are two types of sampling
i) Voltage or shunt or node sampling.
ii) Current or series or loop sampling.

Fig. 10.2 Feedback connections at the output of a basic amplifier, sampling the
output (a) voltage and (b) current
Feedback network :
This is the network that decides how much percentage of the output will be given as
feedback. The gain of the feedback network is given by β.
 Digital Circuits & Design 229

Mixer network :
This network does the mixing of the source signal with the feedback signal. There are
two types of mixing.
i) Shunt or current or node mixing.
ii) Series or voltage or loop mixing.

Fig. 10.3 Feedback connections at the input of a basic amplifier.

(a) Series comparison. (b) Shunt mixing.
10.3 TYPES OF FEEDBACK
i) Positive feedback or regenerative feedback :
When Feedback energy of a device (amplifier) is inphase with the input signal, it is
known as positive feedback.
The positive feedback is also known as regenerative or direct feedback.
- It increases the gain of the amplifier.
- It increases the noise, distortion.
- It decreases the stability.
- It is used in oscillator circuits.
ii) Negative or degenerative Feedback :
When feedback energy of the amplifier is 1800 out of phase with the input signal and
thus opposes it then it is known as negative feedback.
It is also known as degenerative feedback or reverse feedback.
- It decreases the gain of the amplifier.
- It decreases noise, distortion.
- It increases the stability.
- It is used in amplifier circuits.
10.4 PRINCIPLE OF FEEDBACK IN AMPLIFIERS
For an ordinary amplifier (i.e. one without feedback), the voltage gain equals the ratio of
output voltage and input voltage.
230 Basic Electronics

Vout
i.e. Voltage gain, A = V
in

The gain is called the open-loop gain.

A block illustrating the principle of feedback in an amplifier is given in fig. 10.1. Let
a fraction (say β) of the output voltage Vout be supplied back to the input and A be the
Vout
open-loop gain (i.e. A = ). Now the input voltage becomes
Vin
Vin = Vs + Vf = Vs + β Vout in case of positive feedback
and Vin = Vs – Vf = Vs – β Vout in case of negative feedback
i.e Vin = Vs ± β Vout depending on whether the feedback voltage is in phase with or in
phase opposition to the input signal voltage.
Consider a negative feedback case. The actual input voltage to the amplifier is the
signal voltage Vs less feedback voltage Vf ( β Vout).
i.e. Actual input voltage to amplifier, Vin = Vs – β Vout
The-output voltage Vout must be equal to the input voltage (Vs – β Vout) multiplied by
amplifier gain A. So
Output voltage, Vout = A (Vs – β Vout)
or (1 + β A) Vout = A VS,

Vout A
or Vs = 1+ β A

Vout
But V is called the voltage gain of the amplifier with feedback, Af. This is also referred
s

to as closed-loop gain.

Vout A
Thus voltage gain with negative feedback, Af = =
Vs 1+ βA

A
Similarly voltage gain with positive feedback, A f = 1 − β A

The term β A is called the feedback factor whereas β is known as the feedback
ratio Land (1 ± β A) is known as loop gain.
1. If (1 – β A) is less than unity then Af exceeds A. This condition, corresponds to
positive feedback because voltage feedback adds to input signal voltage and increases
input voltage Vin. Positive feedback, though, increases the gain but it reduces the
stability and increases the distortion and so it is usually avoided.
 Digital Circuits & Design 231

2. If (1 – β A) is equal to zero then the gain Af becomes infinite. This is only possible
when input is zero. Thus the amplifier is then capable of giving output voltage even
with zero signal. Under such situation the circuit operates as an oscillator.
3. If (1 – β A) is greater than unity then Af is smaller than A. This means the feedback
voltage Vin becomes smaller than input signal voltage VS. This corresponds to negative
feedback in an amplifier. Though negative feedback reduces the gain of the amplifier
but improves its performance in several aspects, given in the succeeding Articles. It
may be noted that negative voltage feedback does not affect the current of the circuit.

1
Example 10.1 : An amplifier with voltage gain of 60 db uses of its output in negative
20
feedback, Calculate the gain with feedback in db.

60
Solution: Open-loop voltage gain, A = 60 db or antilog = 1,000
20

1
Feedback ratio, β = = 0.05
20

A 1,000
Gain with feedback, A f = = = 19.6 or 20 log10 19.6 db = 26,85 db
1 + β A 1 + 0.05 × 1,000
= 25.85 db Ans.
Example 10.2 : Voltage gain of an amplifier without feedback is 60 db. It decreases to 40
db with feedback. Calculate the feedback factor.
Solution: Voltage gain of amplifier without feedback, A = 60 db or 1,000
Voltage gain with feedback, Af = 40 db or 100 Q 20 log Af = 40 db or Af = 100

A
∴ Gain with feedback, A f = 1 + β A

A 1,000
or Feedback factor, β A = −1= − 1= 9 Ans.
Af 100

Example 10.3 : A single stage transistor amplifier has a voltage gain of 600 without
feedback, and 50 with feedback. Calculate the %age of output which is fedback to
the input.
Solution : Voltage gain without feedback, A = 600
Voltage gain with feedback, Af = 50

A
Q Af =
1+ βA
232 Basic Electronics

600
∴ 50 =
1 + 600β
or β = 0.01833
Percentage of output voltage that is fedback to the input

Vf
= V × 100 = β × 100 = 0.01833 x 100 = 1.833% Ans.
out

Example 10.4 : An amplifier with a negative feedback provides an output voltage of 5 V

with an input voltage of 0.2 V. On removal of feedback, it needs only 0.1 V input to
give the same output. Determine (i) gain without feedback (ii) gain with feedback
and (iii) feedback ratio.
Solution :

Output voltage 5
Gain without feedback, A = without feedback = = 50 Ans.
Input voltage 01
.

Output voltage 5
Gain with feedback, A f = Input voltage with feedback = = 25 Ans.
0.2

A
Now since A f = 1 + β A

50
∴ 25 =
1 + 50β

50
−1
or Feedback ratio = 25 = 0.02 Ans.
50
Example 10.5 : A negative feedback of β = 0.002 is applied to an amplifier of gain 1,000.
Calculate the change in overall gain of the feedback amplifier if the internal am-
plifier is subjected to a gain reduction of 15%.
Solution : Voltage gain without feedback, A = 1,000
β = 0.002

A 1,000
Voltage gain with feedback, A f = 1 + β A = 1 + 0.002 × 1,000 = 333.33

When open-loop gain is reduced by 15%

A’ = (1 – 0.15) × 1,000 = 850
 Digital Circuits & Design 233

850
Voltage gain with feedback, A ′f = = 314.8
1 + 0.002 × 850

A f − A'f
Percentage change in overall gain = × 100 = 5.6% Ans.
Af
10.5 ADVANTAGES OF NEGATIVE FEEDBACK
There are numerous advantages of negative feedback which outweigh its only drawback
of reduction in gain. Among the advantages are :
1. Gain Stability. The voltage gain of an amplifier with negative feedback is given as
1
Af= A/ (1 + A β). If Aβ > 1 then the expression becomes A,- = i.e. overall gain of
β
feedback amplifier A, is independent of internal gain and depends only on feedback
ratio β, and β in turn depends on the passive elements such as resistors. Resistors
remain fairly constant and so the gain is stabilised.
2. Reduced Non-linear Distortion. A large signal stage has non-linear distortion which
is reduced by a factor (1 + A β) when negative feedback is used.
3. Reduced Noise. There is always a noise voltage in the amplifier which is reduced by
a factor (1 + A β) when negative feedback is used.
4. Increased Bandwidth (or Improved Frequency Response). The bandwidth (BW)
of an amplifier without feedback is equal to the separation between 3-db frequencies
f1 and f2. If A is the gain then gain-bandwidth product is A x BW. With the negative
feedback the amplifier gain is reduced and since gain bandwidth product has to remain
constant in both cases, so obviously the bandwidth will increase to compensate for the
reduction in gain.
5. Increased Input Impedance. The input impedance of the amplifier with negative
feedback is increased by a factor (1 + A β).
6. Reduced Output Impedance. The output impedance of the amplifier with negative
feedback is reduced by a factor (1 + A β)
10.6 TYPES OF NEGATIVE FEEDBACK CONNECTIONS
Depending on types of sampling and mixing, there are four types of negative feedback
connections.
i) Voltage - series feedback
ii) Voltage - shunt feedback
iii) Current - series feedback
iv) Current - shunt feedback
In all connections the first word refers to the type of sampling and 2nd word refers to the
type of mixing.
234 Basic Electronics

Fig. 10.4 Feedback amplifier types : (a) Voltage-series feedback, Af / Vo /Vs;

(b) voltage-shunt feedback, Af = Vo/Is; (c) current-series feedback, Af = Io /Vs;
(d) current-shunt feedback, Af = Io /Is.
Table 10.1 Summary of Gain, Feedback, and Gain with Feedback from Fig. 9.2

Voltage-Series Voltage-Shunt Current-Series Current-Shunt

Vo Vo Io Io
Gain without feedback A Vi Ii Vi Ii

Vf If Vf If
Feedback β Vo Vo Io Io

Af Vo Vo Io Io
Gain with feedback
Vs Is Vs Is

10.7 EFFECT OF NEGATIVE FEEDBACK ON INPUT IMPEDANCE

High input impedance is always desirable in an amplifier as it will not load the preceding
stage or the input voltage source. Such a desirable characteristic can be had with the help
of negative feedback. The effect of negative feedback on the input impedance of an
amplifier is explained below.
A more detailed series feed back connection is shown in fig. 10.5. The input impedance
can be determined as follows :
 Digital Circuits & Design 235

Vin Vs − Vf
I in = =
Z in Z in

Vs − βVout
=
Z in

Q Vf = βVout

Vs − βVin
= Q Vout = AV
Vin
Z in
Fig. 10.5
or IinZin = Vs – βA Vin

or Vs = IinZin + βA Vin= IinZin + βA IinZin

Vs
or = Z in + β A Z in
I in

Vs
and Z inf = = Z in + (β A ) Z in = Z in (1 + βA )
I in
Thus, series voltage negative feedback increases the input impedance of an amplifier
by a factor (1+ βA). This is the same factor by which voltage gain is reduced.
10.8 EFFECT OF NEGATIVE FEEDBACK ON OUTPUT IMPEDANCE
Just an high input impedance is advantageous to an amplifier, so is low output impedance.
With lower output impedance, the amplifier is better suited to drive a low impedance load.
Such a desirable characteristic can be had by employing negative feedback. The effect of
negative feedback on the output impedance of an amplifier is explained below.
The voltage-series feedback circuit given in fig.10.3 provides sufficient circuit detail
for determining output impedance with feedback. The input terminals are short-circuited
so that, Vf is now the only input voltage to the amplifier. Now a voltage source Vout is
applied at the output terminals so that Iout current is drawn from the applied source.
Now Vout = IoutZout + AVin = IoutZout – AVf Q Vin = – Vf
= IoutZout – A (βVout) Q Vf = βVout
or Vout +AβVout= IoutZout
Vout Z out
or Vout(l + βA) = IoutZout or I = 1 + β A
out

Z out Z out
or Z out f = 1 + β A Q Output impedance with feedback Z out f = I
out
236 Basic Electronics
Thus, series voltage negative feedback reduces the output impedance of an amplifier
by a factor (1 + β A). This is the same factor by which voltage gain is reduced.
Example 10.6 : An amplifier has an input impedance of 1 kΩ and output impedance of 10
kΩ and a voltage gain of 10,000. If a negative feedback of β = 0.02 is applied to
it, determine the input and output impedances of the amplifier.
Solution: Open-loop gain of amplifier, A = 10,000
Feedback ratio, β = 0.02
Input impedance without feedback, Zin= 1 kΩ
Output impedance without feedback, Zout = 10 kΩ
Input impedance with feedback, Zin f = (1 + β A) Zin
= (1 + 0.02 × 10,000) × l kΩ = 201 kΩ Ans.
Z out 10 k Ω
Output impedance with feedback, Zout f = Z out f = 1 + β A = 1 + 0.02 × 10,000

= 49.75Ω Ans.
Example 10.7 : An amplifier with a gain of 60 db has an output impedance of 10 kΩ. It is
required to modify its output impedance to 1 kΩ. What type of feedback has to be
applied ? Calculate the feedback factor. Also find the percentage change in the
overall gain, for a 10 % change in the open-loop gain of the amplifier.
Solution:
60
Open-loop voltage gain, A = 60 db or antilog = 1,000
20

Z out
Output impedance with feedback, Z out f = 1 + β A

10 × 103
∴ 1 × 103 = QZ out f = 1k Ω; Zout = 10 kΩ; and A = 1,000
1 + β × 1,000
or β = 0.009
Feedback factor, βA = 0.009 × 1,000 = 9 Ans.

For 10% decrease in open-loop gain, we have new open-loop gain

FG 10 IJ
H
A′ = 1 −
100 K
A = 0.9 A = 0.9 × 1,000 = 900

A′ 900
New gain with feedback, A ′f = = = 98.9
1 + βA ′ 1 + 0.009 × 900
 Digital Circuits & Design 237

A f − A ′f 100 − 98.9
Percentage change in overall gain = × 100 = × 100 = 11%
.
Af 100

A 1,000
QA f = = = 100
1 + βA 1 + 0.09 + 1,000

10.9 EFFECTS OF NEGATIVE FEEDBACK ON AMPLIFIER CHARACTERISTICS

S.No. Type of feedback Voltage Voltage Current Current
series shunt series Shunt
Characteristics
1 Voltage gain Decreases Decreases Decreases Decreases
2 Non-linear distortion Decreases Decreases Decreases Decreases
3 Noise Decreases Decreases Decreases Decreases
4 Input impedance Increases Decreases Increases Decreases
5 Output impedance Decreases Decreases Increases Increases
6 Bandwidth Increases Increases Increases Increases
10.10 INTRODUCTION TO OSCILLATOR
An oscillator is the basic element of all ac signal sources and generates sinusoidal signal
of known frequency and amplitude. It is one of the basic and useful instrument used in
electrical and electronic measurements. For example, an oscillator finds wide applications in
electronic communication equipment. In AM (amplitude modulation) and FM (frequency
modulation) superheterodyne receivers, “local” oscillators are used to assist the reduction of
the incoming radio frequency (RF) to a lower intermediate frequency (IF). Oscillator circuits
are also employed in the “exciter” section of a transmitter to generate the RF carrier. Other
applications include their use as “clocks” in digital systems such as microcomputers, in the
sweep circuits found in TV sets and oscilloscopes.
Since sinusoidal waveforms are encountered so frequently in electronic measurement
work, the oscillator (sine wave generator) represents the largest single category of signal
generators. This device covers the frequency range from a few Hz to many GHz.
Although we speak of an oscillator as “generating” a sinusoidal signal, it is to be noted that it
does not create energy, but merely acts as an energy converter. It simply converts
unidirectional current drawn from a dc source of supply into alternating current of desired
frequency. The function of an oscillator is reverse of that of a rectifier and, therefore, sometimes
called inverter. However, we generally think of oscillator circuits as providing an ac voltage
signal.
It is worthmentioning here that although an alternator (ac generator) generates sinusoidal
ac power of 50 Hz, it cannot be called an oscillator. An alternator is a mechanical device that
have rotating parts, converts mechanical energy into ac energy and that cannot produce ac
energy of high frequency whereas an oscillator is a non-rotating electronic device that converts
dc energy into ac energy of frequency ranging from a few Hz to many GHz.
238 Basic Electronics
Though alternator generates large amount of ac power but for several applications such
as radio-transmitters and receivers, radars etc., an oscillator is preferred owing to its numerous
advantages over alternators for such applications.
These advantages are :
(i) Portable and cheap in cost.
(ii) An oscillator is a non-rotating device. Consequently, there is no wear and tear and
hence longer life.
(iii) Frequency of oscillation may be conveniently varied.
(iv) Voltage or currents of any frequency (20 Hz to 100 MHz) adjustable over a wide
range can be generated.
(v) Frequency once set remains constant for a considerable period of time.
(vi) Voltages free from harmonics as well as rich with harmonics can be generated by
sinusoidal oscillators and relaxation oscillators respectively.
(vii) Operation of an oscillator is silent, as there is no moving part in it.
(viii) High operation efficiency—due to absence of moving part, there is no wastage of
energy owing to friction.
For having a sinusoidal oscillator, we
require an amplifier with positive
feedback. The idea is to use the
feedback signal in place of an input
signal. If the loop gain and phase are
correct, there will be an output signal even though there is no external input signal. In other
words, an oscillator is an amplifier that is modified by positive feedback to supply its own
input signal.
10.11 CONDITION FOR OSCILLATOR OPERATION / BARKHAUSEN CRITERION
For a circuit to operate as a oscillator it should satisfy Barkhausen's criteria
(i) The Phase difference between the feedback signal and the source is zero or 360 0 i.e.
+ve feedback is used.
(ii) The loop gain (βA) should be atleast unity. i.e β A > 1
Every oscillator circuit has +ve feed back but Every +ve feed back circuit is not an
oscillator.
It is know that in a positive feedback circuit, the gain with feedback is

A
Af =
1 − βA
Ø When βA= 1, then oscillation starts.
 Digital Circuits & Design 239

But may be due to external noise, βA may go below unity, then oscillation will be disrupted.
So for sustained oscillation it is made greater than oh equal to unity So that if any noise
present then also the average value of loop gain will be equal to unity.
10.12 ESSENTIALS OF TRANSISTOR OSCILLATOR
From the above discussion it can be inferred that an oscillator must have the following three
elements
1. Oscillatory circuit or element.
2. Amplifier.
3. Feedback network.
The oscillatory circuit or element, also called the tank circuit, consists of an inductive
coil of inductance L connected in parallel with a capacitor of capacitance C. The frequency
of oscillation in the circuit depends upon the values of L and C. The actual frequency of
oscillation is the resonant or natural frequency and is given by the expression

1
f= Hz
2π L C

where L is inductance of coil in henrys, and C is the capacitance of capacitor in farads.

The electronic amplifier receives dc power from the battery or dc power supply and
converts it into ac power for supply to the tank
circuit. The oscillations occurring in the tank
circuit are applied to the input of the electronic
amplifier. Because of the amplifying properties
of the amplifier, we get increased output of
these oscillations. This amplified output of
oscillations is because of dc power supplied
from the external source (a battery or power
supply). The output of the amplifier can be Block Diagram of An Oscillator
supplied to the tank circuit to meet the losses. Fig. 10.6
The feedback network supplies a part of output power to the tank or oscillatory circuit in
correct phase to aid the oscillations. In other words the feedback circuit provides positive
feedback.
The block diagram of an oscillator is illustrated in fig. 10.6.
10.13 TYPES OF TRANSISTOR OSCILLATORS
A transistor can be operated as an oscillator for producing continuous undamped
oscillations of any desired frequency if tank (or oscillatory) and feedback circuits are properly
connected to it. All oscillators under different names have similar function i.e. they generate
continuous undamped output. However, they differ in methods of supplying energy to the
tank or oscillatory circuit to meet the losses and the frequency ranges over which they are
used.
240 Basic Electronics
Approximate
Type of Oscillator Frequency Ranges
Wien bridge oscillator 1 Hz — 1 MHz
Phase shift oscillator 1 Hz — 10 MHz
Hartley oscillator 10 kHz — 100 MHz
Colpitt’s oscillator 10 kHz — 100 MHz
Negative resistance oscillator > 100 MHz
Crystal oscillator Fixed frequency
10.14 OP-AMP OSCILLATOR CIRCUITS
A circuit to act as oscillator, should satisfy Barkhausen criterion. Op-amp itself produces
1800 phase shift to its input and another 1800 phase shift is provided by the external circuit.
Also the loop gain (βA) is made greater than unity, then it can be used as oscillator circuit.
10.14.1 RC Phase-Shift Oscillator

Fig. 10.7
Here the Op-amp is used in inverting made that produces 1800 phase shift because of –ve
gain. The rest 1800 phase shift is provided by three RC circuits connected in cascade.
Here each RC circuit provices 600 phase shift. For oscillation to be sustained, the value of
K should be equal to inverse magnitude of RC network transfer function at the frequency
of oscillation.
For sustained oscillation,

1
A> 29 and β=
29
A = Gain of Op-amp

1
and frequency of oscillation, f =
2 π RC 6
 Digital Circuits & Design 241

Advantage
1. It is cheap and simple circuit as it contains resistors and capacitors (not bulky and
expensive high-value inductors).
2. It provides good frequency stability.
3. The phase shift oscillator circuit is much simpler than the Wein bridge oscillator circuit
because it does not need negative feedback and the stabilization arrangements.
4. The output is sinusoidal that is quite distortion free.
5. They have a wide frequency range (from a few Hz to several hundred kHz.)
6. They are particularly suitable for low frequencies, say of the order of 1 Hz, as these
frequencies can be easily obtained by using R and C of large values.
Disadvantages
1. The output is small. It is due to smaller feedback.
2. It is difficult for the circuit to start oscillations as the feedback is usually small.
3. The frequency stability is not as good as that of Wien bridge oscillator.
4. It needs high voltage (12V) battery so as to develop sufficiently large feedback voltage.
10.14.2 Wein-Bridge Oscillator

Fig. 10.8
It is one of the most popular type of socillator used in audio and sub-radio frequency
ranges (20Hz - 20 kHz). This type of filter is simple in design, compact in size and remarkable
stable in its frequency output. Also its output is relatively free from distortion and its frequency
can be varied easily.
It consists of an op-amp in inverting mode providing 1800 phase shift and rest 1800
phase shift is provided by a bridge circuit consisting of 4 arms. Here R1, R2, C1 and C2 are
frequency adjustment elements. R3 & R4 form the part of Feedback path.
The bridge circuit will be balanced if
R 3 R1 C 2
= +
R 4 R 2 C1
242 Basic Electronics
The frequency of oscillation will be,
1
f=
2π R 1 , R 2 C1 C 2
If R1 = R2 = R & C1 = C2 = C
1
then f =
2πRC
R3
and = 2 ⇒ R 3 = 2R 4
R4

For sustained oscillatin, R 3 > 2 .

R4
Advantages :
1. It provides a stable low distortion sinusoidal output over a wide range of frequency.
2. The frequency range can be selected simply by using decade resistance boxes.
3. The frequency of oscillation can be easily varied by varying capacitances C 1 and C2
simultenously.
4. The overall gain is high because of two transistors.
Disadvantages :
1. The circuit needs two transistors and a large number of other components.
2. The maximum frequency output is limited because of amplitude and the phase shift
characteristics of the amplifier.

10.14.3 Crystal Oscillators

In crystal oscillators, the usual electrical
resonant circuit is replaced by a mechanically
vibrating crystal. The crystal (usually quartz)
has a high degree of stability in holding constant
at whatever frequency the crystal is originally
cut to operate. The crystal oscillators are,
therefore, used whenever great stability is (a) Crystal (b) Electrical Equivalent
needed, for example, in communication Mounting Circuit fo a Crystal
transmitters, and receivers, digital clocks etc. Fig. 10.9
A quartz crystal exhibits a very important property known as piezo-electric effect. When
a mechanical pressure is applied across the faces of the crystal, a voltage proportional to the
applied mechanical pressure appears across the crystal. Conversely, when a voltage is applied
across the crystal surfaces, the crystal is distorted by an amount proportional to the applied
voltage. An alternating voltage applied to a crystal causes it to vibrate at its natural frequency.
 Digital Circuits & Design 243

Besides quartz, the other substances that exhibit the piezo-electric effect are Rochelle
salt and tourmaline. Rochelle salt exhibits the greatest piezoelectric effect, but its applications
are limited to manufacture of microphones, headsets and loudspeakers. It is because the
Rochelle salt is mechanically the weakest and strongly affected by moisture and heat.
Tourmaline is most rugged but shows the least piezo-electric effect. Quartz is a compromise
between the piezoelectric effect of Rochelle salt and the mechanical strength of tourmaline.
It is inexpensive and readily available in nature. It is mainly the quartz crystal that is used in
radio-frequency (RF) oscillators.
For use in electronic oscillators, the crystal is suitably cut and then mounted between
two metal plates, as shown in fig. 10.9(a). Although the crystal has electro-mechanical
resonance but the crystal action can be represented by an electrical resonant circuit, as
shown in fig. 10.9 (b). The crystal actually behaves as a series R-L-C circuit in parallel with
CM where CM is the capacitance of the mounting electrodes. Because the crystal losses,
represented by R, are small the equivalent crystal Q is high-typically 20,000. Values of Q
upto 106 can be obtained by making use of crystals.
Because of presence of CM, the crystal
has two resonant frequencies. One of these is
the series resonant frequency f s at which

IMPEDANCE, Z
1
2π f L =
2 π f C and in this case the crystal
impedance is very low. The other is parallel
resonance frequency fp which is due to parallel
resonance of capacitance C M and the fs fp
reactance of the series circuit. In this case FREQUENCY, f IN Hz
crystal impedance is very high. The impedance
Crystal Impedance Versus
versus frequency curve of the crystal is shown Frequency Curve
in fig.10.10. In order to use the crystal properly Fig. 10.10
it must be connected in a circuit so that its low
impedance in the series-resonant operating mode or high impedance in the anti-resonant or
parallel resonant operating mode is selected.
Two resonant frequencies are given by the expressions
1
Series resonant frequency, fs =
2π LC

1 1 + C / CM
Parallel resonant frequency, fp =
2π LC

It appears that fp is higher than fs but the two frequencies are very close to each other.
C
It is due to the fact that the ratio is very small.
CM
244 Basic Electronics
To stabilize the frequency of an oscillator, a crystal may be operated at either its series
or parallel resonant frequency.
To excite a crystal for operation in the series-resonant mode it may be connected as a
series element in a feedback path, as shown in fig. 10.11. In this mode of operation the
crystal impedance is the smallest and the amount of positive feedback is the largest. Resistors
R1, R2 and RE provide a voltage-divider stabilized dc bias circuit, the capacitor CE provides ac
bypass of the emitter resistor RE and the radio-frequency coil (RFC) provides for dc bias
while decoupling any ac signal on the power lines from affecting the output signal. The
voltage feedback signal from the collector to the base is maximum when the crystal impedance
is minimum (i.e. in series-resonant mode). The coupling capacitor CC has negligible impedance
at the circuit operating frequency but blocks any dc between collector and base. The circuit
shown in fig. 10.11 is generally called the Pierce crystal. The resulting circuit frequency of
oscillations is set by the series resonant frequency of the crystal. Variations in supply voltage,
transistor parameters, etc. have no effect on the circuit operating frequency which is held
stabilized by the crystal. The circuit frequency stability is set by the crystal frequency stability,
which is good.

Oscillator With Crystal Operating Oscillator With Crystal Operating

in Series Resonance in Parallel Resonance
Fig. 10.11 Fig. 10.12

Oscillator circuit with crystal operating in parallel resonance (a modified Colpitt’s oscillator
circuit) is illustrated in fig. 10.12. Since the parallel-resonant impedance of a crystal is of a
maximum value, it is connected in parallel. C1 and C2 form a capacitive voltage divider which
returns a portion of the output voltage to the transistor emitter. Transistor NPN combined
with R1, R2, RFC, and RE, constitutes a common base circuit. Capacitor C3 provides an ac
short circuit across R2 to ensure that the transistor base remains at a fixed voltage level. As
 Digital Circuits & Design 245

the output voltage increases positively, the emitter voltage also increases, and since the base
voltage is fixed, the base-emitter voltage is reduced. The reduction in V BE causes collector
current IC to diminish, and this in turn causes the collector voltage VC to increase positively.
Thus, the circuit is applying its own input, and a state of oscillation exists. The crystal in
parallel with C1 and C2 permits maximum voltage feedback from the collector to emitter
when its impedance is maximum, i.e., at its parallel resonant frequency. At other frequencies,
the crystal impedance is low, and so the resultant feedback voltage is too small to sustain
oscillations. The oscillation frequency is stabilized at the parallel resonate frequency of the
crystal.
The advantages and disadvantages of a crystal oscillator are given below :
Advantages
1. It is very simple circuit as it does not need any tank circuit other than crystal itself.
2. Different oscillation frequencies can be had by simply replacing one crystal with another.
3. The Q-factor, which is a measure of the quality of resonance circuit of a crystal, is very
high. The Q-factor of a crystal may range from 104 to 106 whereas the L-C circuit may
have a Q-factor only of the order of 100.
4. Most crystals will maintain frequency drift to within a few cycles at 25° C. For greater
frequency stability, the crystal is often contained in an insulated enclosure termed as
crystal oven in which the temperature is thermostatically controlled. In this way it is
possible to have frequency drifts less than 1 part in 1010.
Disadvantages
1. The crystal oscillators have a very limited tuning range (or not at all). They are used for
frequencies exceeding 100 kHz.
2. The crystal oscillators are fragile and, therefore, can only be used in low power circuits.
Crystal oscillators must be designed to provide a load capacitance on the crystal as per
specifications listed by the manufacturer. This requirement is essential for obtaining oscillations
at the specified frequency. It is also important from the point of view of limiting the power
supplied to the crystal to the specified maximum. Too much crystal power causes distortion
in the oscillator waveform. It also causes overheating of the crystal, consequently rendering
the resonant frequency unstable. More important is that the thin-plated electrodes may be
melted off an overdriven crystal, destroying the device. Typical maximum drive levels for
plated crystals varies from 2 m W to 10 m W.
The maximum permissible drive power limits the ac voltages that may be applied across
the crystal and consequently affects the design of oscillator circuits. Crystal manufacturers
usually specify the resistance of individual crystal, as well as maximum drive power. From
these two, the maximum crystal ac voltage may be determined by using the relation
P = V2/R.
Example 10.8 : The parameters of a crystal oscillator equivalent circuit are LS = 0.8 H;
Cs = 0.08 pF, Rs = 5 k W and CP = 1.0 pF. Determine the resonance frequencies fs
and fp.
246 Basic Electronics
Solution : Series resistance, Rs = 5 k W = 5,000 W
Series inductance, Ls = 0.8 H
Series capacitance, Cs = 0.08 pF = 8 x 10–14 F .
Parallel capacitance, CP or CM = 1.0 p F = 1 × 10–12 F
1 1
Series resonant frequency, f s = = = 629 kHz Ans
2 π LS C S 2 π 0.8 × 8 × 10 −14

1 1 + Cs C p 1 1 + 8 × 10 −14 1 × 10 −12
Parallel resonant, f p = = Ans
2π L sC s 2π 0.8 × 8 × 10 −14
= 654 kHz Ans.

SHORT QUESTIONS

1. State the three fundamental assumptions which are made in order that the expression
A
Af =
1 + β A be satisfied exactly..
List five characteristics of an amplifier which are modified by negative feedback. Draw
a feedback amplifier in block diagram form. Identify each block, and state its function.
2. Differentiate between positive and negative feedback. How does negative feedback modify
the gain of an amplifier?
3. Discuss with the help of a circuit example, the purpose of providing
(i) negative feedback
(ii) positive feedback in amplifiers.
4. What is feedback in amplifiers ? Derive an expression for the closed-loop gain of the
amplifier with feedback. State the assumptions made in your derivation.
5. Derive an expression for the overall gain of a voltage series-feedback amplifier.
6. Derive the expression for the gain of an amplifier using negative feedback.
7. Explain the major advantages of using negative feedback in amplifiers.
8. What are the requirements of an oscillator circuit?
9. What is an oscillator? What are the essential elements of an oscillator? Bring but the
difference between a mechanical oscillator and an electronic oscillator.
10. (i) What is an oscillator?
(ii) Explain the basic principle of an oscillator with a block diagram.
11. i) What is feedback? Explain feedback.
ii) Explain the Barkhausen criterion for oscillations.
 Digital Circuits & Design 247

EXERCISE
1. A feedback amplifier has a voltage gain of 500 without feedback. Determine the voltage
gain with feedback if feedback ratio is 0.1. [Ans. 9.8]
2. The overall gain of an amplifier is 200. When negative feedback is applied, the gain decreases
to 10. Determine the fraction of the output that is fedback to the input. [Ans. 0.095]
3. In a negative feedback amplifier A = 100; β = 0.02 and input signal voltage is 40 m V.
Determine (i) voltage gain with feedback (ii) feedback factor, (iii) feedback voltage and
(iv) output voltage.
[Ans. (i) 33.33 (ii) 2 (iii) 26.666 mV (iv) 1.333 V]
4. To an amplifier of 60 db gain a feedback (negative) of β = 0.006 is applied. What would be
the change in the overall gain of the feedback amplifier if the gain of the amplifier decreases
by 15%. [ Ans. 2.462%]
5. An amplifier has a gain of 200 and distortion 10% with an input signal voltage of 200 mV.
Determine (i) output signal voltage (ii) distortion voltage and (iii) output voltage when an
input signal voltage is 200 m V. [ Ans. (i) 40 V (ii) 4 V (iii) 44 V]
6. An amplifier has gain of 60 and distortion 10% without feedback. Determine (i) gain and (ii)
distortion when negative feedback is applied, the feedback factor being 6.
[Ans. (i) 8.57 (ii) 1.43%]
7. Open-circuit voltage of an amplifier is reduced by 6 when a negative series feedback is
applied, by what factor the input and output impedances change ?
1
[Ans. Input impedance is increased to 6 times and output impedance is reduced to time]
6
8. A single- stage amplifier has a voltage gain of 10 and a bandwidth of 1 MHz. Three such
stages are cascaded and a negative feed of 10% is applied to the cascade stage. Find the
overall voltage gain and bandwidth of the cascaded stage with feedback.
[Ans. 10; 100 MHz]
9. In a CE amplifier, the emitter resistor is not bypassed the capacitor. Find the voltage gain if
RC = 20 kΩ and RE = 1.25 kΩ. [Ans. 16]
10. An emitter follower is found to have a voltage gain of 0.99. Determine β for the transistor.
[Ans. 99]
ppp
248 Basic Electronics

Electronic Instruments
11
CHAPTER

11.1 INTRODUCTION
Electronic instruments are either indicating or recording type instruments just like the
electrical measuring instruments. In addition to indicating and recording a quantity, some
instruments also control a quantity e.g. tacho-generator may be used for indicating or
recording the speed as well as for controlling the speed in a speed controlled motor. The
electronic instruments are computing, manipulating and processing information in much
the same way as the mind. Although some electronic instruments are more expensive than
simple electrical instruments but electronic instruments have some significant advantages
over electrical measuring instruments. The use of an electronic amplifier results in an
electronic instrument with high sensitivity capable of measuring very small signals. The
electronic instruments also have the ability to monitor remote signals. These instruments
are becoming more and more popular because of high speed operation, high sensitivity and
versatility and therefore, their study has become imperative.
In this chapter we shall discuss most commonly used electronic instruments i.e.
electronic voltmeters, electronic galvanometers, Q-meter and multimeter (VOM).
11.2 CATHODE RAY OSCILLOSCOPE
The cathode ray oscilloscope (CRO) is basically an electronic measuring instrument
(high-impedance voltmeter). It is used to measure voltage and time. The CRO is more
complicated and is used in many fields such as engineering, biology and medicine. CRO
provides a means of measuring and observing events that occur faster than the eye can
see them and hand record them. Moreover, the CRO gives us an instant picture (we call it
a display) of how a voltage varies with time, even when this variation is so fast and takes
place in a few microseconds. In otherwords, the display seen on the screen of a CRO is a
graph of voltage against time.
Many biological phenomena are already in the form of a voltage (e.g. the nerve
impulse and the electrical activity associated with the heart beat) and these can be applied
directly to the input of the CRO amplifier. The quantities such as temperature, blood pressure,
acceleration, etc., not in the form of a voltage signal can be changed (transduced) into a
 Digital Circuits & Design 249

voltage. Any quantity can by means of a transducer, be converted into a voltage (electrical
signal). Many transducers already exist in animals, for example some nerve endings in the
skin are transducers which convert pressure into a voltage impulse in the nerve.
Cathode ray oscilloscope is an electronic instrument used to display and measure
electrical quantities like ac / dc voltages / currents, time-phase relationships
current, etc.
Typical oscilloscopes have a frequency response from 0 Hz for direct current upto 40
MHz, RF and AF signals can be checked, peak to peak amplitude measurements are
possible. Following are the main parts of a CRO :
1. The cathode ray tube.
2. A low voltage and high voltage power supplies.
3. A linear time base generator and synchronizing circuit.
4. Vertical and horizontal amplifiers.
11.3 CATHODE RAY TUBE (CRT)
The cathode ray tube is the “heart” of an oscilloscope. The properties of electrons
being deflected by electric and magnetic fields and of producing fluorescence on a
fluorescent screen are made use of in the construction and working of the cathode ray
tube. It is used to display the waveform.
The major components of a general-purpose CRT are : Electron gun assembly
Accelerating anodes Deflection system Fluorescent screen Evacuated glass envelope
Figure 11.1 shows a cross sectional view of a CRT, showing its major components. A
CRT is an evacuated funnel shaped glass tube. An electron gun produces a focused
beam of electrons, a deflection system changes the direction of the beam and a fluorescent
screen converts the energy of the beam into visible light.
C
AC V/cm Y shift

DC AC/DC
Input Vertical (Y)
amplifier CRT

A1 A2 A3 Y X Aquadag
G
K coating
F

Base Deflection
Electron Focusing and Flourescent
Power supply

emission acceleration Screen

Time/cm
Electron gun High voltage
Level Stabiliser Low Voltage

Trigger Sweep Horizontal (X)

circuit generator amplifier To all circuits

X shift X gain

Fig. 11.1 Cathode ray tube

250 Basic Electronics
11.3.1 Electron Gun
An arrangement for producing and focusing an electron beam is called an
electron gun.
It consists of an indirectly heated cathode K, a control grid G, a pre-accelerator
anode A1, focussing anode A2 and an accelerating anode A3.
The purpose of the electron gun assembly is to provide a source of electrons, converged
and focused into a well-defined beam, which is accelerated towards the fluorescent screen.
The cathode is surrounded by a cylindrical cap G that is at a negative potential. This
cap, which has a small hole located along the longitudinal axis of the CRT, acts as the
control grid.
Electrons are emitted from the hot cathode due to thermionic emission. The control
grid G maintained at negative voltage (with respect to cathode) determines the amount of
electron flow (intensity and brightness).
The electrons emitted from the cathode and passing through the hole in the control grid are
accelerated by the high positive potential (2 kV to 10 kV) which is applied to the ‘pre-
accelerating’ (A1) and ‘accelerating anodes’ (A3). Both anodes are cylindrical in shape
having small openings located in the centre of each electrode, co-axial with the tube axis.
The electron beam is focused by the “focusing anode” (A2). The focusing anode A-
i is given a slightly lower potential (500 V to 1 kV) than the anodes Al and A3. Because of
the difference in potentials, the equipotential surface between the anodes A1 and A3 form
a shape like a convex lens (electron lens). Hence the knob controlling the potential of
anode A2 provides a focus control.
11.3.2 Deflection System
After the electrons leave the electron gun assembly, they pass through a region
controlled by the deflection plates. The deflecting system consists of a pair of horizontal
deflecting plates (X-set) and a pair of vertical deflecting plates (Y-set) placed at right
angles to each other. A positive voltage applied to the X-plates will deflect the beam
towards the right (+ x-axis) while a negative voltage applied to the X-plates will deflect the
beam towards the left (– x-axis). Similarly, a positive voltage applied to the Y-plates cause
the beam to deflect vertically upwards (+ y-axis) due to the attraction forces, while a
negative voltage applied to the Y-plates cause the beam to deflect vertically downwards
(– y-axis) due to the repulsion forces. The amount of deflection is directly proportional to
the potential across the plates.
If the voltages are applied simultaneously to X- and Y-plates, the electron beam is
deflected due to the resultant of these voltages. When no voltage is applied across the
plates X and Y, beam passes between them undeflected and produces a bright spot at the
centre of the screen.
If ac voltage is applied to the vertical plates, the spot will move up and down on the
screen at the frequency of ac voltage. Because of persistence of vision, the moving spot
 Digital Circuits & Design 251

will actually appear as a continuous, luminous vertical line. The maximum displacement of
the spot from its central position (X-axis) is equal to the amplitude (Vm) of the applied ac
voltage.
If an ac voltage (50 Hz) is applied to the horizontal plates, the spot moves left and
right at the rate of 50 times per second. Due to persistence of vision, the moving spot
appears as a solid horizontal line.
The distance that the beam will be moved on the screen by a potential difference of
1 V across a pair of deflection plates is called the deflection sensitivity.
Deflection factor of a CRT is the reciprocal of sensitivity.
The part of the CRO responsible for moving the spot horizontally is called the time-
base. It produces an internal voltage called sweep or sawtooth voltage waveform which
when applied to X-plates ensures that the spot moves horizontally across the screen at a
constant speed.
If a sinusoidal (input) voltage is applied to Y-plates at the same time as the spot is
moved across, we obtain a display of voltage against time. The pattern will appear stationary
only if the time T of sweep voltage is equal to, or is some multiple of the time for one cycle
of the wave on the Y-plates.
11.3.3 Fluorescent Screen
The screen is usually coated with a thin layer of zinc oxide or zinc orthosilicate
(phosphor). When the electron beam strikes the phosphor a spot of light is produced.
Because the phosphor absorbs kinetic energy from the electrons that strike it and then
gives up the energy in the form of light. This property of phosphor emitting light when
stimulated by electron bombardment is called fluorescence. Phosphor possesses a second
desirable characteristic called phosphorescence. It means that phosphor continues to emit
light for a period of time even after the source of excitation is removed. Persistence is
usually classified as short (lasting for (is), medium (lasting for ms) and long (lasting for
sees). A medium persistence time, generally used, ranges from 5 to 50 ms. Depending
upon the phosphor material used in the fluorescent screen, it is possible to have either
green, orange or white light.
The various types of phosphors used are :
PI, P2, Pll or P31 for short persistence (General purpose oscilloscopes) P7 and P39
are for medium (Medical oscilloscopes) and P10, P26 and P33 for long persistence (Radar).
11.3.4 Glass Envelope
The inner walls of the flared part of the tube, except for the screen is coated with a
conducting graphite substance called aquadag. It is maintained at the same potential as
focusing anode A2. The coating performs two functions.
252 Basic Electronics
(i) It accelerates the electron beam to the screen to produce a spot of light after it
passes between the deflecting plates.
(ii) Although the coating is not directly connected to the screen, the electrons are removed
by means of secondary emission from the screen and no pile-up occurs. The coating
collects the secondary electrons and returns them to the cathode.
CRT Graticule : The graticule is usually rectangular in form and is placed inside the
display area to allow correct measurements. Most CROs have a graticule inscribed on a
clear or tinted plastic plate, placed over the outside of the CRT face.
11.3.5 Time Base (Waveform display)
A special property of the CRO is its ability to display high frequency and short duration
waveforms. The signal to be viewed or displayed on the screen is applied across the
vertical (Y) plates of a CRT. In order to see the actual waveform or pattern, it is essential
to spread it out horizontally from left to right with a constant velocity. It is achieved by
applying sawtooth (ramp) voltage from the sweep (time-base) generator to X-plates. The
typical waveform of a time base voltage is shown in Fig. 11.2. If both voltages are applied
simultaneously, the pattern displayed on the screen is the signal as a function of time. A
blanking circuit turns off the electron beam at the end of the sweep so the return trace is not
visible. Due to repetitive tracing of the viewed waveform, we get a continuous display because
of persistence of vision. However, for getting a stable stationary display on the screen, it is
essential to synchronize the horizontal sweeping of the beam with the input signal across the
Y-plates. The signal will be properly synchronized only when its frequency equals the generator
frequency. In general, for proper synchronization of time-base with the signal, the condition
is

TSW = nTsig

where Ts jg is the time period of the signal and n is an integer.

Voltage

Vmax

0 Tsig Time

Fig. 11.2 Sawtooth waveform

 Digital Circuits & Design 253

11.4 BLOCK DIAGRAM OF CRO

The block diagram of a typical oscilloscope is shown in Fig. 11.3. The CRT itself needs dc
voltages for operation. The functions of components are as follows :

Fig. 11.3 Block diagram of CRO

Cathode ray tube (CRT): It displays the quantity being measured.
Vertical amplifier (Y) : The voltage signal which is to be measured is applied to the input of
the amplifier. The Y-amplifier is a device which multiplies a voltage which is then fed to the
Y-plates of the CRT. The multiplying factor is known as the gain of the amplifier. The gain of
the amplifier can be varied in steps by means of a control knob on the front panel (volts/cm
for each gain position). The Y-amplifier gain control can adjust the height of the trace pattern.
Horizontal amplifier (X) : The time base voltage (sawtooth) is fed to the X-plates through
an X-amplifier. Horizontal amplifier is used to cause a deflection proportional to a signal at the
horizontal terminal. The X-amplifier gain control can adjust the width of the trace.
Sweep generator : It produces a sawtooth voltage and causes a horizontal deflection of the
spot proportional to time. It is triggered to start at the left of the screen at a particular instant
on the internal vertical signal (“Int”), the external signal (“Ext”), or the ac supply (“Line”).
Trigger circuit: It is used to start the horizontal sweep of a specific instant with respect to
the waveform under observation. Triggering or synchronization is achieved by making a
connection between the Y-amplifier and the time base. Synchronization has to be done to
observe a stationary pattern on the screen.
An intensity control varies the accelerating potentials in the electron gun and a focus
control determines the potentials on the focusing electrodes.
Power Supply
The power supply block has two sections. High Voltage (HV) section and Low Voltage
(LV) section.
254 Basic Electronics
The power supply unit provides the voltages required by CRT to generate and accelerate
an electron beam and voltages required by other circuits of CRO such as vertical amplifier,
horizontal amplifier, etc.
The high voltage section provides high voltages of the order of 1 kV to 2 kV. Since the
negative voltages have the following advantages, they are also required by CRT :
1. The accelerating anodes and the deflection plates are close to ground potential. This
ground potential protects the operator from electric shocks.
2. Since the deflection voltages are measured with respect to ground, blocking or coupling
capacitors are not necessary.
3. Insulation required between CRO controls and chassis is less.
The low voltage section provides the voltage for the heater of the electron gun.
Basically, the oscilloscope is a high impedance voltmeter that shows the waveform of the ac
signal. The input impedance is typically 1 MΩ shunted by 20 pF.
11.5 FRONT PANEL CONTROLS OF CRO
On the front panel of CRO, there are several types of controls, knobs and switches.
Some controls rotate smoothly through almost a full circle, some of these have a switch
(click) action when they are turned fully anti-clockwise. Then others are rotary switches
having several set positions and other switches have a slide action and some are push buttons.
The numerous controls on the CRO are grouped into three sets, each set operating on
one section of a CRO.
1. Cathode ray tube controls
2. Y-amplifiers
3. Time base and trigger
11.5.1. Cathode Ray Tube Controls
(a) ON Power : It is a toggle switch used for switching ON or OFF power.
(b) Intensity Control : Intensity control potentiometer changes the grid potential with
respect to cathode. The grid potential determines the amount of electrons leaving the
cathode and thus controls the intensity of the beam, from zero to maximum.
(c) Focus Control : The focusing anode acts like a lens whose focal length can be
changed. Focusing of the spot is obtained by changing the potential of the focusing
anode. Hence it controls the sharpness of the trace.
(d) Astigmatism : It is an additional focusing control. By successive adjustment of
focus and astigmatism controls, the spot can be focused correctly in the centre and
also at the edges of the screen.
11.5.2. Vertical Section
(a) Vertical Scale : This control sets the vertical scale, i.e., it determines how much the
 Digital Circuits & Design 255

spot will be deflected by an input signal applied to vertical input (Y) terminals. The
units are either volts per centimeter or volts per division.
(b) Invert: This control inverts the applied input signal.
(c) Position : This control enables the movement of the display along the y-axis.
(d) X 10 : When this switch is pushed IN, the gain of the vertical (Y) amplifier is increased
ten-fold (X 10), i.e., in all positions of the volts/cm switch, the gain is increased 10
times.
(e) Vertical Coupling : It selects coupling to the vertical amplifier. In dc mode, it directly
couples the signal to the input. In ac mode, it couples the signal to the input through a
capacitor. In ground position, the input to the attenuator is grounded, whereas Y-input
is isolated.
(f) Vertical Mode Control : This control serves for the vertical section of the scope as
a whole.
(g) Balance Control : It is a preset control. This is adjusted so that the display does
move vertically when V/cm control is switched between various settings.
11.5.3 Horizontal Section
(a) Time Base Control : Most of the CRO applications involve measurement or display
of a quantity which varies with time. The spot has to move at a constant velocity which is
achieved by a linear time base generator. The time base control is claiberated in terms of
time / cm or time / division.
(b) X-Position : This control enables the movement of display along the x-axis.
(c) Synchronization:
In order to present a stationary display on the screen, the sweep generator signal must be
forced to run in synchronization with the vertical input signal. If synchronization is not
done, the pattern is not stationary. The trigger circuit helps to achieve a ‘stationary trace’.
There are various signals which can be applied to the trigger circuit. The signals can be
selected using a synchronization selector switch. There are three sources for synchronization
which can be selected by the synchronizing selector :
(i) Internal : The trigger is obtained from the signal being measured through the vertical
amplifier.
(ii) External: An external trigger source is also used to trigger the signal being measured.
(iii) Line : The input to the trigger circuit is obtained from ac mains (230 V, 50 Hz). The
INT/EXT switch selects internal or external signal.
(d) Sweep Selector : When the sweep selector switch is in the internal position, the
horizontal amplifier receives an input from the saw tooth generator which is triggered by
256 Basic Electronics
the synchronous amplifier. The external signal also can be applied to the horizontal deflection
system by keeping a sweep selector switch in the external position. There are four basic
types of sweep.
(i) Free running (ii) Triggered (iii) Driven and (iv) Non saw tooth sweep.
(f) Intensity (z-axis) Modulation : Intensity modulation is done by inserting a signal
between the ground and the cathode (or control grid). Z-axis modulation is applied during
normally visible portion of the trace. It can be used for brightening the display.
(g) Trigg. Level : This control selects the mode of triggering. In auto position, the time
base line is displayed in the absence of input signal.
(h) Horizontal Input : It connects the external signal to horizontal amplifier.
11.6 LISSAJOUS FIGURES
It two sine waves are applied simultaneously to the vertical and horizontal deflecting
plates of a CRO, the light spot on the screen would trace a definite pattern. The patterns
obtained on the screen are called Lissajous figures. The shape of the Lissajous pattern
depends on frequency, amplitude and phase relationships of the two sine waves. Lissajous
patterns are named after the man who first used them. The horizontal internal sweep is not
used.
Both the vertical and horizontal
deflection signals have equal
amplitude. Patterns can be predicted
by plotting X and Y deflections from
the two signals at corresponding Signal
Signal
instants of time. generator Y X
generator

Two sine waves of the same

frequency and amplitude may produce
a straight line, an ellipse or a circle
depending on their phase difference,
shown in Fig. 11.5. Fig-11.4 Circuit to obtain Lissajous figures
Lissajous figures are used for :
i) Determining an unknown frequency by comparing it with a known frequency.
ii) Comparing the phase relationship of two sine waves.
iii) Calibrating an audio oscillator with a known frequency signal and
iv) Checking audio amplifiers and feedback networks for phase shift.
Let two sine waves vH = Vm sin cot and vH – Vm sin (ωt + φ) be applied across the
horizontal and vertical deflection plates. The Lissajous patterns obtained are shown in Fig.
11.5.
 Digital Circuits & Design 257

Lissajous Figures
Lissajous Pattern
Vertical deflection
Voltage vv = Vm sin (ωt+φ)

0 = 00
0 0 0 = 1350 or
2250

0 = 450 or 31500
0 0 0 = 1800

0 = 900 or 2700 Horizontal deflection

0
voltage vH = Vm sin ωt

Fig. 11.5 Lissajous figures

11.7 CRO MEASURMENTS
The various parameters such as voltage, current, period, frequency, phase, amplitude,
peak to peak value, duty cycle, etc., can be measured using CRO.
11.7.1 Study or Examination of waveforms
To study the waveform of any signal, the signal should be applied to vertical input terminals
Y. The size of the signal displayed on the screen can be adjusted suitably by adjusting the
gain controls. The sweep voltage is applied to X-plates using internal sweep circuitry.
11.7.2 Measurement of amplitude of AC / DC voltage
An illuminated scale dividing the screen into 1 cm divisions permits use of the CRO as a
voltmeter. Each centimetre is further divided into five parts. In order to measure any
vertical deflection, it is essential to know exactly where the trace starts from i.e., its zero
level.
An AC voltage is measured by applying
it to the vertical plates (Y) and sweep is
applied to the horizontal plates(X) using
internal sweep circuitry. The distance the spot
moves in, say, the Y direction is directly
proportional to the voltage applied to the Y-
plates, For example, if 10 V moves the spot
by 1 cm, 30 V will deflect it by 3 cm. Thus Fig. 11.6 Waveform on CRO screen
258 Basic Electronics
the CRT responds to voltage and if we know the sensitivity (number of cm deflection per
volt) then we can measure the unknown voltage by measuring the distance the spot is
deflected.
Measuring the length of the vertical line and multiplying this length with the deflection
sensitivity gives the peak to peak value of the ac voltage.

volts No. of divisions

Vpeak − peak = × = 2 Vm
division 1

Vpeak − peak Vm
Vrms = =
2 2 2
If the observed spot deflection is 5.2 cm, the input voltage is calculated as
2 Vm = VP − P = 10 V cm × 5.2 cm = 52 V

2 Vm 52
Vrms = = = 19.30V
2 2 2 2
If the observed spot deflection is 5.2 cm, the input voltage is calculated as
The value of the dc voltage is obtained by measuring the displacement of the spot and
multiplying it with the deflection sensitivity.
Current can also be measured by measuring voltage across a known resistance.

SI. Volts RMS voltage

Gain Height 2 Vm
Waveform peak - peak
No. Volts / cm cm Vrms =
Vpp = 2Vm 2 2
1 1
2 2
3 3
11.7.3 Measurement of Time Period
A calibrated sweep generator permits time measurement. The waveform must be displayed
in such a manner that one complete cycle is displayed on the screen. For example, with the
sweep generator set at 5 ms/cm, two events separated on the screen by 2 cm are separated
in time by 10 ms or 0.01 second. In general, time period is given by

time No. of divisions

Time period, T= ×
division cycle
From Fig. 11.6, T = 5 ms/cm × 5.8 cm = 29 ms

1
Frequency, f=
T
 Digital Circuits & Design 259

Time-base 1 cycle Calculated Signal generator

Sl. Periodic
speeds occupies cm frquency frequency
No. Time T
ms / cm f = 1/THz setting Hz
1
2
3

Fig. 11.7 and Fig. 11.8 Waveforms on CRO screen

11.7.4 Measurement of Frequency

The unknown signal whose frequency is to be measured is connected to the vertical
plates and the calibrated signal source to the horizontal plates. The frequency of this voltage
is varied till a suitable stationary pattern is obtained on the screen. The number of
intersections or points are individually counted. The frequency ratio is given by
f v No. of po int s of horizontal frequency
=
fH No. of po int s of vertical frequency

No. of po int s of on horizontal

Unknown frequency, f v = f H × No. of po int s on vertical

fv 1
In Fig. 11.9 (a) = or 1 : 1 i.e, fv = 3fH
fH 1

fv 3
In Fig. 11.9 (b) = or 1 : 1 i.e, fv = 3fH
fH 1

(a ) f v = f H ( b) f v = 3 f H 1 2
(c) f v = fH (d ) fv = fH
Fig. 11.9 2 3
260 Basic Electronics

fv 2 1
In Fig. 11.9 (c) = or 1 : 1 i.e, fv = f
fH 1 2 H
fv 3 2
In Fig. 11.9 (d) = or 1 : 1 i.e, fv = f
fH 2 3 H
11.7.5 Measurement of Phase angle
If two sinusoids of the same frequency are connected to X and Y terminals, the phase
difference is revealed by the resulting pattern (Fig. 11.10). For voltages vx = Vx sin ωt and
vy = Vy sin (ωt + θ), it can be shown that the phase difference is
y1 x1
sinθ = =
y2 x2
where y1 is the Y-axis intercept and y2 is the maximum vertical deflection. Similarly, x1 is
the X-axis intercept and x2 is the maximum horizontal deflection. The phase difference
between two voltages is given by

θ = sin −1
FG y IJ = sin FG x IJ −1
Hy K Hx K
1 1

2 2

Y2= 4
Y1 = 3
x1 X

(a ) θ = sin −1
FG 3IJ LM FG 0IJ OP LM FG 15. IJ OP LM FG 3IJ OP
H 4K ( b) 00 θ = sin −1
H 3K Q ( c) 300 θ = sin −1
N H 3 KQ (d ) 900 θ = sin −1
N H 3K Q
x2 N
Fig. 11.10
The parameters of the circuit are useful in determining whether the angle is leading or
lagging.
11.7.6 Current Measurement
Since CRO is basically voltage measuring device, current can be measured by passing it
through a known standard resistance. The voltage across the resistance is displayed on
V
the V screen and is measured. Using Ohm’s law, 1 = , the current can be calculated.
R
11.8 APPLICATIONS OF CRO
Cathode ray oscilloscope is the most useful single piece of electronic equipment and is
extensively used for trouble shooting. Some of its uses are listed below :
 Digital Circuits & Design 261

1. In Radio Work
i) to trace and measure a signal throughout the RF, IF and AF channels of radio
and television receivers,
ii) it is used to adjust FM receivers, broadband high-frequency RF amplifiers and
AFC circuits.
iii) to trace visual display of waveshapes such as sine waves, square waves and
their many different combinations.
iv) to trace transistor curves,
v) to display the response of tuned circuits, etc.
vi) to visually show the composite synchronized circuit.
vii) to test AF circuits for different types of distortions and other spurious oscilla-
tions.
2. Scientific and Engineering Applications
i) measurement of ac/dc voltages,
ii) finding B-H curves for hysteresis loop,
iii) for engine pressure analysis,
iv) study of stress, strain, torque, acceleration/etc,
v) frequency and phase determination by using Lissajous figures,
vi) radiation patterns of antenna.
vii) amplifier gain.
viii) modulation percentage.
ix) complex waveforms as a short-cut for Fourier analysis,
x) standing waves in transmission lines, etc.
11.9 SWEEP-FREQUENCY GENERATORS
A sweep frequency generator is a special type of signal generator which generates a
sinusoidal output whose frequency is automatically varied or swept between two selected
frequencies. One complete cycle of the frequency variation is called a sweep. The rate at
which the frequency is varied can be either linear or logarithmic, depending upon the
design of a particular instrument. However the amplitude of the signal output is designed to
remain constant over the entire frequency range of the sweep.
Sweep-frequency generators are primarily employed for measurement of responses
of amplifiers, filters, and electrical components over various frequency bands. The frequency
range of a sweep-frequency generator usually extends over three bands, 0.001 Hz - 100
kHz (low frequency to audio), 100 kHz : 1,500 MHz (RF range), and 1-200 GHz (microwave
range). Performance of measurement of bandwidth over a wide frequency range with a
manually tuned oscillator is a time-consuming task. With the use of a sweep-frequency
262 Basic Electronics
generator, a sinusoidal signal that is automatically swept between two chosen frequencies
can be applied to the circuit under test and its response against frequency can be displayed
on an oscilloscope or X-Y recorder.
Thus the measurement time and effort is considerably reduced. Sweep generators
may also be employed for checking and repairing of amplifiers used in TV and radar
receivers.
The block diagram of an electronically tuned sweep frequency generator is shown in
fig. 11.11.
The main component of a sweep-frequency generator is a master oscillator, usually an RF
type, with several operating ranges which are selected by a range switch. The frequency
of the output signal of the signal generator may be varied either mechanically or electronically.
In the mechanically varied models, the frequency of the output signal of the master oscillator
is varied (tuned) by a motor driven capacitor.

Block Diagram of An Electronically Tuned Sweep Frequency Generator

Fig. 11.11
In the electronically tuned models, the frequency of the master oscillator is kept fixed
and a varying frequency signal is produced in another oscillator, called the voltage controlled
oscillator (VCO). The VCO contains an element whose capacitance depends upon the
voltage applied across it. This element is employed for varying the frequency of the
sinusoidal output of the VCO. The output of the VCO is then combined with the output of
the master oscillator in a special electronic device, called the mixer. The output of the
mixer is sinusoidal, whose frequency depends on the difference of frequencies of the
output signals of the master oscillator and VCO. For example, if the master oscillator
frequency is fixed at 10.00 MHz and the variable frequency is varied between 10.01 MHz
to 35 MHz, the mixer will give sinusoidal output whose frequency is swept from 10 KHz to
25 MHz.
 Digital Circuits & Design 263

The sweep rates of sweep frequency generators can be adjusted to vary from 100 to
0.01 seconds per sweep. A voltage varying linearly or logarithmically according to sweep
rate can be used for driving the X-axis of an oscilloscope or X-Y recorder synchronously.
In the electronically tuned sweep generators, the same voltage which drives the VCO
serves as this voltage.
The frequency of various points along the frequency-response curve can be interpolated
from the values of the end frequencies if it is known how does the frequency vary.
11.10 BLOCK DIAGRAM OF STANDARD SIGNAL GENERATORS
The signal generator, like an oscillator, is a source of sinusoidal signals but the signal
generator is also capable of modulating its sinusoidal output signal with other signals. This
is the main difference between the two instruments (signal generator and oscillator). When
the signal generators are employed for producing an unmodulated sinusoidal output they
are said to be producing CW (continuous height wave) signal. When the produced output
signal is modulated, the modulating waveforms may be either externally applied sine-waves,
square waves, triangular waves, pulses or more complex signals, as well as internally
generated sine-waves. Amplitude modulation (AM) or frequency modulation (FM) may
be used. Normally amplitude (AM) modulation is employed. Principles of amplitude
modulation (AM) and frequency modulation (FM) are illustrated in fig. 11.12.

(a) Unmodulated or (b) AM Signal (c) FM Signal

CW signal
Fig : 11.12 : Signal Modulation
Signal generators are primarily employed for providing appropriate signals for
calibration, testing and troubleshooting of the amplifier circuits used in communication,
electronics such as radio and television amplifiers. They are also employed for measurement
of characteristics of antennas and transmission lines.
Block diagram of a signal generator is shown in fig. 11.13. An RF oscillator is employed
for generating a carrier waveform whose frequency can be adjusted typically from about
100 kHz to 30 MHz. Carrier wave frequency can be varied and indicated with the help of
a range selector switch and a vernier dial setting. Range is selected by employing frequency
dividers. Frequency stability of oscillator is kept very high at all frequency ranges.
Following measures are taken in order to achieve stable frequency output. 1. Frequency
of output voltage changes with the change in supply voltage so regulated power supply is
used.
264 Basic Electronics

Fig. 11.13 : Block Diagram of An AM Signal Generator

2. Buffer amplifiers are used to isolate the oscillator circuit from output circuit so that
any change in the circuit connected to the output does not affect the frequency and
amplitude of the oscillator output.
3. Temperature also causes change in oscillator frequency, so temperature compensating
devices are used.
4. Q-factor of L-C circuit should be very high, say above 20,000. This can be achieved
by employing quartz crystal oscillator in place of L-C oscillator.
An audio-frequency modulating signal is generated in another very stable oscillator, called
the modulation oscillator. Provision is made in the modulation oscillator for changing the
frequency and the amplitude of the signal being generated.
In this oscillator provision is also made to get various types of waveforms such as the
square, triangular waves or pulses. The radio-frequency and the modulation-frequency
signals are fed to a wide-band amplifier, called the output amplifier. Percentage of modulation
can also be adjusted and it is indicated by the meter.
Modulation level can be adjusted upto 95% by a control device. The output of the amplifier
is then fed to an attenuator and finally the signal goes to output of signal generator. Output
meter is provided to read the final output signal.
The accuracy to which the frequency of the RF oscillator is known is an important
specification of the signal generator performance. Most laboratory type models are usually
calibrated to be within 0.5 - 1.0% of the dial setting. This accuracy is usually sufficient for
most measurements. For greater accuracy, if needed, a crystal oscillator, whose frequency
is known to be within 0.01% or better, may be used as an internal RF calibration source.
Another key specification of signal generators is their amplitude stability. It is very important
that the amplitude of the output signal remains constant as the RF frequency is varied.
11.11 PULSE AND SQUARE-WAVE GENERATORS
These generators are often employed with an oscilloscope as the measuring device.
The waveforms displayed by the oscilloscope either at the output or at pertinent points in
the system under test provide qualitative as well as quantitative information about the
system or device under test.
 Digital Circuits & Design 265

These generators are designed for generating a periodic train of equal-amplitude pulses, as
shown in fig. 11.14 (a). In pulse generators, the duration of the on time of a pulse may be
independent of the time between pulses. However, if the pulse train has the property of
being on 50 per cent of the time and off-50 per cent of the time, as illustrated in fig.11.14(b),
the waveform is called the square wave and the generators producing such waveforms
are called the square—wave generators.

(a) Ideal Pulse Train (b) Square- Wave Signal

Fig. 11.14
Thus square-wave generators can be considered to be a special class of pulse generators.
Square-wave generators are used for investigating the low frequency characteristics
of a system including testing of audio-systems. Square-waves are also preferred over
short-duration pulses if the transient response of a system needs a comparatively high
settling time.
Pulse-Characteristics and Terminology. For describing the output of pulse
generators and the applications in which they are used, the introduction of terminology
associated with the pulses is very important. The first group of such terms denotes the
characteristics of ideal rectangular pulses whereas the second group provides measures
of the deviation from the shape and periodicity of ideal pulses.
1. Period is defined as the time duration in seconds between the start of one pulse and
the start of the next one.
2. Frequency (or pulse repetition frequency) is the reciprocal of the period.
3. Amplitude is defined as the peak value of the voltage and polarity of the pulse.
4. Pulse width is defined in terms of time duration of the pulse in seconds.
5. Duty Cycle is defined as the ratio of the pulse width to the period or pulse repetition
time. It is expressed in per cent of the period. The duty cycle for square waves is of
50 percent.
However, real pulses and pulse trains only approximate the characteristics of their
ideal counterparts. So some additional terms are used for describing the non-ideal aspects
of real pulses. These terms along with their definitions are given below and illustrated in
fig. 11.15.
266 Basic Electronics

Fig : 11.15 Pulse Characteristics

The base line is referred to the dc level and is the line at which the pulse starts and
ends. The shift of this line from zero volt, or the expected value is called the base line
offset.
The amplitude of the pulse is measured from the base line to the steady state value of
the pulse.
1. Rise Time. The time the pulse takes to increase form 10 per cent to 90 per cent of its
normal amplitude is called the rise time.
2. Fall Time. The time the pulse takes to decrease from 90 per cent to 10 per cent of its
normal amplitude is called the fall time.
3. Overshoot is the extent, in terms of per cent of pulse normal amplitude, to which the
pulse surpasses its correct value during the initial rise.
4. Ringing is the positive and negative peak distortion, excluding overshoot. It is expressed
in percent of pulse amplitude.
5. Sag or Droop is the fall, in terms of per cent of pulse amplitude, in the pulse amplitude
taking place during the pulse width.
6. Pulse Jitter is a measure of short term instability of one event with respect to another,
such as instability in the starting time, the pulse width or the pulse amplitude. It is
usually expressed as a percentage of the main parameter.
Pulse generators are designed to generate pulses as close to ideal pulses as possible.
High-quality pulses ensure that any distortion in the output pulse from a test circuit is owing
to test circuit alone. The amplitude, pulse width, and period of the generated pulses are
usually adjustable over various ranges. The duty cycle is also made adjustable; but in case
the power contained by each pulse is large, the maximum duty cycle must be kept small.
 Digital Circuits & Design 267

As the maximum duty cycle of a pulse generator is reached, the waveform of the pulse
becomes irregular or the pulse width no longer increases.
The output impedance of the pulse generator is an important consideration in fast
pulse systems. This is so because the generator, which has a source impedance matched
to the connecting cable, will absorb reflections resulting from impedance mismatches in
the external circuitry. If it is not so, total absorption would not take place, a portion of the
pulse would be re-reflected, and spurious pulses would appear to be generated from the
pulse generator.
DC coupling of the output circuit is necessary when retention of the dc bias levels in
the test circuit is desirable, inspite of variations in pulse width, pulse amplitude, or pulse
repetition rate (PRR).
There are two types of circuits which are generally used in pulse generation. These
circuits are active or pulse generating circuits and passive or pulse shaping circuits.
Active generators are the relaxation type oscillators which make use of charge-and-
discharge action of capacitor for controlling the conduction of a vacuum tube or a transistor.
Multivibrators and the blocking oscillators are common types of relaxation oscillators.
In passive type circuits, a sine-wave oscillator is employed as the basic generator and
its output is passed through a pulse-shaping circuit to have the desired waveform. For
instance, an approximate square-waveform may be had by first amplifying and then clipping
a sine-wave.

Fig. 11.16 Circuit Diagram

A circuit for converting a sine-wave from an oscillator into a pulse train is shown in
fig.11.16. The amplifier is saturated between two limits, by the sine-wave, and the sharpness
of the pulse depends upon the magnitude of sine-wave relative to dc bias, and the amplifier
gain. This circuit can also be employed for cleaning up of a pulse input having undershoots,
overshoots rings etc.
268 Basic Electronics
Applications. Some of the important applications of pulse generators are given below:
1. Measurement of rise times of amplifiers, oscilloscopes, and electrical components.
2. Measurement of rise times and switching times of digital circuits and components,
such as diodes, transistors etc., used in digital circuits.
3. For providing very narrow pulses to circuits whose response to impulse excitation is
to be determined.
4. For triggering such devices as sweep-waveform generators.
5. For providing pulses of varying widths to determine the minimum energy required for
triggering such devices as SCRs.
11.12 FUNCTION GENERATORS
A function generator is a signal source that has the capability of producing different
types of waveforms as its output signal. The most common output waveforms are sine-
waves, triangular-waves, square-waves, and sawtooth-waves. The frequencies of such
waveforms may be adjusted from a fraction of a hertz to several hundred kHz.
Actually the-function generators are very versatile instruments as they are capable
of producing a wide variety of waveforms and frequencies. In fact, each of the waveform
they generate are particularly suitable for a different group of applications. The uses of
sinusoidal outputs and square-wave outputs have already been described in the earlier
Arts. The triangular-wave and sawtooth-wave outputs of function generators are commonly
used for those applications which need a signal that increases (or reduces) at a specific
linear rate. They are also used in driving sweep oscillators in oscilloscopes and the X-axis
of X-Y recorders.
Many function generators are also capable of generating two different waveforms
simultaneously (from different output terminals, of course). This can be a useful feature
when two generated signals are required for particular application. For instance, by providing
a square wave for linearity measurements in an audio-system, a simultaneous sawtooth
output may be used to drive the horizontal deflection amplifier of an oscilloscope, providing
a visual display of the measurement result. For another example, a triangular-wave and a
sine-wave of equal frequencies can be produced simultaneously. If the zero-crossings of
both the waves are made to occur at the same time, a linearly varying waveform is available
which can be started at the point of zero phase of a sine-wave.
Another important feature of some function generators is their capability of phase-
locking to an external signal source. One function generator may be used to phase lock a
second function generator, and the two output signals can be displaced in phase by an
adjustable amount. In addition, one function generator may be phase locked to a harmonic
of the sine-another function generator. By adjustment of the phase and the amplitude of
 Digital Circuits & Design 269

Fig. 11.17 Block Diagram of Function Generator

the harmonics, almost any waveform may be produced by the summation of the fundamental
frequency generated by one function generator and the harmonic generated by the other
function generator. The function generator can also be phase locked to an accurate
frequency standard, and all its output waveforms will have the same frequency, stability,
and accuracy as the standard.
The block diagram of a function generator is given in fig 11.17. In this instrument the
frequency is controlled by varying the magnitude of current that drives the integrator. This
instrument provides different types of waveforms (such as sinusoidal, triangular and square
waves) as its output signal with a frequency range of 0.01 Hz to 100 kHz.
The frequency controlled voltage regulates two current supply sources. Current supply
source 1 supplies constant current to the integrator whose output voltage rises linearly with

z
time according to output signal voltage equation υ out = −1 i dt . An increase or decrease
C 0
t

in the current increases or reduces the slope of the output voltage and thus controls the
frequency.
The voltage comparator multivibrator changes state at a predetermined maximum
level, of the integrator output voltage. This change cuts-off the current supply from supply
source 1 and switches to the supply source 2. The current supply source 2 supplies a
reverse current to the integrator so that its output drops linearly with time. When the output
attains a predetermined level, the voltage comparator again changes state and switches on
to the current supply source 1.
The output of the integrator is a triangular wave whose frequency depends on the
current supplied by the constant current supply sources.
The comparator output provides a square wave of the same frequency as output.
The resistance diode network changes the slope of the triangular wave as its amplitude
changes and produces a sinusoidal wave with less than 1% distortion.
270 Basic Electronics
11.13 DIGITAL MULTIMETERS
Digital multimeter (DMM) is basically a digital voltmeter and may be used for the
measurement of voltage, current (dc or ac) and resistance. All quantities other than dc
voltage are first converted into an equivalent dc voltage by some device.
The block diagram of a basic digital multimeter is given in fig. 11.18.

Fig.11.18 : Block Diagram of Digital Multimeter

For measurement of ac voltage the input voltage is converted into a dc voltage by
means of a rectifier. A compensated attenuator is employed. Many manufacturers provide
the same attenuator for both dc and ac measurements.
For measurement of resistance a constant current, depending on the range, supplied
from a battery or a constant current source is passed through the resistance under
measurement and the voltage developed across it is measured. The resistance value is
displayed in ohms.
For measurement of current, the
un- 100 known current is passed
through a precision resistor in many
commercial digital multimeters and the
voltage developed across the precision
resistor is measured. The current value
is displayed in mA.
For measurement of current, a
current-to-voltage converter may also Block Diagram of Current-To-Voltage
be used, as illustrated by block diagram Converter Fig. 11.19
in fig. 11.19.
The current under measurement is applied to the summing junction at the input of the
op-amp. The current in the feedback resistor IR is equal to the input current IIN because of
very high input impedance of the op-amp. The current IR causes a voltage drop across one
of the resistors, which is proportional to the input current IIN. Different resistors are employed
for different ranges.
 Digital Circuits & Design 271

Specifications of Digital Multimeters

Ranges : DC voltage upto 1,000 V in 5 ranges
AC voltage upto 750 V in 5 ranges
DC current upto 10 A in 5 ranges
AC current upto 10 A in 5 ranges
Resistance upto 200 MΩ in seven ranges
Basic Accuracy : 0.5% for dc voltages
1% for ac voltages
1% for dc current
1.2% for ac current
0.8% for resistance.
1
Display : 3digits, LCD
2
Power Source : 9 V battery.

SHORT QUESTIONS AND ANSWERS

Q.1. For what vertical and horizontal plates are provided in a CRO ?
Ans. Horizontal and vertical plates are provided between electron gun and screen to deflect the
beam according to the input signal.
Q.2. For what purpose a triggering circuit is provided in a CRO ? Ans. In a CRO, a triggering
circuit is provided for synchronising two types of deflections so that horizontal deflection
starts at the same point of the input vertical signal each time it sweeps.
Q.3. What are the essential components of a CRT ? Ans. The essential components of a CRT are
electron gun, focusing and accelerating anodes, horizontal and vertical deflection plates and
evacuated glass envelope with phosphorescent screen.
Q.4. For what electron gun assembly is provided in a CRT ?
Ans. The sole function of an electron gun assembly in a CRO is to provide a narrow and sharply
focused electron beam which is accelerated towards the phosphor screen.
Q.5. Why is the grid in a CRO provided with a hole in it ?
Ans. The hole in a grid of a CRO is provided to allow passage for electrons through it and concen-
trate the beam of electrons along the axis of the tube.
Q.6. What is meant by the deflection sensitivity of a CRO ? Ans. The deflection sensitivity of a
CRO is defined as the vertical deflection of the beam on the screen per unit deflecting
voltage.
Q.7. What is meant by the deflection factor of a CRO ?
Ans. The deflection factor of a CRO is the reciprocal of the deflection sensitivity.
Q.8. Name any two applications of CRO.
Ans. Measurement of phase .difference and frequency of a voltage signal.
ppp
272 Basic Electronics

Digital Electronics Principles

12CHAPTER

12.1 INTRODUCTION
Digital means having to do with numbers. Digital systems operate on numbers that
represent some real logical or arithmetic function. More appropriate for students of
electronics and computers, digital systems are systems that process discrete information.
Discrete means distinct or separated as opposed to continuous or connected. Analog systems
process information that varies continuously. Digital system employs devices which operate
only in two states, the OFF state and the ON state. Each of the two states is discrete and
the two states are designated as logic 1 and logic 0 state. Since the allowed states are only
two, they are known as binary states. In logic, a statement is characterised as TRUE or
FALSE.
As digital devices and digital circuits operate in the binary number system (0 and 1), they
make it possible to use Boolean Algebra as a mathematical tool for analysis and design of
digital circuits and system. George Boole in 1854 invented a new kind of algebra known as
Boolean algebra. Table 12.1
Boolean algebra, the algebra of logic
Logic 0 Logic 1
is the mathematical framework upon
which logic design is based and it is False True
used in the description, synthesis and Off On
analysis of binary logical functions. A Low High
Boolean variable is a quantity that may No Yes
be equal to either 0 or 1. In the digital Open switch Closed switch
logic field, several other terms are Down Up
used synonymously with 0 and 1. Cold Hot
Some of the more common ones are
South North
shown in Table 12.1.
12.2 NUMBER SYSTEM
We are familiar with the number system in which count is upto ten numerals. So its
base is 10 and ten numerals 0, 1, 2...9 are used for expressing any arbitrary number. This
number system is popularly known as the decimal number system. For writing any number
 Digital Circuits & Design 273

exceeding 9, an array of numerals (digits) are used. Each position of numeral is assigned a
well defined meaning. Decimal numbers are used to represent quantities outside the digital
system. There are some other systems also to represent numbers. Some of the other
commonly used number systems are: binary, octal and hexadecimal number systems.
The binary number system is the most important one in digital systems, but others are also
important. Binary (base-2) number system is extensively used in digital systems like digital
computers which operate on binary information. Octal (base-8) system has certain
advantages in digital work as it needs less circuitry to get information into and out of a
digital system. Moreover, it is easier to read, record and print out octal numbers than binary
numbers. Hexadecimal (base-16) number system is particularly suited for microcomputers.
12.3 DECIMAL NUMBER SYSTEM
The decimal number system, as already mentioned above, has a base of 10 and is a position-
value system. The statement ‘the decimal number system has a base of 10’ implies that it
contains ten unique symbols (or digits) i.e. 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. The ten digits do not
limit us to express only ten different quantities because we use the various digits in appropriate
positions within a number to indicate the magnitude of the quantity. For expressing quantities
exceeding nine, two or more digits are used, and the position of each digit within the
number indicates the magnitude it represents. The placement of the digits in the sequenced
order from right to left is understood to carry a specific meaning.
12.4 BINARY NUMBER SYSTEM
The binary number system is simply another way to count. It is less complicated than the
decimal number system because it is composed of only two digits 0 and 1. Just as the
decimal system with its ten digits is a base-10 system, the binary system with its two digits
is a base-2 system. These two digits namely 0 and 1 carry the same meaning as in the
decimal system but different meaning is given to the position occupied by the numeral or
digit. In a binary system, the base is 2, so any number can be expressed by an array of
numerals representing the co-efficients of power of 2 and not 10. In a binary system, the
weight of each successively higher position (to the left) is an increasing power of 2.
12.4.1. Counting in Binary
To learn to count in binary, let us first look how we count in decimal number system.
We start counting from 0, 1, 2, 3 and upto 9. After 9 we write 0 with 1 on its left side i.e.
10. Now we have two digit number. To continue counting, first digit of number i.e. 0 is
again changed upto 9 and after that it is written 0 and second digit of number (which was
earlier 1) is written 2. Thus we get number 20. This way we count the number upto 99. In
further counting the number digit 99 is changed to 00 with digit 1 on the left side of these
digits added. So we get number 100. This is the way of counting and writing down the
numbers in decimal number system.
A comparable situation occurs when counting in binary, except that we have only two
digits. Counting is started with zero and, ended with next number 1. After 1 there is no
other digit in this system so in further counting, digit 1 is replaced by 0 with digit 1 on its left
274 Basic Electronics
side i.e. 10. Next number follows 11. Again after number 11 digit 00 is written with digit 1
on the left side i.e. 100. This way we count in binary system. Table 12.2 shows the equivalent
binary numbers of decimal numbers from 0 to 15. This Table makes us more clear about
binary number system.
TABLE 12.2
Table Showing Equivalent Binary Number of Decimal Number
Decimal Number Equivalent Binary Decimal Number Equivalent Binary
Number Number
0 0000 8 1000
1 0001 9 1001
2 0010 10 1010
3 0011 11 1011
4 0100 12 1100
5 0101 13 1101
6 0110 14 1110
7 0111 15 1111

12.4.2 Binary-To-Decimal Conversion

The binary number system is a positional system where each binary digit (bit) carries
a certain weight based on its position relative to the least significant bit (LSB). The right-
most bit is the LSB in a binary number and has a weight of 20 = 1. Any number can be
converted to its decimal equivalent simply by adding the products of each bit and its
weight. For example
10011 = 1 (24) + 0 (23) + 0 (22) + 1 (21) + 1 (20) = 16+ 0 + 0 + 2 + 1 = 19
Example 12.1 : Convert (110110)2 to its decimal equivalent.
Solution:
Binary weight : 25 24 23 22 21 20
Weight value : 32 16 8 4 2 1
Binary number : 1 1 0 1 1 0
So (110110)2 = l × 32 + l × 16 + 0 × 8 + 1 × 4 + 1 × 2 + 0 × 1 = (54)10
The subscripts 2 and 10 identify that they are respectively binary and decimal numbers.
12.4.3 Binary Fractions
So far, we have discussed binary integers (whole numbers). Fractional numbers can
also be represented in binary by placing bits to the right of the binary point, just as fractional
decimal digits are placed to the right of the decimal point. The column weights of a binary
number are
2n .... 22 21 20 2–1 2–2 2–3... 2–n
binary point
 Digital Circuits & Design 275

This indicates that all the bits to the left of the binary point have weights that are
positive powers of two, as previously mentioned, but all bits to the right of the binary point
−1
have weights that are negative power of two, or fractional weights 2 =
FG 1 IJ
H 21
etc
K
Binary fractional number can also be converted into decimal fractional numbers. Let
us take, for example, a binary fractional number 0.1001.
It can also be written as
0.1001 = 1 (2–1) + 0 (2–2) + 0 (2–3) + 1 (2–4)
and after solving the above expression, we get
0.1001 = 1 (0.5) + 0(0.25) + 0 (0.125) + 1 (0.0625) = 0.5625
So decimal equivalent of binary fractional number 0.1001 is 0.5625.
Mixed binary number can be converted into a decimal number by converting integer
binary number and fractional binary number individually as described above.
Example. 12.2 : Convert the binary fractional number 0.1101 into its decimal equivalent.
Solution: Binary weight 2 –1 2 –2 2–3 2–4
Weight value 0.5 0.25 0.125 0.0625
Binary number 1 1 0 1
Decimal equivalent 1 × 0.5 + 1 × 0.25 + 0 × 0.125 + 1 × 0.0625 = 0.8125 Ans.
Example 12.3 Convert the binary number 110.111 into its equivalent decimal number.
Solution: 110.111 = 1 × 22 + 1 × 21 + 0 × 20 + 1 × 2–1 + 1 × 2–2 + 1 × 2–3
= 4 + 2 + 0 + 0.5 + 0.25 + 0.125 = 6.875 Ans.
12.4.4 Decimal to Binary Conversion
There are several methods for converting a decimal number to a binary number. The
first method is simply to subtract values of powers of 2 which can be subtracted from the
decimal number until nothing remains. The value of highest power of 2 is subtracted first,
then the second highest and so on.
Example 12.4 : Convert the decimal integer 29 to the binary number system.
Solution: First the value of highest power of 2 which can be subtracted from 29 is found. This
is 24 = 16.
Then, 29 – 16 = 13
The value of highest power of 2 which can be subtracted from 13, is 23, then 13 – 23 =
13 – 8 = 5. The value of highest power of 2 which can be subtracted from 5, is 22. Then
5 – 22 = 5 – 4 = 1. The remainder after subtraction is 1 or 20. Therefore, the binary
representation for 29 is given by
2910 = 24 + 23 + 22 + 20
276 Basic Electronics
= 16 + 8 + 4 + 0 × 2 + 1
= 1 1 1 0 1
[29]10 = [11101]2
Similarly,
[25.375]10 = 16 + 8 + 1 + 0.25 + 0.125
= 24 +23+ 0 + 0 + 20 + 0 + 2–2 + 2–3
[25.375]10 = [11011.011]2
This is a laborious method for converting numbers. It is convenient for small numbers
and can be performed mentally, but is less used for larger numbers.
Double-Dabble Method
A popular method known as double-dabble method also known as divide-by-two
method, is used to convert a large decimal number into its binary equivalent. In this method,
the decimal number is repeatedly divided by 2, and the remainder after each division is
used to indicate the co-efficient of the binary number to be formed. Notice that the binary
number derived is written from the bottom up.
Example 12.5 : Convert 19910 into its binary equivalent.
Solution: 199 ÷ 2 = 99 + remainder 1 (LSB)
99 ÷ 2 = 49 + remainder 1
49 ÷ 2 = 24 + remainder 1
24 ÷ 2 = 12 + remainder 0
12 ÷ 2 = 6 + remainder 0
6÷2 = 3 + remainder 0
3÷2 = 1 + remainder 1
1÷2 = 0 + remainder 1 (MSB)
The binary representation of 199 is, therefore, 11000111. Checking the result we
have
[11000111]2 = 1 × 27 + 1 × 26 + 0 × 25 + 0 × 24 + 0 × 23 + 1 × 22 + 1 × 21 + 1 × 20
= 128 + 64 + 0 + 0 + 0 + 4 + 2 + 1
∴ [11000111]2 = [199]10
Notice that the first remainder is the LSB and last remainder is the MSB. This method will
not work for mixed numbers.
12.4.5 Decimal Fraction to Binary
The conversion of decimal fraction to binary fractions may be accomplished by using
several techniques. Again, the most obvious method is to subtract the highest value of
negative power of 2, which may be subtracted from the decimal fraction. Then, the next
highest value of negative power of 2 is subtracted from the remainder of the first subtraction,
and this process is continued until there is no remainder or to the desired precision.
 Digital Circuits & Design 277

Example 12.6 : Convert decimal 0.875 to a binary number.

Solution: 0.875 – 1 × 2–1 = 0.875 – 0.5 = 0.375
0.375 – 1 × 2–2 = 0.375 – 0.25 = 0.125
0.125 – l × 2–3 = 0.125 – 0.125 = 0
∴ [0.875]10 = [0.111]2
A much simpler method of converting longer decimal fractions to binary consists of
repeatedly multiplying by 2 and recording any carriers in the integer position.
Example 12.7 : Convert 0.694010 to a binary number.
Solution: 0.6940 × 2 = 1.3880 = 0.3880 with a carry of 1
0.3880 × 2 = 0.7760 = 0.7760 with a carry of 0
0.7760 × 2 = 1.5520 = 0.5520 with a carry of 1
0.5520 × 2 = 1.1040 = 0.1040 with a carry of 1
0.1040 × 2 = 0.2080 = 0.2080 with a carry of 0
0.2080 × 2 = 0.4160 = 0.4160 with a carry of 0
0.4160 × 2 = 0.8320 = 0.8320 with a carry of 0
0.8320 × 2 = 1.6640 = 0.6640 with a carry of 1
0.6640 × 2 = 1.3280 = 0.3280 with a carry of 1
We may stop here as the answer-would be approximate.
∴ [0.6940]10 = [0.101100011]2
If more accuracy is needed, continue multiplying by 2 until you have as many digits as
necessary for your application.
Example 12.8 : Convert 14.62510 to binary.
Solution: First the integer part 14 is converted into binary and then, the fractional part 0.625 is
converted into binary as shown below :
Integer part Fractional part
14 ÷2 = 7 + 0 0.625 × 2 = 1.250 with a carry of 1
7÷2=3+1 0.250 x 2 = 0.500 with a carry of 0
3÷2=1+1 0.500 x 2 = 1.000 with a carry of 1
1÷2=0+1
12.5 OCTAL NUMBER SYSTEM
The number system with base (or radix) eight is known as the octal number system.
Although we can use any eight digits, it is customary to use the first eight decimal digits: 0,
1, 2, 3, 4, 5, 6, 7. There is no 8 or 9 in octal number code. These digits 0 through 7, have
exactly the same physical meaning as in decimal number system. The digit positions in
octal number have weights as follows.
278 Basic Electronics

84 83 82 81 80 8 –1 8 –2 8 –3 8 –4 8 –5
In digital systems, binary numbers are required to be entered and certain results or status
signals are required to be displayed. It is highly inconvenient to handle long strings of
binary numbers. It may cause errors also. Therefore, octal numbers are used for entering
the binary data and displaying certain information. The octal number system requires one-
third in length as compared to binary numbers. Thus from the users point of view, it
would be comparatively much easier to handle the input and output data of a digital computer
in octal form. Moreover, the print-outs are more compact and easy to read. Conversion
from binary-to-octal and octal-to-binary is also quick and simple. Infact, octal numbers are
used to represent binary numbers because of ease of conversion and compactness. Since
digital circuits can process only zeros and ones, the octal numbers have to be converted
into binary form employing special circuits known as octal-to-binary converters before
being processed by the digital circuits.
12.5.1 Octal-To-Decimal Conversion
An octal number can be easily converted to its decimal equivalent by multiplying each
octal digit by its positional weight. For example
3148 = 3 × (82) + 1 (81) + 4 (80)
= 192 + 8 + 4 = 20410
Another example 0.734 = 7 × (8–1) + 3 × (8–2) + 4 (8–3)
FG 119 IJ
= 0.875 + 0.046875 + 0.0078125 = (0.9296875)10 or 128 H K 10

12.5.2 Decimal-To-Octal Conversion

A decimal integer can be converted to octal by using the same repeated-division
method, called the double dabble method, that we used in the decimal-to-binary conversion,
but with a division factor of 8 rather than 2. The following examples will illustrate the
procedure.
Example 12.9 : Convert (1375)10 = ( )8
Solution :
8 1375
8 171 – 7
8 21 – 3
8 2 – 5
0 – 2
So equivalent octal number of (1375)10 is 2537
Note that first remainder becomes the least significant digit (LSD) of the total number, and
the last remainder becomes the- most significant digit (MSD).
 Digital Circuits & Design 279

Example 12.10 What is octal equivalent of the decimal fraction 0.685 ?

Solution: 0.685 × 8 = 5.48 = 0.48 with a carry of 5
0.48 × 8 = 3.84 = 0.84 with a carry of 3
0.84 × 8 = 6.72 = 0.72 with a carry of 6
0.72 × 8 = 5.76 = 0.76 with a carry of 5
0.76 × 8 = 6.08 = 0.08 with a carry of 6
The carries read downward give the octal fraction 0.53656 i.e. (0.685)10 = (0.53656)8
Ans.
12.5.3 Octal-To-Binary Conversion
Because 8 (the base of octal numbers) is the third power of 2 (the base of binary number),
the conversion from octal to binary can be performed by converting each octal digit to its
3-bit binary equivalent. The eight possible digits are converted as indicated below in Table
12.3.
TABLE 12.3
Octal Digit 0 1 2 3 4 5 6 7
Binary Equivalent 000 001 010 011 100 101 110 111
Using these conversions, any octal number can be converted to binary by individually
converting each digit. The following examples will illustrate the procedure.
Example 12.11 : Convert (5272)8 = ( )2
Solution : 5 2 7 2
↓ ↓ ↓ ↓
101 010 111 010
Hence (5272)8 = (101 010 111 010)2
Example 12.12 : Convert (37.13)8 into binary.
Solution: 3 7 . 1 2
011 111 . 001 010
Hence (37.12)8 = (01l 111.001010)2 Ans.

12.5.4 Binary-To-Octal Conversion

Conversion of a binary number to an octal number is simply the reverse of the foregoing
process. The bits of the binary number are grouped into groups of three bits starting at the
LSB. Then each group is converted to its octal equivalent. The following examples will
illustrate the procedure.
280 Basic Electronics
Example 12.13 : Convert the binary number 11011.1011 to its octal equivalent.
Solution: 11011.1011 → 01l 01l . 101 100
↓ ↓ ↓ ↓
3 3 . 3 3
i.e. (11011.1011)2 = (33.54)8 Ans.
Example 12.14 : Convert (11011100.101010)2 = ( )8
Solution: 11011100.101010
01l 011 100 . 101 010
↓ ↓ ↓
3 3 4 . 5 2
i.e. (110 11100.101010)2 = (334.52)8 Ans.
12.5.5 Octal Arithmetic
Normally Octal arithmetic operations using octal representation of numbers are not
performed. This number system is normally employed to enter long strings of binary data
into a digital system like a microcomputer. This makes the task of the operator easier.
Arithmetic operations can be performed by converting the octal numbers into binary numbers
and then using the rules of binary arithmetic. Following few examples are considered for
illustration.
Example 12.15 : Perform (1766)8 - (23)8 = (?)8
Solution: (1766)8 = (001 111 110 110)2
(23)8 = (010 011)2
So (1766)8 – (23)8= 001 111 110 110
010 011
001 111 100 011
(1766)8 – (23)8 = (1743)8 Ans.
12.6 HEXADECIMAL NUMBER SYSTEM
The binary number system forms the natural choice for the two-state systems. But in
this system, the numbers tend to get short rather long. Hence to reduce the length of a
given number it is quite common to use hexadecimal system. The hexadecimal system has
a base of 16 : that is, it is composed of 16 digits and characters. It uses the digits 0 through
9 plus the letters A, B, C, D, E and F. Since numeric digits and alphabets both are used to
represent the digits in the hexadecimal number system, therefore, this is an alphanumeric
number system. Table 12.4 shows the relationship between hexadecimal, decimal and
binary. It is important to note that hex (abbreviation for hexadecimal) digits A through F
are equivalent to the decimal values 10 through 15.
 Digital Circuits & Design 281

TABLE 12.4
Hexadecimal Decimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111
From the above Table it is observed that there are 16 combinations of 4-bit binary numbers
and sets of 4-bit binary numbers can be entered in the computer in the form of hexadecimal
(hex) digits. These numbers are required to be converted into binary representations using
hexadecimal-to-binary converter circuits before these can be processed by the digital
circuits.
This system is extensively used in microprocessor work.
12.6.1 Counting in Hexadecimal
How do we count in hexadecimal system once we get to F ? Simply start over with
another column and continue as follows
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1A, IB, 1C, ID, IE, IF
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D, 2E, 2F
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B and so on.
With two hexadecimal digits, we can count upto F F16, which is equal 25510. For
counting beyond this, three hexadecimal digits are required. For instance, 10016 is equal, to
25610, 10116 is equal to 25710 and so forth. The maximum three-digit hexadecimal number
is FFF16 which is equal to 409510.
12.6.2 Hexadecimal-To-Decimal Conversion
A hexadecimal number can be converted to its decimal equivalent by multiplying each hex
digit by its weight and then taking the sum of these products. The weights of a hex number
are increasing powers of 16 (from right to left). For a four-digit hex number the weights
are as follows:
163 162 161 161
4096 256 16 1
For illustration let us consider some examples.
282 Basic Electronics
Example 12.16 : Convert 34516 into decimal equivalent.
Solution: 34516 = 3 × 162 + 4 × 161 + 5 × 160
= 768 + 64 + 5 = (837)10 Ans.
Example 12.17 : Convert the following (ABC)16 = ( )10.
Solution : (ABC)16 = 10 × 162 + 11 × 161 + 12 × 160
= 2,560 + 176 + 12 = (2748)10 Ans.
Example 12.18 : Convert 2B.1FA into decimal equivalent.
Solution : (2B.1FA)16 = 2 × 161 + 11 × 160 + 1 × 16-1 + 15 × 16–2 + 10 × 16–3

1 15 10
= 32 + 11 + + + = (43.123535156)10 Ans.
16 162 163
12.6.3 Decimal-To-Hexadecimal Conversion
Repeated division of a decimal number by 16 will produce the equivalent hex number
formed by the remainder of each division. This is similar to the repeated division by 2 for
decimal-to-binary conversion and repeated division by 8 for decimal-to-octal conversion.
Following examples illustrate the procedure.
Example 12.19 : Convert 76810 into hexadecimal.
Solution : 16 768
16 48 – 0
16 3 – 0
0 – 3
So 76810 = 30016
Example 12.20 : Convert decimal number 374.37 to hexadecimal.
Solution :
1. Integer 374 16 374
16 23 – 6
16 1 – 7
0 – 1
So equivalent hex number of (374)10 is 176
2. Fraction 0.37
0.37 × 16 = 5.92 = 0.92 with a carry of 5
0.92 × 16 = 14.72 = 0.72 with a carry of 14
0.72 × 16 = 11.52 = 0.52 with a carry of 11
0.52 × 16 = 8.32 = 0.32 with a carry of 8
So equivalent fractional hex number of 0.37 is 0.5EB8
Hence 374.3710 = 176.5EB816 Ans.
 Digital Circuits & Design 283

12.6.4 Hexadecimal-To-Binary Conversion

Hex numbers can be converted into equivalent binary numbers by replacing each hex digit
by its equivalent 4-bit binary number. This procedure is illustrated below.
Example 12.21 : Convert hexadecimal 763 to its binary equivalent.
Solution: 7 6 3
↓ ↓ ↓
0111 0110 0011
Hence 76316 = 0111 0110 00112 Ans.
Example 12.22 : Convert the (524.36)l6 to its binary equivalent.
Solution: 5 2 4 . 3 6
↓ ↓ ↓ ↓ ↓
0101 0010 0100 . 0011 0110
Hence (524.36)16 = (0101 0010 0100 . 0011 0110), Ans.
12.6.5 Binary-To-Hexadecimal Conversion
Conversion from binary to hex is just the reverse of the process above. The binary
number is grouped into groups of 4-bits starting from LSB and moving towards MSB for
integer part and then each group of four bits is replaced by its hex representation. Zeros
are added, as required to complete a 4-bit group.
For the fractional part, the above procedure is repeated from the bit next to the
binary point and moving towards the right.
Example 12.23 Convert the following binary numbers to hexadecimal.
1001011010101 ; 1011000001
Solution: 100 101 101 0101 → 0001 0010 1101 0101
↓ ↓ ↓ ↓
4 2 D 5
i.e. (100 101 1010 101)2 = (12D5)16 Ans.
101 100 0001 → 0010 1100 0001
↓ ↓ ↓
2 C 1
i.e. (101 100 0001)2 = (2Cl)16 Ans
Example 12.24 : Convert the binary number 1010.0111 to its hexadecimal equivalent.
Solution: 1010.0111 → 1010 . 0111
A . 7
i.e. (1010.0111)2 = (A.7)16 Ans.
284 Basic Electronics
12.6.6 Conversion From Hex-To-Octal and Vice-versa
Hexadecimal numbers can be converted to equivalent octal numbers and octal
numbers can be converted to equivalent hex numbers by converting the hex/octal number
to equivalent binary and then to octal / hex respectively. The procedure is illustrated by the
following examples.
Example 12.25 : Convert (1375)8 = ( )2 = ( )l6
Solution: 1375 → 1 3 7 5
001 01l 111 101
i.e. (1375)8 = (001011111101)2 Ans.
Now 001011111101 → 0010 1111 1101
↓ ↓ ↓
2 15 13
↓ ↓ ↓
2 F D
i.e (1375)8 = (001011111 101)2 = (2FD)16 Ans.
Example 12.26 : Convert the following hexadecimal numbers to octal through binary.
(a) 7FD6 (b) ABCD
Solution : (a) 7FD6 → 7 F D 6
↓ ↓ ↓ ↓
0111 1111 1101 0110 → 111 111 111 010 110
7 7 7 2 6
So (7FD6)16 = (77726)8 Ans.
(b) ABCD → A B C D
↓ ↓ ↓ ↓
1010 1011 1100 1101→ 001 010 101 111 001 101
1 2 5 7 1 5
So (ABCD)16 = (125715)8 Ans.
12.6.7 Hexadecimal Arithmetic
The rules for arithmetic operations with hexadecimal numbers are similar to the rules for
decimal, octal and binary numbers. The information can be handled only in binary form in
a digital circuit and it is convenient and easier to enter the information using hex numbers.
Since arithmetic operations are performed by the digital circuits on binary numbers, therefore,
hex numbers are to be first converted into binary numbers. Following few examples illustrate
the procedure.
 Digital Circuits & Design 285

Example 12.27 : Add (5EA)16 and (ABC)16

Solution: 5EA16 = 0101 1110 1010
+ ABC16 = + 1010 1011 1100
10000 1010 0110→ 0001 0000 1010 0110
1 0 A 6
Thus (5EA)16 + (ABC)16 = (10A6)16 Ans.

12.7 BINARY OPERATIONS

We are familiar with the arithmetic operations such as addition, subtraction,
multiplication and division in a decimal number system. Similar operations can be performed
on binary numbers, infact, binary arithmetic is much simpler than decimal arithmetic because
here only two digits, 0 and 1 are involved.
12.7.1 Binary Addition
One method of addition of binary numbers is to convert binary numbers into decimal
numbers, add them and then again convert the resultant decimal number into binary number.
But this method is very time consuming and, therefore, we would discuss the direct and
time saving method.
There are four cases, described below for addition of binary numbers.
0+0=0
0+1=1
1+0=1
1 + 1 = 10
With the help of the above four cases, all binary numbers can be added.
Example 12.28 : Add 110011 to 101101
Solution: 1st column : 1 + 1 = 0 with carry 1
110011 2nd column : 1 + 0 = 1 combined with carry 1 = 0 with carry 1
101101 3rd column : 0 + 1 = 1 combined with carry 1 = 0 with carry 1
1100000 4th column : 0 + 1 = 1 combined with carry 1 = 0 with carry 1
5th column : 1 + 0 = 1 combined with carry 1 = 0 with carry 1
6th column : 1 + 1 + carry of 1 = 11
12.7.2 Binary Subtraction
Again for subtraction of binary numbers, four cases are required to be considered
while subtracting
0–0 =0
1–0 =1
1–1 =0
10 – 1 = 1
286 Basic Electronics
Example 12.29 : Subtract 0111 from 1001.
Solution : 1001 1st column : 1 – 1 = 0
– 0111 2nd column : 0 – 1 = 1 with a borrow of 1
0010 3rd column : 1 (after borrow) – 1 = 0
4th column : 0 (after borrow) – 0 = 0
Example 12.30 : Subtract 01011 from 10110.
Solution: 10110
– 01011
01011 Ans.
12.7.3 Binary Multiplication
Multiplication is performed in binary in the same way as with decimal numbers. It involves
forming the partial products, shifting each successive partial product left one place, and
then adding all the partial products. The four simple rules are as follows:
Rule 1 : 0 × 0 = 0
Rule 2 : 0 × 1 = 0
Rule 3 : 1 × 0 = 0 and
Rule 4 : 1 × 1 = l
Example 12.31 : Perform the arithmetic operation 11.01 × 10.11
Solution: 11.01
10.11
1101
1101
0000
1101
1000.1111 Ans.
12.7.4 Binary Division
Binary division is obtained as decimal division. A few examples will illustrate the procedure.
Example 12.32 : Divide 1110101 by 1001.
1101
Solution : 1001 1110101
1001
1011
1001
1001
1001
×
Ans : 1101
 Digital Circuits & Design 287

12.8 1’s COMPLEMENT REPRESENTATION

1’s complement of a binary number can be obtained by substituting 1’s by 0’s and 0’s
by 1. If a number is (11011001)2 then it’s 1’s complement is (00100110)2 .
12.8.1 1’s Complement Subtraction
Subtraction of binary numbers can be accomplished by using 1’s complement method,
which allows us to subtract using only addition. This method of subtraction is particularly
useful in arithmetic logic circuits because subtraction can be accomplished with an adder.
Also the 1’s complement of a number is easily obtained by inverting each bit in the number.
Steps for 1’s Complement Subtraction -
(i) Find 1’s complement of subtra-end
(ii) Add it to minuend
(iii) If there is a carry, then the carry is added to the sum part and the result is
positive.
(iv) If there is no carry, then the sum part is re-complemented and the result is
negative.
Example 12.33 : Perform the subtraction with the following binary numbers using 1’s
complement, (i) 11010 – 1101 (ii) 100 – 1100000.
Solution: Direct Subtraction 1’s Complement Subtraction
(i) 11010 11010
– 1101 + 0010 1’s complement of 1101
1101 1100
1 Add end around carry
1101 Ans.
(ii) 100 100
–110000 + 001111 1’s complement of 110000
–101100 010011 1’s complement of result
– 101100 Final result (No carry indicates
that the answer is negative and
in complement form)

12.9 2’s COMPLEMENT REPRESENTATION

The 2' complement of a binary number is obtained by adding 1 to the LSB of its 1’s
complement i.e.,
2’s complement = 1’s complement + 1.
Example 12.34 : Find the 1’s and 2’s complements of the following binary numbers.
0.101; 101.0
Solution: 1’s complement of binary number 0.101 is 0.010 Ans.
2’s complement of binary number 0.101 is 0.010 + 0.001 = 0.011 Ans.
 1’s complement of binary number 101.0 is 010 Ans.
2’s complement of binary number 101.0 is 010 + 1 = 01l Ans.
12.9.1 2’s Complement Subtraction
For subtracting a smaller number from a larger one by 2’s complement subtraction method,
the procedure applied is as follows :
1. Determine the 2’s complement of the smaller number.
2. Add the 2’s complement of the smaller number to the larger one.
3. Discard the carry (there is always a carry in this case).
For subtracting a larger number from smaller one by 2’s complement subtraction method,
the procedure applied is as follows :
1. Determine the 2’s complement of the larger number.
2. Add 2’s complement of the larger number to the smaller one.
3. There is no carry. The result is in 2’s complement and is negative.
4. For having result in true form, take 2’s complement and change the sign. Both of
the methods of complement subtraction have distinct advantages when implemented with
logic circuits because they allow subtraction to be accomplished by using only addition.
Both of the 1’s and the 2’s complements of a binary number are relatively easy to accomplish
with logic circuits; and the 2’s complement has an advantage over the 1’s complement in
that an end-around carry operation does not have to be performed.
Example 12.35 : Perform the subtraction of binary numbers using 2’s complement
11011 - 10100.
Solution: Direct Subtraction 2’s Complement Subtraction
11011 11011
– 10100 + 01100 2’s complement of 10100
00111 Drop carry 00111
00111 Ans.

Example 12.36. Perform (11011 - 100101) using 2’s complement method.

Solution : Direct Subtraction 2’s Complement Subtraction
11011 11011
–100101 + 011011 2’s complement of 100101
– 01010 110110 No carry;2’s complement of the result
– 01010
Ans.

ppp
Boolean Algebra & Logic Gates
13
CHAPTER

13.1 INTRODUCTION
Boolean algebra, named after its pioneer George Boole (1815-64), is the algebra of
logic applied in the design and analysis of digital systems. The rules of this algebra are
based on human reasonings.. It originated from the study of how we reason, what lines of
reasoning are valid and what constitutes proofs etc. Boolean algebra is a mathematical
system of logic in which truth functions are expressed as symbols and then these symbols
are manipulated to arrive at conclusion.
The basic logic elements are NOT gate, AND gate, OR gate and bistable multivibrator,
or flip-flop. Actually, the flip-flop can be constructed from combinations of basic logic
gates (i.e. NOT, AND, OR gates), but it is treated as a distinct logic element because of its
importance in digital systems.
13.2 BOOLEAN ALGEBRA
Ø According to this algebra the boolean constants and variables are allowed to have
only two possible values 0 or 1.
Ø In Boolean algebra fractions, decimals, –ve numbers, square roots, cube roots, logarithm
& imaginary numbers are not allowed.
Ø In Boolean there are only three basic operations
(i) Logic addition
(ii) Logic multiplication
(iii) Logic Complementation.
13.2.1 Boolean Algebra Laws
Three of the basic laws of Boolean algebra are the same as in ordinary algebra.
These are commutative laws, associative laws and distributive laws.
1. Commutative Laws. These laws of addition and multiplication say that this order in
which the variables are ORed or ANDed makes no difference as the same answer is
290 Basic Electronics
arrived at either way. These laws of addition and multiplication for two variables are
written algebraically as below :
Commutative law of addition of two variables : A + B = B + A
Commutative law of multiplication of two variables : A.B = B.A
2. Associative Laws. These laws of addition and multiplication say that in the ORing or
ANDing of several variables, grouping of the variables is immaterial and the results obtained
are the same. These laws of addition and multiplication for three variables are written
algebraically as below :
Associative law of addition of three variables : A + (B + C) = (A + B) + C
Associative law of multiplication of three variables : A . (B.C) = (A.B).C
3. Distributive Law. This states that ORing several variables and ANDing the result
with a single variable is equivalent to ANDing the single variable with each of several
variables and then ORing the products. This law is written algebraically as below
A . (B +C) =A . B + A . C
The above laws are familiar because they are the same as in ordinary algebra. It is to
be noted that these laws can be extended to include any number of variables.
13.2.2 Boolean Algebra Rules
Basic rules that are useful in manipulation and simplification of Boolean algebra expressions
are tabulated below in Table 13.1. We will now look at rules 1 through 9 of Table 13.1 in
terms of their application to logic gates. Rules 10 through 12 will be derived in terms of the
simpler rules and laws already discussed.
TABLE 13.5
Boolean Algebra Basic Rules
Rule No Rule Name of Rules
1 A+0=A OR Rules
2 A+1=1
3 A+A=A
4 A+A =1
5 A.0=0
6 A.1=A AND Rules
7 A.A=A
8 A. A =0

9 A =A Complementation Rule
10 A + AB = A
11 A + AB = A + B Absorptive Rules
12 (A + B) (A + C) = A + BC
 Digital Circuits & Design 291

13.2.3 Proof of Boolean Rules

1) A + 0 = A 2) A+1=1
Proof Proof
LHS : A + 0 LHS : A + 1
= A + AA = A+A+A
= A + (1 + A ) = A+A
= A ⋅1 = 1 = RHS
= A = RHS
3) A+A=A 4) A⋅ A = A

Proof Proof
LHS : A + A LHS : A ⋅ A + 0
= (A + A) ⋅ A = A⋅A + A⋅A
= (A + A) (A + A ) = A (A + A )
= A + A⋅A = A ⋅1
= A + 0 = A = RHS = A = RHS

5) A ⋅ 0 = 0 6) A ⋅1 = A
Proof : Proof :
LHS : A ⋅ 0 LHS : A ⋅1
= A ⋅ AA c
= A⋅ A + A h
= A⋅A = A + AA
= 0 = RHS =A+0
7) A+A =1 8) A⋅A = 0

These two can only be proved by truth table

A A A + A A⋅A
0 1 1 0 A+A =1
⇒
1 0 1 0 A−A =0

9) (A+B) (A+C) = A + BC
Proof :
LHS : (A + B) (A + C)
= A ⋅ A + A ⋅ C + A ⋅ B + BC
= A + AC + AB + BC
= A (1 + C + B) + BC
= A ⋅ 1 + BC
= A + BC RHS
292 Basic Electronics

10) A + AB = A + B
Proof :
LHS : A + AB
c hb
= A+A A+B g
= 1 (A + B)
=A+B RHS
11) A + AB = A
Proof :
LHS : A + AB
= A (1 + B)
= A ⋅1
=A RHS
12) A = A
Proof

e
LHS : A = A + 0 = A + AA = A + A A + A je j
e j e
= A + A ⋅1 = A + A j cA + A h
= A+AA
=A+0
=A RHS
13.2.4 Boolean Postulates
There are five basic postulates of Boolean algebra. A list of these postulates is given
below :
1 (a) If A = 1, then A = 0 1 (b) If A = 0, then A = 1
2 (a) 0.0 = 0 2 (b) 1+1=1
3 (a) 1.1 = 1 3 (b) 0+0=0
4 (a) 1.0 = 0 4 (b) 0+1=1
5 (a) 1 = 0 5 (b) 0=1
13.3 DE-MORGAN’S THEOREMS
There are two theorems given by De-Morgan’s,
A + B= A . B
A .B= A + B
The two theorem can be stated as below :
 Digital Circuits & Design 293

(i) The complement of the sum of two A B A + B A .B

or more variables is equal to the 0 0 1 1
product of the complements of the 0 1 0 0
1 0 0 0
variables. 1 1 0 0

(ii) The complement of the product of A B A .B A + B

two or more variables is equal to 0 0 1 1
the sum of the complements of the 0 1 1 1
variables 1 0 1 1
1 1 0 0

13.4 DUALITY THEOREM

The duality theorem is one of those elegant theorems proved in advanced mathematics.
Basically duality underlies all Boolean algebra. Each Boolean expression has its dual which is
as true as the original expression. The dual of a given Boolean expression can be obtained by
following the procedure given below :
1. Change each OR (+) sign to an AND (.) sign.
2. Change each AND (.) sign to an OR (+) sign.
3. Complement any 0 or 1 appearing in the expression.
Some of the Boolean relations and their duals, for future reference, are given below
Relation Dual Relation Relation Dual Relation
A+0=A A.1=A A + (B + C) = (A + B) + C A . (B . C) = (A . B) . C
A+1=1 A.0=0 A (B + C) = AB + AC A + B . C = (A + B) . (A + C)
A+A=A A.A=1 A+B=AB AB = A + B
A+ A =1 A. A =0 A + AB = A A (A + B) = A
A+B=B+A A.B=B.A A+ A B=A+B A ( A +B) = A . B
13.5 STANDARD REPRESENTATIONS FOR LOGICAL FUNCTIONS
Logical functions are expressed in terms of logical variables. The values assumed by the
logical functions as well as the logical variables are in the binary form. Any arbitrary logic
function can be expressed in the following two forms.
1. Sum-of-products (SOP) form.
2. Product-of-sums (POS) form.
This does not mean that the logic function cannot be written in any other form. It can
be written in various forms but the above two forms are conveniently suited in arriving at the
standard methods for designing the circuits.
13.5.1 Sum-of-Products (SOP) Form
A product of two or more variables or their complements, in Boolean algebra, is simply the
AND function of those variables. The product of two variables can be expressed as AB, the
product of three variables ABC, and so on. Similarly a sum in Boolean algebra is the same as
294 Basic Electronics
the OR function. So a sum-of-products expression is two or more AND functions ORed
together. For instance AB + BC + CD is sum-of-products expression. Following are the some
other examples of expression in SOP form.

AB + AB + AB
AB + ABC + BC
AB + BCD
ABC + DEF

A SOP form can also contain a term with a single variable, such as A + AB + BC
One reason the SOP is a useful form of Boolean expression is the straight forward
manner in which it can be implemented with logic gates.
13.5.2 Product-of-Sums (POS) Form
The product-of-sums (POS) form can be thought of as the dual of the sum-of-products
(SOP). It is, in terms of logic functions, the AND of two or more OR functions. For instance
(A + B) (C + D) is a product-of-sums expression. Several other examples of POS are:
(A + B) ( A + B)
(A + B ) (A + B + C) (B + C)
(A + B) (B + C + D)
(A + B + C) (D + E + F + G) (A + E + G)
A product-of-sum expression can also contain a single variable term, such as
A ( B + C ) (B + C)
POS form also lends itself to straight forward implementation with logic gates because it
involves simply ANDing two or more ORed terms.
13.6 LOGIC GATES
Ø These are the Logic circuits that form the building blocks of complex digital systems
which can do arithmetic and logic functions.
Ø They can accept one or more input voltages but with one output voltage.
Ø They work on basis of Boolean algebra.
Ø The logic gates are

→ NOT U|
→ AND → V| Basic gates
→ OR W
→ NAND U|
→ NOR |V → Derived gates.
→ X − OR |
→ X − NOR |W
 Digital Circuits & Design 295

13.6.1 NOT Gate

Ø It performs a basic logic function called inversion or complementation.
Ø The purpose of inverter is to change one logic level to opposite level.
Ø This gate has only one input and one output.
Truth table

Input Output A Y=A

A A
0 1 Y→output
(symbol)
13.6.2 AND Gate
Ø It performs logic multiplication, know as AND function.
Ø It may have two or move no.of inputs. But one output.
Truth table
A Y = A.B
inputs Output B
A B Y = A⋅B (Symbol
0 0 0
0 1 0
1 0 0 A B
1 1 1 (Electrical
output Equivalent)

Ø Here output will be " HIGH " If all inputs are " HIGH " othrewise " LOW "
13.6.3 OR Gate
Ø It performs logic addition, know as ‘OR’ function.
Ø It may have two or mores inputs but one output.
A

A
Y=A+B B

B
output

(Symbol) (electrical equivalent)

296 Basic Electronics
Truth Table
input Output
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

The output is " HIGH " if any of input is “HIGH” otherwise “LOW”.
13.6.4 NAND Gate
Ø The term NAND is a Contraction of NOT-AND & implies an AND function with
complemented output.
Ø Here output is “LOW” when all inputs are “HIGH” other wise “HIGH”
Ø It has minimum two inputs.

A
A Y = A⋅B AB Y = AB
B
B
(Symbol) (equivalent Circuit)

Truth table input Output

A B Y = AB
0 0 1
0 1 1
1 0 1
1 1 0
13.6.5 NOR Gate
Ø The term NOR is a contraction of NOT-OR & implies an OR function with
complemented output.
Ø Here the output is “HIGH” when both inputs are LOW, otherwise LOW.
Ø It has minimum two inputs.
A A
Y=A+B A+B A+B

B B
(Symbol) (equivalent Circuit)
 Digital Circuits & Design 297

Truth table input Output

A B Y=A+B
0 0 1
0 1 0
1 0 0
1 1 0

13.6.6 Exclusive - OR (X - OR) Gate

Ø This gate produce the output, “HIGH” when the inputs have odd no. of 1’s.
Ø It has minimum two inputs.

A
Y=A⊕B
B

Ø Here the expression for output is, Y = A ⊕ B = AB + AB

A

Y=A⊕B

Ø Truth table input Output

A B Y = A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

Ø This is know as even parity-checker in equality comparator or detector.

298 Basic Electronics
13.6.7 Exclusive-NOR (X-NOR) Gate
Ø It is the complement of X-OR gate.
Ø It's out put is “HIGH” when number of 1’s in the inputs is odd.

Y = A ⋅ B =A ⊕ B
Ø

Ø Y = A ⋅ B = AB + A B

Y=A ⋅ B

Ø Truth table input Output

A B Y=A ⋅ B
0 0 1
0 1 0
1 0 0
1 1 1

Ø It is also known as odd parity checker circuit.

13.7 UNIVERSAL GATES
Ø The logic gates, only with the help of which all other logic gates can be implemented,
known as universal gate.
Ø NAND & NOR are universal gates.
13.7.1 NAND as Universal Gate
Using NAND gate only, all other gates can be derived.
i) NOT
If ‘A’ is the input then output of NOT gate,

Y = A = A ⋅A
 Digital Circuits & Design 299

A
A A A

ii) AND
If A & B are imputs, then output is,
Y = A⋅B

e j
= A⋅B

A A AB = AB
AB AB
B
B
iii) OR
If A & B are inputs then output is,

Y = A+B= A+B= A⋅B

A
A A A+B
A+B

B B
B

iv) NOR

Here output is Y = A + B = NOT of A + Bb g

A
A
A A+B
A+B A+B

B
B
B

v) X-OR
Here output is Y = A ⊕ B = AB + AB
300 Basic Electronics

= AB + AB

= AB + AB

c h c h
= A A+B + A+B B

= A c ABh + c ABh B
A
A A A⊕B
A⊕B AB AB

B AB
B
B AB

vi) X-NOR
It is the not of X-OR.

A A
A⋅B A⊕B A⋅B

B B

13.7.2 NOR as Universal gate

Using NOR gate only all other logic gates can be implemented.
i) NOT
Here output is, Y = A = A + A
A
A A A

ii) OR

e
Here output is, Y = A + B = A + B j
A A
A+B A+B A+B=A+B

B B
 Digital Circuits & Design 301

iii) AND
Here output is, Y = A ⋅ B = A ⋅ B = A + B
A
A

A A⋅B
A.B

B
B
B
iv) NAND
It is the NOT of AND gate

A
A
A
A⋅B A⋅B A⋅B

B
B
B
v) X-NOR
Here output is Y = A ⋅ B = A ⊕ B = AB + AB

= A+ B+A+B

= A+AB+AB+B

b g b
= A+ A+B + A+B +B g
A
A + B = AB

A A A⋅B
A+B
B B

B A + B = AB
vi) X-OR
It is the NOT of X-OR Gate, So
302 Basic Electronics

A A
A⊕B A⊕B A⊕B

B B

Example 13.1 : Draw the logic circuit represented by the expression

Z = AB + A B + A BC
Solution : A circuit using gates can simply be designed by looking at the expression and finding out
the basic gates which can be used to realize the various terms and then connect these
gates appropriately.
In the given expression there are three input logical variables and Z is the output.

The first term AB is obtained by

ANDing A with B, as shown in fig.(a).
The second term A B is obtained by
using 2 INVERTERs and one AND
gate and connecting them, as shown
in fig. (b). The last term is obtained
by using one INVERTER and one
AND gate and connecting them, as
shown in fig. (c). Now the complete logic expression is realized by ORing the three outputs
of the arrangements explained above i.e by ORing. AB, A B and A BC . The gate network
representing the expression
Z = AB + A B + A BC is given in fig.(d).
Example 13.2 : Simplify the following expression using Boolean algebra technique.
Z = AB + A (B + C) + B (B + C)
Solution : Applying the distributive law to the second and third terms in the given expression, the
expression becomes
Z = AB + AB + AC + BB + BC
= AB + AB + AC + B + BC
= AB + AC + B +BC
= AB + AC + B (1 + C)
 Digital Circuits & Design 303

= AB + AC + B . l
= AB + AC + B
= B (1 + A) + AC
= B + AC Ans.
Example 13.3 : Show that
(i) ABC + A B C + AB C = A (B + C)
(ii) AB + ABC + A B +A B C = B + AC
(iii) AB + AC + B C = AC + B C
(iv) (A + B) ( A + C) = AC + A B
Solution: (i) ABC + A B C + AB C
= AC (B + B ) + AB C
= AC + AB C
= A (C + B C )
= A (C + B)
= A (B + C) Proved.
(ii) AB + ABC + A B + A B C
= AB + A B + ABC + A B C
= B (A + A ) + AC (B + B )
= B + AC Proved
(iii) AB + AC + B C
= AB (C + C ) + AC + B C
= ABC + AB C + AC + B C
= ABC + AC + AB C + B C

= AC (B +1) + B C (A + 1)
= AC + B C Proved
(iv) (A + B) ( A + C)
= A A + AC + B A + BC
= AC + B A + BC
Multiplying the third term BC by (A + A ), we have
304 Basic Electronics

= AC + B A + BC (A + A )
= AC + B A + ABC + A BC
= AC (1 +B) + B A (1 + C)
= AC + B A
= AC + A B Proved
Example 13.4 : Simplify the following expressions
(i) (AB + C) (AB + D)
(ii) A A + C ( A + C ) + AC
Solution: (i) (AB + C) (AB + D)
= AB . AB + AB . D + ABC + CD
= AA . BB + ABD + ABC + CD
= AB + ABD + ABC + CD
= AB (1 + D) + ABC + CD
= AB + ABC + CD
= AB (1 + C) + CD
= AB + CD Ans.

(ii) A . A + C ( A + C ) + AC
= 0 + C ( A + C ) + AC
= C ( A . C ) + AC
= C A C + AC
= 0 + AC = AC Ans.
Example 13.5 : (a) Draw a logic circuit to implement the Boolean Eqn. Y= AB + A B .
(b) Simplify the above equation and draw the logic circuit for the simplified equation.
Solution : (a) The logic circuit is shown in Fig. (a). It has two AND gates and one OR gate.
(b) Y = AB + AB = A ( B + B) = A .1= 1
 Digital Circuits & Design 305

The simplified equation does not require any gate. Just connect the output to the
input A. It is shown in Fig. (b).
Example 13.6 : (a) Draw a logic circuit to implement the function Y= AB+ A (B+ C) + B(B+ C).
(b) Simplify the function and draw logic circuit for the simplified function.
Solution : (a) The logic circuit is shown in Fig. (a). It requires 3 AND gates and 2 OR
gates.
(b) Y=AB + A(B+C) + B(B+C) = AB+AB + AC+BB+BC
= AB + AC + B + BC
or Y=AB+AC + B (1 + C)
= AB + AC + B . 1
= AB + AC + B
= B (A + 1) + AC = B .1 + AC
or Y= B + AC
Fig. (b) shows the logic circuit for Y= B + AC. It requires only 1 AND and 1 OR gate.

Example 13.7 : (a) Draw a logic circuit for the Boolean equation Y=AB + AC + BD+ CD.
(b) Simplify the expression and draw logic circuit for the simplified ex
pression.

Solution : (a) The logic circuit is shown in Fig. (a). It requires 4 AND gates and one OR
(b) Y=AB + AC+BD+CD
= A(B+C) + D(B+C)
= (A + D)(B+C)
Fig. (b) shows the logic circuit. It requires 2 OR gates and 1 AND gate.
306 Basic Electronics

Example 13.8 (a) Draw logic circuit for the expression Y=[A B (C+ BD) + A B ] C.
(b) Simplify the expression and draw logic circuit for the simplified expression.
Solution : (a) Fig. (a) shows the logic circuit.
(b) Y=[A B (C + BD) + A B ] C = [A B C+A B BD + A B ]C
= [ ABC + A .0. D + AB] C
= (ABC + 0 + A B) C
= A B CC + A B C
= ABC + A BC
= B C (A+ A ) + B C.A
or Y = BC

Fig. (b) shows the logic circuit for the simplified expression for the Fig. (a)
 Digital Circuits & Design 307

Example 13.9 : Devise a logic circuit for the function

Y = B.( A + C ) + A. B
Solution: Y = B.( A + C ) + A. B
= B. A + B. C + A . B
= A ( B + B) + B. C
= A + B. C
The logic circuit is shown in Figure given below.

Example 13.10 : Simplify the expression

Y = AB + A + AB

Solution: Y = AB + A + AB
= A + B + A + AB

= A + B + AB

=A + B + A

=A + A + B

=1 + B

=1
=0
Example 13.11 : Simplify the expression
Y= (A + B) ( A + C) (B + C)
Solution : Y= (A + B) ( A + C) (B + C)
= (A A + AC + B A + BC) (B + C)

= (AC + B A +BC)(B+C)
= ABC+BB A + BBC+ACC+B A C+BCC
308 Basic Electronics

= ABC + B A + BC + AC + B A C + BC
= ABC + AC + B A + B A C + BC
= AC (B + 1) + B A + BC ( A + 1)
or Y = AC + B A + BC
= AC + B A + BC (A + A )
= AC + B A + BCA + BC A
= AC (1 +B) + B A (1 + C)
= AC + B A
Example 13.12 : Simplify the expression
A = XY + XZ + XYZ( XY + Z)
Solution : A = XY + XZ + XYZ( XY + Z)
= XY + XZ + XXYYZ ( XY + Z)
= XY + XZ + XYZ
= XY + X + Z + XYZ
= XY + Z + X + XYZ
= XY + Z + X + YZ
= X + XY + Z + Y Z
= X+Y+ Z+Y
=1

Example 13.13 : Simplify XY + X + XY

Solution: XY + X + XY
= X + Y + X + XY
= X + Y + XY
= X+Y+Y
= X +1
=1
=0
 Digital Circuits & Design 309

Example 13.14 : XY + XYZ + X(Y + XY )

Solution: XY + XYZ + X(Y + XY )

= X( Y + YZ) + X(Y + XY )

= X( Y + Z) + X(Y + X)

= XY + XZ + X
= ( X + Y)( X + Z ) + X

= X X+ X Z+ XY+YZ+ X

= X+ X Z+ XY+YZ+ X

= X + (1 + Z + Y ) + Y Z + X
= X + YZ+X
=1=0

SHORT QUESTIONS AND ANSWERS

Q.1. What is Boolean algebra ?
Ans. Boolean algebra is a mathematical system of logic in which truth functions are expressed
as symbols and then these symbols are manipulated to arrive at conclusion.
Q.2. What is difference in Boolean algebra and ordinary algebra ?
Ans. Ordinary algebra deals with real numbers, which constitute an infinite set of elements
while Boolean algebra deals with undefined set of elements, B, where B is defined as a set
with only two elements, 0 and 1. Ordinary algebra does not include associative laws,
commutative laws and distributive law but Boolean algebra does. In Boolean algebra,
there are no additive or multiplicative inverses; thus, there arc no subtraction or division
operations. The NOT operator complement is not available in ordinary algebra.
Q.3. What are the basic logic elements ?
Ans. Basic logic elements are NOT gate, AND gate, OR gate and the flip-flop.
Q.4. What is a truth table ?
Ans. Truth table is a table that gives outputs for all possible combinations of inputs to a logic
circuit.
Q.5. Define positive logic and negative logic.
Ans. If the higher of the two voltages represents a 1 and the lower voltage represents a 0, the
logic is called a positive logic. On the other hand, if the lower voltage represents a 1 and
the higher voltage a 0, we have a negative logic.
Q.6. What is pulse logic system ?
Ans. A logic system in which a bit is recognised by the presence or absence of a pulse is called
a pulse or dynamic logic system.
Q.7. What is an inverter?
Ans. An inverter is a logic gate whose output is the inverse or complement of its input.
Q.8. What are the universal logic gates ?
Ans. Universal gate is a gate that can perform all the basic logical operations such as NAND
and NOR gates.
Q.9. What are basic logic gates and what are universal logic gates ?
Ans. Basic logic gates are AND gate, OR gate, and NOT (INVERTER) gate. Universal logic
gates are NAND and NOR gates.
Q.10. What is the speciality of NAND and NOR gates ?
Ans. The speciality of NAND and NOR gates is that they are universal gates and can perform
all the basic logical operations.
Q.11. Why NAND-NAND realization is preferred over AND-OR realization?
Ans. NAND-NAND realization needs only one type of gate (NAND), that minimizes 1C pack-
age counter.
Q.12. Why is a two-input NAND gate called universal gate?
Ans. NAND gate is called universal gate because any digital system can be implemented with
the NAND gate. Sequential and combinational circuits can be constructed with these
gates because element circuits like flip-flop can be constructed from two NAND gates
connected back-to-back. NAND gates are common in hardware because they are easily
available in the ICs form. A NAND gate is in fact a NOT-AND gate. It can be obtained
by connecting a NOT gate in the output of an AND gate.
Q.13. Distinguish between sum-of-products and product-of-sums.
Ans. Sum-of-products (SOP) is a logic expression in the form of ANDed terms ORed together
where as product-of-sums (POS) is a logic expression in the form of ORed terms ANDed
together.
Q.14. How many output functions are possible when we have n input variables ?
Ans. For n binary variables, we can have 2n distinct min terms. Since the function can be either
0 or 1 for each min term, and since there are 2n min terms, one can calculate the possible
functions that can be formed with n variables to be 2n. Thus, for n = 3
Number of min terms = 2n = 23 = 8
and Number of possible functions = 2 . 2n = 2 × 23 = 16.
Q.15. What is the use of De-Morgan’s theorem?
Ans. De-Morgan’s theorems are extremely useful in simplification of Boolean expressions in
which a sum or product of variables is inverted.

ppp
Digital Circuits & Design
14
CHAPTER

14.1 COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS

Logic circuits can be classified into two categories, i.e., Combinational Logic Circuits and
Sequential Logic Circuits. In a combinational logic circuit the output is a function of input
only at that instant. It does not have any memory. On the other hand a sequential logic
circuit has a memory. Its output depends on the present input as well as the past values of
output. The features of these two types of circuits are as under:

14.2 COMPARISON OF COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS

Combinational logic circuit Sequential Logic Circuit
1. It has one or more inputs and one or more
It has one or more inputs and one or more
outputs outputs
2. Its output is determined by the present
Its output is determined by the present
values of inputs only values of inputs as well as past values of
outputs
3. It does not have a memory It has a memory
4. It does not have a feedback path from It has a feedback path from output to
output to input input
5. Its operation can be described by a truth Its operation can be described by a truth
table table and timing diagram
6. It does not have a clock signal It may or may not have a clock signal.
Most sequential circuits have a clock
signal
7. Its action does not depend on clock Its action is governed by clock transition
transition
8. Its circuit is simpler than that of sequential Its circuit is more complex than that of
logic circuit combinational logic circuits
9. It is built using basic gates i.e., NOT, It is built using basic gates and
NAND, NOR. AND, OR, XOR gates combinational logic circuits
10. Its examples include adders, subtracters, Its examples include flip flops, counters
multiplexer, demultiplexer, decoder, shift registers etc.
comparator etc.
312 Basic Electronics
14.3 DESIGN PROCEDURE
A combinational logic circuit is designed to give a desired output for specified input
variables. Either a statement of the design problem is given or a truth table is given. If the
problem is given in the form of statement, the first step in design is to prepare a truth table.
The Boolean expression for the required circuit can be easily written down from the truth
table.
Consider the truth table shown in Table. 14.1
Table 14.1
A B Y
0 0 0
0 1 1
1 0 0
1 1 0

As per this truth table the output should be 1 only for one combination inputs
A = 0 and B= 1. An AND gate gives an output of 1 only if all its inputs are 1. Therefore,
the input A must be inverted before feeding it to AND gate. The resulting circuit is given in

Fig. 14.1.
As mentioned in chapter 3 NAND and NOR gates are universal gates and any logic
circuit can be designed using either of these two gates. NAND equivalent of Fig. 14.1 (a)
is shown in Fig. 14.1 (b).
The different combinations of two variables and the circuits to generate high output
are shown in Fig. 14.2.

Fig. 14.2. Logic circuits to general high output for various combinations of
two variables.

Consider the expression Y = AB + CDE

 Digital Circuits & Design 313

This expression has two terms and five

variables. AB are ANDed to give output AB.
Similarly, C, D. E are ANDed to give output
CDE. These two outputs are ORed to give
final output. The logic circuit is shown in Fig. Fig. 14.3
14.3.
Consider the truth table shown in Fig. 14.4 (a). The output is High for two combinations
of A and B. Each input combination must be so ANDed as to give High output.
This requires two NOT gates and two AND gates. The AND outputs must be ORed
to give final output. The logic circuit is shown in Fig. 14.4 (b). It is important to note that
this realization can be obtained by one XOR gate also.

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

Fig. 14.4. (a) Truth table (b) logic circuit

Consider the Boolean expression
Y = AB( C D + EF)
This expression has five inputs. Moreover, it is a hybrid expression (neither SOP nor
POS). Its implementation requires the following gates.
1. One NOT gate give D
2. Two 2 input AND gates to give CD and EF
3. One two input OR gate to give CD + EF
4. One two input AND gate to give AB
5. One two input AND gate to give Y.
The realization is shown in Fig. 14.5 (a).
Expression can be written as
Y = ABC D + ABEF

It is a SOP expression. It realization requires only four gates and is shown in

Fig. 14.5 (b).
314 Basic Electronics

Fig. 14.5
The above example shows that it is better to simplify the Boolean expression before
realizing it. The simplification can be done by the use of Boolean laws and Demorgan’s
theorems. Alternatively Karnaugh map can be used to simplify the expression.
The above discussion leads to the following steps for designing a combinational logic
circuit.
1. Prepare a truth table.
2. Write AND term for each case where output in the truth table is 1.
3. Write sum of products expression for the output.
4. Simplify the output expression.
5. Implement the circuit for the final expression using AND, OR, NOT gates.
6. Obtain an equivalent NAND/NOR realization if required.
Example 14.1 : Design a logic circuit which has three inputs A, B, C and gives a high
output when majority of inputs is high.
Solution : The design of this circuit can be done in the following steps.
1. Prepare a truth table. The output Y is 1 whenever, two or more inputs are 1,. Otherwise
output is 0.
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 or A BC
1 0 0 0
1 0 1 1 or A B C
1 1 0 1 or AB C
1 1 1 1 or ABC
 Digital Circuits & Design 315

2. Write AND terms when Y = 1. These terms have each input variable in either non-
inverted or inverted form. These terms are shown in truth table.
3. Write the output expression
Y = ABC + ABC + ABC + ABC
4. Simplify the expression
Y = A BC + A B C + AB C + ABC
= A BC + ABC + A B C + ABC + AB C + ABC
or Y = BC + AC + AB
5. Draw the logic circuit. This implementation required three AND gates and one OR
gate. Fig. 14.6 shows the logic circuit.

Fig. 14.6

Example 14.2 : Design a logic circuit having three inputs A, B, C such that output is 1 when
A = 0 or whenever B = C = 1. Also obtain logic circuit using only NAND gates.
Solution : The truth table is an under.
A B C Y
0 0 0 1 or A B C
0 0 1 1 or A B C
0 1 0 1 or A BC
0 1 1 1 or A BC
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1 or ABC
Y = A B C + A BC + ABC + A BC + ABC
= A B ( C + C) + A B ( C + C) +ABC
= A B + AB + ABC = A ( B + B) +ABC
= A + ABC = A + BC
316 Basic Electronics
Fig. 14.7. (a) Shows the logic circuit having AND, OR gates, NAND implementation is
shown in Fig. 14.7 (b).

(a) (b)
Fig. 14.7
14.4 HALF ADDER
The rules for binary addition are

0 0 1 1
+ 0 + 1 + 0 + 1
0 0 ← Sum 0 1←Sum 0 1←Sum 1 0←Sum
↑ ↑ ↑ ↑
Carry Carry Carry Carry
The 0 and 1 can represent numerical or logical values.
It is seen that binary addition generates a sum Sand carry C. In the four additions
shown above, carry is 0 in three of them and 1 in the last one. We can tabulate the above
additions in the truth table in Table 14.2.
Table 14.2. Truth table for half adder
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

The truth table leads to following logic equation for SUM (S) and CARRY (C)
S=AB+AB
C= AB
The expression for sum is the same as ths output of an exclusive OR gate with inputs
A and B. Thus S=A⊕B
A circuit with inputs A and B and outputs S & C is known as half adder. The logic
circuit is shown in Fig. 14.8 (a) and symbol in Fig. 14.8 (b).
Applications of half adder are very limited because it cannot accept a carry from a
previous addition. A full adder can do it.
 Digital Circuits & Design 317

Fig. 14.8

14.5 FULL ADDER

It is a type of Adder that does the A Sum
addition of two data bits with previous B
Full
carry, resulting a sum and carry bit. Adder Carryout
C in
(C0)
Fig. 14.9
Table 14.3. Truth table for adding A, B and a carry Cin*
Inputs Outputs
A B C in Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Carry + A + B Sum Carry out

S = A BCin + A BCin + A B Cin + A BCin

= A BC in + A BC in + A BC in + A BC in
= ( A B + A B) C in + ( A B + AB) C in
= (A ⊕ B ) Cin + (A ⋅ B ) Cin
= A ⊕ B ⊕ C in

C = A BC in + A B C in + ABC in + ABC in
= ( A B + A B) C in + AB (C in + C in )
= (A ⊕ B ) C in + AB
14.6 HALF SUBTRACTOR
318 Basic Electronics

(a) (Logic Diagram of Full Adder)

Fig. 14.10

(b) (Full Adder using two Half Adders)

The rules for binary subtraction are
1 Borrow
↓
0 0 1 1
–0 –1 –0 –1
0 1 1 0

It is a type of subtractor that does the subtraction of two

data bits resulting a difference and borrow bit
The truth table for half subtracter is given in Table 14.4.
Table 14.4. Truth table for half subtracter Fig. 14.11

Inputs Outputs
A B D B0
(Difference) (Borrow)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

From the table it is obvious that

D = A B+ A B
=A⊕B

and B0 = A B
 Digital Circuits & Design 319

So the logic diagram is -

Fig. 14.12

14.7 FULL SUBTRACTOR

A full subtracter has to take care of repeated borrow from the next higher bit. At any
stage along with the two bits (one of which is to be subtracted from the other) is another
input Bin, i.e., borrow bit from the previous stage of subtraction. Thus there are three
inputs and two outputs. The two outputs are difference Di and borrow B0.
Table 14.5. Truth table for full subtracter
Inputs Outputs
A B B in D B0
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

The Boolean expression for difference and output borrow is given as -

D = A BCin + A BCin + A BCin + A BCin A

D
= A BC in + A BC in + A BCin + A BCin B

= ( A B + A B) Cin + ( A B + AB) C in BD
= (A ⊕ B ) Cin + (A ⋅ B ) Cin
= A ⊕ B ⊕ Cin Bin (a)

B0 = A B Bin + A BBin + A BBin + ABBin

A A⊕B A⊕B⊕C
D
= A B Bin + ABBin + A BBin + A BBin H H
(A⊕B) Cin
B S AB S
= ( A B + AB) Bin + A B ( Bin + Bin ) Bin B0
= (A ⋅ B) Bin + A B
Fig. 14.13 (b)
320 Basic Electronics
14.8 2-BIT BINARY MULTIPLIER
It is the circuit that does multiplication of two binary numbers each of two bits.
Let two binary numbers are A (A1A0) & B (B1B0).
A A1 A0
× B × B B 1 0

A 1B 0 A 0B 1
C’

A1B A 0B 0

C S S’

M3 M2 M1 M0

So the logic circuit is -

A1
A 1B 1 M0

S’ M1
A0
A0 B 0 Half
Adder C’

B1 A 0B 1
M2
Half
A 1B 1 M3
B0 Adder
Fig. 14.14

14.9 MULTIPLEXER (MUX)

Ø It is a combinational digital circuit
that accepts several data inputs, I0 0
N :1 Y (output)
selects one of many inputs and M
connect it to the output. (Data inputs)
U
Ø One of many input is selected X
I N– 1 N–1
with the help of selection inputs.
Fig. 14.15
Ø It is also known as data selector. S0 S n–1
(Selection inputs)
 Digital Circuits & Design 321

Ø Let a MUX has ‘n’ no. of selection inputs & ‘N’ no. of data inputs or informations.
Then N < 2n.
But the MUX has only one output.
Ø The name of MUX is given by N : 1.
Ø It’s internal circuit consists of several AND gates with one multi-input OR gate.
Ø This is helpful in communication, when many informations are to be transmitted
through a single channel.
4 : 1 MUX I0
It has 4 data inputs, one output. 4:1
4 = 22 I1
M Y
So it has two selection lines. I2 U
Ø The data inputs are I0, I1, I2, I3 & X
I3
selection inputs are S1, S0.

Ø Truth table S1 S 0 Y S1 S0
0 0 I0 Fig. 14.16
0 1 I1
1 0 I2
1 1 I3

So Y = I 0 S1 S0 + I1 S1 S0 + I 2 S1 S0 + I 3 S1 S0
Ø The logic circuit is :-

I0
I 0 S1S0

I1
I 2 S1S0
Y
I2

I 2S1S0

I3
I3S1S0
Fig. 14.17
S1 S0
322 Basic Electronics
Example 14.3 : Implement AND gate using 2 : 1 MUX.
Solution : In AND gate Y = AB
But in 2 : 1 MUX,
I0
S Y 2:1
0 I0 M Y
I1 U
1 I1
X

So Y = I 0 S + I1S
S
If I 0 = S = A & I 1 = B

then Y = AA + BA
= AB
So implementation is →

A I0 2:1
M Y=AB
U
B I1 X
S

Example 14.4 : Implement OR gate using 2 : 1 MUX.

Solution : In OR gate Y = A + B
But in 2 : 1 MUX, Y = I 0 S + I1S
If I1 = S = A and I0 = B
then Y = BA + A.A

c hb
= A + AB = A + A A + B = A + B g
So implementation is -

2:1
B I0 Y
M
A U
I1 X
S
 Digital Circuits & Design 323

Example 14.5 : Implement X-OR gate using 2 : 1 MUX and an inverter.

Solution : In X-OR gate Y = AB + AB

In 2 : 1 MUX, Y = I 0 S + I1S

So By comparing I0 = A, I1 = A & S = B
So implementation is,

A
I0 2:1
Y= A⊕B
M
I1 U
X

S
B
14.10 DEMULTIPLEXER (D-MUX)
Ø It is the reverse of multiplexer.
Ø It has one Data input and many outputs. The data is connected to one of output,
selected by selection lines.
Ø It is also known as data distributor.
Ø It is named as 1 : N.
Ø If n = number of selection lines then N < 2n.
1 : 4 DMUX :
1:4 0 Y0
* Here one input and 4 outputs.
I D 1 Y1
* It requires two selection lines.
M
2 Y2
U
X 3 Y3
Truth table :
S1 S0
S1 S0 Y0 Y1 Y2 Y3 Fig. 14.18
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
324 Basic Electronics

Here Y0 = I S1 S0

Y1 = I S1 S0

Y2 = IS1S0

Y3 = IS1S 0

IS1S0 Y0

IS1S0 Y1

I
IS1S0 Y2

IS1S0 Y3

Fig. 11.19
S1 S0

14.11 SEQUENTIAL DIGITAL CIRCUITS

Logic circuits can be either combinational logic circuit or sequential logic circuits. The
different gates are used in combinational logic circuits. Arithmetic circuits, encoding and
decoding circuits multiplexing and demultiplexing circuits are all combinational logic cir-
cuits. Sequential logic circuits involve timing and memory devices. The basic building block
for a sequential circuit is a flip flop. Flip flops are combined to form counters, shift registers
and various memory devices.
Both latches and flip flops are similar. Both are bistable logic circuits and can reside in any
of the two stable states due to a feedback arrangement. The main difference between
them is in the method used for changing the state.
14.12 SYNCHRONOUS SYSTEM, EDGE TRIGGERING
The operations performed by a digital computer are very numerous and complex. Some
method is required to synchronise the different operations. This is done by using a master
clock. This clock provides a regulated pulse train. A sequential circuit (or system) solves a
sequence of combinational problems. Each sequence lasts for Enable one clock period.
 Digital Circuits & Design 325

Such a system is called

synchronous system and the
operation is termed as
synchronuous operation. An
alternative is asynchronous
operation which is not Fig. 14.20
satisfactory for digital system.
The transition from state 0 to state 1 is called leading or positive edge of the pulse. The
transition from state 1 to state 0 is called trailing edge of the pulse. The triggering of flip
flops can occur either at positive edge or negative edge. These two triggerings are called
positive edge triggering and negative edge triggering. The time during which the clock is at
logic 1 is called enable and the time during which the clock is at logic 0 is called disable.
This is shown in Fig. 14.20.
14.13 LATCHES AND FLIP FLOPS

Latch Flip Flop

Ø It is the sequential circuit that samples its Ø It is the sequential circuit that
input and produces output on the samples its input and produces
application of control input output on the application of clock
pulse.
Ø It may be synchronous or asynchronous. Ø It is always synchronous.
Ø It comparatively requires less no. of logic Ø It requires more no. of gates.
gates.
Ø It is faster Ø It is comparatively slower.
Ø It is sensitive to glitches Ø It is resistive to glitches.
14.14 FLIP FLOPS (F/F)
Ø These are building block of any sequential logic circuit.
Ø In any flip-flop, there are two types of inputs
- Synchronous
- Asynchronous
Ø Synchronous inputs depend on type of Flip Flop that, the depends on presence of clock
pulse.
Ø Asynchronous inputs are those for which output does not depend upon presence of
clock pulse. Once asynchronous input is activated the output suddenly changes
accordingly.
Ø There are two asynchronous inputs :-
(I) PRESET ( PR )
(II)CLEAR ( CR )
326 Basic Electronics

Ø PRESENT ( PR ) is active low, when it is activated, the output suddenly changes to

“HIGH”.
Ø CLEAR ( PR ) is also active low. When it is activated, the output changes to “LOW”.

PR CR Q Q
0 0 un det er min ed
0 1 0 1
1 0 1 0
Synchronous i / ps
1 1
are considered

Q → Uncomplemented output of the F/F

Q → Complemented output of the F/F

14.14.1 Types of Flip Flops
There are mainly four types of Flip Flops.
I) S – R F/F
II) J–K F/F
III) D F/F
IV) T F/F
14.14.2 S-R Flip Flop
Ø Here two synchronous inputs are S & R and two asynchronous inputs preset and
clear.

PR PR
S Q
S Q
S-R
Clk Flip Flop Clk
Q
R
Q
CR R CR

(a) (b)
Fig. 14.21
(Block diagram) (Internal / logic diagram)
 Digital Circuits & Design 327

Ø Truth table :

S R Q n +1 Q n +1 Condition
0 0 Qn Qn no change
0 1 0 1 Re set
1 0 1 0 Set
1 1 1 1 Invalid

Here Qn →Previous output

Qn+1 → Present output
Ø Due to its invalid condition, It is disadvantageous.
Ø It is the basic Flip Flop for other Flip Flops.
14.14.3 J-K Flip Flop
Ø Here J - K are synchronous inputs.
Ø The invalid condition of S-R Flip Flop is overcomed with the help of extra Feedback to
1st stage.
PR
PR

J Q n+1

J Q
J-K
Clk Flip Flop Clk
Q n+1
K Q
K

CR CR
(a) Block diagram Fig. 14.22 (b) Internal / logic diagram

Ø Truth Table : J K Q Q n +1 Condition

n +1

0 0 Qn Qn no change
0 1 0 1 Re set
1 0 1 0 Set
1 1 Qn Qn Toggle

Ø When both inputs are HIGH, then present output is complement of previous output. S
output continuously changes between 1 & 0, on application of clock pulse. So the
output toggles between 1 & zero. It is known as Toggling condition.
328 Basic Electronics
14.14.4 D Flip-Flop
Ø Here only one synchronous input i.e. D.

PR PR
D D
S
D Q Q
S-R
Flip Flop Flip Flop
Clk Clk
R
Q Q
CR
CR
(a) (Block diagram) Fig. 14.23 (b) (D-Flip Flop using
S-R Flip Flop)

Ø When D = 0, then S=0&R=1

D = 1, S=1&R=0
So Truth table is :-

D Q Q Condition
0 0 1 Re set
1 1 0 Set

Ø Here output is same as the input to D. So it is known as Data Flip-Flop. The data is
appearing at output after some delay. So it is also known as Delay Flip-Flop.
T Flip-Flop
Ø Here only one synchronous input i.e T.

Ø PR PR
J
T T Q
Q
T JK
Clk Flip-Flop Clk Flip-Flop
Q
Q K

CR CR

(a) (Block diagram) Fig. 14.24 (b) (T F/F using JK F/F)

 Digital Circuits & Design 329

Ø When T = 0 ⇒ J = 0, K = 0
T = 1 ⇒ J = 1, K = 1
So truth table is :

T Q n +1 Q n +1 Condition
0 Qn Qn no change
1 Qn Qn Toggle

Ø It is known as toggle Flip Flop as its output is continuously changing between 1

and 0.
14.14.5 JK Master Slave Flip Flop
This flip flop has two clocked SR flip flops. One of them is known as master and the
other one slave. Fig. 14.25 (a) shows the circuit. The master is positively clocked. Due to
the presence of inverter, the slave is negatively clocked. This means that when clock is high,
the master is active and the slave is inactive. When the clock is low, the master is inactive
and the slave is active. Fig. 14.25 (b) shows the symbol. This is a level clocked flip flop.
When clock is high, any changes in Jand K”mputs can affect S and R outputs. Therefore, J
and K are kept constant during positive half of clock. When clock is low, the master is
inactive and J and K inputs can be allowed to be changed. The different conditions are set,
reset and toggle. The race condition is avoided because of feedback from slave to the
master and the slave being inactive during positive half of clock.
To understand the set state, assume that Q is low (and Q is high). For high J, low K
and high CLK, the master goes to set state giving high S and low R. Since slave is inactive,
Q and Q do not change. When CLK becomes low, the slave goes to set state giving high Q
(and low Q ).

Next is the reset condition. At the end of set state Q is high (and Q low). Now if J is
low, Kts high and CLK is high, the master resets giving low S and high R. Q and Q do not
change because slave is inactive. When CLK becomes low, the slave becomes active and
resets giving low Q (and high Q ).
If both J and K are high, the slave copies the master. When CLK is high, the master
toggles once. Then the slave toggles once when CLK is low. If the master toggles into set
state, the slave copies the master and toggles into set state. If the master toggles into reset
state, the slave again copies the master and toggles into reset state.
Table 14.6 shows the truth table of JK master slave flip flop.
It is seen from Table 14.6 that a low PR and low CLR can cause race condition.
330 Basic Electronics
Therefore, PR and CLR are kept High when inactive. To clear, we make CLR Low and to
preset we make PR Low. in both cases we change them to High when the system is to be
run.

PR

J
M-S Q
CLK
K Q

CLR
(b)
Fig 14.25 JK master slave flip flop (a) circuit (b) symbol

Low J and Low K produce inactive state irrespective of clock input. If K goes High,
the next clock pulse resets the flip flop. If J goes High by itself, the next clock pulse sets
the flip flop. When both J and K are High, each clock pulse produces one toggle.
Table 14.6 : Truth table of JK master slave flip flop

INPUTS OUTPUT
PR CLR CLK J K Q

0 0 × × × Race condition
0 1 × × × 1
1 0 × × × 0
1 1 × 0 0 No change
1 1 0 1 0
1 1 1 0 1
1 1 1 1 Toggle
 Digital Circuits & Design 331

14.15 BASIC CONCEPTS OF MEMORY (RAMs)

Memory is a group of registers that can store informations (either instruction or data)
for the micro-processor.
It is the main component of micro computer system.
To communicate with memory, the microprocessor unit should be able to
- Select the chip
- identify the register
- read from or write in to the register.
The capacity of a memory is represented by 2n × m, where
n- no. of address lines
2n - no. of memory locations
m- no. of bits of data that each location can contain.
14.16 TYPES OF MEMORIES
Access to the memory may be carried out in a serial function. Alternately, information
stored in a memory may be accessed at random. In the first type, we cannot access a
particular location, at will, it has to be done in a sequential manner. For example, a magnetic
tape is such a device data stored in a particular portion of a magnetic tape type can be
accessed only if the tape is sequenced through till the desired data point is needed. So, we
may call such a memory device as sequential access memory. A memory device, in which,
random access to data is possible, is called as a random access memory (or RAM).
Another classification of memories, is based on the storage-time. A memory, in which the
information stored, is retrieved INDEFINITELY, until a new information is over-written or
electrical power is switched-off to the memory, is termed as the STATIC type. Thus a
DYNAMIC memory device needs periodic REFRESHING, in order to retrieve the stored
information. A static memory uses flip-flops as basic memory cells, to store information.
In dynamic memories, capacitors are used as the basic storage cells. Since the charge on
the capacitors leaks away, we need to refresh this charge Dynamic memories are very
much smaller then static ones. So a dynamic memory device can store information that is
approximately four times the information stored in a static device, having the same physical
dimension. It results in a lower cost per bit for dynamic memory devices. The dynamic and
static memory device are called as VOLATILE and NON-VOLATILE memories
respectively.
If the contents of a memory device are lost, when it is read, the memory is called as
destructions. So, to save the contents of the memory, it has to be re-written after every
read-operation. Thus, a magnetic-core memory is destructive type. But IC, magnetic drum,
disc and tape are nondestructive.
If locations may be accessed at any order and access-time is independent of the
location being accessed, the memory is termed as RANDOM ACCESS MEMORY (RAM).
332 Basic Electronics
Ferrite-cores, and semiconductor memories are usually of this type. Static RAM is made
up of a large number of flip-flop on ICs. In the process of refreshing, the information is
read from the cell and written back in the same position. That is why, D-RAMs chips are
preferred compared to S-RAM chips, because of the smaller size.
There are some memories in which we can enter or write data into the device, and
also fetch or read data for it, as often as we desire. Such a memory is called as Read-write
memory. Memories, on which we can read only are called as Read-Only Memories (ROM).
Fresh data is not written during normal operation of the circuits, only read-operation is
possible in such devices.

Fig 14.26
14.17 MEMORY DEVICE PARAMETERS OR CHARACTERISTICS
Ø Access time : The access time of a memory is defined as the time required to
access a memory location for reading or writing.
Ø The access time of a magnetic drum is defined as the sum of seek time and transfer
time.
Ø Access rate : It is defined as the reciprocal of access time. It is measured in words
per second.
Ø Access time depends on the physical characteristics of the storage medium, and also
on the type of access mechanism used.
Ø Access models: An important property of a memory device is the order or sequence
in which information can be accessed.
 Digital Circuits & Design 333

Ø Random Access: It the access time is independent of position of the memory location,
then it is called random-access mode. I.e. The access time of every memory location
is same. Eg: ROM, CAM (content addressable memory)
Ø Sequential Access: A memory in which the locations can be accessed in a sequence
only is referred to as a sequential memory. Eg: Magnetic tape, magnetic bubble
Ø Some memory devices such as magnetic disks or drums contain a large number of
independent rotating tracks. If each track has its own read-write head, the tracks
may be accessed randomly, although access within each track is serial. In such cases
the access mode is same times called semi random or direct access.
Ø Alterability: The method used to write information into a memory may not be
irreversible, in that once information has been written, it can not be alterable while
the memory is in use i.e. on-line.
Ø Memory whose contents can not be altered on-line are called ROM's.
Ø ROMs whose contents can be changed are called PROM's.
Ø Memories in which reading or writing can be done on-line are called R/W Memories.
Ø Volatile memory: In this type of memory, the stored information is dependent on
power supply i.e. the stored information will remains as it is as long as power is
applied, Eg: RAM.
Ø Non-volatile memory: In this type of memory, the stored information is independent
of power supply. I.e. the stored information will present as it is even if the power
fails. Eg: ROM, PROM, EPROM, EEPROM etc.
Ø PROM: Programmable Read Only Memory
EPROM: Erasable programmable Read Only Memory
EPROM or EPROM: Electrically Erasable Programmable Read Only Memory
EAPROM: Electrically Alterable Programmable Read Only Memory
Ø Static RAM (SRAM): In this type of memory binary information is stored in terms of
voltage. SRAMs stores ones and zeros using conventional Flip-plops.
Ø Dynamic RAM (DRAM): In this type of memory, binary information is stored in
terms of charge on the capacitor. The memory cells of DRAMs are basically charge
storage capacitors with driver transistors. The presence or absence of charge in a
capacitor is interpreted as logical 1 or 0.
Ø Because of the leakage property of the capacitor, DRAMs require periodic charge
refreshing to maintain data storage.
Ø The package density is more in the case of DRAMs. But additional hardware is
required for memory refresh operation.
Ø SRAMs Consume more power when compared to RAMs. SRAMs an faster than
DRAMs.
334 Basic Electronics
14.18 COUNTER
It is the sequential digital circuit that can count a prescribed binary sequence on the application
of clock pulse and repeats.
Ø Each sequence is called binary states, through which counter will progress.
Ø If n = No. of Flip-Flops used in the counter design &
N = No of binary states that counter can count then N < 2n.
Ø It is named as MOD - N or n - bit counter.
Ø For counter design, except S - R flip-Flop, JK, T or D F/F can be used.
but mostly J-K or T-Flip-Flip is used.
14.19 CLASSIFICATION OF COUNTER
Ø On the basic of clock Pulse connection, counter is of two types :-
i) Synchronous counter :
The counter where all Flip - Flops get clock pulse from a single source directly.
ii) Asynchronous counter :
If clock pulse from source is given to first Flip-Flop, output of first is given is clock to
second F/F and so on.

Clk
F/F F/F F/F
F/F F/F F/F
Clk
(a) (Synchrmous) Fig. 14.27 (b) (Asynchronous)
Ø Depending on counting sequence, It is of two types
- Up Counter
- Down counter
i) Up Counter :
If the counter counts the binary sequence in ascending order, then it is
called Up Counter
ii) Down counter :
If the counter counts the sequence in descending order, then it is called
Down counter
Ø Depending on no. of counting sequences, It is of two types -
- Natural counter
- Un-Natural counter
i) Natural counter :
If N = 2n i.e maximum no. of counting sequences, then natural counter.
 Digital Circuits & Design 335

ii) Un-Natural Counter :

If N < 2n, i.e less than maximum number of countings, then it is Un-Natural
Counter.
Asynchronous counter
As here, all the flip-flops are not getting clock from a single source, so all are not
triggered at a time.

Here we may have to take the help of asynchronous inputs like PR & CR .
14.20 STEPS FOR DESIGNING ASYNCHRONOUS COUNTER
Ø At first all the Flip-Flops are set in toggling mode.
a) Case-I (If all Flip-Flops are +ve edge triggered) :
i) For up counting, the clock from source is given to 1st Flip-Flop, the complemented
output of 1st is given as clock to 2nd and so on.
ii) For Down counting, the clock from source is given to 1st Flip-Flop, the un-
complemented output of 1st is given as clock to 2nd and so on.;
b) Case-II (If all Flip-Flops are –ve edge triggered) :
i) For up counting, the clock from source is given to 1st Flip-Flop, the un-
complemented output of 1st is given as clock to 2nd F/F and s on.
ii) For down counting, the clock from source is given to 1st Flip-Flop, the
complemented output of 1st is given to 2nd as clock & so on.
Ø Asynchronous counter is also known as ripple counter. As the carry move through
Flip Flops like a ripple on water.
14.21 NATURAL ASYNCHRONOUS COUNTER DESIGNS
MOD - 8 or 3-bit Up counter
This counter can count & binary states from 0 - 7. Here three Flip-Flops are used.
Let all Flip-Flops are +ve edge triggered.

logic 1 PR1 PR 2 PR 3
T1 Q1 T2 Q 2 T3 Q
3

F/F1 F/F2 F/F3

Clk
Q1 Q2
Q3
CR 1 CR 2 CR 3

Q1(LSB) Q2 Q3(MSB)
Fig. 14.28
336 Basic Electronics
Truth table :

Clk Q3 Q2 Q1
A 0 0 0
A 0 0 1
A 0 1 0
A 0 1 1
A 1 0 0
A 1 0 1
A 1 1 0
A 1 1 1

Clk Diagram :

T1 T2 T3 T4 T5 T6 T7 T8

Clk

1 1 1 1
Q1 0 0 0 0 0
(ISB)
1 1 1 1
0 0 0
Q2 0 0

1 1 1 1

Q3 0 0 0 0 0
(MSB)

If → f Frequency of clock pulse

then frequency of Q1 → f/2
Q2 → f/4
Q3 → f/8
 Digital Circuits & Design 337

14.22 UN-NATURAL ASYNCHRONOUS COUNTER DESIGNS

Here along with normal design rules, some extra rules are followed.
Ø The Boolean expression for the state to be immediately skipped is found out.
Ø As per this expression, corresponding outputs are given to NAND gate.
Ø The output of NAND gate is given to preset and clear inputs of the Flip Flops,
depending on next count after the ‘skip’ sequence.
MOD-10 up counter/BCD counter / Decade counter :
Ø Here 10 states can be counted. The counting sequence is 0 - 9, i.e (0000)2 – (1001)2.
Ø Here four flip-flops are used for designing.
Truth table :

ClK Q4 Q3 Q2 Q1
A 0 0 0 0
A 0 0 0 1
A 0 0 1 0
A 0 0 1 1
A 0 1 0 0
A 0 1 0 1
A 0 1 1 0
A 0 1 1 1
A 1 0 0 0
A 1 0 0 1
1 0 1 0 → Q 4 Q 3 Q 2 Q1

1 1 1 1

The immediate state to be skipped is 1010 i.e Boolean expression is Q 4 Q 3 Q 2 Q1 .

it is given to the NAND gate. The output of NAND gate is connected to clears of all Flip-
Flops, as next state after skip is (0000)2.
338 Basic Electronics
Circuit diagram :

logic 1 PR 2
PR1 PR 3 PR 4
T1 Q 1 T2 Q 2 Q
T3 3 T4 Q 4
Clk F/F1 F/F2 F/F3 F/F4

CR 1 CR 2 CR 3 CR 4

Q1 Q2 Q3 Q4
(LSB) (MSB)
Fig. 14.29
Timing diagram

T1 T2 T3 T4 T5 T6 T7 T8 T9 T 10
Clk

1 1 1 1 1
0 0 0 0 0
Q1 0
(LSB)
1 1 1 1
0 0 0 0 0 0 0
Q2

1 1 1 1
0 0 0 0 0 0 0
Q3
1 1
Q4 0 0 0 0 0 0 0 0 0
(MSB)

Here if f → frequency of clock

then frequency of Q1 → f/2
Q2 → f/4
Q3 → f/8
Q4 → f/10
 Digital Circuits & Design 339

Example 14.6 : Design a counter that can count 0, 1, 2, 6, 7 & repeats.

Solution :
Normally a counter consisting of three Flip Flops will count from 0 to 7. Here we have to
skip binary equivalent of 3, 4, 5.

Truth table Clk Q3 Q2 Q1

A 0 0 0
A 0 0 1
A 0 1 0
0 1 1 OP Q3Q 2 Q1
1 0 0 PP skipped
To be

1 0 1 Q
A 1 1 0
A 1 1 1

The binary equivalent of the state after the count 010 is 011 i.e boolean expression is
Q 3 Q 2 Q1 . Q 3 , Q 2 & Q1 are given to a NAND gate. The output of NAND gate is given to
preset of F/F2, F/F3 & clear of F/F1 as after the skip we want to go the state 6 i.e. 110.

logic 1

PR1 PR 2 PR 3
T1 Q 1 T2 Q 2 T3 Q 3
Clk F/F1 F/F2 F/F3

CR 1 logic 1 CR 2 logic 1 CR 3

Q1 Q2 Q3
(LSB) (MSB)
14.23 SHIFT REGISTER
A register is a device capable of storing a bit. The data can be serial or parallel. A
register can convert a data from serial to parallel and vice versa. Shifting the digits to left
and right is an important aspect of arithmetic operations. In this chapter we discuss these
concepts.
It is a sequential digital circuit that can store and shift the data without any mathematical
manipulation. It may consist of one or more Flip Flops.
340 Basic Electronics
In a n-bit shift register, there are n Flip Flops present.
To design a shift register, S-R, J-K or D-Flip Flops can be used. But widely D Flip Flop
is used.
14.24 BUFFER REGISTER
A register is used for storing and shifting data entered into it from an external source.
We know that a flip flop is the basic storage element in digital system. Fig. 14.30 explains
the concept of storing a 1 or 0 in a flip flop. A 1 is applied to the input of flip flop and a
clock pulse is applied. 1 is stored by setting the flip flop. Even when 1 is removed from the
input, the flip flop remains in the set state storing 1. If a 0 is applied at the input, 0 is stored
in the flip flop on the application of clock pulse. For storing more bits we need more flip
flops. Each state of a flip flop has one bit of storage capacity. Thus the number of stages
is equal to the storage capacity.
A buffer register is the simplest type of register. It can only store a digital word.

Fig. 14.30. Flip flop as storage element . Fig. 14.31. 3 bit buffer register
(a) Q= 1 on positive edge of clock or remains 1
if already in that state (b) Q = 0 on positive edge
of clock or remain 0 if already in that state
Fig. 14.31 shows a 3 bit buffer register. The X bits set the flip flops for loading. When the
first positive clock edge arrives the output becomes
Q2 Q1 Q0 = X2 X2 X0
The buffer register is too primitive to be of any use. A control over the Xbits is needed.
14.25 BASIC SHIFT OPERATIONS
A simple example of shift operation is
that in a calculator. Suppose we have
to enter 356 in the calculator. First we
press and release 3. The digit 3
appears in the display. Next we press
and release 5. The digit 3 is shifted
one place to the left and 5 appears on
the extreme right. As we press and
release 6, the digit 3 and 5 shift to the
left and 6 appears in the extreme right
position. This simple example
illustrates two characteristics of a shift Fig. 14.32 Basic shift operations in digital register
 Digital Circuits & Design 341

register. 1. It is a temporary memory and holds the number displayed. 2. When we press a
new digit on the keyboard, the earlier number is shifted to the left. Thus, shift register has
memory and shifting characteristics.
The basic shift operations are :
(a) serial shift left, then out
(b) serial shift right, then out
(c) parallel shift in
(d) parallel shift out
(e) rotate left
(f) rotate right.
These operations are shown in Fig. 14.32
14.26 SHIFT LEFT REGISTER
Fig. 14.33 shows a shift left
register. It uses D flip flops.
The circuit shown has positive
edge triggering. It is a 4 bit
register using 4 flip flops FF0,
FF1, FF2, FF3. Din is the input Fig. 14.33 Shift left registor
to FF0. Output of FF0 is Q0 and
is fed to D1 Similarly Q1 is fed to D2 and Q2 to D3. All the flip flops are clocked together by
the clock pulse.
Initially Q3 Q2 Q1 Q0 = 0000
At the first positive edge of clock pulse FF0 is set and then Q3 Q2 Q1 Q0 = 0001
At the second positive edge of clock pulse FF1 is set and then Q3 Q2 Q1 Q0 = 0011
The positive edge of the third pulse sets FF2 and then Q3 Q2 Q1 Q0 = 0111
Finally, the positive edge of fourth clock pulse sets FF3 and then Q3 Q2 Q1 Q0 = 1111
As long as Din = 1, the stored word cannot change further. Now let Din be changed
to 0. Then the successive clock pulses produce the following stored contents.

Clock pulse Stored contents

1 1110
2 1100
3 1000
4 0000

As long as Din = 0, the stored contents cannot change further.

342 Basic Electronics
14.27 SHIFT RIGHT REGISTER
Fig. 14.34 shows a shift right register using D flip flops. As the name suggests the
stored contents are shifted right on each clock pulse. The Q output is connected to the D
input of preceding flip flop. At the arrival of each positive edge of clock shift right operation
occurs. Let Din = 1 and
Q3 Q2 Q1 Q0 = 0 0 0 0

Fig. 14.34. Shift right register

The positive edge of first clock pulse sets up flip flop F/F3 and
Q3 Q2 Q1 Q0 = 1000
The positive edge of second clock pulse makes the stored contents as
Q3 Q2 Q1 Q0 =1100
The positive edge of third clock pulse gives
Q3 Q2 Q1 Q0 =1110
and the positive edge of fourth clock pulse gives
Q3 Q2 Q1 Q0 = 1111
After this the stored contents remain the same till Din = 1. Let Din be changed to 0 now.
The successive clock pulses make the stored contents as under:
Clock pulse Stored contents
1 0111
2 0011
3 0001
4 0000
As long as Din = 0, the subsequent clock pulse do not cause any further change in stored
contents.
14.28 SHIFT REGISTER OPERATIONS
One method to describe the operation of shift register is the method of loading in and
reading from the storage bits. There could be 4 such operations :
 Digital Circuits & Design 343

(a) Serial in - Serial out : The data is loaded into and read from the shift register
serially. [Fig. 14.35 (a)]
(b) Serial in - Parallel out : The data is loaded into the register serially but read in
parallel (i.e., data is available from all bits simultaneously.) [Fig. 14.35 (b)]
(c) Parallel in - Serial out : The data is loaded in parallel, i.e., the bits are entered
simultaneously in their respective stages and read serially. [Fig. 14.35 (c)]
(d) Parallel in - Parallel out: The data is loaded and read from the register in parallel,
i.e., all bits are loaded simultaneously and read simultaneously. [Fig. 14.35 (d)]

Fig. 14.35. Shift register operations (a) serial in - serial out (SISO) (b) serial in - parallel out
(SIPO) (c) parallel in - serial out (PISO) (d) parallel in - parallel out (PIPO)
14.29 SERIAL IN - SERIAL OUT SHIFT REGISTER
It is the shift register that accepts the data serially and gives output serially.
Let a 4.bit SISO -

Serial
input data D0 Q0 D1 Q1 D2 Q2 D3 Q3
Serial
Clk FF0 output data
FF1 FF2 FF3

Fig. 14.36

Connection Condition :
Serial input data → D0
Q0 → D1
344 Basic Electronics
Q1 → D2
Q2 → D3
Q3 → Serial output data.
Let serial data is (B3 B3 B1 B0)2 & data is given starting from LSB.
Sl.No Clk Serial input data Q 0 Q1 Q2 Q3
------------ Initially ----------- 0 0 0 0
1 ↑ B0 B0 0 0 0
2 ↑ B1 B1 B0 0 0
3 ↑ B2 B2 B1 B0 0
4 ↑ B3 B3 B2 B1 B0 → o/p (LSB)
5 ↑ 0 0 B3 B2 B1 → o/p
6 ↑ 0 0 0 B3 B2 → o/p
7 ↑ 0 0 0 0 B3 → o/p (MSB)

1st four clock pulses required to load the data and then three clock pulses required to shift
the data.
⇒ Total seven pulse required to load & shift the data.
⇒ (2n –1) pulses required to load & shift for a n-bit SISO.

14.30 SERIAL IN-PARALLEL OUT SHIFT REGISTER

It is the shift register that accepts data serially and gives data parallelly, i.e output is
taken from all flip-flops simultaneously.

Let a 4 bit right shift SIPO :

Serial input
data D0 Q0 D1 Q1 D2 Q2 D3 Q3

Clk FF0 FF1 FF2 FF3

Q0 Q1 Q2 Q3
Fig. 14.37
Let the data is (B3 B2 B1 B0)2
 Digital Circuits & Design 345

Sl.No. Clk Serial input data Q0 Q1 Q2 Q3

---------------- Initially --------------- 0 0 0 0
1 ↑ B0 B0 0 0 0
2 ↑ B1 B1 B0 0 0
3 ↑ B2 B2 B1 B0 0
4 ↑ B3 B3 B2 B1 B0
↓ ↓ ↓ ↓
(MSB) Outputs (LSB)
Here only four clock pulses required four clock pulses required for compute operation.
⇒ n clock pulse required for n-bit SIPO.
14.31 PARALLEL IN - PARALLEL OUT SHIFT REGISTER
Here data is given simultaneously to all Flip Flops, and also data is collected from all the
Flip-Flops simultaneously.
Let 4 bit PIPO :

B0 B1 B2 B3
D0 Q0 D1 Q1 D2 Q2 D3 Q3
Clk

Q0 Q1 Q2 Q3
(MSB) Fig. 14.38 (LSB)

Clk Parallel input data Q0 Q1 Q2 Q3

------ Initially --------- 0 0 0 0
↑ B3 B2 B1 B0 B3 B2 B1 B0
↓ ↓ ↓ ↓
O/P O/P O/P O/P
Outputs
(LSB) (MSB)

Here only one clock plse required for complete operation

⇒ One clock pulse required for n-bit PIPO.
346 Basic Electronics
14.32 PARALLEL IN-SERIAL OUT SHIFT REGISTER
Ø Here data is given to all the Flip Flops simultaneously but data is collected serially
from one flip flop.
Ø Here a control line is used to distinguish between parallel in an serial out.
The control line is S L .

when S L = 0 → Loading occurs.

=1 → Shifting occurs.

B0(LSB) B1 B2 B3
S L

1 2 3 4 5 6

D0 Q0 D1 Q1 Q2 D3 Q3
D2 Serial
data O/P

Clk

Fig. 14.39

When S L = 0, the AND gates numbered 1, 3, 5 have output zero. So what ever at B0,
B1, B2, B3, that is connected to corresponding Flip Flops, so parallel loading occurs.

S L = 1, the AND gates numbered 2, 4, 6 have output zero. So

Q0 → D1
Q1 → D2
Q2 → D3
This the case of serial out.

S L Clk Parallel input data Q0 Q1 Q2 Q3

D0 D1 D2 D4
---------------- Initially ---------------- 0 0 0 0
0 ↑ B0 B1 B2 B3 B0 B1 B2 B3 → output (MSB)
1 ↑ 0 – – – 0 B0 B1 B2 → O/P
1 ↑ 0 – – – 0 0 B1 B2 → O/P
1 ↑ 0 – – – 0 0 0 B0 → O/P (LSB)
 Digital Circuits & Design 347

Here only 4 clock pulses required for loading & shifting operation.
⇒ n clocks required for n- bit PISO.
14.33 CIRCULAR SHIFT REGISTER
It is the type of shift register where output of last Flip-Flop is connected to input of 1st
Flip Flop.
They are :-
i) Ring counter (uncomplemented output of last Flip Flop is connected input of 1st Flip
Flop)
ii) Johnson counter (Complemented output of last Flip Flop is connected to input of 1st
Flip Flop)
14.34 DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSION
Because most sensors have analog output while much data processing is accomplished
with digital computers, analog-to-digital and digital-to-analog conversion obviously play an
important role. The process of changing an analog signal to an equivalent digital signal is
accomplished with the help of an analog-to-digital converter (ADC). For example, an
ADC is used to convert an analog signal from a transducer, (measuring some physical
quantity such as temperature, pressure, position, rotational speed or flow rate) into an
equivalent digital signal. An analog-to-digital converter (ADC) is often referred to as an
encoding device, as it is employed for encoding signals for entry into a digital system.
Digital-to-analog conversion involves translation of digital information into equivalent
analog information and this is accomplished by the use of digital-to-analog converter
(DAC). DACs are used whenever the output of a digital circuit has to provide an analog
voltage or current to drive an analog device. As an example, the output from a digital
system might be converted into an analog control signal for adjusting the motor speed or
the furnace temperature, or for controlling almost any physical variable. Computers can be
programmed to generate the analog signals (through a DAC) required for testing analog
circuitry. A digital-to-analog converter (DAC) is sometimes considered a decoding device.
Digital-to-analog (D/A) conversion is a straight forward process and is considerably
easier than analog-to-digital (A/D) conversion. In fact, DACs are used as components
in some ADCs. So we will consider D/A conversion first.
14.34.1 Digital-To-Analog (D/A) Conversion
Basically, D/A conversion is the process of taking a value represented in digital code
(such as simple binary or BCD) and converting it into a voltage or current which is proportional
to the digital value. As already mentioned, D/A conversion is accomplished by the use of
digital-to-analog converter abbreviated as D/A converter or DAC.
348 Basic Electronics

DAC Circuitry Fig. 14.40

The basic configuration of a simple DAC is shown in fig.14.40. It consists of a precision
resistor ladder network, a reference precision voltage supply, logic inputs, semiconductor
switches and an operational amplifier (op-amp). The inputs A, B, C, D, ...H are binary
inputs which are assumed to have values of either 0 V (LOW) or 8V (HIGH). When the
input is HIGH, the switch closes and connects a precision reference supply to the input
resistor and when the input is LOW the switch is open. The reference supply produces a
very stable, precise voltage required for generating an accurate analog output. The op-
amp is used as a summing amplifier, which produces the weight sum of the binary inputs.
In an 8-bit code input the switch A is actuated by most significant bit (MSB) and the
switch H is actuated by least significant bit (LSB). If the input binary number is 100,00,000
then switch A is closed and others are open. The output voltage which depends upon
feedback resistor, is equal to the reference voltage.
It is known that the summing amplifier multiplies each input voltage by the ratio of
feedback resistor Rf to the corresponding input resistor Rin. In this circuit Rf = R (say of 1
k Ω) and the input resistors range from R to 2n–1 R (i.e. to 8 R, 128 R, 2048 R in case of
4-bit, 8-bit and 12-bit DAC) depending upon the number of bits of the DAC.
The A input has Rin = R and so the op-amp possess the voltage at A with no attenuation
i.e. the output voltage VOUT is equal to the reference voltage, VREF. The B input has
Rin = 2 R, so it will be attenuated by half. Similarly the input C, input D and input H will be
1
attenuated by 1/4, 1/8 and n−1 respectively. The amplifier output can thus be expressed
2
as
FG 1 1 1 1 IJ
H
VOUT = − VA +
2
VB + VC + VD +... n −1 VH
4 8 2 K
 Digital Circuits & Design 349

The –ve sign is present in the above expression because the summing amplifier is an
inverting amplifier, but it will not concern us here.
Table 14.7
Clearly, the summing amplifier
output is an analog voltage which Input Code
represents a weighted sum of the Output Voltage
A B C D
digital inputs, as shown by the table
14.7, for a 4-bit DAC. This Table 0 0 0 0 0
lists all the possible input conditions 0 0 0 1 -1.0 LSB
and the resultant amplifier output 0 0 1 0 -2.0
voltage. The output is evaluated 0 0 1 1 -3.0
for any input condition by setting 0 1 0 0 -4.0
the appropriate inputs to either 0 0 1 0 1 -5.0
V or 8 V. For example, if the digital 0 1 1 0 -6.0
input 1001, then VA = VD = 8 V 0 1 1 1 -7.0
and VB = VC = 0 V. Thus
1 0 0 0 -8.0
FG 1IJ 1 0 0 1 -9.0
H
VOUT = − 8V + 0V + 0V + × 8
8 K 1 0 1 0 -10.0
= – 9 V. 1 0 1 1 -11.0
The resolution of this DAC is equal 1 1 0 0 -12.0
to the weighting of the LSB, which
1 1 0 1 -13.0
1
is × 8 V = 1 V. As shown in the 1 1 1 0 -14.0 MSB
8
1 1 1 1 FULL SCALE
Table, the analog output increases
by 1 V as the binary input number
advances one step.
If we look at the input resistor values in fig. 14.40. It should come as no surprise
that they are binarily weighted. In other words, starting with the MSB resistor, the resistor
values increase by a factor of 2. This of course provides the desired weighting in the
output voltage.
There are two serious drawbacks of the above D/A conversion system. The biggest
problem is the large difference in resistor values between the LSB and MSB, especially in
high-resolution (or many bit) DAC. For example if the MSB resistor is of 1 kΩ in a 10-bit
DAC, the LSB resistor will be 512 kΩ. With the current IC fabrication technology, it is
very difficult to produce resistors of values over a wide resistance range that maintain an
accurate ratio especially with variations in temperature. Moreover, the MSB resistor is
required to handle a much greater current than that used for LSB resistor. For example, in
a 10-bit system, the current through the MSB resistor will be more than 500 times as large
as the current through the LSB resistor. For these reasons it is preferable to employ a
circuit that uses resistances of fairly close values. One of the most widely used DAC
circuit that satisfies the above requirement is the R-2R ladder network (binary ladder),
350 Basic Electronics
where the resistors used have only two values and that in the ratio of only 2 to 1.
Binary Ladder. A DAC using R-2R ladder network with four input voltages,
representing 4-bits” of digital data and dc voltage output is illustrated in fig. 14.41.

DAC Using R-2R Ladder Network With Four Input Voltage and DC Voltage Output
Fig. 14.41
The output current, INPUT depends on the positions of the four switches, and the digital
inputs D 0, D1, D2, D3 control the states of the switches. The current is allowed to flow
through an op-amp current-to-voltage converter to give VOUT.
The output voltage (analog), VOUT is proportional to the digital input and is given by the
expression

D 0 × 2 0 + D1 × 21 + D 2 × 2 2 + D 3 × 2 3
VOUT = VREF
24
For example, if the digital input is 1010 then output voltage VOUT will be given by the
expression

0 ×1+ 1× 2 + 0 × 4 + 1× 8 10
VOUT = VREF = VREF
16 16
The function of the ladder network is to convert the 16 possible binary values (from 0000
VREF
to 1111) into one of 16 voltage levels in steps of
16
So,
D 0 × 2 0 + D1 × 21 + D 2 × 2 2 + D 3 × 2 3 + D 4 × 2 4 +.... D n −1 × 2 n −1
VOUT = × VREF
2n
 Digital Circuits & Design 351

Thus we can have more digital or binary inputs and greater quantization for each step
by using more sections of ladder network. For example, an 8-stage ladder network could

VREF VREF
extend the number of voltage steps or voltage resolution to or .
28 256

VREF
In general the voltage resolution for an n-stage ladder network is given as .
2n
Example 14.7 : Determine the (i) resolution, (ii) full-scale output and weight of each input
bit for the DAC shown in fig. 14.40. Assume VREF = 10 V.
Determine also the full scale output when the feedback resistor Rf is made one-
fourth of R.
Solution :
The MSB passes with unity gain, so its weight in the output is equal to VREF i.e. 10 V.
Ans.

VREF 10
The second MSB weight = = =5V Ans.
2 2

VREF 10
The third MSB weight = = = 2.5 V Ans.
4 4

VREF 10
The fourth MSB (or LSB) weight = = = 1.25 Ans.
8 8
(ii) Full scale output = 10 + 5 + 2.5 + 1.25 = 18.75 V Ans.
(i) The resolution of the DAC is equal to the weight of the LSB i.e. 1.25 V Ans.
If Rf is reduced to one-fourth, each input will be 4 times smaller than the values above.
18.75
Thus the full scale output will be reduced in the same ratio and becomes = 4.675 V
4
Example 14.8 : Determine the output voltages caused by each bit in a 6-bit ladder if the
input levels are 0 = 0 V and 1 = + 16 V. Determine the resolution and full-scale
output of this circuit. Find out the voltage from the above ladder for a digital input
of 101011.

D n −1 × 2 n −1 D n −1 16
Solution : First MSB output = = = =8V Ans.
2n 2 2

D n − 2 × 2 n − 2 D n − 2 16
Second MSB output = = 2 = =4V Ans.
2n 2 4
352 Basic Electronics

D n − 3 × 2 n − 3 D n − 3 16
Third MSB output = = 3 = =2V Ans.
2n 2 8

16
Fourth MSB output = 1 V Ans.
16

16
Fifth MSB output = = 0.5 V Ans.
32

16
Sixth MSB (LSB) output = = 0.25 V Ans.
64
The resolution is’ equal to the weight of the LSB i.e. 0.25. V Ans.
The full scale output occurs for digital input of 111111
i.e. 8 + 4 + 2 + 1 + 0.5 + 0.25 = 15.75 V Ans.
The voltage output for a digital input of 101011

D 0 × 2 0 + D 1 × 21 + D 2 × 2 2 + D 3 × 2 3 + D 4 × 2 4 + D 5 × 2 5
VOUT =
26

16 × 1 + 16 × 2 + 0 × 4 + 16 × 8 + 0 × 16 + 16 × 32
= = 10.75 V Ans.
64
Example 14.9 : The output V0 of an N-bit D/A converter is given by

d i
V0 = 2 N −1 a N −1 + 2 N − 2 a N − 2 +....2 a22 + 21a1 + a 0 K

where K is a proportionality factor determined by the system parameters and

where the coefficient aj represents the binary word and aj = 1 (0) if the jth bit is 1
(0).
(i) A-6 bit D/A converter gives V0 = 3.6 V for the word 100100. Find the
value of V0 for the word 110011.
(ii) For the R – 2R ladder D/A converter (shown in fig 14.42), find the value of
the output voltage V0 where VR = 6 V. Clearly show the steps in the calculations.

Solution: (i) d
V0 = 2 N −1 a N −1 + 2 N − 2 a N − 2 +....2a 22 + 21 a 1 + a 0 i
where N = Number of bits, a = value of bits, and V0 = 3.6 V
 Digital Circuits & Design 353

Fig. 14.42

For the word 100100, N = 6, a5 = 1, a4 = 0, a3 = 0, a2 = 1, a1 = 0, a0 = 0

So 3.6 = K (25 × l + 24 × 0 + 23T × 0 + 22 × 1 + 21 × 0 + 20 × 0).= 36 K

3.6
or K = = 0.1
36
For the word 110011, N = 6, a5 = 1, a4 =1, a3 = 0, a2 = 0, a1 = 1, a0 = 1
So V0 = 0.1 (25 × l + 24 × l + 23 × 0 + 22 × 0 + 21 × l + 20 × l
= 0.1 (32 + 16 + 2 + 1) = 5.1 V Ans.
(ii) When the switches are connected to earth the bit is 0 and when connected to the
reference voltage the bit is 1. So is LSB and S3 is MSB. so the word is 1010

VR
∴ V0 = (a n −1 2 n −1 + a n −2 2 n −2 +... a1 21 + a 0 2 0 )
2n

6 6
= 4
(1 × 2 3 + 0 × 2 2 + 1 × 21 + 0) = × 10 = 3.75 V Ans.
2 16
14.34.2 Analog-To-Digital (A/D) Conversion
The analog-to-digital (A/D) conversion is the process of converting an analog input
voltage into an equivalent digital signal. The operation is somewhat more complex and
time-consuming than the D/A conversion. A number of different methods have been
developed and used for A/D conversion. Few of these will be described here.
1. Ramp A/D Conversion. This is the simplest and popular method of A/D conversion
and employs a digital counter as the register and allows the clock to increment the counter
one step at a time until the reference ramp voltage, VREF becomes equal to or exceeds the
analog input voltage, VA. It is called a digital-ramp ADC because the waveform of DAC’s
output, VREF is a step-by-step ramp (actually a staircase), like the one shown in fig. 14.43(b).
It is also referred to as a counter-type ADC. Such an ADC quantizes an analog signal
through conversion of the signal to a time duration pulse.
A ramp ADC is shown in fig 14.43 (a). It consists of a digital counter, a DAC, an
analog comparator and a control AND gate. The digital counter advances from a zero
count while the reference voltage VREF, output of the DAC driven by the counter, increases
354 Basic Electronics
one voltage increment for each count step. A comparator circuit, receiving both DAC’s
output (reference ramp voltage VREF) and analog input voltage VA, provides a signal to
stop the count when VREF rises above VA. The counter value at this time is the digital
output.

Fig. 14.43

For explaining the operation let us assume that analog input voltage VA is positive.
When a start pulse is applied, it resets the counter to zero and initiates the operation of the
DAC which produces a linear ramp output signal VREF = K t where K is a constant and t
is the time. A comparator then continuously compares the reference ramp signal, V REF
with analog input voltage VA. The resulting output of the comparator represents a binary 0
when VREF is greater than VA and a binary 1 when VREF is less than VA. While the comparator
output is 1, pulses from a clock pulse generator are counted by the digital counter. When
VREF becomes equal to or exceeds VA, the comparator output changes to a binary zero.
Also, by the action of AND gate, clock pulses are prevented from entering the counter.
The time during which the comparator output remains in the 1 state is proportional to the
magnitude of the input signal VA. Also, the count in the counter at the instant the comparator
changes state is proportional to the time interval that the comparator output is 1. Thus, the
count in the counter is a digital representation of the input signal.
The amount of voltage change stepped by the reference ramp signal depends on the
reference voltage applied and on the number of count bits employed. A 10-stage counter
operating a 10-stage DAC using a reference voltage of 5 V would step each count by a

VREF 5
voltage of 10
= V = 4.9 m V
2 1,024
This would result in a conversion resolution of 4.9 mV. The clock rate of counter
would affect the time required to carry out a conversion. A clock rate of 1 MHz operating
a 10-stage counter would require a maximum conversion time of 1,024 × 1 µs = 1.025 ms.
 Digital Circuits & Design 355

The minimum number of conversions that could be carried out each second would
then be
Number of conversions = 1000/1.025 = 976 conversions per second.
Since on an average, with some conversions requiring little count time and other
1025
.
near maximum count time a conversion time of average number of conversions
2
would be 976 × 2 = 1,952 conversions per second. A slower clock rate would result in few
conversions per second. A converter employing fewer count stages (and less conversion
resolution) would carry out more conversions per second. The conversion accuracy depends
on the accuracy of the comparator.
This type of a ADC may be used for conversion of less than 10 or 12 bits at speeds
that do not exceed several thousand conversions per second. Higher speeds can be obtained
at lower resolution. Added to simplicity is the advantage of excellent differential linearity,
accounting for the very wide use of this type of ADC, particularly in such applications as
the generation of histograms as encountered in the field of nuclear experimentation.
2. Dual Slope A/D Conversion.
This is a popular method of
converting an analog voltage into
a digital value. The block diagram
of the basic dual-slope ADC is
shown in fig. 14.44. The analog
voltage to be converted into a digital
signal is applied through an
electronic switch to an integrator
or ramp generator circuit,
(essentially a constant current Fig. 14.44
charging a capacitor to give a
linear-ramp voltage). The counter operated during both positive and negative slope intervals
of the integrator gives the digital output. The operation is as follows. -
For a fixed time interval (usually the full
count range of the counter), the analog input
voltage, connected to the integrator, raises the
voltage in the comparator to some positive
level, as shown in fig. 14.45. From fig. 14.45
it is obvious that at the end of fixed time interval
the voltage from the integrator is greater for
greater input voltages.” At the end of the fixed
count interval, the count is set zero and the
electronic switch connects the integrator to a
reference or fixed input. The integrator output Fig. 14.45
or input to capacitor then decreases at a fixed
356 Basic Electronics
rate, as shown in fig. 14.45. The counter advances during this time. The integrator output
voltage decreases at a fixed rate until it drops below the comparator reference voltage, at
which the control logic receives a signal (the comparator output) to stop the count. The
count shown by the counter at this time represents the digital output of the ADC.
Typically, a dual-slope ADC is limited to conversion speeds of from 1,000 to 2,000
samples per second at a resolution of 10 or 12 bits as a result of limitations on the counter
counting speed. The conversion rate can be increased to approximate 30,000 samples per
second at a 14-bit resolution without markedly increasing the logic requirements by using a
two-step integration during the second integration period.
The averaging characteristics and cancellation of errors that usually limit the
performance of a ramp-type ADC are the main advantages of this ADC. The integration
characteristic provides the average value of the input signal during the period of first
integration. Consequently, disturbances, such as spurious noise pulses, are minimized.
Performance analysis of these ADCs also indicates that some other types of errors cancel
out as well. Long-term drifts in the time constant, as may result from temperature variations
or aging, do not affect conversion accuracy. Also long-term alteration in clock frequency
have no effect.
3. Successive-Approximation A/D Conversion. This is one of the most widely used
method of A/D conversion. Though it employs more complex circuitry than that used by
ramp A/D conversion but it has much shorter conversion time. In addition, it has a fixed
value of conversion time that does not depend upon the value of the analog input.
This type of ADC makes direct Analog comparison between an unknown input
signal and a reference signal,
o The basic arrangement of a
successive-approximation
ADC shown in fig. 14.46 is
similar to the digital ramp
ADC. This type of ADC,
however does not employ a
counter to provide the input to
the DAC but employs a
register instead. The DAC
provides a reference variable
voltage in steps. The control
logic modifies the contents of Fig. 14.46
the register bit by bit until the
register data are the digital equivalent of the analog input VA within the resolution of the
converter. Usually the measurement sequence selects the largest step of the DAC output
voltage first. The number of clock pulses represents the digital output of the DAC.
Successive-approximation ADC can be employed at conversion speeds of upto about
1,00,000 samples per second at resolutions of upto 16 bits (not including sign). At lower
 Digital Circuits & Design 357

resolutions, speeds of over 2,50,000 samples per second are practical. Factors to be
considered in the design and applications of these ADCs include stability and regulation of
the reference voltage source, overload and recovery characteristics of the comparator,
characteristics of the analog switches and speed and response of the ladder network.
4. Voltage-To-Frequency A/D Conversion. An analog voltage can be converted into
digital form, by producing pulses whose frequency is proportional to the analog voltage.
These pulses are counted by a counter for a fixed duration and the reading of the counter
will be proportional to the frequency of the pulses, and hence, to the analog voltage.
A block diagram of a voltage-to-frequency ADC is given in fig. 14.47. The analog
input voltage VA is applied to an integrator which in turn produces a ramp signal whose
slope is proportional to the input voltage. When the output voltage VOUT attains a certain
value (a preset threshold level), a trigger pulse is produced and also a current pulse is
generated which
V A is used to
discharge the
integrator
capacitor 0.
Now a new ramp
is initiated. The
time between
successive
threshold level Fig. 14.47
crossings is
inversely proportional to the slope of the ramp. Since the ramp slope is proportional to the
input analog voltage VA, the frequency of the output pulses from the comparator is, therefore,
directly proportional to the input analog voltage. This output frequency may be measured
with the help of a digital frequency counter, explained in Fig. 14.46.
The above method provides measurement of the true average of the input signal
over the ramp duration, and so provides high discrimination against noise present at the
input. However, the digitizing rates are slow because of long integration durations. The
accuracy of this method is comparable with the ramp type ADC, and is limited by the
stability of the integrator time constant, and the stability and accuracy of the comparator.
358 Basic Electronics

IMPORTANT NOTES
1. Logic circuits can classified into two categories, i.e.. combinational logic circuit and sequential
logic circuit.
2. A combinational logic circuit does not have a memory.
3. A sequential logic has a memory.
4. Adders, substractors, multiplexers, demultiplexers, encoders, decoders are combinational logic
circuits.
5. The Boolean expression of a combinational logic circuit may be in sum of products or product
of sum form.
6. To design a combinational logic circuit a truth table is drawn. From the truth table the Boolean
expression is written. This expression is simplified by using Boolean laws or by K-map tech-
nique.
7. A combinational logic circuit can be fabricated from NAND or NOR gates.
8. An arithmetic circuit performs Arithmetic operations on a binary number.
9. A half adder can add two one bit numbers. It uses a XOR gate and AND gate. Its outputs are
SUM and CARRY.
10. A full adder can accept three inputs viz., the two bits of the two numbers and a carry in from
the lower order adder. Its outputs are SUM and CARRY. A full adder circuit has two XOR
gates, two AND gates and one OR gate.
11. A 4 bit full adder circuit has one half adder (for LSB) and three full adders. 1C adders are
parallel adders for faster addition.
12. A half subtractor has one XOR gate, one NOT gate and one AND gate.
13. A full subtractor has two XOR gates, two NOT gates, two AND gates and one OR gate.
14. 2’s complement method is used for addition and subtraction. 2’s complement of a binary
number is obtained by complementing each bit and adding 1.
15. BCD number system is used in calculators. A BCD adder has half adders, full adders OR gates
and AND gate.
16. In BCD arithmetic 10’s complement method is used.
17. Multiplexers and demultiplexers help in reducing the cost of transmission of digital signals.
18. A multiplexer is a device having many inputs and one output. By applying control signals, any
one of the inputs can be directed to the output. It is also known as data selector. An N : 1
multiplexer is like a N throw selector switch.
19. An N : 1 multiplexer has N inputs, one output and m select lines where 2m = N. Depending on
the status of select lines, any of the inputs is directed to the output.
20. A multiplexer can also be used to implement a Boolean expression as a combinational logic
circuit.
21. Multiplexers are available as ICs. The standard packages are 2 :1, 4 : 1, 8 :1 and 16:1.
22. For more than 16 inputs, multiplexers can be connected to form a multiplexer tree.
23. A demultiplexer has one input and many outputs. By using select lines, the input can be directed
to any of the outputs.
 Digital Circuits & Design 359

24. Latches and flip flops are bistable elements with two stable states. The main difference between
a latch and flip flop is in the method used for changing state.
25. Latches are bistable elements whose state depends on asynchronous inputs. On the other hand,
edge triggered flip flops are bistable elements with synchronuous inputs whose state depends
on inputs only at the triggering transition of a clock pulse. Edge triggering can be positive edge
triggering or negative edge triggering.
26. Flip flops often have preset (PR) and clear (CLR) inputs also. A clear signal is the same as reset
signal. A preset is equivalent to set the flip flop before the computer run.
27. JK master slave flip flop has two clocked SR flip flops, one known as master and the second
known as slave.
28. Edge triggered JK flip flop is used in digital counters.
29. A T flip flop is obtained by connecting the J and K inputs of JK edge triggered flip flop.
30. Pulse triggering means that data is entered into the flip flop at the leading edge of the clock
pulse but the output occurs only on the trailing edge of clock pulse.
31. Data lock out flip flop has dynamic clock input but the data inputs are disabled after the leading
edge transition.
32. Various parameters of flip flops are : propagation delay, set up time, hold time, maximum clock
frequency, pulse width and power dissipation.
33. Flip flops are used for contact bounce elimination, data storage, data transfer, counting and
frequency division.
34. Flip flops are available as ICs in TTL, ECL and CMOS families.
35. Counters consist of flip flops. They are classified as synchronous and asynchronous. In a
synchronous counter the clock terminal is connected to each stage of the counter so that all the
flip flops are triggered together. In asynchronous counter all the flip flops are not triggered
together.
36. A counter having N flip flops has 2N states. The actual number of states may be equal or less
than 2N. The actual number of states is called modulus of counter.
37. A ripple counter consists of JK flip flops. The O output of each stage feeds the clock input of
next stage. In this counter the carry moves through the flip flops like a ripple on water.
38. A decade counter has a modulus of 10. It uses 4 flip flops but only 10 states are used.
39. A Mod-m counter has m states. It uses a NAND gate to skip the remaining states.
40. An up counter counts from 0000 upwards. A down counter starts with the highest state and
counts downwards to 0000. An up-down counter can count in both directions.
41. A self stopping down counter stops at 0000 and does not start the next cycle.
42. In synchronous counter all the flip flops are clocked simultaneously. Therefore, there is no
propagation delay. A synchronous counter can also have any modulus.
43 Shift registers have two functions: to store data and to shift data (for arithmetic operations
etc.). Flip flops are connected together to form shift registers. 1C shift registers are also
available. A buffer register is the simplest of all registers. It can only store data. Basic shift
operations are : shift left, shift right.
44. Data entry and output can be : serial in - serial out, serial in - parallel out, parallel in - serial out,
parallel in -parallel out. ICs are available for all the above configurations.
ppp
360 Basic Electronics

Communication Systems
15CHAPTER

15.1 INTRODUCTION
The prime function of a communication system is to transfer information from one
point to another via some communication link. The communication system also involves
sorting, processing and storing of information. A transmitter processes the information and
makes it fit for transmission. A receiver decodes, stores and interprets the received
information.
15.2 BASIC BLOCK DIAGRAM OF A COMMUNICATION SYSTEM
Block diagram of a general communication system is shown in Fig. 15.1. Its basic
components are transmitter, communications channel or medium, and a receiver. The
elements of communications system are (i) Information (ii) Transmission (iii) Communications
channel (iv) Noise and (v) Reception.

Noise

Information
Transmitter Channel Receiver Destination
Source

Fig. 15.1 Block diagram of a communication system

Information
The communicated matter called information, or intelligence, signal may consist
of speech, music, computer data, visual information in the form of still pictures or a movie,
typewritten messages or signals, etc. In most systems, a human generates a message. The
information is a physical pattern that has been assigned a commonly understood meaning.
The pattern must be unique, capable of being sent by the transmitter and capable of being
detected and understood by the receiver. In almost all cases the information must be
placed in a physical form that can be transmitted and received.
 Digital Circuits & Design 361

Transmitter
The transmitter is a collection of electronic components and circuits designed to convert
the information into an electrical signal suitable for transmission over a given communication
medium. Usually, a microphone is used to convert speech into an electrical signal. Next,
this electrical signal is processed. In case of wire telephony, no real processing is required.
However, in case of long distance radio communication, the electrical signal is amplified at
several stages. The audio signals are superimposed on high frequency signals known as
carrier (RF) signals by means of modulation. The modulated signal is transmitted through
a channel specially allocated to it.
Communications Channel
Communications channel is the medium by which the electronic signal is sent from
one place to another. The channel may be a pair of wires, coaxial cable (in case of telephone
and telegraph systems), optical fibre or may be an open space (wireless) in case of radio
transmission. The channel is a link connecting the transmitter and receiver and is a path
followed by the signal as it leaves the transmitter. Every channel introduces some amount
of transmission loss or attenuation, so signal power at destination keeps on decreasing with
increasing distance.
Noise
Noise is an electrical extraneous form of energy that interferes with the transmitted
message. The modulated signal gets deteriorated due to distortion in the system and noise
introduced in the system. The various forms of external noise produced in nature include
atmospheric and extraterrestrial noise and industrial noise. The noise generated by lightning
during rainy season is atmospheric noise and that generated due to radiations produced by
the sun and other stars is called extraterrestrial noise. The noise generated by automobile
and circuit ignition, electric motors and switching equipment, leakage from high-voltage
lines and a multitude of heavy electric machines and fluorescent light to the receiver is
called industrial noise. Noise also generated by any of the active or passive device in
receivers is called internal noise.
Distortion is caused by imperfect response of the system to the desired signal itself.
Interference is due to other transmitter, power lines, machinery and switching circuit,
etc., operating in the vicinity.
Noise is one of the more serious problems of electronic communications. It cannot be
completely eliminated.
Receiver
The receiver is a collection of electronic components and circuits that accept the
transmitted message from the channel and convert it back to the original information. The
important function of the receiver is demodulation. Demodulation and decoding are the
reverse of the signal processing performed at the transmitter. Receiver operation includes
amplification for compensating transmission losses, attenuation, etc.
362 Basic Electronics
15.3 PRINCIPLE OF COMMUNICATION
In radio and TV transmission, voice (audio) and picture (video) signals are propagated
over a long distance. The sound or picture as such cannot be made for transmission. They
are first converted to equivalent electrical signal and even then they can not be transmitted
over long distance directly for the following reasons.
i) Audio or video signals cover a range of frequencies. So even if transmission is made
possible, no receiver can be tuned to them.
ii) If the audio or video signals could be transmitted and received, there will be ‘n’ ways
of distinguishing the signals of different stations.
iii) Audio signal is below 20KHZ. To transmit at that frequency, we will require an
antenna of very big size.
iv) Radiation efficiency at low frequency is poor. So high powered Transmitters will be
required.
In order to avoid these difficulties, a radio frequency (RF) wave of a fixed frequency
is used to carry the audio on video signal without affecting the contents of the signal. This
radio frequency wave is called the carrier wave.
The process of combining the signal (information) with the carrier is called modulation.
The carrier does not introduce any change in the signal; only it carries the signal from
the broadcasting station to the destination. The modulated signal is received in the receiver
where a reverse process takes place. This reverse process known as demodulation.
Demodulation involves separating the signal from the RF carrier in the modulate wave.
So total communication system is given by :-

TRANSMITTER
Source Transducer Modulator Channel

RECEIVER
Demodulator Transducer Destination

Fig. 15.2

Ø The source may be audio or video message.

Ø The transducer converts audio or video message to its equivalent electrical signa.
Ø The modulator mixes the message signal with carrier signal and generates modulated
signal.
Ø Through channel the modulated signal is transmitted. It may be any physical medium
or air/free space.
 Digital Circuits & Design 363

Ø The demodulator separates the message signal from the modulated signal.
Ø The transducer is used to convert the electrical form of message to its physical form.
Ø The destination may be TV, loud speaker etc.
15.4 MODULATION
The term modulation may be considered to mean variation on change in some
characteristic (eg. amplitude, frequency, phase) of the RF carrier wave in accordance
with the instantaneous value of the intensity of the signal.
The resultant wave is called the modulated wave. that means :
carrier wave + modulating signal = modulated wave.
The signal which contains information is known as modulating signal or baseband
signal.
The electronic device where the modulation is done is called a modulator.

Modulation

Analog Modulation Digital Modulation

Baseband Carrier
modulation modulation
AM Angle modulation
ASK FSK PSK QPSK
DSB SSB FM PM

DSB FC DSB SC ASK : Amplitude Shift Keying

AM : Amplitude modulation FSK : Frequency-Shift Keying
FM : Frequency Modulation PSK : Phase shift Keying
PM : Phase Modulaton PCM : Pulse Code Modulation
DSB FC : Double sideband full carrier QPSK : Quadrature Phase Shift Keying
DSB SC : Double sideband supplied carrier

15.5 AMPLITUDE MODULATION

This is the type of modulation where amplitude of carrier changes in accordance with
the amplitude of message signal.
Let es = Es cos ωst (Qe s = message signal)
Kaes = KaEs cos ωst
where Ka is the proportionality constant / amplitude sensitivity.
So the instantaneous voltage amplitude of the modulated wave is
EC + Kaes = EC + KaEs cos ωst
Since the frequency of the modulated wave is the same as the carrier frequency, the
modulated wave can be expressed as,
364 Basic Electronics

b
e m = E C + K a E s cos ωt cos ω C tg [Here we have omitted the phase angle φ as it
does not play any part in the modulation process]

LM
= EC 1 +
Ka Es OP
cos ω s t cos ω C t
N EC Q
b
= E C 1 + ma cos ω t g cos ω t
s C

Where ma is known as the modulation index or degree of modulation

Now; e m = E C cos ω C t + E C m a cos ω C t .cos ω s t

= E C cos ω C t +
ma E C
2
b mE
g
cos ω C + ω S t + a C cos ω C − ω S
2
b g
Hence the modulated ES
wave contains three Modulating
frequency terms f C ; Signal
fC + fS and fC − fS . Since t

fC >> fS , all of them are in EC

the RF range. The two new
frequencies are called side Carrier

b
bands; f C + fS is the g Signal t

upper sideband (USB) and Emax = EC + ES

bf g
− fS is the lower
C
Amplitude
Modulated Emin = EC–ES
sideband (LSB). The signal t
voltage amplitude of the For (m < 1)

ma E C Fig. 15.3
side bands is .
2
15.6 MODULATION INDEX
The term modulation index (ma) indicates the degree of change in the amplitude of
the carrier wave when it is modulated by a signal wave.
Modulation index can also defined as the ratio of amplitude of message signal to the
amplitude of carrier signal.
ES
So ma =
EC

E max − E min
and also ma =
E max + E min
 Digital Circuits & Design 365

E max − E C E C − E min Change in amplitude of carrier

Also ma = = =
EC EC Amplitude of the carrier
So; i) When ma = 0, means there is no modulation.
ii) When ma = 1 or 100%
then Emax = 2EC
Emin = 0
iii) 0 < ma < 1, there is under modulation

iv) ma > 1 represent the case of over modulation, where signal distortion
occurs.
E max + E min
∴ EC = → amplitude of carrier..
2
E max − E min
ES = → amplitude of baseband signal.
2
ES
Therefore; ma =
EC
The modulation index is also known as depth of modulation, degree of modulation
or modulation factor.

15.7 POWER CONTENT IN AM WAVE

Ø An amplitude modulated signal can be expressed as

ma A C
S( t ) = A C cos ω C t +
2
mA
b g b
cos ω C + ω m t + a C cos ω C − ω m
2
g
Ø We know that power of a sinusoidal signal is proportional to mean-square value of
the signal.
i.e. P = square of rms value of the signal.
i) Carrier Power PC :

FA I 2
A 2C
PC =
H C
2K
= 2
366 Basic Electronics
ii) Sideband power (Ps) :

=F
m A I + FG m A IJ
2 2
m a2 A C2
PS = PUSB + PUSB
H 2K H22K =
a C a C
2 2 2
iii) Total Power :

P1 = PC + PS =
A 2C m2a A 2C A 2C
+ =
m2
1+ a
LM OP
2 4 2 2 N Q
FG
PT = PC 1 +
m2a IJ
⇒ H 2 K
PC PC 2
= =
Now :
d
PT PC 1 + ma 2
2
2 + m2a i
PS ma2 A C2 4 ma2
= =
PT LM
A C2 2 1 + a
m2 OP
2 + ma2
N 2 Q
PS m 2a A 2C 4
= = m2a 2
PC A 2C 2
15.8 GENERATION OF AM WAVE
Ø Square Law Diode Modulation :
Ø Square Law Diode modulation circuit make use of non-linear current voltage
characteristics of diode.
Ø This method is used at low voltage levels because of the fact that current-voltage
characteristics of a diode is highly non-linear particularly in the low voltage region.
Ø The diagram of a square Law modulator is shown below.
V0
S(t)
+
C(t) ~
L C V0

m(t) ~
–
BPF
V CC
Fig. 15.4
 Digital Circuits & Design 367

Ø The Carrier & modulating signals are applied across the diode. The diode is operated
in its non-linear region of operation.
Ø The working of this circuit may be explained by considering the fact that when two
different frequencies are paned through a non-linear device, the process of amplitude
modulation takes place.
Ø When carrier & modulating frequencies are applied at the input of a diode then different
frequency terms appear at the output of diode.
Ø These different frequency terms are applied across a tuned circuit which is tuned to
the carrier frequency and has a narrow bandwidth just to pan two side bands along
with the carrier & reject other frequencies. Hence at the output of tuned circuit is
carrier & two side bands are obtained.
Mathematical Analysis
Ø Let C(t) = AC cos ωCt → Carrier signal with frequency ωC &
m(t) = Am cos ωmt → modulating signal with frequency ωm.
Ø Now S(t) = C(t) + m(t)
= AC cos ωCt + Am cos ωmt
Ø The non-linear relationship between voltage & current for a diode is expressed as
i = a + bs + cs2
Where i → current through the diode
s → signal across the diode.
Here i = a + b (AC cos ωCt + Am cos ωmt) + C (AC cos ωCt + Am cos ωmt)2
= a + bA C cos ω C t + bA m cos ω m t + C

dA 2
C cos2 ω C t + A 2m cos ω 2m t + 2A C A m cos w C t.cos ω m t i
= a + bA C cos ω C t + bA m cos ω m t + CA 2C cos2 ω C t + CA 2m cos2 ω m t
+2 C A C A m cos ω C t .cos ω m t

1 1
= a + bA C cos ω C t + bA m cos ω m t + CA 2C 2 cos2 ω C t + CA 2m 2 cos2 ω m t
2 2
b
+CA C A m 2 cos ω C t cos ω m t g
1
d 1
i
= a + bA C cos ω C t + bA m cos ω m t + CA C2 1 + cos2 ω C t + CA 2m 1 + cos2 ω m t
2 2
d i
b g b
+CA C A m cos ω C + ω m t + cos ω C − ω m t g
368 Basic Electronics

1 1
= a + bA C cos ω C t + bA m cos ω m t + C 2 A 2C + CA 2C cos2 ω C t +
2 2
1
2
1
CA 2m + CA 2m cos2 ω m t + CA m A C cos ω C + ω m t +
2
b g
b
CA mA C cos ω C − ω m t g
FG a + 1 CA 1 IJ
H 2 + CA 2m
K + bA
2
C
2 cos ω m t bA m cos ω m t
= C
+
1 2 3

FG 1 CA 1 IJ
H2 cos 2ω m t + C A 2m cos 2 ω m t
K b g
2
C
2 CA C A m cos ω C + ω m
+ +
4 5

+
b
CA C A m cos ω C − ω m t g
6
Ø The above equation consists of six terms such as
1 → d.c term
2 → carrier signal
3 → modulating signal
4 → harmonics of carrier & modulating signal.
5 → represents the upper side band
6 → represents the lower sideband.
Ø We have to transmit only carrier signal & the two side band frequencies.
Hence i 0 = bA C cos ω C t + CA m A C cos ω C + ω m t + b g
b
CA mA C cos ω C − ω m t g
= bA C cos ω C t + CA C A m cosbω C g b
+ ω m t + cos ω C + ω m tg
= b A C cos ω C t + 2C A C A m cos ω C t.cos ω m t

LM
= bA C 1 +
2cAm OP
cos ω m t cos ω C t
N b Q
⇒ i = b A C 1 + ma + cos ω m t cos ω C t
Ø The above equation is the required expression for AM signal.
 Digital Circuits & Design 369

15.9 DEMODULATION OF AM WAVE

Ø Envelope Detector :- A diode operating in a linear region of its V-I characteristics
can extract the envelope of an AM wave. This type of detector is known as envelope
detector or linear detector or diode detector.
Ø Envelope detector is most popular in commercial receiver circuits since it is very
simple & not expensive.
Ø The following circuit shows the envelope detector.

+
RS

SAM(t) ~ C R0 V0

–
Fig. 15.5
LPF

m(t)

(a) (b) (c)

Fig. 15.6

Ø For the positive half cycle the diode conducts & the capacitor is charged to the peak
value of the carrier voltage in time period τ = RSC
Ø However for a negative half cycle the diode is reversed biased & does not conduct.
This means that the input carrier voltage is disconnected from the RC network & the
diode becomes open circuited
Ø Therefore the capacitor starts discharging through the resistance R with a time constant
τ = RC. This time constant. τ = RC is so chosen that the voltage across the capacitor
C will not fall appreciably during the small period of negative half cycle & by that
time, the next positive cycle appears.
Ø This positive cycle again charges the capacitor C to the peak value of the carrier
voltage and the process repeats again & again.
370 Basic Electronics
Ø
Hence the output voltage across the capacitor C is a spiky modulating or baseband
signal. This means the voltage across the capacitor C is same as envelope of the
modulated carrier signal.
Ø The spikes can be reduced to a negligible amount by keeping the time constant RC
large so that the capacitor C discharges negligibly small.
Ø But much large value of τ produces another problem known as diagonal clipping.
15.10 NEED OF MODULATOIN
1) It improves the signal strength, means low frequency signal can’t transmit to a
larger distance but after modulation, frequency translation occur so strength increases
and can travel to a longer distance.
2) Reduce antenna height, because, antenna height α λ 2 of the transmitted signal. If
signal is transmitted without modulatoin then λ becomes very high so antenna design
will be impracticable.
3) Reduce distortion
4) Multiplexing can be done
5) Can transmit large amount of information.
6) We can change information from one orm to other i.e. encryption of data. Thats
why we are hiding the information without any hacking.
15.11 LIMITATIONS OF AMPLITUDE MODULATION
Amplitude modulation has the following drawbacks :
(i) Low efficiency : Since the maximum power that can be carried by the sidebands for the
distortionless transmission is 33.3%, the efficiency of amplitude modulation is low.
(ii) Small operating range : Since the efficiency is low, long distance transmission is difficult.
(iii) Noise transmission : The main disadvantage of amplitude modulation is that, AM is
practically not free from noise.
(iv) Poor audio quality : AM broadcasting stations are allotted a bandwidth of only 10 kHz
in order to reduce interference between adjacent broadcasting stations. Since the
highest modulating frequency can only be 5 kHz, it is insufficient to reproduce infor-
mation satisfactorily. Therefore, the quality of AM transmission is poor.
15.12 FREQUENCY MODULATION
In frequency modulation, the frequency of the carrier signal is made to vary in accor-
dance with the modulating signal. The amplitude and phase of the carrier signal remain
constant. The amount by which the carrier frequency is varied from its unmodulated value
is called frequency deviation (5). The amount of change of the frequency deviation in-
creases with an increase in the modulating signal voltage.
The process of varying the frequency of a carrier signal in proportion to the
instantaneous amplitude of the modulating signal without any variation in the
amplitude and phase of the carrier signal is known as frequency modulation.
 Digital Circuits & Design 371

Assume, for example, that the frequency of the transmitted carrier without modulation,
called the centre frequency (or rest frequency), is 100 MHz and the audio modulating
frequency is 50 kHz during the peaks of the audio signal. The carrier signal is then deviated
to 100.05 MHz during the positive peaks of the audio signal and to 99.95 MHz during the
negative peaks of the audio signal. The total deviation above and below centre frequency
is called the frequency swing. The frequency swing in the above example is then 100 kHz
(from 99.95 MHz to 100.05 MHz), or twice the deviation in either direction.
Vm vC VC vFM
vm
O =
t t

Modulating SignalCarrier Signal FM Signal

Fig. 15.7
15.13 COMPARISON BETWEEN AM AND FM
Amplitude Modulation Frequency Modulation
1. The amplitude of the carrier signal 1. The frequency of the carrier signal varies
varies in accordance with modulating in accordance with modulating signal,
signal, keeping frequency and phase keeping amplitude and phase constant.
constant.
2. Modulation index (ma) varies from 0 2. Modulation index (mf ) can have values
to 1. from 1 to any value.
3. AM has only two sidebands. 3. FM has an infinite number of sidebands.
4. When Vm > Vc, over modulation results 4. There is no limit on Vm and no distortion
in distortion, hence, V m has to be occurs in FM.
limited.
5. Bandwidth is small (10 kHz) and is 5. Bandwidth is wider on account of a
proportional to the highest frequency number of sideband pairs (200 kHz) and
in the modulating signal. is independent of the modulating signal.
6. In AM, all transmitted power is not 6. In FM, all transmitted power is useful.
useful. The total power remains constant.
7. Area of reception is large. 7. Area of reception is smaller than AM.
8. AM broadcasts operate in the medium 8. FM broadcasts operate in very high
and high frequency (MF and HF) frequency and ultra high frequency (VHF
ranges, and UHF) ranges.
9. Noise suppression is not good. 9. Noise suppression is better than in AM.
10. AM is less complex and less 10. FM is more complex and more
expensive. expensive.
11. Adjacent channel interference is 11. Adjacent channel interference is Jess in
more in AM than present in FM. FM.
12. Modulating voltage amplitude 12. Modulating voltage amplitude determines
determines RF carrier frequency. RF carrier amplitude.
13. Sidebands are always symmetrical. 13. Sidebands are always symmetrical.
372 Basic Electronics
Example 15.1 :
Am amplitude modulated carrier wave has maximum and minimum amplitudes of
750 mV and 250 mv respectively. Calculate the modulation index and the
percentage modulation.
Solution : Given Vmax = 750 mV and Vmin = 250 mV
Vmax − Vmin
Modulation index, ma = V +V
max min

750 × 10 −3 − 250 + 10 −3
=
750 × 10 −3 + 250 × 10 −3

500
∴ ma = = 0.5
1000
Percentage modulation = 0.5 × 100 = 50
Example 15.2 : A radio transmitter radiates 10 kW when the modulation percentage is
60. How much of this carrier power ?
Solution : Given Pt = 10 kW, ma = 60% and PC = ?
Total power of the amplitude modulated wave is given by

d
Pt = PC 1 + ma2 2 i
LM
10 × 103 = PC 1 +
0.62OP
= PC 1 +
LM
0.36 OP
N 2 Q N 2 Q
10 × 103 = PC [1.18]

103
PC = 10 × = 8.47 kW
118
.
Example 15.3 : The total power content of an AM wave is 1200 W for 80% modulation.
Determine (1) the power transmitted by the carrier (2) power transmitted by
each sideband.
Solution : Given Pt = 1200 W, ma = 80% = 0.8. PC = ? and PSB = ?

We know d
Pt = PC 1 + ma2 2 i
1200 = PC [1 + (0.82/2)]
1200 = PC (1.32)
or PC = 1200/1.32 = 909.09 W
 Digital Circuits & Design 373

Pt − PC 120 − 909.09
Power in each sideband, PSB = =
2 2
PSB = 145.45 W

Example 15.4 : The output of an amplitude modulator is found to have maximum and
minimum amplitudes of 10 V and 5 V respectively. What is the modulation index ?
Solution : Given Vmax = 10V, Vmin = 5V and ma = ?
Vmax − Vmin 10 − 5
We know ma = = = 0.33
Vmax + Vmin 10 + 5
Example 12.5 : What is the power developed in an AM wave in a load of 100Ω , when the
peak voltage of the carrier is 80V and modulation factor is 0.6 ?
Solution : Given R = 100Ω, VC = 80 , ma = 0.6 and Pt = ?

VC2 802
We know Carrier power, PC = = = 32 W
2 R 2 × 100

Total power d i
Pt = PC 1 + ma2 2

= 32 1 + d0.6 2i
2

Pt = 32 [1.18] = 37.76 W

Example 15.6: The carrier power radiated from the transmitter is 75 kW. If the percentage
of modulation is 40, calculate the total power.
Solution : Given PC = 75 kW, ma = 40% = 0.4

Total power is given by Pt = PC 1 + ma 2

2
d i
d
Pt = 75 × 103 1 + 0.4 2 2 i
= 75 × 103 [1.08] = 81 kW
Example 15.7 : A 220 W carrier is modulated to a depth of 65%. Calculate the total
power in the modulated wave.
Solution : Given PC = 220 W, ma = 65% = 0.25
Total power in the modulated (AM) wave is given by

F m2a I
GH
Pt = PC 1 +
2 JK
374 Basic Electronics

= 220 = 1 +
LM (0.65) 2 OP
= 220 1 + 0.211 = 266W
N 2 Q
Example 15.8 : A 500 W, 100 kHz carrier is modulated to a depth of 60% by modulating
signal of frequency 1 kHz. Calculate the total power transmitted. What are sideband
components of the wave ?
Solution : Given PC = 500 Wtfc = 100 kHz, ma = 60% = 0.6 and fm = 1 kHz.

P = P 1 +
m2a LM OP
Total power, t C
2 N Q
LM
= 500 1 +
(0.6) 2 OP
= 600 1 + 018
. = 590 W
N 2 Q
Frequencies of the sideband components = (fC + fm) and (fC – fm)
∴ Upper sideband frequency = (fC + fm) = 100 + 1 = 101 kHz
Lower sideband frequency = (fC – fm) = 100 – 1 = 99 kHz

15.14 DIGITAL COMMUNICATION TECHNIQUES

15.14.1 Sampling
Sampling of the signal is the fundamental operation in signal processing.
A continious time signal is first converted to discrete time signal by sampling process.
The sufficient number of samples of the signal must be taken, so that the original
signal is represented in its samples completely. Also it is possible to recover the original
signal completely from its samples. The no. of samples to the taken depends on the maximum
signal frequency present in the signal.
15.14.2 Sampling theorem
A continuous time signal may be completely represented in its samples and recovered
back if the sampling frequency is

fs ≥ 2 f m
fs = sampling frequency.
fm = Max. frequency present in the signal.
Let m(t) → Base band signal.
s(t) → Train of pulses (same amplitude)
 Digital Circuits & Design 375

S(t)
m(t)

t
(a) Continuous time signal (b) Impulse train or
Fig. 15.8 simpling function

Both signals are passed through a multiplier circuit The output is the sampled signal.
g(t)

x(t)
Multiplier g(t) t

s(t)
(a) Sampler Circuit (b) Sampled signal
Fig. 15.9

15.14.3 Quantization

Ø In communication system whenever there is necessity to change analog signal to

digital form, the concept of quantization arises.
Ø Whenever we have to convert an analog signal to digital form we have to convert a
continuous time signal in the form of digits.
Ø The conversion can be better understood by the following figure.
m(t) g(t)

t t

(a) Continuous time signal (b) Sampled signal

Fig. 15.10
376 Basic Electronics

R| 4
3
Quartization || 2

|S
Level 1

||
0 t
–1

||
–2

T
–3
–4
Quantized Signal
Fig. 15.11
Ø First of all we have to take samples of the given signal according to sampling theorem.
Ø Then at each of the samples the magnitude of the signal is measured. This means that
the signal no longer is a continuous functions of time but rather it is a discrete-time
signal.
Ø Since the magnitude of each sample can take any value in continuous range, the
signal is still an analog signal.
Ø Then the total amplitude range which the signal may occupy is divided into a number
of standard level called as

15.15 PULSE CODE MODULATION (PCM)

Pulse code modulation uses sampling theorem and quantization for digital modulation.
The combined operations of sampling and quantization generate a quantized Pulse
Amplitude Modulated (PAM) waveform. i.e a train of pulses whose amplitudes are restricted
to a member of discrete magnitudes.
In case of pulse code modulation each quantized level is represented by a code number
and the code number is transmitted rather then sample values itself.
The code number to be transmitted is converted into its binary equivalent before
transmission. The digits of the binary representation of the code number are transmitted as
pulses. Hence this system is called as Pulse Code Modulation (PCM)
Let us assume that we have to transmit the message signal m(t) shown below.
 Digital Circuits & Design 377

m(t) g(t)

t t

(a) Message Signal

(b) Sampled Signal

7 4
6 3
5 2
4 1

3 –1
2 –2
1 –3
0 –4
(c) Quantized Signal Fig. 15.12
The signal is in analog form. So at first it is to be converted into digital form. The
signal is first sampled by using sampling theorem. Then the signal is quantized to give PAM
signal.
The analog signal m(t) is limited in its excessions to the range from – 4 to 4 volts.
Thus the step size is set at 1 volt.
Then each quantization level are assigned a code member and each code number has
its representation in binary arithmetic ranging from 000 to 111 i.e. from 0 to 7 respectively.
Thus in correspondence with each sample a specified sample value is found which is
then converted to the nearest quantization level and the code number & to its binary
representation.
If we have to transmit the signal the codes are transmitted in pulse code modulation
system.

Sample Value 4 4.3 3.7 2.4 1 −1

Nearest quanti −
4 4 4 2 1 −1
zation level
Code Number 7 7 7 5 4 3
Binary Equivalent 111 111 111 101 100 011
378 Basic Electronics
15.16 PCM SYSTEM
Ø The block diagram of PCM system is shown below.

Quantized PAM Digitally

encoded
signal
Analog
Sampler Quantizer Encoder
Signal

Communication
A to D Converter

Channel
D to A Converter
m1(t)
Filter Quantizer Decoder

Fig. 15.13

Ø The analog signal m(t) is sampled & these samples are subjected to the operation of
qantization.
Ø The quantized samples are applied to an encoder. The encoder responds to each such
samples by the generation of a unique & identifiable binary pulse.
Ø The combination of the quantizer and encoder is called an analog-to-digital converter.
Thus the A/D converter outputs are the digitally encoded signal.
Ø This digitally encoded signal is then transmitted through the communication channel.
Ø When the digitally encoded signal arrives at the receiver, the first operation to be
performed is the decoding the signal.
Ø So the received signal is then fed to a decoder. The decoder performs the reverse
operation that was performed by encoder.
Ø To separate the noise from the signal that has been added during transmission is
performed by again a quantizer and hence the decoder output is given to the quantizer
block.
Ø Thus the output is the sequence of quantized multilevel sample pulses.
Ø Hence the decoder and quantizer is also called as a digital to analog, D/A converter.
Ø The quantized PAM signal is then reconstructed and then filtered to reject any
frequency components using outside of the baseband.
Ø Now the final output signal is identical with the input m(t).
 Digital Circuits & Design 379

15.17 FIBRE OPTIC COMMUNICATION

Block diagram of Fibre optic communication
Ø The components of a typical fibre-optic communications system are shown below.
Pulses
Information Light at rapid rate
input Coder/ Light source
(voice/video) Converter transmitter

Receiver Pulses

Shaper Origin
Decoder
voice/video

Photocell/ Amplifier
light detector Fig. 15.14

Ø The information signal to be transmitted may be voice, video or computer data. At

first these messages are converted into a series of digital pulses by an A/D converter.
Ø These digital pulses are then used to flash a powerful light source off and on very
rapidly. Specially LED or LASER. The light sources generates light with of certain
intensity.
Ø The light beam pulses are then fed into a fibre optic cable where they are transmitted
over long distances.
Ø At the receiving end a light sensitive device known as a photocell or light detector
is used to detect the light pulses.
Ø This photocell or photodetector converts the light pulses into an electrical signal.
The electrical signals are amplified and reshaped back into digital form.
Ø The digital signal or pulses are fed to a decoder such as a D/A converter where the
original voice or video is recovered.
Ø In very long transmission systems repeater units must be used along the way. Since
the light is greatly attenuated when it travels over long distances at some point it may
be too weak to be received reliably.
Ø To overcome this problem, special relay stations are used to pick up the light beam,
convert it back into electrical pulses that are amplified and then transmit the pulses on
another light beam.
380 Basic Electronics
15.17.1 Structure of Optical Fibre
Ø The fibres which are used for optical communication are wave guides mode of
transparent dielectrics. Its function is to guide visible & infrared light over long distances.

Jacket
Priimary coating
cladding
core

Secondary coating
(Jacket)
Ø An optical fibre consists of an inner cylinder which is made of glass called the core.
The core carries light.
Ø The core is surrounded by another cylindrical shell of lower refractive index called
the cladding.
Ø The cladding helps to keep the light with in the core through the phenomenon of total
internal reflection.
Ø For greater strength & protection of the fibre a soft plastic coating (primary coating)
is used along with another layer of coating known as secondary coating.
1) Refractive index of core > Refractive index of cladding.
2) The concept used for propagation of light through optical fiber is total internal reflection
which is the modification of Snell’s law of refraction. i.e

µ 1 sin θ 1 = µ 2 sin θ 2
RSQ θ → angle of incidence
1

T θ → angle of refraction
1

sin θ1 µ 2 µ
⇒ = ⇒ sin θ1 = 2 sin θ 2
sin θ 2 µ1 µ1

⇒ θ1 = sin −1
FG µ IJ = θ
Hµ K
2
When θ 2 = 900 C
1

Here θC = critical angle.

For total internal reflection,
θ1 > θC
15.17.2 Principle of Optical Fibre
Ø When the angle of incidence is made greater than the critical angle the light ray will
actually be reflected from the interface. This phenomenon is called as total internal
reflection.
 Digital Circuits & Design 381

Ø The optical fibres are based on the principle of total internal reflection. An optical
fibre is a hair thin cylindrical fibre of glass or any transparent medium. It consists of
many thousands of very long fine quality glass/ quartz fibres.
Ø Again the fibres are coated with a layer of cover refractive index.
Ø The fibre optic Cross sectional view is shown below.
Coating (µ = 1.5)
θ
r
i

Fig. 15.16 Fibre material (µ =1.7)

& When light is incident on one end of the fibre at small angle it passes through the fibre
as explained below.
→ Let i be the angle of incidence of light ray with the axis & r be the angle of refraction.
→ If θ be the angle at which the ray is incident on the fibre boundary then θ = (90 - r).
Let ni be the refractive index of fibre.

→ FH IK
If θ > θC critical angle where θC = sin −1 1 n then the ray is totally internally reflected.
i

Ø In this way the ray undergoes repeated total internal reflections until it emerges out of
the other end of the fibre.
Ø Thus the light ray is guided through the fibre from one end to other end without any
energy being lost due to refraction.
15.17.3 Types of optical fibre
There are two basic ways of classifying fiber optic cables. The first way is an indication
of how the index of refraction varies across the cross section of the cable. The second
way of classification is by mode. Mode refers to the various paths that the light rays can
take in passing through the fiber. Usually these two methods of classification are combined
to define the types of cable.
Step Index
There are two basic ways of defining the index of refraction variation across a cable.
These are step index and graded index. Step index refers to the fact that there is a sharply
defined step in the index of refraction where the fibre core and the cladding interface. It
means that the core has one constant index of refraction N1 while the cladding has another
constant index of refraction N2.
Graded Index
The other type of cable has a graded index. In this type of cable, the index of
refraction of the core is not constant. Instead, the index of refraction varies-smoothly and
382 Basic Electronics
continuously over the diameter of the core. As you get closer to the center of the core, the
index or retraction gradually increases, reaching a peak at the core and then declining as
the other outer edge of the core is reached. The index of refraction of the cladding is
constant.
15.17.4 Application of Fibre Optics
1) Local & long distance telephone system.
2) TV studio-to-transmitter interconnection i.e. elimination of microwave link.
3) Aircraft communications.
4) Aircraft control.
5) Shipboard communications.
6) Closed-circuit TV Systems used in buildings for security.
15.17.5 Advantages of Fibre Optics
1) Wider Bandwidth
3) Light weight
4) Small size
5) Fibre optic cables are stronger than electrical cables.
6) High security.
7) No possibility of internal noise & cross Talk generation along with the immunity to
ambient electrical noise.
8) No hazards of short circuits as in metal wires.
9) Immunity to temperature & moisture conditions.
10) No need for additional equipment to protect against grounding and voltage problems.
11) Less noisy.
12) High data rate.
15.18 NOISE
Ø Noise may be defined as any unwanted introduction of energy tending interfere with
the proper reception and reproduction of transmitted signals.

Noise

External Noise
Internal Noise

Atmospheric Extraterestrial
Noise Noise
Industrial Noise

Thermal Agitation Transit time

Shot Noise
Noise Noise
 Digital Circuits & Design 383

15.18.1 External Noise

Ø Atmospheric Noise : The lighting discharges in thunderstorms and other natural
electric disturbances occurring in the atmosphere causes atmospheric noise. It originates
in the form of amplitude modulated impulses and because such process are random in
nature it is spread over most of the RF spectrum normally used for broadcasting.
Ø Extraterrestrial Noise : The extraterrestrial noise is of various types such as solar
noise, cosmic noise etc. The sun radiates so manything our way that we use to transmit
signals. Under normal condition, there is a constant radiadiation from the sun which
causes noise in the signal.
Ø Again sun is a constantly charging star which undergoes cycles of peak activity from
which electrical disturbances except such as corona flares & sunspots that affects
the signal.
Ø Since distant stars are also suns and have high temperature, they radiate RF noise in
the same manner as our sun.
The noise received is called thermal or black-body noise & is distributed fairly uniformly
over the entire sky. Such noise are called cosmic noise.
Ø Industrial Noise : The industries in urban, suburban & other industrial areas radiates
unwanted frequency components that affects the signal & causes noise.
15.18.2 Internal Noise
Thermal Agitation Noise
Most internal noise is caused by a phenomenon know as thermal agitation. Thermal
agitation refers to the random motion of the atoms and electrons in an electronic component
caused by heat. Increasing the temperature causes this motion to increase. Since the
components are conductors, the movement of electrons constitutes a current flow that
causes a small voltage to be produced across that component.
Short Noise
Electronic components such as transistors and tubes are also major contributors of
Noise. The most common type of noise referred to as shot noise, which is produced by
the random arrival of electrons or holes at the output element, at the plate in a tube, or at
the collector or drain in a transistor. Shot noise is also produced by the random movement
of electrons or holes across a PN junction. Even though current flow is established by
external bias voltages, there will still be some random movement of electrons or holes due
to discontinuities in the device.
Transit Time Noise
Another kind of noise that occurs in transistors is called transit time noise. Transit
time is the duration of time that it takes for a current carrier such as a hole or electron to
move from the input to the output. The devices themselves are very tiny, so the distances
involved are minimal. Yet the time it takes for the current carriers to move even a short
distance is finite. At low frequencies this time is negligible. But when the frequency of
384 Basic Electronics
operation is high and the period of the signal being processed is the same order of magnitude
as the transit time, then problems can occur. The transit time shows up as a kind of random
noise within the device, and this noise directly proportional to the frequency of operation.

SHORT QUESTIONS AND ANSWERS

Q.1. What is modulation?

Ans. The process of super imposing audio signal over the carrier (high frequency) wave is
called the modulation.
Q.2. What is amplitude modulation ?
Ans. The process of varying amplitude of the high frequency or carrier wave in accordance
with the intelligence (code, voice or music) to be transmitted, keeping the frequency and
phase of the carrier wave unchanged, is known as the amplitude modulation.
Q.3. What is frequency modulation ?
Ans. The process of varying frequency of the high frequency or carrier wave in accordance
with the modulating signal keeping the amplitude and phase of the carrier wave unchanged
is known as the frequency modulation.
Q.4. What is modulation index in AM ?
Ans. The extent to which the amplitude of the carrier wave is varied by the modulating signal is
called the modulation index and is defined as the ratio of change in amplitude of the carrier
wave to the amplitude of normal carrier wave.
Q.5. Why the reception in case of amplitude modulation is usually noisy ?
Ans. In case of AM, the reception is usually noisy because radio receiver cannot distinguish
between the amplitude variations that represent noise and those contain the desired signal.
Q.6. Why is DSB-FC transmission system widely used in broadcasting inspite of the fact that
SSB-SC or SSB transmission system has numerous advantages over-it?
Ans. DSB-FC transmission system is widely used in broadcasting because of its relative simplicity
of its modulating equipment.
Q.7. Why is base modulation employed in TV transmission ?
Ans. Base modulation is employed in TV transmission because it needs little power and can
meet the power need of large bandwidth.
Q.8. What is frequency deviation?
Ans. The change or shift above or below the mean or centre frequency is called the frequency
deviation.
Q.9. What is carrier swing ?
Ans. The total variation in frequency from minimum to maximum value is called the carrier
swing and it is twice the frequency deviation.
Q.10. What is FM index ?
Ans. The ratio of frequency deviation to modulation frequency is called the FM index.
 Digital Circuits & Design 385

Q.11. What is deviation ratio ?

Ans. The ratio of maximum permitted frequency deviation to the maximum permitted audio-
frequency is known as the deviation ratio.
Q.12 What is demodulation ?
Ans : The process of recovering of original modulating signal (intelligence) from the modulated
carrier wave is called the demodulation or detection.

EXERCISE

1. What is radio communication? Why is it called wireless communication?

2. What is meant by frequency and wavelength of a radio wave? Write the relation between
the two.
3. Explain with a block diagram, the general communication system.
4. What is modulation? Why is it required? Name the different modes of modulation.
5. Define amplitude modulation and modulation index of AM wave.
6. Why is modulation necessary for the transmission of intelligence?
7. What is modulation? Why is it required?
8. Write a short note on “amplitude modulation”.
9. What is modulation? Explain why is it needed in radio communication?
10. Explain the principle of amplitude modulation with suitable waveforms.
11. (a) What is modulation? Why is it necessary ?
(b) Explain amplitude and frequency modulation.
12. What do you mean by amplitude modulation? Write the equation for AM.
13. What is amplitude modulation ? Derive an expression for the instantaneous voltage of the
amplitude modulated wave.
14. Define modulation index of an AM. Derive an expression for the modulation index in terms
of the maximum and minimum amplitudes of the AM wave.
15. Derive an expression for the total power of AM wave in terms of modulation index.
16. Explain the distribution of power in the carrier and sidebands of an AM wave.
17. Prove that the total power radiated in AM is 150% of the carrier wave.
18. Distinguish between AM and FM.
19. What is amplitude modulation ? Derive the expressions for (a) modulation index and
(b) transmitted power in terms of carrier power and modulation index.
20. What is noise and explain its different types.
21. What fibre optic communication ? Write its principle of working.
22. What are different types of optical fibre.
23. What is total internal reflection.
24. A transmitter supplies 8 kW to the antenna when unmodulated. Determine the total power
radiated when modulated to 30%. (Ans. 8.36 kW)
25. The r.m.s value of the antenna current before modulation is 10.A and after modulation is
12A. Calculate the percentage modulation employed assuming no distortion. (Ans: 93.8%)
26. In an aerial, the aerial current (r.m.s) before modulation is 10 A and after modulation, it rises
to 11.6/4. Determine percentage modulation. If the carrier power is 10 kW, what is the
power after modulation ? (Ans : 83.13%, 13.456 kW)
27. A transmitter radiates 9 kW without modulation and 10.125 kW after modulation. Determine
depth of modulation. (Ans: 0.5)
28. A transmitter radiates 1200 W of power under carrier conditions. If the carrier is modulated
simultaneously by two tones to 20% and 40% respectively, determine the total power radiated.
(Ans. 1320 W)
29. An AM wave has a side frequency power of 50 W when the carrier is modulated by a single
modulating frequency. The depth of modulation is 40%. Calculate the carrier power and the
total power taken by the complete modulated wave. (Arts : 1350 W)
30. A transmitter uses a power of 20 kW when sending an AM wave. What will be the saving
in power if (a) the carrier is suppressed and (b) only one sideband is transmitted when the
depth of modulation is 30%. (Ans: 19.138 kW;431W)
31. The antenna current of an AM transmitter is 8 A when only the carrier is sent, but it increases
to 8.93 A when the carrier is sinusoidally modulated. Find the percentage modulation.
(Ans: 70.0%)
32. The antenna current of an AM transmitter modulated to a depth of 40 % by an audio wave
is 11 A. It increases to 12 A as a result of simultaneous modulation by another wave. What
is the modulation index due to this second wave ? (Ans: 64.2%)
33. An amplitude modulated current is represented by i = 10 (1 + 0.4 sin 3140f) sin (6.28 × 105)t.
Determine (a) the modulation depth (b) the modulating frequency (c) the carrier frequency.
Expand the expression and calculate r.m.s values of current and side frequency currents.
The modulated current is fed to an aerial whose input resistance is 50 Ω. Calculate total
power fed to the aerial. (Ans : 40%, 500 Hz, 100 kHz and 1.414 A, 2.7 kW)
34. Calculate the percentage power saving when the carrier and one of the sidebands is suppressed
in an AM wave modulated to a depth of 100% and 50%. (Ans: 83.3%, 94.5%)
35. The total power content of an AM wave is 2.64 kW at a modulation factor of 80%. Determine
the power content of (i) carrier (ii) each side band. (Ans. (i) 2 kW (ii) 0.32 kW)

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