EECS150 - Digital Design

Lecture 23 - FFs revisited, FIFOs,

ECCs, LSFRs

April 16, 2009

John Wawrzynek

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Cross-coupled NOR gates

remember,

• If both R=0 & S=0, then cross-couped NORs

equivalent to a stable latch:

• If either R or S becomes =1 then state may

change:

• What happens if R or S or both become = 1?

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Asynchronous State Transition Diagram
Transitions triggered by input changes.

SR Latch:

• S is “set” input
• R is “reset” input
QQ’=00 is often called a “forbidden state”
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Nand-gate based SR latch

• Same behavior as cross-coupled NORs with inverted inputs.

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 Level-sensitive SR Latch

• The input “C” works as an “enable” signal, latch only changes output
when C is high.
• usually connected to clock.
• Generally, it is not a good idea to use a clock as a logic signal (into
gates etc.). This is a special case.
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D-latch

All state elements could

Compare to transistor version:
be built using logic gates.

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 Flip-flops

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J-K FF

• Add logic to eliminate

“indeterminate” action of
RS FF.
• New action is “toggle”
• J = “jam”
clk
• K = “kill”
J
Q
K

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 Storage Element Taxonomy

synchronous asynchronous
level-sensitive edge-triggered
D-type   n.a.
JK-type   n.a.
RS-type   
“latch” “flip-flop” “latch”

“natural” form
 “possible” form

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Design Example with RS FF

• With D-type FF state elements, new state is computed
based on inputs & present state bits - reloaded each cycle.
• With RS (or JK) FF state elements, inputs are used to
determine conditions under which to set or reset state
bits.
• Example: bit-serial adder (LSB first)

With D-FF for carry

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 Bit-serial adder with RS FF
• RS FF stores the carry:
a b ci ci+1 s
Carry kill a’b’

Carry generate
ab

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FIFOs

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 First-in-first-out (FIFO) Memory
• Used to implement queues. • Producer can perform many writes
without consumer performing any
• These find common use in
reads (or vis versa). However,
computers and communication because of finite buffer size, on
circuits. average, need equal number of
• Generally, used for rate matching reads and writes.
data producer and consumer: • Typical uses:
– interfacing I/O devices.
stating state Example network interface.
Data bursts from network, then
processor bursts to memory
buffer (or reads one word at a
after write time from interface).
Operations not synchronized.
– Example: Audio output.
Processor produces output
after read samples in bursts (during
process swap-in time). Audio
DAC clocks it out at constant
sample rate.

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FIFO Interfaces
• Address pointers are used internally
DIN RST CLK to keep next write position and next
read position into a dual-port
WE
FIFO memory.
FULL
write ptr
HALF FULL
EMPTY
read ptr
RE
DOUT • If pointers equal after write ⇒ FULL:

• After write or read operation, FULL

and EMPTY indicate status of buffer.
• Used by external logic to control write ptr read ptr
own reading from or writing to the If pointers equal after read ⇒ EMPTY:
•
buffer.
• FIFO resets to EMPTY state. write ptr read ptr
• HALF FULL (or other indicator of
partial fullness) is optional.
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 FIFO Implementation Details
• Assume, dual-port memory with asynchronous read,
synchronous write.
• Binary counter for each of read and write address.
CEs controlled by WE and RE.
• Equal comparator to see when pointers match.
• Flip-flop each for FULL and EMPTY flags:
WE RE equal EMPTYi FULLi
0 0 0 0 0
• Control logic with truth-
0 0 1 EMPTYi-1 FULLi-1 table shown to left.
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 0 1
1 1 0 0 0
1 1 1 EMPTYi-1 FULLi-1

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Xilinx Virtex5 FIFOs

• Virtex5 BlockRAMS include special logic for FIFOs.
• Details in User Guide (ug190).
• Take advantage of separate dual ports and independent ports
clocks.

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 ECCs

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Error Correction Codes (ECC)

• Memory systems generate errors (accidentally flipped-bits)
– DRAMs store very little charge per bit
– “Soft” errors occur occasionally when cells are struck by alpha
particles or other environmental upsets.
– Less frequently, “hard” errors can occur when chips permanently fail.
• Where “perfect” memory is required
– servers, spacecraft/military computers, …
• Memories are protected against failures with ECCs
• Extra bits are added to each data-word
– extra bits are used to detect and/or correct faults in the memory
system
– in general, each possible data word value is mapped to a unique
“code word”. A fault changes a valid code word to an invalid one -
which can be detected.

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 Simple Error Detection Coding
Parity Bit
• Each data value, before it is • Each word, as it is read from
written to memory is “tagged” memory is “checked” by finding
with an extra bit to force the its parity (including the parity
stored word to have even parity: bit).

b 7b 6b 5b 4b 3b 2b 1b 0p b 7b 6b 5b 4b 3b 2b 1b 0p

+ +
c
• A non-zero parity indicates an error occurred:
– two errors (on different bits) is not detected (nor any even number of
errors)
– odd numbers of errors are detected.

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Hamming Error Correcting Code

• Use more parity bits to pinpoint bit(s) 1 2 3 4 5 6 7
in error, so they can be corrected. p1 p2 d1 p3 d2 d3 d4
• Example: Single error correction
(SEC) on 4-bit data Note:
Bit position number number bits
– use 3 parity bits, with 4-data bits 001 = 110 from left to
results in 7-bit code word 011 = 310 right.
– 3 parity bits sufficient to identify any 101 = 510
p1
one of 7 code word bits
111 = 710
– overlap the assignment of parity bits
so that a single error in the 7-bit word 010 = 210
can be corrected 011 = 310
p2
• Procedure: group parity bits so they 110 = 610
correspond to subsets of the 7 bits: 111 = 710
– p1 protects bits 1,3,5,7 100 = 410
– p2 protects bits 2,3,6,7 101 = 510
110 = 610
p3
– p3 protects bits 4,5,6,7
111 = 710
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 Hamming Code Example
1 2 3 4 5 6 7
• Example: c = c3c2c1= 101
p1 p2 d1 p3 d2 d3 d4
– error in 4,5,6, or 7 (by c3=1)
– error in 1,3,5, or 7 (by c1=1)
– Note: parity bits occupy power-of-
two bit positions in code-word. – no error in 2, 3, 6, or 7 (by c2=0)
– On writing to memory: • Therefore error must be in bit 5.
• parity bits are assigned to force • Note the check bits point to 5
even parity over their respective
groups.
– On reading from memory: • By our clever positioning and
assignment of parity bits, the
• check bits (c3,c2,c1) are generated
check bits always address the
by finding the parity of the group
and its parity bit. If an error position of the error!
occurred in a group, the
corresponding check bit will be 1, • c=000 indicates no error
if no error the check bit will be 0.
• check bits (c3,c2,c1) form the
position of the bit in error. • Review procedure with example
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Hamming Error Correcting Code

• Overhead involved in single • Adding on extra parity bit covering the
error correction code: entire word can provide double error
– let p be the total number of detection
parity bits and d the number of 1 2 3 4 5 6 7 8
data bits in a p + d bit word. p1 p2 d1 p3 d2 d3 d4 p4
– If p error correction bits are to
point to the error bit (p + d
• On reading the C bits are computed
cases) plus indicate that no
(as usual) plus the parity over the
error exists (1 case), we need:
entire word, P:
2p >= p + d + 1,
thus p >= log(p + d + 1)
C=0 P=0, no error
for large d, p approaches log(d)
C!=0 P=1, correctable single error
C!=0 P=0, a double error occurred
C=0 P=1, an error occurred in p4 bit

Typical modern codes in DRAM memory systems:

64-bit data blocks (8 bytes) with 72-bit code words (9 bytes).
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 LFSRs

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Linear Feedback Shift Registers (LFSRs)

• These are n-bit counters exhibiting pseudo-random behavior.
• Built from simple shift-registers with a small number of xor gates.
• Used for:
– random number generation
– counters
– error checking and correction
• Advantages:
– very little hardware
– high speed operation
• Example 4-bit LFSR:

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 4-bit LFSR

• Circuit counts through 24-1 different

non-zero bit patterns.
• Leftmost bit decides whether the
“10011” xor pattern is used to
compute the next value or if the
register just shifts left.
• Can build a similar circuit with any
number of FFs, may need more xor
gates.
• In general, with n flip-flops, 2n-1
different non-zero bit patterns.
• (Intuitively, this is a counter that
wraps around many times and in a
strange way.)
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Applications of LFSRs
• Performance: • Can be used as a random
– In general, xors are only ever 2- number generator.
input and never connect in series. – Sequence is a pseudo-
– Therefore the minimum clock period random sequence:
for these circuits is: • numbers appear in a
T > T2-input-xor + clock overhead random sequence
• repeats every 2n-1 patterns
– Very little latency, and independent
– Random numbers useful in:
of n!
• computer graphics
• This can be used as a fast counter, • cryptography
if the particular sequence of count • automatic testing
values is not important. • Used for error detection and
– Example: micro-code micro-pc correction
• CRC (cyclic redundancy
codes)
• ethernet uses them

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 Galois Fields - the theory behind LFSRs
• LFSR circuits performs • Example fields:
multiplication on a field. – set of rational numbers
• A field is defined as a set with the – set of real numbers
following: – set of integers is not a field
– two operations defined on it: (why?)
• “addition” and “multiplication” • Finite fields are called Galois
– closed under these operations fields.
– associative and distributive laws • Example:
hold – Binary numbers 0,1 with XOR
– additive and multiplicative identity as “addition” and AND as
elements “multiplication”.
– additive inverse for every – Called GF(2).
element
– multiplicative inverse for every
non-zero element

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Galois Fields - The theory behind LFSRs

• Consider polynomials whose coefficients come from GF(2).
• Each term of the form xn is either present or absent.
• Examples: 0, 1, x, x2, and x7 + x6 + 1
= 1·x7 + 1· x6 + 0 · x5 + 0 · x4 + 0 · x3 + 0 · x2 + 0 · x1 + 1· x0
• With addition and multiplication these form a field:
• “Add”: XOR each element individually with no carry:
x4 + x3 + + x + 1
+ x4 + + x2 + x
x3 + x2 +1
• “Multiply”: multiplying by x is like shifting to the left.
n

x2 + x + 1
× x+1
x +x+1
2

x3 + x2 + x
x3 +1
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 Galois Fields - The theory behind LFSRs
• These polynomials form a • Additionally, …
Galois (finite) field if we take the • Every Galois field has a primitive
results of this multiplication element, α, such that all non-zero
modulo a prime polynomial p(x). elements of the field can be
– A prime polynomial is one that expressed as a power of α. By
cannot be written as the product raising α to powers (modulo p(x)),
of two non-trivial polynomials all non-zero field elements can be
q(x)r(x) formed.
– Perform modulo operation by • Certain choices of p(x) make the
subtracting a (polynomial) simple polynomial x the primitive
multiple of p(x) from the result. element. These polynomials are
If the multiple is 1, this called primitive, and one exists for
corresponds to XOR-ing the every degree.
result with p(x). • For example, x4 + x + 1 is primitive.
• For any degree, there exists at So α = x is a primitive element and
least one prime polynomial. successive powers of α will
generate all non-zero elements of
• With it we can form GF(2n) GF(16). Example on next slide.

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Galois Fields - The theory behind LFSRs

α0 = 1 • Note this pattern of coefficients
α1 = x matches the bits from our 4-bit
LFSR example.
α =
2 x2

α =x
3 3

α4 = x +1
α =
5 x +x
2

α = x + x2
6 3

α7 = x3 +x +1
α =
8 x2 +1 α4 = x4 mod x4 + x + 1
α9 = x3 +x = x4 xor x4 + x + 1
α10 = x2 + x + 1 =x+1
α11 = x3 + x2 + x • In general finding primitive
α12 = x3 + x2 + x + 1 polynomials is difficult. Most people
α13 = x3 + x2 +1 just look them up in a table, such
as:
α =x
14 3 +1
α =
15 1
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 Primitive Polynomials
x2 + x +1 x12 + x6 + x4 + x +1 x22 + x +1
x3 + x +1 x13 + x4 + x3 + x +1 x23 + x5 +1
x4 + x +1 x14 + x10 + x6 + x +1 x24 + x7 + x2 + x +1
x5 + x2 +1 x15 + x +1 x25 + x3 +1
x6 + x +1 x16 + x12 + x3 + x +1 x26 + x6 + x2 + x +1
x7 + x3 +1 x17 + x3 + 1 x27 + x5 + x2 + x +1
x8 + x4 + x3 + x2 +1 x18 + x7 + 1 x28 + x3 + 1
x9 + x4 +1 x19 + x5 + x2 + x+ 1 x29 + x +1
x10 + x3 +1 x20 + x3 + 1 x30 + x6 + x4 + x +1
x11 + x2 +1 x21 + x2 + 1 x31 + x3 + 1
x32 + x7 + x6 + x2 +1
Galois Field Hardware
Multiplication by x ⇔ shift left
Taking the result mod p(x) ⇔ XOR-ing with the coefficients of p(x)
when the most significant coefficient is 1.
Obtaining all 2n-1 non-zero ⇔ Shifting and XOR-ing 2n-1 times.
elements by evaluating xk
for k = 1, …, 2n-1
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Building an LFSR from a Primitive Polynomial

• For k-bit LFSR number the flip-flops with FF1 on the right.
• The feedback path comes from the Q output of the leftmost FF.
• Find the primitive polynomial of the form xk + … + 1.
• The x0 = 1 term corresponds to connecting the feedback directly to the D input
of FF 1.
• Each term of the form xn corresponds to connecting an xor between FF n and n
+1.
• 4-bit example, uses x4 + x + 1
– x4 ⇔ FF4’s Q output
– x ⇔ xor between FF1 and FF2
– 1 ⇔ FF1’s D input
• To build an 8-bit LFSR, use the primitive polynomial x8 + x4 + x3 + x2 + 1 and
connect xors between FF2 and FF3, FF3 and FF4, and FF4 and FF5.

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 Error Correction with LFSRs

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Error Correction with LFSRs

• XOR Q4 with incoming bit sequence. Now values of shift-register don’t follow a
fixed pattern. Dependent on input sequence.
• Look at the value of the register after 15 cycles: “1010”
• Note the length of the input sequence is 24-1 = 15 (same as the number of
different nonzero patters for the original LFSR)
• Binary message occupies only 11 bits, the remaining 4 bits are “0000”.
– They would be replaced by the final result of our LFSR: “1010”
– If we run the sequence back through the LFSR with the replaced bits, we would get
“0000” for the final result.
– 4 parity bits, “neutralize” the sequence with respect to the LFSR.
11001000111 0000 ⇒ 1010
11001000111 1010 ⇒ 0000
• If parity bits not all zero, an error occurred in transmission.
• If number of parity bits = log total number of bits, then single bit errors can be
corrected.
• Using more parity bits allows more errors to be detected.
• Ethernet uses 32 parity bits per frame (packet) with 16-bit LFSR.

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