Features:

8 levels of interrupts. Can be cascaded in master-slave configuration to handle 64 levels of interrupts. Internal priority resolver. Fixed priority mode and rotating priority mode. Individually maskable interrupts. Modes and masks can be changed dynamically. Accepts IRQ, determines priority, checks whether incoming priority > current level being serviced, issues interrupt signal. In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector number. Polled and vectored mode. Starting address of ISR or vector number is programmable. No clock required.

Pinout Bi-directional, tristated, buffered data lines. Connected to data bus directly or through buffers Active low read control Address input line, used to select control register Active low chip select

D0-D7 RD-bar A0 CS-bar

WR-bar Active low write control

Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on these lines. In slave mode, the PIC CAS0-2 reads slave ID no. from master on these lines. It may be regarded as slave-select. Slave program / enable. In non-buffered mode, it is SP-bar SP-bar / input, used to distinguish master/slave PIC. In buffered EN-bar mode, it is output line used to enable buffers INT IR0-7 Block diagram Interrupt line, connected to INTR of microprocessor Asynchronous IRQ input lines, generated by peripherals. INTA-bar Interrupt ack, received active low from microprocessor

ICW1 (Initialisation Command Word One) A0 0 D7 A7 D6 A6 D5 A5 D4 1 D3 LTIM D2 ADI D1 SNGL D0 IC4

D0: IC4: 0=no ICW4, 1=ICW4 required D1: SNGL: 1=Single PIC, 0=Cascaded PIC D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204, etc) 0=ISR's are 8 byte apart (0200, 0208, etc) D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is A7 A6 A5 A4 A3 A2 A1 A0 of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if ADI=0. A4-A0 (or A5-A0) are set by 8259 itself: ADI=1 (spacing 4 bytes) IRQ A7 A6 A5 A4 A3 A2 A1 A0 IR0 A7 A6 A5 0 IR1 A7 A6 A5 0 IR2 A7 A6 A5 0 IR3 A7 A6 A5 0 IR4 A7 A6 A5 1 IR5 A7 A6 A5 1 IR6 A7 A6 A5 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADI=0 (spacing 8 bytes) IRQ A7 A6 A5 A4 A3 A2 A1 A0 IR0 A7 A6 0 IR1 A7 A6 0 IR2 A7 A6 0 IR3 A7 A6 0 IR4 A7 A6 1 IR5 A7 A6 1 IR6 A7 A6 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IR7 A7 A6 A5 1

IR7 A7 A6 1

ICW2 (Initialisation Command Word Two) Higher byte of ISR address (8085), or 8 bit vector address (8086). A0 1 D7 A15 D6 A14 D5 A13 D4 A12 D3 A11 D2 A10 D1 A9 D0 A8

ICW3 (Initialisation Command Word Three) A0 1 Master Slave

D7 S7 0

D6 S6 0

D5 S5 0

D4 S4 0

D3 S3 0

D2 S2 ID3

D1 S1 ID2

D0 S0 ID1

Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000 0100)

ICW4 (Initialisation Command Word Four) A0 1

D7 0

D6 0

D5 0

D4 SFNM

D3 BUF

D2 M/S

D1 AEOI

D0 Mode

SFNM: 1=Special Fully Nested Mode, 0=FNM M/S: 1=Master, 0=Slave AEOI: 1=Auto End of Interrupt, 0=Normal Mode: 0=8085, 1=8086

OCW1 (Operational Command Word One) A0 1 D7 M7 D6 M6 D5 M5 D4 M4 D3 M3 D2 M2 D1 M1 D0 M0

IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)

OCW2 (Operational Command Word Two) A0 1 D7 R D6 SL D5 EOI D4 0 D3 0 D2 L3 D1 L2 D0 L1

R SL EOI Action

0 0 EOI 0 1 1 0 Auto rotation of priorities (L3L2L1=000) 1 0 0 0 1 1 Specific rotation of priorities (Lowest priority ISR=L3L2L1) 1 1 0 1 OCW3 (Operational Command Word Three) A0 1 D7 D7 D6 ESMM D5 SMM

1 1 1 0 0 1 0 0

Non specific EOI (L3L2L1=000) Specific EOI command (Interrupt to clear given by L3L2L1) Rotate priorities on non-specific EOI Rotate priorities in auto EOI mode set Rotate priorities in auto EOI mode clear Rotate priority on specific EOI command (resets current ISR bit) Set priority (does not reset current ISR bit) No operation

D4 0

D3 1

D2 MODE

D1 RIR

D0 RIS

ESMM SMM Effect 0 1 1 X 0 1 No effect Reset special mask Set special mask

Interrupt sequence (single PIC) 1. 2. 3. 4. 5. 6. 7. 8. 9. One or more of the IR lines goes high. Corresponding IRR bit is set. 8259 evaluates the request and sends INT to CPU. CPU sends INTA-bar. Highest priority ISR is set. IRR is reset. 8259 releases CALL instruction on data bus. CALL causes CPU to initiate two more INTA-bar's. 8259 releases the subroutine address, first lowbyte then highbyte. ISR bit is reset depending on mode.

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Intel 8259
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The Intel 8259 is a family of Programmable Interrupt Controllers (PICs) designed and developed for use with the Intel 8085 and Intel 8086 8-bit and 16-bit microprocessors. The family originally consisted of the 8259, 8259A, and 8259B[citation needed] PICs, though a number of manufacturers make a wide range of compatible chips today. The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device.
Contents

[hide] 1 History 2 Programming Considerations o 2.1 DOS and Windows o 2.2 Other Operating Systems o 2.3 Edge/Level Triggered Mode o 2.4 Spurious Interrupts 3 PC/XT and PC/AT 4 See also 5 External links

6 References

[edit] History

The 8259 was included in the original PC introduced in 1981 and maintained by the PC/XT when introduced in 1983. A second 8259 was added with the introduction of the PC/AT. The 8259 has coexisted with the Intel APIC Architecture since its introduction in Symmetric Multi-Processor PCs. Modern PCs have since begun to completely phase out the use of the 8259 family in favor of the exclusive use of the Intel APIC Architecture. However, while not anymore a separate chip, the 8259 interface is still provided by the Southbridge chipset on modern x86 motherboards. The main connectors on an 8259 are as follows: eight interrupt input request lines named IRQ0 through IRQ7, an interrupt request output line named INTR, interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connectors include CAS0 through CAS2 for cascading between 8259s. Up to eight slave 8259s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259. There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). The IRR maintains a mask of the current interrupts that are pending acknowledgement, the ISR maintains a mask of the interrupts that are

pending an EOI, and the IMR maintains a mask of interrupts that should not be sent an acknowledgement. End Of Interrupt (EOI) operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. Auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged. Edge and level interrupt trigger modes are supported by the 8259A. Fixed priority and rotating priority modes are supported. The 8259 may be configured to work with an 8085 or an 8086. On the 8086, the interrupt controller will provide an interrupt number on the data bus when an interrupt occurs; instead, the interrupt cycle of the 8085 will issue three bytes on the data bus (corresponding to a CALL instruction in the 8085 instruction set). The 8259A provides additional functionality compared to the 8259 (in particular buffered mode and level-triggered mode) and is upward compatible with it. It is believed that the NEC Corporation created the 8259A[citation needed], and the 8259B may be nothing more than a mnemonic for the second 8259A introduced in the PC/AT[citation needed].
[edit] Programming Considerations

[edit] DOS and Windows

Programming an 8259 in conjunction with DOS and Microsoft Windows has introduced a number of confusing issues for the sake of backwards compatibility, which extends as far back as the original PC introduced in 1981. The first issue is more or less the root of the second issue. DOS device drivers are expected to send a non-specific EOI to the 8259s when they finish servicing their device. This prevents the use of any of the 8259's other EOI modes in DOS, and excludes the differentiation between device interrupts rerouted from the master 8259 to the slave 8259. The second issue deals with the use of IRQ2 and IRQ9 from the introduction of a slave 8259 in the PC/AT. The slave 8259's INT output is connected to the master's IR2. The IRQ2 line of the ISA bus, originally connected to this IR2, was rerouted to IR1 of the slave. Thus the old IRQ2 line now generates IRQ9 in the CPU. To allow backwards compatibility with DOS device drivers that still set up for IRQ2, a handler is installed by the BIOS for IRQ9 that redirects interrupts to the original IRQ2 handler. On the PC, the BIOS (and thus also DOS) traditionally maps the master 8259 interrupt requests (IRQ0-IRQ7) to interrupt vector offset 8 (INT08-INT0F) and the slave 8259 (in PC/AT and later) interrupt requests (IRQ8-IRQ15) to interrupt vector offset 112 (INT70INT77). This was done despite the first 32 (INT00-INT1F) interrupt vectors being reserved by the processor for internal exceptions (this was ignored for the design of the PC for some reason). Because of the reserved vectors for exceptions most other operating systems map (at least the master) 8259 IRQs (if used on a platform) to another interrupt vector base offset.

[edit] Other Operating Systems

Since most other operating systems allow for changes in device driver expectations, other 8259 modes of operation, such as Auto-EOI, may be used. This is especially important for modern x86 hardware in which a significant amount of time may be spent on I/O address space delay when communicating with the 8259s. This also allows a number of other optimizations in synchronization, such as critical sections, in a multiprocessor x86 system with 8259s.
[edit] Edge/Level Triggered Mode

Since the ISA bus does not support level triggered interrupts, level triggered mode may not be used for interrupts connected to ISA devices. This means that on PC/XT, PC/AT, and compatible systems the 8259 must be programmed for edge triggered mode. On MCA systems, devices use level triggered interrupts and the interrupt controller is hardwired to always work in level triggered mode. On newer EISA, PCI, and later systems the Edge/Level Control Registers (ELCRs) control the mode per IRQ line, effectively making the mode of the 8259 irrelevant for such systems with ISA buses. The ELCR is programmed by the BIOS at system startup for correct operation. The ELCRs are located 0x4d0 and 0x4d1 in the x86 I/O address space. They are 8-bits wide, each bit corresponding to an IRQ from the 8259s. When a bit is set, the IRQ is in level triggered mode; otherwise, the IRQ is in edge triggered mode.
[edit] Spurious Interrupts

The 8259 generates spurious interrupts in response to a number of conditions. The first is an IRQ line being deasserted before it is acknowledged. This may occur due to noise on the IRQ lines. In edge triggered mode, the noise must maintain the line in the low state for 100nS. When the noise diminishes, a pull-up resistor returns the IRQ line to high, thus generating a false interrupt. In level triggered mode, the noise may cause a high signal level on the systems INTR line. If the system sends an acknowledgment request, the 8259 has nothing to resolve and thus sends an IRQ7 in response. This first case will generate spurious IRQ7's. A similar case can occur when the 8259 unmask and the IRQ input deassertion are not properly synchronized. In many systems, the IRQ input is deasserted by an I/O write, and the processor doesn't wait until the write reaches the I/O device. If the processor continues and unmasks the 8259 IRQ before the IRQ input is deasserted, the 8259 will assert INTR again. By the time the processor recognizes this INTR and issues an acknowledgment to read the IRQ from the 8259, the IRQ input may be deasserted, and the 8259 returns a spurious IRQ7. The second is the master 8259's IRQ2 is active high when the slave 8259's IRQ lines are inactive on the falling edge of an interrupt acknowledgment. This second case will generate spurious IRQ15's, but is very rare.
[edit] PC/XT and PC/AT

The PC/XT ISA system had one 8259 controller, while PC/AT and later systems had two 8259 controllers, master and slave. IRQ0 through IRQ7 are the master 8259's interrupt lines, while IRQ8 through IRQ15 are the slave 8259's interrupt lines. The actual names on the pins on an 8259 are IR0 through IR7. IRQ0 through IRQ15 are the names of the ISA bus's lines to which the 8259's are historically attached.

Master 8259 o IRQ0 Intel 8253 or Intel 8254 Programmable Interval Timer, aka the system timer o IRQ1 Intel 8042 keyboard controller o IRQ2 not assigned in PC/XT; cascaded to slave 8259 INT line in PC/AT o IRQ3 8250 UART serial port COM2 and COM4 o IRQ4 8250 UART serial port COM1 and COM3 o IRQ5 hard disk controller in PC/XT; Intel 8255 parallel port LPT2 in PC/AT o IRQ6 Intel 82072A floppy disk controller o IRQ7 Intel 8255 parallel port LPT1 / spurious interrupt Slave 8259 (PC/AT and later only) o IRQ8 real-time clock (RTC) o IRQ9 no common assignment o IRQ10 no common assignment o IRQ11 no common assignment o IRQ12 Intel 8042 PS/2 mouse controller o IRQ13 math coprocessor o IRQ14 hard disk controller 1 o IRQ15 hard disk controller 2

Initially IRQ7 was a common choice for the use of a sound card, but later IRQ5 was used when it was found that IRQ7 would interfere with the printer port (LPT1). The serial ports are frequently disabled to free an IRQ line for another device. IRQ2/9 is the traditional interrupt line for an MPU-401 MIDI port, but this conflicts with the ACPI system control interrupt (SCI is hardwired to IRQ9 on Intel chipsets); this means ISA MPU-401 cards with a hardwired IRQ 2/9, and MPU-401 device drivers with a hardcoded IRQ 2/9, cannot be used in interrupt-driven mode on a system with ACPI enabled.