Design of a Digital

AC/DC SMPS using

the 56F8323 Device

Designer Reference Manual

56800E
16-bit Digital Signal Controllers

DRM074
Rev. 0
08/2005

freescale.com
Design of a Digital AC/DC SMPS using the 56F8323 Device
Designer Reference Manual

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Revision History
Revision Page
Date Description
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08/2005 0 Initial release N/A

 TABLE OF CONTENTS

Chapter 1
Hardware Design of a Power Factor Correction System
1.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3 Main Power Circuit Hardware Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3.1 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3.2 Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.3 Main Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.4 Output Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.5 Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 Drive Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 Sample Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Chapter 2
Hardware Design of a DC/DC Converter System
2.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Main Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3.1 Main Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3.2 Transformer’s Turns Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.3 Resonance Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.4 Transformer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.4.1 Number of Turns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.4.2 Lead Diameter and the Primary Winding’s Number of Leads . . . . . . . . . . . . . . 2-5
2.3.4.3 The Secondary Winding’s Number of Leads . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.4.4 Check the Window’s Filling Factor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.5 Resonance Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.6 Output Filter Inductor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.7 Output Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.8 Output Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.4 Sample Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5 Drive Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6 Optocoupler Isolation Drive Circuit Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

Table of Contents, Rev. 0

Freescale Semiconductor i
Preliminary
Chapter 3
Controller Board Hardware Architecture
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Control System Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.3 CPU Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4 ADC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.5 Power Supply Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.6 DAC Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.7 LED Display Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.8 Signals Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Chapter 4
Communication Interface Board Hardware Architecture
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 SCI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Chapter 5
Control Strategy Design
5.1 Control of Power Factor Correction System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2 Arithmetic of Power Factor Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2.1 Arithmetic of Current Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2.2 Voltage and Current Loop Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 Control of DC/DC Converter Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3.1 DC/DC Converter Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.3.2 Voltage and Current Loops Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Chapter 6
Software System Design—PWM Control Strategy
6.1 PFC PWM Control Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1.1 DC/DC PWM Value Register Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

ii Freescale Semiconductor
Preliminary
Chapter 7
Software Architecture
7.1 Software Infrastructure—Dual Digital Signal Controllers . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Details of Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2.1 PFC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2.2 DC/DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3 Software Interrupt Service Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3.1 PFC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3.2 DC/DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Chapter 8
Flow Chart of Software System Design
8.1 Software System Design—Flow Chart of PFC Control System . . . . . . . . . . . . . . . . . . 8-1
8.2 Software System Design—Flow Chart of DC/DC Control System . . . . . . . . . . . . . . . . 8-4

Table of Contents, Rev. 0

Freescale Semiconductor iii
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
iv Freescale Semiconductor
Preliminary
 LIST OF FIGURES
1-1 PFC Configuration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 PFC Main Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 PFC Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1-4 PFC Sampling Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2-1 DC/DC System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2-2 DC/DC Main Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2-3 Output Voltage Sample Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-4 Inductance Current Sample Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-5 Output Voltage Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6 Output Voltage Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
3-1 Connection Between Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3-2 CPU Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-4 ADC Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3-5 Power Supply Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-6 DAC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3-7 LED Display Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3-8 Signals Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
4-1 Communication Board Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-3 SCI Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
5-1 Digital PFC Arithmetic Structure Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 Simple PFC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5-3 Discrete Voltage Loop Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-4 PFC Module Frame Based on the 56F8323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5-5 Digital Control PSFB Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5-6 Power Factor Correction Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
6-1 PFC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6-2 Gate Drive Waveforms of the Main and ZVS Transistors . . . . . . . . . . . . . . . . . . . . 6-2
6-3 DC/DC Full Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6-4 DC/DC PWM Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6-5 Current Doubler and Synchronous Rectification PWM Generation . . . . . . . . . . . . 6-4
7-1 System Software Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

List of Figures, Rev. 0

Freescale Semiconductor v
Preliminary
8-1 PFC Main Program Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8-2 PFC Reload Interrupt ISR Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8-3 PFC Timer A2 Period Interrupt ISR Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8-4 DC/DC Main Program Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8-5 DC/DC Timer A0 Period Interrupt ISR Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8-6 DC/DC Timer A1 Period Interrupt ISR Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

vi Freescale Semiconductor
Preliminary
 LIST OF TABLES
1-1 Interface Description with the Controller
(Connected to J1 of Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2-1 Interface Description with the Controller
(Connected to J1 of Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3-1 Controller Board Pin-Out Description
(Connected to J16 and J17 of the Power Board) . . . . . . . . . . . . . . . . . . . . . 3-2
3-2 JTAG Interface Pin-Out Description
(Connected to J204 of the Communication Board) . . . . . . . . . . . . . . . . . . . 3-3
3-3 SCI Interface Pin-Out Description
(Connected to J201 of the Communication Board) . . . . . . . . . . . . . . . . . . . 3-3
3-4 DAC Debug Interface Pin-Out Description
( Debug purpose only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3-5 GPIO Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3-6 ADC Resource Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3-7 PWM Resources Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
4-1 JTAG Interface Pin-Out Description
(Connected to the Controller’s J2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 SCI Interface Pin-Out Description
(Connected to the Controller’s J3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
5-1 PFC Experiment PI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5-2 PFC Experiment PI Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
6-1 Relation Between the 56F8323’s Ports and Control Signals . . . . . . . . . . . . . . . . . 6-3
7-1 Bandwidth Consideration of PFC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7-2 Bandwidth Consideration of DC/DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

List of Tables, Rev. 0

Freescale Semiconductor vii
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
viii Freescale Semiconductor
Preliminary
About This Document
This manual describes the use of a 56F8323 device in an SMPS application.

Audience
This manual targets design engineers interested in developing a digital AC/DC SMPS application.

Organization
This User’s Manual consists of the following sections:
• Chapter 1, Hardware Design of a Power Factor Correction System, explains system and
hardware designs for a PFC system.
• Chapter 2, Hardware Design of a DC/DC Converter System, provides system and hardware
designs for the application’s DC/DC system.
• Chapter 3, Controller Board Hardware Architecture, contains a detailed explanation of the
controller board’s hardware design.
• Chapter 4, Communication Interface Board Hardware Architecture, details the hardware
architecture of the communication interface board.
• Chapter 5, Control Strategy Design, describes control strategies for the application’s PFC and
DC/DC systems.
• Chapter 6, Software System Design—PWM Control Strategy, explains design of the PWM
and DC/DC software systems.
• Chapter 7, Software Architecture, details the application’s software architecture.
• Chapter 8, Flow Chart of Software System Design, illustrates the software system design.
• Appendix A, Schematics, contains schematics for the digital AC/DC SMPS application.
• Appendix B, SMPS Bill of Materials, lists all parts used in the application.

Preface, Rev. 0
Freescale Semiconductor ix
Preliminary
Conventions
This document uses the following notational conventions:

Typeface, Symbol
Meaning Examples
or Term

Courier Code examples //Process command for line flash

Monospaced Type

Italic Directory names, ...and contains these core directories:

project names, applications contains applications software...
calls,
functions, ...CodeWarrior project, 3des.mcp is...
statements,
procedures, ...the pConfig argument....
routines,
arguments, ...defined in the C header file, aec.h....
file names,
applications,
variables,
directives,
code snippets
in text

Bold Reference sources, paths, ...refer to the Targeting DSP56F83xx Platform

emphasis manual....
...see: C:\Program Files\Freescale\help\tutorials

Blue Text Linkable on-line ...refer to Chapter 7, License....

Number Any number is considered a 3V

positive value, unless pre- -10
ceded by a minus symbol to DES-1
signify a negative value

ALL CAPITAL # defines/ # define INCLUDE_STACK_CHECK

LETTERS defined constants

Brackets [...] Function keys ...by pressing function key [F7]

Quotation Returned messages ...the message, “Test Passed” is displayed....

marks, “...”
...if unsuccessful for any reason, it will return “NULL”...

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

x Freescale Semiconductor
Preliminary
Definitions, Acronyms, and Abbreviations
The following list defines the acronyms and abbreviations used in this document. As this template
develops, this list will be generated from the document. As we develop more group resources, these
acronyms will be easily defined from a common acronym dictionary. Please note that while the
acronyms are in solid caps, terms in the definition should be initial capped ONLY IF they are
trademarked names or proper nouns.
IC Integrated Circuit
LC Inductor Capacitance
PI Proportional-Integral
PSFB Phase Shifted Full Bridge
RMS Root Mean Square
SMPS Switch Mode Power Supply
ZCS Zero Current Switch
ZVS Zero Voltage Switch
ZVT Zero Voltage Transition

References
The following sources were used to produce this book; we recommend that you have a copy of these
references:
1. DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor, Inc.
2. 56F8300 Peripheral User Manual, MC56F8300UM, Freescale Semiconductor, Inc.
3. 56F8323 Data Sheet, MC56F8323, Freescale Semiconductor, Inc.
4. Implementing a Digital AC/DC Switched-Mode Power Supply using a 56F8300 Digital
Signal Controller, AN3115, Freescale Semiconductor, Inc.

Preface, Rev. 0
Freescale Semiconductor xi
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
xii Freescale Semiconductor
Preliminary
 System Design

Chapter 1
Hardware Design of a Power Factor Correction System

1.1 Requirements
This section provides the hardware design for the Power Factor Correction (PFC) system. Specifications
and performance include:
Input voltage: 85~265V AC
Input frequency: 45~65Hz
Rating output voltage: 370V, voltage range: 350—390V
Rating output power: 500W
Switch frequency: 100K
Power factor: >95%
Efficiency: >90%

1.2 System Design

The main circuit consists of two single-switch PFC circuits operated in interleaved mode; see
Figure 1-1. The circuit is composed of Q1/Q2, D1/D2, L1/L2 and filter capacitance C and includes an EMI
filter, input relay and full-wave rectifier. In addition, two assistant switches, Q3/Q4, and their assistant
network are introduced to realize the Zero Voltage Switch (ZVS) of two main switches.
In the PFC module system, the 56F8323 samples voltage signal, Vrect, from the full-wave rectifier; input
current, Iin; and output voltage, Vbus. The outer voltage loop, G1, insures that the output voltage is
constant. The output of the voltage loop determines the reference shape of the current loop, which
guarantees the input current is a sine wave. The input voltage sample not only determines the input
current’s crossing point, but at the same time, the input feed forward voltage also accelerates the system
response speed when input changes. The speed of the inner current loop, G2, is more rapid. It
compares the current sample with current reference, extracts the duty parameters through the
current-loop PI regulator, and sends control signals through PWM0—2, achieving the aim of PFC and
stabilizing the output voltage.
Zero Voltage Transition (ZVT) technology can realize the ZVS of the main switch and the Zero Current
Switch (ZCS) of the boost diode, reducing di/dt of the diode and consequently reducing switch loss and
the system’s EMI. The operating theory is to realize the ZVS of the main switch, paralleling capacitance
in its drain-source, and thus limiting the switch’s dv/dt. Before the main switch operates, it releases the
charge on capacitance to zero through an assistant circuit, realizing the ZVS of the main switch. The
assistant circuit operates a short time before the main switch turns on.

Hardware Design of a Power Factor Correction System, Rev. 0

Freescale Semiconductor 1-1
Preliminary
 Figure 1-1. PFC Configuration Diagram

1.3 Main Power Circuit Hardware Design

The topology of the main circuit is a double-boost circuit with interleaving and paralleling. The switch
period and duty ratio of the two switches are equal, but conduct time is interlaced. Three signals, input
current (Ii), input voltage (Vi), and output bus voltage (Vbus), are sampled and sent to the 56F8323.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

1-2 Freescale Semiconductor
Preliminary
 Main Power Circuit Hardware Design

D45 DSEP60-06A
1 2 1 2
1 2 1 2
L8 250u
F2 250V/10A C104
R107

10/3W
0.003U/2K

D46 DSEP60-06A
1 2 1 2 1 2 DCBUS+
1 2 1 2 K A DCBUS+
L9 250u
F3 250V/10A C105
R108 D47

2
D48 DSEP8-06B
10/3W
DSEP8-06B 0.003U/2K

A K
R109
C106 560K

1
470nF/275V
R110
1 2 1 2 560K
1 2 1 2
L10 8u L11 8u
R111
AC1 470K/2W

2
1

2
1
AC1
J26 J27

1
R113 D49
ZVSJP2 ZVSJP2 D50 C107 C108
390K C109 C110 J20

2 1
PFCDRV1 PFCDRV2
1 1 470uF 470uF

SD

SD
PFCDRV1 G 470p(op) PFCDRV2 G 470p(op) 1
Q14 MUR460 Q15 MUR460
R114 2

2
4

TE29 IRFPC60 IRFPC60 390k DCBUS

3
D51 INPUTVOL R112
R117 R118

2
3 1 470K/2W
220 220
C

K A
INPUTVOL
ZVSDRV1 ZVSDRV2 DCBUS
1 1
C

SD

SD
ZVSDRV1 G ZVSDRV2 G TE30 DCBUS
IR25XB08H Q16 Q17
R120 R122 C111
13K 15K IRF830B IRF830B
2

3
220p INPUTVOL
R123 R121
D52 D53 C103
Input voltage sampling 15K 13K
MUR260 MUR260 220pF
Sended to primary controller's
board as ADC input signal TE28
AC2 GNDP
AC2
U23
HDC-15LX
6 5 GNDP
DCBUS-
DCBUS
1 2
+12V_P -12V_P
+12V_P
LEM PFC output voltage sampling
+12V_P
+12V_P Sended to primary controller's board
INPUTCUR_SAM
3

C101 as ADC input signal

INPUTCUR 0.1uF
TE31 R124
C112 GNDP
300 GNDP
Input current sampling
C102
Sended to primary controller's 10nF
board as ADC input signal
0.1uF
-12V_P
-12V_P

-12V P

Figure 1-2. PFC Main Circuit

1.3.1 Inductor Selection

Maximum peak line current:

2 × PO 2 × 500
I pk (max) = = =9.24A
ηVin (min) 0.9 × 85
Eqn. 1-1
Ripple current:

∆I L = 20% I pk =0.2×9.24=3.7A
Eqn. 1-2
Determine the duty factor at Ipk, where Iin(peak) is the peak of the rectified line voltage.

Vo − Vin ( peak ) 380 − 2 × 85

D= = =0.68
Vo 380
Eqn. 1-3
Inductance calculation; fs is the switching frequency.

Vin × D 2 × 85 × 0.68
L= = =221 µH
fs × ∆I 100000 × 3.7 Eqn. 1-4
Round up to 250µH.

Hardware Design of a Power Factor Correction System, Rev. 0

Freescale Semiconductor 1-3
Preliminary
1.3.2 Output Capacitor
Output filter inductor can be calculated as follows:

2 × PO × ∆t
C=
V 2
− VO2(min)
O (max)
Eqn. 1-5
Po = 500W
Vo(min) = 380 x (1-10%) = 342V
Vo(max) = 380 x (1 +10%) = 418V
∆t = 50ms
According to Equation 1-5, C = 866µH.
Select the output capacitor to be C = 940µH.
Two 470µH / 450V electrolytic capacitors, connected in parallel, are chosen.

1.3.3 Main Switch

The voltage limit of the main switch is:

VCEM(S)>1.5Vcem(S)＝1.5Vin（max）＝1.5×380=570V Eqn. 1-6

The circuit limit of the main switch is calculated by RMS value:

2 ⋅ Po 2 ⋅ 500
I CEM ( S ) > 1.5 I = 1.5 × = 1 .5 × =13.86 A
L(max) η ⋅ Vin(min) 0.9 × 85
Eqn. 1-7
Select main switch Q400—Q401 to be the MOSFET IRFPC60LC.
Parameters are:
• VDSS = 600V
• ID = 16A
• RDS(on)tye = 0.4Ω
• TO-247AC package

1.3.4 Output Diode

The voltage limit of the output diode is:

VCEM(S)>1.5Vcem(S)＝1.5Vin（max）＝1.5×380=570V Eqn. 1-8

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

1-4 Freescale Semiconductor
Preliminary
 Main Power Circuit Hardware Design

The circuit limit of the output diode is calculated by RMS value:

2 ⋅ Po 2 ⋅ 500
I CEM ( S ) > 1.5 I = 1.5 × = 1 .5 × =13.86 A
L(max) η ⋅ Vin(min) 0.9 × 85
Eqn. 1-9
Select output diode D400—D402 to be FRED DSEP60-06A.
Parameters are:
• VRRM = 600V
• IFAVM = 60A
• trr = 35nS
• TO-247AD package

1.3.5 Inductor Design

As shown in Section 1.3.1, L = 250µH.
Select Bm = 0.3T.
Select magnetic core to be E133, with an effective area of 118mm2.
Inductor winding can be calculated as follows:

LI L (max)
N= = 38.2
Ae Bm
Eqn. 1-10
Select N = 38
The gap is:

µ o N 2 Ae 1.25 × 10 −6 × 382 × 118 × 10 −6

δ= = = 0.85mm
L 250 ×10 −6 Eqn. 1-11
When work frequency of inductance is 150kHz, the penetrate depth of copper lead is:

2 1
Λ= = = 0.209mm
2πf s µγ 3.14 ×100 × 10 ×1.25 × 10 −6 × 58 ×10 6
3
Eqn. 1-12
Where:
γ is the electric conductive ratio of lead
µ is the magnetic conductive ratio of lead
A copper lead with a diameter less than 0.42mm can be selected.
In this case, a high intensity lead with a 0.33mm diameter has an effective area of 0.0855mm2.

Hardware Design of a Power Factor Correction System, Rev. 0

Freescale Semiconductor 1-5
Preliminary
Selecting circuit density to be J = 3.5A / mm2, the area of leads is:
3.84
S= = 1.1mm 2
3.5
Thirteen leads with a 0.33mm diameter must be used.

38 × 13 × 0.0855
Kc = = 0.32 <<0.35
132 Eqn. 1-13

1.4 Drive Circuit Hardware Design

A simple and reliable gate drive circuit based on a current-limiting, single-channel driver, IC IR2125, is
used, shown in Figure 1-3.

Figure 1-3. PFC Drive Circuit

1.5 Sample Circuit Hardware Design

The sample circuit of three signals, input current, (Ii), input voltage (Vi), and output bus voltage (Vbus), is
shown in Figure 1-4. A simple voltage divider is used for the input voltage sample and the bus voltage
sample. A current LEM HDC-15LX is used for the input current sample.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

1-6 Freescale Semiconductor
Preliminary
 Controller Interface

Figure 1-4. PFC Sampling Circuit

1.6 Controller Interface

The entire PFC is controlled by one 56F8323 device, which provides a complete digital solution for
high-frequency Power Factor Correction. The interface between the PFC and the controller is shown in
Table 1-1.

Table 1-1. Interface Description with the Controller

(Connected to J1 of Controller)
Pin # Name Description Pin# Name Description

J17-1A GND_A Analog ground J17-1B GND_A Analog ground

J17-2A J17-2B
J17-3A DCBUS ADC channel #4, PFC J17-3B
output voltage sample
J17-4A INPUT_VOL ADC channel #0, PFC J17-4B INPUT_CUR ADC channel #1, PFC
input voltage sample input current sample
J17-5A GND_A Analog ground J17-5B GND_A Analog ground
J17-6A GND_A Analog ground J17-6B GND_A Analog ground
J17-7A +3.3VA +3.3V analog power J17-7B +3.3VA +3.3V analog power
J17-8A GND_A Analog ground J17-8B GND_A Analog ground
J17-9A GND_A Analog ground J17-9B GND_A Analog ground
J17-10A RXD1 SCI1 receive data input J17-10B RXD1 SCI1 receive data input
J17-11A TXD1 SCI1 transmit data output J17-11B TXD1 SCI1 transmit data output

Hardware Design of a Power Factor Correction System, Rev. 0

Freescale Semiconductor 1-7
Preliminary
 Table 1-1. Interface Description with the Controller (Continued)
(Connected to J1 of Controller)
Pin # Name Description Pin# Name Description

J17-12A GND_D Digital ground J17-12B GND_D Digital ground

J17-13A GND_D Digital ground J17-13B GND_D Digital ground
J17-14A AC_RELAY Input relay control signal J17-14B AC_RELAY Input relay control signal
J17-15A GND_D Digital ground J17-15B GND_D Digital ground
J17-16A NOP J17-16B NOP
J17-17A NOP J17-17B NOP
J17-18A NOP J17-18B NOP
J17-19A NOP J17-19B NOP
J17-20A PFCPWM2 PWM output for PFC J17-20B PFCPWM2 PWM output for PFC
control control
J17-21A PFCPWM1 PWM output for PFC J17-21B PFCPWM1 PWM output for PFC
control control
J17-22A GND_D Digital ground J17-22B GND_D Digital ground
J17-23A INPUTVOL_FRQ Input voltage frequency J17-23B INPUTVOL_FRQ Input voltage frequency
J17-24A PONSIGNAL Input IO port, tests the J17-24B PONSIGNAL Input IO port, tests the
power-on signal power-on signal
J17-25A GND_D Digital ground J17-25B GND_D Digital ground
J17-26A NOP J17-26B NOP
J17-27A INPUTCUR_PRO FAULTA1, masks PWM J17-27B INPUTCUR_PRO FAULTA1, masks PWM
output if PFC input is output if PFC input is
overcurrent overcurrent
J17-28A GND_D Digital ground J17-28B GND_D Digital ground
J17-29A NOP J17-29B NOP
J17-30A GND_D Digital ground J17-30B GND_D Digital ground
J17-31A GND_D Digital ground J17-31B GND_D Digital ground
J17-32A +5V_DSP +5V digital power J17-32B +5V_DSP +5V digital power

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

1-8 Freescale Semiconductor
Preliminary
 System Design

Chapter 2
Hardware Design of a DC/DC Converter System

2.1 Requirements
This section contains information about the design of the DC/DC converter system. Specifications and
performance include:
Input voltage: 300~380V DC output by PFC
Output voltage: 48V, precision: 3%, ripple: 500mV
Rating output power: 500W
Switch frequency: 150K

2.2 System Design

A phase-shifted, full-bridge DC/DC converter combines the advantages of quasi-resonant technology
and traditional PWM technology. It has fixed frequency, utilizes Inductor Capacitance (LC) resonant
energy to realize the main switches’ ZVS, then utilizes PWM technology to transfer energy. Its
advantages include control, limited switching loss, and high reliability. In addition, this system adopts a
current doubler with a synchronous rectifier rather than a traditional full-wave rectifier, which adds
several advantages, such as limited duty loss, no reverse recovery and less difference required to
realize ZVS between two legs.

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-1
Preliminary
 Figure 2-1. DC/DC System Design

2.3 Main Circuit Hardware Design

The DC/DC system design is shown in Figure 2-2. The topology of the main circuit is a phase-shifted,
full-bridge converter, including four MOSFET (Q1—Q4), a transformer (Tr), capacitance (Cr) to prevent
saturation of the transformer, secondary synchronous rectifier (Q5 and Q6), filter inductors (Lf1 and Lf2)
and output filter capacitance (Cf). Three signals, inductance current (IL), output voltage (Vo), and output
current (Io), are sampled and sent to the 56F8323 device.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-2 Freescale Semiconductor
Preliminary
 Main Circuit Hardware Design

DC/DC output OUTP UTCUR

current sampling OUTP UTCUR
Sent to secondary
C6 5
DCBUS + controller’s board 1 .5 u
DCBUS + as ADC input signal

R6 7 5 7 k
S2 TE1 9
C6 7 OUTCUR
IRFP C6 0 5 6 0 p F/2 k V
S3

4
ME L
PWM A PWM B IRFP C6 0
PWM A PWM B
1 2
+ 1 2 V_ S -1 2 V_ S

Lf1
1 2 5 6
1 2 OUTP UT+
12u U1 1

2
P WM ARNT C7 3 S6 HDC-1 5 LX
Cr1 3 0 0 0 P /2 KV
0 .1 u F /2 7 5 VAC R6 8
J1 9 T5 1

SD
P WM ARNT PWM S1 G
57k TE2 0 J7
1 C6 9 IRFP 2 6 4
OUTPUTVOL
2 C7 0 1

3
2 u /4 5 0 V C7 1 R7 1
DCBUS 2 u /4 5 0 V C7 2 2 2 0 0 u F /1 0 0 V 1 .5 K(2 W)
OUTP UTVOL 2

3
OUTP UTVOL 3
R6 9 R7 0 R1 4 6
2 .2 u /6 5 VC7 4 2 .2 u /6 5 V
2 0 /3 2W0 /3 W 2K DC/DC output voltage FAN
C6 6
sampling

3
2
P WM BRNT TRANS F ORM ER1 5 S7 1 R7 2 1 .5 u
P WM BRNT G PWM S2 2K TE1 8 Sent to secondary

4
GNDS controller’s board as

D
S
ADC input signal

1
T6 IRF P2 6 4 Lf2

12

34
(5 0 0 :1 ) 1 2
1 2 OUTP UT-

2
S4 12u
C6 8
5 6 0 p F/2 k V 2

3
IRFP C6 0 S5 1 N4 1 4 8

1 N4 1 4 8 D2 9 P F C CONCTROLLER S AM PLE 2 -3
SD

PWM C 1 D
PWM D3 0
PWM C P WM D G 2 1 2 1
IRF PC6 0 KA KA
2 1 2 1
3

KA KA
DC/DC CONCTROLLER SAM PLE 1 -2
1 N4 1 4 8 D3 1 1 N4 1 4 8 D3 2
GNDP
GNDP

TE2 1 R7 35 0 0
INDCUR
TE2 2

R7 4 1 .6 K
C7 5 2 2 0 p F GNDS

J8
J9 GNDJUM P ER

1
2
OUTJUM PER
3

1
2

INDCUR_ P INDCUR_ S
INDCUR_ S

DC/DC induction DC/DC induction

current sampling current sampling
Sent to primary Sent to secondary
controller’s board as controller’s board as
ADC input signal ADC input signal

Figure 2-2. DC/DC Main Circuit

2.3.1 Main Switch

The voltage stress of the main switch is:

VCEM(S)>1.5Vcem(S)＝1.5Vin（max）＝1.5×380=570V Eqn. 2-1

The main switch’s current stress is calculated by RMS value:

Po (max) 500
I CEM ( S ) > 4 I cem ( s ) = 4 × = 4× = 7 .4 A
ηVin (min) 0.9 × 300
Eqn. 2-2
Select switch S1—S4 to be MOSFET IRFPC60LC.
Parameters are:
• VDSS = 600V
• ID = 16A
• RDS(on)tye = 0.4Ω
• TO-247 AC package

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-3
Preliminary
2.3.2 Transformer’s Turns Ratio
Taking into account the duty ratio loss of the secondary side, select the secondary side’s maximum duty
ratio to be 0.85. The secondary side’s minimum voltage can then be calculated as follows:

Vo (max) + VD + VLf 52 + 1.5 + 0.5

Vsec(min) = = = 67.5V
Dsec(max) 0 .8
Eqn. 2-3
Where:
Vo(max) is the maximum output voltage
VD is the output diode’s forward voltage
VLf is the output filter inductor’s voltage drop
The transformer’s turns ratio is:
300
n= = 4 .4
67.5
Select the transformer’s turns ration to be n = 4.

2.3.3 Resonance Inductor

In order that the zero voltage switch of the lag bridge be achieved, Equation 2-4 must be satisfied:

1 4
Lr I 2 = C DSVin2
2 3 Eqn. 2-4
Where:
Lr is the resonance inductor
I is the primary circuit current when the switch of the lag bridge is closed
CDS is the drain to source capacitance of MOSFET
The factors below should be considered when resonance indicator, Lr, is selected:
• In order that zero voltage switch is sure to properly handle Vin, Vin should be calculated by
Vin(max)
• The zero voltage switch occurs when the load is beyond 0.7 of full load
• When the load circuit is 1.04A (10% of full load circuit), the circuit of inductor Lf is in critical
current mode, so pulse current ∆iLf is 2.08A
When load is 0.7 of full load:

0.7 I o (max) + ∆iLf / 2 0.7 ×10.4 + 1.04

I= = = 2.08 A
n 4 Eqn. 2-5

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-4 Freescale Semiconductor
Preliminary
 Main Circuit Hardware Design

The drain to source capacitance of IRFBC30 is CDS = 360pF.

Vin(max) = 380V
According to Equation 2-4, Lr = 30µH.

2.3.4 Transformer

2.3.4.1 Number of Turns

If magnetic core is selected to be EI40 and the maximum magnetic flux density is determined to be
Bm = 0.10T, then the turns of the secondary side Wsec can be calculated as follows:

Vsec(min) • Dsec(max)
Wsec =
4 f s Ae Bm
Eqn. 2-6
Where:
The effective area of magnetic core is Ae = 138mm2
Dsec(max) = 1 - 0.15 = 0.85
Vin (min) 300
Vsec(min) = = ＝75V
n 4
According to Equation 2-5, Wsec = 6.2
If the secondary side’s number of turns is selected to be Wsec = 6, the primary side’s number of turns is
Wp = 24.

2.3.4.2 Lead Diameter and the Primary Winding’s Number of Leads

When transformer’s PWM frequency is 150kHz, the penetration depth of the copper lead is:

2 1
Λ= = = 0.171mm
2πf s µγ 3.14 × 150 × 10 × 1.25 × 10 −6 × 58 × 10 6
3
Eqn. 2-7
Where:
γ is the electric conductive ratio of lead
µ is the magnetic conductive ratio of lead
A copper lead with a diameter smaller than 0.34mm can be selected. In this case, high-intensity lead
with a 0.33mm diameter is selected; the effective area is 0.0855mm2.
The primary winding’s maximum circuit is:

Po (max)
I p (max) =
η trVin (min)
Eqn. 2-8

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-5
Preliminary
If the transformer’s maximum output power is Po(maximal) = 500W, suppose that the efficiency of the
transformer is ntr = 0.98. According to Equation 2-8, Ip(max) = 2.04A; select circuit density to be
J = 3.5A/mm2 and the primary side’s area of leads is:
2.04
Sp = = 0.583mm 2
3.5
Seven leads with a 0.33mm diameter must be used.

2.3.4.3 The Secondary Winding’s Number of Leads

There are two secondary windings which compose a double half-wave commutator, so the maximum
RMS current of the secondary side is:

Is（max） = 10.4 = 7.35A

2
If the circuit density is selected to be J = 3.5A/mm2, the secondary side’s effective area of leads is:
7.35
SS = = 2.1mm 2
3.5
Twenty-five leads with a 0.33mm diameter must be used.

2.3.4.4 Check the Window’s Filling Factor

The window area of EI40 is Sc = 155.4mm2, so the window’s filling factor is:

24 × 7 × 0.0855 + 2 × 6 × 25 × 0.0855
Kc = = 0.26
155.4 Eqn. 2-9

2.3.5 Resonance Inductor Design

As shown in Section 2.3.3, Lr = 30µH.
The maximum current of Lr is:

1 1
I o (max) + ∆I max 10.4 + × 2.08
I Lr (max) = 2 = 2 = 2.86 A
n 4 Eqn. 2-10
2
Select the magnetic core to be EE25, with an effective area of 42.2mm .
Select the gap length to be δ = 1.2mm.
The value of the resonance inductor winding can be calculated as follows:

L ⋅δ
N= = 26.06
µ ⋅ Ae
Eqn. 2-11
Select N = 26.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-6 Freescale Semiconductor
Preliminary
 Main Circuit Hardware Design

Check the maximum magnetic flux density:

µN Im ax 2
Bm = = 0.096T < 0.2T
δ Eqn. 2-12
Since the circuit of the resonance inductor is equivalent to the circuit of the transformer’s primary side,
the diameter of the lead and the number of windings can be selected to be the same as the transformer’s
primary side. According to Section 2.3.4, seven leads with a 0.33mm diameter can be used. Finally,
check the window’s fulfilling ratio as follows:

26 × 7 × 0.0855
Kc = = 0.19 <<0.35
81.94 Eqn. 2-13

2.3.6 Output Filter Inductor Design

The output filter inductor can be calculated by the following formula:

Vo (min) Vo (min)
Lf = [1 − ]
2 × (2 f s ) • (10% I o (max) ) Vin (max)
− VLf − VD
n Eqn. 2-14
Where:
Vo(min) = 35V
Io(max) = 10.4A
Vin(max) = 380V
N=4
VLf = 0.5V
VD = 1.5V
According to Equation 2-14, Lf = 35µH.
The maximum circuit of Lf is:

1 1
I Lf (max) = I o (max) + ∆I max = 10.4 + × 2.08 = 11.44 A
2 2 Eqn. 2-15
Select magnetic core to be Ei30.
Select the maximum magnetic flux density Bm = 0.40T.
The turns of the output filter inductor can be calculated as follows:

Lr I Lr (max) 35 × 11.44
N= = = 9 .5
Ae Bm 111 × 0.4
Eqn. 2-16

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-7
Preliminary
If N = 10, the gap is:

µ o N 2 Ae 1.25 ×10 −6 × 10 2 × 111×10 −6

δ= = = 0.3mm
Lr 35 ×10 −6
Eqn. 2-17
The maximum RMS circuit of the output filter inductor is 10.4A.
Select the circuit density to be J = 3.5A/mm2, and the winding’s area of leads is:
10.4
S Lf = = 2.97mm 2
3.5
Thirty-five leads with a 0.33mm diameter must be used.
The effective area of EI30 is Sc = 132mm2.
Finally, check the window’s fulfilling ratio as follows:

13 × 35 × 0.0855
Kc = = 0.295 <0.35
132 Eqn. 2-18

2.3.7 Output Filter Capacitor

One 2200µF/100V output filter capacitor is used.

2.3.8 Output Diode

The output diode’s voltage limit is:

Vcem ( DR ) = 2Vin (max) / n = 2 × 380 / 4 = 190V

Eqn. 2-19
The diode’s maximum circuit is:

1 1
IDR（max）＝Io（max）+ ΔILf=10.4+ ×1.04=10.9A
2 2 Eqn. 2-20
An ultrafast recovery diode, 60CTQ150, produced by IR Corporation, has been selected for this
application.
Parameters are:
• IF(AV) = 60A
• VRRM = 400V
• Vfm = 0.93V

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-8 Freescale Semiconductor
Preliminary
 Sample Circuit Hardware Design

2.4 Sample Circuit Hardware Design

The output voltage sample circuit is composed of a simple voltage divider and a voltage follower circuit,
shown in Figure 2-3.

Vo

57K

3K

Figure 2-3. Output Voltage Sample Circuit

As the resonance inductance current iL is an AC quantity, one current transformer can be used for the
inductance current sample. The inductance current sample circuit is shown in Figure 2-4. Ds1~Ds4
compose a full-bridge rectifier. Rs1 is a sample resistor. Rs2 is used for current limiting.

iL Rs2
Ds1 Ds2

TiL Rs1 Cs2

Ds3 Ds4

Figure 2-4. Inductance Current Sample Circuit

The output current can be sensed by a current LEM HDC-15LX.

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-9
Preliminary
2.5 Drive Circuit Hardware Design
A simple and reliable isolated gate drive circuit is used for each MOSFET, shown in Figure 2-5. Only
one +12V DC power supply is needed for the four driver circuits.

+12VDRV_S C51
220uF/25V
TE12

+
C47 PWMA
0.1uF D17
BYV26C
Q6
PWMA
2SD882 R49
51/0.5W
C55 D21
1uF R50 1N4744
PWMA_IN 51/0.5W

R63
Q10 3.6k
2SB772
T1
TE13 D22
TRANS3
PWMARNT 1N4744

PWMARNT

Figure 2-5. Output Voltage Driver Circuit

2.6 Optocoupler Isolation Drive Circuit Hardware Design

Transformer isolation is a convenient solution for the 50% duty signal output. When the duty signal
varies, optocoupler isolation is a suitable solution. The HCPL2611 optocoupler is used for isolation and
the TC4420 is a special driver IC for MOSFET.

+20V_3

D39

500 5V
R78
1K U15 +20V_3 R82
R86 1 8 10
D40 C82 VDD VDD C83 C87 J13
0.47uF
0.1uF 2 7 R90 1
DIP4 INPUT OUTPUT 0.1uF 2
5.1K 3 6 4.7k 3
R94 5V NC OUTPUT
+3.3VAS R98
CON3
300 4 5
PWM2_A GND GND
GND_3 TC4420 GND_3
PWM2_A
2611
GND 3

Figure 2-6. Output Voltage Driver Circuit

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-10 Freescale Semiconductor
Preliminary
 Controller Interface

2.7 Controller Interface

All DC/DC conversion is controlled by one chip, the 56F8323, which provides a full digital solution for
high-frequency DC/DC conversion. The interface between the PFC power system and the controller is
shown in Table 2-1.

Table 2-1. Interface Description with the Controller

(Connected to J1 of Controller)
Pin # Name Description Pin# Name Description

J16-1A GND_A Analog ground J16-1B GND_A Analog ground

J16-2A OUTPUT_CUR ADC channel #6, DC/DC J16-2B OUTPUT_VOL ADC channel #5, DC/DC
output current sample output voltage sample
J16-3A J16-3B IND_CUR ADC channel #2, DC/DC
induction current sample
J16-4A J16-4B
J16-5A GND_A Analog ground J16-5B GND_A Analog ground
J16-6A GND_A Analog ground J16-6B GND_A Analog ground
J16-7A +3.3VA +3.3V analog power J16-7B +3.3VA +3.3V analog power
J16-8A GND_A Analog ground J16-8B GND_A Analog ground
J16-9A GND_A Analog ground J16-9B GND_A Analog ground
J16-10A RXD1 SCI1 receive data input J16-10B RXD1 SCI1 receive data input
J16-11A TXD1 SCI1 transmit data output J16-11B TXD1 SCI1 transmit data output
J16-12A GND_D Digital ground J16-12B GND_D Digital ground
J16-13A GND_D Digital ground J16-13B GND_D Digital ground
J16-14A J16-14B
J16-15A GND_D Digital ground J16-15B GND_D Digital ground
J16-16A PWM4_S PWM output for DC/DC J16-16B PWM4_S PWM output for DC/DC
control control
J16-17A PWM3_S PWM output for DC/DC J16-17B PWM3_S PWM output for DC/DC
control control
J16-18A PWM2_S PWM output for DC/DC J16-18B PWM2_S PWM output for DC/DC
control control
J16-19A PWM1_S PWM output for DC/DC J16-19B PWM1_S PWM output for DC/DC
control control
J16-20A PWM6_S PWM output for J16-20B
synchronized control
J16-21A PWM5_S PWM output for J16-21B
synchronized control
J16-22A GND_D Digital ground J16-22B GND_D Digital ground

Hardware Design of a DC/DC Converter System, Rev. 0

Freescale Semiconductor 2-11
Preliminary
 Table 2-1. Interface Description with the Controller (Continued)
(Connected to J1 of Controller)
Pin # Name Description Pin# Name Description

J16-23A J16-23B
J16-24A J16-24B
J16-25A GND_D Digital ground J16-25B GND_D Digital ground
J16-26A INDCUR_PRO FAULTA2, masks PWM J16-26B INDCUR_PRO FAULTA2, masks PWM
output if DC/DC output if DC/DC
inductance is overcurrent inductance is overcurrent
J16-27A J16-27B
J16-28A GND_D Digital ground J16-28B GND_D Digital ground
J16-29A J16-29B
J16-30A GND_D Digital ground J16-30B GND_D Digital ground
J16-31A GND_D Digital ground J16-31B GND_D Digital ground
J16-32A +5V_DSP +5V digital power J16-32B +5V_DSP +5V digital power

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

2-12 Freescale Semiconductor
Preliminary
 Control System Circuit

Chapter 3
Controller Board Hardware Architecture

3.1 Introduction
The system consists of two parts: a Power Factor Correction (PFC) circuit and a DC/DC conversion
circuit. The controller’s boards used to control these two subsystems are the same. This section details
the hardware design of the controller’s board.
The controller board comprises these components:
• Control system circuit
• CPU circuit
• ADC circuit
• Power supply circuit
• DAC circuit
• LED display circuit
• Signals output interface

3.2 Control System Circuit

The system circuit shows the connection between key components and the pin-out arrangement.

Output Signal Interface

SIGNAL OUT .Sch
PFCPWM 1
PWM A0 PFCPWM 1
PWM A1 PFCPWM 2 PFCPWM 2
Analog Signal For ADC Filters 56F8323 Proces s or M ain Circuit PWM A2 PWM 1 PWM 1
ADCIN.SCH PROCE SSOR.Sch PWM 2
PWM A3 PWM 2
INPUT _VOL PWM 3
INPUT _CUR INPUT _VOL ANA0 ANA0 PWM A0 PWM A4 PWM 3 PWM 4
DCBUS INPUT _CUR ANA1 ANA1 PWM A1 Z VSPWM A1 PWM A5 PWM 4 Z VSPWM 1
DCBUS ANA2 ANA2 PWM A2 Z VSPWM A1 Z VSPWM 1
IND_CUR Z VSPWM A2 Z VSPWM 2
IND_CUR ANA4 ANA4 PWM A3 Z VSPWM A2 Z VSPWM 2
OUT PUT _VOL
OUT PUT _CUR OUT PUT _VOL ANA5 ANA5 PWM A4
OUT PUT _CUR ANA6 ANA6 PWM A5
+3.3VA Z VSPWM A1
+3.3VA Z VSPWM A2
GND_A GND_A
PONSIGNAL LED L E D.SCH
GND_D PONSIGNAL
RE L AY RE L AY
J2 T DOD T DOD L E DDAT A L E DDAT A AC_RE L AY AC_RE L AY
T DID 1 2 T M SD T M SD L E DCL K L E DCL K
T DOD 3 4 T CKD T CKD /L E DE N /L E DE N
T CKD T DID
5 6 /J _T RST D T DID INPUT CUR_PRO
/J _RE SE T D 7 8 T M SD /J _RE SE T D /J _T RST D INPUT CUR_PRO INDCUR_PRO
9 10 /J _RE SE T D INDCUR_PRO
+3.3V_DSP
R30 11 12 +5V_DSP J6
/J _T RST D RXD0
+3.3V_DSP 13 14 T XD0 RXD0 +3.3V_DSP 1 2 +3.3V_DSP
47K T XD0
J T AG INPUT VOL _FRQ GND_D 3 4 GND_D
INPUT VOL _FRQ DACCL K 5 6 DACDAT A
R1 R2 /DACE N /RE SE T D
J3 7 8
5.6K 5.6K
+3.3V_DSP 1 2 +5V_DSP DA-T AG
GND_D 3 4 GND_D
T XD0 T XD0 IRQA
5 6 IRQA
RXD0 7 8 RXD0 J4
GPIOC2 GPIOC2 1 I2C PORT
SCI T AG GND_D GND_D GPIOC3 GPIOC3 2
+3.3VA
+3.3VA
POWE R CIRCUIT T XD1
POWE R.Sch GND_A GND_A T XD1 RXD1
RXD1
+5V_DSP +3.3V_DSP
+5V_DSP +3.3V_DSP +3.3V_DSP
+3.3V_PL L DA
GND_D +3.3V_PL L +3.3V_PL L DA.Sch
/RE SE T D
GND_D /RE SE T D DACDAT A /RE SE T D
DACDAT A DACDAT A
DACCL K DACCL K DACCL K
/DACE N
/DACE N /DACE N
+3.3VA
+3.3VA
GND_A GND_A
+3.3V_DSP +3.3V_DSP
GND_D GND_D

Figure 3-1. Connection Between Subsystems

Controller Board Hardware Architecture, Rev. 0

Freescale Semiconductor 3-1
Preliminary
 Table 3-1. Controller Board Pin-Out Description
(Connected to J16 and J17 of the Power Board)
Pin # Name Description Pin# Name Description

J1-1A GND_A Analog ground J1-1B GND_A Analog ground

J1-2A OUTPUT_CUR ADC channel #6, DC/DC J1-2B OUTPUT_VOL ADC channel #5, DC/DC
output current sample output voltage sample
J1-3A DCBUS ADC channel #4, PFC J1-3B IND_CUR ADC channel #2, DC/DC
output voltage sample induction current sample
J1-4A INPUT_VOL ADC channel #0, PFC J1-4B INPUT_CUR ADC channel #1, PFC
input voltage sample input current sample
J1-5A GND_A Analog ground J1-5B GND_A Analog ground
J1-6A GND_A Analog ground J1-6B GND_A Analog ground
J1-7A +3.3VA +3.3V analog power J1-7B +3.3VA +3.3V analog power
J1-8A GND_A Analog ground J1-8B GND_A Analog ground
J1-9A GND_A Analog ground J1-9B GND_A Analog ground
J1-10A RXD1 SCI1 receive data input J1-10B RXD1 SCI1 receive data input
J1-11A TXD1 SCI1 transmit data output J1-11B TXD1 SCI1 transmit data output
J1-12A GND_D Digital ground J1-12B GND_D Digital ground
J1-13A GND_D Digital ground J1-13B GND_D Digital ground
J1-14A AC_RELAY Input relay control signal J1-14B AC_RELAY Input relay control signal
J1-15A GND_D Digital ground J1-15B GND_D Digital ground
J1-16A PWM4 PWM output for DC/DC J1-16B PWM4 PWM output for DC/DC
control control
J1-17A PWM3 PWM output for DC/DC J1-17B PWM3 PWM output for DC/DC
control control
J1-18A PWM2 PWM output for DC/DC J1-18B PWM2 PWM output for DC/DC
control control
J1-19A PWM1 PWM output for DC/DC J1-19B PWM1 PWM output for DC/DC
control control
J1-20A PFCPWM2 PWM output for PFC J1-20B ZVSPWM2 PWM output for
control synchronized control
J1-21A PFCPWM1 PWM output for PFC J1-21B ZVSPWM1 PWM output for
control synchronized control
J1-22A GND_D Digital ground J1-22B GND_D Digital ground
J1-23A INPUTVOL_FRQ Input voltage frequency J1-23B INPUTVOL_FRQ Input voltage frequency
J1-24A PONSIGNAL Input IO port, tests the J1-24B PONSIGNAL Input IO port, tests the
power-on signal power-on signal
J1-25A GND_D Digital ground J1-25B GND_D Digital ground

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

3-2 Freescale Semiconductor
Preliminary
 Control System Circuit

Table 3-1. Controller Board Pin-Out Description (Continued)

(Connected to J16 and J17 of the Power Board)
Pin # Name Description Pin# Name Description

J1-26A INDCUR_PRO FAULTA2, masks PWM J1-26B INDCUR_PRO FAULTA2, masks PWM
output if DC/DC output if DC/DC
inductance is overcurrent inductance is overcurrent
J1-27A INPUTCUR_PRO FAULTA1, masks PWM J1-27B INPUTCUR_PRO FAULTA1, masks PWM
output if PFC input is output if PFC input is
overcurrent overcurrent
J1-28A GND_D Digital ground J1-28B GND_D Digital ground
J1-29A IRQA External interrupt request J1-29B IRQA External interrupt request
A A
J1-30A GND_D Digital ground J1-30B GND_D Digital ground
J1-31A GND_D Digital ground J1-31B GND_D Digital ground
J1-32A +5V_DSP +5V digital power J1-32B +5V_DSP +5V digital power

Table 3-2. JTAG Interface Pin-Out Description

(Connected to J204 of the Communication Board)
Pin # Name Description Pin# Name Description

J2-1 TDID Test Data Input J2-2 GND_D Digital ground

J2-3 TDOD Test Data Output J2-4 GND_D Digital ground
J2-5 TCKD Test Clock Input J2-6 GND_D Digital ground
J2-7 NOP J2-8 NOP
J2-9 /J_RESETD Reset J2-10 TMSD Test Mode Select Input
J2-11 +3.3V_DSP +3.3V digital power J2-12 +5V_DSP +5V digital power
J2-13 PULLUP +3.3V Pull-up pin J2-14 /J_TRSTD Test Reset

Table 3-3. SCI Interface Pin-Out Description

(Connected to J201 of the Communication Board)
Pin # Name Description Pin# Name Description

J3-1 +3.3V_DSP +3.3V digital power J3-2 +5V_DSP +5V digital power
J3-3 GND_D Digital ground J3-4 GND_D Digital ground
J3-5 TXD0 SCI0 transmit data output J3-6 TXD0 SCI0 transmit data output
J3-7 RXD0 SCI0 receive data output J3-8 RXD0 SCI0 receive data output

Controller Board Hardware Architecture, Rev. 0

Freescale Semiconductor 3-3
Preliminary
 Table 3-4. DAC Debug Interface Pin-Out Description
( Debug purpose only)
Pin # Name Description Pin# Name Description

J3-1 +3.3V_DSP +3.3V digital power J3-2 +5V_DSP +5V digital power
J3-3 GND_D Digital ground J3-4 GND_D Digital ground
J3-5 DACCLK DAC clock signal J3-6 DACDATA DAC data signal
J3-7 /DACEN DAC enable signal J3-8 /RESETD DAC reset signal

3.3 CPU Circuit

This circuit shows the signal connections around the controller.
PWMA0 and PWMA1 are used for PFC control; PWMA2, PWMA3, PWMA4 and PWMA5 are used for
DC/DC control. FAULTA1 and FAULTA2 are used for hardware protection. If the current through PFC
input inductance is too large, FAULTA1 will be high, which indicates than an overcurrent fault has
occurred, and the PWM outputs will be masked. If the current through DC/DC primary side inductance is
too large, FAULTA2 will be high and the PWM outputs will be masked.
ANA0, ANA1, ANA2, ANA4, ANA5 and ANA6 are used to sample analog signals. ANA7 is used for ADC
test.

+3.3VA GND_A
R4 R5 R6
10K 10K 10K ANA0 26 3 PWMA0 +3.3V_DSP
ANA0 ANA0 PWMA0/GPIOA0 PWMA0
ANA1 27 4 PWMA1
ANA1 ANA1 PWMA1/GPIOA1 PWMA1
ANA2 28 7 PWMA2
ANA2 ANA2 PWMA2/GPIOA2/SS1 PWMA2
GND_A 29 8 PWMA3
ANA3 PWMA3/GPIOA3/MISO1 PWMA3 D3 D21
ANA4 30 9 PWMA4
ANA4 ANA4 PWMA4/MOSI1/GPIOA4 PWMA4 1N4148 1N4148
ANA5 31 10 PWMA5
ANA5 ANA5 PWMA5/SCLK1/GPIOA5 PWMA5
ANA6 32
ANA6 ANA6
ANA7 33 13
ANA7 FAULTA0/GPIOA6
14 INPUTCUR_PRO
FAULTA1/GPIOA7 INPUTCUR_PRO
J5 +3.3VA 40 15 INDCUR_PRO
1
2
3
4
5
6
7
8

VREFH FAULTA2/GPIOA8 INDCUR_PRO

37 10K
C20 VREFP R7
AD SET 36 16 /LEDEN
C21 VREFMID ISA0/GPIOA9 /LEDEN
35 18 LEDCLK 10K
0.1uF C24 VREFN ISA1/GPIOA10 LEDCLK R8
38 19LEDDATA
0.1uF VREFLO ISA2/GPIOA11 LEDDATA
0.1uF +3.3VA 41 52 ZVSPWMA1 R11 10K
100pF 0.001uF 0.1uF VDDA_ADC TA0/GPIOB7/PA0 ZVSPWMA1
+3.3V_PLL 42 51 DACDATA GND_D
VDDA_OSC_PLL TA1/GPIOB6/PB0 DACDATA
6 50 DACCLK D6
C26 C27 C28 VDD_IO TA2/GPIOB5/INDEX0 DACCLK R10 RED LED
GND_A 20 49 INTPUTVOL_FRQ
+3.3V_DSP VDD_IO TA3/GPIOB4/HOME0 INPUTVOL_FRQ
48 25 FAULTDIS1 300
+3.3V_DSP VDD_IO SCLK0/GPIOB3
59 24 /DACEN D5
VDD_IO MOSI0/GPIOB2 /DACEN R9 RED LED
GND_A 22 RXD1
RXD1/MISO0/GPIOB1 RXD1
39 21 TXD1 300
GND_A VSSA_ADC TXD1/SS0/GPIOB0 TXD1
11 64 RXD0 +3.3V_DSP
VSS RXD0/TC1/GPIOC5 RXD0
17 1 TXD0
GND_D VSS TXD0/TC0/GPIOC6 TXD0
44 61 GPIOC2
VSS CAN_RX/GPIOC2 GPIOC2
60 62 GPIOC3
VSS CAN_TX/GPIOC3 GPIOC3
VCAP1 57
VCAP1
VCAP2 23 46 RELAY
C22 VCAP2 EXTAL/GPIOC0 RELAY
VCAP3 5 47 PONSIGNAL
2.2uF C23 VCAP3 XTAL/GPIOC1 PONSIGNAL
VCAP4 43 55 TDID
2.2uF C25 VCAP4 TDI TDID
OCR_DIS 45 56 TDOD D4
2.2uF C29 OCR_DIS TDO TDOD
53 TCKD INTPUTVOL_FRQ
2.2uF TCK TCKD +3.3V_DSP
ZVSPWMA263 54 TMSD D22
ZVSPWMA2 TC3/GPIOC4 TMS TMSD
IRQA 12 58 /TRSTD 1N4148
IRQA IRQA TRST +3.3V_DSP
34 2 /RESETD
TEMP_SENSE RESET /RESETD
GND_D +3.3V_DSP 1N4148
R12 U3 F8323
47K

C5 C6 C7 C8
0.1uF 0.1uF 0.1uF 0.1uF

GND_D
GND_D

Figure 3-2. CPU Circuit

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

3-4 Freescale Semiconductor
Preliminary
 CPU Circuit

Table 3-5 shows the resources of General Purpose Inputs/Outputs (GPIOs).

Table 3-5. GPIO Resources

PIN# Name Description

GPIOC0 RELAY Relay on control signal; if high, the relay is closed

GPIOB6 DACDATA
GPIOB5 DACCLK DAC control signals
GPIOB2 /DACEN
GPIOA11 LEDDATA
GPIOA10 LEDCLK LED control signals
GPIOA9 /LEDEN
GPIOB2 FAULTDIS3
GPIOB3 FAULTDIS2 Fault display
GPIOB4 FAULTDIS1
GPIOC2 GPIOC2
I2C reserved ports
GPIOC3 GPIOC3
GPIOC1 PONSIGNAL Tests the power-on signal

Figure 3-3 shows the reset circuit. If S1 is pressed, /RESETD and /TRSTD become low, resetting both
the device and the JTAG.

Figure 3-3. Reset Circuit

Controller Board Hardware Architecture, Rev. 0

Freescale Semiconductor 3-5
Preliminary
3.4 ADC Circuit
The ADC circuit filters the analog signals for sampling. There are six analog signals: three for PFC
control and three for DC/DC control.

Table 3-6. ADC Resource Configuration

PIN# Name Description

ANA0 INPUT_VOL Input voltage sample

ANA1 INPUT_CUR Input current sample
ANA2 IND_CUR DC/DC inductance current sample
ANA3 GND_A GND
ANA4 DCBUS DCBus sample
ANA5 OUTPUT_VOL Output voltage sample
ANA6 OUTPUT_CUR Output current sample
ANA7 CONFIG Reserved for software configuration

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

3-6 Freescale Semiconductor
Preliminary
 ADC Circuit

Figure 3-4. ADC Input Circuit

Controller Board Hardware Architecture, Rev. 0

Freescale Semiconductor 3-7
Preliminary
3.5 Power Supply Circuit
The power supply circuit changes +5V DC to +3.3V regulated DC power, used to power the device.

POWER GOOD LED

D1 D2
R3
TE2
+5V_DSP 300 +3.3V
FM4001
GND_D GREEN LED U1
+5V_DSP 4 2
D20 VIN VOUT +3.3V_DSP
L1 5 3 +3.3V_DSP
1N4733 NC VOUT L2 L3
8 6 +3.3V_PLL
C9 + NC VOUT +3.3V_PLL
C10 C11 C12 C13 C14 1 7
GND VOUT
47uF/10V TE1
MC33629DT-3.3 GND_D + C16 C17 +
GND_D C15 C19
GND_D C16&C17 C18
C10-C14 0.1uF 47uF/10V 0.1uF
0.1uF 47uF/10V

GND_D GND_D

Figure 3-5. Power Supply Circuit

3.6 DAC Circuit

The DAC circuit has no control function and is used only to debug the system.

Figure 3-6. DAC Circuit

3.7 LED Display Circuit

This circuit displays the system parameters, such as input voltage, input current, output voltage, output
current, and so on.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

3-8 Freescale Semiconductor
Preliminary
 Signals Output Interface

12

6
11 DIG.1 DIG.2 DIG.3 DIG.4
a
7 a a a a
b
4
c f g b f
g
b f
g
b f
g
b
2
d
1
e e c e c e c e c
+5V_DSP U8 10 d d d d
f
19 2 5 dp dp dp dp
V+ DIG0 g
U7 11 3
2 18 R29 10K 18
DIG1
6
dp
1A1 1Y1 ISET DIG2 U9
4 16 7
1A2 1Y2 DIG3 FYQ-3641A
6 14 1 3
1A3 1Y3 DIN DIG4
8 12 10
1A4 1Y4 DIG5
24 5
DOUT DIG6
11 9 8
2A1 2Y1 DIG7
LEDDATA 13 7 LEDDATA1
/LEDEN 2A2 2Y2
LEDCLK 15 5 LEDCLK1 13 14
LEDCLK 2A3 2Y3 CLK SEGA
/LEDEN 17 3 /LEDEN1 16
LEDDATA 2A4 2Y4 SEGB
20
SEGC
1 12 23
1G CS SEGD

12
19 21

6
2G SEGE
15
SEGF
MC74HC244 9 17 11 DIG.1 DIG.2 DIG.3 DIG.4
GND SEGG a
GND_D 4 22 7 a a a a
GND SEGDP b
4
c f g b f
g
b f
g
b f
g
b
GND_D MAX7221 2
d
1
e e c e c e c e c
10 d d d d
f
5 dp dp dp dp
g
3
dp

Figure 3-7. LED Display Circuit

3.8 Signals Output Interface

This interface changes the +3.3V level voltage to the +5V level.

Table 3-7. PWM Resources Configuration

Pin # PFC Part Descriptions DC/DC Part Descriptions

PWM0 PFCPWM1 PWM5 Synchronous driver

PFC driver signals
PWM1 PFCPWM2 PWM6 signals

PWM2 PWM1
PWM3 PWM2 Full bridge of DC/DC
PWM4 PWM3 converter driver signals

PWM5 PWM4
TA0 ZVSPWM1 ZVS assistant driver
TC3 ZVSPWM2 signals

Controller Board Hardware Architecture, Rev. 0

Freescale Semiconductor 3-9
Preliminary
 TE3 TE4 TE5 TE6 TE7 TE8
PFCPWM1 PFCPWM2 PWM1 PWM2 PWM3 PWM4
+5V_DSP

20
U4
PWMA0 2 18 PFCPWM1
PWMA0 1A1 1Y1 PFCPWM1
PWMA1 4 16 PFCPWM2
PWMA1 1A2 1Y2 PFCPWM2
ZVSPWMA1 6 14 ZVSPWM1
ZVSPWMA1 1A3 1Y3 ZVSPWM1

VCC
ZVSPWMA2 8 12 ZVSPWM2
ZVSPWMA2 1A4 1Y4 ZVSPWM2
PWMA2 11 9 PWM1
PWMA2 2A1 2Y1 PWM1
PWMA3 13 7 PWM2
PWMA3 2A2 2Y2 PWM2
PWMA4 15 5 PWM3
PWMA4 2A3 2Y3 PWM3
PWMA5 17 3 PWM4
PWMA5 2A4 2Y4 PWM4
1
1G
19
2G
GND

MC74HC244 RP1
GND_D TE21 PWMA5 8
TE22 ZVSPWM1 PWMA4 7
10

ZVSPWM2 PWMA3 6
GND_D PWMA2 5
PWMA1 4
PWMA0 3
+3.3V_DSP ZVSPWMA1 2
ZVSPWMA2 1 9

PWMA0 1 2 R15 GREEN LED GND_D

D7 8X5K
300
U5A MC74HC04

PWMA1 3 4 R16 GREEN LED

D8
300 +5V_DSP +3.3V_DSP
U5B MC74HC04

PWMA2 5 6 R17 GREEN LED C4 C39

D9
300 0.1uF 0.1uF
U5C MC74HC04

GND_D GND_D
PWMA3 9 8 R18 GREEN LED
D10 MC74HC244(U5) MC74HC04(U4)
300
U5D MC74HC04

PWMA4 13 12 R19 GREEN LED

D11
300
U5F
MC74HC04

PWMA5 11 10 R20 GREEN LED

D12
300
U5E MC74HC04

GND_D

Figure 3-8. Signals Output Interface

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

3-10 Freescale Semiconductor
Preliminary
 Introduction

Chapter 4
Communication Interface Board Hardware Architecture

4.1 Introduction
The communication interface board decreases the controller’s size and creates a universal-purpose
communication platform. This board provides mixed communication functions, such as JTAG debug and
SCI interface, between the power module and the PC. At the same time it provides isolation between the
power electronics and microelectronics which is needed to insure safety.
The communication system consists of two parts: the JTAG circuit and SCI. JTAG is designed for
debugging and programming the device. SCI is designed for background communication to software
running on the PC or for power management and supervision from an external system.

Figure 4-1. Communication Board Frame

Table 4-1. JTAG Interface Pin-Out Description

(Connected to the Controller’s J2)
Pin # Name Description Pin# Name Description

J204-1 TDID1 Test Data Input J204-2 GND_D Digital ground

J204-3 TDOD1 Test Data Output J204-4 GND_D Digital ground
J204-5 TCKD1 Test Clock Input J204-6 GND_D Digital ground
J204-7 NOP J204-8 NOP
J204-9 /J_RESETD1 Reset J204-10 TMSD1 Test Mode Select Input
J204-11 +3.3V_DSP +3.3V digital power J204-12 +5V_DSP +5V digital power
J204-13 PULLUP +3.3V Pull-up pin J204-14 /J_TRSTD1 Test Reset

Communication Interface Board Hardware Architecture, Rev. 0

Freescale Semiconductor 4-1
Preliminary
 Table 4-2. SCI Interface Pin-Out Description
(Connected to the Controller’s J3)
Pin # Name Description Pin# Name Description

J3-1 +3.3V_DSP +3.3V digital power J3-2 +5V_DSP +5V digital power
J3-3 GND_D Digital ground J3-4 GND_D Digital ground
J3-5 TXD11 SCI0 transmit data output J3-6 TXD11 SCI0 transmit data output
J3-7 RXD11 SCI0 receive data output J3-8 RXD11 SCI0 receive data output

4.2 Parallel JTAG Interface

Because the 56F800E core integrates the JTAG/EOnCE function, the device can be debugged and
programmed by a simple interface circuit through the parallel port without any special emulator. All
communications signals between the device and the PC are isolated by optocouplers-HCPL 2611 for
safety.

DSC SIDE PC SIDE

+5V_PC1
+5V_SCI1
+3.3V_D1 +5V_PC1

R202 R203 R208 R204

9

5.1K 47K 1K 47K

1
2
3
4
5
6
7
8

RP200
8X300 RP201
8X300

Q200
R209
1
2
3
4
5
6
7
8

1K
16
15
14
13
12
11
10

U203 2N2222A
8 2 R205
7 47K
3 /J_RESETP1
/J_RESETD1 6
GND_PC1
5
HCPL-2611
U204 GND_PC1
8 2
7
TMSD1 6 3 TMSP1 J203
1
5 14
PORT_RESETP1 2
HCPL-2611 15
U205
8 2 3
7 16
3 TCKP1 4
TCKD1 6
17
5
5
18
HCPL-2611 6
U206 19
8 2
7
7
20
3 TDIP1
TDID1 6 8
21
5 9
+5V_PC1
22
HCPL-2611 10
U207
8 2 23
7 11
3 /J_TRSTP1 24
/J_TRSTD1 6
PORT_PUP1 12
25
5 R206 PORT_CONNECTP1 13
HCPL-2611 47K
U208 DB25
2 8
7
GND_PC1
TDOD1 3
6 TDOP1

5
HCPL-2611
U209
RXD11 4 1
C A
3 2 TXDP11
E K
NEC2501
U210
1 4 RXDP11
A C
TXD11 2 3
C209 K E C210
NEC2501

0.1uF 0.1uF
GND_PC1
GND_D1

Figure 4-2. Parallel JTAG Interface

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

4-2 Freescale Semiconductor
Preliminary
 SCI Interface

4.3 SCI Interface

This circuit is the serial communication interface between the device and the PC. A charge pump voltage
converter, TC7660, generates +5V power from the PC, which is the power supply for the MAX202CSE,
the RS-232 communication protocol transformer’s special IC.

+5V_SCI1
C200 U200 C201
0.1uF 2 1 0.1uF
V+ C1+
C202 6 3 +5V_SCI1
V- C1-
0.1uF 16 4 0.1uF C203
VCC C2+
15 5
GND C2-
GND_PC1 RXD_PC1 14 11 RXDP11 C211
T1O T1I 0.1uF
7 10
T2O T2I
TXD_PC1 13 12 TXDP11
R1I R1O
8 9
R2I R2O
GND_PC1
+5V_SCI1 MAX202CSE MAX5251(U6)

+5V_SCI1

+ C206 D200
2

J202 D201 D202 D203 10uF/10V 1N4733

1 BAV99 BAV99 BAV99
6 3 3 3
2
7 D204
3 + C207 GND_PC1 BAV99
8 10uF/10V 1 8 1 2
NC V+
1

4
9 2 7
CAP+ OSC

3
5
3 6
GND LV
DB9 GND_PC1 + C208
4 5 10uF/10V
CAP- VOUT
U202 TC7660

Figure 4-3. SCI Interface Circuit

Communication Interface Board Hardware Architecture, Rev. 0

Freescale Semiconductor 4-3
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
4-4 Freescale Semiconductor
Preliminary
 Arithmetic of Power Factor Correction

Chapter 5
Control Strategy Design

5.1 Control of Power Factor Correction System

Based on the 56F8323, a digital PFC rectifier is implemented as shown in Figure 5-1. The main circuit
contains two switches operated in interleaved mode. The circuit is composed of Q1/Q2, D1/D2, Lq/Lw,
and filter capacitance C and includes EMI filter, input relay and full-wave rectifier.

5.2 Arithmetic of Power Factor Correction

Power Factor (PF) is defined as the ratio between AC input’s real power and apparent power. Assuming
input voltage is a perfect sine wave, PF can be defined as the product of current distortion and phase
shift. Consequently, the PFC circuit’s main tasks are:
• Controls inductor current, which makes the current sinusoidal and maintains the same phase
as the input voltage
• Controls output voltage, which insures the output voltage’s stability
Two closed loops are needed to control the circuit:
• The voltage loop is the outer loop, which samples the output voltage and maintains a stable
level
• The current loop is the inner loop, which samples inductor current and forces the current to
follow the standard sinusoidal reference in order to reduce the input harmonic current

Arithmetic Digital Sine

PFC
Structure Wave Reference

+ Verr Ierr
Vref A Km • A • B Iref
X Gvol Iref = X Gcur
C + Dout
- -
V_out C V_ff I_input

Voltage Loop Reference Arithmetic Current Loop

Figure 5-1. Digital PFC Arithmetic Structure Design

Control Strategy Design, Rev. 0

Freescale Semiconductor 5-1
Preliminary
According to PFC theory, PFC arithmetic can be divided into three parts:
• Voltage outer loop insures the output voltage follows the reference-constant voltage output
• Reference arithmetic insures that the current reference follows the sine reference and constant
power feed forward
• Current inner loop insures the input current follows the given current reference and implements
PRC function

5.2.1 Arithmetic of Current Reference

In analog control arithmetic, the current reference wave is referred to as input voltage; at the same time,
it introduces the squared input voltage as reciprocal to maintain constant power control.

K m ⋅ vvo
iL* = Vs sin ϖ 0t
V ff2
Eqn. 5-1
Where:
Km is the proportion value
Vvo is the output of the voltage regulator
Vs is the instantaneous value of input voltage
Vff is the RMS value of feed forward voltage
In analog arithmetic, the input voltage sample must be introduced as the input current’s reference so the
ripple voltage is introduced to current control at the same time. The PFC will be greatly affected under
conditions of extreme input. In addition, because the input voltage acts as current reference, the
denominator of current reference will be the square of input voltage. It will be additional calculation
spending, which consequently affects system performance. In a digital control system, sine reference
can be given accurately and conveniently by the controller’s software, which not only will create a perfect
sine wave, so there will be no effect from input voltage, but will also simplify the arithmetic structure.

K m ⋅ Vvo
iL* = I shape
V ff
Eqn. 5-2
Where:
Ishape is the reference sine wave generated by software
Km is the proportional value
Vvo is the output of voltage regulator
Vff is the RMS value of feed forward voltage
This demonstrates that current reference is calculated from input voltage in analog arithmetic,
unavoidably introducing ripple voltage to current control. Once the operating condition changes, the PFC
effect will be obviously affected, but digital arithmetic can completly avoid this influence. The sine

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

5-2 Freescale Semiconductor
Preliminary
 Arithmetic of Power Factor Correction

reference is generated by DSP software and the wave can be perfect even if the input voltage has great
distortion, so the system input current can be a very clean sine wave, which results in a perfect PFC
effect. In addition, in analog arithmetic, the denominator of current reference must be the square of input
voltage to calculate the current reference. The digital equation doesn’t require the square of the input
voltage, so it is also simpler.

5.2.2 Voltage and Current Loop Design

Because of its simplicity and reliability, PI loop control is widely used in industry control. In this
application, the voltage and current loops adopt PI regulator arithmetic.
To simplify the analysis, the following assumptions are made:
• Input current follows reference perfectly, and is proportional to the input voltage
• The power efficiency is 1
• The output power is constant

Figure 5-2. Simple PFC Model

Because input current is proportional to input voltage, and inductor current is assumed to follow
reference perfectly:

2 Pin
iin = K i sin ϖ 0t
Vrms
Eqn. 5-3
Where:
Ki is input current sample modulus
Pin is average input power
Vrms is the virtual value of input voltage
Input power equals output power, so:

Pin = Pout = Vo ⋅ I o
Eqn. 5-4
Where:
Pout is the average output power
Vo is the average output voltage
Io is the average output current

Control Strategy Design, Rev. 0

Freescale Semiconductor 5-3
Preliminary
Substituting Equation 5-2, Equation 5-3 and Equation 5-4, and taking the sample modulus of the sine
reference as 1 yields:

iin ⋅Vrms K mVrms

Vo I o = Pin = = Vvo = K ⋅Vvo
2 K i | sin ω 0t | 2 K i K ff V ff
Eqn. 5-5
Including:

K mVrms
K=
2 K i K ff V ff
Eqn. 5-6
K is constant value
Assume (Vo, Io, Vvo) is the stable point of voltage
According to small signal analysis, introducing small signal disturbance to Equation 5-5 yields:
~
(V0 + v~o )( I o + io ) = K (Vvo + v~vo )
Eqn. 5-7
If:
Vvo, Vo and Io are stable parts
~
vvo, ~vo and~io are small signal parts
Then:

~ K~ I
io = vvo − o v~o
Vo Vo
Eqn. 5-8
Vo and Io are stable parts
~
vo and ~io are small signal disturbances
Considering the relation of output current:

dvo Pout
io = C +
dt vo
Eqn. 5-9
Applying small signal analysis to Equation 5-9 yields:

~ dv~ P
io = C o − out2 v~o
dt Vo
Eqn. 5-10
So:

K~ I dv~ I
vvo − o v~o = C o − o v~o
Vo Vo dt Vo
Eqn. 5-11

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

5-4 Freescale Semiconductor
Preliminary
 Arithmetic of Power Factor Correction

PFC transfer function can be derived easily from the following:

v~ K
Gv ( S ) = ~o =
vvo SCVo
Eqn. 5-12
Control is discrete digital control, so it’s necessary to consider the effect of the sample and hold time and
calculation delay when modeling the system. Applying Z transfer to Equation 5-12 yields the discrete
mathematical model of the power transfer function:

Gv ( S ) K ⋅ TS
Gvh ( z ) = Z (Gvh ( S )) = (1 − z −1 ) Z [ ]=
S CVo ( z − 1)
Eqn. 5-13
Where:
Ts is the sample period of the voltage loop
The discrete voltage loop structure is shown in Figure 5-3, where:
Kvs is the out voltage sample modulus
GVEA(Z) is the discrete control transfer function
Gvh(Z) is the discrete power transfer function
After deriving the discrete power transfunction, it’s necessary to consider the discrete control transfer
function.

Vo* Vo
X GVEA(Z) Gvh(Z)
_

Kvs

Figure 5-3. Discrete Voltage Loop Structure

The voltage regulator adopts the PI regulator, so:

K iv z ( K pv + K iv ) z − K pv z −ξ
GVEA ( z ) = K pv + = = Kp
z −1 z −1 z −1 Eqn. 5-14
Where:
Kpv is the P parameter
Kiv is the I parameter
Kp and ξ are two temporary variables

Control Strategy Design, Rev. 0

Freescale Semiconductor 5-5
Preliminary
 K pv
K p = K pv + K iv , ξ =
K pv + K iv
Eqn. 5-15
The voltage open loop transfer function is:

Gvopen ( z ) = K vs GVEA ( z )Gvh ( z )

Eqn. 5-16
To restrain the effect to the current loop caused by two order harmonics in the output voltage, the
voltage loop must have the ability to restrain the harmonics voltage to a range between 100 to 120Hz. If
close frequency is 6Hz, and phase abundance is 45, according to the characteristic of the open loop
transfer function, it’s possible to calculate the P, I parameters of the voltage loop. The current loop is
also a PI regulator, with a design course similar to the voltage loop. There is no need to introduce it once
again.
The parameters of the voltage and current loops are determined through simulation and experiment. To
insure the best system performance in a wide input voltage, different parameters are adopted when the
input voltage is between 110V and 220V, which is impossible in analog control.

Table 5-1. PFC Experiment PI Parameters

Input Voltage Loop Parameter Symbol Value

Proportion modulus Kpv 5

Voltage loop
Integration modulus Kiv 0.007
110V
Proportion modulus Kpi 0.17
Current loop
Integration modulus Kii 0.044

Proportion modulus Kpv 5

Voltage loop
Integration modulus Kiv 0.007
220V
Proportion modulus Kpi 0.44
Current loop
Integration modulus Kii 0.09

5.3 Control of DC/DC Converter Subsystem

Figure 5-4 shows the main circuit, composed of four switches (Q1—Q4); transformer (Tf); Capacitance
(Cr), which prevents saturation of the transformer; secondary synchronous rectifiers (Q5 and Q6); filter
inductors (Lf1 and Lf2); and output filter capacitance (Cf). Input voltage is 380V DC and switching
frequency is 150KHz.
Ignoring the dead time that is inserted by the PWM peripheral, the two switches in one power bridge
operate at a 180o complement to each other. Constant output is achieved by adjusting the value of
phase shift. When α = 0°, and Q1/Q4 or Q2/Q3 are on simultaneously, output value is maximum; when
α = 180° and Q1/Q2 or Q3/Q4 are on simultaneously, output voltage is zero. The 56F8323 samples three
signals: output voltage (Vo), primary inductor current (iL), and output current (io).

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

5-6 Freescale Semiconductor
Preliminary
 Control of DC/DC Converter Subsystem

The 56F8323’s PWM1—PWM4 output the drive signal, whose dead time and duty have been fixed, and
according to α, adjust the value of phase shifted in order to stabilize the output voltage. From the
relationship between the synchronous signal and primary drive signal, the synchronous drive signal can
be derived easily. The digital DC/DC converter’s software also drives the LED circuits to show the output
voltage value, protects the output current and communicates with the PC.

Figure 5-4. PFC Module Frame Based on the 56F8323

Control Strategy Design, Rev. 0

Freescale Semiconductor 5-7
Preliminary
5.3.1 DC/DC Converter Arithmetic

Arithmetic
PSFB
Structure

+ Verr Ierr
Vref Iref Dout PWM PWM
X Gvol X Gcur
+ Generation Output
- -
V_out I_L

Voltage Loop Current Loop

Figure 5-5. Digital Control PSFB Converter

The voltage and current loops are adopted by the system. The error signal is generated by comparing
the reference and sample values of output voltage. The voltage loop is composed by a PI regulator
whose input is the error signal. The output of voltage acts as the reference of the current loop and the
error signal between the primary inductor current, and its reference acts as the input of the current loop’s
PI regulator. The current loop outputs the results of the PI regulator, which is the control signal of
shifted-Phase α.

5.3.2 Voltage and Current Loops Design

Vo* Vo
X GVEA(Z) Gvh(Z)
_

Kvs

Figure 5-6. Power Factor Correction Arithmetic

PI regulators are also adopted for voltage and current loops of the PSFB DC/DC converter.
Device-based control is actually a kind of discrete digital control; control results can be calculated
according to the sampled value, so the transfer function of the PI regulator can be shown as follows:

⎧U (n) = K 0 × E (n) + I (n − 1)
⎪
⎨ I (n) = I (n − 1) + K1× E (n) + Kcorr × Epi
⎪ Epi = Us − U (n)
⎩

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

5-8 Freescale Semiconductor
Preliminary
 Control of DC/DC Converter Subsystem

Us is calculated as follows:

⎧U max U (n) ≥ U max

⎪
Us = ⎨ U min U (n) ≤ U min
⎪U (n) else
⎩
U(n) is the calculation result corresponding to the nth sample value
E(n) is the variable error at the nth sampling time
I(n)—I(n-1) is the sum of n sample values and n-1 sample values separately
K0 is proportion modulus
KI is integral modulus
Kcorr is the modulus used to prevent saturation
Epi prevents saturation
Kcorr x Epi operates only when U(n) overflows, so usually Epi = 0
Parameters of the voltage and current loops are determined through emulation and experiment. To
insure the best system performance in a wide input voltage, different parameters are adopted when the
input voltage is between 110V and 220V, which is impossible in analog control.

Table 5-2. PFC Experiment PI Parameters

Loop Parameter Symbol Value

Proportion modulus Kpv 0.195

Voltage loop
Integration modulus Kiv 0.004

Proportion modulus Kpi 0.42

Current loop
Integration modulus Kii 0.001

Control Strategy Design, Rev. 0

Freescale Semiconductor 5-9
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
5-10 Freescale Semiconductor
Preliminary
 PFC PWM Control Strategy

Chapter 6
Software System Design—PWM Control Strategy

6.1 PFC PWM Control Strategy

PFC control requires two PWM signals, between which there is a 180° phase shift. The 56F8323
device’s PWMA0 and PWMA1 are used to generate these two PWM signals.

One switching period

(10us)

PMVAL0

PMVAL1

PWMA0

PWMA1

Figure 6-1. PFC PWM Generation

As Figure 6-1 shows, PMVAL0 is active high and PMVAL1 is active low. Write the result of PFC current
control loop to PMVAL0, and PMVAL1 has the following relation with PMVAL0:
PMVAL0 + PMVAL1 = PWMCM
So:
PMVAL1 = PWMCM - PMVAL0
The ZVS gate drive precedes the PVC switch’s Q gate drive output. The duration of the ZVS output is
the time necessary for a controlled turn-off of the boost diode plus the time required for the main
MOSFET drain voltage to resonate to zero. The ZVS Q then turns off and the main Q turns on
simultaneously.

Software System Design—PWM Control Strategy, Rev. 0

Freescale Semiconductor 6-1
Preliminary
Figure 6-2 shows the gate drive waveforms of the main and ZVS transistors. The ZVS drive is high until
the main transistor switches on. The ZVS transistor keeps active high for a certain time, which is
determined by the soft-switching condition of the main MOSFET and DIODE reverse recovery. The ZVS
pulse is then terminated and the main gate drive initiated. According to Vg_Q1, the ZVS transistors’ gate
drive waveform will be generated by the device, shown in Figure 6-2. At t1, the rising edge of ZVS_Q1
can be obtained by the Timer module that operates in variable frequency PWM mode. ZVS_Q1 will
remain high until t2.
TMRCMP1 = Const
TMRCMP2 = 2 x PWMCM - PWMVALUE - TMRCMP1 - Delay

Start Timer
PWMCM
PWMVALUE

Vg_Q1

ZVS_Q1
t1 t2 TMRCMP1
TMRCMP2
Timer Start Delay

Figure 6-2. Gate Drive Waveforms of the Main and ZVS Transistors

6.1.1 DC/DC PWM Value Register Update

DC/DC requries four PWM signals. PWM signals Q1 and Q3 are oppositional; PWM signals Q2 and Q4
are oppositional. There is a phase shift between Q1 and Q4 and between Q2 and Q3.

Figure 6-3. DC/DC Full Bridge

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

6-2 Freescale Semiconductor
Preliminary
 PFC PWM Control Strategy

The relationship between the device’s ports and the control signals is shown in Table 6-1.

Table 6-1. Relation Between the 56F8323’s Ports and Control Signals
Ports Control Signals

PWMA2 Q1

PWMA3 Q3

PWMA4 Q4

PWMA5 Q2

The 56F8323’s PWM module has a special feature, asymmetric PWM output mode, which allows the
PWM duty cycle the ability to change alternatively at every half-cycle when in complementary mode with
center-align operation. The count direction of the PWM counter selects either the odd or even PWM
value registers to use in the next PWM cycle. To count up, select the odd PWM value registers to use in
the next PWM cycle. To count down, select the even PWM value registers to use in the next PWM cycle.
Using this feature, the 56F8323’s PWM module can realize phase-shifting operation without any external
auxiliary circuit or additional expenditure of software resources.

Figure 6-4. DC/DC PWM Generation

Set ICC1 and ICC2 of the PWM Internal Correction Control Register (PMISCCR). PMVAL2 and
PMVAL4 will be used when the counter is counting up and PMVAL3 and PMVAL5 will be used when the
counter is counting down.

Software System Design—PWM Control Strategy, Rev. 0

Freescale Semiconductor 6-3
Preliminary
As Figure 6-4 shows, PMVAL2 and PMVAL 3 are set at initialization and will not be changed during
control. The result of the DC/DC current control loop is the shift_angle, then:
Th = Duty x Period
PMVAL2 = Th - Shift_angle
PMVAL3 = Th + Shift_angle
PMVAL4 = Th + Shift_angle
PMVAL5 = Th - Shift_angle
In this design, the same 56F8323 that drives the DC/DC converter circuitry also drives the synchronous
rectifier. According to the analysis of the circuit, there is a direct relationship between the main DC/DC
switches and the synchronous rectifiers, so control of the synchronous rectifer can be derived from the
control of the DC/DC converter. The relationships are illustrated in Figure 6-5.

Lead Leg

Lag Leg

Synchronous Rectifier

CONST2
CONST1

Figure 6-5. Current Doubler and Synchronous Rectification PWM Generation

As shown in Figure 6-5, the control of the synchronous rectifier is derived from the DC/DC converter
main switches’ signals. To avoid short circuiting the transformer when voltage is established, the
synchronous rectifier must turn off when the switch in the lag leg turns on. Also, to avoid the current
flows from the synchronous rectifier’s body diode, it must turn on when the lead leg switches on. But to
avoid a short circuit, there must be a delay time between the rectifier’s turn on and the lead leg’s turn off.

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

6-4 Freescale Semiconductor
Preliminary
 Details of Interrupt Service Routines

Chapter 7
Software Architecture

7.1 Software Infrastructure—Dual Digital Signal Controllers

Figure 7-1. System Software Structure

7.2 Details of Interrupt Service Routines

7.2.1 PFC Controller
Current Loop Interrupt—PWM Reload Interrupt (100KHz):
• Configures Timer A0 to gain the delay signal for ZVSPWM
• Calculates current loop
• Calculates the input frequency and confirms the sinusoid table step
Fault2 Interrupt:
• Forces PWM to output logic low
• Sends a fault message to the DC/DC controller
RS-232 Communication Interrupt:
• Receives the communication data from the secondary-side 56F8323
• Sets the Switch-on or Protect directive from the secondary-side 56F8323
Voltage Loop Interrupt—Timer A2 Period Interrupt (10KHz):
• Manages software protection
• Voltage Loop

Software Architecture, Rev. 0

Freescale Semiconductor 7-1
Preliminary
7.2.2 DC/DC Controller
Current Loop Interrupt—Timer A1 Period Interrupt (50KHz):
• Starts ADC
• Calculates PI current loop
• Calculates each PWM register value and refreshes the new duty PWM output
Voltage Loop Interrupt—Timer A0 Period Interrupt (25KHz):
• Manages software protection
• Calculates PI voltage loop
• Calculates the value of output voltage and output current
Fault2 Interrupt:
• Forces PWM to output logic low
• Sends a fault message to the PFC controller

7.3 Software Interrupt Service Timing

7.3.1 PFC Controller

Table 7-1. Bandwidth Consideration of PFC Controller

56F8323 Frequency 60MHz
Instruction Period 16.67ns
PWM Switching Frequency 100kHz
Sampling Rate 100kHz
Analog-to-Digital 1.7µs
Interrupt Name Interrupt Period Interrupt Assignment
Voltage loop 10kHz Timer Calculates the PI of voltage loop
Voltage loop output
Calculates the mean of input voltage
Current loop 100kHz Timer Starts ADC
Calculates current loop reference
Calculates the PI of the current loop and get sthe new duty
Updates the PWM
Produces ZVS_PWM
Fault2 Interrupt: Event trigger Powers the system off
RS-232 Communication Interrupt Event trigger Receives communication data from the secondary-side 56F8323
Sets the Switch-on or Protect directive from the secondary-side
56F8323

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

7-2 Freescale Semiconductor
Preliminary
 Software Interrupt Service Timing

7.3.2 DC/DC Controller

Table 7-2. Bandwidth Consideration of DC/DC Controller

56F8323 Frequency 60MHz
Instruction period 16.67ns
PWM Switching Frequency 150kHz
Sampling Rate 50kHz
Analog-to-Digital 1.7µs
Interrupt Name Interrupt Period Interrupt Assignment
Voltage loop 25kHz Timer Software Protection judgement and management
Calculates the PI of the voltage loop
Calculates the mean of output voltage and output current
Current loop 50kHz Timer Starts ADC
Calculates the PI of the current loop and gets the new duty
Updates the PWM output of the main power driver and
synchronous driver signal
Produces ZVS_PWM
Fault2 Interrupt: Event trigger Powers the system off
Transmits the communication data to the primary side 56F8323

Software Architecture, Rev. 0

Freescale Semiconductor 7-3
Preliminary
 Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0
7-4 Freescale Semiconductor
Preliminary
 Software System Design—Flow Chart of PFC Control System

Chapter 8
Flow Chart of Software System Design

8.1 Software System Design—Flow Chart of PFC Control System

start

Initialization: The interrupt includes:

PWM reload interrupt: 100KHZ, which is halved by setting
1. Interrupt curloop_flag 0 or 1 to get the current loop calculation period,
2. Pulse Width Modulator Module (PWM) 50KHZ
3. Analog-to-Digital Converter (ADC) Timer A2 period interrupt: voltage loop calculation, 10KHZ
4. General Purpose Input/Output (GPIO) PWM initialization considerations:
5. Serial Communication Interface(SCI) PWMA0 active high and PWMA1 active low
ADC initialization considerations:
6. Quad Timer(TMR) Use the START bit to initiate a conversion
7. User-defined variables Use channel ANA0, ANA1, ANA4
Once Sequential sampling
SCI0: used for communication between DSC and PC
SCI1: used for communication between two DSCs
GPIO used pins and functions:
N GPIOC0: RELAY, output
PONSIGNAL=“1”
Y ? output logic one to close the input relay
GPIOB6: DADATA, output
GPIOB5: DACLK, output
GPIOB2: DACEN, output
these three pins are used for Digital-to-Analog
Read DC/DC message Conversion
GPIOA7: output, used for fault display
GPIOA11: LEDDATA, output
DC/DC initialization finished? GPIOA10: LEDCLK, output
GPIOA9: LEDEN, output
N
these three pins are used to drive LED display
Y GPIOC2, GPIOC3: reserved for I 2 C
GPIOC1: PONSIGNAL, input
Relay (GPIOC0) =“1” logic one: enable the system
Close the input relay logic zero: disable the system

Soft Start PFC

Received DC/DC fault signal?

N
Y
PONSIGNAL=“1”?
Mask PWM out, open the input relay Y
N

Open the input relay

Refresh LED display

Loop wait for ISR

Figure 8-1. PFC Main Program Flow Chart

Flow Chart of Software System Design, Rev. 0

Freescale Semiconductor 8-1
Preliminary
 start
Current loop calculation frequency = 50KHz
Start ADC

FAULTA1 =“1”？
Y
N
Read the ADC results of input voltage

curloop_flag = 1 ?
N
Y

Initialize Timer A0 PFC PI current loop

calculation Mask PWM out

Calculate PFC current

loop reference Initialize Timer C3
Open the input relay

Curloop_flag = 0 Curloop_flag = 1

Update PWM value register

PMVAL0, PMVAL1

RET

Figure 8-2. PFC Reload Interrupt ISR Flow Chart

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

8-2 Freescale Semiconductor
Preliminary
 Software System Design—Flow Chart of PFC Control System

start
Voltage loop calculation frequency = 10KHz
Read the ADC result of DCBus

Y
Input voltage > 270V? or Input
voltage < 75V? or DCBus >
430V?
N
Calculate the average of Mask PWM out and
input voltage (inputvolavg) open the input relay

PFC voltage loop

RET

Figure 8-3. PFC Timer A2 Period Interrupt ISR Flow Chart

Flow Chart of Software System Design, Rev. 0

Freescale Semiconductor 8-3
Preliminary
8.2 Software System Design—Flow Chart of DC/DC Control System

start
The interrupt includes:
Timer A1 period interrupt: current loop calculation, 50KHz
Timer A0 period interrupt: voltage loop calculation, 25KHz
PWM initialization considerations:
Initialization: PWMA2, PWMA3, PWMA4, PWMA5 active high
1. Interrupt ADC initialization considerations:
Use the START bit to initiate a conversion
2. Pulse Width Modulator Module (PWM) Use channel ANA2, ANA5, ANA6
3. Analog-to-Digital Converter (ADC) Once Sequential sampling
4. General Purpose Input/Output (GPIO) SCI0: used for communication between DSC and PC
5. Serial Communication Interface (SCI) SCI1: used for communication between two DSCs
6. Quad Timer (TMR) GPIO used pins and functions:
GPIOA9: DADATA, output
7. User-defined variables GPIOA10: DACLK, output
GPIOA11: /DACEN, output
these three pins are used for Digital-to-Analog
Conversion
GPIOB2,GPIOB3,GPIOB4: output, used for fault display
Enable PWM output GPIOB5: LEDDATA, output
in specific order GPIOB6: LEDCLK, output
GPIOB7: /LEDEN, output
these three pins are used to drive LED display
GPIOC2, GPIOC3: reserved for I2 C
Send READY message
to PFC controller

N
Is there any protection ?

Mask PWM out

Transmit fault signal to

primary-side controller

Refresh LED display

Loopwait ISR

Figure 8-4. DC/DC Main Program Flow Chart

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

8-4 Freescale Semiconductor
Preliminary
 Software System Design—Flow Chart of DC/DC Control System

start DC/DC voltage loop calculation frequency = 25KHz

Read the ADC result of output

voltage and output current

Y
Output voltage overvoltage

Output voltage undervoltage

Y

Output current overcurrent

Y

Mask PWM out

DC/DC PI voltage loop calculation

Send fault message to PFC controller

The mean value of output voltage
and output current calculation

RET

Figure 8-5. DC/DC Timer A0 Period Interrupt ISR Flow Chart

Flow Chart of Software System Design, Rev. 0

Freescale Semiconductor 8-5
Preliminary
 start DC/DC current loop calculation frequency = 50KHz

Read the ADC result of primary

side inductance current

Start the ADC

DC/DC PI current loop calculation

Update PWM value register

by current loop result

RET

Figure 8-6. DC/DC Timer A1 Period Interrupt ISR Flow Chart

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

8-6 Freescale Semiconductor
Preliminary
Appendix A
Schematics

Schematics, Rev. 0
Freescale Semiconductor Appendix A-1
Preliminary
 1 2 3 4 5 6

Appendix A-2
J1 Output Signal Interface
32A +5V_DSP 32B +5V_DSP SIGNALOUT.Sch
31A GND_D 31B GND_D PFCPWM1
PWMA0 PFCPWM1
30A GND_D 30B GND_D PFCPWM2
PWMA1 PFCPWM2
A 29A IRQA 29B IRQA Analog Signal For ADC Filters 56F8323 Processor Main Circuit PWM1 A
PWMA2 PWM1
28A GND_D 28B GND_D ADCIN.SCH PROCESSOR.Sch PWM2
PWMA3 PWM2
27A INPUTCUR_PRO 27B INPUTCUR_PRO INPUT_VOL PWM3
INPUT_VOL ANA0 ANA0 PWMA0 PWMA4 PWM3
26A INDCUR_PRO 26B INDCUR_PRO INPUT_CUR PWM4
INPUT_CUR ANA1 ANA1 PWMA1 PWMA5 PWM4
25A GND_D 25B GND_D DCBUS ZVSPWMA1 ZVSPWM1
DCBUS ANA2 ANA2 PWMA2 ZVSPWMA1 ZVSPWM1
24A PONSIGNAL 24B PONSIGNAL IND_CUR ZVSPWMA2 ZVSPWM2
IND_CUR ANA4 ANA4 PWMA3 ZVSPWMA2 ZVSPWM2
23A INPUTVOL_FRQ 23B INPUTVOL_FRQ OUTPUT_VOL
OUTPUT_VOL ANA5 ANA5 PWMA4
22A GND_D 22B GND_D OUTPUT_CUR
OUTPUT_CUR ANA6 ANA6 PWMA5
21A PFCPWM1 21B ZVSPWM1
ZVSPWMA1
20A PFCPWM2 20B ZVSPWM2 +3.3VA
+3.3VA ZVSPWMA2
19A PWM1 19B PWM1 GND_A
GND_A
18A PWM2 18B PWM2
17A PWM3 17B PWM3 PONSIGNAL LED LED.SCH
GND_D PONSIGNAL
16A PWM4 16B PWM4
RELAY RELAY
15A GND_D 15B GND_D J2 TDOD AC_RELAY
TDOD LEDDATA LEDDATA AC_RELAY
14A AC_RELAY 14B AC_RELAY TDID TMSD
1 2 TMSD LEDCLK LEDCLK
13A GND_D 13B GND_D TDOD TCKD
3 4 TCKD /LEDEN /LEDEN
12A GND_D 12B GND_D TCKD TDID
5 6 TDID
11A TXD1 11B TXD1 /J_TRSTD INPUTCUR_PRO
7 8 /J_TRSTD INPUTCUR_PRO
10A RXD1 10B RXD1 /J_RESETD TMSD /J_RESETD INDCUR_PRO
9 10 /J_RESETD INDCUR_PRO
9A GND_A 9B GND_A +3.3V_DSP
R30 11 12 +5V_DSP
8A GND_A 8B GND_A /J_TRSTD RXD0
+3.3V_DSP 13 14 RXD0
7A +3.3VA 7B +3.3VA 47K TXD0
TXD0
6A GND_A 6B GND_A JTAG INPUTVOL_FRQ
B INPUTVOL_FRQ B
5A GND_A 5B GND_A
4A INPUT_VOL 4B INPUT_CUR J3 R1 R2
3A DCBUS 3B IND_CUR 5.6K 5.6K
+3.3V_DSP 1 2 +5V_DSP
2A OUTPUT_CUR 2B OUTPUT_VOL
GND_D 3 4 GND_D
1A GND_A 1B GND_A TXD0 TXD0 IRQA
5 6 IRQA
RXD0 RXD0 J4
7 8
DIN64 (to power board) GPIOC2 I2C PORT
GPIOC2 1
SCI TAG GPIOC3
GND_D GND_D GPIOC3 2
+3.3VA
+3.3VA
POWER CIRCUIT TXD1
GND_A GND_A TXD1
POWER.Sch RXD1
RXD1
+5V_DSP +3.3V_DSP
+5V_DSP +3.3V_DSP +3.3V_DSP
+3.3V_PLL DA
GND_D +3.3V_PLL +3.3V_PLL
DA.Sch
/RESETD
/RESETD /RESETD
GND_D DACDATA
DACDATA DACDATA
DACCLK
DACCLK DACCLK
/DACEN
/DACEN /DACEN
+3.3VA
+3.3VA
GND_A
GND_A
+3.3V_DSP
+3.3V_DSP
GND_D
GND_D
C C

J6
+3.3V_DSP 1 2 +3.3V_DSP
GND_D 3 4 GND_D
DACCLK DACDATA
5 6
/DACEN /RESETD
7 8
DA-TAG

D D

Title
The Hierarchy System Schematic of Controller Board
Size Number Revision
B 3.0

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 1 /7
File:
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4

Preliminary
A A

Freescale Semiconductor
POWER GOOD LED
D1 D2
R3
TE2
+5V_DSP 300 +3.3V
FM4001
GND_D GREEN LED U1
+5V_DSP 4 2
D20 VIN VOUT +3.3V_DSP
B L1 5 3 +3.3V_DSP B
1N4733 NC VOUT L2 L3
8 6 +3.3V_PLL
C9 + NC VOUT +3.3V_PLL
GND_D 1 7
C10 C11 C12 C13 C14
47uF/10V GND VOUT
0.1uF0.1uF0.1uF0.1uF0.1uF TE1 0.1uF 0.1uF
MC33629DT-3.3 C15+ C18+
GND_D 47uF/10V 47uF/10V C19
GND_D
GND_D C16 C17 0.1uF

GND_D GND_D

C C

Schematics, Rev. 0
Title
D Power Supply For DSC System D

Size Number Revision

A 3.0
Date: 2004-12-27 Sheet of 5 /7
File:
1 2 3 4

Appendix A-3
 1 2 3 4
D13
+3.3VA BAV99 GND_A
TE9
2 1
+3.3VA GND_A INPUT_VOL

3
INPUT_VOL R21 ANA0

Appendix A-4
INPUT_VOL ANA0
100
C30
A A
2.2nF
D14
BAV99 GND_A
TE10
2 1
+3.3VA GND_A INPUT_CUR

3
INPUT_CUR R22 ANA1
INPUT_CUR ANA1
100
C31
PFC SAMPLE
0.1uF TE23
GNDA
D15
BAV99 GND_A
TE11
2 1
+3.3VA GND_A DCBUS

3
DCBUS R23 ANA4
B DCBUS ANA4 B
100 GND_A
C32

2.2nF

GND_A
D16
BAV99
TE12
2 1
+3.3VA GND_A IND_CUR

3
IND_CUR R24 ANA2
IND_CUR ANA2
100
C33

2.2nF
D17
BAV99 GND_A
C TE13 C
2 1
+3.3VA GND_A OUTPUT_VOL

3
OUTPUT_VOL R25 ANA5
OUTPUT_VOL ANA5
100
C34

2.2nF DC/DC SAMPLE

D18
BAV99 GND_A
TE14
2 1
+3.3VA GND_A OUTPUT_CUR

3
OUTPUT_CUR R26 ANA6
OUTPUT_CUR ANA6
100
C35

2.2nF

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Title
D GND_A Analog Signal For ADC Filters D

Size Number Revision

A 3.0
Date: 2004-12-27 Sheet of 2/ 7
File:
1 2 3 4

Preliminary
Freescale Semiconductor
 1 2 3 4

+3.3VA GND_A
R4 R5 R6

Preliminary
10K 10K 10K ANA0 26 3 PWMA0 +3.3V_DSP
ANA0 ANA0 PWMA0/GPIOA0 PWMA0
ANA1 27 4 PWMA1
ANA1 ANA1 PWMA1/GPIOA1 PWMA1
ANA2 28 7 PWMA2
ANA2 ANA2 PWMA2/GPIOA2/SS1 PWMA2
GND_A 29 8 PWMA3
A ANA3 PWMA3/GPIOA3/MISO1 PWMA3 D3 D21 A
ANA4 30 9 PWMA4
ANA4 ANA4 PWMA4/MOSI1/GPIOA4 PWMA4 1N4148 1N4148
ANA5 31 10 PWMA5
ANA5 ANA5 PWMA5/SCLK1/GPIOA5 PWMA5
ANA6 32
ANA6 ANA6
AD SET ANA7 33 13
ANA7 FAULTA0/GPIOA6
14 INPUTCUR_PRO

1
2
3
4
5
6
7
8
FAULTA1/GPIOA7 INPUTCUR_PRO
J5 +3.3VA 40 15 INDCUR_PRO

Freescale Semiconductor
VREFH FAULTA2/GPIOA8 INDCUR_PRO
37 10K
C20 VREFP R7
36 16 /LEDEN
C21 VREFMID ISA0/GPIOA9 /LEDEN
35 18 LEDCLK 10K
0.1uF C24 VREFN ISA1/GPIOA10 LEDCLK R8
38 19 LEDDATA
0.1uF VREFLO ISA2/GPIOA11 LEDDATA
0.1uF +3.3VA 41 52 ZVSPWMA1 R11 10K
100pF 0.001uF 0.1uF VDDA_ADC TA0/GPIOB7/PA0 ZVSPWMA1
+3.3V_PLL 42 51 DACDATA
VDDA_OSC_PLL TA1/GPIOB6/PB0 DACDATA
6 50 DACCLK GND_D
D6
C26 C27 C28 VDD_IO TA2/GPIOB5/INDEX0 DACCLK R10 RED LED
GND_A 20 49 INTPUTVOL_FRQ
+3.3V_DSP VDD_IO TA3/GPIOB4/HOME0 INPUTVOL_FRQ
48 25 FAULTDIS1 300
+3.3V_DSP VDD_IO SCLK0/GPIOB3
59 24 /DACEN D5
VDD_IO MOSI0/GPIOB2 /DACEN R9 RED LED
GND_A 22 RXD1
RXD1/MISO0/GPIOB1 RXD1
B 39 21 TXD1 300 B
GND_A VSSA_ADC TXD1/SS0/GPIOB0 TXD1
11 64 RXD0 +3.3V_DSP
VSS RXD0/TC1/GPIOC5 RXD0
17 1 TXD0
GND_D VSS TXD0/TC0/GPIOC6 TXD0
44 61 GPIOC2
VSS CAN_RX/GPIOC2 GPIOC2
60 62 GPIOC3
VSS CAN_TX/GPIOC3 GPIOC3
VCAP1 57
VCAP1
VCAP2 23 46 RELAY
C22 VCAP2 EXTAL/GPIOC0 RELAY
VCAP3 5 47 PONSIGNAL
2.2uF C23 VCAP3 XTAL/GPIOC1 PONSIGNAL
VCAP4 43 55 TDID
2.2uF C25 VCAP4 TDI TDID
OCR_DIS 45 56 TDOD D4
2.2uF C29 OCR_DIS TDO TDOD
53 TCKD INTPUTVOL_FRQ
2.2uF TCK TCKD +3.3V_DSP
ZVSPWMA2 63 54 TMSD D22
ZVSPWMA2 TC3/GPIOC4 TMS TMSD
IRQA 12 58 /TRSTD 1N4148
IRQA IRQA TRST +3.3V_DSP
34 2 /RESETD
TEMP_SENSE RESET /RESETD
GND_D +3.3V_DSP1N4148
R12 U3 F8323
47K

C5 C6 C7 C8
C 0.1uF 0.1uF 0.1uF 0.1uF C

Schematics, Rev. 0
U2A GND_D U2B
/J_RESETD 1 4 GND_D
/J_RESETD
MC74HC00 3 MC74HC00 6 /RESETD
S1 2 5
VDD
GND_D
+3.3V_DSP
VSS
RESET PUSHBUTTON +3.3V_PLL
R13 +3.3V_PLL

14
+3.3V_DSP U2C U2D
10K R14
9 12 OCR_DIS GND_D
GND_D
MC74HC00 8 MC74HC00 11 /TRSTD 1K

VCC
/J_TRSTD 10 13 +3.3VA

GND
/J_TRSTD +3.3VA
GND_A
+3.3V_DSP

7
GND_A
GND_D
C3 Title
D 0.1uF D

Size N 56F8323 Processor Main Circuit Revision 3.0

GND_D
A
MC74HC00(U2)
Date: 2004-12-27 Sheet of 6 / 7
File:
6
1 2 3 4

Appendix A-5
 1 2 3 4

Appendix A-6
A TE3 TE4 TE5 TE6 TE7 TE8 A
PFCPWM1PFCPWM2PWM1 PWM2 PWM3 PWM4
+5V_DSP

20
U4
PWMA0 2 18 PFCPWM1
PWMA0 1A1 1Y1 PFCPWM1
PWMA1 4 16 PFCPWM2
PWMA1 1A2 1Y2 PFCPWM2

VCC
ZVSPWMA1 6 14 ZVSPWM1
ZVSPWMA1 1A3 1Y3 ZVSPWM1
ZVSPWMA2 8 12 ZVSPWM2
ZVSPWMA2 1A4 1Y4 ZVSPWM2
PWMA2 11 9 PWM1
PWMA2 2A1 2Y1 PWM1
PWMA3 13 7 PWM2
PWMA3 2A2 2Y2 PWM2
PWMA4 15 5 PWM3
PWMA4 2A3 2Y3 PWM3
PWMA5 17 3 PWM4
PWMA5 2A4 2Y4 PWM4
1
1G
19

GND
2G
B B
MC74HC244 RP1

10
GND_D PWMA5 8
TE22 TE21 PWMA4 7
ZVSPWM2 ZVSPWM1 PWMA3 6
GND_D PWMA2 5
PWMA1 4
PWMA0 3
+3.3V_DSP ZVSPWMA1 2
ZVSPWMA2 1 9

PWMA0 1 2 R15 GREEN LED GND_D

D7 8X5K
300
U5A MC74HC04

PWMA1 3 4 R16 GREEN LED

D8
300 +5V_DSP +3.3V_DSP
U5B MC74HC04
C C

PWMA2 5 6 R17 GREEN LED C4 C39

D9
300 0.1uF 0.1uF
U5C MC74HC04

GND_D GND_D
PWMA3 9 8 R18 GREEN LED
D10 MC74HC244(U5) MC74HC04(U4)
300
U5D MC74HC04

PWMA4 13 12 R19 GREEN LED

+3.3V_DSP D11
300
U5F

14
MC74HC04

R20 GREEN LED

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

PWMA5 11 10 D12

VCC
300 Title

GND
D U5E Output Signal Interface D
MC74HC04

7
Size Number Revision
A 3.0
GND_D Date: 2004-12-27 Sheet of 7 /7
File:
1 2 3 4

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
A A

Freescale Semiconductor
12
9
8
6

11 DIG.2 DIG.3 DIG.4

a DIG.1
7 a a a a
b
4 f b f b f b
c f g b g g g
+5V_LED 2
d
1 c e c e c e c
ee
D19 +5V_LED U8 10 d d d d
f
19 2 5 dp dp dp dp

20
+5V_DSP V+ DIG0 g
U7 11 3
R29 10K DIG1 dp
RELAY 2 18 1N4148 18 6
RELAY 1A1 1Y1 AC_RELAY ISET DIG2 U9
4 16 7
1A2 1Y2 DIG3

VCC
6 14 + C38 1 3 FYQ-3641A
1A3 1Y3 47uF/10V DIN DIG4
8 12 10
1A4 1Y4 DIG5
24 5
B DOUT DIG6 B
11 9 8
2A1 2Y1 DIG7
LEDDATA 13 7 LEDDATA1
LEDDATA 2A2 2Y2
LEDCLK 15 5 LEDCLK1 GND_D 13 14
LEDCLK 2A3 2Y3 CLK SEGA
/LEDEN 17 3 /LEDEN1 16
/LEDEN 2A4 2Y4 SEGB
20
SEGC
1 12 23
1G CS SEGD
19 21
12
9
8
6

GND
2G SEGE
15
SEGF
MC74HC244 9 17 11 DIG.2 DIG.3 DIG.4
GND SEGG a DIG.1

10
GND_D 4 22 7 a a a a
GND SEGDP b
4 f b f b f b
c f g b g g g
GND_D MAX7221 2
d
GND_D 1 c e c e c e c
ee
10 d d d d
f
+5V_LED +5V_LED 5 dp dp dp dp
g
3
dp
U10
C1 C2 FYQ-3641A
0.1uF 0.1uF

GND_D GND_D
C MC74HC244(U7) MC7221(U8) C

Schematics, Rev. 0
D D

Title
LED DISPLAY
Size Number Revision
B 3.0
Date: 2004-12-27 Sheet of 4 /7
File:
1 2 3 4 5 6

Appendix A-7
 1 2 3 4

Appendix A-8
A A

+3.3V_DSP
U6 +3.3VA
B +3.3V_DSP 20 2 DAOUTA TE15 B
VDD FBA DAOUTA
DACDATA 9 3
DACDATA DIN OUTA
12 4 DAOUTB TE16
DOUT OUTB DAOUTB
DACCLK 10 5
C36 DACCLK SCLK FBB
6 +DAREF R28 SET TO 2.7V
0.1uF REFAB
/DACEN 8 15 +DAREF
/DACEN CS REFCD
/RESETD 7 16 DAOUTC TE17 1K
/RESETD CL FBC DAOUTC
14 17
+3.3V_DSP PDL OUTC
GND_D 18 DAOUTD TE18
R27 5.1K OUTD DAOUTD C37
MAX5251(U6) 19
FBD 0.1uF
13 DACTEST TE19
UPO DACTEST
11 1
DGND AGND
TE20
MAX5251BEAP GND_A GND_A
GND_D
GND_A

C C

+3.3VA
+3.3V_DSP
+3.3VA
+3.3V_DSP +3.3VA
+3.3V_DSP
GND_A
GND_D
GND_A
GND_D GND_A
GND_D

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Title
D DIGITAL TO ANALOG CONVERTER D

Size Number Revision

A 3.0
Date: 2004-12-27 Sheet of 3 /7
File:
1 2 3 4

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
PFCMAIN Analog Signal Sample Circuit For PFC Part
POWER ENTRY POWER ENTRY.SCH PFCMAIN.SCH ANALOG SIGNAL SAMPLE(PFC).SCH
INPUT_VOL
INPUTVOL INPUTVOL INPUT_VOL
INPUT_CUR PRIMARY SIDE - PFC RECTIFIER PART
AC1 AC1 INPUTCUR_SAM INPUTCUR_SAM INPUT_CUR
DCBUS_VOL
AC2 AC2 DCBUS DCBUS DCBUS_VOL
J14 INPUTFRQ1
INPUTFRQ1
1 INPUTFRQ2 INPUTCUR_PRO
1 ACINPUT1 INPUTFRQ2 INPUTCUR_PRO
A 2 AC_RELAY PFCDRV A
2 ACINPUT2 AC_RELAY PFCDRV1
+12V_P PFCDRV.SCH +12V_P PONSIGNAL

+12V_P
GNDP
+12V_P PFCDRV2 +12V_P PONSIGNAL
ACINPUT GNDP PFCPWM1 GNDP +5V_P

DCBUS+
DCBUS-
ACIN1 GNDP PFCPWM1 PFCDRV1 ZVSDRV1 GNDP +5V_P
PFCPWM2 -12V_P +3.3VAP INPUTVOL_FRQ
ACIN2 PFCPWM2 PFCDRV2 ZVSDRV2 -12V_P +3.3VAP INPUT_FRQ
INPUTFRQ1 ZVSPWM1 GNDP
INPUTFRQ1 ZVSPWM1 ZVSDRV1 GNDP
INPUTFRQ2 ZVSPWM2 +12V_P
INPUTFRQ2 ZVSPWM2 ZVSDRV2 +12V_P SCIDSP

GNDP
-12V_P

+12V_P

Freescale Semiconductor
AP Power -12V_P SCIDSP.SCH
AP Power.SCH TXD_P +3.3VAP
TXD_P +3.3V_P
RXD_P GNDP
ACIN2 RXD_P GNDP
+12V_P
ACIN1 +12V_P
-12V_P TXD_S +3.3VAS
-12V_P TXD_S +3.3V_S
+5V_P RXD_S GNDS
+5V_P DCDCMAIN RXD_S GNDS
GNDP
GNDP DCDCMAIN.SCH Analog Signal Sample Circuit For DC/DC Part
OUTPUTCUR ANALOG SIGNAL SAMPLE(DCDC).SCH
OUTPUTCUR
DCDCDRV OUTPUT_VOLS
OUTPUTVOL OUTPUTVOL OUTPUT_VOLS DRIVER_44201
DCDCDRV.SCH IND_CURS
INDCUR_S INDCUR_S IND_CURS DRIVER_44201.SCH
PWM1_S
+12V_S PWM1_S PWMA PWMA PWM1_A

GNDP
+12V_S PWM2_S PWM1_A
-12V_S PWM2_S PWMARNT PWMARNT PWM2_A

DCBUS+
-12V_S PWM3_S +5V_S INDCUR_PROS PWM2_A
+5V_S PWM3_S PWMB PWMB +5V_S INDCUR_PRO PWM3_A
+5V_S PWM4_S +3.3VAS PWM3_A
+20V_S PWM4_S PWMBRNT PWMBRNT +3.3VAS PWM4_A
+20V_S PWM5_S GNDS PWM4_A
GNDS PWM5_S PWMC PWMC GNDS +3.3VAS
GNDS PWM6_S +12V_S +3.3VAS
PWM6_S PWMD PWMD +12V_S
GNDP -12V_S
B GNDP -12V_S B
J15
PWMS1 PWMS1
PWM1_A
PWM1_A PWMS2 PWMS2 OUTPUT+ 1
PWM2_A
PWM2_A OUTPUT- 2
PWM3_A

+3.3VAS
GNDS
+12VDRV_S
VCC4
PWM3_A
PWM4_A DCOUTPUT Sec_APC

+12V_S
GNDS
-12V_S
PWM4_A
Sec_APC.Sch
+20V_S
+20V
GNDS
GNDS

GNDS
+12V_S
+20V_S

+3.3VAS
GNDS
-12V_S
SECONARY SIDE - DC/DC CONVERT PART

+12V_S
J16
J17
32A +5V_S 32B +5V_S
32A +5V_P 32B +5V_P
31A GNDS 31B GNDS D57 D55
31A GNDP 31B GNDP R126
30A GNDS 30B GNDS K A
30A GNDP 30B GNDP 2 1
29A 29B 300
29A 29B
28A GNDS 28B GNDS +5V_P 1N4001
28A GNDP 28B GNDP 5V_P DIS
27A 27B U24
27A INPUTCUR_PRO 27B INPUTCUR_PRO
26A INDCUR_PROS 26B INDCUR_PROS 3 2
26A 26B VIN VOUT
25A GNDS 25B GNDS +3.3VAP
25A GNDP 25B GNDP L12
24A 24B 1 +3.3VAP
C 24A PONSIGNAL 24B PONSIGNAL GND +3.3VAP C
23A 23B
23A INPUTVOL_FRQ 23B INPUTVOL_FRQ INPUTCUR_PRO 10uH
22A GNDS 22B GNDS MC33269DT-3.3 + C114
22A GNDP 22B GNDP 47uF
21A PWM5_S 21B
21A PFCPWM1 21B ZVSPWM1 INPUTVOL_FRQ
20A PWM6_S 20B
20A PFCPWM2 20B ZVSPWM2
19A PWM1_S 19B PWM1_S
19A 19B
18A PWM2_S 18B PWM2_S
18A 18B
17A PWM3_S 17B PWM3_S D56

Schematics, Rev. 0
17A 17B D58
16A PWM4_S 16B PWM4_S K A R127 2 1
16A 16B 2 1 12
15A GNDS 15B GNDS 300
15A GNDP 15B GNDP
14A 14B 1N4001
14A AC_RELAY 14B AC_RELAY +5V_S DIS +5V_S
13A GNDS 13B GNDS U25
13A GNDP 13B GNDP
12A GNDS 12B GNDS 3 2
12A GNDP 12B GNDP VIN VOUT
11A TXD_S 11B TXD_S
11A TXD_P 11B TXD_P L13
10A RXD_S 10B RXD_S 1 +3.3VAS
10A RXD_P 10B RXD_P GND +3.3VAS
9A GNDS 9B GNDS
9A GNDP 9B GNDP 10uH
8A GNDS 8B GNDS MC33269DT-3.3 + C115
8A GNDP 8B GNDP 47uF
7A +3.3VAS 7B +3.3VAS
7A +3.3VAP 7B +3.3VAP
6A GNDS 6B GNDS
6A GNDP 6B GNDP
5A GNDS 5B GNDS
5A GNDP 5B GNDP
4A 4B
4A INPUT_VOL 4B INPUT_CUR
3A 3B IND_CURS
3A DCBUS_VOL 3B
2A OUTPUTCUR 2B OUTPUT_VOLS
2A 2B
1A GNDS 1B GNDS
1A GNDP 1B GNDP
D DIP64_S(to power board) D
DIP64_P(to power board)
Title
The Hierarchy System Schematic of Power Board
(To Primary DSC Controller) (To Secondary Side DSC Controller)
Size Number Revision
PRIMARY PFC PART INTERFACE B
SECONDARY DC/DC INTERFACE
Date: 2004-12-27 Sheet of 1 / 12
File:
1 2 3 4 5 6

Appendix A-9
 1 2 3 4 5 6

Appendix A-10
A A

D54 T7
+12V_P 2SD882
2 3
+12V_P C E GNDP
K1 1N4004

B
C113
1 5 0.1u

1
ACRELAY 2 R125 1
2 1 AC_RELAY
GR2-1 300
F4
ACINPUT1 1 2 4 3 AC1
ACINPUT1 1 2 AC1
250V/10A G4W-1112P-US-TV8-HP
R115
B B
ACIN1 500K

FOR AUXILIARY POWER INPUT

ACIN2 R119
12K
AC2
AC2

R116
500K

ACINPUT2
ACINPUT2

C INPUTFRQ1 C
INPUTFRQ2

D D

Title
Power Entry Circuit

Size Number Revision

B

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 2 / 12
File:
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
A A
TE2
Q1 +5VP
D3 7805
L1 1 2 +5V_P
Vin +5V +5V_P
3.3u

GND
MUR420 C13 C20 C21

Freescale Semiconductor
330UF/35V 104 C32

3
220UF/25V 220UF/25V
C37 105 GNDP
D4 Q2 7812
L2 1 2 +12V_P
Vin +12V +12V_P
3.3u

GND
C38 TE3 +12VP
MUR420 C14 C22 C23
330UF/35V 220UF/25V104 C33 TE4 GNDP

3
220UF/25V
TE5 105 GNDP

3
GNDP
+5VS D5
L3 J30
D6
+5V_S 2 1 L4 1
+5V_S +5V Vin 3.3u

GND
MUR420 C15 C39 C24 2
1
3.3u
C132 C131 Q18 MUR420 TR1 5 330UF/35V C25 104 Q4 7912 C34 TE6 -12VP 3
220UF/25V
105 7805 104 C26 C16 15 220UF/25V 3 2 105 -12V_P
220UF/25V TE7 C133 220UF/25V 330UF/35V -Vin -12V -12V_P FAN
6
GNDS
GND

GNDS 16 7 D7 Q3 7812 TE8 +12VS

2 L5 1 2 +12V_S
B Vin +12V +12V_S B
8 3.3u
GND

VR1 P6KE200
9 MUR420 C17 C27 C40 C28
330UF/35V 104 C35
3

220UF/25V 220UF/25V
D10 10 105 GNDS
GNDS
1 11 D8
L6 J29
3

3
D11 BYV26C 12 3.3u TE9 1
F1 13 MUR420 C18 C29 -12VS 2
1

C30 C41

K
ACIN1 2 4 C43 4 330UF/35V
TE40 C36 3
ACIN1 J1 C C 220UF/25V 104 220UF/25V
47uF/400V 14 D9 +20VS 3 2 105 -12V_S

A
1 2A250VAC L7 -Vin -12V -12V_S FAN
1 17 +20V_S
2
GND

2 C44 2KBB40 3.3u

1
0.1UF/250VAC C19 +20V_S
AC APC 18 MUR420 C31 C42 Q5
ACIN2 APC TRANSFORMER 330UF/35V 7912
ACIN2 220UF/25V 104
C10 GNDS

R35
0.1uF R36
2k
U3 200/0.5W
D12 4 1
C A

1N4148 3 2
E K R33
NEC2501
C 100K C
K

C11 0.1uF
U4
1 C12
DRAIN 0.1uF
C45 U5 C C
2 2 1 R37
SOURCE TL431
6.2
A

Schematics, Rev. 0
3 47uF R38
CONTRO 10k
TOP223YAI
C46

1.6nF/450VAC

D D

Title
Power Board Auxiliary Power Circuit

Size Number Revision

B
Date: 2004-12-27 Sheet of 3 / 12
File:
1 2 3 4 5 6

Appendix A-11
 1 2 3 4 5 6

Appendix A-12
A A

D41

1N4001

U16 C88
TE23
+12V_P 1 8
VCC VB ZVSDRV1
0.1uF 6.8/0.5W
ZVSPWM1 C89 2 7 R103 ZVSDRV1
ZVSPWM1 0.1uF IN HO ZVSDRV1
3 6 GNDP
ERR CS
D42
R99 C98
1K 20pF 4 5
COM VS
1N4001
C97 IR2125
220UF/25V U20 C90
+12V_P 1 8 TE24
+12V_P VCC VB PFCDRV1
0.1uF
PFCPWM1 C91 2 7 R104 6.8/0.5W PFCDRV1
B PFCPWM1 0.1uF IN HO PFCDRV1 B
3 6 GNDP
ERR CS
R100 C96
1K 10pF 4 5 TE25
COM VS
PFCDRV1RNT
IR2125
GNDP
GNDP

D43

1N4001

U21 C92
TE26
+12V_P 1 8
VCC VB ZVSDRV2
0.1uF 6.8/0.5W
ZVSPWM2 C93 2 7 R105 ZVSDRV2
ZVSPWM2 0.1uF IN HO ZVSDRV2
D44 3 6 GNDP
ERR CS
C C
R101 C99
1N4001 1K 20pF 4 5
COM VS
U22 C94 IR2125
TE27
+12V_P 1 8
VCC VB PFCDRV2
0.1uF 6.8/0.5W
PFCPWM2 C95 2 7 R106 PFCDRV2
PFCPWM2 0.1uF IN HO PFCDRV2
3 6 GNDP
ERR CS
R102 C100
1K 20pF 4 5
COM VS
IR2125

D D

Title

Size Number Revision

B

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 4 / 12
File:
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
A A

D45 DSEP60-06A
1 2 1 2
1 2 1 2
L8 250u
F2 250V/10A C104
R107

Freescale Semiconductor
10/3W
0.003U/2K

D46 DSEP60-06A
1 2 1 2 1 2 DCBUS+
1 2 1 2 KA DCBUS+
L9 250u
F3 250V/10A C105
R108 D47

2
D48 DSEP8-06B
10/3W
DSEP8-06B 0.003U/2K

K A
1
R109
C106 560K
470nF/275V
R110
B 1 2 1 2 560K B
1 2 1 2
L10 8u L11 8u
R111

2
1
2
1
AC1 470K/2W
AC1
J26 J27

2
2
1

R113 ZVSJP2
D49 ZVSJP2 D50 C107 C108
390K C109 C110 J20
1 2

S
S

D
D
PFCDRV1 PFCDRV2
1 1 470uF 470uF
2

PFCDRV1 G 470p(op) PFCDRV2 G 470p(op) 1

MUR460 MUR460

3
3
Q14 Q15 2
R114

4
TE29 IRFPC60 IRFPC60 390k DCBUS
D51 INPUTVOL R112

2
2

C
R117 R118
3 1 470K/2W
K A 220 220
INPUTVOL

C
S
S

D
D
ZVSDRV1 ZVSDRV2 DCBUS
1 1
ZVSDRV1 G ZVSDRV2 G TE30 DCBUS

2
3
3

IR25XB08H Q16 Q17

R120 R122 C111
13K 15K IRF830B IRF830B
220p INPUTVOL
R123 R121
D52 D53 C103
Input voltage sampling 15K 13K
MUR260 MUR260 220pF
Sended to primary controller's
C board as ADC input signal TE28 C
AC2 GNDP
AC2
U23
HDC-15LX
6 5 GNDP
DCBUS-
DCBUS
1 2

Schematics, Rev. 0
+12V_P -12V_P

3
4
LEM PFC output voltage sampling
INPUTCUR_SAM Sended to primary controller's
INPUTCUR board as ADC input signal
+12V_P
TE31 R124
C112
300 +12V_P
Input current sampling +12V_P
Sended to primary controller's 10nF C101
board as ADC input signal 0.1uF
GNDP
GNDP

C102

0.1uF
D -12V_P D
-12V_P
Title
PFC Main Circuit
-12V_P
Size Number Revision
B
Date: 2004-12-27 Sheet of 5 / 12
File:
1 2 3 4 5 6
-12V_P

Appendix A-13
 1 2 3 4 5 6

+5V_P

+5V_P
+5V_P
+12V_P +5V_P

Appendix A-14
0.1uF Cu5 0.1uF
GNDP Cu6
GNDP
-12V_P
A A
-12V_P
Input voltage sampling

11
+3.3VAP
R15 3
INPUTVOL R29
10K 1 INPUT_VOL +3.3VAP
INPUT_VOL +3.3VAP
[email protected] 2 TL074 200
U17A

4
+12V_P +12V_P

-12V_P -12V_P
+12V_P

R16 +3.3VAP
10K R13
1M
R18 R17
10K DCBUS 2 R19 1 10
INPUTFRQ1 DCBUS 2 1 R20
10K 10K 8 DCBUS_VOL
12 C5 DCBUS_VOL
R21 [email protected] 9 TL074 10K
B 14 5 U19B 1000pF B
13 TL074 7 R30 U17C
R22 10K INPUT_FRQ
U17D 6 1.8K
INPUTFRQ2 LM293 C6
10K
1000pF
C7
R23 1000pF
10K

2 R28 1 5
INPUTCUR_SAM 2 1
100 7 INPUT_CUR
INPUT_CUR
6 TL074
100mV@20A
U17B
C9 +12V_P TE1
1n PONSIG
POWER ON SWITCH
C C
3 S1
+3.3VAP NO R24
1 PON SIGNAL
COMMON PONSIGNAL
+5V_P 2
A

NC 10k
D2 R31
R14 POWER ON DIS
3.6k
2 1

R25
10K Input current protect

8
1M
K

3 U19A
1
INPUTCUR_PRO
2 R32
R26 LM293 INPUTCUR_PRO 2k
100K

4
1 3

2
R27
100K
C8 0.1uF

D D
+5V_P
Title
Analog Signal Sample Circuit For Primary Side (1)

Size Number Revision

B

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 6 / 12
File
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
A A

Freescale Semiconductor
COMMUNICATION BETWEEN TWO DSCs

+3.3V_P
TE32
+3.3V_P
+5V_P

B R128 B
300
TE33 TE34
RXD_P +3.3V_S TXD_S
TE35
U26 R129 +5V_S
RXD_P
RXD_P +3.3V_S
300
TXD_S
TXD_S
TE36 NEC2501
TXD_P TE37
RXD_S
+3.3V_P U27
R130 RXD_S
RXD_S
300
TXD_P
TXD_P R131
NEC2501 TE38 300
GND_S
TE39
GNDP
GND_P
GNDS
GND_P GND_S +3.3V_S

C C

Schematics, Rev. 0
D D

Title
Serial Communication Interface Between Two DSC System

Size Number Revision

B
Date: 2004-12-27 Sheet of 10 / 12
File:
1 2 3 4 5 6

Appendix A-15
 1 2 3 4 5 6

A A

Appendix A-16
+12VDRV_S +12VDRV_S C51 220uF/25V

+
+12VDRV_S
+12VDRV_S TE12

2
+12VDRV_S PWMA
Cu7 Q6 D17

C
0.1uF 12SD882
GNDS B C47 0.1uF PWMA
PWM1_A

E
J2 BYV26C
C55 D21

PWM1_A
3
1 1N4744
1 2 R49
PWM1_S 2 12

2
3 51/0.5W
1uF
CON3 PWM1 Q10 R50 +20V_S
B B

E
2SB772
1 3 4 51/0.5W R63
B 34 3.6k VCC4

C
R39 T1 D13
1K TRANS3 TE13 D22

3
PWMARNT 1N4744
5V
PWMARNT R45
U6 +20V_S
+12VDRV_S C52 220uF/25V PWMS1
1 8

+
+12VDRV_S VDD VDD 10
C59 C60 0.47uF C63
PWMC PWM5_A 0.1uF 2 7 R57
PWM5_S INPUT OUTPUT 0.1uF
Q7 D18 TE14
J6 3 6 4.7k
2SD882 NC OUTPUT
GNDS C48 0.1uF PWMC
1
PWM1 4 5 GNDS
2 BYV26C GND GND
PWM2 D23
3 C56
PWM3 1N4744 TC4420
4
PWM4 PWM2_A R51
5
PWM5_A PWM2
6 J4 1uF 51/0.5W
PWM6_A R52
7 Q11

PWM2_A
1 R64
R41 2SB772 51/0.5W
CON7 PWM2_S 2 3.6K
3 1K
T2
CON3 TRANS3 TE10 D24
GNDP 1N4744
U10
GNDP
3 2
A G +12VDRV_S C53 220uF/25V
5 4

+
B H +12VDRV_S
7 6 TE15
PWM3_A C I

2
9 10 PWMB
J3 D J
11 12
E K Q8 D19

PWM3_A
C
1 14 15
F L 12SD882 C49
PWM3_S 2 13 16 B 0.1uF PWMB D15
NC NC

E
3 1 8
VCC GND BYV26C +20V_S
C CON3 C57 D25 C

3
PWM3 CD4049 5V
1N4744
CD4049
+12VDRV_S R53 R46
U7 +20V_S
R40 1uF PWMS2
51/0.5W 1 8 10
1K Q12 R54 C61 VDD VDD C62 C64
2SB772 R65 0.47uF
51/0.5W 3.6K PWM6_A 0.1uF 2 7 R58
PWM6_S INPUT OUTPUT 0.1uF
T3
TE16 D26 3 6 4.7k
TRANS3 NC OUTPUT
PWMBRNT 1N4744
4 5 GNDS
GND GND
PWMBRNT TC4420
+12VDRV_S C54 220uF/25V

+
+12VDRV_S
TE17
PWMD
Q9 D20
C50
2SD882 0.1uF PWMD
PWM4
BYV26C
PWM4_A C58 D27
R42 1N4744
J5 R55
1K
1uF

PWM4_A
1 51/0.5W
Q13 R56
PWM4_S 2 R66
2SB772
3 51/0.5W 3.6K
CON3 T4
TRANS3 TE11 D28
GNDP 1N4744

GNDP
GNDP

D D

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Title
DC/DC Convert Drive Circuit

Size Number Revision

C
Date: 2004-12-27 Sheet of 7 / 12
File:

1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
DCDC output current OUTPUTCUR
OUTPUTCUR
sampling
Sended to secondary C65
1.5u
DCBUS+ controller's board as
DCBUS+
ADC input signal
A TE19 R67 57k A
S2 C67
IRFPC60 OUTCUR
560pF/2kV
S3

3
4
LEM
PWMA PWMB IRFPC60
PWMA PWMB
1 2
+12V_S -12V_S

Freescale Semiconductor
Lf1
1 2 5 6
1 2 OUTPUT+
U11

2
PWMARNT 12u
C73 S6 HDC-15LX
Cr1 3000P/2KV

S
D
0.1uF/275VAC R68
J19 T5 1
PWMARNT PWMS1 G
57k TE20 J7

3
1 IRFP264
C69 OUTPUTVOL
2 C70 1
2u/450V R71
DCBUS 2u/450V C72 2200uF/100V C71 2
1.5K(2W) OUTPUTVOL

3
R69 R70 R146 OUTPUTVOL 3
20/3W20/3W 2.2u/65V C74 2.2u/65V 2K FAN
C66

3
2 DCDC output voltage sampling
PWMBRNT TRANSFORMER15 S7 1 R72 1.5u
PWMBRNT G PWMS2
2K TE18 Sended to secondary controller's

2
4
S
D
1
GNDS
board as ADC input signal
T6 IRFP264 Lf2

12
34
2
B (500:1) 1 2 B
1 2 OUTPUT-
12u

1
3
S4 C68

2
IRFPC60 560pF/2kV S5 1N4148

S
D
1N4148 D29 PFC CONCTROLLER SAMPLE 2-3
PWMC PWMD
1 D30
PWMC PWMD G 2 1 2 1
KA KA

3
IRFPC60
2 1 2 1
KA KA
DCDC CONCTROLLER SAMPLE 1-2
1N4148 D31 1N4148 D32
GNDP
GNDP

TE21 R73 500

INDCUR
TE22
R74 1.6K
C75 220pF GNDS

J8

2
3
1
J9 GNDJUMPER

2
3
1
OUTJUMPER

C INDCUR_P INDCUR_S C
INDCUR_S

DCDC induction DCDC induction current

current sampling sampling
Sended to primary Sended to secondary

Schematics, Rev. 0
controller's board as controller's board as
ADC input signal ADC input signal

+12V_S

+12V_S
+12V_S
+12V_S -12V_S

Cu8 0.1uF Cu9 0.1uF

GNDS
D GNDS D

Title
DC/DC CONVERT MAIN CIRCUIT
-12V_S
Size Number Revision
-12V_S B
-12V_S
Date: 2004-12-27 Sheet of 8 / 12
File:
1 2 3 4 5 6

Appendix A-17
 1 2 3 4 5 6

-12V_S

11

Appendix A-18
3
1 IND_CURS
IND_CURS
2 TL074
U18A

4
A A

INDCUR_S +3.3VAS
INDCUR_S +12V_S

+5V_S Output voltage sampling

R1 R2
Input current protect OUTPUTVOL R3 12
10K R4

8
1M 14 OUTPUT_VOLS
10K OUTPUT_VOLS
13 TL074 1K
3 U46A
1 INDCUR_PRO C1 1000pF U18D
INDCUR_PRO
2 LM293
R5
100K

4
R6
100K
C2 0.1uF

B B

+5V_S

DCDC output voltage

sampling
Sended to primary
+12V_PP controller's board as
ADC input signal
7

R10
4 U2 5 U1
10M R7 3
100K 6 OUTPUTVOL_P
3 6 2

10 2 7 LM101A
4
1
5

OUTPUTVOL 5 8
OUTPUTVOL R8
7 9 TL074
6 TL074 R11 1 8
100K U18C
U18B 100 HCNR201 -12V_PPC3
C C
R96.8pF
DCDC induction current J28
D1 100K
2 1 sampling DCDC induction +12V_PP 1
KA current sampling
Sended to secondary -12V_PP 2
OUTPUTVOL_P
1N4148 controller's board as Sended to primary 3
controller's board as 4
ADC input signal R12 5
ADC input signal 47K 6
C4
10pF
CON6

+5V_S +5V_S

+3.3VAS +3.3VAS
+12V_PP
+12V_S +5V_S +5V_S
GNDS GNDS Cu3 0.1uF
Cu1 0.1uF Cu2 0.1uF
Cu4
+12V_S +12V_S 0.1uF
-12V_PP
-12V_S
D -12V_S -12V_S D

Title
Analog Signal Sample Circuit For DC/DC Part

Size Number Revision

B

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 9 / 12
File:
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
 1 2 3 4 5 6

Preliminary
J18
A A
+20V 1
JUMP FOR SEC-APC :
+20V 2
1-2: SEC-APC WORK
GNDS 3
2-3: SEC-APC DOES NOT WORK VD1
CON3 R135
120
+20V MUR120 R138

Freescale Semiconductor
C118 1nF 4.7K
TR2 3 C122 VD5
C119 R133 1 R141 100uF/25V 1N4748A
1K 4 470
R132 1nF 2 5

C126
10K
6

200uF/36V
D59 C123 VD2 MUR120 7
1 8 C117 C116
COMP VREF
8
2 7 0.1uF0.1uF 100uF/25V 2611
VFB VCC VT1 VD3
3 6 R144 IRF530 R136 J22
ISENSE OUTPUT
10 120 1
4 5 MUR120 R139
RT/CT GROUND C120 1nF 4.7K 2
C129 UC3844 C124 3
B 680pF R134 R142 100uF/25V 4 B
470 VD6 5
Comment: 1K 6
C130 1N4748A

C127
470pF R145 CON6
1.5/1W

200uF/36V
VD4
R137
120
MUR120
C121 1nF R140
C125 4.7K
100uF/25V VD7
R143 1N4748A
470

C128
200uF/36V
C C

Schematics, Rev. 0
D D

Title
APC FOR SECONDARY DRIVER CIRCUIT
Size Number Revision
B
Date: 2004-12-27 Sheet of 12 / 12
File:
1 2 3 4 5 6

Appendix A-19
 1 2 3 4 5 6
+20V_1

D33

+20V_4

Appendix A-20
500 5V
R75
1K U12 +20V_1 R79 D34
+3.3VAS +3.3VAS
R83 1 8 10
D35 C76 VDD VDD C77 C84 J10
A 0.47uF A
0.1uF 2 7 R87 1 500 5V
DIP1 INPUT OUTPUT 0.1uF
1 8 2 R76
5.1K 3 6 4.7k 3 1K U13 +20V_4 R80
R91 2 5V NC OUTPUT
+3.3VAS 7 R95 R84 1 8 10
CON3 D36 C78 VDD VDD C79 C85 J11
300 6 4 5 0.47uF
3 GND GND 0.1uF 2 7 R88 1
DIP2 INPUT OUTPUT 0.1uF
PWM1_A
4 5 GND_1 TC4420 GND_1 2
PWM1_A 5.1K 3 6 4.7k 3
R92 5V NC OUTPUT
2611 +3.3VAS R96
CON3
GND_1 +20V_2 300 4 5
GND GND
GND_4 TC4420 GND_4
D37 PWM4_A
PWM4_A
2611
GND_4
500 5V
R77
1K U14 +20V_2 R81
R85 1 8 10
D38 C80 VDD VDD C81 C86 J12
0.47uF
0.1uF 2 7 R89 1
DIP3 INPUT OUTPUT 0.1uF
1 8 2
+3.3VAS 5.1K 3 6 4.7k 3
B R93 2 5V NC OUTPUT B
7 R97
CON3
300 6 4 5
PWM3_A
3 GND GND
PWM3_A 4 5 GND_2 TC4420 GND_2

2611
GND_2
+20V_3

D39

500 5V
R78
1K U15 +20V_3 R82
R86 1 8 10
D40 C82 VDD VDD C83 C87 J13
0.47uF
0.1uF 2 7 R90 1
DIP4 INPUT OUTPUT 0.1uF 2
5.1K 3 6 4.7k 3
R94 5V NC OUTPUT
+3.3VAS R98
CON3
300 4 5
PWM2_A GND GND
C C
GND_3 TC4420 GND_3
PWM2_A J21
2611 +20V_1 1
GND_3 2
GND_1 3
CON3
J23
+20V_2 1
2
GND_2 3
CON3
J24
+20V_3 1
2
GND_3 3
CON3
J25
+20V_4 1
2
D GND_4 3 D

CON3 Title
DC/DC DRIVER CIRCUIT FOR SECONDARY
Size Number Revision
B

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Date: 2004-12-27 Sheet of 11 / 12
File:
1 2 3 4 5 6

Preliminary
Freescale Semiconductor
Appendix B
SMPS Bill of Materials

Controller Board

Designator Comment Footprint Description Library Reference Quantity

C1—C8, 0.1µF 1206C Capacitor CAP 18

C10—C14,
C16, C17,
C36, C37,
C39

C9, C15, 47µF/10V 4025T Capacitor CAPACITOR POL 4

C18, C38

C19—C21, 0.1µF 1206C Capacitor CAPACITOR 6

C24, C28,
C31

C22, C23, 2.2µF 1206C Capacitor CAPACITOR 4

C25, C29

C26 100pF 1206C Capacitor CAPACITOR 1

C27 0.001µF 1206C Capacitor CAPACITOR 1

C30, 2.2nF 1206C Capacitor CAPACITOR 5

C32—C35

D1 Green LED 1808LED LED 1

D2 FM4001 3216d Diode FM4001 1

D3, D4, 1N4148 3216d Diode 1N4148 5

D19, D21,
D22

D5, D6 Red LED 1808LED LED 2

D7—D12 Green LED 1808LED LED 6

D13—D18 BAV99 SOT-23 Double Diode BAV99 6

D20 1N4733 3216D Zener Diode ZENER3 1

J1 DIN64 DIN64RA DIN64 1

J2 JTAG IDC14 HEADER 7x2 1

J3 SCI TAG IDC8 HEADER 4x2 1

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-1
Preliminary
 Controller Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

J4 I2C PORT SIP2 Connector CON2 1

J5 AD SET IDC8 Connector CON8 1

J6 DA-TAG IDC8 Header 4x2 1

L1—L3 1µh 3225L INDUCTOR1 3

R1, R2 5.6K 1206R RES2 2

R3 300 1206R RES2 1

R4—R8, 10K 1206R RES2 8

R11, R13,
R29

R9, R10, 300 1206R RES2 8

R15—R20

R12, R30 47K 1206R RES2 2

R14 1K 1206R RES2 1

R21—R26 100 1206R RES2 6

R27 5.1K 1206R RES2 1

R28 1K VR Potentiometer POT2 1

RP1 8 x 5K SIP9 RESPACK8 1

S1 RESET KG SW-PB 1
PUSHBUTTON

TE1 GND_D SIP-1 TESTPORT 1

TE2 +3.3V SIP-1 TESTPORT 1

TE3 PFCPWM1 SIP-1 TESTPORT 1

TE4 PFCPWM2 SIP-1 TESTPORT 1

TE5 PWM1 SIP-1 TESTPORT 1

TE6 PWM2 SIP-1 TESTPORT 1

TE7 PWM3 SIP-1 TESTPORT 1

TE8 PWM4 SIP-1 TESTPORT 1

TE9 IPUT_VOL SIP-1 TESTPORT 1

TE10 INPUT_CUR SIP-1 TESTPORT 1

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-2 Freescale Semiconductor
Preliminary
 Controller Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

TE11 DCBUS SIP-1 TESTPORT 1

TE12 IND_CUR SIP-1 TESTPORT 1

TE13 OUTPUT_VOL SIP-1 TESTPORT 1

TE14 OUTPUT_CUR SIP-1 TESTPORT 1

TE15 DAOUTA SIP-1 TESTPORT 1

TE16 DAOUTB SIP-1 TESTPORT 1

TE17 DAOUTC SIP-1 TESTPORT 1

TE18 DAOUTD SIP-1 TESTPORT 1

TE19 DACTEST SIP-1 TESTPORT 1

TE20 GND_A SIP-1 TESTPORT 1

TE21 ZVSPWM1 SIP-1 TESTPORT 1

TE22 ZVSPWM2 SIP-1 TESTPORT 1

TE23 GNDA SIP-1 TESTPORT 1

U1 MC33629DT-3.3 SO-8 MC33629DT-3.3 1

U2 MC74HC00 SO-14 Quad 2-IN Pos MC74F00 1

Nand G

U3 56F8323 LQFP64 MC56F8323 56F8323 1

U4 MC74HC244 SO20-300 74LS244 1

U5 MC74HC04 SO-14 Hex Inverters MC74F04 1

U6 MAX5251BEAP SSOP20 MAX5251BEAP 1

U7 MC74HC244 SO20-300 74LS244 1

U8 MAX7221 SOL-24 MAX7221 1

U9, U10 FYQ-3641A LG3641AH 7-SEG 2

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-3
Preliminary
 Power Board

Designator Comment Footprint Description Library Reference Quantity

C1, C5—C7 1000pF RAD0.2 Capacitor CAP 4

C2, C8, 0.1µF RAD0.2 Capacitor CAPACITOR 42

C10—C12,
C47—C50,
C59—C62,
C76—C83
C88—C95,
C101, C102,
C116, C117,
Cu1—Cu9

C3 6.8pF RAD0.2 Capacitor CAP 1

C4 10pF RAD0.2 Capacitor CAP 1

C9 1n RAD0.2 Capacitor CAP 1

C13—C19 330µF/35V CAP RB5/10 ELECTRO 7

C20—C31 220µF/25V RB3/8 ELECTRO 12

C32—C36, 105pF RAD0.2 CAP 6

C132

C37—C42, 104pF RAD0.2 CAP 7

C133

C43 47µF/400V RB10/22.4 ELECTRO 1

C44 0.1µF/250VAC RAD15/18/6 Capacitor CAP 1

C45 47µF RB2.5/5 ELECTRO2 1

C46 1.6nF/450VAC RAD0.4 Capacitor CAP 1

C51—54 220µF/25V RB3/8 Capacitor CAPACITOR POL 4

C55—C58 1µF RAD0.2 Capacitor CAP 4

C63, C64, 0.47µF RAD0.2 Capacitor CAPACITOR 6

C84—C87

C65, C66 1.5µ RAD0.2 Capacitor CAP 2

C67, C68 560pF/2kV RAD0.3 Capacitor CAP 2

C69, C70 2µ/450V RAD27/30/14 Capacitor CAP 2

C71, C72 2.2µ/65V RAD10/13/6 Capacitor CAP 2

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-4 Freescale Semiconductor
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

C73 3000P/2KV RAD0.3 Capacitor CAP 1

C74 2200µF/100V RB10.5/30 Electrolytic ELECTRO1 1

Capacitor

C75, C103 220pF RAD0.2 Capacitor CAP 2

C96 10pF RAD0.2 Capacitor CAP 1

C97, C131 220µF/25V RB3/8 ELECTRO 2

C98—C100 20pF RAC0.2 Capacitor CAP 3

C104, C105 0.003µ/2K RAD10/13/6 Capacitor CAP 2

C106 470nF/275V RAD22/26/9 ELECTRO 1

C107, C108 470µF RB10/35 Capacitor CAPACITOR 2

C109, C110 470p(op) RAD0.2 Capacitor CAP 2

C111 220p RAD0.2 Capacitor CAP 1

C112 10nF RAD0.2 Capacitor CAP 1

C113 0.1µ RAD0.2 Capacitor CAP 1

C114, C115 47µF RB2.5/5 Capacitor CAPACITOR POL 2

C118—C121 1nF RAD0.2 CAP 4

C122—C125 100µF/25V RB3/8 ELECTRO 4

C126—C128 200µF/36V RB3/8 ELECTRO 3

C129 680pF RAD0.2 CAP 1

C130 470pF RAD0.2 CAP 1

Cr1 0.1µF/275VAC RAD15/18/6 Capacitor CAP 1

D1, D12, 1N4148 DIODE0.4 Diode DIODE 6

D29—D32

D2 POWER ON DIS LEDA LED 1

D3—D9 MUR420 DIODE0.5 DIODE1 7

D10 BYV26C DIODE0.4 DIODE1 1

D11 2KBB40 2KBB40 Full Wave Diode Bridge1 1

Bridge

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-5
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

D13, D15, 5V DIODE0.4 Zener Diode ZENER3 10

D33—D40

D17—D20 BYV26C DIODE0.4 DIODE2 4

D21—D28 1N4744 DIODE0.4 Zener Diode ZENER3 8

D41—D44 1N4001 DIODE0.4 Diode DIODE 4

D45, D46 DSEP60-06A TO247AD DIODE1 2

D47, D48 DSEP8-06B TO220AC DIODE1 2

D49, D50 MUR460 DIODE0.5 DIODE1 2

D51 IR25XB08H IR25XB Full Wave Diode Bridge1 1

Bridge

D52, D53 MUR260 D-E DIODE1 2

D54 1N4004 CASE 267-03 DIODE1 1

D55, D56 1N4001 DIODE0.4 Diode FM4001 2

D57 5V_P DIS LEDA LED 1

D58 +5V_S DIS LEDA LED 1

D59 UC3844 DIP8 UC3844 1

DIP1—DIP4 HCPL2611 DIP8 OPTOISO3 4

F1 2A250VAC FUSE20/5/7 D-FOR3.SCH_5A250V_116 1

F2—F4 250V/10A FUSE20/5/7 Fuse FUSE1 3

J1 AC APC CON5/3.96 Connector CON2 1

J2—J5, CON3 SIP3 Connector CON3 13

J10—J13,
J18, J21,
J23—J25

J6 CON7 SIP7 Connector CON7 1

J7 FAN CON3/2.54 Connector CON3 1

J8 GNDJUMPER SIP3 CON3R 1

J9 OUTJUMPER SIP3 CON3R 1

J14 ACINPUT CON5/3.96 Connector CON2 1

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-6 Freescale Semiconductor
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

J15 DCOUTPUT OUTTAG Connector CON2 1

J16 DIP64_S DIN64RA-CON DIN64 1

J17 DIP64_P DIN64RA-CON DIN64 1

J19, J20 DCBUS CON5/3.96 Connector CON2 2

J22 CON6 SIP6 Connector CON6 1

J26, J27 ZVSJP2 CON2/3.96 Connector CON2 2

J28 CON6 SIP4 Connector CON6 1

J29, J30 FAN CON3/2.54 Connector CON3 2

K1 G4W-1112P-US- GR2L-1 RELAY-SPDT(1C) 1

TV8-HP

L1—L7 3.3µ IND 3.3µ INDUCTOR1 7

L8, L9 250µ CORE EI33 INDUCTOR IRON 2

L10, L11 8µ IND-EE25.4 INDUCTOR IRON 2

L12, L13 10µH AXIAL0.4 INDUCTOR 2

Lf1, Lf2 12µ IND-EI33 INDUCTOR 2

Q1, Q18 LM7805 TO220V Component_1 2

Q2, Q3 LM7812 TO220V 7812 2

Q4, Q5 LM7912 TO220V 7912 2

Q6—Q9 2SD882 882 NPN Transistor NPN 4

Q10—Q13 2SB772 772 PNP Transistor PNP 4

Q14, Q15 IRFPC60 TO247AC MOSFET N 2

Q16, Q17 IRF830B TO220AB MOSFET N 2

R1 1M AXIAL0.4 RES2 1

R2, R3, 10K AXIAL0.4 RES2 13

R15—R23,
R25, R132

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-7
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

R4, 1K AXIAL0.4 RES2 11

R39—R42,
R99—R102,
R133, R134

R5, R26, 100K VRESLV RES-VRAU 3

R33

R6—R9 100K AXIAL0.4 RES2 4

R10 10M AXIAL0.4 RES2 1

R11 100 Ohm AXIAL0.4 RES2 1

R12 47K VRESLV RES-VRAU 1

R13, R14 1M AXIAL0.4 RES2 2

R24, R38 10k AXIAL0.4 RES2 2

R27 100K AXIAL0.4 RES2 1

R28 100 Ohm AXIAL0.4 RES2 1

R29 200 Ohm AXIAL0.4 RES2 1

R30 1.8K AXIAL0.4 RES2 1

R31 3.6k AXIAL0.4 RES2 1

R32 2k AXIAL0.4 RES2 1

R35 2k AXIAL0.4 RES2 1

R36 200/0.5W AXIAL0.5 RES2 1

R37 6.2 Ohm AXIAL0.4 RES2 1

R45 10 Ohm AXIAL0.4 RES1 1

R46 10 Ohm AXIAL0.4 RES1 1

R49—R56 51/0.5W AXIAL0.5 RES1 8

R57, R58, 4.7k AXIAL0.4 RES1 6

R87—R90

R63 3.6k AXIAL0.4 RES1 1

R64—R66 3.6K AXIAL0.4 RES1 3

R67, R68 56k AXIAL0.4 RES2 2

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-8 Freescale Semiconductor
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

R69, R70 20/3W R2WV RES2 2

R71 1.5K(2W) R2WV RES2 1

R72 2K AXIAL0.4 RES2 1

R73 500 Ohm AXIAL0.4 RES2 1

R74 1.6K AXIAL0.4 RES2 1

R75—R78 500 Ohm AXIAL0.4 RES1 4

R79—R82 10 Ohm AXIAL0.4 RES1 4

R83—R86 1K AXIAL0.4 RES1 4

R91—R94 300 Ohm AXIAL0.4 RES1 4

R95—R98 5.1K AXIAL0.4 RES1 4

R103—R106 6.8/0.5W AXIAL0.5 RES2 4

R107, R108 10/3W R2WV RES2 2

R109, R110 560K AXIAL0.4 RES2 2

R111, R112 470K/2W R2WV RES2 2

R113 390K AXIAL0.4 RES2 1

R114 390k AXIAL0.4 RES2 1

R115, R116 500K AXIAL0.4 RES2 2

R117, R118 220 Ohm AXIAL0.4 RES2 2

R119 12K AXIAL0.4 RES2 1

R120, R121 13K AXIAL0.4 RES2 2

R122, R123 15K AXIAL0.4 RES2 2

R124—R131 300 Ohm AXIAL0.4 RES2 8

R135—R137 120 Ohm AXIAL0.4 RES2 3

R138—R140 4.7K AXIAL0.4 RES2 3

R141—R143 470 Ohm AXIAL0.4 RES2 3

R144 10 Ohm AXIAL0.4 RES2 1

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-9
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

R145 1.5/1W R2WV RES2 1

R146 2K VRESLV RES-VRAU 1

S1 POWER ON CON3/2.54 SW SPDT 1

SWITCH

S2—S5 IRFPC60 TO247AC MOSFET N 4

S6, S7 IRFP264 TO247AC MOSFET N 2

T1—T4 TRANS3 DRVTRAN TRANS3 4

T5 TRANSFORMER15 TRAN-EI40 TRANSFORMER15 1

T6 (500:1) CURTRAN TRANS3 1

T7 2SD882 882 NPN Transistor NPN 1

TE1 PONSIG SIP-1 TESTPORT 1

TE2 +5VP SIP-1 TESTPORT 1

TE3 +12VP SIP-1 TESTPORT 1

TE4 GNDP SIP-1 TESTPORT 1

TE5 +5VS SIP-1 TESTPORT 1

TE6 -12VP SIP-1 TESTPORT 1

TE7 GNDS SIP-1 TESTPORT 1

TE8 +12VS SIP-1 TESTPORT 1

TE9 -12VS SIP-1 TESTPORT 1

TE10, TE11, GNDP SIP-1 TESTPORT 3

TE28

TE12 PWMA SIP-1 TESTPORT 1

TE13 PWMARNT SIP-1 TESTPORT 1

TE14 PWMC SIP-1 TESTPORT 1

TE15 PWMB SIP-1 TESTPORT 1

TE16 PWMBRNT SIP-1 TESTPORT 1

TE17 PWMD SIP-1 TESTPORT 1

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-10 Freescale Semiconductor
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

TE18, TE22 GNDS SIP-1 TESTPORT 2

TE19 OUTCUR SIP-1 TESTPORT 1

TE20 OUTPUTVOL SIP-1 TESTPORT 1

TE21 INDCUR SIP-1 TESTPORT 1

TE23 ZVSDRV1 SIP-1 TESTPORT 1

TE24 PFCDRV1 SIP-1 TESTPORT 1

TE25 PFCDRV1RNT SIP-1 TESTPORT 1

TE26 ZVSDRV2 SIP-1 TESTPORT 1

TE27 PFCDRV2 SIP-1 TESTPORT 1

TE29 INPUTVOL SIP-1 TESTPORT 1

TE30 DCBUS SIP-1 TESTPORT 1

TE31 INPUTCUR SIP-1 TESTPORT 1

TE32 +5V_P SIP-1 TESTPORT 1

TE33 RXD_P SIP-1 TESTPORT 1

TE34 TXD_S SIP-1 TESTPORT 1

TE35 +5V_S SIP-1 TESTPORT 1

TE36 TXD_P SIP-1 TESTPORT 1

TE37 RXD_S SIP-1 TESTPORT 1

TE38 GND_S SIP-1 TESTPORT 1

TE39 GND_P SIP-1 TESTPORT 1

TE40 +20VS SIP-1 TESTPORT 1

TR1 APC TRAN-EI33-2 TRANSFORMER 8 1

TRANSFORMER

TR2 2611 TRAN-EI25 TRANSFORMER 5 1

U1 LM101A DIP8 741 1

U2 HCNR201 DIP8EXB HCNR201 1

U3 NEC2501 DIP4 OPTOISO1 1

SMPS Bill of Materials, Rev. 0

Freescale Semiconductor Appendix B-11
Preliminary
 Power Board (Continued)

Designator Comment Footprint Description Library Reference Quantity

U4 TOP223YAI TO-220 D-FOR3.SCH_TOP_202 1

U5 TL431 TL431 TL431 1

U6, U7, TC4420 DIP8 Generic Driver TC4420 6

U12—U15 Module

U10 CD4049 DIP16 CD4049 CD4049 1

U11 HDC-15LX HLX-15 HE 1

U16 IR2125 DIP8 IR2125 1

U17, U18 TL074 DIP14 Op-Amp Quad LF444A 2

U19 LM293 DIP8 LM193 1

U20—U22 IR2125 DIP8 IR2125 3

U23 HDC-15LX HLX-15 HE 1

U24, U25 MC33269DT-3.3 TO220AB MC33269DT-3.3(TO220) 2

U26, U27 NEC2501 DIP4 NEC2501 2

U46 LM293 DIP8 LM193 1

VD1—VD4 MUR120 DIODE0.4 Diode DIODE 4

VD5—VD7 IN4748A DIODE0.4 Zener Diode ZENER3 3

VR1 P6KE200 DIODE0.4 Zener Diode ZENER3 1

VT1 IRF530 TO220V MOSFET-N 1

Design of a Digital AC/DC SMPS using the 56F8323 Device, Rev. 0

Appendix B-12 Freescale Semiconductor
Preliminary
 INDEX
Numerics Z
56F8300 Peripheral User Manual Preface-xi ZCS
56F8323 Data Sheet Preface-xi Zero Current Switch Preface-xi
Zero Current Switch Preface-xi
D Zero Voltage Switch Preface-xi
Zero Voltage Transition Preface-xi
DSP56800E Reference Manual Preface-xi ZVS
Zero Voltage Switch Preface-xi
I ZVT
Zero Voltage Transition Preface-xi
IC
Integrated Circuit Preface-xi
Implementing a Digital AC/DC Switched-Mode Power
Supply using a 56F8300 Digital Signal
Controller Preface-xi
Inductor Capacitance Preface-xi
Integrated Circuit Preface-xi

L
LC
Inductor Capacitance Preface-xi

P
Phase Shifted Full Bridge Preface-xi
PI
Proportional-Integral Preface-xi
Proportional-Integral Preface-xi
PSFB
Phase Shifted Full Bridge Preface-xi

R
RMS
Root Mean Square Preface-xi
Root Mean Square Preface-xi

S
SMPS
Switch Mode Power Supply Preface-xi
Switch Mode Power Supply Preface-xi

Index
Freescale Semiconductor i
Preliminary
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or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,

Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.

DRM074
Rev. 0
08/2005