MODULE 4

Interfacing chips

MODULE 4
Syllabus:
Programmable Peripheral Input/output port 8255 - Architecture and
modes of operation-Programmable interval timer 8254-Architecture
and modes of operation- DMA controller 8257 Architecture (Just
mention the control word, no need to memorize the control word of
8254 and 8257)
 8255 Programmable Peripheral INPUT-OUTPUT
PORT(PPI)
• Also known as parallel input-output port chip
• It is an I/O port chip used for interfacing I/O devices with
microprocessor.
• The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit
microprocessors
• It has 24 input/output lines which may be individually
programmed in groups.
• The groups of I/O pins are named as Group A , Group B and
group C upper and Group C lower.

8255 Introduction
• It is developed by Intel
• Used to transfer data under various condition from simple I/O
• It has three 8 bit ports:-
• Port A (PA0-PA7),
• Port B (PB0-PB7),
• Port C(PC0-PC7)
• Port C has Port C upper (PC0-PC7) and Port C lower(PC0-PC3).
• The 24 I/O lines which may be individually programmed into 2
groups:-
• Group A (port A and Port C upper)
• Group B(port B and port C lower )
8255 Pin Diagram

Function of pins:
• Data bus(D0-D7):These are 8-bit bi-directional buses,
connected to 8085 data bus for transferring data.

• CS: This is Active Low signal. When it is low, then data

is transfer from 8085.

• Read: This is Active Low signal, when it is Low read

operation will be start.

• Write: This is Active Low signal, when it is Low Write

operation will be start.
 Function of pins:
• Address (A0-A1):This is used to select the ports.

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC

Control
1 1
reg.

Function of pins:
• RESET: This is used to reset the device. That means
clear control registers.

• PA0-PA7:It is the 8-bit bi-directional I/O pins used to

send the data to peripheral or
or to receive the data from peripheral.

• PB0-PB7:Similar to PA

• PC0-PC7:This is also 8-bit bidirectional I/O pins. These

lines are divided into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups working in separately using 4 data’s.
Selecting the ports

8255 Internal Architecture

Data Bus buffer:
• It is a 8-bit bidirectional Data bus.

• Used to interface between 8255 data bus with system

bus.

• The internal data bus and Outer pins D0-D7 pins are
connected internally.

• The direction of data buffer is decided by Read/Write

Control Logic.

Read/Write Control Logic:

• This is getting the input signals from control bus and
Address bus

• Control signal are RD and WR.

• Address signals are A0,A1,and CS.

• 8255 operation is enabled or disabled by CS.

 Group A and Group B control:
• Group A and B get the Control Signal from CPU and
send the command to the individual control blocks.

• Group A send the control signal to port A and Port

C (Upper) PC7-PC4.

• Group B send the control signal to port B and Port

C (Lower) PC3-PC0.

• PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .
• PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.
• PORT C:
• This is a 8-bit Unlatched buffer Input and an Output latch.
• It is splitted into two parts.
• It can be programmed by bit set/reset operation.
 8255 Operation modes:
• The 8255 can work in 2 modes that are I/O mode and Bit
Set or Reset(BSR) mode

• I/O mode is further divided in to

1. Mode 0 (Basic I/O)

2. Mode 1 (Strobe I/O)

3. Mode 2 (Bi – Directional Bus)

Operation modes:
BIT SET/RESET MODE:
• Only port C(PC0-PC7) can be used to set or reset its individual
port bits.
• The PORT C can be Set or Reset by sending OUT instruction to the
CONTROL registers.
BIT SET/RESET MODE Control Word Register Format:
• This is bit set/reset control word format.

BIT SET/RESET MODE:

• Any of the 8 bit of port c can be set or reset depending on B0 of
control word
• The bit to be set or reset is selected by bit select flags B3, B2 & B1
• A BSR word is written for each bit
• Example:
• PC3 is Set then control register will be 0XXX0111.
• PC4 is Reset then control register will be 0XXX01000.
• X is a don’t care.
 I/O MODE Control Word Register format:
The mode format for I/O as shown in figure

I/O MODE:
• 8255 ports work as programmable i/o ports
• All these modes can be selected by programming control word
register(CWR).
• The control word for both mode is same.
• Bit B7 is used for specifying whether word loaded in to Bit set/reset
mode or Mode definition word.
• B7=1=Mode definition mode.
• B7=0=BSR mode.
 MODE 0 (Basic input / Output mode):
-provides simple input/output capability using each of the three ports.
-In this mode , port A, port B and port C is used as individually.
-data can be simply read from and written to input and output port.
Features:
i. In this mode , two 8 bit ports(port A and port B) and two 4 bit ports(port
C upper and port C lower) are available.
ii. Any port can be used as an input or output port.
iii. Outputs are latched , Inputs are buffered
iv. Ports do not have Handshake or interrupt capability.

21

MODE 1 :(Strobed I/O mode)

-This mode is used when the data is supplied by the input device at
irregular interval of time
Features of mode 1:
i. Two groups-group A and group B are available for strobed data
transfer.
ii. Each group contains one 8-bit data I/O port and one 4 bit control
port.
iii. The 8 bit data port can be either used as input or output port.
Both the input and outputs are latched
iv. Out of 8 bit port C ,PC0-PC2 are used to generate control signals
for port B and PC3-PC5 are used to generate control signals for
Port A. The lines PC6, PC7 may be used as independent data lines.
22
MODE 1 :(Strobed I/O mode)

B
MODE 1 :(Strobed I/O mode)
MODE 1 :(Input/output with Hand shake)
• In this mode, input or output is transferred by hand
shaking Signals.

Computer DATA BUS Printer

STB
ACK

Busy

• Handshaking signals is used to transfer data between

whose data transfer is not same.
 • Example:
• The computer send the data to the printer large speed
compared to the printer.
• When computer send the data according to the printer
speed at the time only, printer can accept.
• If printer is not ready to accept the data then after
sending the data bus , computer uses another
handshaking signal to tell printer that valid data is
available on the data bus.
• Each port uses three lines from port C as handshake
signals

MODE 2: Strobed bi-directional I/O mode

• This mode allows bidirectional data transfer over a single 8-bit data bus
using handshake signals.
• This feature is possible only Group A
• Port A is working as 8-bit bidirectional .
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port , when the peripheral request it.
• This mode of operation provides 8255 with an additional feature for
communicating with a peripheral device on an 8-bit databus.
• Handshaking signals are provided to maintain proper data flow and
synchronization between the data transmitter and receiver.
 Intel 8253/8254 –
Programmable Interval Timer

35

Introduction
• It is always possible to generate accurate time delays using the microprocessor
system by using software loop programs.
• But that will waste the precious time of CPU.
• INTEL introduced the chips 8253/8254 which is a hardware solution for the
problem of generating accurate time delays.
• Programmable interval timer/counter
• When 8253/8254 used as timing and delay generation peripheral, the
microprocessor becomes free from the tasks related to counting process and can
execute programs in memory while timer device may perform counting tasks. This
minimizes software overhead on the microprocessor.
• Has six modes of operation
• It has three independent 16-bit down counters each with a maximum count rate 2.6
MHz
• Operation
- A 16 bit count is loaded on the counter and on command it starts to decrement
- When the count reaches zero it generates a pulse
Features of 8253 / 54
• It can handle inputs from DC to 10 MHz.
• 3 counters can be programmed for either binary or BCD count.
• To operate a counter, a 16-bit count is loaded in its register on
command, it begins to decrement the count until it reaches 0. At the end
of the count, it generates a pulse that can be used to interrupt the CPU.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which
allows the user to check the count value, the programmed mode, the
current mode, and the current status of the counter.

8253/8254 Architecture
 Data Bus Buffer
• It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the
internal circuit of 8253/54 to microprocessor system data bus.

• Data is transmitted or received by the buffer upon execution of IN or OUT

instruction.

• It has three basic functions −

• Programming the modes of 8253/54.

• Loading the count registers.

• Reading the count values.

Read/Write Logic
• Controls the direction of data buffer upon whether it is a read or write operation.
• It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1.
• In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW,
respectively. In the memory-mapped I/O mode, these are connected to MEMR and
MEMW.
• Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and
CS is tied to a decoded address.
• The control word register and counters are selected according to the signals on lines
A0 & A1.
A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection
Control Word Register
• This register is accessed when lines A0 & A1 are at logic 1.

• The control word register contains the information that can be used for writing or
reading the count value into or from the respective count register using OUT and IN
instructions.

• The specialty of 8254 counter is that they can be read on line without disturbing the
clock input to the counter. This facility is called “on the fly” reading of counters.

• It is used to write a command word, which specifies the counter to be used, its
mode, and either a read or write operation. Following table shows the result for
various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Counters
• Each counter consists of a single, 16 bit presettable down counter, which can be
operated in either binary or BCD.
• Its input and output is configured by the selection of modes stored in the control word
register.
• The programmer can read the contents of any of the three counters without disturbing
the actual count in process.
• Counters are programmed by writing a Control Word and then an initial count.
• GATE=1 enables counting, GATE=0 disables counting.
Counter Latch Command
• It is written to the Control Word Register like a Control Word, but two bits
(D5, D4) distinguish this command from a Control Word.
• The selected Counter latches the count at the time the Counter Latch
Command is received.
• The count is held in the latch until it is read by the CPU.
Read-Back Command (Available only for 8254)
• This command allows the user to check the count value, programmed Mode,
and current states of the OUT pin, etc...

Intel 8253/54 - Operational Modes

Mode 0 ─ Interrupt on Terminal Count
• It is used to generate an interrupt to the microprocessor after a certain
interval.

• Initially the output is low after the mode is set. The output remains LOW
after the count value is loaded into the counter.

• The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero & output goes HIGH and will remain
high until it reloads a new count.

• The GATE signal is high for normal counting. When GATE goes low,
counting is terminated and the current count is latched till the GATE goes
high again.
Mode 1 – Programmable One Shot
• It can be used as a mono stable multi-vibrator(produce time delays within a circuit).
• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a trigger is applied.
• In Mode 1, after sending the 0-to-1 pulse to GATE, OUT becomes low and stays
low for a duration of count, then becomes high and stays high until the GATE is
triggered again

Mode 2 – Rate Generator or Divide by N counter

• The output is normally high after initialization.
• After loading the counter and triggering (gate=1) it, the output will be high till
the last one period (i.e. The output will be high for (n-1) clock pulses and then
it will go low for one cycle of input clock and then return HIGH and the count
value is automatically reloaded into the counter
• If the gate is low, the output will be HIGH and no counting will be performed.
Mode 3 – Square Wave Rate Generator
• This mode is similar to Mode 2 except the output remains low for
half of the timer period and high for the other half of the period.
• This is accomplished internally by decrementing the counter by two
on the falling edge of each pulse
• When the count N loaded is EVEN, then for half of the count, the
output remains high and for the remaining half it remains low.
• If the loaded count value N is ODD, then for (N+1)/2 pulses the
output remains high & for (N-1)/2 pulses it remains low

Mode 4 − Software Triggered Mode

• In this mode, the output will remain high until the timer has counted to zero, at which point
the output will pulse low and then go high again.
• The count is latched when the GATE signal goes LOW.
• On the terminal count, the output goes low for one clock cycle then goes HIGH. This low
pulse can be used as a strobe.
• Here, the counter is not reloaded automatically. To repeat the strobe, the count must be
reloaded
• This is called software triggered strobe as the count down is initiated by a program
Mode 5 – Hardware Triggered Mode
• This mode generates a strobe in response to an externally generated signal.
• This mode is similar to mode 4 except that the counting is initiated by a
signal at the gate input, which means it is hardware triggered instead of
software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output goes low for one clock cycle.

Programmable DMA Controller

[8257]

54
 DMA
• DMA stands for Direct Memory Access.
• It is designed by Intel to transfer data at the fastest rate.
• It allows the device to transfer the data directly to/from memory
without any interference of the CPU.
• Using a DMA controller, the device requests the CPU to hold its
data, address and control bus, so the device is free to transfer data
directly to/from the memory.
• The DMA data transfer is initiated only after receiving HLDA signal
from the CPU.

55

DMA Controller

56
 DMA Controller 8257
• The DMA I/O technique provides direct access to the memory while the
microprocessor is temporarily disabled.

• The DMA controller temporarily borrows the address bus, data bus and
control bus from the microprocessor and transfers the data directly from
the external devices to a series of memory locations (and vice versa).

• DMA controller: dedicated hardware used for controlling the DMA

operation

57

How DMA Operations are Performed?

• Initially, when any device has to send data between the device and the
memory, the device has to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the
CPU to assert the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control
bus.
• The CPU leaves the control over bus and acknowledges the HOLD request
through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.

58
 Features of 8257
• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify
transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes
have been transferred.
• Its frequency ranges from 250Hz to 3MHz.

59

Features of 8257
• It execute 3 DMA cycles
1.DMA read 2.DMA write 3.DMA verify.
• It provide AEN signal that can be used to isolate CPU and
other devices from the system bus.
• It is operate in two modes.
1.Master Mode
2.Slave Mode

60
 8257 Architecture

61

DMA Controller 8257

• The 8257 is a four-channel device that can be expanded
to include any number of DMA channel inputs.

• The 8257 is capable of DMA transfers at rates of up to

1.6 M Bytes per second.

• Each channel is capable of addressing a full 64k-byte

section of memory and can transfer up to 64k bytes with
a single programming.

62
 Main Blocks of 8257
• Five main Blocks
1. Data bus buffer
2. Read/Write logic
3. Control logic block
4. Priority resolver
• Resolves the priority of the 4 DMA channels depending upon
whether normal priority or rotating priority is programmed
5. DMA channels

63

Block Description
DATA BUS BUFFER:
• 8 bit, tristate, bi-directional buffer.
• Interfaces internal bus of 8257 with the external system bus under the
control of various control signals.
• Slave mode
• it transfer data between microprocessor and internal data bus.
• Master mode:
• Dataflow to or from the selected peripherals.

64
 Block Description
READ/WRITE CONTROL LOGIC:
• It control all internal Read/Write operation.
• Slave mode:
• it accepts address bits and control signal from microprocessor.
• It accepts I/O read and I/O write signals, decodes A0-A3 lines and either either
write the content of databus to the addressed internal register or read content of
selected register depending on depending upon whether IOW or IOR signal is
activated.
• Master mode:
• it generates IOR and IOW signals to control dataflow to or from the selected
peripheral.

Block Description
CONTROL LOGIC BLOCK:
• It contains
1. Control logic
2. Mode set register and
3. Status Register.

• Master mode:
• Controls the sequence of operations and generates the required
control signals like AEN, ADSTB, MEMR,MEWR, TC and MARK along
with the address lines A4-A7.
• It increments 16 bit address and decrement 14 bit counter registers.
• It activate a HRQ(Hold request) signal on DMA channel Request.
• Slave mode - it is disabled.
66
REGISTER ORGANIZATION OF 8257

REGISTER ORGANIZATION OF 8257

REGISTER ORGANIZATION OF 8257
Block Description
• MODE SET REGISTERS:
 Block Description
MODE SET REGISTERS:
• It should be programmed by the CPU for enabling the DMA channels
only after the initialization of DMA address register and terminal count
register

73

MODE SET REGISTERS:

• Rotating priority Mode:

• Priorities assigned to channels are not fixed
• The priority of the channels has a circular sequence.
• Avoids dominance of any one channel

• Fixed Priority Rotating Mode:

• Each device connected to a channel is assigned a fixed priority
• DRQ3 has lowest priority
• DRQ0 has highest priority
 MODE SET REGISTERS:

Block Description
STATUS REGISTERS:

76
 Block Description
STATUS REGISTERS

77

Transfer data from memory to disk

1. Device requests service of DMA by pulling DREQ (DMA request)
high
2. DMA puts high on HRQ (hold request),
3. CPU finishes present bus cycle and puts high on HDLA (hold
acknowledge). HOLD remains active for duration of DMA
4. DMA activates DACK (DMA acknowledge), telling device to start
transfer
5. DMA starts transfer by putting address of first byte on address bus
and activating MEMR; it then activates IOW to write to peripheral.
DMA decrements counter and increments address pointer. Repeat
until count reaches zero
6. DMA deactivates HRQ, giving bus back to CPU

78
 Pin Diagram of 8257

79

Pin Description
CLK:
• It is the input line ,connected with TTL clock generator.
• This signal is ignored in slave mode.
RESET:
• Used to clear mode set registers and status registers
A0-A3:
These are the tristate, buffer, bidirectional address lines.
In slave mode ,these lines are used as address inputs lines
and internally decoded to access the internal registers.
In master mode, these lines are used as address outputs
lines,A0-A3 bits of memory address on the lines.
 Pin Description
CS:
• It is active low, Chip select input line.
• In the slave mode, it is used to select the chip.
• In the master mode, it is ignored.
A4-A7:
These are the tristate, buffer, output address lines.
In slave mode ,these lines are used as address outputs
lines.
In master mode, these lines are used as address outputs
lines,A0-A3 bits of memory address on the lines.

Pin Description
READY:
• It is a asynchronous input line.
• In master mode,
• When ready is high it is received the signal.
• When ready is low, it adds wait state between S1 and S3
• In slave mode ,this signal is ignored.
HRQ:
• It is used to receiving the hold request signal from the
output device.
 Pin Description
HLDA:
• It is acknowledgment signal from microprocessor.
MEMR:
• It is active low ,tristate ,Buffered control output line.
• In slave mode, it is tristated.
• In master mode ,it activated during DMA read cycle.
MEMW:
• It is active low ,tristate ,Buffered control input line.
• In slave mode, it is tristated.
• In master mode ,it activated during DMA write cycle.

Pin Description
AEN (Address enable):
• It is a control output line.
• In master mode ,it is high
• In slave mode ,it is low
• Used it isolate the system address ,data ,and control
lines.
ADSTB: (Address Strobe)
• It is a control output line.
• Used to split data and address line.
• It is working in master mode only.
• In slave mode it is ignore.
 Pin Description
TC (Terminal Count):
• It is a status of output line.
• It is activated in master mode only.
• It is high ,it selected the peripheral.
• It is low ,it free and looking for a new peripheral.
MARK:
• It is a modulo 128 MARK output line.
• It is activated in master mode only.
• It goes high ,after transferring every 128 bytes of data
block.

Pin Description
DRQ0-DRQ3(DMA Request):
• These are the asynchronous peripheral request input
signal.
• The request signals is generated by external peripheral
device.
DACK0-DACK3:
• These are the active low DMA acknowledge output
lines.
• Low level indicate that ,peripheral is selected for giving
the information (DMA cycle).
• In master mode it is used for chip select.
 Data Transfer modes
• Single Transfer Mode
In Single Transfer mode the device is programmed
to make one transfer only.
The word count will be decremented and the
address decremented or incremented following each
transfer.
• Block Transfer Mode
In Block Transfer mode the device is activated by
DREQ to continue making transfers during the service
until a TC, or an external End of Process (EOP) is
encountered.
ie, block of data is transferred
87

Data Transfer modes

• Demand Transfer Mode:
In Demand Transfer mode the device is programmed to
continue making transfers until a TC or external EOP is
encountered or until DREQ goes inactive.

Transfers may continue until the I/O device has

exhausted its data capacity. the DMA service can be re-
established by means of a DREQ.

During the time between services when the

microprocessor is allowed to operate, the intermediate
values of address and word count are stored in the
8237A Current Address and Current Word Count
registers.
88
 Modes of Operation
• Rotating priority Mode:
• Priorities assigned to channels are not fixed
• The priority of the channels has a circular sequence.
• Avoids dominance of any one channel

• Fixed Priority Rotating Mode:

• Each device connected to a channel is assigned a fixed
priority
• DRQ3 has lowest priority
• DRQ0 has highest priority