LIBRARY IEEE;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY mux_2_1 IS PORT( ENTITY mux_2_1_tb IS

END mux_2_1_tb;

A: IN STD_LOGIC;
B: IN STD_LOGIC;
ARCHITECTURE rtl OF mux_2_1_tb IS
SEL: IN STD_LOGIC;
S: OUT STD_LOGIC); COMPONENT mux_2_1 IS PORT(

END mux_2_1; A: IN STD_LOGIC;

B: IN STD_LOGIC;
SEL: IN STD_LOGIC;
ARCHITECTURE rtl OF mux_2_1 IS S: OUT STD_LOGIC);
END COMPONENT;

BEGIN SIGNAL X,Y,SEL,S: STD_LOGIC;

S <= A WHEN SEL='1' ELSE
BEGIN
B WHEN SEL='0' ELSE
'Z'; U1: mux_2_1 PORT MAP (
A => X,
END rtl;
B => Y,
SEL => SEL,
S => S);

PROCESS
BEGIN
X <= '1';
Y <= '0';
WAIT FOR 15 NS;
X <= '0';
Y <= '1';
WAIT FOR 20 NS;
END PROCESS;

PROCESS
BEGIN
SEL <='1';
WAIT FOR 10 NS;
SEL <='0';
WAIT FOR 9 NS;
SEL<= 'X';
WAIT FOR 3 NS;
END PROCESS;
END rtl;
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY reg_8bits_tb IS
END reg_8bits_tb;
--
ARCHITECTURE rtl OF reg_8bits_tb IS
COMPONENT reg_8bits IS PORT (
ENTITY reg_8bits IS PORT( clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
clk: IN STD_LOGIC; data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rst: IN STD_LOGIC; data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
data_in: IN STD_LOGIC_VECTOR(7 END COMPONENT;
DOWNTO 0); SIGNAL CLK ,RST :STD_LOGIC;
SIGNAL DATA_IN ,DATA_OUT:STD_LOGIC_VECTOR(7 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR(7
DOWNTO 0));
BEGIN

END reg_8bits; U1: reg_8bits PORT MAP (

clk => CLK,
ARCHITECTURE rtl OF Reg_8bits IS rst => RST,
data_in => DATA_IN,
BEGIN data_out=> DATA_OUT);
PROCESS(clk,rst) PROCESS
BEGIN BEGIN
RST <= '1';
IF(rst='0')THEN
WAIT FOR 50 ns;
data_out <= (others =>'0');
RST <= '0';
ELSIF (clk'event AND clk='1')THEN
WAIT FOR 50 ns;
data_out <= data_in;
END IF; END PROCESS;
END PROCESS;
END rtl; PROCESS
BEGIN
CLK <= '1';
WAIT FOR 25 ns;
CLK <= '0';
WAIT FOR 25 ns;

END PROCESS;

PROCESS
BEGIN

DATA_IN <= "00001111";

WAIT FOR 40 ns;
DATA_IN <= "11100000";
WAIT FOR 40 ns;
DATA_IN <= "10101010";
WAIT FOR 40 ns;
DATA_IN <= "01010101";
WAIT FOR 40 ns;

END PROCESS;
END RTL;
ENTITY compt_decompt_16bits_tb IS
END compt_decompt_16bits_tb;
ENTITY compt_decompt_16bits IS PORT(
ARCHITECTURE rtl OF compt_decompt_16bits_tb IS
COMPONENT compt_decompt_16bits IS PORT ( ABCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ABCD:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
up:IN STD_LOGIC; up:IN STD_LOGIC;
down:IN STD_LOGIC; down:IN STD_LOGIC;
load:IN STD_LOGIC;
load:IN STD_LOGIC;
clear:IN STD_LOGIC;
clk:IN STD_LOGIC); clear:IN STD_LOGIC;
END COMPONENT; clk:IN STD_LOGIC);

SIGNAL X,Y : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL UP ,DOWN ,LOAD ,CLEAR ,CLK : STD_LOGIC; END compt_decompt_16bits;
BEGIN
ARCHITECTURE rtl OF compt_decompt_16bits IS
U1: compt_decompt_16bits PORT MAP (
ABCD => X,
SIGNAL sig_out:STD_LOGIC_VECTOR(3 DOWNTO 0);
cout => Y,
up => UP, BEGIN
down=> DOWN,
load => LOAD,
PROCESS(clk,clear)
clear => CLEAR, BEGIN
clk => CLK); IF(clear='0') THEN
PROCESS
sig_out <= (OTHERS => '0');
BEGIN
clk<='1'; ELSIF (rising_edge(clk))THEN
wait for 10 ns ; IF (load = '1')THEN
clk<='0';
sig_out <= ABCD;
wait for 10 ns ;
END PROCESS; ELSE
IF (up='1') THEN
PROCESS
sig_out <= sig_out + 1;
BEGIN
load<='0'; ELSIF (down='1') THEN
wait for 40 ns ; sig_out <= sig_out - 1;
load<='1'; END IF;
wait for 20 ns ;
load<='0'; END IF;
wait for 40 ns; END IF;
END PROCESS; END PROCESS;
PROCESS
cout <= sig_out;
BEGIN
clear<='0';
wait for 20 ns ;
clear<='1';
wait for 40 ns ; END rtl;
END PROCESS;

PROCESS
BEGIN
up<='0';
down<='0';
wait for 20 ns ;
up<='1';
down<='0';
wait for 30 ns ;
up<='0';
down<='1';
wait for 50 ns ;
END PROCESS;
X<="1000";

END rtl;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY comp_8bits IS PORT(

-- ENSA FES -- A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- FILIERE : GSEII -- ega: OUT STD_LOGIC;
-- TITLE : comp_4bits -- sup: OUT STD_LOGIC;
-- TP : Lab_01 -- inf: OUT STD_LOGIC);
-- AUTHOR : CHAYMAE FILALI -- END comp_8bits;

ENTITY comp_4bits IS PORT(

ARCHITECTURE rtl OF comp_8bits IS
A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT comp_4bits IS PORT (
ega: OUT STD_LOGIC;
sup: OUT STD_LOGIC; A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
inf: OUT STD_LOGIC); B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
END comp_4bits; ega: OUT STD_LOGIC;
sup: OUT STD_LOGIC;
ARCHITECTURE rtl OF comp_4bits IS inf: OUT STD_LOGIC);

BEGIN END COMPONENT;

ega <= '1' WHEN A=B ELSE SIGNAL
'0'; sup_Msb,sup_Lsb,inf_Msb,inf_Lsb,ega_Msb,ega_Lsb,sig_
inf <= '1' WHEN A<B ELSE 1,sig_2:std_logic;
'0';
sup <= '1' WHEN A>B ELSE BEGIN
'0'; U1: comp_4bits PORT MAP(
A => A(7 DOWNTO 4),
END rtl; B => B(7 DOWNTO 4),
ega => ega_Msb,
inf => inf_Msb,
sup => sup_Msb);

U2: comp_4bits PORT MAP(

A => A(3 DOWNTO 0),
B => B(3 DOWNTO 0),
ega => ega_Lsb,
inf =>inf_Lsb,
sup =>sup_Lsb);

sig_1 <= ega_Msb AND sup_Lsb;

sig_2 <= ega_Msb AND inf_Lsb;
ega <= ega_Msb AND ega_Lsb;
inf <= inf_Msb OR sig_2;
sup <= sup_Msb OR sig_1;

END rtl;
ENTITY comp_4bits_tb IS ENTITY comp_8bits_tb IS
END comp_4bits_tb; END comp_8bits_tb;

ARCHITECTURE rtl OF comp_4bits_tb IS

COMPONENT comp_4bits IS PORT ( ARCHITECTURE rtl OF comp_8bits_tb IS
A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT comp_8bits IS PORT (
ega: OUT STD_LOGIC;
sup: OUT STD_LOGIC; A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
inf: OUT STD_LOGIC); B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
END COMPONENT; ega: OUT STD_LOGIC;
sup: OUT STD_LOGIC;
SIGNAL X,Y : STD_LOGIC_VECTOR(3 DOWNTO 0); inf: OUT STD_LOGIC);
SIGNAL EQA,SUP,INF : STD_LOGIC;
BEGIN END COMPONENT;

U1: comp_4bits PORT MAP (

A => X,
B=> Y, SIGNAL X,Y : STD_LOGIC_VECTOR(7 DOWNTO 0);
ega => EQA, SIGNAL EQA,SUP,INF : STD_LOGIC;
sup=> SUP,
inf => INF); BEGIN
U1: comp_8bits PORT MAP (
PROCESS A => X,
BEGIN B=> Y,
X <= "1001"; ega => EQA,
Y <= "1001"; sup=> SUP,
WAIT FOR 10 MS; inf => INF);
X <= "1100";
Y <= "1000"; PROCESS
WAIT FOR 20 MS;
X <= "0001"; BEGIN
Y <= "1000"; X <= "11111111";
WAIT FOR 30 MS; Y <= "11111111";
END PROCESS; wait for 12 ns;

END rtl; X <= "11111111";

Y <= "11101100";
wait for 12 ns;

X <= "11101100";
Y <= "11111100";
wait for 12 ns;

END PROCESS;

END rtl;
ENTITY top IS PORT ( ENTITY top_tb IS
ABCD:in STD_LOGIC_VECTOR(3 DOWNTO 0); END top_tb;
clk:in STD_LOGIC; ARCHITECTURE rtl OF top_tb IS
clear:in STD_LOGIC; COMPONENT top IS PORT (
load:in STD_LOGIC; ABCD:in STD_LOGIC_VECTOR(3 DOWNTO 0);
data_in:in STD_LOGIC_VECTOR(7 DOWNTO 0); clk:in STD_LOGIC;
data_out:out STD_LOGIC_VECTOR(3 DOWNTO 0)); clear:in STD_LOGIC;
END top; load:in STD_LOGIC;
data_in:in STD_LOGIC_VECTOR(7 DOWNTO 0);
ARCHITECTURE rtl OF top IS data_out:out STD_LOGIC_VECTOR(3 DOWNTO 0));
COMPONENT reg_8bits IS PORT( END COMPONENT;
SIGNAL data_in:STD_LOGIC_VECTOR(7 DOWNTO 0);
data_in:in STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL data_out:STD_LOGIC_VECTOR(3 DOWNTO 0);
clk:in STD_LOGIC;
SIGNAL clk,clear,load:STD_LOGIC;
rst:in STD_LOGIC;
SIGNAL ABCD: STD_LOGIC_VECTOR(3 DOWNTO 0);
data_out:out STD_LOGIC_VECTOR(7 DOWNTO 0));
BEGIN
END COMPONENT;
U : top PORT MAP(
clk=>clk,
COMPONENT comp_8bits IS PORT( clear=> clear,
A:in STD_LOGIC_VECTOR(7 DOWNTO 0); load=>load,
B:in STD_LOGIC_VECTOR(7 DOWNTO 0); data_in=>data_in,
sup:out STD_LOGIC; ABCD=>ABCD,
ega:out STD_LOGIC; data_out=>data_out);
inf:out STD_LOGIC);
END COMPONENT; PROCESS
BEGIN
COMPONENT compt_decompt_16bits IS PORT ( clk <= '1';
ABCD:in STD_LOGIC_VECTOR(3 DOWNTO 0); wait for 5 ns;
cout:out STD_LOGIC_VECTOR(3 DOWNTO 0); clk <= '0';
load:in STD_LOGIC; wait for 5 ns;
clear:in STD_LOGIC; clk <= '1';
wait for 5 ns;
clk:in STD_LOGIC;
clk <= '0';
up:in STD_LOGIC;
wait for 5 ns;
down:in STD_LOGIC);
END PROCESS;
END COMPONENT;
PROCESS
SIGNAL sig_reg:STD_LOGIC_VECTOR(7 DOWNTO BEGIN
0); clear <= '0';
SIGNAL sig_ega:STD_LOGIC; wait for 12.5 ns;
BEGIN clear <= '1';
U1 : reg_8bits PORT MAP( wait for 100 ns;
clk=>clk, END PROCESS;
rst=>clear,
data_in=>data_in, PROCESS
data_out=>sig_reg); BEGIN
load <= '0';
U2 : comp_8bits PORT MAP( wait for 20 ns;
A=>data_in, load <= '1';
B=>sig_reg, wait for 10 ns;
sup=>open, load <= '0';
wait for 82.5 ns;
inf=>open,
END PROCESS;
ega=>sig_ega);

PROCESS
U3 : compt_decompt_16bits PORT MAP (
BEGIN
ABCD=>ABCD,
data_in <= "11111000";
cout=>data_out, wait for 25 ns;
up=>sig_ega, data_in <= "11111000";
down=>'0', wait for 30 ns;
load=>load, data_in <= "00110011";
clear=>clear, wait for 57.5 ns;
clk=>clk); END PROCESS;
ABCD<="0000";
END rtl; END rtl;
 signal
ENTITY Multiplieur_8bits IS PORT( data_0,data_1,data_2,data_3,data_4,data_5,data_6,data_7:S
TD_LOGIC_VECTOR(15 DOWNTO 0);
clk: IN STD_LOGIC; signal enable:STD_LOGIC;
rst: IN STD_LOGIC; begin
N1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
N2: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Reg0:L_Shifter generic map(0)
start:IN STD_LOGIC;
port map( clk=>clk,
Rdy: OUT STD_LOGIC;
rst=>rst,
R: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
); enable=>N1(0),
data_in=>N2,
END Multiplieur_8bits; data_out=>data_0);

ARCHITECTURE rtl OF Multiplieur_8bits IS Reg1:L_Shifter generic map(1)

COMPONENT L_Shifter IS PORT( port map( clk=>clk,
clk: IN STD_LOGIC; rst=>rst,
rst: IN STD_LOGIC; enable=>N1(1),
enable: IN STD_LOGIC; data_in=>N2,
data_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0); data_out=>data_1);
data_out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END COMPONENT; Reg2:L_Shifter generic map(2)
COMPONENT Adder_16bits IS PORT(
port map( clk=>clk,
rst=>rst,
in_0: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
enable=>N1(2),
in_1: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
in_2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data_in=>N2,
in_3: IN STD_LOGIC_VECTOR(15 DOWNTO 0); data_out=>data_2);
in_4: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
in_5: IN STD_LOGIC_VECTOR(15 DOWNTO 0); Reg3:L_Shifter generic map(3)
in_6: IN STD_LOGIC_VECTOR(15 DOWNTO 0); port map( clk=>clk,
in_7: IN STD_LOGIC_VECTOR(15 DOWNTO 0); rst=>rst,
enable:IN STD_LOGIC; enable=>N1(3),
R_out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) data_in=>N2,
); data_out=>data_3);
END COMPONENT;
Reg4:L_Shifter generic map(4)
COMPONENT Fsm IS PORT( port map( clk=>clk,
rst=>rst,
clk: IN STD_LOGIC;
enable=>N1(4),
rst: IN STD_LOGIC;
data_in=>N2,
start: IN STD_LOGIC;
data_out=>data_4);
enable: OUT STD_LOGIC;
Rdy: OUT STD_LOGIC
); Reg5:L_Shifter generic map(5)
END COMPONENT; port map( clk=>clk,
rst=>rst,
enable=>N1(5),
data_in=>N2,
data_out=>data_5);
Reg6:L_Shifter generic map(6)
port map( clk=>clk,
rst=>rst,
enable=>N1(6),
data_in=>N2,
data_out=>data_6);

Reg7:L_Shifter generic map(7) LIBRARY IEEE;

port map( clk=>clk, USE IEEE.STD_LOGIC_1164.ALL;
rst=>rst, USE IEEE.NUMERIC_STD.ALL;
enable=>N1(7),
data_in=>N2, ENTITY L_Shifter IS
data_out=>data_7); generic (n: integer:=2); -- 2 valeur initiale
PORT (
Adder:Adder_16bits port map( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
in_0=>data_0, Enable : IN STD_LOGIC;
in_1=>data_1, Data_In: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
in_2=>data_2, Data_Out: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
in_3=>data_3, END L_Shifter;
in_4=>data_4,
in_5=>data_5, ARCHITECTURE rtl OF L_Shifter IS
in_6=>data_6, SIGNAL data_msb :STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
in_7=>data_7, SIGNAL data_lsb :STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000";
enable=>enable, BEGIN
R_out=>R); PROCESS(CLK,RST)
BEGIN
IF (RST='0')THEN
FSM_Multiplieur:Fsm port map( data_msb <= (others => '0');
clk=>clk, data_lsb <= (others => '0');
rst=>rst, ELSIF (CLK'EVENT AND CLK='1')THEN
start=>start, IF (Enable = '1') THEN
enable=>enable, data_msb(7 DOWNTO n) <= (others => '0');
Rdy=>Rdy); data_msb((n-1) DOWNTO 0) <= Data_In(7 DOWNTO (7-(n-1)));
end rtl; data_lsb(7 DOWNTO n) <= Data_In((7-n) DOWNTO 0);
data_lsb((n-1) DOWNTO 0) <= (others => '0');
ELSE
data_msb <= (others => '0');
data_lsb <= (others => '0');
END IF;
END IF;
END PROCESS;
Data_Out <= data_msb & data_lsb;
END rtl;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY adder_16bits IS PORT(
in_0: in std_logic_vector(15 DOWNTO 0); ENTITY Fsm IS PORT(
in_1: in std_logic_vector(15 DOWNTO 0);
in_2: in std_logic_vector(15 DOWNTO 0); clk: IN STD_LOGIC;
in_3: in std_logic_vector(15 DOWNTO 0); rst: IN STD_LOGIC;
in_4: in std_logic_vector(15 DOWNTO 0); start: IN STD_LOGIC;
in_5: in std_logic_vector(15 DOWNTO 0);
enable: OUT STD_LOGIC;
in_6: in std_logic_vector(15 DOWNTO 0);
Rdy: OUT STD_LOGIC
in_7: in std_logic_vector(15 DOWNTO 0);
);
enable:in std_logic;
end Fsm ;
R_out: OUT std_logic_vector(15 DOWNTO 0));
END adder_16bits; ARCHITECTURE rtl OF Fsm IS
type etat is (S0,S1);
ARCHITECTURE rtl of adder_16bits is signal c_etat,n_etat: etat := S0;
BEGIN
R_out<=in_0+in_1+in_2+in_3+in_4+in_5+in_6+in_7 WHEN begin
enable='1'ELSE(others=>'0'); process(clk,rst)
END rtl; begin
if(rst='0')then
c_etat<=S0;
elsif (clk'event and clk='1')then
c_etat<=n_etat;
end if;
end process;
process(c_etat,start)
begin
case c_etat is
when S0 =>
Rdy<='1';
if(start='1')then
enable<='1';
n_etat<=S1;
end if;
when S1 =>
enable <='1';
Rdy<='0';
n_etat<=S0;
when others =>
enable <='0';
Rdy <= '1';
n_etat<=S0;
end case;
end process;
END rtl;
ENTITY L_shifter IS ENTITY adder_mbits IS
GENERIC ( generic (
n, m: INTEGER := 2 n : integer := 4;
); m : integer := 8
PORT ( );
clk : IN STD_LOGIC; PORT (
rst : IN STD_LOGIC; enable : in std_logic;
enable : IN STD_LOGIC; data_in : in std_logic_vector(m-1 downto 0);
data_in : IN STD_LOGIC_VECTOR(m-1 DOWNTO result_out : out std_logic_vector(m-1 downto
0); 0)
data_out: OUT STD_LOGIC_VECTOR(2*m-1 );
DOWNTO 0) END adder_mbits;
); ARCHITECTURE rtl OF adder_mbits IS
END L_shifter; signal data_temp : unsigned(m-1 DOWNTO 0) :=
(others => '0');
ARCHITECTURE RTL OF L_shifter IS signal multiplicand_shifted: std_logic_vector(m-1
SIGNAL DATA_MSB: STD_LOGIC_VECTOR(m-1 DOWNTO 0);
DOWNTO 0) := (OTHERS => '0'); BEGIN
SIGNAL DATA_LSB: STD_LOGIC_VECTOR(m-1 PROCESS(enable, data_in)
DOWNTO 0) := (OTHERS => '0'); BEGIN
BEGIN IF enable = '1' THEN
PROCESS (clk, rst) multiplicand_shifted <= '0' & data_in(m-1
BEGIN DOWNTO 1);
IF (rst = '0') THEN data_temp <= data_temp +
DATA_MSB <= (OTHERS => '0'); unsigned(multiplicand_shifted);
DATA_LSB <= (OTHERS => '0'); END IF;
ELSIF (CLK'EVENT AND CLK='1') THEN END PROCESS;
IF (enable = '1') THEN
DATA_MSB(m-1 DOWNTO n) <= (OTHERS => result_out <= std_logic_vector(data_temp);
'0'); END rtl;
DATA_MSB(n-1 DOWNTO 0) <= data_in(m-1
DOWNTO (m-n));
DATA_LSB(m-1 DOWNTO n) <= data_in((m-n-
1) DOWNTO 0);
DATA_LSB(n-1 DOWNTO 0) <= (OTHERS =>
'0');
END IF;
END IF;
END PROCESS;

data_out <= DATA_MSB & DATA_LSB;

END RTL;
 COMPONENT L_shifter
ENTITY multiplieur_n_bits IS GENERIC (
GENERIC ( n, m: INTEGER := 2
);
n : integer := 4;
PORT (
m : integer := 8
clk : IN STD_LOGIC;
); rst : IN STD_LOGIC;
PORT ( enable : IN STD_LOGIC;
clk : in std_logic; data_in : IN STD_LOGIC_VECTOR(m-1 DOWNTO 0);
rst : in std_logic; data_out: OUT STD_LOGIC_VECTOR(2*m-1 DOWNTO 0)
start : in std_logic; );
data_in : in std_logic_vector(m-1 END COMPONENT;
downto 0);
result : out std_logic_vector(2*m-1
signal fsm_enable, fsm_Rdy, adder_enable, shifter_enable: std_logic;
downto 0);
signal adder_result: std_logic_vector(m-1 downto 0);
enable : out std_logic; signal shifter_data_out: std_logic_vector(2*m-1 downto 0);
Rdy : out std_logic
); BEGIN
END multiplieur_n_bits;
fsm_inst: Fsm PORT MAP(
ARCHITECTURE rtl OF multiplieur_n_bits clk => clk,
IS rst => rst,
start => start,
enable => fsm_enable,
COMPONENT Fsm
Rdy => fsm_Rdy
PORT( );
clk: IN STD_LOGIC;
rst: IN STD_LOGIC; adder_inst: adder_mbits
start: IN STD_LOGIC; GENERIC MAP (
enable: OUT STD_LOGIC; n => 4,
Rdy: OUT STD_LOGIC m => 8
)
);
PORT MAP (
END COMPONENT;
enable => adder_enable,
data_in => data_in,
COMPONENT adder_mbits result_out => adder_result
GENERIC ( );
n : INTEGER := 4;
m : INTEGER := 8 shifter_inst: L_shifter
); GENERIC MAP (
PORT ( n => 2,
m => 8
enable : IN STD_LOGIC;
)
data_in : IN
PORT MAP (
STD_LOGIC_VECTOR(m-1 DOWNTO 0); clk => clk,
result_out : OUT rst => rst,
STD_LOGIC_VECTOR(m-1 DOWNTO 0) enable => shifter_enable,
); data_in => adder_result,
END COMPONENT; data_out => shifter_data_out
);

enable <= fsm_enable and adder_enable and shifter_enable;

Rdy <= fsm_Rdy;
result <= shifter_data_out;
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mux_4_1 IS PORT( USE IEEE.NUMERIC_STD.ALL;

A_in: IN STD_LOGIC; ENTITY Adder_4bits IS PORT(

B_in: IN STD_LOGIC;
C_in: IN STD_LOGIC; A:in std_logic_vector(3 downto 0);
D_in: IN STD_LOGIC; B:in std_logic_vector(3 downto 0);
SEL:IN STD_LOGIC_vector(1 downto 0); S:out std_logic_vector(3 downto 0)
S_out: OUT STD_LOGIC); );
END mux_4_1; END Adder_4bits;

ARCHITECTURE rtl OF mux_4_1 IS ARCHITECTURE rtl of Adder_4bits is

begin
BEGIN S<= A+B;
PROCESS (A_in,B_in,C_in,D_in,SEL) END rtl; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
BEGIN USE IEEE.STD_LOGIC_ARITH.ALL;
CASE SEL IS USE IEEE.STD_LOGIC_UNSIGNED.ALL;
WHEN "00" =>
ENTITY Cpt_16B IS PORT (
S_out<= A_in;
CLK, CLEAR, LOAD, UP, DOWN: IN STD_LOGIC;
WHEN "01" => ABCD : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_out<= B_in; OUT_ABCD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
WHEN "10" => END Cpt_16B;

S_out<= C_in;
ARCHITECTURE RTL OF Cpt_16B IS
WHEN "11" =>
S_out<= D_in; SIGNAL SIG: STD_LOGIC_VECTOR(3 DOWNTO 0);
when others => S_out <= 'X';
BEGIN
end case; PROCESS(CLK,CLEAR)
end process; BEGIN
END rtl; IF (CLEAR = '1') THEN
SIG <= (OTHERS=>'0');
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF (LOAD ='1') THEN
SIG<=ABCD;
ELSIF (LOAD = '0') THEN

lab0 IF (UP = '1') THEN

IF (SIG="1111")THEN
SIG<=(OTHERS=>'0');
ELSE
SIG<= SIG + 1;
END IF;
ELSIF (DOWN ='1') THEN
IF (SIG="0000") THEN
SIG<=(OTHERS=>'1');
ELSE
SIG <= SIG - 1;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
OUT_ABCD <= SIG;

END RTL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

ENTITY Adder_top IS
PORT(
A: IN std_logic_vector(3 DOWNTO 0);
B: IN std_logic_vector(3 DOWNTO 0);
S: OUT std_logic_vector(6 DOWNTO 0)
);
END Adder_top;

ARCHITECTURE rtl OF Adder_top IS

COMPONENT Adder_4bits IS
PORT(
A: IN std_logic_vector(3 DOWNTO 0);
B: IN std_logic_vector(3 DOWNTO 0);
S: OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;

COMPONENT Seven_seg IS
PORT(
sig_in: IN std_logic_vector(3 DOWNTO 0);
sig_out: OUT std_logic_vector(6 DOWNTO 0)
LAB0
);
END COMPONENT;

SIGNAL Adder_sig: std_logic_vector(3 DOWNTO 0);

BEGIN
U0: Adder_4bits PORT MAP(
A => A,
B => B,
S => Adder_sig
);

U1: Seven_seg PORT MAP(

sig_in => Adder_sig,
sig_out => S
);

END rtl;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Seven_seg IS PORT(
USE IEEE.NUMERIC_STD.ALL;
sig_in:in std_logic_vector(3 downto 0);
sig_out:out std_logic_vector(6 downto 0)
ENTITY Div_freq IS PORT(
);
END Seven_seg;
clk_in:in std_logic;
ARCHITECTURE rtl of Seven_seg is
rst:in std_logic
signal seven_sig:std_logic_vector(6 downto 0);
CLK_out:out std_logic;
BEGIN
);
process(sig_in)
END Div_freq;
begin
case sig_in is
ARCHITECTURE rtl of Div_freq is
when "0000"=>
signal count : integer range 0 to 23456798;
seven_sig<="0111111";
begin process (rst,clk_in)
when "0001"=>
begin
seven_sig<="0000110";
if(rst='0')THEN
when "0010"=>
count<=0;
seven_sig<="1011011";
elsif(clk_in'event and clk_in='1')then
when "0011"=>
if(count=20000000)THEN
seven_sig<="1001111";
count<=0;
when "0100"=>
else
seven_sig<="1100110";
count<=count+1;
when "0101"=>
seven_sig<="1101101";
end if;
when "0110"=>
end if;
seven_sig<="1111101";
end process;
when "0111"=>
process(rst,clk_in)
seven_sig<="0000111";
begin
when "1000"=>
if(rst='0')then
seven_sig<="1111111";
clk_out<='0';
when "1001"=>
elsif(clk_in'event and clk_in='1')then
seven_sig<="1101111";
if(count<=10000000)THEN
when "1010"=>
clk_out<='1';
seven_sig<="1110111";
else
when "1011"=>
clk_out<='0';
seven_sig<="1111100";
end if;
when "1100"=>
end if;
seven_sig<="0111001";
when "1101"=>
end process;
seven_sig<="1011101";
when "1110"=>
END rtl;
seven_sig<="1111001";
when "1111"=>
seven_sig<="1110001";
WHEN OTHERS =>
seven_sig<="0111111"; LAB1
END CASE;
end process;
sig_out<= not(seven_sig);
library ieee;
use ieee.std_logic_1164.all;

entity bcd_count_top is port (

BCD
clk: in std_logic; library ieee;
rst: in std_logic; use ieee.std_logic_1164.all;
enable: in std_logic; use ieee.numeric_std.all;
count_U: out std_logic_vector(6 downto 0);
count_D: out std_logic_vector(6 downto 0));
entity bcd_count is port(
end entity;
clk: in std_logic;
architecture rtl of bcd_count_top is
rst: in std_logic;
component bcd_count is port ( enable: in std_logic;
clk: in std_logic; count_U: out std_logic_vector(3 downto 0);
rst: in std_logic; count_D: out std_logic_vector(3 downto 0)
enable: in std_logic;
count_U: out std_logic_vector(3 downto 0); );
count_D: out std_logic_vector(3 downto 0)
end bcd_count;
);
architecture RTL of bcd_count is
end component;
component seven_7 is port ( signal count_D_sig : integer range 0 to 9 := 0;
sig_in : in STD_LOGIC_VECTOR(3 DOWNTO 0); signal count_U_sig : integer range 0 to 9 := 0;
sig_out : out STD_LOGIC_VECTOR(6 DOWNTO 0)
); begin
end component; process (clk,rst)
component div is port ( begin
clk_in : in std_logic;
if (rst = '0') then
rst : in std_logic;
count_D_sig <= 0;
clk_out : out std_logic );
end component; count_U_sig <= 0;
elsif(clk'event and clk = '1') then
signal clk_out_sig : std_LOGIC; if(enable = '1')then
signal count_U_sig : std_LOGIC_VECTOR(3 downto 0); if(count_U_sig = 9)then
signal count_D_sig : std_LOGIC_VECTOR(3 downto 0); count_U_sig <= 0;
if(count_D_sig = 9)then
begin
count_D_sig <= 0;
U0: div port map (
else
clk_in=> clk,
rst => rst, count_D_sig <= count_D_sig+1;
clk_out=> clk_out_sig); end if;
else
U1: bcd_count port map ( count_U_sig <= count_U_sig +1;
clk => clk_out_sig, end if;
enable => enable, end if;
rst => rst,
end if;
count_U => count_U_sig,
end process;
count_D => count_D_sig);
count_U <= std_logic_vector(to_unsigned
U2: seven_7 port map ( (count_U_sig,4));
sig_in => count_U_sig, count_D <= std_logic_vector(to_unsigned
sig_out => count_U); (count_D_sig,4));
END RTL;
U3: seven_7 port map (
sig_in => count_D_sig,
sig_out => count_D);
end rtl ;
library ieee; LIBRARY IEEE;
use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all; USE IEEE.NUMERIC_STD.ALL;

entity bcd_count_min is ENTITY bcd_count_sec IS PORT (

port ( clk : IN STD_LOGIC;
clk: in std_logic;
rst: in std_logic; MONTRE rst : IN STD_LOGIC;
enable : IN STD_LOGIC;
enable: in std_logic; Count_U : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
min_up: in std_logic; Count_D : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sig_in : in std_logic_vector(3 downto 0); min_up : OUT STD_LOGIC
sig_out_U : out std_logic_vector(3 downto 0); );
sig_out_D : out std_logic_vector(3 downto 0) END bcd_count_sec;
);
end bcd_count_min; ARCHITECTURE RTL OF bcd_count_sec IS

architecture rtl of bcd_count_min is SIGNAL Count_U_sig : integer range 0 to 9 := 0;

signal count_U_sig: integer range 0 to 9 := 0; SIGNAL Count_D_sig : integer range 0 to 9 := 0;
signal count_D_sig: integer range 0 to 9 := 0;
begin BEGIN
process(clk, rst) PROCESS(clk,rst)
begin BEGIN
if rst = '0' then IF(rst='0') THEN
count_U_sig <= 0; Count_U_sig <= 0;
count_D_sig <= 0; Count_D_sig <= 0;
elsif rising_edge(clk) then ELSIF(clk'event AND clk='1') THEN
if enable = '1' then IF (enable ='1') THEN
if count_U_sig = 9 then IF (Count_U_sig = 9) THEN
count_U_sig <= 0; Count_U_sig <= 0;
if count_D_sig = 5 then IF (Count_D_sig = 5) THEN
count_D_sig <= 0; Count_D_sig <= 0;
else min_up <= '1';
count_D_sig <= count_D_sig + 1; ELSE
end if; Count_D_sig <= Count_D_sig + 1 ;
else min_up <= '0';
count_U_sig <= count_U_sig + 1; END IF;
end if; ELSE
end if; Count_U_sig <= Count_U_sig + 1 ;
end if; END IF;
end process; END IF;
END IF;
sig_out_U <= END PROCESS;
std_logic_vector(to_unsigned(count_U_sig, 4));
sig_out_D <= Count_U <=
std_logic_vector(to_unsigned(count_D_sig, 4)); STD_LOGIC_VECTOR(TO_UNSIGNED(Count_U_sig,4));
Count_D <=
end rtl; STD_LOGIC_VECTOR(TO_UNSIGNED(Count_D_sig,4));

END RTL;
library ieee; component div is
use ieee.std_logic_1164.all; port (
clk_in : in std_logic;
rst : in std_logic;
entity bcd_count_top is
clk_out : out std_logic
port ( );
clk : in std_logic; end component;
rst : in std_logic;
enable : in std_logic; signal clk_out_sig : std_logic;
count_sec_U : out std_logic_vector(3 signal count_sec_U_sig : std_logic_vector(3 downto 0);
signal count_sec_D_sig : std_logic_vector(3 downto 0);
downto 0);
signal count_min_D_sig : std_logic_vector(3 downto 0);
count_min_D : out std_logic_vector(3 signal count_min_U_sig : std_logic_vector(3 downto 0);
downto 0);
count_min_U : out std_logic_vector(3 begin
downto 0);
count_sec_D : out std_logic_vector(3 U0: div port map (
clk_in => clk,
downto 0)
rst => rst,
);
clk_out => clk_out_sig
end entity; );

architecture rtl of bcd_count_top is U1: bcd_count_sec port map (

component bcd_count_min is clk => clk_out_sig,
port ( enable => enable,
rst => rst,
clk : in std_logic;
count_sec_U => count_sec_U_sig,
rst : in std_logic; count_sec_D => count_sec_D_sig
enable : in std_logic; );
count_min_D : out std_logic_vector(3
downto 0); U2: bcd_count_min port map (
count_min_U : out std_logic_vector(3 clk => clk_out_sig,
enable => enable,
downto 0)
rst => rst,
);
count_min_U => count_min_U_sig,
end component; count_min_D => count_min_D_sig
);
component bcd_count_sec is
port ( U3: seven_7 port map (
clk : in std_logic; sig_in => count_min_D_sig,
sig_out => count_min_D
rst : in std_logic;
);
enable : in std_logic;
count_sec_U : out std_logic_vector(3 U4: seven_7 port map (
downto 0); sig_in => count_min_U_sig,
count_sec_D : out std_logic_vector(3 sig_out => count_min_U
downto 0) );
);
U5: seven_7 port map (
end component;
sig_in => count_sec_U_sig,
sig_out => count_sec_U
component seven_7 is );
port (
sig_in : in std_logic_vector(3 downto U6: seven_7 port map (
0); sig_in => count_sec_D_sig,
sig_out => count_sec_D
sig_out : out std_logic_vector(6 downto
);
0)
); end rtl;
library ieee; library ieee;
use ieee.std_logic_1164.all; entity pwm_top is port(
use ieee.std_logic_unsigned.all; clk : in std_logic;
rst : in std_logic;
sel_div : in std_logic_vector (1 downto 0);
entity pwm_device is port (
sel_duty : in std_logic_vector (1 downto 0);
clk : in std_logic;
out_port : out std_logic_vector (17 downto 0)
rst : in std_logic; );
div : in std_logic_vector(31 downto end pwm_top;
0); architecture rtl of pwm_top is
duty : in std_logic_vector(31 downto component pwm_device is port
0); (
out_port : out std_logic_vector (17 clk : in std_logic;
downto 0) rst : in std_logic;
); div : in std_logic_vector(17 downto 0);
duty : in std_logic_vector(17 downto 0);
end pwm_device;
out_port : out std_logic_vector (17 downto 0)

architecture RTL of pwm_device is

);
end component;
signal counter : std_logic_vector (31
downto 0); signal div : std_logic_vector(31 downto 0);
signal pwm_on : std_logic; signal duty : std_logic_vector(31 downto 0);
begin
begin
PWM div <= "00111111111111111111111111111111" when sel_div = "01"
else
divider: process (clk, rst) "00000000000000111111111111111111" when sel_div = "10"
else
begin
"00000000000000000000000000011110" when sel_div="11" else
if rst = '0' then
"00000000000000000000000000000000";
counter <= (others => '0');
duty <= "00000000000000000000000011111111" when sel_duty =
elsif clk'event and clk = '1' then "01" else
if counter >= div then "00000000000000011111111111111111" when sel_duty = "01"
counter <= (others => '0'); else
else "11111111111111111111111111111111" when sel_duty = "11"
counter <= counter + 1; else
end if; "00000000000000000000000000000011";
end if;
end process;
u0:pwm_device port map(
clk=>clk,
duty_cyle: process (clk, rst)
rst=>rst,
begin div=>div,
if rst = '0' then duty=>duty,
pwm_on <= '1'; out_port=>out_port
elsif clk'event and clk = '1' then
if counter >= duty then );
pwm_on <= '0'; end rtl;
elsif counter = 0 then
pwm_on <= '1';
end if;
end if;
end process;

out_port <= (others=> pwm_on);