;*********************************************************************

; File Name: Addition.asm

; Target System: C240x Evaluation Board
; Description: This sample program helps you get familiar with
;add 2 numbers that are stored as uninitialized variables and obtainning the
;2`s compliment of the result using F2407 EVM Development Board
;*********************************************************************
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Global symbol declarations
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.def _c_int0
.def PHANTOM
.def GISR1
.def GISR2
.def GISR3
.def GISR4
.def GISR5
.def GISR6
.bss RESULT,1
.bss ANS,1
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Address definitions
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.include f2407.h

;=====================================================================
; M A I N C O D E - starts here
;=====================================================================
.text
_c_int0
NOP
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Configure the System Control and Status Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF1 ;set data page

SPLK #0000000011111101b, SCSR1

; ||||||||||||||||
; FEDCBA9876543210
;* bit 15 0: reserved
;* bit 14 0: CLKOUT = CPUCLK
;* bit 13-12 00: IDLE1 selected for low-power mode
;* bit 11-9 000: PLL x4 mode
;* bit 8 0: reserved
;* bit 7 1: 1 = enable ADC module clock
;* bit 6 1: 1 = enable SCI module clock
;* bit 5 1: 1 = enable SPI module clock
;* bit 4 1: 1 = enable CAN module clock
;* bit 3 1: 1 = enable EVB module clock
;* bit 2 1: 1 = enable EVA module clock
;* bit 1 0: reserved
;* bit 0 1: clear the ILLADR bit
LACC SCSR2 ;ACC = SCSR2 register
OR #0000000000001011b ;OR in bits to be set
AND #0000000000001111b ;AND out bits to be cleared
; ||||||||||||||||
; FEDCBA9876543210
;* bit 15-6 0's: reserved
;* bit
5 0: do NOT clear the WD OVERRIDE bit
;* bit
4 0: XMIF_HI-Z, 0=normal mode, 1=Hi-Z'd
;* bit
3 1: disable the boot ROM, enable the FLASH
;* bit
2 no change MP/MC* bit reflects the state of the MP/MC* pin
;* bit
1-0 11: 11 = SARAM mapped to prog and data (default)
SACL SCSR2 ;store to SCSR2 register
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Other setup
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;----------------------------------------------------------------------
; Setup Core Interupts
;----------------------------------------------------------------------
LDP #0h
SPLK #0h,IMR ;Clear IMR
SPLK #3Fh,IFR ;Clear all pending Interupts
SPLK #02h,IMR ;ENABLE the desired Core
Interupt
;-----------------------------------------------------------------------
; RESET SECTION - ENDS
;-----------------------------------------------------------------------
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Setup the event manager interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_EVA ;set data page
SPLK #0FFFFh, EVAIFRA ;clear all EVA group A interrupts
SPLK #0FFFFh, EVAIFRB ;clear all EVA group B interrupts
SPLK #0FFFFh, EVAIFRC ;clear all EVA group C interrupts
SPLK #00080h, EVAIMRA ;disable EVA group A interrupts
SPLK #00000h, EVAIMRB ;disable EVA group B interrupts
SPLK #00000h, EVAIMRC ;disable EVA group C interrupts
LDP #DP_EVB ;set data page
SPLK #0FFFFh, EVBIFRA ;clear all EVB group A interrupts
SPLK #0FFFFh, EVBIFRB ;clear all EVB group B interrupts
SPLK #0FFFFh, EVBIFRC ;clear all EVB group C interrupts
SPLK #00000h, EVBIMRA ;disable EVB group A interrupts
SPLK #00000h, EVBIMRB ;disable EVB group B interrupts
SPLK #00000h, EVBIMRC ;disable EVB group C interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Enable global interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CLRC INTM ;enable global interrupts
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;Disable the watchdog timer
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
LDP #DP_PF1 ;set data page
SPLK #0000000011101000b, WDCR
; * ||||||||||||||||
; * FEDCBA9876543210
;* bits 15-8 0's reserved
;* bit 7 1: clear WD flag
;* bit 6 1: disable the dog
;* bit 5-3 101: must be written as 101
;* bit 2-0 000: WDCLK divider = 1

;-----------------------------------------------------------------------
; RESET SECTION - BEGINS
;-----------------------------------------------------------------------
LDP #DP_EVA ;set data
page
 SPLK #0000000001000101b, GPTCONA
SPLK #0, T1CNT
SPLK #40000,T1PR
SPLK #1042h,T1CON ;Continuous up-counting
;Disable
timer compare operation

;* Initialize ADC registers

LDP #DP_PF2
SPLK #0100000000000000b,ADCTRL1 ; Reset ADC module
NOP
SPLK #0011000000010000b,ADCTRL1 ; Take ADC out of reset
; ||||||||||||||||
; 5432109876543210
; 15 - RSVD | 14 - Reset(1) | 13,12 - Soft & Free
; 11,10,9,8 - Acq.prescalers | 7 - Clock prescaler
; 6 - Start/stop mode (0) | 5 - Int.priority (Hi.0)
; 4 - Seq.casc (0 - dual)
;* Setup a maximum of 01 conversions
SPLK #0, MAX_CONV ; Setup for 1 conversions
;* Program the conversion sequence. This is the sequence of channels that
;* will be used for the 16 conversions.
SPLK #3012h, CHSELSEQ1 ; Convert Channels 0,1,2,3

SPLK #0100000000000000b,ADCTRL2

SPLK #0010000001000000b,ADCTRL2 ; Start the conversions

; ||||||||||||||||
; 5432109876543210

;----------------------------------------------------------------------
;Enable Global Interupts
;----------------------------------------------------------------------
CLRC INTM ;Enable interrupts
CLRC SXM
CLRC XF
;----------------------------------------------------------------------
LDP #DP_PF2
SPLK #0000h,MCRA

END B END ;end of the program

;=====================================================================
; I S R - PHANTOM and unused GISRs
;
; Description: transferser converted adc value on to dac.
;
; Modifies: Nothing
;=====================================================================
GISR2
LDP #0h
SETC INTM ;disable all interrupts
CLRC SXM
LDP #0e8h ;load dp to event manager page
SPLK #0FFFh,EVAIFRA ;clear eventmanager
interrupts

LDP #0E1h ;set data page to adc

 SPLK #04000h,ADCTRL2 ;RESET ADC

SPLK #02000h,ADCTRL2 ; Start the conversions

CHK_EOS1:

LACC ADCTRL2 ; Wait for SEQ1 Busy bit to clear

AND #0001000000000000b ; BIT12 is loaded into TC bit of ST1
BCND CHK_EOS1,NEQ ; If TC=1, keep looping.

LACC RESULT0 ; Load conversion result of Channel

1
; from Ch1 buffer register into ACC
CLRC SXM
; enabling logic shifts of the accumulator.
RPT #5 ; Repeat the following instruction 6 times
SFR
; NOP
;AND #3FFh
;NOP
LDP #RESULT
SACL RESULT
LAR AR1,#2

SUB #0FFh
BCND LOOP1,LT

LDP #RESULT
LACC RESULT
SUB #200h
BCND LOOP2,LT

LDP #RESULT
LACC RESULT
SUB #0400h
BCND LOOP3,LT

LOOP1: LDP #DP_PF2

SPLK #1111111100001111b,PBDATDIR

LAR AR0, #09FFh

MAR *,AR0

DELAY1: RPT #255

NOP
BANZ DELAY1

LDP #DP_PF2
SPLK #1111111111110000b,PBDATDIR

LAR AR0, #09FFh

MAR *,AR0
DELAY2: RPT #255
NOP

BANZ DELAY2
 MAR *,AR1
BANZ LOOP1
B out1

LOOP2: LDP #DP_PF2

SPLK #1111111101010101b,PBDATDIR

LAR AR0, #05FFh

MAR *,AR0

DELAY3: RPT #255

NOP
BANZ DELAY3
LDP #DP_PF2
SPLK #1111111110101010b,PBDATDIR

LAR AR0, #05FFh

MAR *,AR0
DELAY4: RPT #255
NOP

BANZ DELAY4

MAR *,AR1
BANZ LOOP2
B out1

LOOP3: LDP #DP_PF2

SPLK #1111111100000000b,PBDATDIR

LAR AR0, #05FFh

MAR *,AR0
DELAY5: RPT #255
NOP
BANZ DELAY5
LDP #DP_PF2
SPLK #1111111111111111b,PBDATDIR

LAR AR0, #05FFh

MAR *,AR0
DELAY6: RPT #255
NOP
BANZ DELAY6

MAR *,AR1
BANZ LOOP3

out1:

CLRC INTM ;enable the interrupts

CLRC XF
RET
;=====================================================================
; I S R - PHANTOM and unused GISRs
;
; Description: Dummy ISR, used to trap spurious interrupts.
;
; Modifies: Nothing
;=====================================================================
PHANTOM B PHANTOM
GISR1 RET
;GISR2 RET
GISR3 RET
GISR4 RET
GISR5 RET
GISR6 RET