CY7C1019CV33

128K x 8 Static RAM

Features device has an automatic power-down feature that significantly
reduces power consumption when deselected.
• Pin and Function Compatible with CY7C1019BV33 Writing to the device is accomplished by taking Chip Enable
• High speed (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
— tAA = 8, 10, 12, 15 ns pins (I/O0 through I/O7) is then written into the location speci-
• CMOS for optimum speed/power fied on the address pins (A0 through A16).
• Data Retention at 2.0V Reading from the device is accomplished by taking Chip
• Center power/ground pinout Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
• Automatic power-down when deselected the memory location specified by the address pins will appear
• Easy memory expansion with CE and OE options on the I/O pins.
• Available in 32-pin TSOP II and 400-mil SOJ package The eight input/output pins (I/O0 through I/O7) are placed in a
Functional Description high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
The CY7C1019CV33 is a high-performance CMOS static operation (CE LOW, and WE LOW).
RAM organized as 131,072 words by 8 bits. Easy memory The CY7C1019CV33 is available in a standard 32-pin TSOP
expansion is provided by an active LOW Chip Enable (CE), an II and 400-mil-wide SOJ.
active LOW Output Enable (OE), and three-state drivers. This

Logic Block Diagram Pin Configuration

SOJ/TSOP II
Top View

A0 1 32 A16
A1 2 31 A15
A2 3 30 A14
I/O
0 A3 4 29 A13
INPUT BUFFER
CE 5 28
I/O
OE
A0 1 I/O0 6 27 I/O7
A1 I/O1 7 26 I/O6
I/O
ROW DECODER

A2 2
VCC 8 25 VSS
A3
SENSE AMPS

A4 I/O V SS 9 24 VCC
512 x 256 x 8 3
A5 I/O2 23 I/O5
A6
ARRAY 10
A7
I/O
4
I/O3 11 22 I/O4
A8 WE 12 21 A12
I/O A4 A11
5 13 20
A5 14 19 A10
I/O
POWER 6 A6
COLUMN 15 18 A9
CE DECODER DOWN
I/O A7 16 17 A8
WE 7
A 10

A 12
A 13
A 14
A 15
A 16
A9

A 11

OE

Selection Guide
7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15 Unit
Maximum Access Time 8 10 12 15 ns
Maximum Operating Current 85 80 75 70 mA
Maximum Standby Current 5 5 5 5 nA

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05130 Rev. *B Revised June 6, 2002
 CY7C1019CV33

Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage............................................ >2001V
(Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Operating Range
Power Applied............................................. –55°C to +125°C
Ambient
Supply Voltage on VCC to Relative GND[1] ... –0.5V to + 4.6V Range Temperature VCC
DC Voltage Applied to Outputs
Commercial 0°C to +70°C 3.3V ± 10%
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V Industrial –40°C to +85°C 3.3V ± 10%

Electrical Characteristics Over the Operating Range

7C1019CV33 7C1019CV33 7C1019CV33 7C1019CV33
-8 -10 -12 -15
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., 2.4 2.4 2.4 2.4 V
IOH = –4.0 mA
VOL Output LOW Voltage VCC = Min., 0.4 0.4 0.4 0.4 V
IOL = 8.0 mA
VIH Input HIGH Voltage 2.0 VCC 2.0 VCC 2.0 VCC 2.0 VCC V
+ 0.3 + 0.3 + 0.3 + 0.3
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage GND < VI < VCC, –1 +1 –1 +1 –1 +1 –1 +1 µA
Current Output Disabled
IOS[2.] Output Short VCC = Max., –300 –300 –300 –300 mA
Circuit Current VOUT = GND
ICC VCC Operating VCC = Max., 85 80 75 70 mA
Supply Current IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1 Automatic CE Max. VCC, CE > VIH 15 15 15 15 mA
Power-down Current VIN > VIH or
—TTL Inputs VIN < VIL, f = fMAX
ISB2 Automatic CE Max. VCC, 5 5 5 5 mA
Power-down Current CE > VCC – 0.3V,
—CMOS Inputs VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0

Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz, 8 pF
VCC = 5.0V
COUT Output Capacitance 8 pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Tested initially and after any design or process changes that may affect these parameters.

Document #: 38-05130 Rev. *B Page 2 of 10

 CY7C1019CV33

AC Test Loads and Waveforms[4]

8-ns devices: 10-, 12-, 15-ns devices:

Z=50Ω R 317Ω
OUTPUT 3.3V
OUTPUT
50 Ω 30pF*
* CAPACITIVE LOAD CONSISTS 30 pF R2
OF ALL COMPONENTS OF THE 1.5V 351Ω
TEST ENVIRONMENT

(a) (b)

High-Z characteristics:
R 317Ω
ALL INPUT PULSES 3.3V
3.0V
90% 90% OUTPUT
10% 10% 5 pF R2
GND 351Ω

Rise Time: 1 V/ns (c) Fall Time: 1 V/ns

(d)

Notes:
4. AC characteristics (except High-Z) for all 8ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load
shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).

Document #: 38-05130 Rev. *B Page 3 of 10

 CY7C1019CV33

Switching Characteristics[5] Over the Operating Range

7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 8 10 12 15 ns
tAA Address to Data Valid 8 10 12 15 ns
tOHA Data Hold from Address Change 3 3 3 3 ns
tACE CE LOW to Data Valid 8 10 12 15 ns
tDOE OE LOW to Data Valid 5 5 6 7 ns
tLZOE OE LOW to Low Z 0 0 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 4 5 6 7 ns
tLZCE CE LOW to Low Z[7] 3 3 3 3 ns
tHZCE CE HIGH to High Z[6, 7] 4 5 6 7 ns
tPU[8] CE LOW to Power-Up 0 0 0 0 ns
tPD[8] CE HIGH to Power-Down 8 10 12 15 ns
Write Cycle[9, 10]
tWC Write Cycle Time 8 10 12 15 ns
tSCE CE LOW to Write End 7 8 9 10 ns
tAW Address Set-Up to Write End 7 8 9 10 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Start 0 0 0 0 ns
tPWE WE Pulse Width 6 7 8 10 ns
tSD Data Set-Up to Write End 5 5 6 8 ns
tHD Data Hold from Write End 0 0 0 0 ns
tLZWE WE HIGH to Low Z[7] 3 3 3 3 ns
tHZWE WE LOW to High Z[6, 7] 4 5 6 7 ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document #: 38-05130 Rev. *B Page 4 of 10

 CY7C1019CV33

Switching Waveforms
Read Cycle No. 1[11, 12]

tRC

ADDRESS

tAA
tOHA

DATA OUT PREVIOUS DATA VALID DATA VALID

Read Cycle No. 2 (OE Controlled)[12, 13]

ADDRESS

tRC
CE

tACE

OE
tHZOE
tDOE
tHZCE
tLZOE HIGH
HIGH IMPEDANCE IMPEDANCE
DATA OUT DATA VALID
tLZCE
tPD
VCC tPU ICC
SUPPLY 50% 50%
CURRENT ISB

Write Cycle No. 1 (CE Controlled)[14, 15]

tWC

ADDRESS

tSCE
CE

tSA

tSCE
tAW tHA
tPWE

WE

tSD tHD

DATA I/O DATA VALID

Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Document #: 38-05130 Rev. *B Page 5 of 10

 CY7C1019CV33

Switching Waveforms (continued)

Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]

tWC

ADDRESS

tSCE
CE

tAW tHA
tSA tPWE
WE

OE

tSD tHD

DATA I/O NOTE 16 DATAIN VALID

tHZOE

Write Cycle No. 3 (WE Controlled, OE LOW)[15]

tWC

ADDRESS
tSCE

CE

tAW tHA
tSA tPWE

WE

tSD tHD

DATA I/O NOTE 16 DATA VALID

tHZWE tLZWE

Note:
16. During this period the I/Os are in the output state and input signals should not be applied.

Document #: 38-05130 Rev. *B Page 6 of 10

 CY7C1019CV33

Truth Table
CE OE WE I/O0–I/O7 Mode Power
H X X High Z Power-Down Standby (ISB)
X X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)

Ordering Information
Package Operating
Speed (ns) Ordering Code Name Package Type Range
8 CY7C1019CV33-8VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019CV33-8VI V33 32-Lead 400-Mil Molded SOJ Industrial
10 CY7C1019CV33-10VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019CV33-10ZC ZS32 32-Lead TSOP II
CY7C1019CV33-10VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-10ZI ZS32 32-Lead TSOP II
12 CY7C1019CV33-12VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019CV33-12ZC ZS32 32-Lead TSOP II
CY7C1019CV33-12VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-12ZI ZS32 32-Lead TSOP II
15 CY7C1019CV33-15VC V33 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019CV33-15ZC ZS32 32-Lead TSOP II
CY7C1019CV33-15VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-15ZI ZS32 32-Lead TSOP II

Document #: 38-05130 Rev. *B Page 7 of 10

 CY7C1019CV33

Package Diagram

32-Lead (400-Mil) Molded SOJ V33

51-85033-A

51-85033-*B

Document #: 38-05130 Rev. *B Page 8 of 10

 CY7C1019CV33

Package Diagram (continued)

32-Lead TSOP II ZS32

51-85095

All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05130 Rev. *B Page 9 of 10

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
 CY7C1019CV33

Document Title: CY7C1019CV33 128K x 8 Static RAM

Document Number: 38-05130
Issue Orig. of
REV. ECN NO. Date Change Description of Change
** 109245 12/16/01 HGK New Data Sheet
*A 113431 04/10/02 NSL AC Test Loads split based on speed
*B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved ICC limits

Document #: 38-05130 Rev. *B Page 10 of 10