Solid-State Electronics 52 (2008) 1127–1139

Contents lists available at ScienceDirect

Solid-State Electronics
journal homepage: www.elsevier.com/locate/sse

Review

ESD protection design for I/O libraries in advanced CMOS technologies

Oleg Semenov *, Sergei Somov
Freescale Semiconductor LLC, Research Laboratory, Savelkinsky Proezd 4, Floor 11, Zelenograd, Moscow 124489, Russia

a r t i c l e i n f o a b s t r a c t

Article history: There are several approaches for ESD protection of integrated circuits. This paper provides practical
Received 17 November 2007 guidelines to I/O library designers to choose the right methodology for ESD protection of I/O libraries
Received in revised form 8 May 2008 in advanced CMOS technologies. Guidelines are provided predominantly for low-voltage I/O libraries that
Accepted 12 May 2008
are commonly used for general purpose interfaces and industrial low-voltage interfaces such as DDR,
Available online 27 June 2008
MLB, USB, etc. Additionally, some general background issues of ESD protection methodologies used in
The review of this paper was arranged by the industry are considered. This paper is focused on HBM and MM ESD protection solutions. Special
Prof. S. Cristoloveanu CDM ESD protection solutions are not considered.
Ó 2008 Elsevier Ltd. All rights reserved.
Keywords:
Electrostatic discharge (ESD)
Failure mechanisms
ESD devices
I/O architecture

Contents

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
1.1. Scope of the paper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
2. I/O ring architecture for wire-bond packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
3. Basic ESD devices for I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
3.1. Non-snapback protection devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
3.1.1. p–n Junction diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
3.1.2. Zener diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
3.2. Snapback protection devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
3.2.1. Gate grounded MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
3.2.2. Silicon controlled rectifier (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
3.2.3. Lateral diffused MOS (LDMOS) transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
4. ESD device modeling for local and distributed clamps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
4.1. ESD simulations of I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
4.2. Compact modeling of ESD diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
5. ESD protection networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
5.1. Local based ESD protection networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
5.2. Distributed ESD protection networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
5.3. Comparison of local and distributed ESD protection networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
5.4. ESD protection network across different power domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
6. Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138

* Corresponding author. Tel.: +7 495 536 5062; fax: +7 495 787 2804.
E-mail addresses: [email protected], [email protected] (O. Semenov).

0038-1101/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2008.05.008
1128 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

1. Introduction scaling down of the device sizes, the gate oxide thickness is also re-
duced resulting in a decrease of the VBD Typically, this defect re-
Electrostatic discharge (ESD) is a common phenomenon in the sults in a low-ohmic short of gate and drain terminals in
nature. Its name comes from the fact that different materials can damaged transistor [4].
carry static positive or negative charges resulting into a built-in (ii) Junction filamentation and spiking: Junction filamentation
static voltage. The amount of this static charge depends on the causes an increase in the reverse bias leakage of a p–n junction.
material characteristics and from external parameters like the rel- In the worst case, the junction is shorted. The ESD event causes
ative humidity. But once the statically charged material is put in current to flow through the junction. The high power dissipated
contact with a grounded object (large enough to act as ground), in the junction causes the temperature to rise until a region of sil-
charge balance will be restored through a discharge of the charged icon melts. When silicon melts, its resistance drops by a factor of
material towards the ground. The discharge is extremely fast, in 30 or more [5]. This causes more of the current to flow in the nar-
the order of tens of nanoseconds. ESD is a subset of the class of fail- row, melted region which further heats the melted region, leading
ure causes known as electrical overstress (EOS). to thermal runaway. This phenomenon is often referred to as the
As microelectronics technology continues shrink to nano-metric second or thermal breakdown [6]. In MOSFET devices the drain
dimensions, ESD damage in integrated circuits has become one of junction filamentation is typically located close to the surface in
the major reliability issues. Several studies carried out over the the gate to drain overlap region, where the dielectric acts a thermal
past two decades ranked ESD and EOS (electrical overstress) as insulator. Therefore, devices, in which hot spot regions are located
the major cause for field returned ICs, as it shown in Table 1-1. It deeper in the silicon (like BJT, SCR and thick field oxide device), are
was found that ESD related failures can reach up to about 70% fail- used as a high reliable ESD protection devices. The damage thresh-
ure modes, depending on the product type [1]. olds are lower for aluminum contacts because the aluminum–sili-
The thinner gate oxide and shallower junction depth used in the con eutectic forms at 577 °C rather than at the melting point of
advanced technologies make them very vulnerable to ESD damage. silicon (1415 °C) [7].
The silicidation reduces the ballast resistance provided by drain (iii) Metallization and polysilicon burn-out: Thin-film fusing af-
contact to gate edge spacing (DCGS) with at least a factor of 10. fects each conducting film in a circuit. These include the metal
As a result, scaling of the ESD performance with device width is interconnects, polysilicon interconnect, and thin-film and diffused
lost and even zero ESD performance is reported for standard sili- resistors. The most susceptible to damage are circuits with thin-
cided devices [2]. film resistors. It is important during the chip design that the resis-
ESD failures are caused by at least one of three sources: local- tor be made wide enough to handle an ESD current pulse for the
ized heat generation, high-current densities, and high electric field desired level of protection. Because of the high temperatures in-
intensities. The current densities associated with an ESD stress duced by the ESD pulse, a metal or polysilicon line, located close
unavoidably imply high power dissipations, with consequent rise to the hot spot region in p–n junction, can be melted resulting in
in the lattice temperature that often results in thermal damages. a metal open circuit.
When the rate of heat generation becomes greater than the rate
of heat removal, the junction temperature in hot spot region starts 1.1. Scope of the paper
to increase and thermal runaway occurs.
For CMOS circuits, the electric field intensity refers to the volt- A typical system-on-chip (SOC) IC includes digital logic, RAM
age developed across the dielectric and junctions in the circuit. The memory, microprocessor core, analog, and mixed-signal circuitry.
gate oxide is the most vulnerable dielectric owing to its thinness. Analog and mixed-signal circuitry is very sensitive to all sources
Structural defects and sharp corners in layouts result in higher of noise, but in SOC systems switching noise from the digital cir-
electric field and current crowding making failure more likely at cuitry becomes a dominant source of noise frequently limiting ana-
these points. log performance. To minimize cross-talk between different blocks
ESD-induced failures can be grouped in two categories: soft and IC designers take great care to isolate analog circuitry from digital
hard failures. In case of soft failure, the device has a partial damage by providing custom layout moats and powering up each block
typically resulting in an increased leakage current that might not from a separate, filtered power supply. While the design of individ-
meet the requirements for a given circuit. Still, the basic function- ual ESD protection for each block is important, the key to ESD
alities of the device are operative but without any guarantee about robustness of mixed-signal SOC is a proper ESD protection archi-
potential latency effects. In case of hard failures, the basic function- tecture for the whole chip.
alities of the device are completely destroyed during the ESD event. ESD protection is usually achieved by implementing an ESD
Each ESD failure mode is traced to one or more of three fundamen- protection device in an I/O cell, and placing a power clamp device
tal damage mechanisms discussed below [3]. between different power and ground domains to form an ESD dis-
(i) Oxide rupture (breakdown): Typically, gate oxides can with- charge return path with low impedance. With peripheral I/Os, cir-
stand an electric field of 6–10 MV/cm before it’s breaking down. In cuit damage after ESD stress is relatively easily detectable.
CMOS technology input/output buffers require an ESD protection However, with internal core circuit failure it is more difficult to
circuit that limits the peak voltage during an ESD event that could find out the ESD-induced failure site and fix the design. Since the
cause irreversible failure (rupture) of the gate oxide. Being the peak internal core device failure is induced mainly by gate oxide dam-
voltage (Vpeak) the maximum voltage across the protected device, it age, this makes it even more difficult to observe and quantify the
is necessary to maintain a margin between this voltage and the ESD-induced failure [8,9].
gate oxide breakdown (VBD) to avoid oxide failures. The gate oxide In this paper, we analyze the I/O architecture used for VLSI/
breakdown (VBD) is a critical function of its thickness. But with the SOC applications implemented in sub-100 nm CMOS technologies

Table 1-1
The EOS/ESD failure percentage as total failure modes studied by the different author over the years, adopted from [2]

Percentage 51% 72% 23% 38% 45% 43% 39%

Author (year) Green (88) McAteer (88) Euzent (91) Merill (93) Wagner (93) Shumway (95) Brodbeck (97)
 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139 1129

and provide recommendations for appropriate choice of ESD pro-

tection networks (local or distributed ESD protection) for digital
and mixed-signal I/O libraries. This paper is organized as follows.
In Section 2, we review the I/O pad architecture and discuss the
ESD challenges in VLSI design. The basic ESD devices for I/Os
are analyzed in Section 3. The basic principles of ESD device mod-
eling are described in Section 4. The design issues of local and
distributed ESD protection networks and their comparison are
given in Section 5. Finally, the conclusions are summarized in
Section 6.

2. I/O ring architecture for wire-bond packages

Conventional pad design uses the chip periphery for pad con-
nections and pad drivers. The pad driver and ESD circuit of each
pad occupies a certain amount of space, disallowing any other cir-
cuitry within that space. Furthermore, the peripheral pad design
often requires that a signal be routed great distances from the core
circuitry to the pad frame. This cause extra delay and/or require a
buffer stage. To further reduce the chip size, grouped I/O circuits
should be used. It is achieved through a complete reorganization
of the I/O circuits into groups of I/O functions with identical type.
For example, we can create a macro of a group of output drivers,
create another of groups of tri-state buffers and input receivers
and so on. Fig. 2-1. Typical pad ring structure [10].
With reducing of chip dimensions and increasing of operating
frequency requirements, the IR drop on a wire-bond chip, where
pads are placed at the die periphery, is becoming a dominant factor
in the determining of chip frequency. The typical power ring struc-
ture of wire-bond chip is shown in Fig. 2-1 [10]. There is a global
power ring across the chip perimeter. Power (P)/Ground (G) pads
are placed all across the chip periphery. Typically, the global power
ring is drawn in higher metal layers, since the resistance of the
higher metal layers is relatively less as compared to the lower lay-
ers. Note, that all the current that flows in the chip passes through Fig. 2-2. Typical placement of power/ground cells in an I/O bank. POP is the probe
the global power ring, therefore these wires are a candidate for over passivation region, BOP is the bond over passivation region and BOA is the
higher IR drop. A chip power network can be modeled as a cur- bond over active region.
rent/voltage sink/source network and the optimization equations
can be solved to realize the optimal P/G pad placement. This chip
floorplan and IR drop analysis can be performed in a VoltageStorm
software tool developed by Cadence [11].
To develop the area efficient I/O bank, it is necessary to find the
answer on the following question ‘‘How frequently would we like
to place standalone P/G pad cells?” Obviously, we need lots of P/
G cells for good electrical performance. The typical placement of
power/ground cells in an I/O bank is shown in Fig. 2-2. The general
rule is to place 1 P/G pair for every 10 I/Os.
Typically, approximately 17% of all pad cells in the I/O ring are
P/G cells. However, we must often settle for far fewer P/G cells to
Fig. 2-3. The pad and ESD integration scheme (OVDD bus segment) developed for
fit in pad limited I/O rings. This results in less than optimum I/O 90 nm CMOS I/O library.
pad to P/G pad ratio. In addition, the I/Os most distant from P/G
pads are often power starved and power supply bus resistance/
inductance are serious concerns. As an example of ESD and PAD 3. Basic ESD devices for I/Os
integration issues in sub-100 nm CMOS VLSIs, the 90 nm CMOS
I/O library is discussed below. ESD protection circuits should be able to handle a large amount
This I/O library used the distributed ESD protection network of ESD current without being destroyed. Various semiconductor
that is considered in details in Section 5. For the effective and ro- devices can be used for the ESD protection circuits. In this chapter,
bust ESD protection, every unique OVDD bus segment must be ter- the most important and generally used protection devices are dis-
minated with OVDD/OVSS dedicated supply cells. In addition, it is cussed. Based on the shape of I–V characteristic of ESD devices,
necessary to place an 18 lm wide trigger circuit spacer cell every they are divided into two main categories: non-snapback devices
10–12 pads. This spacer cell is included as a part of the IO library. and snapback devices.
Fig. 2-3 illustrates the OVDD Bus Segment. I/O pads of the same I/O
supply voltage are grouped together to form an OVDD segment. 3.1. Non-snapback protection devices
There can be several OVDD segments of the same voltage scattered
around the chip to get the pads closer to their drivers or receivers A typical request for RF and high-speed digital pads is approxi-
inside the core. mately 200 fF. This target not only includes the ESD protection
1130 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

Fig. 3-1. ESD diodes: (a) p+/n-well diode, (b) STI (shallow-trench-isolation) diode, (c) poly-gated diode.

be shortened. Hence, the ESD protection level of poly-gate diode

should be higher in comparison to STI diode at the same layout
area. However, for RF ESD applications, the poly-gated diode has
the additional gate oxide capacitance, that causes the RF perfor-
mance to degrade more than STI diode.

3.1.2. Zener diodes

In addition to p–n junction diodes, zener diodes can be used in
ESD protection circuits. The advantage of the zener diode over a
regular reverse-biased p–n junction is its lower triggering (junc-
tion breakdown) voltage (3–6 V) in reverse-biased mode. The main
Fig. 3-2. Cross-section of ESD zener diode. idea is to create the diode using high doped n+ and p+ regions,
thereby ensuring the low triggering voltage. Zener diode is created
by using n+ and p+ diffusion regions [13]. Fig. 3-2 shows the cross-
devices but also the bond pad itself. In order to fulfill these require- section of this diode with silicide block option.
ments, diodes are commonly used for ESD protection in high-speed
I/O circuits. 3.2. Snapback protection devices

3.1.1. p–n Junction diodes In snapback protection devices by increasing the pad voltage
Diodes have highly doped p+ and n+ diffusion regions separated device goes into breakdown region. After breakdown, due to an
by a low-doped region. At low current level, the low-doped region internal negative feedback mechanism, the voltage across the de-
is like a resistor in series with either the anode or cathode of the vice drops to a holding point. MOSFET and Silicon Controlled Rec-
diode. However, at high-current level, the low-doped region be- tifier (SCR) are the most important snapback ESD devices in the
comes strongly conductivity modulated, so the on-resistance of CMOS technology.
the diode at high-current level is much lower than at low current
level. This characteristic is good for diode in ESD condition. Typi- 3.2.1. Gate grounded MOSFET
cally, p–n diodes are used in a forward biased mode for ESD protec- The simplest design of a MOS transistor for ESD protection is the
tion. In a standard CMOS process, three different implementations grounded gate configuration where the gate of the transistor is
of diodes can be created, as it shown in Fig. 3-1: (i) p+/n-well diode, connected to ground. Fig. 3-3a shows the cross-section of a
(ii) STI (shallow-trench-isolation) diode and (iii) poly-gated diode. grounded gate NMOS (GG-NMOS) transistor. The DC characteris-
p+/n-Well diodes are widely used in all CMOS technologies. They tics of the GG-NMOSFET is depicted in Fig. 3-3b. As the drain volt-
have good ESD robustness and area efficient. The disadvantages age increases due to the ESD event applied for the I/O pad, the
of these diodes are the leakage at high temperatures and strong drain-substrate junction becomes more reverse biased until it goes
influence of bus resistance. In STI diode [13], the n+ diffusion (cath- into avalanche breakdown. At this point, the drain current in-
ode) and p+ diffusion (anode) are separated by shallow-trench-iso- creases, and the generated holes drift towards the substrate con-
lation (STI). The poly-gated diode [12] uses a poly-gate to isolate its tact (Isub), thereby increasing the substrate voltage (base voltage
cathode (n+) and anode (p+). Because the design rule of minimum of the parasitic bipolar transistor) and makes the base–emitter
gate length is smaller than the minimum STI length, the distance junction of the parasitic bipolar transistor more forward biased.
between n+ diffusion and p+ diffusion in the poly-gate diode can As the base–emitter voltage reaches 0.7 V, the parasitic bipolar

Fig. 3-3. Cross-section of ESD GG-NMOSFET (a) and its I–V characteristics (b).
 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139 1131

Fig. 3-4. Cross-section of ESD SCR structure (a) and its equivalent circuit (b).

degraded; (iii) It2 determines the robustness of ESD protection de-

vice and should be as high as possible; (iv) Vh should be greater
than VDD. Otherwise, GG-NMOSFET may turn on during the normal
operating conditions, which is called latch-up. Typically, Vh should
be 10–20% more than VDD.

3.2.2. Silicon controlled rectifier (SCR)

Silicon controlled rectifier (SCR) is another active device that is
often used as a ESD protection element. Fig. 3-4a shows a cross-
section of conventional SCR. It consists on a p–n–p–n structure.
The p+ diffusion in the n-well forms the anode, and the n+ diffusion
in the p-sub forms the cathode of the SCR. As an ESD protection de-
vice, the n-well contact is connected to the anode, and the p-sub
Fig. 3-5a. Cross-section of ESD LVTSCR structure. contact is connected to the cathode. The anode is connected to
the I/O pad, and the cathode is connected to the ground. The equiv-
alent circuit of the SCR is shown in Fig. 3-4b.
As the anode voltage increases, the n-well to p-sub junction
Anode Cathode becomes more reverse biased until it goes into avalanche break-
down. Typically, the gain of the npn transistor is an order of
magnitude higher than that of the pnp transistor. Therefore, the
n-well n+ p+ p+ n+ n-well npn transistor turns on more easily than the pnp transistor.
When the npn transistor turns on, its current will generate a
R1 R4
Q1 Q3 voltage drop across Rn-well and will turn on the pnp transistor
Q2
as well. When it’s happened, the anode voltage is reduced to
Vh. The I–V characteristics of the SCR is similar to that of the
p-sub
R2 R3 GG-NMOSFET. The typical value of Vt1 of GG-NMOSFET is be-
tween 5 and 10 V, while Vt1 for SCR is between 20 and 25 V.
Fig. 3-5b. Cross-section of dual SCR ESD protection structure. The value of Vh for GG-NMOSFET is usually between 3 and 5 V,
while Vh for SCR is around 1.5 V. The most important drawback
of SCR is its high first breakdown voltage (Vt1), which is due to
transistor will turn on. The drain voltage at this point is Vt1 (trig- a high avalanche breakdown voltage of n-well/p-sub junction.
gering voltage). This bipolar action will generate more current, In order to lower the Vt1 of SCR, the n+region and the gate elec-
and therefore, there is no need to keep the drain voltage at Vt1 to trode can be inserted between anode and cathode terminals, as it
maintain the drain current. Hence, the drain voltage will reduce is shown in Fig. 3-5a. This configuration of SCR is called the low-
to Vh (holding voltage), and snapback behavior will be observed. voltage triggered SCR (LVTSCR). LVTSCR may have the triggering
When the bipolar transistor is turned on, the increasing of drain voltage (Vt1) approximately 4–6 V, that is suitable for sub-
voltage increases the current until the thermal damage occurs. This 100 nm CMOS technologies. Note, that the NMOS transistor in
point is called the second breakdown point and the voltage and LVTSCR structure reduces the breakdown voltage of NPN parasitic
current at this point are Vt2 and It2, respectively. Vt1, Vh, Vt2, and transistor (the gate-assisted NPN breakdown mode). The adding a
It2 are the most important parameters. bridging n+ region between the n-well and p-sub reduces the
In order to protect a circuit against the ESD event, the following breakdown voltage of SCR structure since the n+/p-sub break-
requirements must be met: (i) Vt1 must be less than the gate oxide down is lower that the n-well/p-sub junction breakdown. To pro-
breakdown voltage to protect the gate during an ESD event. This tect I/O driver from the positive and negative ESD stresses two
assures that the GG-NMOSFET will turn on before the gate oxide SCR structures should be used in parallel with the I/O driver. This
breakdown occurs in I/O drivers; (ii) Vt2 must be greater than Vt1 will double the parasitic capacitance added to the pad. Therefore,
to ensure the uniform triggering of multi-finger ESD transistor. based on SCR operation, a dual SCR protection structure has been
By doing this, even if one finger triggers first, the voltage build- developed for high-speed I/O applications [27,28]. The cross-sec-
up can turn on other fingers before the first finger reaches the sec- tion of dual SCR protection structure is shown in Fig. 3-5b. This
ond breakdown region. Otherwise, the effective width of the device ESD protection structure can protect I/O driver from the positive
is decreased and the performance of the GG-NMOSFET will be and negative ESD stresses.
1132 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

on process and device simulations. This approach requires all the

information about materials, topology and doping profiles speci-
fied for the given technology. In practice, the ESD design groups
are typically have limited technology information.
In addition, they cannot modify technology steps to optimize
ESD devices, because ICs technology is primarily optimized for
functional or core transistors. Therefore if the process simulations
are not possible due to the limited technology information, the fol-
lowing strategy for ESD device calibration can be used:
Fig. 3-6. Cross-section of ESD LDMOS transistor.
(1) At the first step, all available information from the technology
file in a given circuit simulation environment should be col-
3.2.3. Lateral diffused MOS (LDMOS) transistor lected for the given technology. For example, in case of ESD
The lateral diffused MOS (LDMOS) transistor is a power tran- MOSFET it can be gate oxide thickness (Tox), effective channel
sistor that is commonly used in high-voltage circuit designs in length (Leff), channel and polysilicon dopings, threshold volt-
SMARTMOS technologies. The cross-section of typical LDMOS age (Vth), leakage and drive currents at normal operating con-
transistor is shown in Fig. 3-6. The drain terminal is formed in ditions and device geometry parameters. These parameters
N-well region and body and source terminals are formed in P- should be used to create the device structure in a device sim-
well region. In LDMOS transistor, the avalanche generation is ini- ulator and calibrate it at normal operating conditions.
tiated by the n+ buried layer (NBL)/P-well junction. The gate (2) For ESD devices, accurate high-current device models, which
oxide thickness and effective channel length are determined by adequately capture the device breakdown and post-break-
the required operating voltage. For example, 500 Å of gate oxide down behavior, are of particular interest. For MOSFET devices
thickness and 1 lm of effective channel length are typically used this means that simulation models must match experimental
for 70 V applications. The width of LDMOS ESD devices is varied triggering voltage (Vt1) and post-snapback ‘‘on” resistance
in a wide range (200–2400 base–emitter) to pass 2–6 kV HBM (Ron). Mixed-mode simulation is used to run a snapback anal-
ESD stress. ysis of the device. Less well-known device parameters such as
The typical ESD protection design based on LDMOS transistor typically doping profile are adjusted to achieve a match to
triggered by the string of Zener diodes is shown in Fig. 3-7. Zener available experimental data, which can be TLP I–V curve. This
clamps are used to prevent the device from entering bipolar break- procedure is generally known as inverse modeling.
down when transient ESD peaks appear at the drain of LDMOS de- (3) If sufficient agreement could not be achieved by previous
vice. Under ESD event, the LDMOS operates as a saturated MOSFET steps, the physical model coefficients in device simulator
and therefore a lower drain clamp (triggering) voltage should re- are adjusted as a final calibration step.
sult in better ESD performance. To optimize the ESD performance
of ESD protection design shown in Fig. 3-6, a 10 KX resistor can This calibration strategy was used for design of ESD protection
be inserted between the gate of LDMOS transistor and ground. devices (MOSFET and LVTSCR) implemented in 180 nm and
The Zener diodes should be sufficiently large (>50 lm) to survive 130 nm CMOS technologies [15,16]. The synthesized MOSFET
the ESD current before the LDMOS conduction begins. structure based on the reverse engineering approach is shown in
Fig. 4-1. The doping profile parameters were adjusted to match
4. ESD device modeling for local and distributed clamps electrical test data, which included I–V characteristics at normal
operating conditions and TLP data.
Moving from the given technology to the next one is a major A mixed-mode (circuit-device) simulator was used to perform
challenge for ESD development, since in general there can be no quasi-DC snapback simulations. The obtained results were com-
simple and smooth transfer of protection concepts from the pre- pared with TLP data as shown in Fig. 4-2. The TLP pulse duration
ceding technology. The standard ESD design methodology is based was 100 ns and the rise time (10–90%) was 10 ns. The excellent

Fig. 3-7. ESD protection design based on 20 V LDMOS (a) and 45 V LDMOS [14].
 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139 1133

Fig. 4-3. I/O pre-buffer and ESD protection circuit simulated in mixed-mode,
adopted from [17].
Fig. 4-1. Synthesized ESD N-MOSFET structure (0.18 lm CMOS technology),
adopted from [15].

Fig. 4-2. ESD N-MOSFET (50 lm width): I–V TLP data and simulation results,
adopted from [15]. Fig. 4-4. Mixed-mode simulation results of circuit shown in Fig. 4-3 at 2 kV HBM
ESD stress, adopted from [17].

agreement is seen between measured data and simulation results. 4.2. Compact modeling of ESD diodes
A good match was obtained for the key ESD parameters such as
triggering voltage (Vt1), holding voltage (Vh) and post-snapback ESD protection networks comprising forward biased gated
‘‘on” resistance (Ron). diodes and transient triggered active MOSFET rail clamps have
been proven effective on advanced CMOS bulk and SOI products.
4.1. ESD simulations of I/Os A key advantage of this protection strategy is the possibility to sim-
ulate ESD protection network in Cadence environment, since for-
Mixed-level circuit-device simulation is a powerful tool for the ward biased gated diodes and transient triggered ESD MOSFET do
ESD stress analysis of semiconductor products. Physical finite-ele- not operate in snapback mode. However, since these diodes should
ment (FEM) level models are utilized for MOSFETs and other de- operate in a high-current ESD regime, a special SPICE compact
vices involved in the high-voltage high-current ESD event. model should be developed. In 90 nm SOI CMOS technology devel-
Embedding these devices in realistic circuit simulation environ- oped by Freescale semiconductor, the p+/N-well ESD diodes are
ment including probe, chip and interconnect parasitics (R, L, C) as- used, since these diodes have slightly less parasitic capacitance
sures the required level of accuracy. CPU requirements (time and than the n+/P-well diodes [18]. The equivalent electrical circuit of
memory) for such simulations depend on the total number of de- a special compact diode model is depicted in Fig. 4-5.
grees of freedom. Each circuit element contributes to this number, In this model, the diode p–n junction is modeled by the stan-
with FEM-level devices contributing the most. On a modern PC, dard gated SOI diode model D0 available in the design kit of this
complete I/O buffer circuits can be implemented with up to 20 technology with one modification: the base resistance of D0 is set
MOSFETs modeled at the FEM level. Fig. 4-3 represents the ESD to zero and modeled by a separate temperature dependent resistor
protection circuit and I/O pre-buffer simulated in mixed-mode. Rb as specified in Eq. (1). The resistance of the metallization of the
Each transistor in this circuit was implemented as a physical device diode fingers Rm is calculated similar. Both resistors are described
structure (see Fig. 4-2) optimized and calibrated for 180 nm CMOS by a transient self heating model implemented in Verilog-A, which
technology. The results of mixed-mode simulations at 2 kV HBM accounts for a linear temperature dependence
ESD stress are depicted in Fig. 4-4 [17]. In this figure, Vg_M0 is
the gate voltage of ESD transistor M0 and Vpad is the pad voltage lb
Rb ¼  q  ð1 þ ab  V temp;b  1 K=VÞ ð1Þ
at 2 kV HBM ESD stress applied to the I/O pad. wb 0;b
1134 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

5. ESD protection networks

The internal ESD protection requires the placement of adequate

on-chip protection devices on the I/O and on the power supply pins
to reliably bypass the ESD energy before it can damage the sensi-
tive core circuits. This protection circuits should not interfere with
the I/O circuits during its normal operation. A perfect protection
device should have the following characteristics:

– Very low on-resistance.

– Triggering voltage should be above the worst-case operating
supply voltage (VDD + 10%).
– Triggering voltage should be below the voltage level that can
damage protected devices.
– Almost instantaneous turn-on time.
– Very high energy handling capability.
– Only trigger during ESD events, not during normal operation.
– Very low parasitics to minimize performance degradation of I/
O circuit.
– Consumes small area.
Fig. 4-5. ESD diode compact model with transient self heating [18].

These criteria provide a list of optimizations and compromises

to be struck when the protection circuit is designed.
The parameters lb and wb define the length and width of the inter-
connect structure, q0,b denotes the sheet resistance at ambient tem-
5.1. Local based ESD protection networks
perature, ab is the linear temperature coefficient, and Vtemp,b the
equivalent voltage for the temperature increase. To obtain the time
Different ESD protection elements should be combined to form
dependent temperature of the resistor, an equivalent thermal RC
a protection network. One well-known local based I/O ESD protec-
network (Rth,b and Cth,b are model fitting parameters) is included
tion circuit is a pi-network as shown in Fig. 5-1 [19].
in the model sub-circuit. The dissipated current per unit area (Eq.
During the ESD stress, the secondary (optional) ESD clamp trig-
(2)) in the resistor Rb is provided by the Verilog-A model as a cur-
gers first and then the voltage drop through the resistor is in-
rent source output IP,b that drives the RC network (I is the current
creased and it triggers the primary ESD clamp. Subsequently,
through the resistor Rb)
most of ESD energy is bypassed through the primary ESD clamp.
Rb  I 2 lm2 Typically, primary and secondary clamps are implemented using
IP;b ¼ 1 ð2Þ the snapback ESD devices that were described in Subsection 3.2.
wb  lb V
The example of application of local based ESD protection approach
The temperature increase appears as an equivalent voltage Vtemp,b for high-voltage NLDMOS power arrays is shown in Fig. 5-2a [20].
across the RC network, and is used in Eq. (1) to calculate the Rb in- In this example, only one local clamp is used to protect I/O pad. The
crease due to self heating. This compact model has been calibrated major advantages of the pi-protection network are the voltage
to diode and metal line high-current pulse data with varying TLP division and safer triggering of ESD devices.
pulses. The TLP measurement data versus data obtained from the The first advantage ensures the lower voltage stress in the inter-
ESD diode compact model is shown in Fig. 4-6. In addition, the nal node, and the second one gives lower trigger voltage in
TLP curve for a typical 90 nm bulk STI bound diode is shown in this comparison with using the primary ESD clamp only. The disadvan-
figure for comparison. tage of local based ESD protection networks in sub-100 nm CMOS
technologies is that the ESD protection devices must be located in
each I/O and VDD/VSS pads and the size of these ESD devices is sig-
nificantly increased with technology scaling since the distractive
voltage of core transistors is reduced with scaling. For example,
to pass the minimal ESD requirements (2 kV HBM ESD stress) the
NMOS transistor in ESD clamp shown in Fig. 5-2a should be
400 lm widths [20]. The ESD current path between VDD and VSS
is provided by the local based ESD clamp. This device is normally
off during the circuit operation. During the ESD event it has low
impedance path. Typically, the gate grounded NMOS clamp pro-
vides the current path between VDD and VSS. The VDD/VSS busses
are used to provide a low-ohmic path between any couple of pins

Fig. 4-6. High-current diode measurements (symbols) vs. ESD model (lines). Diode
current is scaled to junction perimeter [18]. Fig. 5-1. The pi-ESD protection network for I/O, adopted from [19].
 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139 1135

technique is illustrated in Fig. 5-2b. When the ESD/EOS event is

happened on I/O pad, its energy is dissipated through the forward
biased I/O ESD diode, floating rail #1, supply clamp, floating rail #2
and ESD diode connected to the grounded (V) pad or other
grounded I/O pad, respectively.
ESD circuit parameters do influence the design parameters of
circuit to be protected. Therefore, the interaction between ESD pro-
tection circuit and the main circuit is another challenge that should
be studied carefully. This issue is becoming very important as cir-
cuits are moving towards higher frequencies and higher data rates
since ESD parasitics may affect the performance of these circuits.
An ESD protection circuit adds extra parasitic capacitance to the
main circuit. This capacitance is mainly reverse-biased pn junction
capacitance, which is highly non-linear. As a result, an ESD protec-
tion circuit can degrade both frequency response and linearity per-
formance of the main circuit. Table 5-1 shows the maximum
swing, rise time and jitter for different ESD capacitance values of
the 4 Gb/s two stage CML driver that was designed in 0.13 lm
Fig. 5-2a. The typical local based ESD protection approach used for high-voltage CMOS process [30]. Differential output swing of the driver was tar-
applications [20]. geted to be at least 800 mV with rise/fall time of less than 150 ps.
At the same time, jitter should be less than 1 ps. This table shows
that the cable driver should have the parasitic capacitance of the
Floating Rail #1 ESD protection circuit below 150 fF to meet these requirements.

5.2. Distributed ESD protection networks

Supply Supply
Clamp
V+ Clamp
The previously mentioned local based ESD protection networks
have some limitations and disadvantages. The first primary disad-
vantage is that power ESD clamps require a large layout area. In
many chip applications, large banks of tightly packed I/O pads
Input Output must be placed, offering no room for large ESD rail clamp circuits.
In these ‘‘pad limited” designs, I/O ESD robustness is reduced with
increasing distance from the remote rail clamps, simply due to the
Core bus resistance, which is typically 1–2 X. For the 2 kV HBM ESD
Circuit stress, which is equivalent to a discharge current of 1.3 A, this leads
to a voltage drop of 1.3–2.6 V. As a result, each new chip design
Input Output should be optimized with respect to the size and location of the
power clamps and the power bus resistances in order to protect
Floating Rail #2 I/O pads.
To overcome disadvantages of ESD protection networks based
on the large local MOSFET based ESD clamps, distributed active
Supply
V-
Supply MOSFET power clamp ESD networks were developed [18,21]. In
Clamp Clamp
an ideal on-chip ESD network, rail clamps should be placed in close
proximity to all external pads to minimize the impact of power rail
resistance. It is well known that for a given drain-to-source voltage
Fig. 5-2b. ESD protection network for input voltages that exceed supply levels, (Vds), the conductance of an NMOSFET increases as the gate-to-
adopted from [29]. source voltage (Vgs) is increased. In the boosted ESD rail configura-
tion [21], it was found a way to apply a larger Vgs voltage to the
gate of ESD MOSFET (M0) in a large clamp circuit during the ESD
during the ESD event. In the simplest form the supply busses are event. Fig. 5-3 shows a general schematic of the boosted active
organized as a ring at the perimeter of the IC for the IO supply MOSFET rail clamp configuration [21].
and a power mesh in the center of the IC for the core supply. The Boost bus serves as a power supply bus for the rail clamp
Any resistance along this path must be controlled by the width trigger circuit. Note, that the drain of M0 remains connected to
of the metal busses and the distance between the supply pads VDD. Second, a relatively small (20 lm widths) VPNP protection de-
and connections on the package substrate. Typical values for vice (A2) in diode configuration was added in each I/O pad cell. The
wire-bond ICs with an acceptable density of supply pads are 1– A2 device couples ESD current onto the Boost bus from the stressed
2 X. For the 2 kV HBM ESD stress, which is equivalent to a dis-
charge current of 1.3 A, this leads to a voltage drop of 1.3–2.6 V.
Some circuits must work in an environment where input volt- Table 5-1
Impact of parasitic capacitance of ESD protection devices on CML driver performance
age levels exceed the supply lines. Examples of these are multi-
[30]
plexers and switches. For instance, the inputs can be specified
with a 24 V over-voltage rating, even though the supplies are rated Capacitance (fF) Diff. output swing (mV) Rise time (ps) Output jitter (fs)
at 12 V. Having inputs exceeding the supply lines becomes chal- 50 888 121 284
lenging, because typical protection techniques, as shown in Fig. 150 824 132 511
300 782 146 1160
4-2, cannot be used. One technique, which can solve this issue, is
600 711 163 4060
to allow the inputs to be tied to an isolated bus on chip [29]. This
1136 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

Fig. 5-3. Boosted rail clamp ESD protection network, adopted from [21].

Fig. 5-4. Optimized boosted and distributed ESD network, adopted from [21]. Nodal voltages are shown for 3.8 A ESD event applied at I/O1 with I/O2 grounded.

I/O pad. The primary ESD current path is through A1, M0 and B pro- clamp network shown in Fig. 5-4 the ESD bus serves as the high-
tection devices and there is a very little current flow through A2 de- current rail clamp anode bus and the VSS bus serves as the cathode
vice in the stressed I/O pad. Therefore, the voltage drop on the bus.
Boost bus at stressed I/O is only about a diode drop below the I/ Therefore, it is important that these two buses should be as
O pad voltage. In addition, an insignificant voltage drop is seen wide as possible to ensure the low resistance to ESD currents flow-
across the two Boost bus resistors R1. It was shown by Stockinger ing around the chip periphery. The Boost and Trigger buses do not
et al. [21] that in boosted ESD rail protection network, the Vgs volt- move significant current during an ESD event, and may, therefore,
age of rail clamp NMOSFET (M0) is 2 higher than the Vgs voltage be much more narrow and resistive. Each I/O pad cell in Fig. 5-4
of rail clamp protection device in non-boosted ESD rail protection contains a small rail clamp NMOSFET M1 and ESD diodes A1, A2,
network at the same Vds voltage. As a result, the rail clamp NMOS- and B. A1 and A2 represent the emitter–base junction diodes of
FET (M0) may pass significantly higher ESD current. For the same the VPNP devices A1 and A2 shown in Fig. 5-3. The VSS pad cell con-
ESD robustness, M0 transistor can be smaller by 2.3 in boosted tains the same ESD elements as the I/O pad cells and also provides
ESD rail protection network in comparison with non-boosted ESD a convenient location for a remote ESD rail clamp trigger circuit.
rail protection network. An obvious concern with the boosted This trigger circuit is defined as remote because, in addition to
ESD rail clamp configuration is that the clamp NMOS M0 may be the local NMOSFET M1, it also drives, via the Trigger bus, NMOSFET
at increased risk of damage under the Vgs > Vds boosted bias condi- devices M1 beyond the VSS pad cell. With remote trigger circuits, no
tions. At an ESD event, the boosted ESD rail protection network local trigger circuits are needed in the I/O pad cells, saving signif-
should be optimized to avoid the snapback operating mode of M0 icant layout area. Since there is very little IR voltage drop along
transistor and Vgs voltage should be not higher than the gate oxide the Boost and Trigger buses, trigger circuits may be placed in some
breakdown voltage for the given CMOS technology. The snapback distance from the stressed pad and some distance from the distrib-
mode is hard to simulate in SPICE-like simulators, therefore it uted clamp NMOS devices, which they drive.
should be avoided in this approach.
In case of distributed boosted ESD networks shown in Fig. 5-4 5.3. Comparison of local and distributed ESD protection networks
the single large boosted active MOSFET rail clamp (M0) can be split
into multiple, much smaller clamp NMOS devices M1, connected in In this subsection we compare local and distributed ESD protec-
parallel, and distributed in each of the I/O and power supply pad tion networks with respect to ESD robustness per unit layout area.
cells for efficient, uniform ESD protection. The incremental para- Stockinger et al. from the Freescale ESD group in Austin optimized
sitic bus resistances R1, R2, R3, and R4 for each bus are shown be- the distributed ESD protection network shown in Fig. 5-4 for 90 nm
tween each pad cell. In the boosted and distributed ESD rail CMOS process [21]. This ESD network was optimized for 3.8 A ESD
 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139 1137

current, corresponding to a worst case of 200 V ESD MM event. The Table 5-2
optimizations were constrained by the requirement that for a 3.8 A Comparison of local and distributed ESD protection networks

peak of ESD current both VNBUF (in the stressed pad) and VPBUF (in ESD Network CMOS ESD layout area
the grounded pad) voltages should not exceed 7.9 V (failure volt- technology efficiency, VHBM/lm2
age of I/O buffer). In addition, it was required that the rail clamp Distributed and boosted ESD network 90 nm 12.2
NMOS devices must operate within the safe operating region (without triggering circuits and CMOS
(Vds, Vgs < 9 V). For all simulations, the size of VPNP device A2 termination cells) [21]
Distributed and boosted ESD network 90 nm SOI 2500 V/1131 lm2 = 2.2
was set to 1/16 of the size of A1. Incremental Boost and Trigger (without triggering circuits and CMOS
bus resistors (R1 and R3) were fixed at 5 and 17 X, respectively. termination cells) [18]
Optimizations were repeated for a range of typical R2 and R4 val- Local (snapback) MOSFET based ESD clamp 180 nm 5
ues. Worst-case distributed bus capacitances were included in all [23] CMOS
Local (snapback) SCR based ESD clamp 100 nm 4
transient simulations, but did not show any significant impact on
[24] CMOS
the ESD performance. The results of these optimizations are shown Transient MOSFET based local ESD clamp 90 nm 5000 V/
in Table 5-1. Note, that 7 V target pad voltage was chosen to have with triggering circuit [25] CMOS (35 lm  200 lm) = 0.7
the sufficient reliability margin.
As shown in Table 5-1, for an input target voltage VNBUF =
VPBUF = 7 V and R2 = R4 = 0.165 X, the optimized output values
(3) low capacitance and low leakage current suitable for high-
are A1 = 111 lm, B = 113 lm, and M1 = 164 lm. The total combined
speed I/Os;
layout area of all ESD elements in I/O pad cell in this example is
(4) can be used for wire-bond chips and flip chips and for thin
511 lm2. In this example eight identical I/O pad cells and a VSS
(OD1) gate oxide MOSFET output buffers.
pad cell were placed along Boost, ESD, Trigger, and VSS buses.
Assuming ESD failure will occur at 3.8 A (200 V MM ESD stress),
Below are given the typical advantages of distributed ESD pro-
the 511 lm2area translates into an ESD layout efficiency of 12.2
tection networks:
VHBM/lm2 [21]. Note, that these numbers do not include the layout
area of triggering circuits and the termination cells, which should
(1) works for low-voltage (1.5 V) and medium voltage (5 V)
be located at ends of I/O banks. Previously, it was mentioned that
applications;
the distributed ESD protection networks require the accurate opti-
(2) can be easily simulated in Cadence environment;
mization of size of each ESD device in these networks to achieve
(3) the distribution of power clamps over multiple I/O cells low-
the target ESD reliability level. In order to perform these optimiza-
ers the influence of bus resistance.
tions, Freescale developed software tool called MICO [22]. Re-
cently, Freescale developed a new response surface method
Note, that the distributed ESD protection networks have some
(RSM) to conveniently optimize ESD device sizes depending on
limitations as well:
the output buffer configuration [18].
It is difficult to make direct comparisons of results shown in Ta-
(1) the usage of this approach for flip-chips requires signifi-
ble 5-1 for distributed ESD protection networks with the data for
cantly increased ESD layout area in I/O cells and it’s difficult
local based ESD protection networks. For example, in Table 5-1,
to use it for designs with limited number of digital I/O pads;
the area numbers include everything for ESD protection in the
(2) the big diodes connected to I/O pad have limited application
I/O pad cell, not just a single clamp device for one zap polarity,
for RF pads due to their relatively high parasitic capacitance
as it is frequently published for local clamps. Some recently pub-
(200 fF).
lished data are collected in Table 5-2.
Data presented in Table 5-2 depicts that the distributed and
The comparison of local and distributed ESD protection tech-
boosted ESD protection networks may have the ESD layout area
niques with respect to ESD layout area per I/O cell is shown in
efficiency significantly better than the local based ESD protection
Fig. 5-5. The boosted and distributed ESD protection network
networks, if these networks are properly optimized. The typical
was implemented in 90 nm CMOS technology developed by Free-
advantages of local based ESD protection networks are summa-
scale for advanced system-on-chip (SoC) applications [26]. This
rized below:
ESD protection network passed 3 kV HBM and 350V MM ESD test-
ing. It was optimized for 0.15X VSS and ESD bus resistance and
(1) tunable triggering voltage (Vt1), can be used for low-voltage
(1.2 V), medium voltage and high-voltage applications;
(2) tunable holding voltage (Vhold) provides latch-up immunity;

Table 5-1
Summary of 90 nm CMOS technology optimization utilizing the ESD network shown
in Fig. 5-4, adopted from [21]

Target R2, R4 bus Optimum Optimum Optimum Total combined

pad resistance A1 B M1 width ESD layout area
voltage ( X) perimeter perimeter (lm) (lm2) per I/O cell
(lm) (lm)
7 0.110 104 106 127 475
7 0.165 111 113 164 511
7 0.220 117 120 196 541
7 0.275 122 125 224 567
7.9 0.110 87 88 100 436
7.9 0.165 92 93 132 465
7.9 0.220 98 100 155 489
7.9 0.275 102 104 180 510 Fig. 5-5. ESD layout area per I/O cell for distributed ESD clamps [26] and SCR based
local ESD clamps [24].
1138 O. Semenov, S. Somov / Solid-State Electronics 52 (2008) 1127–1139

VDD1 VDD2

Dp1 M p1 D p2 M p2

IN OUT IN OUT
Circuit I Circuit II
Pad Pad Pad Pad

Dn1 M n1 D n2 M n2

VSS1 VSS2

Fig. 5-6. ESD protection network for coupling between two power domains in mixed-mode ICs, adopted from [31].

1600 lm widths of large ESD clamp M0 in the power pads. For In this paper using the broad Freescale experience in ESD and I/
comparison the SCR based local ESD protection approach was cho- O libraries design, we analyzed the different I/O architectures suit-
sen [24]. This ESD protection network was implemented in 100 nm able for VLSI/SOC applications implemented in sub-100 nm CMOS
CMOS technology. The measured ESD robustness was 4VHBM/lm2. technologies and provided recommendations for the choice of
Hence, to pass 3 kV HBM test, the ESD protection structure requires appropriate ESD protection networks (local or distributed ESD pro-
750 lm2per I/O cell. As it shown in Fig. 5-5, the distributed ESD tection) for digital and mixed-signal I/O libraries.
protection network consumes less layout area per I/O cell in com-
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