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com
BIHE university

Introduction to STM32 and Arm

Microcontrollers

Electronics Department, HCMUT 1

 Topics
www. Micro Digital Ed. com
BIHE university

• Microcontrollers vs. Microprocessors

• Most common microcontrollers
• STM32 family

Electronics Department, HCMUT 2

 General Purpose Microprocessors vs.
www. Micro Digital Ed. com
Microcontrollers BIHE university

• General Purpose Microprocessors

General I/O Serial

Purpose RAM ROM Timer
Port Port
Micropro
cessor
(CPU) Buses

• Microcontrollers (MCUs)
Microcontroller

I/O Serial
RAM ROM Timer
Port Port
CPU

Buses

Electronics Department, HCMUT 3

 Most common microcontrollers
www. Micro Digital Ed. com
BIHE university

• 8-bit microcontrollers
– AVR
– PIC
– HCS12
– 8051

• 32-bit microcontrollers
– ARM
– AVR32
– PIC32

Electronics Department, HCMUT 4

 Arm
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BIHE university

• Arm does not produce chips but designs & sells

the license of its of architecture to others.
• More than 200 companies have bought the Arm
architecture and provide their Arm chips.

Electronics Department, HCMUT 5

 Arm MCUs of Different Companies
www. Micro Digital Ed. com
BIHE university

• The same CPU and Assembly Language

• Different Peripherals

Electronics Department, HCMUT 6

 Arm families and Architectures
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Electronics Department, HCMUT 7

 STM32 Family
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BIHE university

• ST is a multinational
company
– STM8: 8-bit MCUs
– STM32: 32-bit MCUs
based on Arm
• Low prices
• Various chips

Electronics Department, HCMUT 8

 ST32 Naming Conventions
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BIHE university

STM32F103C8T
type series package
family Sub Pin Flash
series count size
Family Series
Type
Flash Package
Pin count
size
Sub series
L:0:Low
Names of the new Cortex-M0
H:Chips
Arm BGAwith
Power (Ballhigher
Grid Array)
4 F
6products
8 G
F: ST
of K
B begin
1,2: with
T:LQFP
Mainstream T
Cortex-M3D S
C(Low-profile
(Foundation)
sub-series
C
E
Quad RF Pack)
Flat VG ZH I
Group Number
Low Medium density
20STM32.
28
H: 32
3,4:
High High
36 density
Cortex-M4
U:QFN (Quad
performance 44 have
48No-leads)
Flat 64 100 144
numbers
density 7: Wireless
Cortex-M7Y:WLCSP
of pins W: richer
Flash 16K 32K 64K 128K 256K 384K 512K 768K 1M 1.5M 2M
configurations

STM32F429AIH6 STM32F103C8T6 STM32F031K6U6

Electronics Department, HCMUT 9

 STM32F103
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 10

 Topics
www. Micro Digital Ed. com
BIHE university

• ARM’s CPU
– Its architecture
– Some simple programs
• Data Memory access
• Program memory RAM EEPROM Timers

• RISC architecture PROGRAM

Flash ROM

Program Data
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Electronics Department, HCMUT 11

 ARM ’s CPU
www. Micro Digital Ed. com
BIHE university

• ARM ’s CPU
– ALU
– 16 General Purpose
R0
registers (R0 to R15) R1
ALU
– PC register (R15) R2

…
– Instruction decoder CPSR: I T H S V N Z C
R13 (SP)

CPU R14 (LR)

R15 (PC)

PC registers

Instruction decoder

Instruction Register

Electronics Department, HCMUT 12

CPU

13
 Some simple instructions
1. MOV (MOVE)
www. Micro Digital Ed. com
BIHE university

• MOV Rd, #k ◼ MOV Rd, Rs

– Rd = k ◼ Rd = Rs
– k is an 8-bit value ◼ Example:
• Example: ◼ MOV R5,R2
– MOV R5,#53 ◼ R5 = R2
• R5 = 53 ◼ MOV R9,R7
– MOV R9,#0x27 ◼ R9 = R7
• R9 = 0x27
– MOV R3,#2_11101100

Electronics Department, HCMUT 14

 LDR pseudo-instruction (loading 32-bit values)
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BIHE university

• LDR Rd, =k
– Rd = k
– k is an 32-bit value
• Example:
– LDR R5,=5543
• R5 = 5543
– LDR R9,=0x123456
• R9 = 0x123456
– LDR R4,=2_10110110011011001

Electronics Department, HCMUT 15

 Some simple instructions
Instruction
2. Arithmetic
Description
calculation
www. Micro Digital Ed. com
BIHE university

ADD Rd, Rn,Op2 * ADD Rn to Op2 and place the result in Rd

• Opcode
ADC destination,
Rd, Rn,Op2 source1,
ADD Rn to Op2 with Carry andsource2
place the result in Rd

– Opcodes:
AND Rd, Rn,Op2
ADD,AND Rn with Op2 and place the result in Rd
SUB, AND, etc.
BIC Rd, Rn,Op2 AND Rn with NOT of Op2 and place the result in Rd
• Examples:
CMP Rn,Op2 Compare Rn with Op2 and set the status bits of CPSR**
CMN Rn,Op2 Compare Rn with negative of Op2 and set the status bits
– ADD
EOR
R5,R2,R1
Rd, Rn,Op2 Exclusive OR Rn with Op2 and place the result in Rd
• R5 =Rd,Op2
MVN R2 + R1Store the negative of Op2 in Rd
MOV Rd,Op2 Move (Copy) Op2 to Rd
– SUB
ORR
R5, R9,#23
Rd, Rn,Op2 OR Rn with Op2 and place the result in Rd
– R5
RSB = R9 - 23 Subtract Rn from Op2 and place the result in Rd
Rd, Rn,Op2
RSC Rd, Rn,Op2 Subtract Rn from Op2 with carry and place the result in Rd
SBC Rd, Rn,Op2 Subtract Op2 from Rn with carry and place the result in Rd
SUB Rd, Rn,Op2 Subtract Op2 from Rn and place the result in Rd
TEQ Rn,Op2 Exclusive-OR Rn with Op2 and set the status bits of CPSR
TST Rn,Op2 AND Rn with Op2 and set the status bits of CPSR
* Op2 can be an immediate 8-bit value #K which can be 0–255 in decimal, (00–FF in hex).
Op2 can also be a register Rm. Rd, Rn and Rm are any of the general purpose registers
** CPSR is discussed later in this chapter

Electronics Department, HCMUT 16

 A simple program
www. Micro Digital Ed. com
BIHE university

• Write a program that calculates 19 + 95

MOV R6, #19 ;R6 = 19

MOV R2, #95 ;R2 = 95
ADD R6, R6, R2 ;R6 = R6 + R2

Electronics Department, HCMUT 17

 A simple program
www. Micro Digital Ed. com
BIHE university

• Write a program that calculates 19 + 95 - 5

MOV R1, #19 ;R6 = 19
MOV R2, #95 ;R2 = 95
MOV R3, #5 ;R21 = 5
ADD R6, R1,R2 ;R6 = R1 + R2
SUB R6, R6,R3 ;R6 = R6 - R3

MOV R1, #19 ;R6 = 19

MOV R2, #95 ;R2 = 95
ADD R6, R1,R2 ;R6 = R1 + R2
MOV R2, #5 ;R21 = 5
SUB R6, R6,R2 ;R6 = R6 - R2

Electronics Department, HCMUT 18

 Status Register (CPSR)
www. Micro Digital Ed. com

D31 D30 D29 D28 ………. D7 D6 D5 D4 D3 D2 D1 D0 BIHE university

CPSR: N Z C V Reserved I F T M4 M3 M2 M1 M0

Negative oVerflow Interrupt Thumb

Zero carry

Example:Show
Example: Showthe thestatus
statusofofthe
theZZflag
flagafter
afterthe
thesubtraction
subtractionofof0x73
0x23
Example:
Example: Show
Show the
the status of the C and
status instructions:
ofinstructions:
the Z
C flag Z flags
and after after
theafter
Z flags the addition
subtraction of
of 0x9C
the addition of
from0x52
from 0xA5ininthe
the following
following
0x0000009C
from
0x38 0x9C in and
and 0x2F the 0xFFFFFF64
in following in the following instructions:
instructions:
the following instructions:
LDR
LDR R0,=0xA5
R0,=0x52
LDR
MOV LDR
R6, #0x38 R0,=0x9C
R0,=0x9C;R6 = 0x38
LDR
LDR R1,=0x23
R1,=0x73
LDR
MOV LDR
R7, #0x2F R1,=0xFFFFFF64
R1,=0x9C;R17 = 0x2F
SUBS
SUBS R0,R0,R1
R0,R0,R1 ;subtract R1
;subtract R1 from
from R0R0
ADDS
ADDS SUBS
R6, R6,R7 R0,R0,R1 ;add
R0,R0,R1;add R7 ;subtract
to R6 R1 to R0
R21 from R20
Solution:
Solution:
Solution: 52
Solution: 0xA5 0101 101000100101
-- 9C
7338 00000000
1001 1100 00000000 00000000 0011 1000
0x23 0111
0000009C 0011
00000000
0010 0011 00000000 00000000 10011100
+ - +DF
2F
FFFFFF64
9C
0x82 1101
00000000
11111111
1001
1000 1100
1111 00000000
0010 11111111 R0 00000000
11111111
R0= =0xDF0x82
0010 1111
01100100
Z = 10 because 67the R20
00000000
00 00000000
10000
00000000
has a value 00000000
0000other00000000
thanR0 00000000
zero=00000000
after 01100111
00000000
$00 the subtraction.
CZ====01
R6
R0
Z because
becauseR1
=000000000
0x67
because theis
the bigger
R20
R20 ishasthan
zero R0 the
after
a value and there
thanis0 aafter
subtraction.
other borrow from D32 bit.
the subtraction.
CC==11because
becausethere
R21 isisnot
R1 is a carry
not beyond
bigger theand
than R0
R20 D7there
andbit.
thereisisno
noborrow
borrowfrom
fromD32
D32bit.
bit.
C = 0 because there is nobigger than
carry beyond the D31 bit.
Z = 1 because R0 (the result) has a value 0 in it after the addition.
Z = 0 because the R6 (the result) has a value other than 0 after the addition.

Electronics Department, HCMUT

Harvard in ARM9 and Cortex

20
 Memory Map in STM32F103
www. Micro Digital Ed. com
BIHE university

8 bits
4G 0xFFFF FFFF
Cortex-M3 internal
peripherals
0xE000 0000
Example: Add contents of location 0x90 to contents of location 0x94
Afterand
running the following
store instruction:
the result STR (Store register)
in location 0x20000300.

SRAM
3G STR R5, 0000
0xC000 [R2]
Solution:
locations 0x20000000 through 0x20000003 will be loaded
with 0x78, 0x56, 0x34, and 0x12, respectively.
STR Rx,[Rd] ;[Rd]=Rx
LDR (Load register)
LDR R6,=0x90
Example: Write a program ;R6 that
= 0x90
copies the contents of location 0x80
FSMC 0x12 0x2000 0003
into location
LDR
0x8000 0000
0x88.
R1,[R6] Example:
;R1 = [0x90]
LDR Rd, [Rx]
;Rd = [Rx]
2G 0x34 0x2000 0002
Solution:
LDR R6,=0x94 ;R6 = 0x94 0x56
;[0x20000000]=0x12345678
0x2000 0001
0x6000 0000
LDRR2,[R6]
LDR R2,=0x80 ;R2 == [0x94]
;R1 0x80
Example: 0x78 0x2000 0000
Peripherals
0x5FFF FFFF LDR R5,=0x12345678
1G LDR R2,R2,R1
ADD
0x4000 0000 R1,[R2] ;R1 == R2
;R2 [0x80]
+ R1
LDR
R4,=0x20000000
0x3FFF FFFF
LDR R6,=0x20000300
LDR R2,=0x88 ;R2 LDR
;R6= =0x88
R2, =0x20000000
0x20000300
SRAM R5: 0x2000
0x12 0x34 0x56 0x78
0000 LDR R1, [R4]
STR R2,[R6]
0x1FFF STR
FFFF R1,[R2] ;[0x88] =STR
;[0x20000300]R1 = R5,[R2]
R2 ; [R2] = R5
Flash
0 0x0000 0000

Electronics Department, HCMUT

 LDRB, LDRH, STRB, STRH
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BIHE university

Data Size Bits Load instruction used Store instruction used

Byte 8 LDRB STRB
Half-word 16 LDRH STRH
Word 32 LDR STR

LDR Rd,[Rs] STR Rs,[Rd]

LDRB Rd,[Rs] STRB Rs,[Rd]
LDRH Rd,[Rs] STRH Rs,[Rd]

Assumethat
Assume thatR5=0x40000200,
R5=0x40000200,and andR1locations 0x40000200
= 0x41526374.

SRAM
through
After 0x40000203
running contain
the following 0x78, 0x56, 0x34 ,and 0x12,
instruction:
respectively.
STRB R1, [R5]
After running
locations the following
0x40000200 will beinstruction:
loaded with 0x74.
LDRH R7, [R5]
R7 will be loaded with 0x00005678 0x12
- 0x4000 0203
0x34
- 0x4000 0202
0x56
- 0x4000 0201
0x00 0x00 0x78
0x74 0x4000 0200

R7
R1 0x00
x 0x00
x 0x56
x 0x78
0x74
Electronics Department, HCMUT 22
 Memory Map in STM32F103
www. Micro Digital Ed. com
BIHE university

I/O Register Address

GPIOA_LCKR 0x40010818
GPIOA_BRR 0x40010814
GPIOA_BSRR 0x40010810
GPIOA_ODR 0x4001080C
GPIOA_IDR 0x40010808
GPIOA_CRH 0x40010804
GPIOA_CRL 0x40010800
Example: Read the contents of GPIOA_IDR.
Example: Write 0x53F6 into GPIOA_ODR.
Solution:
Solution: LDR R1,=0x40010808 ;R1= 0x40010808
LDR R2,=0x53F6 LDR ;R6
R2,[R1]
= 0x53F6 ;R2 = [0x4001080C]
LDR R1,=0x4001080C ;R1= 0x4001080C
STR R2,[R1] ;[0x4001080C] = 0x53F6

Electronics Department, HCMUT 23

 Power up in Cortex-M
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Electronics Department, HCMUT 24

 Startup and main files
Startup_stm32f10x.s
www. Micro Digital Ed. com
BIHE university

Electronics Department, HCMUT 25

 Flash memory and PC register
www. Micro Digital Ed. com
BIHE university

0x08000200 F04F0125
0x08000204 F04F0234
0x08000208 0F02
EB020301
0x0800020C E7FE
0x0800020E

RAM

PROGRAM
Flash ROM ALU

0x08000200
PC: 0x0800020C
0x08000208
0x08000204
0x0800020E
main.lst 32bit Data
32bit
CPU Bus
Line Offset Machine Instruction _ Code Instruction dec.
1 00000000 ; The program adds some data Bus
2 00000000 EXPORT __main
3 00000000 AREA PROG_2_4, CODE, READONLY
4 00000000 __main
Ports
5 00000000 F04F 0125 MOV R1, #0x25 ; R1 = 0x25
6 00000004 F04F 0234 MOV R2, #0x34 ; R2 = 0x34
7 00000008 EB02 0301 ADD R3, R2, R1 ; R3 = R2 + R1 I/O
8 0000000C PINS

9 0000000C E7FE HERE B HERE ; stay here forever 26

10 0000000E END

Electronics Department, HCMUT

 How to speed up the CPU
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BIHE university

• Increase the clock frequency

– More frequency ➔ More power consumption &
more heat
– Limitations
• Change the architecture
– Pipelining
– Harvard
– RISC

Electronics Department, HCMUT 27

 Pipeline
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• Non-pipeline
– Just fetches, decodes, or executes in a given time

• Pipeline

Electronics Department, HCMUT 28

 Pipeline (Cont.)
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BIHE university

SUB R3,R3,R4
LDR R2, [R4] ; R2 = [R4] ADD R0, R0,R1
ADD R0,R0,R1 ; R20 = R20 + R21 LDR R2, [R4]
SUB R3,R3,R4

Fetch

Decode

Execute

Electronics Department, HCMUT 29

 Harvard Architecture
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• separate buses for opcodes and operands

– Advantage: opcodes and operands can go in and out of the CPU
together.
– Disadvantage: Using Harvard architecture in motherboards leads
to more cost in general purpose computers.

Control bus Control bus

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus

Electronics Department, HCMUT 30

 Changing the architecture
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RISC vs. CISC BIHE university

• CISC (Complex Instruction Set Computer)

– Put as many instruction as you can into the CPU
• RISC (Reduced Instruction Set Computer)
– Reduce the number of instructions, and use your
facilities in a more proper way.

Electronics Department, HCMUT 31

 RISC architecture
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BIHE university

• Feature 1 (fixed instruction size)

– RISC processors have a fixed instruction size. It
makes the task of instruction decoder easier.
• In ARM the instructions are 4 bytes.
• In Thumb2 the instructions are either 2 or 4 bytes.
– In CISC processors instructions have different
lengths
• E.g. in 8051
– CLR C ; a 1-byte instruction
– ADD A, #20H ; a 2-byte instruction
– LJMP HERE ; a 3-byte instruction

Electronics Department, HCMUT 32

 RISC architecture
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• Feature 2: reduce the number of instructions

– Pros: Reduces the number of used transistors
– Cons:
• Can make the assembly programming more difficult
• Can lead to using more memory

Electronics Department, HCMUT 33

 RISC architecture
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• Feature 3: limit the addressing mode

– Advantage
• hardwiring
– Disadvantage
• Can make the assembly programming more difficult

Electronics Department, HCMUT 34

 RISC architecture
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BIHE university

• Feature 4: Load/Store
LDR R8,=0x20
LDR R0,[R8]
LDR R8,=0x220
LDR R1,[R8]
ADD R0, R0,R1
LDR R8,=0x230 RAM USART Timers
STR R0,[R8]
PROGRAM
Flash ROM ALU

PC: Data
CPU Bus
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

Electronics Department, HCMUT 35

 RISC architecture
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• Feature 5: more than 95% of instructions are

executed in 1 machine cycle

Electronics Department, HCMUT 36

 RISC architecture
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• Feature 6
– RISC processors have at least 32 registers.
Decreases the need for stack and memory
usages.
• In ARM there are 16 general purpose registers (R0
to R15)

Electronics Department, HCMUT 37

 SOC block diagram
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BIHE university

Electronics Department, HCMUT 38

 SOC block diagram
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BIHE university

Electronics Department, HCMUT 39