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Timer

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 Topics
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• SysTick Timer
• STM32 Timers

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 8-bit counter Stages
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• Up-counter

• Down counter

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 Some Counter Usages
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• Event Counter

• Timer

• Measuring the time between 2 events

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 System Tick Timer
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• Available in all Cortex-M MCUs

• It is a 24-bit down counter. It counts down from
an initial value to 0.
• Used to initiate an action on a periodic basis
– OS ticks

SysTick->LOAD

SysTick->VAL

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 System Tick Counting
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 STCTRL (System Tick Control) Register
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Name bit Description

ENABLE 0 0: The counter is disabled, 1: enables SysTick to begin counting down
TICKINT 1 Interrupt Enable
0: Interrupt generation is disabled.
1: when SysTick counts to 0 an interrupt is generated
CLKSOUR 2 Clock Source
CE 0: AHB clock divided by 8
1: AHB clock
COUNTFL 16 Count flag
AG 0: The SysTick has not counted down to zero since the last time this
bit was read
1: The SysTick has counted down to zero
Note: This flag is cleared by reading the STRCTRL or writing to
STCURRENT.

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 Example: Assuming system clock = 8 MHz, calculate the
delay which is made by the following function.
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void delay() {
SysTick->LOAD = 9;
SysTick->CTRL = 5; /*Enable the timer and choose system clock as the
clock source */

while((SysTick->CTRL &0x10000) == 0) /*wait until the Count flag is set */

{}
SysTick->CTRL = 0; /*Stop the timer (Enable = 0) */

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 Example
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• In an ARM microcontroller a clock with frequency of clk is fed to the

sysTick timer. Calculate the delay which is made by the timer if the
STRELOAD register is loaded with N.

Solution:

The timer is initialized with N. So, it goes through N+1 stages.

Since the system clock is chosen as the clock source, each clock lasts 1 / clk
So, the program makes a delay of (N + 1) × (1 / clk) = (N + 1) / clk.

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 Example: Using the System Tick timer, write a function that
makes a delay of 1 ms. Assume APB clock = 72 MHz.
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Solution:
delay = (N + 1) / clk ➔ (N + 1) = delay × clk = 0.001 sec × 72 MHz =
72,000 ➔ N = 72,000 – 1 = 71999

void delay1ms(void)
{
SysTick->LOAD = 71999;
SysTick->CTRL = 0x5; /* Enable the timer and choose sysclk as the clock
source */

while((SysTick->CTRL & 0x10000) == 0) /* wait until the COUNT flag is set */

{}
SysTick->CTRL = 0; /* Stop the timer (Enable = 0) */
}

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STM32 Timers

11
 STM32 Timers
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• ARR (Auto-Reload Register)

Note:
In STM32 microcontrollers, all the timer registers begin with TIMx. So, for
simplicity, just consider the letters which come after TIM. For example,
consider TIMx_CNT as CNT (Counter).
• CNT (Counter)

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 TIMx_CR1 (Control Register)
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CMS (Center-aligned
•◼ CEN (Counter Enable) Mode Selection)
◼ DIR
– 0:(Direction)
counter disabled
– 1: count
• OPM (One
CMS Pulse
DIRMode)
Counting mode
00 0 Counting up
– 0: the
00
counter
1
counts continuously
Counting down
– 1: the
01 counter
X stops
Countatupthe
andnext
downupdate event.
10 X Count up and down
11 X Count up and down

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 Example: Find the TIMx_CR1 value to: (a) count up
continuously (b) count down continuously (c) stop counting.
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TIMx_ CKD ARPE CMS DIR OPM URS UDIS CEN

CR1: 0 0 00 0 0 0 0 1

TIMx_ CKD ARPE CMS DIR OPM URS UDIS CEN

CR1: 0 0 00 1 0 0 0 1

TIMx_ CKD ARPE CMS DIR OPM URS UDIS CEN

CR1: 0 0 00 0 0 0 0 0

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 TIMx_SR (Status Register)
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 Counting Up
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 Example
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• Assume TIM2_ARR = 5 and TIM2_CNT is

counting up. (a) Explain when the UIF flag is
raised. (b) How many clocks does it take until the
UIF flag rises?

(b) When the counter starts counting, it goes through 6 states

(ARR+1 states) until the flag rises.

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 STM32F10X Clock
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TIM2, 3, and 4

TIM1

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 By default, the CPU clock frequency is 72MHz; the APB1 clock is set to 36MHz,
and APB2 is 72MHz. Calculate the frequency of the clock that is fed to the
timers.
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• Since the CPU clock is 72MHz and APB1 clock is 36MHz,

the prescaler for APB1 is set to 2 (other than 1). So the
APB2 clock is multiplied by 2 and fed to the timers which
are connected to APB1 bus. 36MHz × 2 = 72MHz.
• APB2 clock has the same frequency as the CPU. So, its
prescaler is set to 1 and the timer clocks are the same as
the APB2 clock. According to Figure 8-8, TIM1 and TIM8
are connected to APB2. So, a clock with frequency of
72MHz are fed to the timers.
• So, the clocks for all timers are 72MHz by default, unless
we change the APB prescalers.

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 Enabling Clocks
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Label Description Label Description

IOPx I/O port x clock enable ADCnEN ADCn clock enable
USARTnEN USARTn clock enable DACnEN DACn clock enable
USBEN USB clock enable TIMnEN TIMn timer clock enable
CANEN CAN clock enable SPInEN SPI n clock enable
PWREN Power interface clock enable BKPEN Backup interface clock enable
WWDG Window watchdog clock enable SDIOEN SDIO clock enable
DMAnEN DMAn clock enable FSMCEN FSMC clock enable
CRCEN CRC clock enable I2CnEN I2Cn clock enable
Note: (0: clock disabled, 1: clock enabled)

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 Example: Calculate the delay which is made by
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the following function. BIHE university

void delay()
{
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
TIM2->ARR = 71;
TIM2->SR = 0; /* clear the UIF flag */
TIM2->CR1 = 1; /* up counting */
while((TIM2->SR & 1) == 0); /* wait until the UIF flag is set */
TIM2->CR1 = 0; /*stop counting */
}

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 Example: Using TIM2 make a delay of 50µs. The clock
frequencies are set by default.
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Solution:

Delay = ARR+1 /72MHz ➔ ARR+1 = delay × 72MHz = 50 µs × 72MHz = 3600

➔ ARR = 3600 – 1 = 3599.

void delay()
{
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
TIM2->ARR = 3599;
TIM2->CR1 = 1; /* up counting */
while((TIM2->SR & 1) == 0); /* wait until the UIF flag is set */
TIM2->CR1 = 0; /*stop counting */
TIM2->SR = 0; /* clear the UIF flag */
}

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 Prescaler
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• Prescaler is a 16-bit up-counter and a

comparator

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 Example: Calculate the delay which is made by
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void delay() {
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
TIM2->PSC = 7200-1; /* PSC = 7199 */
TIM2->ARR = 500-1;
TIM2->SR = 0; /* clear the UIF flag */
TIM2->CR1 = 1; /* up counting */
while((TIM2->SR & 1) == 0); /* wait until the UIF flag is set */
TIM2->CR1 = 0; /*stop counting */
}

Electronics Department, HCMUT 24

 Example: Using TIM2 write a program that toggles
PC13, every second.
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#include <stm32f10x.h>
void delay(void);
int main( ) {
RCC->APB2ENR |= 0xFC; /* enable GPIO clocks */
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
GPIOC->CRH = 0x44344444; /* PC13 as output */

while(1) {
GPIOC->ODR ^= (1<<13); /* toggle PC13 */
delay();
}
}
void delay() {
TIM2->PSC = 7200-1; /* PSC = 7199 */
TIM2->ARR = 10000-1;
TIM2->SR = 0; /* clear the UIF flag */
TIM2->CR1 = 1; /* up counting */
while((TIM2->SR & 1) == 0); /* wait until the UIF flag is set */
TIM2->CR1 = 0; /*stop counting */
}
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 Down Counting
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 Example: Calculate the delay which is made by the
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following function.
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void delay()
{
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
TIM2->ARR = 999;
TIM2->CR1 = 1; /* up counting */
while((TIM2->SR & 1) == 0); /* wait until the UIF flag is set */
TIM2->CR1 = 0; /*stop counting */
TIM2->SR = 0; /* clear the UIF flag */
}

Solution:

It takes 1000 clocks to rise the flag.

Each clock lasts 1/72MHz
Delay = 1000×1/72MHz = 1/72K = 13.8µs.

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Output Compare

28
 The Channels of TIMx
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 Timer Pins in the Blue Pill
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TIM1 BIHE university

TIM3

TIM2
TIM4

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 Output Circuit
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 CCER (Compare/Capture Enable Reg.)
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• CCnP (Compare/Capture n output Polarity)

– 0: Active high (directly)
– 1: Active low (inverted)
• CCnE (Compare/Capture n output Enable
– 0: the output is disabled.
– 1: the output is enabled

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 CCMR1 and CCMR2
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OCnM Mode Description

000 Frozen Compare match has no effect on the GPIO pin
001 Active on matchWhen CNT=CCRn, the wave generator makes
its output high and the GPIO pin (TIMx_CHn)
becomes active.
010 Inactive on match When CNT=CCRn, the wave generator makes
its output low and the GPIO pin (TIMx_CHn)
• CCnS (Compare/Capture changes to n Selection):
inactive level.
011 Toggle on match When CNT=CCRn, it toggles the GPIO pin
– 00: Compare (output) (TIMx_CHn).
100– : Capture
Force inactive
(input) It forces the GPIO pin to inactive level without
considering the values of the TIMx_CNT and
• OCnM (Output Compare TIMx_CCRn n Mode)
registers.
101 Force active It forces the GPIO pin to active level without
considering the values of the TIMx_CNT and
TIMx_CCRn registers.
110 PWM 1 It is discussed in the PWM chapter.
111 PWM 2 It is discussed in the PWM chapter.

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 Toggle mode (OCnM = 011)
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 Set Mode (OCnM = 001)
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 Clear Mode (OCnM =010)
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 Example: Find the CCMR value to: (a) Set high channel 2 on compare match,
(b) toggle channel 2 on compare match, (c) toggle channel 3 on compare match
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OCnM Mode
000 Frozen
001 Active on match
010 Inactive on match
011 Toggle on match
100 Force inactive
101 Force active
110 PWM 1
111 PWM 2
(a)
OC2CE OC2M OC2PE OC2FE CC2S OC1CE OC1M OC1PE OC1F CC1S
TIMx_CCMR1: E
0 001 0 0 00 0 000 0 0 00
TIMx->CCMR1 = 0x1000;
(b)
OC2CE OC2M OC2PE OC2FE CC2S OC1CE OC1M OC1PE OC1FE CC1S
TIMx_CCMR1:
0 011 0 0 00 0 000 0 0 00

TIMx->CCMR1 = 0x3000;
(c)
OC4CE OC4M OC4PE OC4FE CC4S OC3CE OC3M OC3PE OC3FE CC3S
TIMx_CCMR2:
0 000 0 0 00 0 011 0 0 00

TIMx->CCMR2 = 0x0030;

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 Example: Draw the wave generated by the following
program. Calculate the frequency of the generated wave.
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#include <stm32f10x.h>
int main( ) {
RCC->APB2ENR |= 0xFC; /* enable GPIO clocks */
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
GPIOA->CRL = 0x44444B44; /* PA2: alternate func. output */

TIM2->CCR3 = 200;
TIM2->CCER = 0x1 << 8; /* CC3P = 0, CC3E = 1 */
TIM2->CCMR2 = 0x0030; /* toggle channel 3 */
TIM2->ARR = 10000-1;
TIM2->CR1 = 1; /* start counting up */

while(1) {}
}

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 Example: Draw the waves generated by the following
program.
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#include <stm32f10x.h>
int main( ) {
RCC->APB2ENR |= 0xFC; /* enable GPIO clocks */
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
GPIOA->CRL = 0x44444BB4; /* PA2(CH3), PA1(CH2): alternate func. output */
TIM2->CCR2 = 1000;
TIM2->CCR3 = 3000;
TIM2->CCER = (0x1<<8)|(0x1<<4); /*CC3P = 0, CC3E = 1, CC2E = 1 */
TIM2->CCMR1 = 0x3000; /* toggle ch.2 */
TIM2->CCMR2 = 0x0030; /* toggle ch. 3 */
TIM2->PSC = 7200-1;
TIM2->ARR = 10000-1;
TIM2->CR1 = 1;
while(1) { }
}

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40
 CCMR1 and CCMR2
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• CCnS (Compare/Capture n Selection)

• ICnPSC (Input Capture Prescaler)
CC1S Mode CC2S Mode
• ICnF
00 (Input
OutputCapture Filter) 00
Compare mode Output Compare mode
01 Input from TIMx_CH1 01 Input from TIMx_CH2
10 Input from TIMx_CH2 10 Input from TIMx_CH1
ICnF N Fsam ICnF N Fsam ICnF N Fsam ICnF N Fsam
11 Input from TRC 11 Input from TRC
pling pling pling pling
0000 1CC3S fDTS 0100 Mode
6 fDTS/2 1000CC4S
6 fDTS/8 1100Mode 8 fDTS/16
0001 2 00 fCK_INT 0101Compare
Output 8 fDTS/2
mode 1001 008 fDTS/8 Compare
Output 1101 5 modefDTS/32
0010 4 01 fCK_INTInput
0110from6TIMx_CH3
fDTS/4 1010 015 fInput
DTS/16from
1110TIMx_CH4
6 fDTS/32
0011 8 10 fCK_INTInput
0111from8TIMx_CH4
fDTS/4 1011 106 fInput
DTS/16from
1111TIMx_CH3
8 fDTS/32
11 Input from TRC 11 Input from TRC

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• CCnE (Compare/Capture n Enable)

– 0: disable
– 1: enable

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 TIM_SR (Status Register)
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• CCnIF (Capture/Compare n Input Flag)

– 0: No capture occurred,
– 1: capture occurred
• CCnOF (Capture/Compare n Over-capture flag)
– 0: No over-capture,
– 1: over-capture detected)

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 Example
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• Find the CCMR1 and CCER values to configure

channel 1 for capturing pin TIMx_CH1 on rising
edge, and no division. The noise filter should
accept signals after 4 timer clocks.

Solution:
TIMx_CCM IC2F IC2PSC CC2S IC1F IC1PSC CC1S
R1: 0000 00 00 0010 00 01
TIMx->CCMR1=0x0021;

TIMx_CC Res. CC4P CC4E Res. CC3P CC3E Res. CC2P CC2E Res. CC1P CC1E
ER 00 0 0 00 0 0 00 0 0 00 0 1
TIMx->CCER=0x0001;

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 Measuring Period and Pulse width
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 Example: The program measures the frequency of the
wave and reports through usart1
#include <stm32f10x.h>
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#include <stdio.h>

void usart1_init(void);
void usart1_sendByte(unsigned char c);
void usart1_sendInt(unsigned int i);
void usart1_sendStr(char *str);

int main( ) {
RCC->APB2ENR |= (0xFC| (1<<14)); /* enable GPIO clocks and USART1 clock */
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */

GPIOA->CRL = 0x44444844; /* PA2(CH3): input pull-up */

GPIOA->ODR |= (1<<2);

TIM2->CCMR2 = 0x001; /* Pin TIM2_CH3 as input for channel 3 */

TIM2->CCER = 0x1 << 8; /*CC3P = 0 (rising), CC3E = 1 */
TIM2->PSC = 7200-1;
TIM2->ARR = 50000-1;
TIM2->CR1 = 1; /* start counting up */
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Using Timer as a
Counter

47
 Timers Clock Sources
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SMCR.TS:
000 to 011: Internal Triggers
SMS Mode Description
0 Timer mode clocked by the internal clock (TI1F_ED)
100: TI1 Edge detector
1 Encoder mode 1 101:counts
counter Filtered Timer
up/down onInput 1 (TI1FP1)
TI2FP1 from TIMx_CH1
edge depending on TI1FP2 level.
2 Encoder mode 2 110:counts
counter Filtered TimeronInput
up/down 2 (TI2FP2)
TI1FP2 from TIMx_CH2
edge depending on TI2FP1 level.
3 Encoder mode 3 111:counts
counter External Trigger
up/down Input
on both (ETRF)
TI1FP2 andfrom TIMx_ETR
TI2FP2 edges pin
depending on the level of the other.
4 Reset mode The counter is reset and the registers are updated on each rising
edge of TRGI signal. (See the manual.)
5 Gated mode As long as the TRGI signal is high, the timer counts. The timer stops
SMCR (Slave
counting Mode
when Control
the TRGI Register)
signal is low.
6 Trigger mode at the rising edge of the TRGI signal, it starts counting.
7 External clock mode 1 Counts the rising edges of TRGI signal. 48
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 TIMx_CH1 and TIMx_CH2 External Clock
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Circuit BIHE university

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 Example: Find the SMCR value to choose (a) TIMx_CH1
(b) TIMx_CH2 as the clock source for the counter.
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(a)
TIMx_S ETP ECE ETPS ETF MSM TS Res. SMS
MCR 0 0 00 0000 0 101 0 111
TIMx_SMCR = 0x57;

(b)
TIMx_S ETP ECE ETPS ETF MSM TS Res. SMS
MCR 0 0 00 0000 0 110 0 111
TIMx_SMCR = 0x67;

Electronics Department, HCMUT 50

 Example: Write a program that counts the input pulses of TIMx_CH2 on
rising edge and sends the value of counter through USART1.
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int main( ) {
RCC->APB2ENR |= (0xFC| (1<<14)); // enable GPIO clocks and USART1 clock
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */

usart1_init(); /* initialize the usart1 */

GPIOA->CRL = 0x44444484; /* PA1(CH2): input pull-up */

GPIOA->ODR |= (1<<1);

TIM2->CCMR1 = 0x0000; /* no filter */

TIM2->CCER = 0; /* CC2P = 0 (rising) */
TIM2->SMCR = 0x67; /* TIM2_CH2 as clock source */
TIM2->ARR = 50000-1; /* count from 0 to 49999 then roll over to 0 */
TIM2->CR1 = 1; /* start counting up */

while(1) {
usart1_sendInt(TIM2->CNT); /* send the counter value through serial */
usart1_sendStr("\n\r"); /* go to new line */
delay_ms(100);
}
}
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 Example: A clock pulse is fed into pin TIM2_CH1(PA0). Write a
program that toggles PC13 every 100 pulses.
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#include <stm32f10x.h>
int main( ) {
RCC->APB2ENR |= 0xFC; /* enable GPIO clocks and USART1 clock */
RCC->APB1ENR |= (1<<0); /* enable TIM2 clock */
GPIOA->CRL = 0x44444448; /* PA0(CH1): input pull-up */
GPIOA->ODR |= (1<<0);
GPIOC->CRH = 0x44344444; /* PC13 as output */
TIM2->CCMR1 = 0x0000; /* no filter */
TIM2->CCER = 0x1 << 1; /* CC0P = 1 (falling) */
TIM2->SMCR = 0x57; /* TIM2_CH1 as clock source */
TIM2->ARR = 100-1;
TIM2->CR1 = 1;
while(1) {
if((TIM2->SR&1) != 0) {
TIM2->SR = 0;
GPIOC->ODR ^= (1<<13);
}
}
}
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 ETR (External clock) input Block
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Electronics Department, HCMUT 53