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Lab Module 2 Subtractor

This lab exercise aims to design a 4-bit binary subtractor circuit using Quartus II. Students will first design a full subtractor circuit and generate its logic symbol. Then a 4-bit subtractor circuit will be designed by connecting four full subtractor blocks. The circuit will be simulated and the output waveforms analyzed to verify correct subtraction operations.

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Hazim Khadri
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29 views

Lab Module 2 Subtractor

This lab exercise aims to design a 4-bit binary subtractor circuit using Quartus II. Students will first design a full subtractor circuit and generate its logic symbol. Then a 4-bit subtractor circuit will be designed by connecting four full subtractor blocks. The circuit will be simulated and the output waveforms analyzed to verify correct subtraction operations.

Uploaded by

Hazim Khadri
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FACULTY OF ELECTRONICS ENGINEERING AND TECHNOLOGY

(FKTEN)
NMK10803 – DIGITAL SYSTEMS

LAB MODULE 2
QUARTUS II: COMBINATIONAL LOGIC CIRCUIT - SUBTRACTOR

LEARNING OUTCOMES
At the end of this laboratory session, students should be able to:
i) To understand the basic operation of a combinational logic gate application.
ii) To design a basic combinational logic circuit.
iii) To verify the design operation based on the constructed circuit.

EQUIPMENT/COMPONENTS
i) Computer Unit
ii) Altera Quartus II software

INTRODUCTIONS
Combinational logic circuits consist of logic gates whose outputs at any time are determined by
combining the values of the applied inputs using logic operations. A combinational circuit performs
an operation that can be specified logically by a set of Boolean expressions. It consists of input
variables, output variables, logic gates, and interconnections. The interconnected logic gates accept
signals from the inputs and generate signals at the outputs.

Referring to the block diagram in Figure 1.1, the n input variables come from the environment of
the circuit, and the m output variables are available for use by the environment. Each input and
output variable exists physically as a signal representing logic ‘1’ or ‘0’.

Figure 1.1: Combinational Circuit Block Diagram

Combinational Design Procedure onto CAD tools may include the following steps:
1 Specification definition Define the specifications for the design
2 Formulation derivation Derive the truth table / Boolean equations between the inputs
and outputs
3 Level Optimization Apply two-level or multiple-level optimization.
4 Technology Mapping Basic EDA synthesis
5 Verification Functional or timing simulation
The objective of this lab module is to make the students understand the design hierarchy
implementations and to use the knowledge acquired to formulate a simple design synthesis and
analysis from the given digital logic system design problems on an EDA/CAD tool.

LABORATORY EXERCISE
PART A: Designing a 4-bit subtractor.

EXPERIMENTAL METHOD:
1) Prepare your folder on the computer.
i) Create a new folder in Drive D (or E).
ii) Name your folder as your “Student Matrix Number”.
2) Follow the instructions in the Quartus II User Manual. Use Quartus II to:
i) Draw the schematic diagram of the full subtractor first.
ii) Provide inputs to the circuit and simulate the circuit using Functional Simulation.
iii) Run the compilation on the circuit.

3) Generate the logic symbol.

4) After that, you need to do the circuit of the 4-bit subtractor using the block diagram of the full
subtractor before this:
i) Draw the schematic diagram of a 4-bit subtractor.

ii) Provide inputs and output to the circuit and run the compilation on the circuit.
iii) Simulate the circuit using Functional Simulation.
End time: 50s
Grid size: 1s
iv) Apply input “A and B” at time intervals:
• 0: 1s ~ 2s
• 1: 2s ~ 4s
• 2: 4s ~ 8s
• 3: 8s ~ 12s
v) Analyze the waveform for the below subtraction operation. Compare the result with a
conventional subtraction operation in decimal.
• 1101-0011
• 0100-1001
• 1111-1100
• 1000-1011
• 1110-1101
vi) If there are any discrepancies, check your schematic design and correct the errors. Re-
simulate until the waveform results comply with your design's truth table.

PART B: Design Problem


1) Design a full subtractor using NAND gate ONLY. Provide the output waveform and circuit
diagram of your design.

SUBMISSION OF PART B
1) Truth Table and circuit diagram
2) Quartus logic circuit
3) Simulation waveform

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