Chapter 1

From Zero to One

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Figure 1.1 Levels of abstraction for an electronic computing system
(Image by Euroarms Italia. www.euroarms.net 2006.)

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Figure 1.2 Flintlock rifle with a close-up view of the lock

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Figure 1.3 Babbage’s Analytical Engine, under construction at the time of
his death in 1871
(image courtesy of Science Museum/Science and Society Picture Library)

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Figure 1.4 Representation of a decimal number

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Figure 1.5 Conversion of a binary number to decimal

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Figure 1.6 Conversion of a hexadecimal number to decimal

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Figure 1.7 Least and most significant bits and bytes

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Figure 1.8 Addition examples showing carries: (a) decimal (b) binary

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Figure 1.9 Binary addition example

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Figure 1.10 Binary addition example with overflow

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Figure 1.11 Number line and 4-bit binary encodings

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Figure 1.12 NOT gate

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Figure 1.13 Buffer

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Figure 1.14 AND gate

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Figure 1.15 OR gate

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Figure 1.16 More two-input logic gates

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Figure 1.17 XNOR gate

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Figure 1.18 XNOR truth table

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Figure 1.19 Three-input NOR gate

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Figure 1.20 Three-input NOR truth table

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Figure 1.21 Four-input AND gate

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Figure 1.22 Four-input AND truth table

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Figure 1.23 Logic levels and noise margins

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Figure 1.24 Inverter circuit

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Figure 1.25 DC transfer characteristics and logic levels

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Figure 1.26 Silicon lattice and dopant atoms

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Figure 1.27 The p-n junction diode structure and symbol

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Figure 1.28 Capacitor symbol

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Figure 1.29 nMOS and pMOS transistors

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Figure 1.30 nMOS transistor operation

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Figure 1.31 Switch models of MOSFETs

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Figure 1.32 NOT gate schematic

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Figure 1.33 Two-input NAND gate schematic

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Figure 1.34 General form of an inverting logic gate

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Figure 1.35 Three-input NAND gate schematic

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Figure 1.36 Two-input NOR gate schematic

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Figure 1.37 Two-input AND gate schematic

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Figure 1.38 Transmission gate

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Figure 1.39 Generic pseudo-nMOS gate

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Figure 1.40 Pseudo-nMOS four-input NOR gate

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Figure 1.41 Three-input majority gate

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Figure 1.42 Three-input AND-OR gate

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Figure 1.43 Three-input OR-AND-INVERT gate

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Figure 1.44 DC transfer characteristics

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Figure 1.45 DC transfer characteristics

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Figure 1.46 DC transfer characteristics

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Figure 1.47 Ben’s buffer DC transfer characteristics

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Figure 1.48 Two-input DC transfer characteristics

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Figure 1.49 Two-input DC transfer characteristics

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Figure 1.50 Mystery schematic

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Figure 1.51 Mystery schematic

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Figure 1.52 RTL NOT gate

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Figure M 01

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Figure M 02

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Figure M 03a

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Figure M 03b

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Figure M 04

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Figure M 05

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Figure M 06

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Figure M 07

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Figure M 08

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Figure M 10

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UNN Figure 1

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