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Output Clock Frequency Range: Table 3-9 Table 3-10 Delay-Locked Loop (DLL)

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7 views

Output Clock Frequency Range: Table 3-9 Table 3-10 Delay-Locked Loop (DLL)

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Thiện Khiêm
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R

DCM Clock Requirements

than the DLL unit. If the application uses both units, then the more restrictive DLL
requirements apply. The table shows the data sheet specification name and an estimated
value. The actual value depends on which speed grade is required for the design and the
value specified in the data sheet takes precedence over the estimate.

Table 3-9 and Table 3-10 show the clock input, CLKIN, frequency range for the Delay-
Locked Loop (DLL) unit. The DLL frequency restrictions apply regardless if the DLL is
used stand-alone or with the DFS unit. The table shows the data sheet specification name
and value. The actual value depends on which speed grade is required for the design, and
the value specified in the data sheet takes precedence over any values shown in this user
guide.
Spartan-3E and Extended Spartan-3A family FPGAs have a single DLL operating range, as
shown in Table 3-9. The frequencies shown for Spartan-3E FPGAs are for the Stepping 1
revision.

Table 3-9: Extended Spartan-3A Family FPGAs: DLL Unit Clock Input Frequency Requirements

Speed Minimum Maximum


FPGA Family Units
Grade CLKIN_FREQ_DLL_MIN CLKIN_FREQ_DLL_MAX
-4 250 MHz
Extended Spartan-3A family FPGAs
-5 280 MHz
5
-4 240 MHz
Spartan-3E FPGAs (Stepping 1)
-5 270 MHz

Table 3-10 shows the frequency range for Spartan-3 FPGAs, where the DLL has two
distinct operating frequency ranges, called Low and High. The operating mode is
controlled by the DLL_FREQUENCY_MODE attribute.

Table 3-10: Spartan-3 FPGAs: DLL Unit Clock Input Frequency Requirements
DLL Frequency Mode Attribute (DLL_FREQUENCY_MODE)

FPGA = LOW = HIGH


Family Minimum Frequency Maximum Frequency Minimum Frequency Maximum Frequency
CLKIN_FREQ_DLL_LF_MIN CLKIN_FREQ_DLL_LF_MAX CLKIN_FREQ_DLL_HF_MIN CLKIN_FREQ_DLL_HF_MIN

Spartan-3
18 MHz 167 MHz 48 MHz 280 MHz
FPGAs

Spartan-3E and Extended Spartan-3A family FPGA DLLs support input clock frequencies
as low as 5 MHz, whereas the Spartan-3 FPGA DLL requires at least 18 MHz.

Output Clock Frequency Range


The various DCM output clocks also have a specified frequency range. See the “Input and
Output Clock Frequency Restrictions” section for more information.

Input Clock and Clock Feedback Variation


As described later in the “A Stable, Monotonic Clock Input” section, the DCM expects a
stable, monotonic clock input. However, for maximum flexibility, the DCM tolerates a

Spartan-3 Generation FPGA User Guide www.xilinx.com 81


UG331 (v1.8) June 13, 2011

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