BASIC PRINCIPLES OF AN AMPLIFIER

Amplification occurs when the amplitude of a signal is increased. Consequently,

the purpose of an amplifier is to produce at its output a magnified replica of a signal at
its input. Signals are ac voltages, which can be sinusoidal, that come from signal
generators. In practice, however, signals are usually complex waveforms that come from
a variety of transducers that convert acoustical, magnetic, or mechanical vibration into
electrical equivalent variations. The basic building blocks of amplifiers are transistors.
Even integrated circuits (ICs) amplifiers otherwise known as operational amplifiers (op-
amps) that have largely replaced amplifier circuits constructed from discrete transistors
are themselves array of transistors and other components built from a single chip of
semiconductor material.
There are two principal types of transistor viz: the bipolar junction transistors
(BJTs) and the field effect transistors (FETs). In the BJTs, a small input-signal current
causes a larger output signal current to flow. Thus a BJT is a current controlled active
device. BJTs can be used in three distinct amplifying configurations: common base
(CB), common emitter (CE), and common collector (CC) otherwise known as emitter
follower. In the FETs, a small input signal voltage causes a large output signal current
to flow, and this current develops an output voltage. Hence a FET is a voltage
controlled active device. Similarly, field effect transistor amplifiers, whether JFET or
MOSFET can be configured as common source (CS), common gate (CG), and common
drain (CD).

COMMON BASE AMPLIFIER

In the common base configuration, the input signal is injected through the emitter
while the output signal is taken from the collector. The base terminal is grounded and
common to both input and output circuits consequently voltages in the circuit are
referenced to the base i.e. VEB, VCB, Veb and Vcb.

Figure 1.1: Common-base amplifier circuit

1
 Figure 1.1 shows the circuit of a single stage common base amplifier using PNP
transistor. Two voltage sources VEE and VCC are used to bias the transistor. The base-
emitter junction is forward biased by VEE while the base- collector junction is reverse
biased by VCC. The operating point of the amplifier is determined by the dc voltages
(VEE and VCC) and resistors RE and RC.

DC ANALYSIS
Applying KVL and ohm’s law at the input, VEE = IEQRE + VEB(ON)
VEE  VEB(ON )
 I EQ 
RE
IEQ is the emitter current at the quiescent point, VEB(ON) is the forward voltage
drop across the emitter-base junction which is about 0.7V for silicon BJTs, and VEE is
the emitter DC supply.
Applying KVL and ohm’s law at the output yields
VCC  VCBQ
I CQ 
RC
ICQ is the collector current at the Q-point, VCBQ is the collector-base voltage at the
Q-point and VCC is the collector DC supply.

AC ANALYSIS
The base-emitter junction offers resistance to the flow of AC signal through it.
This AC resistance is called the dynamic emitter resistance re, and is given by
Vth KT
re  , and Vth 
I EQ q
Where Vth = thermal voltage
K = Boltzmann constant = 1.38 x 10-23J/K
T = temperature in Kelvin
q = electronic charge = 1.602 x 10-19C
Simplified hybrid model of CB amplifier circuit is shown in figure 1.2.

Figure 1.2: Simplified hybrid model of CB amplifier circuit

2
 Capacitors C1 and C2 are assumed to have negligible capacitive reactances at the
frequency of interest while the DC voltages i.e. VEE and VCC are replaced by their
internal resistances.

Characteristics of CB Amplifier

1. Input resistance
rin(base)  re
rin( stage)  ( RE // re )  re if RE >> re
rin(total)  Rs r in( stage)  Rs  ( RE // re )

2. Output resistance
ro  ( RC // RL )
Under no-load condition, R L   ,  ro  RC

3. Current gain
Inherent current gain i.e. the current gain of the transistor
ic
Ai  1
ie
Overall current gain i.e. the current gain of the amplifier
i L ie ic i L
Ais    
i S i s i e iC
Using current divider rule at the input,
 RE  ie RE
ie     is  

 E e
R r is RE  re
ic
   1 if   1
ie
Using current divider rule at the output,
 RC  i RC
i L     ic  l 
 RC  RL  ic RC  RL

4. Voltage gain
Inherent voltage gain i.e. the voltage gain of the transistor
v cb ic ro ro
AV    Since ic  ie if  >> 1
v eb ie re re
Overall voltage gain i.e. the voltage gain of the amplifier

3
 vcb v eb v cb
Avs   
vs vs v eb
Using voltage divider ruler at the input,
 RE // re  veb RE // re
veb     v s  
 RS  RE // re  vs RS  RE // re
vcb
 Av
veb
 RE // re 
 Avs  Av   
 RS  RE // re 
5. Power gain
Inherent power gain i.e. the power gain of the transistor, Ap  Ai . Av
Overall power gain i.e. the power gain of the amplifier Aps  Ais . Avs

Example 1
In the circuit of figure 1.1 V EE  12V , VCC  15V , RE = 22k, RC = 10k, RL=
10k and RS is negligible.

(a) Determine the quiescent values of IE, IC and VCB if the thermal voltage, Vth =
25.7mV, VEB(ON) = 0.7V and hfb =   1.
(b) Find
(i) Current gain of the amplifier in decibel
(ii) Power gain of the amplifier in decibel
(c) If the input signal Vs is sinusoidal with amplitude of 5mV, determine the
amplitude of the output signal, Vcb.

Solution
VEE  VEB(ON ) 12  0.7
(a) I EQ   = 0.514mA
RE 22  10 3
Given that   1, IEQ  ICQ = 0.514mA
VCBQ = VCC - ICQRC
= 15 – (0.514 x 10-3) (104) = 9.86V
(b)

4
 iL ie ic il
Ais    
iS is ie ic
Recall that
ic
   1
ie
ie il
 Ais  
is ic
Applying current divider rule at the input
 RE  V 25.7  10 3
ie     i s Where re  th  = 50
 RE  re  I EQ 0.514  10 3
ie RE 22  10 3
   = 0.998
is RE  re 22  10 3  50
Applying current divider rule at the output,
 RC  i RC 10  10 3
il     ic  l   = 0.2
 RC  RL  ic RC  RL 50  10 3
Ais  0.998  0.2  1.996  0.2
Ais (dB)  20 log 10 (0.2)  13.98dB
ro
(bii) Since Rs = 0, Avs  Av 
re
Where
RC R L
ro  RC \ \ R L 
RC  R L
40  10 6
  8k
50  10 3
ro 8  10 3
 Avs    160
re 50
Power gain, AP  0.2  160  32
Power gain in decibel, APS (dB)  10 log 10 (32) 
(c) If the amplitude of the input signal is 5mV, amplitude of the output signal is
given by Vcb = Avs . Veb = 160 x 5 x 10-3 = 0.8V

COMMON EMITTER AMPLIFIER

In the common emitter configuration, the emitter is grounded and common to
both input and output. Input signal is applied between the base and emitter while output
is taken from the collector-emitter circuit. Figure 1.3 shows an NPN transistor

5
connected in the common emitter mode. As usual, the base-emitter junction is forward
biased by VBB while the collector-base junction is reverse biased by VCC.

Figure 1.3: Common emitter amplifier circuit

In the common emitter mode, the input current is the base current, IB and the
output current is the collector current IC. The ratio of collector current to base current is
the short circuit current gain of a transistor connected in the CE mode and is denoted by
 i.e.
IC ic
  
IB ib
In the CE amplifier, the Q-point or dc operating conditions are determined by
VBB, VCC, RB and RC.

DC ANALYSIS
At the input, by KVL and Ohm’s law,
VBB  VBE (ON )
I BQ 
RB
IBQ is the base current at the Q-point, VBB is the base DC supply voltage, and
VBE(ON) is the base-emitter ON voltage which is about 0.7V for silicon transistor.
Applying KVL and ohm’s law to the output circuit,
VCC  VCEQ
I CQ 
RC

AC ANALYSIS
In the CE amplifier, the dynamic resistance at the base-emitter junction is given
by
Vth Vth
rb  Since re  and IEQ  IBQ
I BQ I EQ

6
 Vth Vth
 re   re   rb
I BQ I BQ
Hence, in the CE amplifier, the dynamic resistance at the base-emitter junction is re.

Figure 1.4: Simplified hybrid model of CE amplifier circuit.

As usual, the capacitive reactances are assumed to be negligible and DC supplies are
replaced by short circuit during AC analysis.

Characteristics of CE amplifier
1. Input resistance
rin(base)  re
rin( stage)  ( RB // re )  re If RB >>β re
rin(total)  Rs r in( stage)  Rs  ( RB // re )

2. Output resistance
ro  ( RC // RL )
Under no-load condition, R L   ,  ro  RC

3. Current gain
ic IC
Inherent current gain, Ai    
ib IB
iL ib ic il
Overall current gain, Ais    
iS is ib ic
Using current divider rule at the input,
 RB  ib RB
ib     i s  
 RB  re  is RB  re

7
 ic
 
ib
In the output circuit,
 RC  iL RC
iL     i s  
 RC  RL  i s RC  RL

4. Voltage gain
 vce ic ro ro
Inherent voltage gain, Av   
vbe ib  re re
Overall voltage gain, Avs i.e. voltage gain of the amplifier is given by
vce vbe v  vbe
Avs     ce   Av 
vs vs  vbe  vs
Using voltage divider rule at the input,
 rin ( stage) 
vbe     vs
R r 
 S in ( stage) 
 rin ( stage) 
 Avs  Av   
R r 
 S in ( stage) 
5. Power gain
Inherent power gain i.e. the power gain of the transistor, Ap  Ai . Av
Overall power gain i.e. the power gain of the amplifier Aps  Ais . Avs

FIXED BIAS COMMON EMITTER AMPLIFIER

The common emitter amplifier circuit of figure 1.3 has two power supplies (VBB
and VCC), one of which is redundant. The base supply can be derived from the collector
supply, VCC by incorporating a suitable value of resistor, RB, to produce whatever base
current and therefore collector current desired.

Figure 1.5: Fixed-bias common emitter amplifier.

8
 All the currents and voltages of the circuit in fig. 1.5 can be found if the value of
 is known.

DC ANALYSIS
By KVL and Ohm’s law at the input,
VBB  VBE (ON )
I BQ 
RB
At the output,
VCC  VCEQ
I CQ 
RC
AC ANALYSIS
The CE amplifier circuit in figure 1.5 has the same AC analysis as the CE
amplifier circuit in figure 1.3.

Example 2
Use the simplified hybrid model circuit to find the current, voltage and power
gains in decibel of the CE amplifier in figure 1.5 which has the following parameters: 
= 100, RB = 228k, RC = 1.4k, RL = 1k, RS = 75,VCC = 12V, VBE(ON) = 0.6V and
Vth = 25mV.

Solution
DC ANALYSIS
VBB  VBE (ON ) 12  0.6
I BQ   = 50A
RB 228  10 3
ICQ = IBQ = 100 x 50 x 10-6 = 5mA

AC ANALYSIS

Simplified hybrid model of the given circuit.

9
 Vth 25  10 3
re   = 500  re  5
I BQ 50  10 6
iL ib ic il
The current gain of the amplifier is given by Ais    
iS is ib ic
Applying current divider rule at the input,
 RB  ib RB 228  10 3
ib     i s     1
 RB  re  is R B   re 228  10 3  500
ic
   100
ib
By current divider rule at the output,
 RC  i RC 1.4  10 3
iL     ic  L   = 0.583
 RC  RL  ic RC  RL 2.4  10 3
Ais = 100 x 0.583 = 58.3
Ais(dB) = 20 log10 (Ais) = 20 log10 (58.3)= 35.32dB
The amplifier’s voltage gain is given by
 v ce  vce vbe vbe
Avs     Av 
vs vbe v s vs
Note that the –ve sign merely indicates that the output signal, vce is 180o out of phase
with the input signal, vs.
ic ro ro
Av  
ib   re re
Where
RC RL 1.4  10 6
ro  
RC  RL 2.4  10 3
= 583.33
583 .33
 Av   116 .67
5
Applying voltage divider rule at the input,
 rin ( stage)  vbe rin ( stage)
vbe     vs  
R r  vs Rs  rin ( stage)
 s in ( stage) 
Where
R B   re 228  5  10 5
rin ( stage)  R B //  re    498.9  499
R B   re 228  10 3  500
vbe 499
   0.87
vs 75  499
Avs = 116.67 x 0.87 = 101.5
The voltage gain in decibel is given by
10
 Avs(dB) = 20 log10 (Avs) = 20 log10 (101.5) = 40.13dB
The amplifier’s power gain in decibel is Aps(dB) = 10 log10(Aps)
Where
Aps = Ais . Avs = 58.3 x 101.5 = 5917.5
Aps(dB) = 10 log10 (5917.5) = 37.72dB

DC LOADLINE, AC LOADLINE AND Q-POINT

In the common emitter amplifier circuits shown in figure 1.3 and 1.5,
VCC = ICQRC + VCEQ
It should be recalled that a BJT is a two junction, three layer device with three regions of
operation namely: cut-off region, active region, and saturation region. Also,
IC = IB + ICEO = IB if ICEO is negligible.
In the cut-off region, the two junctions are reverse-biased, and IB = 0 VCC  VCEQ.
In the cut-off region, VCEQ is designated as VCE(cut-off).
 VCE(Cut-off)  VCC.
In the active region, the first junction is forward biased, while the second junction
is reverse biased. In this region, the collector current is linearly proportional to the base
current. Thus,
VCC = ICQRC + VCEQ = (IBQ)RC + VCEQ
In the saturation region, the two junctions are either forward biased, or first
junction is forward biased while the second junction is reverse biased, and the base
current, IB is sufficiently high such that the equation above i.e. VCC = IBQRC + VCEQ
does not hold again and the transistor is driven into saturation.
In this region, VCEQ is negligible and ICQ is designated as IC(sat).
VCC
 I C ( sat ) 
RC
Consequently, maximum collector current flows in the saturation region while
negligible current flows in the cut-off region.
The plot of ICQ versus VCEQ is a straight line graph with a negative slope or
gradient known as DC load line. Note that DC load line is the locus of all possible
values of ICQ and VCEQ.

AC LOADLINE
The AC cut-off point is given by
Vce(cut-off) = I CQ ro  VCEQ
RC R L
Where ro is the ac output resistance given by ro   RC if RL = 
RC  R L
The AC saturation point is determined as follows,

11
 VCEQ VCEQ
ic  I CQ   I CQ  if RL = 
ro RC
Note that RL =  under no-load condition.
Both DC and AC load lines are drawn on the BJT’s output characteristic curve.
The point of intersection of the load-lines is the operating point or Q-point i.e. quiescent
point of the amplifier.

EXAMPLE 3
In the CE amplifier circuit in figure 1.5, VCC = 12V, VBE(ON) = 0.8V, RB = 1.1M,
RC = 5.1K, RL = 20K, and  = 100.
i. Sketch the DC and AC loadlines of the amplifier, and show the operating
point.
ii. What is the peak-to-peak value of the largest unclipped output voltage of the
circuit?
SOLUTION
At the input,
VCC  VBE (ON ) 12  0.8
I BQ   = 10.2A  10A
RB 1.1  10 6
ICQ = IBQ = 100 x 10-5 = 1mA

DC Loadline
Vce(cut-off)  VCC = 12V
VCC
I C ( sat )   2.35mA
RC
AC Loadline
In the cut-off region,
Vce(cut-off) = I CQ ro  VCEQ
Where

ro 
RC RL

5.1 20   10 6 = 4.1k
RC  RL 25.1  10
3

VCEQ = VCC – ICQRC = 12 – (10-3 x 4.1 x 103) = 6.9V

Vce(cut-off) = Vce(cut-off) = I CQ ro  VCEQ = (10-3 x 4.1 x 103) + 6.9 = 11V

At saturation
VCEQ 6.9
ic ( sat )  I CQ   10 3  = 2.68mA  2.7mA
ro 4.1  10 3

12
The peak-to-peak value of the largest unclipped output voltage is Vpk-pk = 2 x 4.1 = 8.2V

STABILITY OF THE Q – POINT OF BJT

The fixed bias CE amplifier circuit in figure 1.5 which keeps the base current
constant by means of a single resistor connected between VCC and the base, is not the
ideal biasing circuit since it relies on the constancy of the transistor’s  (or hfe) for
maintaining the Q-point i.e. ICQ and VCEQ. Unfortunately,  is not a reliable parameter.
In practice,  varies widely even for transistors of the same type number (e.g.
D313) made in the same batch, and the batch-to-batch variation is even wider. Not only
does  vary from one transistor to another, but it also changes with temperature, base
current and collector-emitter voltage. The consequences are serious for the fixed-bias
circuit.

EXAMPLE 4
If the fixed bias circuit in figure 1.5 has VCC = 30V, RB = 1.5m, RC = 7.5k and
 = 100. VBE(ON) is assumed to be negligible.
i. What are the values of ICQ and VCEQ?
ii. If the BJT is replaced with one having  = 200, and VBE(ON) is assumed to be
negligible, determine the values of ICQ and VCEQ.
iii. Plot the loadlines for (i) and (ii) above and compare the positions of the two
Q-points under no load condition.

13
Solution
i. Given that VCC = 30V, RB = 1.5M, RC = 7.5,  = 100, and VBE(ON) = 0.
VCC  VBE (ON ) 30
I BQ    20 A
RB 1.5  10 6
ICQ = IBQ = 100  20  10-6 = 2mA
VCC 30
I C ( sat )    4mA
RC 7.5  10 3
VCEQ = VCC - ICQRC = 30 – (2  10-3  7.5  103) = 15V

Q-point is at the centre of the active region.

(ii) When  = 200

VCC  VBE (ON ) 30
I BQ   = 20A
RB 1.5  10 6
ICQ = IBQ = 200  20  10-6 = 4mA
VCC 30
I C ( sat )   = 4mA
RC 7.5  10 3
VCEQ = VCC - ICQ RC = 30 – (4  103  7.5  10-3) = 0

Q – point is in the saturation region

14
Hence, it can be concluded that in fixed bias circuit, the Q – point (ICQ and VCEQ)
changes with variation in . In addition to variation in , other factors that affect the
stability of Q – point of a transistor include:
i. Variation in the supply voltage due to imperfect regulation.
ii. Variation in the circuit resistances due to tolerance
iii. Variation in the cut-off voltage due to leakage current which is temperature
dependent.
iv. Variation in the quiescent base-emitter voltage VBEQ due to its dependence on
temperature.
v. There are wide variations in parameters for a particular mass produced
transistor type.

VOLTAGE DIVIDER BIAS CE AMPLIFIER

The objective of biasing an amplifier circuit is to establish a proper operating
point and ensure that the operating point is maintained despite variation in temperature
or variation in the characteristics of the individual transistor of the same type employed
in multistage amplifier circuit. A fully stabilized CE amplifier circuit that is relatively
independent of the variation in the parameters of the transistor used is shown in figure
1.6
Resistors R1 and R2 form a voltage divider that provides a dc bias voltage at the
base of the BJT, thus ensuring a relatively stable Q-point despite variations in  and
other circuit parameters.

Figure 1.6: Voltage-divider bias CE amplifier circuit

15
Figure 1.7: Thevenin equivalent of the voltage divider bias CE amplifier circuit in
figure 1.6

DC ANALYSIS
R1 R2
RTHEV  RB 
R1  R2
 R2 
VTHEV  VBB     VCC
 R1  R2 
Applying KVL and ohm’s law to the input circuit,
VBB – IBQRB – VBE(ON) – IEQRE = 0
IE = IB + IC = (1 + )IB  IB if  >> 1
:. VBB - VBE(ON) - IBQ(RB + RE) = 0
VBB  VBE (ON )
 I BQ  and ICQ = IBQ
RB  RE
The resistors should be such that RE >> RB and RC >> RE. It is customary to take 10RB
= RE.
As with other CE circuits, DC loadline for voltage divider bias circuit gives
graphical details of IC versus VCE.
By KVL and ohm’s law at the output,
VCC – ICQRC – VCEQ – IEQRE = 0
Since ICQ  IEQ.
VCEQ = VCC - ICQ (RC + RE).
In the cut-off region, ICQ  0, and VCE(cut-off) = VCC.
In the saturation region,
VCC
VCEQ  0, and I C ( sat ) 
RC  R E

16
AC ANALYSIS
i. With CE i.e. emitter bypass capacitor, the voltage-divider bias CE amplifier
has the same AC analysis as previous CE amplifier circuits.
ii. Without CE, RE will be in series with hie = re which results in an increase in
the input resistance of the transistor.

1. Input resistance
rin(base)   re  RE 
rin( stage)  RB //  (re  RE )
rin(total)  Rs r in( stage)  Rs  RB //  (re  RE )

2. Output resistance
ro  ( RC // RL )
3. Current gain
ic IC
Inherent current gain,     Ai
ib IB
iL ie ic il
Overall current gain, Ais    
iS is ie ic
Where
ib RB ic iL RC
 ,  and 
is R B   re  R E  ib iC RC  R L

4. Voltage gain
ic ro ro
Inherent voltage gain, Av  
ib  re  R E  re  R E
Vbe
Overall voltage gain, Avs  Av 
Vs

17
 vbe rin ( stage)
Where 
vs Rs  rin ( stage)
5. Power gain
Inherent power gain, Ap= Ai . Av
Overall power gain, Aps= Ais . Avs

Without CE, the voltage gain of the amplifier is drastically reduced but the resulting
amplifier is highly stable thus ensuring high fidelity.

Example 5
The sinusoidal voltage source in figure 1.6 has a negligible resistance. If R1 =
82k,
R2= 12k, RC = 8.2k, RE = 1k, RL = 10k,  = 80, VCC = 9V and VBE(ON) =
0.7V
(a) Determine
(i) Quiescent values of IC and VCE
(ii) The collector power dissipation, PD
(b) Draw the small signal equivalent circuit of the amplifier and use the given
parameters to calculate the power gain of the amplifier in decibel if thermal
voltage Vth = 25mV.
(c) Determine the voltage gain of the amplifier when the emitter bypass capacitor is
removed.

Solution
The Thevenin equivalent circuit is as shown in figure 1.7
R1 R2 82  12  10 6
RTHEV  R BB    10.47 k
R1  R2 94  10 3
 R2   12  10 3 
VTHEV  VBB     VCC     9  1.15V
3 
 R1  R2   94  10 
Applying KVL and ohm’s law to the input circuit,
VBB  VBE (ON ) 1.15  0.7
I BQ    4.97 A
RB  RE 10.47  10 3  80  10 3
I CQ  I BQ = 80  4.97  10-6  0.4mA
VCEQ = VCC - ICQ (RC + RE)
= 9 – 0.4  10-3(8.2 + 1)  103 = 5.32V
PD = ICQVCEQ = 0.4  10-3  5.32 = 2.13mW

18
AC ANALYSIS

Vth 25  10 3
hie  re    5.03k
I BQ 4.97  10 6
5.03  10 3
 re   62.88
80
RC RL 8.2  10 7
ro    4.51k
RC  RL 18.2  10 3
ro 4.51  10 3
Since RS = 0, AVS  AV    71.72
re 62.88
Current gain
iL ie ic il
Ais    
iS is ie ic
At the input
ib RB 10.47  10 3
   0.68
is RB  re 15.5  10 3
ic
   80
ib
At the output,
iL RC 8.2  10 3
   0.45
iC RC  RL 8.2  10   10 3
Ais= 0.68  80  0.45 = 24.48
Aps= Ais . Avs = 24.48  71.72 = 1766.48

In decibel, Aps(dB) = 10log10(Aps) = 10log10 (1766.48) = 32.47dB

When the emitter bypass capacitor is removed
ro 4.51  10 3
  
AVS AV
re  RE 62.88  10 3   4.24
Note that the voltage gain is drastically reduced from 71.72 to 4.24 when CE is removed.

19
EMITTER FOLLOWER OR COMMON COLLECTOR AMPLIFIER

Figure 1.8: Emitter Follower or Common Collector Amplifier

In the circuit of figure 1.8, the input signal voltage Vs is supplied to the base
through the coupling capacitor C1. The output signal Vo is taken from the emitter
through capacitor C2.

DC ANALYSIS
By KVL and Ohm’s law
-VEE + IBQRB + VBE(ON) + IEQRE = 0
Recall that IE = IB + IC = (1 + )IB  IB if  >> 1
– VEE + IBQRB + VBE(ON) + IBRE = 0
VEE  VBE (ON )
 I BQ 
RB  RE

Figure 1.9: Emitter follower or common collector amplifier with a single supply VCC.

20
DC ANAYSIS
By KVL and Ohm’s law
VCC - IBQRB + VBE(ON) + IEQRE = 0
VCC  VBE (ON )
 I BQ 
RB  RE

Figure 1.10 Voltage divider bias emitter follower or common-collector amplifier.

Figure 1.11: Thevenin equivalent of the CC amplifier circuit in figure 1.10

VTHEV  VBE (ON )

I BQ 
RTHEV  RE
Let VTHEV = VBB and RTHEV = RB
VBB  VBE (ON )
 I BQ 
RB  RE

21
 The emitter follower or common collector amplifier circuit in figures 1.8, 1.9,
1.10 and 1.11 have the same AC analysis.
For the AC analysis, all the capacitors and DC voltage suppliers are replaced by
short circuits. The resulting AC equivalent circuits are shown in figure 1.12 (a) and (b).

Figure 1.12 (a) AC equivalent (b) Rearranged AC equivalent

Note that is the rearranged AC equivalent figure 1.12b, the collector terminal is
the grounded or common terminal

AC ANALYSIS

1. Input resistance
rin(base)   re  ro    re  RE  If RL = 
rin( stage)  RB //  (re  ro )  RB //  (re  RE ) If RL = 
rin(total)  Rs r in( stage)  Rs  RB //  (re  ro )
 Rs  RB //  (re  RE ) If RL = 
2. Output resistance
ro  ( RE // RL )  RE If RL = 

22
3. Current gain
ie
Inherent current gain, Ai    1
ib
iL ib ie il
Overall current gain, Ais    
iS is ib ie
By current divider rule at the input,
ib RB iL  RE 
 , and    at the output
is RB   re  ro  iC  RE  RL 
 RB   RE 
 Ais       1   
 RB   re  ro    RE  RL 
4. Voltage gain
ic ro ro
Inherent voltage gain, Av  
ib   re  ro  re  ro
if ro >> re, AV  1
 rin ( stage) 
Overall voltage gain, Avs     ro
R r  r r
 S in ( stage)  e o
 rin ( stage) 
 Avs  AV   
R r 
 S in ( stage) 
5. Power gain
Inherent power gain, Ap = Ai . A v
Overall power gain, Aps= Ais . Avs

EXAMPLE 6
The common collector amplifier circuit in figure 1.10 has the following
parameters:
R1 = 12k, R2 = 10k, RE = 1k, RL = 25k,  = 150, VCC = 15V and RS is
negligible.
Determine the power gain in decibel when thermal voltage, Vth = 25mV.

Solution
R1 R2 12  10 7
RB    5.45k
R1  R2 22  10 3
 R2  10  15
VBB     VCC   6.82V
 R1  R2  22
VBB  VBE (ON ) 6.82  0.7
I BQ    39.4A
RB  RE 5.45  10 3  150  10 3

23
 ICQ = IBQ = 150  39.4  10-6 = 5.91mA

AC ANALYSIS

Vth 25  10 3
re    4.24
I BQ 39.4  10 6
iL ib ie il
Current gain of the amplifier is given by Ais    
iS is ib ie
ie  ic = ib
ib iL
 Ais    
is ie
Applying current divider rule at the input
 RB 
ib     i s
 B
R   re  r 
o 

Where
RE RL 250  10 3
ro    200 
RE  RL 1250
ib RB 5.45  10 3
   0.151
is R B   re  ro  5.45  10 3  1504.23  200 
ic
   150
ib
Applying current divider rule at the output,
 RE 
iL     ie
 RE  RL 
iL  RE  1000
      0.8
ie  RC  Re  1250
Ais = 0.151  150  0.8 = 18
Since RS = 0, the voltage gain of the CC amplifier is given by

24
 ro 200
AVS  AV  =  0.98
re  re 4.23  200
Power gain of the amplifier is given by
Aps = Ais . Avs = 18  0.98 = 17.64
In decibel, Aps (dB) = 10log10 (Aps) = 10log10(17.64) = 12.46dB

CASCADING AMPLIFIER STAGES

To realize greater signal gain than obtainable from single amplifier stage, a
number of stages are cascaded as illustrated in the block diagram below.

Block diagram of a cascaded amplifier.

In a cascaded amplifier, the output of one amplifier stage is coupled to the input
of the following stage. The overall gain is the product of the individual stage gains i.e.
AT = A1  A2  ……………………  An
Where
AT = Overall gain i.e. total gain
A1 = gain of the first stage
A2 = gain of the second stage
An = gain of the nth stage
When determining the total gain of cascaded stages, the gain of the last stage is found
first. After its gain and input resistance are known, the gain and input resistance of the
preceding stage can be determined. This process is simply repeated with each preceding
stage if there are more than two stages.

Example 7
In the circuit shown below, each transistor has  = 80 and VBE(ON) 0.6V. Determine
the overall voltage gain of the amplifier if thermal voltage, Vth = 25mV, and all
reactance’s are assumed to be negligible.

25
Solution
DC ANALYSIS OF TRANSISTOR Q2
R12 R22 22  220  10 6
RB 2    20k
R12  R22 (22  220 )  10 3
R22  22  10 3 
V BB 2   VCC     20  1.82V
3 
R12  R22  ( 22  220 )  10 
VBB 2  VBE (ON )  1.82  0.6 
 I BQ 2     6.2 A
RB 2  RE 2  3 
 20  10  80  12  10 
3

ICQ = 80  6.2  10-6 = 0.5mA

AC ANALYSIS of Q2
Vth 25  10 3
re 2    50.4
I BQ 80  6.2  10 6
RC 2 R L 12  33  10 6
ro 2  =  8.8k
RC 2  R L 12  33  10 3
iC 2 r02 r02 8.8  10 3
AV 2     174
ib 2  re 2 re 2 50.4

DC ANALYSIS OF Q1
R11 R12 330  39  10 6
R B1    34.88k
R11  R12 330  39   10 3
 R12   39  10 3  20 
VBB1     VCC   3
 2.11V
 R11  R12   330  39   10 

26
 VBB1  VBE (ON ) 2.11  0.6
   4.35A
 
I BQ1
RB1  RE1 34.88  10 3  80  3.9  10 3
IEQ1  ICQ1 = 80  4.35  10-6 = 0.35mA

AC ANALYSIS OF Q1
Vth 25  10 3
re1    71.84
I BQ1 0.35  10 3
ro1 = R21//R22//RC1//re2
= RB2//RC1//re2 Since RB2 = R21//R22
Consequently
20  22  10 6
RB 2 // RC1   10.48k
20  22   10 3
10.48  4.032  10 6
:. r01 = 10.48k//4.032k   2.91k
14.512  10 3
r01 2.91  10 3
Av1    40.5
re1 71.84
 V   V 
The overall voltage gain, AVS   ce1   ce 2 
 Vbe1   Vbe2 
Where Vce1 = Vbe2
Vce
 AVS   Av1  Av 2 = 40.5  174.6 = 7071.3
Vbe1
Note that two inverting amplifiers cascaded have a non-inverting gain.

FETs AS AMPLIFIERS
Just as the common emitter amplifier is the most versatile and widely used of all
BJT configurations, the common source (CS) amplifier is the most versatile and widely
used of all FET configurations.

EXAMPLE 8
The CS amplifier with voltage divider bias shown in figure 1.13 has pinch-off voltage,
VP = - 3V, and drain – source saturation current IDSS = 2mA. Determine the values of
R1, R2, RD and RS to produce a Q-point at IDQ = 1mA and VDSQ = 8V. Assume that
RG = 150k, VGG = 2.5V and VDD = 16V

27
Figure 1.13: Voltage divider bias CS amplifier

Solution
The Thevenin equivalent is shown below

 R2 
VTHEV     VDD
 R1  R2 
Let VTHEV = VGG
VGG R2 2 .5
    0.156
V DD R1  R2 6
R1 R2
RTHEV   RG = 150k
R1  R2
Given that
IDQ = 1mA, IDSS = 2mA Vp = -3V
2
 
2
VGSQ  VGSQ 
I DS  I DSS 1   10 3  2  10 1 
3


 Vp  3
   
VGSO = + 0.879V
For n-channel JFET, VGS is always negative  VGSQ = - 0.879V

28
By applying KVL and ohm’s law in the input circuit,
VGG = IGRG + VGSQ + IDQRS
but IG = 0
VGG  VGSQ 2.5   0.879 
 RS    3.3k
I DQ 10 3
 R2 
RG  R1    0.156 R1
 R1  R2 
RG 150  10 3
 R1    961 .54 k
0.156 0.156
Since
R2
 0.156
R1  R2
R2 (1 – 0.156) = 0.156R1
0.156 R1 0.156  961 .54  10 3
 R2    177 .72 k
1  0.156 0.844
Applying KVL and ohm’s law to the output circuit,
VDD = IDQRD + VDSQ + IDQRS
VDD - VDSQ = IDQ(RD + RS)
VDD  VDSQ 16  18
 R D  RS    8k
I DQ 10 3
RD = (8 - 3.38)  103 = 4.62k

AC ANALYSIS OF CS AMPLIFIER
The ID versus VGS curve of a FET shows how the value of drain current, ID is
determined by the value of gate-to-source voltage, VGS. FETs are called voltage
controlled devices because changes in VGS result into changes in ID. Trans-conductance,
gm describes how much control the input voltage, VGS has on the output current, ID i.e.
I D id
gm  
VGS Vgs
 id  g mVgs

29
Since RG >> RS and RD//RL = ro
The output voltage of CS is vo  id ro   g m v gs ro
Since the input voltage is Vgs
gmVbe ro
AV    gmro
V gs
The –ve sign merely indicates that the output signal is 180o out of phase with the
input signal like that of CE amplifier.
Output resistance
ro = RD//RL = RD if RL = 
Input resistance, rin = RG
 id
Inherent current, gain Ai 
iin
 gmVgs
 Ai    gmRG
V gs 
 RG 

Overall current gain
 RD 
Ais   gmRG  
 RD  RL 
Power gain
Inherent power gain, Ap = Ai . Vv
Overall power gain which is the amplifier’s gain is given by Aps = Ais . Avs.

POWER AMPLIFIERS
Power amplifiers are classified by letters according to the amount of time the
active device is on while power is delivered to a load, and this largely determines the
efficiency.

CLASS-A AMPLIFIERS
In class-A amplifiers, the active device, a BJT or FET is on for the whole of time
that power is being delivered to the load. The duty cycle is 100% and the output current
flows through the load during the entire cycle of the input signal i.e. it has a conduction
angle of 360o.
VCE (max) VCE ( cutoff )
Maximum power is delivered to the load when VCEQ  
2 2
Maximum efficiency is 25%. The remaining 75% is lost as heat in the transistor and
load.

30
 CLASS – B AMPLIFIERS
A class B amplifier is one in which the operating point is at an extreme end of its
characteristic, so that the quiescent power dissipation is very small. Hence, either the
quiescent current, or the quiescent voltage is approximately zero. The output current
flows for only half cycle (180o). If the Q-point is located at the cut-off point or very
close to it, the output current only flow for the positive half cycle of the input signal.
Thus,
VCEQ  VCC and ICQ  0, and PD = VCEQ ICQ  0
CLASS B PUSH-PULL AMPLIFIER
The efficiency of class – B amplifier is greatly improved when a matched pair of
complementary (NPN and PNP) transistors are used in push-pull arrangement as shown
below.

Figure 2.1: Class B push pull amplifier.

Note that no DC bias is used with transistors Q1 and Q2 thus both of them are
biased at cut-off and neither conducts collector current in the absence of input signal VS
consequently capacitor C2 becomes unnecessary if all the DC components of the
preceding stage have been filtered by capacitor C1.
When signal VS with significant amplitude is applied to the circuit
shown above, the base-emitter junction of transistor Q1 is forward biased during the
positive half cycle such that Q1 is driven into conduction while Q2 is driven further into
cut-off and current is pushed through the load by Q1. During the negative half cycle, the
base-emitter junction of Q2 is forward biased by the input signal causing Q2 to be driven
into conduction while Q1 is driven further into cut-off as a result of which current is
pulled through the load by Q2. If the input signal is large enough, the conducting BJT

31
can be driven into saturation. A saturated Q1 places up to +VCC across the load RL while
a saturated Q2 places up to –VCC across the load. The output signal voltage can therefore
swing between +VCC and –VCC supply voltage. Unlike class-A amplifier in which the
maximum efficiency is less than 25%, the efficiency of class –B push-pull amplifier is
about 78.5%.
The major drawback of class-B push-pull amplifier is cross over distortion. The
distortion is caused by the fact that the input signal has to exceed + VBE(ON) before either
BJT starts conducting. The distortion is more pronounced is small signals. Since the
distortion occurs while the input signal is crossing 0V, it is called cross over distortion.
A further drawback in class-B push-pull amplifier is the need for a bipolar supply i.e
+VCC and –VCC.

Figure 2.2: Cross over distortion.

CLASS AB PUSH PULL AMPLIFIERS

To eliminate crossover distortion in class – B push-pull amplifier, the base-
emitter junctions of transistor Q1 and Q2 are biased at about 0.7V (if both Q1 and Q2 are
silicon transistors) so that even small input signal can easily drive the transistor into
conduction. The bias is called the turn-on bias. The result is then class – AB rather than
class-B operation.

32
Figure 2.3: Class-AB push-pull amplifier

The diodes and BJTs in figure 2.3 are made of the same material (silicon)
consequently the voltage drops across the terminals of the diodes equal the base-emitter
on voltage (VBE(ON)) of the transistors. Therefore, when input signal is not applied both
BJTs remain on the edge of conduction. With the application of input signal, Q1 pushes
current through the load during the positive half cycle while Q2 conducts and pulls
current through the load during the negative half-cycle.

CLASS-C TUNED AMPLIFIER

Sometimes, amplifiers are designed to amplify a narrow band of frequency
adjacent to some central frequency,  o . These tuned amplifiers are designed to reject all
frequencies below a lower cut-off frequency w2. Tuned amplifiers are also known as
narrow band or band pass amplifier due to the fact that only the pass band (  2  1 ) is
amplified while other frequencies are rejected.
1 1
At the resonant frequency  L   0  fo 
C 2 LC

Figure 2.4: Class-C amplifier with transformer coupled load.

33
3.0 AMPLIFIER FREQUENCY RESPONSE
Hitherto, the amplifier gain has been assumed to be independent of
frequency whereas in reality when an RC-coupled small signal amplifier is used to
amplify a signal covering a wide range of frequencies such as video signal ranging from
dc (f = 0) to as high as MHz, it is observed that the gain of the amplifier in both
amplitude and phase is not constant throughout the frequency range. The gain amplitude
increases with frequency in the low frequency region, levels off and becomes constant at
the middle range of frequencies while it decreases with increasing frequency in the high
frequency region. The frequency response of small signal amplifier in the low frequency
region is similar to the frequency response of a high pass RC circuit while its frequency
response in the high frequency region is analogous to the frequency response of a low
pass RC circuit as shown in the figures below.
Vo R
AV   XC 
1

1
Vin R X2 2
WC 2fc
C
Where

Figure 3.1a: A high-pass RC circuit

(b) (c)

Figure 3.1b Av versus frequency curve of a high-pass RC circuit

34
Figure 3.2: A low-pass RC circuit and its Av versus frequency curve

Figure 3.3 Frequency response of amplifier

Note the change in the phase angle of the signal from +90o at the low frequency
end to -90o at the high frequency end with 0o (constant) phase angle at the mid-
frequency range. The behavior is true for transistors (BJT FET or even vacuum tubes).
The frequency bandwidth (f2 – f1) is defined by the low and upper cut-off
frequencies (or half power) frequencies i.e. f1 & f2 respectively. These are the
1
frequencies at which the gain is reduced to 2 of the maximum value, or the signal
1
power is reduced to the 2 of the maximum power. Thus, at cut-off
AV (max)
AV ( cutoff )   0.707 AV (max)
2
Note that in figure 3.3, AV(max) is normalized to 1, consequently
35
 AV (cutoff )   3.01   3 dB. The phase angle at f1 is +45o and at f2 is – 45o

ANALYSIS OF AMPLIFIER CIRCUITS

Figure 3.4: BJT single stage amplifier and its equivalent circuit.
The interelectrode capacitances C (effective input capacitance between emitter and
base) and Cjs (collector-base junction capacitance) are also included. The circuit model
used for the analysis is called the hybrid-π model. r in figure 3.4 is the resistance of
the base-emitter junction which is identical to hie in the h-parameter model
h fe ib h fe ib h fe
gm    Since vbe  ib hie
vbe ib hie hie
The frequency response of the amplifier circuit can be divided into the low,
medium and high frequency regions.

36
 THE MID-FREQUENCY RANGE
The fact that the gain of the amplifier is independent of frequency in this region
indicated that the capacitance can be neglected in the circuit model for this region.

Figure 3.5 Mid-frequency range circuit model

Rin(stage) = RB//r In a practical situation RB >> r  rin(stage)  r

Using voltage divider rule,
 rin ( stage)   r 
vbe     VS     v S (1)
r 
 in ( total)   RS  r 
At the output circuit,
RC R L
ro  RC // R L 
RC  R L
Vo   g m vbe ro (2)
Substituting equation (1) into equation (2)
 rV 
Vo   gm  S  ro (3)
 RS  r 
The mid-range voltage gain of the amplifier
Vo r R R
Avsm    gm  C L (4)
VS RS  r RC  R L

THE LOW FREQUENCY REGION

The coupling capacitances C1 and C2 are the significant components and must be
included in the circuit model.

Figure (3.6a)

37
Applying Thevenin’s theorem to the left of point AB in the output circuit, the circuit
model is redrawn as shown in figure 3.6b.

The total input impedance is given by

1
Z in (total)  Rs  r 
jC1
Using voltage divider rule, the voltage drop across r is
 
 r 
Vbe     VS (5)

 S   1
jwC1 
R r

The total output impedance is given by
1
Zo  RC  RL 
jC 2
Using voltage divider rule in the output circuit, the voltage drop across RL is given by
 
 RL 
Vo      g mVbe RC  (6)
 RC  RL  1 jwC 
 2 

Substitute equation (5) into equation (6)

   
 RL   rVS 
Vo    gm   RL
 RC  RL  1 jwC   RS  r  1 jwC 
 2   1 

 g m rVS RC RL
Vo   (7)
RS  r  1 RC  RL  1
jwC1 jwC 2
The low frequency gain of the amplifier is
V  g m r RC RL
AVSL  o   (8)
Vs Rs  r  1 RC  RL  1
jwC1 jwC2
Divide both numerator and denominator of equation (8) by (Rs + r)(RC + RL)

38
  r  RC RL
 gm 
Vo  RS  r  RC  RL 
 AVSL   
Vs 1 1
1 1
jwC1 RS  r  jwC 2 RC  RL 

 r   RC R L  1 1
 AVSL   gm       (9)
 RS  r   RC  R L  1 1
1
1
RC  RL 
jwC1 RS  r  jwC 2
Combining equation (4) and equation (9)
1 1
AVSL  AVSM  
1 1
1 1
jwC1 r  RS  jwC 2 RC  RL 
1 1
 AVSM   (10)
j j
1 1
wC1 r  RS  wC2 RC  RL 
1 1
 AVSM   (11)
 
1  j 11 1  j 12
 
Where
1 1
11  and 12  (12)
C1 r  RS  C 2 RC  RL 
When  =  11 or  =  12 i.e. either of the cut-off frequencies, then
1
AVSL  AVSL
2
11 12
If  >>  11 (or  12), then 1 >> j or j , and AVSL  AVSM
 
 
If  <<  11 (or  12), then 1 << j 11 or j 12
 
Consequently,
1 1      
AVSL  AVSM .   AVSM     
11 12   j 11    j 12 
j j
 
 j  j 
AVSL  AVSM   
 11  12

Either of the two cut-off frequencies is substantially greater than the other and
dominates the low-frequency response to give its characteristic rise with increasing
frequency of 20dB/decade.

39
       
Assuming that      , then AVSL  AVSM (13)

 11  
 12  11
Equation (13) indicates that the low frequency gain AVSL increases with frequency i.e.
AVSL   as   

HIGH FREQUENCY RESPONSE

Above the mid-frequency range, the reactances of the coupling capacitors are
negligible, but the inter-electrode capacitances become significant. The circuit mode
used for the high-frequency response of BJT is the hybrid -  model shown in figure
3.7a.

Figure (3.7a)
The bridging capacitance C jc complicates the analysis and is replaced by its equivalent
in the circuit of figure (3.7b).

Figure (3.7b)
The bridging capacitance C jc provides a feedback path between the output and
input of the circuit, thus the equivalent capacitance, C eq is given by
Ceq  1  AV C jc  C (14)
Where the internal voltage gain of the transistor is given by
Vo  gmVbe ro
AV     g m ro (15)
Vbe Vbe
Substitute equation (15) into equation (14)
 Ceq  1  gmro C jc  C (16)

40
The amplification of the bridging capacitance is known as the Miller effect, and Ceq is
known as the Miller capacitance.
At the input circuit,
r 1
jwC eq r
Z in(stage)   (18)
r  1 1  jwr C eq
jwC eq
Zin(total) = RS + Zin(stage)
Using voltage divider rule
 Z in ( stage) 
Vbe     Vs
Z 
 in ( total) 
Applying KVL to the output circuit,
Vo   g m vbe ro (19)
Substitute equation (18) into equation (19)
 Z in ( stage) 
Vo   gm   VS ro
Z 
 in (total) 
The high frequency voltage gain is given by
 r 
 
 Z in ( stage)   1  jwr C 
AVSH 
Vo
  gm   ro   g m ro   eq 
(20)
Vs Z  r
 in (total)  RS 
1  jwr C eq
 r   r 
  g m ro     g m ro  
 R 1  jwr C   r   R  r  jwr C R 
 s  eq    S   eq S 
 
 
 1   g m ro r  1 
  g m ro r  
  (21)
 R  r  jwr C R  RS  r jwr C eq RS
 S   eq S   1  
 RS  r 
RC R L
Since ro 
RC  R L
 
 
Vo r RC RL  1 
AVSH   gm    (22)
VS RS  r RC  RL jwr C eq RS
 1  
 RS  r 
Combining equations (4) and (22)
1
AVSH  AVSM  (23)

1 j
2

41
 RS  r
Where  2 is the cut-off frequency given by  2 
r C eq RS
1
If    2 , AVSH  AVSM 
2
Since   2 f2, the high frequency cut-off frequency in Hz is f2.
If    2  jw  1
2
 
 1    W 
AVSH  AVSM     AVSM  2  =  jAVSM  2  (24)
j    j  W 
 2 

Equation (24) shows that AVSH decreases with increasing frequency i.e. AVSH  0 as 
 .

GAIN IN DECIBELS (dB)

In equation (14), assuming that 11 is the dominant cut-off frequency,
1
 AVSL  AVSM 
11
1 j

1
 
2

    11  2 
1
2
AVSL
  1   1    
AVSM    2      
1   11  
    
Recall that AV(dB) = 20 log10 (AV)
Consequently,
 12
AVSL   11  2    11  2 
(dB)  20 log 10 1       10 log 10 1     (25)
AVSM          
At the lower cut-off frequency, 11   , and
AVSL
(dB)   10 log 10 (2)   3.01dB
AVSM
Hence at f1 and f2, the gain has fallen 3dB below the mid-frequency gain, hence f1
and f2 are called cut-off frequencies or “– 3dB frequencies”.
At values of frequencies when   11 , equation (25) becomes
 
(dB)   20 log 10 11    20 log 10  1   20 log 10  f 
AVSL f
(27)
AVSM     f  f1 

Similarly at values of frequencies when    2 in equation (26), the equation becomes.

42
  
   20 log 10  f 
AVSH
(dB)   20 log 10  (28)
AVSM  2   f2 
AVSL AVSH
The plot of (dB) versus f and (dB) versus f is exactly like the
AVSM f1 AVSM f2

frequency response plotted in figure 3.3. In the low frequency region, the gain increases
by 20dB for every 10-fold increase in frequency i.e. the slope of the response in the low
frequency region is 20dB/decade. In the high frequency region, the gain decreases by
20dB for every 10-fold increase in frequency i.e. the slope of the response in the high
frequency region is -20dB/decade.

4.0 FEEDBACK AMPLIFIERS

In feedback amplifiers, a fraction of the output signal is fed back into
the input circuit. Feedback facilitates the improvement of various aspects of amplifiers.
Consider the circuits shown below.

(a)
(b)
Figure 4.1: (a) Amplifier without feedback (b) Amplifier with feedback

A system with feedback can be described with a block diagram as shown below.

Figure 4.1c Block diagram of a circuit with feedback

43
 Consider the block diagram above which shown a circuit of some kind with an
input signal VS and output signal Vo. The circuit has forward gain G so that without
feedback.
Vo Vo
G   (4.1)
Vin Vs
Without feedback, Vin = Vs.
With feedback, a fraction of the output is fed back into the input via a feedback path
with a gain, H such that HVo is added to the input. The new input is now.
Vin = Vs + VF (4.2)
Where
Z 2Vo
VF = HVo = (4.3)
Z1  Z 2
The output voltage with feedback is
Vo = GVin = G(Vs + HVo)  Vo(1 – GH) = GVs

Vo G
 GF   (4.4)
Vs 1  GH

Where G = Open loop gain or forward gain,

GF = Feedback gain. It is also known as overall gain or closed loop gain

GH = loop gain, and H = feedback factor

There are four cases to consider.

CASE 1: GH = 0. No feedback Vin = VS.

Vo Vo
 G  
Vs Vin

CASE 2: GH < 0. Negative feedback

Vo G G
   GF (4.5)
Vs 1   GH  1  GH

Obviously GF < G since (1 + GH) > 1

The amplitude and phase of the signal fed back into the input are such that the
overall gain of the amplifier GF is less than the forward gain G. This occurs when the
loop gain GH is 180o out of phase with the input signal i.e. GH is negative. Since
negative feedback reduces the amplifier gain it is called degenerative feedback.
44
IMPROVING FREQUENCY RESPONSE BY NEGATIVE FEEDBACK

The forward gain G of amplifiers is frequency dependent because of the

capacitive reactance’s in the circuit. The feedback factor H can however be obtained by
purely resistive element as shown in figure 4.1b in which.

Z1 = R1 and Z2 = R2

If GH is made very large at the frequency of interest, then

Vo G G 1
GF     (4.6)
Vs 1  GH GH H

i.e. the feedback gain can be made independent of frequency. The resulting amplifier is
very stable because it is not affected by changes in temperature, device parameters,
supply voltage and the ageing of circuit components. The feedback gain GF is however
much smaller than the forward gain G under this condition i.e. the overall gain of the
amplifier is reduced in favour of improved frequence response.

In addition to improved frequency response, negative feedback provides a

number of advantages in an amplifier circuit among which are the following. Operating
point can be made practically independent of device parameters. An example of this is
the fully stabilized CE amplifier shown in figure 2.2 in which the collector current I CQ is
made to be relatively independent of . Various distortions like amplitude, phase,
frequency and harmonic distortions are considerably reduced. Higher fidelity i.e. output
signal is a faithful reproduction of the input signal. Gain can be made practically
independent of the reactive element (i.e. Capacitive reactance’s) which results in a
highly stabilized gain. Input and output impedances can be modified as desired.

CASE 3 0 < GH < 1 positive feedback

Vo G
GF    G F  G Since (1 – GH) < 1
Vs 1  GH

Positive feedback is a means of providing high gain.

CASE 4: GH = 1. Positive feedback (oscillator)

Vo G G G
GF       (4.7)
Vs 1  GH 11 0

45
 When GH = 1, no input signal is required to obtain an output signal. Under this
condition, the amplifier is said to be unstable, and will go into oscillation of a frequency
and type determined by the passive components of the amplifier. Such an unstable
amplifier becomes an oscillator or signal generator that generates an ac output signal
without requiring any externally applied input signal.

Barkhausen Criterion: Hitherto both G and GH have been assumed to be

independent of frequency whereas the response of a real amplifier depends on
frequency. Since the phase shift  introduced in a signal being transmitted through a
reactive network is invariably a function of frequency, then the frequency at which a
sinusoidal oscillator will operate is the frequency for which the phase shift of the loop
gain GH is zero or an integral multiple of 2.

Hence the condition for the instability of amplifier (i.e. oscillation) is that the
magnitude and phase shift of the loop gain GH must be unity and zero (or an integral
multiple of 2) respectively i.e. GH = 1 < 0 or GH = 1 <  = 2n where n = 0, 1, 2, …

In the rectangular form, GH = 1 + j0. The condition of unity loop gain and
phase shift of zero (or an integral multiple of 2) is called the Barkhausen criterion. In
practice, a positive feedback amplifier with a loop gain of unity does not give rise to an
infinitely large gain. The upper limit of the increasing gain is limited by the cut-off and
saturation characteristics of the active device, but the gain rises to a level where no input
signal is required to provide an output signal. The transient signal generated from the
power supply when the signal generator (or oscillator) is switched ON is enough to
trigger the amplifier into spontaneous oscillation.

46
LC OSCILLATOR

LC oscillators employ transistors for amplification as these will work better at

higher frequencies than op amps. A general form of BJT oscillator and its equivalent
circuit are shown below.

Figure 4.2: (a) General form of BJT oscillator (b) Equivalent circuit of (4.2a).

Using KVL round the loop containing Z1, Z2 and Z3 yields.

Z1(I + hfeib) + Z3 I + Z2(I – ib) = 0 (4.8)

Z1I + Z1hfeib + Z3I + Z2I - Z2ib = 0

 (Z1 + Z2 + Z3)I + ib(Z1hfe – Z2) = 0 (4.9)

From the equivalent circuit of BJT oscillator shown in figure 4.2b, the parallel
combination of hie and Z2 is in series Z3. Using current divider rule

 Z2I 
ib    (4.10)
 hie  Z 2 

Equation (4.10) in equation (4.9) yields

 Z2I 
Z1  Z 2  Z 3 I    Z 1 h fe  Z 2   0
 hie  Z 2 

Let Zeq= Z1 + Z2 + Z3

47
 Z 1 Z 2 h fe I IZ 22
Z eq I    0
hie  Z 2 hie  Z 2

Multiply through by hie + Z2

ZeqI (hie + Z2) + Z1Z2hfeI - IZ22 = 0

ZeqhieI + ZeqZ2I + Z1Z2hfeI - IZ22 = 0

Divide through by Z2I

Z eq hie Z eq hie
 Z eq  Z1 h fe  Z 2   Z1  Z 2  Z 3  Z1 h fe  Z 2  0
Z2 Z2

 Z1 1  h fe   Z 3  0
Z eq hie Z eq hie
 Z 1  Z 3  Z 1 h fe  (4.12)
Z2 Z2

If all the Zs (i.e. impedances) are purely reactive and hie is real, then equation (4.12)
implies that

Z1 + Z2 + Z3 = 0 (4.13)

Z1(1 + hfe) + Z3 = 0 (4.14)

From equation (4.14)

Z3 = - Z1 (1 + hfe)
(4.15)

Equation (4.15) in equation (4.13) gives

Z1 + Z2 - Z1 (1 + hfe) = 0

Z1 h fe
 Z2  Z1 h fe   1 (4.16)
Z2
Since hfe is real, equations (4.15) and (4.16) show that Z1 and Z2 are the same sort of
reactance’s and opposite in sign to Z3 i.e. if Z1 and Z2 are inductors, Z3 must be a
capacitor and vice-versa.
Two of the best known LC oscillators are Hartley and Colpitts oscillators.

48
HARTLEY OSCILLATOR

Figure 4.3: Hartley oscillator

In the Hartley oscillator, both Z1 and Z2 are inductors while Z3 is a capacitor i.e
1 j
Z1 = jL1 , Z2  jL2 , and Z 3  
jwC wC
From equation (4.13)
Z1 + Z 2 + Z 3 = 0
 1 
 j  wL1  wL2    0
 wC 
At the resonant frequency,    o .

 o L1  L2    o2 L1  L2 C  1

1
(4.17)
o C
1
 o 
L1  L2 C
(4.18)
Since  = 2f
1
 fo  (4.19)
2 L1  L2 C

If there is a mutual inductance M between L1 and L2, equations (4.18) and (4.19) are
modified such that
1
o  (4.20)
L1  L2  2M C

49
 1
fo  (4.21)
2 L1  L2  2M C

COLPITTS OSCILLATOR

Figure 4.4: Colpitts oscillator

In the Colpitts oscillator, both Z1 and Z2 are capacitors while Z3 is an inductor i.e.
Z1  1 , Z2  1 , and Z 3  jL
jC1 jC 2
Note that the decoupling capacitors are labeled as Ca and Cb so that they will not be
confused with the capacitors in the tank circuit. In both figure (4.3) and figure (4.4),
variable capacitors are used in the tank circuits. This facilitates the variation of the
resonant frequency.
From equation 4.13
jL  j  1  L   0
1 1
   1
jC1 jC 2  C1 jC 2 
1 1 1 
 L    
  C1 C2 
At resonance,    o
 1 1  1 1 1 
 o2 L      o     (4.22)
 C1 C2  L  C1 C 2 
1 1 1 1 
 fo     (4.23)
2 L  C1 C 2 

50
Barkhausen criterion stipulates that the loop gain GH must have magnitude of unity and
phase shift of zero or an integral multiple of 2. From equation (4.16).
Z1 h fe Z1
GH   H  (4.24)
Z2 Z2
L1
In the Hartley oscillator, the feedback factor H  ,
L2
C1
While in the colpitts oscillators, H 
C2
From equation (4.24)
Z2
G  h fe  such that GH = 1
Z1

CRYSTAL OSCILLATOR
This crystal is a piece of quartz that has been accurately cut and finished to the
desired thickness; this thickness determines the oscillator frequency. The thinner the
crystal, the higher is the frequency of oscillation. When a potential difference is applied
across its two opposite faces, the crystal expands or contrasts. (If a mechanical force is
applied across the crystal, a voltage is produced. This interaction between pressure and
voltage is known as piezoelectric effect).

Figure 4.5: Piezoelectric crystal and its equivalent circuit.

If an alternating voltage is applied, the crystal is set into vibration. Greatest vibration
occurs at the resonant frequency of the crystal. The equivalent circuit of the crystal is
basically a series RLC circuit in parallel with a capacitor, Co. Because Co >> C 1 the
1
resonant frequency,  o  .
LC
The Q-factor is very large since woL >> R. Typical values for a 90kHz crystal
are L = 137H, C = 0.0235pF1 and R = 15k, corresponding to Q = 5, 165. These
extraordinarily high values of Q and the fact that the characteristics of quartz are
extremely stable with respect to time and temperature account for the exceptional
frequency stability of oscillator incorporating crystals. Crystal oscillators have
51
frequency range of about 10kHz to about 10MHz, and Q’s in the range from several
thousand to several hundred thousand.
The only disadvantage of crystal oscillator is that the resonant frequency cannot
be varied without changing the crystal oscillator.

5.0 OPERATIONAL AMPLIFIERS (OP AMPS)

Operational amplifiers (op amps) are special type of amplifier that are used to
perform mathematical operations such as addition, subtraction, division, multiplication,
integration and differentiation. Op amps were originally developed to work in analogue
computers but they are now widely used in amplification, instrumentation and control,
signal processing, and waveform generation.

Figure 5.1a Op am circuit symbol Figure 5.1b 741 pin configuration

An op am is basically a differential amplifier in which the output voltage is a

function of the difference in the voltage applied to the positive and negative input
terminals i.e. Vo = A Vin where Vin = (Vp – Vin), and
A = gain of the op am
An ideal op am has the following characteristics
i) Infinite voltage gain, Av = 
ii) Infinite bandwidth, BW = 
iii) Infinite input impedance, Zin = 
iv) Infinite common-mode rejection ratio, CMRR = .
v) Negligible output impedance, Zo = 0
vi) Characteristics do not drift with temperature.
vii) When used without feedback,
Vo = 0, if Vp = Vn.

A common mode signal is any unwanted signal (noise) that is applied to both
inputs. An ideal op am has infinite CMRR consequently op amps are able to amplify
signals in environments and systems that are electrically noisy.

52
When used with feedback, the ideal op amp obeys two golden rules.
1. Since an ideal op amp has infinite input impedance, the current into the op amp is
zero. i. e. I in  0
2. The output voltage is whatever makes the input voltages equal. The reason for
Vo
this is that since AV  , Vo is finite, A is infinite, then Vin must be zero.
Vin
Since Vin  V p  Vn , then Vin = 0 iff V p  Vn .
The golden rules make the analysis of the basis op amp circuits very easy and straight
forward.

SOME BASIC OP AMP CIRCUITS

THE INVERTING AMPLIFIER

Figure 5.2 An inverting amplifier, using an ideal op amp and negative feedback.

The circuit above shows an ideal op amp with a feedback resistance between the
output terminal and the inverting input terminal (-), while the non-inverting input (+) is
connected directly to the ground.
Applying KCL at node A,
I IN  I 1  I 2 (5.1)
By the first golden rule, I in  0
Node A is often called the summing point because the algebraic sum of all the currents
in the circuit is found there.
By the second golden rule,
V p  Vn = 0 (5.2)
Note that the ground is assumed to be at zero potential. Equation (5.2) is the reason why
node A is also known as a virtual ground.
By KVL and ohm’s law, the current through R2 is

53
 Vo  V n Vo
I2   (5.3)
R2 R2

The current through R1 is

V s  Vn Vs
I1   (5.4)
R1 R1
Substituting equation (5.3) and (5.4) into equation (5.1)
V0 Vs Vo  Vs
  0  
R2 R1 R2 R1
Vo  R2
 AV   (5.5)
Vs R1
The negative sign in equation (5.5) implies that there is a phase difference of 180o
between the output signal and the input signal, hence the name inverting amplifier.

THE NON-INVERTING AMPLIFIER

Figure 5.3: A non-inverting amplifier

In the non-inverting amplifier, the input signal voltage is applied to the non-
inverting input terminal (+), though the negative feedback is still connected to the
inverting terminal.
Applying KCL at node A,
I1 = I2 + Iin (5.6)
By the first golden rule, I in  0 I1  I 2 (5.7)
Equation (5.7) shows that R1 and R2 are in series using voltage divider rule, input
voltage to the inverting terminal is given by
R1Vo
Vn  (5.8)
R1  R2
Input voltage to the non-inverting terminal is Vs i.e. V p  Vs . By the second golden rule,
V p  Vn

54
 R1Vo
 Vs 
R1  R2
Vo R1  R2 R2
 AV    1 (5.9)
Vs R1 R1

THE BUFFER

A buffer is another name for interface circuit. It allows signals to pass from one circuit
to another when these circuits are incompatible without the buffer. Buffer amplifiers are
used to match (interface) high impedance signal sources to low, possibly varying load
impedance.
Input voltage to the non-inverting terminal, V p  Vs . The output voltage is fed
back directly to the inverting terminal thus Vn  Vo .
By the second golden rule, V p  Vn  Vo  Vs 
Vo
 AV   1 (5.10)
Vs
Note the similarity between this circuit and the emitter follower circuit.

THE SUMMING AMPLIFIER

The summing amplifier is exactly the same as the inverting amplifier except that
it has multiple simultaneous inputs.

Figure 5.5: A summing amplifier

55
Applying KCL at the summing node A.
Iin = I11 + I12 + I13 + I2 (5.11)
By the first golden rule, Iin = 0
 I2 = I11 + I12 + I13 (5.12)
Applying KVL and ohm’s law
 V  Vn   V  Vn   V2  Vn   V3  Vn 
  o    1        (5.13)
 R2   R11   R12   R13 
By the second golden rule, Vp = Vn  Vn = 0
Vo V1 V2 V3
    (5.14)
R2 R11 R12 R13
RV RV RV 
 Vo    2 1  2 2  2 3  (5.15)
 R11 R12 R13 
If R11 = R12 = R13 = R2
Vo = -(V1 + V2 + V3) (5.16)
Equation (5.15) shows that a number of voltages can be multiplied by arbitrary constants
and then added together. The arbitrary constants can be varied by varying the input
resistances.
Note that the same circuit can be used for subtraction. To subtract signal A from
signal B, signal A is passed through a unity gain inverting amplifier before both of them
are added. The negative sign in equations (5.13), (5.14), (5.15) and (5.16) indicates that
the circuit is an inverter. If a positive sign is desired, the output is passed through a unity
gain inverting amplifier.

THE DIFFERENCE AMPLIFIER

Figure 5.6: Difference amplifier

56
Applying KCL at the summing node A,
Iin1 = I1 + I2 = 0 (by the first golden rule)
 I1 = -I2 (5.17)
Applying KCL at the summing node B
I3 = I4 + Iin2 (By the first golden rule, Iin2 = 0)
 I3 = I 4 (5.18)
Equation (5.18) shows that R3 and R4 are in series. Using voltage divider rule, the
voltage at the non-inverting terminal is
 R4 
Vp   V2 (5.19)
 R3  R4 
Using superposition theorem, the voltage at the inverting terminal is given by
 R2   R1 
Vn    V1    Vo (5.20)
 R1  R2   R1  R2 
By the second golden rule, Vp = Vn
 R4   R2   R1 
   V2    V1    Vo
 R3  R4   R1  R2   R1  R2 
Let R1 = R3 = Ra, and R2 = R4 = Rb
 Rb   Rb   Ra 
   V2    V1    Vo (5.21)
 Ra  Rb   Ra  Rb   Ra  Rb 
Multiply both sides of equation (5.21) by (Ra + Rb)
RbV2 = RbV1 + RaVb
 RaVo = Rb(V2 – V1)
Rb
 Vo  V2  V1  (5.22)
Ra

The output voltage is proportional to the difference voltage. The ratio Rb R is the gain
a

of the difference amplifier.

If R1 = R2 = R3 = R4  Ra = Rb.
Vo = V 2 - V1 (5.23)

57
THE INTEGRATOR

E sw

I2
R Iin1
VS -
A
Vo
+

Figure 5.7: Integrator

Applying KCL at the summing node A,

Iin = I1 + I2 = 0  I1 = -I2
By KVL and ohm’s law
V s  Vn
 C
dV
Vo  Vn 
R dt
By the second golden rule Vp = Vn = 0
Vs dVo
  C
R dt
1
RC 
 Vo  Vs dt (5.24)

The output voltage is proportional to the integral of the input voltage. When a
function is integrated there is usually a constant of integration involved. This constant
determines the initial condition of the integrator. The capacitor is usually connected in
parallel with a FET that acts as switch which is closed when the capacitor is to be
discharged and opened when the capacitor is to be charged i.e. during integration. Initial
voltages can be applied to the capacitor by connecting a battery E in series with the
switch such that

1
RC 
Vo  Vs dt  E (5.25)

58
THE DIFFERENTIATOR

Applying KCL at the summing node A

Iin = I1 + I2  I1 = -I2 since Iin = 0
By KVL and ohm’s law
Cd Vs  Vn   Vo  Vn 

dt R
By the second golden rule, Vn = 0 since Vp = 0
CdVs Vo dVs
    Vo   RC (5.26)
dt R dt
The output voltage is proportional to the derivative of the input voltage.

EXAMPLE 8
Use op-amp summers and integrator to solve the differential equation
d 2Vo dVo Vo
 3   Vinm cos wt
dt 2 dt 4
Assume that all initial conditions are zero

SOLUTION
d 2V dVo Vo
 Vinm cos wt  3 
dt 2 dt 4
dVo
Solving for the first derivative by integrating
dt
dVo d 2V  dV V 
  2 o  dt   Vinm cos wt  3 o  o dt
dt dt  dt 4

59
 Recall that
1
RC 
Vo  Vs dt

Using op-amp integrator, the expression above is realized as

The output voltage Vo is realized as shown below

Both diagrams above are combined to give the complete circuit diagram.

60