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21EC023 SV Project File

The document describes a testbench for verifying an adder module using SystemVerilog. It includes modules for the adder design, interface, transactions, configuration, generator, monitor, scoreboard, driver, agent, environment, and test. The testbench uses these modules and classes to generate test cases, drive the inputs, monitor the outputs, and check for errors.

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21ec023
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10 views10 pages

21EC023 SV Project File

The document describes a testbench for verifying an adder module using SystemVerilog. It includes modules for the adder design, interface, transactions, configuration, generator, monitor, scoreboard, driver, agent, environment, and test. The testbench uses these modules and classes to generate test cases, drive the inputs, monitor the outputs, and check for errors.

Uploaded by

21ec023
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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A

Project File
For
EC322 System Verilog Programming
Prepared by
Pruthviraj Mohite (21EC023)

Semester – 6, Branch – B.Tech. (EC)


Academic Year 2023-24

Under the supervision of


Dr. Dharmendra V. Chauhan

Submitted to

Charotar University of Science & Technology


for Partial Fulfillment of the Requirements of the
Degree of Bachelor of Technology in Electronics & Communication

Submitted at
DEPARTMENT OF ELECTRONICS & COMMUNICATION
Faculty of Technology & Engineering, CHARUSAT

Chandubhai S. Patel Institute of Technology


At: Changa, Dist: Anand – 388421
April 2024
Top.sv
`include "adder_design.sv";
`include "interface.sv"
`include "transaction.sv";
`include "configuration.sv";
`include "generator.sv";
`include "monitor.sv";
`include "scoreboard.sv";
`include "driver.sv";
`include "agent.sv";
`include "environment.sv";
`include "test.sv";

module tb_top;

bit clk, reset;

adder_if sif (clk, reset);


test t1 = new(sif);

adder dut (.a(sif.a),


.b(sif.b),
.c(sif.c),
.valid(sif.valid),
.clk(sif.clk),
.reset(sif.reset)
);
initial begin
clk = 0;
reset = 0;
end

always begin
#5ns clk = ~clk;
end
initial begin
t1.run();
#150ns $finish;
end
endmodule

adder_desing.sv
module adder(
input clk ,
input reset,
input [3:0] a ,
input [3:0] b ,
input valid,
output [4:0] c );

reg [6:0] tmp_c;

//Reset
always @(posedge reset)
tmp_c <= 0;

// Waddition operation
always @(posedge clk)
if (valid) tmp_c <= a + b;

assign c = tmp_c;
endmodule
interface.sv
interface adder_if(input clk, reset);

logic [3:0] a, b;
logic [4:0] c;
logic valid;
endinterface

transaction.sv
class packet;
bit[3:0] a = 4'b0101;
bit[3:0] b = 4'b1000;
bit[4:0] c;

function void print();


$display("a= %0d, b= %0d, c= %0d",a,b,c);
endfunction

endclass

configuration.sv
class configuration;
static int pkt_num = 5;
endclass

generator.sv
class generator;

configuration cfg;
packet pkt;
mailbox mgen;
function new(mailbox GEN2DRV);
mgen = GEN2DRV;
endfunction

task run();
repeat(cfg.pkt_num) begin
pkt = new();
pkt.randomize();
mgen.put(pkt);
$display("pkt from generator");
pkt.print();
end
endtask
endclass

monitor.sv
class monitor;
mailbox mmon;
packet pkt;
configuration cfg;
virtual adder_if vif;
function new (mailbox MON2SCB, virtual adder_if VIF);

mmon = MON2SCB;
vif = VIF;
endfunction

task run();
//for(int i=0; i<cfg.pkt_num; i++) begin
repeat(cfg.pkt_num) begin
pkt = new();
@(posedge vif.clk);
if(vif.valid) begin
pkt.a = vif.a;
pkt.b = vif.b;
@(posedge vif.clk);
pkt.c = vif.c;
@(posedge vif.clk);
mmon.put(pkt);
$display("pkt from monitor");
pkt.print();
end
//else
// i--;
end
endtask
endclass

scoreboard.sv
class scoreboard;
mailbox mscb;
packet pkt;
configuration cfg;
function new (mailbox MON2SCB);
mscb = MON2SCB;
endfunction

task run();
repeat(cfg.pkt_num) begin
//pkt = new();
mscb.get(pkt);
if(pkt.a + pkt.b == pkt.c) begin
$display("-----------PASS-------");
end
else begin
$error("Packet failed ");
$display("Failed pkt from scoreboard");
pkt.print();
end
end
endtask
endclass

driver.sv
class driver;
packet pkt;
mailbox mdrv;
configuration cfg;
virtual adder_if vif;

function new(mailbox GEN2DRV, virtual adder_if VIF);


mdrv = GEN2DRV;
vif = VIF;
endfunction

task run();
repeat(cfg.pkt_num) begin
mdrv.get(pkt);
@(negedge vif.clk);
vif.a = pkt.a;
vif.b = pkt.b;
vif.valid = 1;
@(negedge vif.clk);
vif.valid = 0;
@(posedge vif.clk);
@(posedge vif.clk);
$display("pkt is driven on interface from driver");
pkt.print();
end
endtask
endclass

agent.sv
class agent;

mailbox gen2drv;
mailbox mon2scb;
generator gen;
monitor mon;
scoreboard scb;
driver drv;

function new(virtual adder_if vif);


gen2drv =new();
mon2scb =new();
gen = new(gen2drv);
drv = new(gen2drv,vif);
mon = new(mon2scb,vif);
scb = new(mon2scb);
endfunction

task run();
fork
begin
gen.run();
end
begin
drv.run();
end
begin
mon.run();
end
begin
scb.run();
end
join
endtask
endclass

environment.sv
class environment;
agent agt;
function new(virtual adder_if vif);
agt = new(vif);
endfunction
task run();
agt.run();
endtask
endclass

test.sv
class test;
environment env;

function new(virtual adder_if vif);


env = new(vif);
endfunction

task run();
env.run();
endtask
endclass
Output:

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