Birla Institute of Technology and Science-Pilani, Hyderabad Campus

II Semester 2016-2017 3. (a) Consider the interrupts for Intel 8086 listed below. Rank them in the
CS/ECE/EEE/INSTR F241 order of priority with 1 representing the highest priority and 4 representing
Microprocessor Programming and Interfacing
the lowest priority. (2)
Comprehensive Examination - Part B (Closed Book)
Time: 120 min. Date: 03-05-2017 MM: 50 NMI, INTR, SINGLE STEP, DIVIDE ERROR
(Note:Answer all the parts of questions TOGETHER, else answers will NOT be (b) When an interrupt occurs, the following actions are performed by Intel
evaluated). 8086 in response. Identify the correct sequence of actions by numbering
1. (a) Write a single instruction to replace each of the following, where DAT1 them from 1 to 6 with 1 representing the first and 6 representing the last
action. (3)
is a label for memory location (3)
(i) DEC AX FETCH ISR ADDRESS, PUSH CS, PUSH IP, CLEAR IF, CLEAR TF,
(ii) LEA AX, DAT1 PUSH FLAGS
(iii) NOT AX
(c) Consider the occurrence of Type 2 interrupt NMI. In the Figure below,
(b) Write a single logical instruction for each of the following operations. the waveform shown is connected directly to the NMI pin of Intel 8086. At
(i) Clear the even-numbered bits in AX (4) which point 1 or 2 is the occurrence of the NMI interrupt recognized by
(ii) Change the sign of the contents of AX Intel 8086? (1)
(iii) Multiply the contents of AX by 16
(iv) Test whether bit number 5 in AX is zero
2. (a) The following program fills ---------- blocks of memory in the ---------
2 1
segment beginning at address block with the data byte ---------------------
(ASCII Space),where BLOCK is a label for memory location (3) t
MOV AL, 20H
(d) List the address words from which the CS and IP values are taken
LEA DI, BLOCK from the interrupt vector table for Type 2 Interrupt? (2)
MOV CX, 03E7H
REP STOSB 4. Consider the instruction sequence below to set the carry flag in Intel 8086.
(b) Change the sequence of instructions given below to get the biggest of (a) Fill in the appropriate value in Line 3. (1)
the NUMS in DL register (7)
1 PUSHF
NUMS DB 56H, 38H, 09H, 98H, 99H, 0C7H, 07H, 0BCH, 0CH, 0ECH 2 MOV BP, SP
3 OR WORDPTR [BP+0],_____H
1 AGAIN: MOV DL, AL
2 DEC CL
(b) When the carry flag is to be reset, in Q.4(a) line 3 needs to be changed.
3 INC BX
Replace the OR instruction in Q.4(a) line 3 with an AND instruction
4 JNZ REPEA
and an appropriate value to reset the overflow flag. (2)
5 LEA BX, NUMS
6 MOV AL, 0 FLAG REGISTER:
7 MOV CL, 0AH
X X X X OF DF IF TF SF ZF X AF X PF X CF
8 REPEA: CMP AL, [BX]
9 JAE AGAIN
10 MOV AL, [BX]
5. Consider a piece of assembly language program for Intel 8086 to divide a (iii) Write instructions to rotate the motor in Forward direction.
16-bit unsigned number by an 8-bit unsigned number shown below. (1)
(a) Identify the Type number of interrupt that is generated?
MOV AX, 1000H
MOV BL, 02H
DIV BL
(b) Considering the “divide error” generated in Q.5(a). Fill in the blanks
with appropriate values to initialize the interrupt vector table for ISR.
(2)
MOV SI, ____H
MOV AX, 3000H
MOV [SI], AX
MOV SI, ____H
MOV AX, 0000H
MOV [SI], AX
(c) Consider the ISR to be written at 3000H to correctly respond to the
“divide error”. Fill in the first 3 lines of the ISR with appropriate
instructions to obtain the correct result of the division operation in (b) Write the control word and the count to be loaded to generate a 20 KHz
Q.5(a) without “divide error”. (3) square-wave at OUT0 and a 400 KHz continuous pulse at OUT2 of 8254.
_________ Consider a clock of 10 MHz at clk0 and clk2. Address pins A0 and A1 of
_________ 8254 are directly connected to A0 and A1 of 8086 and A15 of 8086 is
_________ connected to 𝐶𝑆(active low) of 8254 through an inverter. Assume that
IRET remaining address lines of 8086 are at logic 0. What is the address of the
CONTROL REGISTER of 8254. (5)
6. (a) Below Figure shows the interfacing of 8255 with 8086 processor to
drive DC motor. The switches SW1 and SW0 control the status of the (c) 8086 is to be interfaced with a memory of size 256 Kbytes of RAM starting
motor according to the Table given below. Assume A19-A8 and A2 at at address 40000H, using 32K RAM chips. Assume all the required RAMs
have continuous addresses and are numbered from RAM 1 to RAM n. (3)
Logic ‘0’ (2+2+4)
(i) Calculate the addresses of Port A and CONTROL REGISTER. (i) How many RAM chips are required for interfacing.
(ii) What is the starting address of the last RAM chip used.
(ii) What is the control word for the configuration shown in the Figure.
Assume that Port C is working as output port. (iii) Which RAM chip entry has the address 5D03FH.

SW1 SW0 Motor Status

0 0 No Rotation
0 1 Forward Direction
1 0 Reverse Direction