Microprocessors

and Interfacing
8086, 8051, 8096, and advanced processors

N. Senthil Kumar
Professor

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Department of Electrical and Electronics Engineering

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Mepco Schlenk Engineering College
Sivakasi, Tamil Nadu

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M. Saravanan
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Professor
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Department of Electrical and Electronics Engineering
Thiagarajar College of Engineering
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Madurai, Tamil Nadu

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S. Jeevananthan
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Professor
Department of Electrical and Electronics Engineering
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Pondicherry Engineering College

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Puducherry
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S.K. Shah
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Professor and Head

Department of Electrical Engineering
MS University of Baroda
Vadodara, Gujarat


© Oxford University Press. All rights reserved.
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© Oxford University Press 2012

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First published in 2012

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and you must impose this same condition on any acquirer.
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ISBN-13: 978-0-19-807906-4
ISBN-10: 0-19-807906-0
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Typeset in Times New Roman

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by Trinity Designers & Typesetters, Chennai

Printed in India by Tara Art Printers (P) Ltd, Noida
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© Oxford University Press. All rights reserved.

 Brief Contents xi

Brief Contents
Features of the Book iv
Preface vii
1. Microprocessors—Evolution and Introduction to 8085 1
2. Methods of Data Transfer and Serial Transfer Protocols 47

PART I: INTEL 8086—16-BIT MICROPROCESSORS

3. Intel 8086 Microprocessor Architecture, Features, and Signals 63
4. Addressing Modes, Instruction Set, and Programming of 8086 80

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5. 8086 Interrupts 175

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6. Memory and I/O Interfacing 210
7. Features and Interfacing of Programmable Devices for
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8086-based Systems 240
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9. 8086-based Systems 372

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PART II: INTEL 8051—8-BIT MICROCONTROLLERS

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10. Introduction to 8051 Microcontrollers 391

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11. 8051 Instruction Set and Programming 402

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12. Hardware Features of 8051 427

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13. 8051 Interface Examples 464

PART III: INTEL 8096—16-BIT MICROCONTROLLERS

14. Overview of Intel 8096 Microcontrollers 517
15. 8096 Instruction Set and Programming 530
16. Hardware Features of 8096 549

PART IV: ADVANCED TRENDS

17. Microprocessor System Developments and Recent Trends 591
18. Advanced Microprocessors and Microcontrollers 604
19. Embedded Systems 663
20. Hybrid Programming Techniques Using ASM and C/C++ 736

© Oxford University Press. All rights reserved.

xii Brief Contents
Appendix A: 8086 Case Studies 752
Appendix B: 8051 Case Studies 758
Appendix C: 8275 CRT Controller Chip 766
Appendix D: Multiple Choice Questions 777
Appendix E: 8086 Instruction Set 797
Appendix F: 8051 Instruction Set 803
Bibliography 811
Index 812

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© Oxford University Press. All rights reserved.

 Detailed Contents xiii

Detailed Contents
Features of the Book iv
Preface vii
Brief Contents xi
1. Microprocessors—Evolution and Introduction to 8085 1
1.1 Introduction 1
1.2 Explanation of Basic Terms 2
1.3 Microprocessors and Microcontrollers 5
1.4 Microprocessor-based System 6
1.5 Origin of Microprocessors 7
1.5.1 First generation (1971–1973) 8

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1.5.2 Second generation (1974–1978) 8

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1.5.3 Third generation (1978–1980) 8
1.5.4 Fourth generation (1981–1995) 8

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1.5.5 Fifth generation (1995–till date)
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1.5.6 Timeline of microprocessor evolution 9
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1.7 Types of Memory 11
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1.8 Input and Output Devices 13

1.9 Technology Improvements Adapted to Microprocessors and
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Computers 14
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1.10 Introduction to 8085 Processor 14

1.11 Architecture of 8085 16
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1.11.1 Arithmetic and logic unit 16

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1.11.2 General-purpose registers 17

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1.11.3 Special-purpose registers 17

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1.11.4 Instruction register and decoder 19

1.11.5 Timing and control unit 19
1.12 Microprocessor Instructions 23
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1.13.1 Based on functionality 24
1.13.2 Based on length 26
1.13.3 Addressing modes in instructions 28
1.14 Instruction Set of 8085 30
1.14.1 Format of assembly language instructions and programs 31
1.14.2 Data transfer instructions 31
1.14.3 Arithmetic instructions 34
1.14.4 Logical instructions 36
1.14.5 Branching instructions 38
1.14.6 Machine control instructions 39
1.15 Sample Programs 40
1.16 Instruction Execution 42

© Oxford University Press. All rights reserved.

xiv Detailed Contents
2. Methods of Data Transfer and Serial Transfer Protocols 47
2.1 Data Transfer Mechanisms 47
2.2 Memory-mapped and I/O-mapped Data Transfer 47
2.3 Programmed Data Transfer 48
2.4 Direct Memory Access 49
2.5 Parallel Data Transfer 50
2.6 Serial Data Transfer 50
2.6.1 Introduction to RS-232 standard 51
2.6.2 Introduction to RS-485 standard 54
2.6.3 GPIB/IEEE 488 standards 55
2.7 Interrupt Structure of a Microprocessor 57
2.8 Types of Interrupts 57
2.8.1 Vectored and non-vectored interrupts 57
2.8.2 Maskable and non-maskable interrupts 58
2.8.3 Software and hardware interrupts 58
2.9 Interrupt Handling Procedure 58

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PART I: INTEL 8086—16-BIT MICROPROCESSORS

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3. Intel 8086 Microprocessor Architecture, Features, and Signals
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3.1 Introduction 63
3.2 Architecture of 8086 63
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3.2.1 Execution unit 63

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3.2.2 Bus interface unit 66

3.2.3 Minimum and maximum mode operations 67
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3.3 Accessing Memory Locations 67

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3.4 Pin Details of 8086 70

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3.4.1 Function of pins common to minimum and maximum modes 70

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3.4.2 Function of pins used in minimum mode 72

3.4.3 Function of pins used in maximum mode 73
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3.5 Differences Between 8086 and 8088 74

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4. Addressing Modes, Instruction Set, and Programming

of 8086 80
4.1 Addressing Modes in 8086 80
4.1.1 Register Addressing Mode 80
4.1.2 Immediate Addressing Mode 80
4.1.3 Data Memory Addressing Modes 81
4.1.4 Program Memory Addressing Modes 83
4.1.5 Stack Memory Addressing Mode 85
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4.3 Instruction Format of 8086 87
4.3.1 One-byte instruction 87
4.3.2 Register to register 87
4.3.3 Register to/from memory with no displacement 87
4.3.4 Register to/from memory with displacement 89
4.3.5 Immediate operand to register 89
4.3.6 Immediate operand to memory with 16-bit displacement 89

© Oxford University Press. All rights reserved.

 Detailed Contents xv
4.4 Instruction Set of 8086 91
4.4.1 Data transfer instructions 91
4.4.2 Arithmetic instructions 94
4.4.3 Logical instructions 102
4.4.4 Flag manipulation instructions 103
4.4.5 Control transfer instructions 103
4.4.6 Shift/rotate instructions 106
4.4.7 String instructions 109
4.4.8 Machine or processor control instructions 110
4.5 8086 Assembly Language Programming 110
4.5.1 Writing programs using line assembler 111
4.5.2 Writing time delay programs 127
4.5.3 8086 Assembler directives 129
4.5.4 Writing assembly language programs using MASM 138
4.6 Program Development Process 162
4.7 Modular Programming 164

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4.7.1 CALL instruction 165

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4.7.2 RET instruction 166

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4.7.3 Macro 167
4.7.4 Illustrative example it y 168
5. 8086 Interrupts 175
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5.1 Introduction 175
5.2 Interrupt Types in 8086 175
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5.3 Processing of Interrupts by 8086 176

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5.4 Dedicated Interrupt Types in 8086 178

5.4.1 Type 00H or divide-by-zero interrupt 178
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5.4.2 Type 01H, single step, or trap interrupt 178

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5.4.3 Type 02H or NMI interrupt 178

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5.4.4 Type 03H or one-byte INT interrupt 179

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5.5 Software Interrupts—Types 00H–FFH 179

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5.6 INTR Interrupts—Types 00H–FFH 180

5.7 Priority Among 8086 Interrupts 182
5.8 Interrupt Service Routines 182
5.9 BIOS Interrupts or Function Calls 189
5.9.1 INT 10H 189
5.9.2 INT 11H 191
5.9.3 INT 12H 192
5.9.4 INT 13H 192
5.9.5 INT 14H 192
5.9.6 INT 15H 192
5.9.7 INT 16H 192
5.9.8 INT 17H 192
5.10 Interrupt Handlers 194
5.11 DOS Services: INT 21H 195
5.12 System Calls—BIOS Services 198
5.12.1 Print screen service: INT 05H 199

© Oxford University Press. All rights reserved.

xvi Detailed Contents
5.12.2 Video services: INT 10H 200
5.12.3 Keyboard services: INT 16H 202
5.12.4 Printer services: INT 17H 204
6. Memory and I/O Interfacing 210
6.1 Physical Memory Organization in 8086 210
6.2 Formation of System Bus 211
6.3 Interfacing RAM and EPROM Chips using Only Logic Gates 213
6.4 Interfacing RAM/EPROM Chips using Decoder IC and
Logic Gates 217
6.5 I/O Interfacing 220
6.5.1 I/O instructions in 8086 220
6.5.2 I/O-mapped and memory-mapped I/O 220
6.6 Interfacing 8-bit Input Device with 8086 222
6.6.1 Assigning 8-bit address to 8-bit input device using
address decoder having only logic gates 222

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6.6.2 Assigning 8-bit address to 8-bit input device using

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address decoder IC 74LS138 222
6.6.3 Assigning 16-bit address to 8-bit DIP switch using

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address decoder having only logic gates 224
6.7 Interfacing 8-bit Output Device with 8086 224
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6.8 Interfacing Printer with 8086 225
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6.9 Interfacing 8-bit and 16-bit I/O Devices or Ports with 8086 229
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6.10 Interfacing CRT Terminal with 8086 233

7. Features and Interfacing of Programmable Devices for
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8086-based Systems 240

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7.1 Intel 8255 Programmable Peripheral Interface 240

7.1.1 Features of 8255 241
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7.1.2 Block diagram of Intel 8255 241

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7.1.3 Operating modes and control words of 8255 242

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7.1.4 Programming examples 248

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7.2 Interfacing Switches and LEDS 249

7.2.1 Debouncing of keys 253
7.3 Interfacing Seven-segment Displays 254
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7.5 Interfacing Analog-to-digital Converters 259
7.5.1 ADC chips and interfacing to microprocessor 260
7.6 Interfacing Digital-to-analog Converters 263
7.6.1 Square wave generation 264
7.6.2 Staircase waveform generation 265
7.6.3 Ramp waveform generation 266
7.6.4 Waveform generation using stored data 267
7.7 Interfacing Stepper Motors 268
7.8 Interfacing Intelligent LCDs 273
7.9 Keyboard and Display Interface IC 8279 278
7.9.1 Matrix keyboard 278
7.9.2 Multiplexed display 283
7.9.3 Features, block diagram, and pin details of 8279 285

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 Detailed Contents xvii
7.9.4 Programming of 8279 287
7.9.5 Display interface using 8279 292
7.9.6 Keyboard interface using 8279 293
7.10 Intel Timer IC 8253 295
7.10.1 Features of IC 8253 295
7.10.2 Block diagram of IC 8253 and pin details 295
7.10.3 Operating modes and control word of IC 8253 297
7.10.4 Interfacing of IC 8253 with 8086 302
7.10.5 Application examples 302
7.11 Introduction to Serial Communication 307
7.11.1 Features and details of 8251 USART 309
7.11.2 Control words 312
7.11.3 Interfacing 8251 with 8086 314
7.12 8259 Programmable Interrupt Controller 317
7.12.1 Features and architecture of 8259 318
7.12.2 Pin diagram and details of 8259 320

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7.12.3 Initialization of 8259 320

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7.12.4 Operation of 8259 324

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7.12.5 Interfacing of 8259 to 8086 325
7.13 8237 DMA Controller it y 326
7.13.1 Features, pin details, and architecture of 8237 327
7.13.2 DMA initialization and operation 333
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7.13.3 Operation of 8237 with 8086 335
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8. Multiprocessor ConÀguration 343

8.1 Introduction 343
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8.2 Multiprocessor System—Need and Advantages 344

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8.4 Bus Arbitration in Loosely-coupled Multiprocessor System 346
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8.4.1 Daisy chaining 347

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8.4.2 Polling 347

8.4.3 Independent requesting 348
8.5 Interconnection Topologies in a Multiprocessor System 349
8.5.1 Shared bus architecture 349
8.5.2 Multi-port memory 349
8.5.3 Linked input/output 350
8.5.4 Crossbar switching 350
8.6 Physical Interconnections Between Processors in a
Multiprocessor System 351
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8.6.4 Regular topology 352
8.6.5 Irregular topology 352
8.7 Operating System used in a Multiprocessor System 353
8.8 Typical Multiprocessor System having 8086 and 8087 353
8.8.1 Architecture of 8087 354

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xviii Detailed Contents
8.8.2 Pin details of 8087 354
8.8.3 Interconnection of 8087 with 8086 356
8.8.4 Data types of 8087 358
8.9 Typical Multiprocessor System having 8086 and 8089 359
8.9.1 Pin details of 8089 360
8.9.2 Local and remote operation of 8089 362
8.9.3 8089 architecture 364
8.9.4 Communication between CPU (8086) and IOP (8089) 367
9. 8086-based Systems 372
9.1 Introduction 372
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9.2.1 Formation of separate address bus and data bus in 8086 372
9.2.2 Formation of buffered address bus and data bus in 8086 374
9.2.3 Connection of 8284A with 8086 375
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9.4 8086 System Bus Timings 378

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9.4.1 Timing diagrams for general bus operation in minimum mode 378
9.4.2 Timing diagrams for general bus operation in maximum mode 382

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9.4.3 Interrupt acknowledgement (INTA) timing 383
9.4.4 Bus request and bus grant timing 384
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9.5 Design of Minimum Mode 8086-based System 385
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PART II: INTEL 8051—8-BIT MICROCONTROLLERS

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10. Introduction to 8051 Microcontrollers 391

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10.1 Introduction 391

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10.2 Intel’s MCS-51 Series Microcontrollers 392

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10.3 Intel 8051 Architecture 392

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10.4 Memory Organization 394

10.5 Internal RAM Structure 395
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10.5.1 Special function registers 397

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10.5.2 Processor status word 397

10.6 Power Control in 8051 399
10.6.1 Idle mode 399
10.6.2 Power down mode 400
10.7 Stack Operation 400
11. 8051 Instruction Set and Programming 402
11.1 Introduction 402
11.2 Addressing Modes of 8051 402
11.2.1 Immediate addressing 402
11.2.2 Register direct addressing 402
11.2.3 Memory direct addressing 403
11.2.4 Memory indirect addressing 403
11.2.5 Indexed addressing 403
11.3 Instruction Set of 8051 404
11.3.1 Data transfer instructions 404
11.3.2 Arithmetic instructions 405

© Oxford University Press. All rights reserved.

 Detailed Contents xix
11.3.3 Logical instructions 406
11.3.4 Branching instructions 407
11.3.5 Bit manipulation instructions 408
11.4 Some Assembler Directives 410
11.5 Programming Examples using 8051 Instruction Set 410
12. Hardware Features of 8051 427
12.1 Introduction 427
12.2 Parallel Ports in 8051 427
12.2.1 Structure of port 1 428
12.2.2 Structure of ports 0 and 2 429
12.2.3 Structure of port 3 430
12.3 External Memory Interfacing in 8051 432
12.3.1 Program memory interfacing 432
12.3.2 Data memory interfacing 434
12.3.3 Timing diagram for external program and data memory access 435

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12.4 8051 Timers 437

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12.4.1 Timer SFRs 437
12.4.2 Timer operating modes 439

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12.4.3 Timer control and operation 442
12.4.4 Using timers as counters 443
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12.4.5 Programming examples 443
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12.5 8051 Interrupts 445
12.5.1 Interrupt sources and interrupt vector addresses 445
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12.5.2 Enabling and disabling of interrupts 446

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12.5.3 Interrupt priorities and polling sequence 447

12.5.4 Timing of interrupts 448
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12.5.5 Programming examples 450

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12.6 8051 Serial Ports 453

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12.6.1 Serial port control SFRs 453

12.6.2 Operating modes 455
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12.6.3 Programming the serial port 457

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13. 8051 Interface Examples 464

13.1 Interfacing 8255 with 8051 464
13.2 Interfacing of Push Button Switches and LEDs 465
13.3 Interfacing of Seven-segment Displays 467
13.4 Interfacing ADC chip 469
13.5 Interfacing DAC chip 471
13.5.1 Square wave generation 472
13.5.2 Staircase wave generation 472
13.5.3 Ramp wave generation 473
13.5.4 Sine wave generation 474
13.6 Interfacing Matrix Keypad 475
13.7 Interfacing Stepper Motor with 8051 478
13.8 Interfacing LCD with 8051 482
13.9 Interfacing DC Motors/Servomotors 487
13.9.1 Bidirectional DC motor control 488
13.10 Microcontroller Application Example—Stopwatch 489

© Oxford University Press. All rights reserved.

xx Detailed Contents
0LFURFRQWUROOHU$SSOLFDWLRQ([DPSOH²7UDI¿F/LJKW&RQWURO 
13.12 Microcontroller Application Example—Thermometer 495
13.13 RTC Interfacing using I2C Standard 498
13.13.1 Details of I2C bus 499
13.13.2 8051 Subroutines used to implement I2C bus 503
13.13.3 DS1307—Serial I2C real-time clock IC 505

PART III: INTEL 8096—16-BIT MICROCONTROLLERS

14. Overview of Intel 8096 Microcontrollers 517

14.1 Introduction 517
14.2 Features of Intel 8096 Microcontroller 519
14.3 Functional Block Diagram 519
14.3.1 CPU section 519
14.3.2 8096 CPU buses 521
14.3.3 Register arithmetic and logical unit 521

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14.3.4 Temporary register 521

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14.3.6 Program status word 523
14.3.7 Memory controller it y 523
14.3.8 Internal timing 523
14.3.9 I/O section 524
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14.4 Memory Structure 525

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14.5 Power Down Mode of CPU 528

15. 8096 Instruction Set and Programming 530
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15.1 8096 Operand Types 530

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15.2 Addressing Modes 531

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15.2.1 Register direct addressing 531

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15.2.2 Indirect addressing 531

15.2.3 Indirect addressing with auto increment 532
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15.2.4 Immediate addressing 532

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15.2.5 Short-indexed addressing 532

15.2.6 Long-indexed addressing 532
15.2.7 Zero register addressing 532
15.2.8 Stack pointer register addressing 533
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15.3.1 Data transfer instructions 533
15.3.2 Arithmetic and logical instructions 533
15.3.3 Shift/rotate instructions 534
15.3.4 Branching instructions 535
15.4 Complete 8096 Instruction Set 536
15.5 Programming Examples using 8096 Instruction Set 540
16. Hardware Features of 8096 549
16.1 Parallel Ports in 8096 and Their Structure 549
16.1.1 Port 0 549
16.1.2 Port 1 550
16.1.3 Port 2 550

© Oxford University Press. All rights reserved.

 Detailed Contents xxi
16.1.4 Ports 3 and 4 551
16.2 Control and Status Registers 551
16.2.1 Input/output control register 0 551
16.2.2 Input/output control register 1 552
16.2.3 Input/output status register 0 552
16.2.4 Input/output status register 1 553
16.3 Timers 553
16.3.1 Timer 1 553
16.3.2 Timer 2 554
16.4 Interrupts 556
16.4.1 Interrupt sources 556
16.4.2 Polling routine 557
16.4.3 Vectored interrupt 557
16.4.4 Interrupt control 559
16.4.5 Interrupt pending register 560
16.4.6 Interrupt mask register 561

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16.4.7 Global disable 561

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16.4.8 Program status word 561

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16.5 Serial Ports 562
16.5.1 Operating modes of serial port
it y 563
16.5.2 Serial port control/status registers 564
16.5.3 Determining baud rate 564
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16.5.4 Program for serial port data reception 565
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16.6 Analog-to-digital Converter 566

16.7 Digital-to-analog Converter 569
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16.8 High Speed Input Unit 570

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16.8.1 HSI interrupts 573

16.8.2 Programming HSI 573
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16.9 High Speed Output Unit 575

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16.9.1 HSO status 578

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16.10 Memory Expansion 578

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16.10.1 Single-chip mode 579

16.10.2 Expanded mode 579
16.10.3 Choice of bus width 580
16.10.4 Bus control 581
16.10.5 ROM/EPROM lock 583

PART IV: ADVANCED TRENDS

17. Microprocessor System Developments and Recent Trends 591

17.1 Introduction 591
17.2 Microcontroller Features and Developments 591
17.3 Microprocessor Development Systems 593
17.3.1 In-system programming 594
17.3.2 Debugger 594
17.3.3 Emulator 594
17.4 Cross Compiler for 8051 595
17.5 Programming 8051 in C Language 596

© Oxford University Press. All rights reserved.

xxii Detailed Contents
18. Advanced Microprocessors and Microcontrollers 604
18.1 Introduction 604
18.2 80186 Microprocessor 605
18.2.1 Architecture 605
18.2.2 Instruction set of 80186 606
18.3 80286 Microprocessor 607
18.3.1 Architecture 607
18.3.2 Register organization and real or protected addressing in
80286 608
18.3.3 Privilege levels in protected mode of operation 611
18.3.4 Descriptor cache or program-invisible registers 613
18.3.5 Accessing memory using GDT and LDT 613
18.3.6 Multitasking in 80286 615
18.3.7 Addressing modes and new instructions in 80286 616
18.3.8 Flag register 617
18.4 80386 Microprocessor 618

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18.4.1 Architecture of 80386 618

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18.4.2 Register organization in 80386 620

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18.4.3 Instruction set of 80386 623
18.4.4 Addressing memory in protected mode
it y 624
18.4.5 Physical memory organization in 80386 625
18.4.6 Paging mechanism in 80386 626
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18.5 80486 Microprocessor 629

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18.6 Pentium Microprocessor 632

18.6.1 Architecture of Pentium 632
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18.6.2 Protected mode operation of Pentium 637

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18.6.3 Addressing modes in Pentium 637

18.6.4 Paging mechanism in Pentium 637
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18.7 Other Versions of Pentium 637

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18.7.1 Pentium Pro processor 637

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18.7.2 Pentium II processor 638

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18.7.3 Pentium III processor 638

18.7.4 Pentium 4 processor 638
18.8 Operating Modes of Advanced Processors 638
18.9 Mode Transition 639
18.10 Memory Management in Protected Mode 640
18.11 Segment Descriptor 640
18.12 Protection: Purpose 643
18.12.1 Type checking 644
18.12.2 Limit checking/restriction of addressable domain 644
18.12.3 Privilege levels 645
18.13 Protected Mode Instructions 647
18.14 Multitasking 649
19. Embedded Systems 663
19.1 Introduction 663
19.1.1 Characteristics of embedded systems 663
19.1.2 Design metric 665
19.1.3 Evolution of embedded systems 667

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 Detailed Contents xxiii
19.1.4 Design technology 667
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19.3 Embedded Processor Architecture 669
19.3.1 RISC and CISC architectures 671
19.3.2 SISD/SIMD 673
19.3.3 The e200z6 core 673
19.3.4 Cell microprocessor 675
19.3.5 PowerPC architecture 675
19.3.6 PIC16F877 microcontroller 679
19.3.7 ARM processors 695
19.4 SUN SPARC Microprocessor 707
19.4.1 SPARC architecture 707
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19.4.3 Data types in SPARC architecture 712
19.4.4 SPARC instruction format 713
19.4.5 Adressing modes in SPARC microprocessor 714

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19.4.6 Instruction set in SPARC microprocessor 714

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19.4.7 Load and store instructions 715

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19.4.8 Arithmetic and logical instructions 716
19.4.9 Branch instructions it y 717
19.4.10 Special instructions 718
19.5 Software Embedded into System 721
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19.5.1 Codesign 722
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19.6 Bus Architectures 725

19.6.1 Parallel bus protocols 725
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19.6.2 Serial bus protocols 726

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19.6.3 Serial wireless protocols 727

19.7 Memory 727
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19.7.1 Memory technologies 728

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19.7.2 Memory hierarchy 728

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19.7.3 Memory interfacing 729

19.8 I/O Interfacing 729
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19.9 Smart Card Design 730

19.9.1 Vertical (concurrent) and horizontal (serial) codesign 731
19.9.2 Security extension 732
20. Hybrid Programming Techniques using ASM and C/C++ 736
20.1 Combining Assembly Language with C/C++ 736
20.2 Calling Conventions 737
20.2.1 CDECL calling convention 738
20.2.2 STDCALL calling convention 739
20.2.3 FASTCALL calling convention 740
20.3 Passing Parameter Techniques 740
20.4 Techniques for 16-bit ALP Microsoft C/C++ for DOS 741
20.4.1 Inline assembly 741
20.4.2 Linked assembly 742
20.5 Using ALP with C/C++ for 32-bit Applications 743
20.5.1 Calling ALP procedure from C 744
20.6 32-bit Windows Programming 744

© Oxford University Press. All rights reserved.

xxiv Detailed Contents
20.6.1 Console functions 745
20.6.2 Microsoft Win32 application programming interface 747
20.7 Program Development Methods 749
Appendix A: 8086 Case Studies 752
Appendix B: 8051 Case Studies 758
Appendix C: 8275 CRT Controller Chip 766
Appendix D: Multiple Choice Questions 777
Appendix E: 8086 Instruction Set 797
Appendix F: 8051 Instruction Set 803
Bibliography 811
Index 812

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 1
Microprocessors—Evolution and
Introduction to 8085
LEARNING OUTCOMES
After studying this chapter, you will be able to understand the following:
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1.1 INTRODUCTION
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The microprocessor is an electronic chip that functions as the central processing

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unit (CPU) of a computer. In other words, the microprocessor is the heart of any
computer system. Microprocessor-based systems with limited resources are called
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microcomputers. Today, microprocessors can be found in almost all consumer

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electronic devices such as computer printers, washing machines, microwave ovens,

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mobile phones, fax machines, and photocopiers and in advanced applications such
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dozen microprocessors in different forms inside various appliances. The recent

developments in the electronics industry and the large-scale integration of devices
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have led to rapid cost reduction and increased application of microprocessors and
their derivatives.
Typically, basic microprocessor chips have arithmetic and logic functional units
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all microprocessors use the basic concept of stored-program execution. Programs
or instructions to be executed by the microprocessor are stored sequentially in
memory locations. The microprocessor, or the processor in general, fetches the
instructions one after another and executes them in its arithmetic and logic unit. So
all microprocessors have a built-in memory access and management part as well
as some amount of memory.
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and programmed by the user. Without a program, the microprocessor unit is a
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© Oxford University Press. All rights reserved.

2 Microprocessors and Interfacing
must also understand the instructions that a microprocessor can support. Every
microprocessor has its own associated set of instructions; this list is given by all
microprocessor manufacturers. The instruction set for microprocessors is in two
forms—one in mnemonic, which is comparatively easy to understand and the other
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for us to understand. Generally, programs are written using mnemonics called
assembly-level language and then converted into binary machine-level language.
This conversion can be done manually or using an application called assembler.
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real world data. Data are available in many forms and from many sources. To input
these data to the microprocessor, the microprocessor-based systems need some
input interfacing circuits and some electronic processing circuits. These circuits
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This again needs interfacing circuits and ports. So a microprocessor-based system

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The physical components of the microcomputer system are called hardware. The
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The semiconductor manufacturing technology for chips has developed from
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transistor–transistor logic (TTL) to complementary metal-oxide-semiconductor
(CMOS). Microprocessor manufacturing also has gone through these technological
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changes. The other semiconductor manufacturing technology available is emitter-

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coupled logic (ECL). TTL technology is most commonly used for basic digital
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integrated circuits; CMOS is favoured for portable computers and other battery-
powered devices because of its low power consumption.
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1.2 EXPLANATION OF BASIC TERMS

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The terms relevant to the use of microprocessors are explained in this section. These
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explanations will give the reader an understanding of various microprocessor-

related terms, technologies, and topics.
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required circuits and transistors etched on it to perform a particular function.
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base just a few millimeters square.
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unit of computer memory. In binary form, a bit can have only two values, 0 or 1,
whereas a decimal digit can have 10 values, represented by symbols 0 through 9.
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processed simultaneously by the basic arithmetic circuits of the microprocessor.
Word $ ZRUG LV D QXPEHU RI ELWV JURXSHG WRJHWKHU IRU SURFHVVLQJ ,Q
microprocessors, a word refers to the basic data size or bit size that can be processed

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 3
E\WKHDULWKPHWLFDQGORJLFXQLW $/8 RIWKHSURFHVVRU$ELWELQDU\QXPEHULV
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DRAM Dynamic random access memory is a semiconductor memory in which
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second. Without refreshing, the stored data will be lost. These memory chips are
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preferred in a computer system as these are slower but economical.

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faster.
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ROM Read only memory devices are memory devices whose contents are
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retained even after removing the power supply.

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to perform arithmetic and logic operations on digital data. The typical operations
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will decide the processor’s functionality.
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memory, and input/output signal ports. Microcontrollers can be called single-chip
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with the memory and I/O devices to execute the required programs is called
microcomputer.
Bus $EXVLV a group of wires/lines that carry similar information.
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between the microprocessor and peripherals.

© Oxford University Press. All rights reserved.

4 Microprocessors and Interfacing
Firmware Software written for a microprocessor application without provision
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of the computer system.
Input device The devices that are used for providing data and instructions to the
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mouse are the common input devices.
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digital computer are together called computer architecture.

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Von–Neumann architecture The architecture in which the same memory is
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used for storing programs as well as data.
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in two separate memory units.

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CISC processor Complex instruction set computer is a processor architecture

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that supports many machine language instructions.

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languages.
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or the instruction set of a particular microprocessor is called assembly language.
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understood as a high-level language program, but is easier than a machine language
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language is the lowest level language and cannot be easily understood.
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program into machine-level language program.
Compiler $FRPSXWHUSURJUDPWKDWFRQYHUWVWKHKLJKOHYHOODQJXDJHSURJUDP
into machine-level language program.

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 5
Interpreter $ FRPSXWHU SURJUDP WKDW UHDGV WKH KLJKOHYHO RU DVVHPEO\OHYHO
program one line at a time and converts it into machine-level program. Compiler
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end points.
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must be provided with the corresponding BIOS routines.
Clock The circuit in the computer that generates the sequence of evenly spaced
pulses to synchronize the activities of the processor and its peripherals is called
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is in the range of megahertz (MHz) or gigahertz (GHz).

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MIPS Million instructions per second is a measure of the speed at which the
instructions are executed in a processor.it y
Tri-state logic It is the logic used by digital circuits. The three logic levels used
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are high (1), low (0), and high impedance state (Z). The logic high state of a digital
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devices connected to it are not affected.

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Operating system The program that controls the entire computer and its
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resources and enables users to access the computer and its resources is called
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operating system. It is required for any computer system to become operational and
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user friendly. Under the control of the operating system, the computer recognizes
and obeys commands typed by the user. In addition, the operating system provides
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built-in routines that allow the user’s program to perform input/output operations
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microprocessor-based systems, the program that controls the hardware is called
monitor routine or monitor software.

1.3 MICROPROCESSORS AND MICROCONTROLLERS

The microprocessor (also called CPU) is the principal element of a computer
as it executes lists of instructions. These instruction lists are commonly called
programs. This programming language is complex to use since it is machine- or
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Two types of processors are manufactured—the microprocessor and the
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The distinction comes from the established functionalities.
The general-purpose microprocessors give the computers all the necessary
computing power. These microprocessors need additional circuitry elements such

© Oxford University Press. All rights reserved.

6 Microprocessors and Interfacing
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especially the start-up program that runs when the microprocessor is powered on.
There are numerous microprocessors developed by many companies. The
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Microcontrollers are microprocessors designed specially for control
applications. Microcontrollers contain memory units and I/O ports inside a chip, in
addition to the CPU. Microcontrollers are otherwise called embedded controllers;
they are generally used to control and operate smart machines. Some of the
machines using microcontrollers are microwave ovens, washing machines, sewing
machines, automobile ignition systems, computer printers, and fax machines.

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other advanced microcontrollers.
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1.4 MICROPROCESSOR-BASED SYSTEM

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called a microcomputer system. The system consists of CPU, memory, and I/O
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processor with the other parts of the microcomputer system needs a three-bus
architecture. The three buses are data bus, address bus, and control bus.
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to a postal address. In microprocessor systems, the addresses are all in binary,
and in general, represented in hexadecimal number format. The address is a

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 7

5$0DQG520 unique pattern used to identify a location

Output
in the memory or an I/O port. The
address bus consists of many lines that
transport the digital data sent by the
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corresponds to eight lines of addresses
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locations. These addresses are written
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bus, the greater the number of locations the processor is able to manage.
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or between the I/O device and the processor is done through the data bus. The

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the peripherals. The control bus basically consists of signals for selection of the
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correct memory or I/O device from the address, indication of the direction of data
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transfer, and synchronization of data transfer between slow devices. Many of the
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control signals are given by the processor itself because the processor is the master
of the computer system. Some control signals such as selection of the correct
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memory chip can be generated externally by the logic circuits. The timing of the
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control signal is very important; the entire timing of the operation is controlled by
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1.5 ORIGIN OF MICROPROCESSORS

7KHPLFURSURFHVVRULVWKHJUHDWHVWLQYHQWLRQRIWKHth century. Its evolution started
from the earlier mechanical calculating devices, in the 1930s. These devices used
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the personal computer revolution in the 1970s.
The transistor technology led to the development of complex devices called
integrated circuits (ICs). The microprocessor, or microprocessing unit (MPU),
later evolved as an IC and was designed to fetch instructions and execute the
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© Oxford University Press. All rights reserved.

8 Microprocessors and Interfacing
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1.5.1 First Generation (1971–1973)

The microprocessors that were introduced from 1971 to 1973 were referred to
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instructions serially—they fetched the instruction, decoded it, and then executed
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WUDQVLVWRUV7KH\ZHUHIDEULFDWHGXVLQJSFKDQQHOPHWDOR[LGHVHPLFRQGXFWRU
(PMOS) technology, which provided low cost, slow speed, and low output currents.
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microprocessors.

1.5.2 Second Generation (1974–1978)

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chip grew. Very large-scale integration (VLSI) led to chips that had speeds up to

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technology to fabricate chips. They were manufactured using n-channel metal-

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execution speed and higher chip densities.

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1.5.3 Third Generation (1978–1980)

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was designed using high density metal-oxide-semiconductor (HMOS) technology.
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1.5.4 Fourth Generation (1981–1995)

The microprocessors entered their fourth generation with designs containing more
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They were fabricated using high density/high speed complementary metal-oxide-
semiconductor (HCMOS), a low-power version of the HMOS technology.

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 9

1.5.5 Fifth Generation (1995–till date)

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Table 1.1 Comparison of general-purpose processors
General-purpose processors Transistors CPU speed Data length (bits)

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1.5.6 Timeline of Microprocessor Evolution

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10 Microprocessors and Interfacing
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operating systems, including Windows.
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memory architectures.
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architecture.
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(i) General-purpose processors
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General-purpose processors are those that are used in general computer system
integration and can be used by the programmer for any application. Common
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processors. Microcontrollers are microprocessor chips with built-in hardware
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generic control application. Special-purpose processorsDUHGHVLJQHGVSHFL¿FDOO\

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 11
to handle special functions required for an application. Digital signal processors
are examples of special-purpose processors; these have special instructions to
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CISC processors have about 70 to a few hundred instructions and are easier to
program. However, CISC processors are slower and more expensive than RISC

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(i) Processor memory/register

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Processor memory refers to a set of CPU registers. Processor registers are the
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are available within the processor, they are the fastest memory registers. The main
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bytes.
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12 Microprocessors and Interfacing
Primary memory is the storage area from which all the programs are executed.
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source codes, compilers, operating systems, etc. These are not accessed directly or
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devices are called non-volatile memories.
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 Microprocessors—Evolution and Introduction to 8085 13
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14 Microprocessors and Interfacing

1.9 TECHNOLOGY IMPROVEMENTS ADAPTED TO

MICROPROCESSORS AND COMPUTERS
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1.10 INTRODUCTION TO 8085 PROCESSOR

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© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 15
fetches instructions from the memory, decodes it (i.e., interprets the nature of
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stored in consecutive memory locations. The execution steps are repeated for all
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the results of the program may be either stored in the memory or transferred out
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the start of execution, the complete program must be stored in the memory. Let us
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single-byte instructions) and so on until it reaches the end of the program.
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16 Microprocessors and Interfacing
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1.11 ARCHITECTURE OF 8085

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similarities.
7KHLVFDOOHGDQELWSURFHVVRUVLQFHLWVGDWDOHQJWKDQGGDWDEXVZLGWKLV
HLJKWELWV,WKDVDQDGGUHVVLQJFDSDELOLW\RIELWVLHLWFDQDGGUHVV .%
RIPHPRU\ .% E\WHV 7KHSURFHVVRUFRQWDLQV¿YHIXQFWLRQDOXQLWV
L  $ULWKPHWLFDQGORJLFXQLW LL  *HQHUDOSXUSRVHUHJLVWHUV

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(iii) Special-purpose registers (iv) Instruction register and decoder

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(v) Timing and control unit

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1.11.1 Arithmetic and Logic Unit
$/8 LV WKH FLUFXLWU\ WKDW SHUIRUPV WKH DFWXDO QXPHULFDO DQG ORJLFDO RSHUDWLRQV
it y
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rs
DQG FRPSDULVRQ &03  DUH WKH DULWKPHWLF RSHUDWLRQV SRVVLEOH LQ WKH 
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,17$ 567 75$3

ni

,175 RST RST SID SOD

 
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Interrupt control Serial I/O control

ELWLQWHUQDO
or

data bus
xf
O

$FFXPXODWRU Temp reg. Instruction Multiplexer

  UHJ 
:   =  

}
)ODJÀLS Temp reg. Temp reg.
ÀRSV  %   &  
Reg. select

Temp reg. Temp reg.

Instruction '   (  
$ULWKPHWLF decoder Temp reg. Temp reg.
and logic and +   /   Register
unit machine Temp reg. Temp reg. array
$/8 cycle 6WDFNSRLQWHU 
 encoding
3URJUDPFRXQWHU 

Power 9 Incrementer/Decrementer

$GGUHVVODWFK 
supply *1'
Timing and control
; CLK
; *(1 Control Status '0$ Reset $GGUHVVEXIIHU  'DWD$GGUHVVEXIIHU 

CLK RD $/( IO/M +/'$ RESET OUT $±$ $'±$'

OUT 5($'< WR S0S1 HOLD 5(6(7,1 $GGUHVVEXV $GGUHVV'DWDEXV

Fig. 1.5 )XQFWLRQDOEORFNGLDJUDPRI,QWHO

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 Microprocessors—Evolution and Introduction to 8085 17
PLFURSURFHVVRU 7KH SRVVLEOH ORJLFDO RSHUDWLRQV DUH $1' $1'  25 25 
H[FOXVLYH25 (;25 FRPSOHPHQW &0$ HWF
7KH$/8RIWKHSURFHVVRULVFDOOHGDFFXPXODWRURULHQWHG$/8DVRQHRI
the data used in arithmetic and logic operations must be stored in the accumulator.
7KH RWKHU GDWD LV WDNHQ IURP D PHPRU\ ORFDWLRQ RU UHJLVWHU 7KH UHVXOWV RI WKH
arithmetic and logical operations are stored in the accumulator. If the operation
needs only one data, that data must be stored in the accumulator.

1.11.2 General-purpose Registers

$UHJLVWHULVDFROOHFWLRQRIHLJKW'W\SHÀLSÀRSVZLWKSDUDOOHOLQDQGSDUDOOHO
RXW RSHUDWLRQ$ ÀLSÀRS FDQ RQO\ VWRUH RQH ELW DW D WLPH7KHUHIRUH WR KDQGOH
HLJKWELWVDWDWLPHHLJKWÀLSÀRSVDUHUHTXLUHGDQGKHQFHWKHWHUPELWUHJLVWHU
Though the registers are all storage areas inside the microprocessor, they differ in
the purpose of storage. The general-purpose registers are used to store only the
data that is being used by the program under execution and the results obtained

s
from it. These general-purpose registers are user accessible through programs.

es
5HJLVWHUV%&'(+DQG/DUHWKHJHQHUDOSXUSRVHUHJLVWHUVLQWKH
DVVKRZQLQ)LJ7KH\FDQDOVREHFDOOHGVFUDWFKSDGUHJLVWHUV,QDOPRVWDOO

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arithmetic and logical it y
operations, these registers $FFXPXODWRU$  )ODJUHJLVWHU
are used as the second
rs
%  & 
RSHUDQGVWKH¿UVWRSHUDQG
ve

'  ( 
being the accumulator
$  7KH JHQHUDOSXUSRVH +  / 
ni

UHJLVWHUV DUH DOO ELW

U

6WDFNSRLQWHU 63  
registers but they can be
3URJUDPFRXQWHU 3&  
d

KDQGOHGDVELWUHJLVWHUV
or

as well. This can be Data bus $GGUHVVEXV

xf

achieved by combining OLQHV ELGLUHFWLRQDO OLQHV XQLGLUHFWLRQDO

the register pairs B and C,
O

D and E, and H and L to

Fig. 1.6 Registers of Intel 8085
SHUIRUPELWRSHUDWLRQV
They are then named register pairs BC, DE, and HL, respectively.
$PRQJ WKHVH SDLUV +/ KDV D VSHFLDO VLJQL¿FDQFH $ IHZ PHPRU\UHODWHG
LQVWUXFWLRQVRIWKH UHIHULQVWUXFWLRQVHW XVHWKH+/SDLUDVDPHPRU\SRLQWHU
)RU H[DPSOH WKH LQVWUXFWLRQ 029 $ 0 WUDQVIHUV WKH FRQWHQW RI WKH PHPRU\
location to which the HL pair is pointing, to the accumulator. The HL pair is pre-
loaded with the memory address in which data is available.

1.11.3 Special-purpose Registers

7KHUHDUHDOVRVSHFLDOSXUSRVHUHJLVWHUVWKDWDUHGHGLFDWHGWRDVSHFL¿FIXQFWLRQ
7KH DFFXPXODWRU ÀDJ UHJLVWHU SURJUDP FRXQWHU 3&  DQG VWDFN SRLQWHU 63 
FRQVWLWXWHWKHVSHFLDOUHJLVWHUVLQWKHPLFURSURFHVVRU
1.11.3.1 Accumulator
7KH DFFXPXODWRU LV DQ ELW UHJLVWHU LW LV D SDUW RI WKH $/8 DQG LV WKH PRVW

© Oxford University Press. All rights reserved.

18 Microprocessors and Interfacing
LPSRUWDQW UHJLVWHU ,W LV XVHG WR VWRUH ELW GDWD DQG WR SHUIRUP DULWKPHWLF DQG
logical operations. The output of an operation is also stored in the accumulator.
7KHDFFXPXODWRULVLGHQWL¿HGDVUHJLVWHU$LQWKHLQVWUXFWLRQVHWRIWKH7KH
SURJUDPPHUFDQXVHLWDWDQ\WLPHWRVWRUHDQELWELQDU\QXPEHU%HLQJRQO\
HLJKWELWVORQJLWFDQRQO\KROGRQHE\WHDWDWLPH$Q\SUHYLRXVGDWDVWRUHGLQWKLV
UHJLVWHUZLOOEHRYHUZULWWHQDVVRRQDVQHZGDWDLVVWRUHG7KHPLFURSURFHVVRU
communicates with input/output devices only through the accumulator.
1.11.3.2 Flag Register
7KLVLVDVSHFLDOELWUHJLVWHU(DFKELWRIWKHÀDJUHJLVWHULVTXLWHLQGHSHQGHQWRIWKH
others. In all other registers, each bit is part of a single binary byte value and hence
HDFKELWZRXOGKDYHDQXPHULFDOYDOXH7KHÀDJLVDQELWUHJLVWHUXVHGWRLQGLFDWH
the status of a recent arithmetic or logical operation. It may be set or reset after an
arithmetic or logical operation according to the condition of the processed data. The
¿YHÀDJELWVDUH]HUR = FDUU\ &< VLJQ 6 SDULW\ 3 DQGDX[LOLDU\FDUU\ $& 
WKHLUELWSRVLWLRQVLQWKHÀDJUHJLVWHUDUHVKRZQLQ)LJ7KHUHPDLQLQJWKUHHELWV
J J

s
es
' ' DQG '  RI WKH ÀDJ
register remain unassigned; S Z ; $& ; P ; CY

Pr
WKH\DUHPDUNHGZLWKDQ;WR D7 '
it y ' ' D3 ' D1 D0
show that they are not used
and are don’t cares. Fig. 1.7 Flag register
rs

$Q\ÀDJUHJLVWHUELWLVVDLGWREHµVHW¶ZKHQLWVYDOXHLVDQGµFOHDUHG¶ZKHQLWV
ve

YDOXHLV7KHPRVWFRPPRQO\XVHGÀDJVDUH]HURFDUU\DQGVLJQ$&ÀDJFDQQRW
be accessed externally.
ni

6LJQÀDJ 6  7KHVLJQÀDJLVMXVWDFRS\RIWKHELW' PRVWVLJQL¿FDQWELW²

U

06%  RI WKH DFFXPXODWRU $ QHJDWLYH QXPEHU KDV D  LQ ELW  DQG D SRVLWLYH
d

QXPEHUKDVDLQ¶VFRPSOHPHQWUHSUHVHQWDWLRQ7KLVÀDJLQGLFDWHVWKHVLJQRI
or

the number. (It may be recalled that signed magnitude numbers use 1 to indicate
xf

DQHJDWLYHQXPEHUDQGWRLQGLFDWHDSRVLWLYHQXPEHU 7KLVÀDJFDQEHXVHGLQ
O

signed arithmetic operations.

=HURÀDJ =  7KH]HURÀDJLVVHWLIDQDULWKPHWLFRSHUDWLRQUHVXOWVLQD]HUR,W
sets, i.e., it changes to binary 1 if the result in the accumulator is zero; if not, it
remains reset, i.e., at binary 0.
&DUU\ ÀDJ &  7KH FDUU\ ÀDJ LV VHW ZKHQ D FDUU\ LV JHQHUDWHG LQ WKH SURFHVV
of an arithmetic operation in the accumulator. When addition is carried out, it
VRPHWLPHVUHVXOWVLQDQLQWKELWEHLQJFDUULHGRYHUWRWKHQH[WE\WH7KH&ÀDJ
FRSLHVWKHYDOXHRIWKHFDUU\ZKLFKLVDQH[WUDELWIURP',WDOVRUHÀHFWVWKH
value of the borrow in subtractions.
$X[LOLDU\ FDUU\ ÀDJ $&  7KH DX[LOLDU\ FDUU\ ÀDJ LV VHW ZKHQ DQ DX[LOLDU\
carry is generated in the process of an arithmetic operation in the accumulator,
LHZKHQDFDUU\UHVXOWVIURPELW'DQGSDVVHVRQWR' IURPWKHORZHUQLEEOH
to the higher nibble). This carry is also called half-carry. It may also occur in the
SURFHVVRIDVXEWUDFWLRQRSHUDWLRQ,QRWKHUZRUGVWKLVÀDJLVVHWLIWKHVXEWUDFWLRQ
operation results in borrowing from the higher nibble.

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 19
3DULW\ÀDJ 3  7KHSDULW\ÀDJLVVHWLIWKHFRQWHQWRIWKHDFFXPXODWRUDIWHUDQ
DULWKPHWLFRSHUDWLRQKDVDQHYHQQXPEHURIV2WKHUZLVHWKHSDULW\ÀDJLVUHVHW
It is set for operation in the even parity mode.
1.11.3.3 Program Counter
3URJUDPFRXQWHU 3& LVDELWUHJLVWHUWKDWDOZD\VSRLQWVWRWKHDGGUHVVRIWKH
next instruction to be executed. In other words, this register is used to sequence the
H[HFXWLRQRIWKHLQVWUXFWLRQV$IWHUH[HFXWLRQRIHYHU\LQVWUXFWLRQWKHFRQWHQWRI
the memory location indicated by the PC is moved to the instruction register and
WKH3&LVORDGHGZLWKWKHQH[WDGGUHVV,WNHHSVWUDFNRIDSURJUDPE\FRXQWLQJWKH
memory address from which the next byte is to be fetched, and hence the name
program counter.
1.11.3.4 Stack Pointer
6WDFN LV DQ DUUD\ RI PHPRU\ ORFDWLRQV RUJDQL]HG LQ ODVWLQ ¿UVWRXW /,)2  RU
¿UVWLQODVWRXW ),/2 IDVKLRQ,WLVDFFHVVHGXVLQJDELWSRLQWHUUHJLVWHUFDOOHG

s
VWDFNSRLQWHU 63 ZKLFKKROGVWKHDGGUHVVRIWKHPHPRU\ORFDWLRQRIWKHWRSRI

es
WKH VWDFN7KH SURJUDPPHU FDQ UHVHUYH DQG DOORFDWH D VHULHV RI 5$0 ORFDWLRQV

Pr
WR EH XVHG DV D VWDFN DQG DFFRUGLQJO\ LQLWLDOL]H WKH VWDFN SRLQWHU7KH UDQJH RI
VWDFN PHPRU\ ORFDWLRQV PXVW EH FKRVHQ FDUHIXOO\ VR WKDW LW GRHV QRW DIIHFW WKH
it y
SURJUDPVSDFH,QDOOPLFURSURFHVVRUEDVHGV\VWHPVWKHVWDFNLVPDLQO\XVHGWR
rs
store the return address of the main program when a subroutine is called. While
WKHSURJUDPPHUXVHVWKHVWDFNIRUVWRUDJHDQGUHWULHYDORIGDWDWKHPLFURSURFHVVRU
ve

XVHVWKHVWDFNGXULQJVXEURXWLQHFDOOV&DUHPXVWEHWDNHQE\WKHSURJUDPPHUWR
ni

HQVXUHWKDWWKHGDWDVWRUHGLQWKHVWDFNLVUHWULHYHGSURSHUO\VRWKDWWKHGDWDVWRUHG
LQWKHVWDFNE\WKHSURFHVVRULVQRWDIIHFWHG
U
d

1.11.4 Instruction Register and Decoder

or

,WLVDQELWUHJLVWHUWKDWWHPSRUDULO\VWRUHVWKHLQVWUXFWLRQVGUDZQIURPPHPRU\
xf

locations, before their actual execution. The content of the register is decoded by
the decoder circuitry, where the nature of the operation to be performed is decided
O

(interpreted). In addition, there are two temporary registers W and Z, which are
controlled internally and not available for user access.

1.11.5 Timing and Control Unit

The timing and control unit gets commands from the instruction decoder and
issues signals on the data bus, address bus, and control bus. The following sections
explain the operation of the various buses and the timing.
 $W\SLFDOPLFURSURFHVVRUFRPPXQLFDWHVZLWKPHPRU\DQGLQSXWRXWSXWGHYLFHV
using buses. There are three types of buses—the address bus, the data bus, and the
control bus.
1.11.5.1 Data Bus
7KHPLFURSURFHVVRUSHUIRUPVLWVIXQFWLRQVXVLQJZLUHVRUOLQHVFDOOHGEXVHV)RU
H[DPSOHDQELWPLFURSURFHVVRUQRUPDOO\XVHVHLJKWZLUHVWRFDUU\GDWDEHWZHHQ
WKHPLFURSURFHVVRUDQGWKHPHPRU\7RPDNHWKHLUUHSUHVHQWDWLRQVLPSOHWKHGDWD
wires with common functions are grouped together and referred to as the data bus.

© Oxford University Press. All rights reserved.

20 Microprocessors and Interfacing
The data bus (D0–D7) is a two-way bus carrying data around the system.
Information going into the microprocessor and results coming out of the
microprocessor are through this data bus. It is used for transfer of binary information
between the microprocessor, memory, and peripherals. The lower group of eight
DGGUHVVOLQHV$±$LVPXOWLSOH[HGZLWKWKHGDWDEXVLQRUGHUWRUHGXFHWKHSLQ
count. Therefore, the multiplexed lower group of address lines and data lines is
PRUHJHQHUDOO\GHQRWHGDV$'±$'
1.11.5.2 Address Bus
The address bus carries addresses and is a one-way bus from the microprocessor to
the memory or other devices. It is a group of sixteen unidirectional lines that allows
ÀRZRIDGGUHVVIURPWKHSURFHVVRUWRLWVSHULSKHUDOGHYLFHV(DFKSHULSKHUDODQG
PHPRU\ORFDWLRQLVLGHQWL¿HGE\DELWELQDU\QXPEHUFDOOHGDGGUHVV,WIROORZV
WKDWWKHPD[LPXPQXPEHURIPHPRU\ORFDWLRQVWKDWFDQEHDGGUHVVHGE\WKH
SURFHVVRU LV  bytes   .% ,WV EDVLF IXQFWLRQ LV WR LGHQWLI\ D SHULSKHUDO RU

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memory location.

es
 7KHDGGUHVVEXVOLQHVDUHJHQHUDOO\LGHQWL¿HGDV$±$7KHDGGUHVVEXVKDV
HLJKWKLJKHURUGHUDGGUHVVOLQHV $±$ ZKLFKDUHXQLGLUHFWLRQDO7KHORZHU

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RUGHUHLJKWOLQHV $±$ DUHPXOWLSOH[HG WLPHVKDUHG ZLWKWKHHLJKWGDWDELWV
it y
(D0–D7) and hence, they are bidirectional. When the instruction is executed, these
lines carry the address bits during the early part, and the eight data bits during the
rs

later part. To separate the address from the data, a latch is used externally to save
ve

the address before the function of the bits changes.

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1.11.5.3 Control Bus

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The control bus carries control signals that are partly unidirectional and partly
ELGLUHFWLRQDO)RUDPLFURSURFHVVRUWRIXQFWLRQFRUUHFWO\WKHVHFRQWUROVLJQDOVDUH
d

vital. The control bus typically consists of a number of single lines that coordinate
or

DQGFRQWUROPLFURSURFHVVRURSHUDWLRQV)RUH[DPSOHDUHDGZULWHFRQWUROVLJQDO
xf

will indicate whether memory is being written into or read from. Thus, they are
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individual lines that provide a pulse to indicate the operation of the microprocessor.
,QIDFWWKHPLFURSURFHVVRUJHQHUDWHVVSHFL¿FFRQWUROVLJQDOVIRUHYHU\RSHUDWLRQ
which in turn are used to identify the type of device the processor intends to
communicate with. The following points describe the control and status signals
RIWKHSURFHVVRU
 L  $/( RXWSXW $GGUHVV /DWFK (QDEOH LV D SXOVH WKDW LV SURYLGHG ZKHQ DQ
DGGUHVV DSSHDUV RQ WKH $'±$' OLQHV DIWHU ZKLFK LW EHFRPHV  7KLV
VLJQDOFDQEHXVHGWRHQDEOHDODWFKWRVDYHWKHDGGUHVVELWVIURPWKH$'

 (ii) RD DFWLYHORZRXWSXW 7KH5HDGVLJQDOLQGLFDWHVWKDWGDWDDUHEHLQJUHDG

lines, thereby de-multiplexing the address bus and data bus.

from the selected I/O or memory device and that they are available on the

(iii) WR DFWLYHORZRXWSXW 7KH:ULWHVLJQDOLQGLFDWHVWKDWWKHGDWDRQWKHGDWD

data bus.

(iv) IO/M RXWSXW ,WLVDVLJQDOWKDWGLVWLQJXLVKHVEHWZHHQDPHPRU\RSHUDWLRQ

bus are to be written into a selected memory or I/O location.

DQG DQ ,2 RSHUDWLRQ$Q DFWLYH ORZ RQ WKLV VLJQDO VKRZV LW LV D PHPRU\

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 21
operation (IO/M = 0) and a high on this line indicates an I/O operation (IO/M
= 1).
Table 1.2 Status signals and
Y  6 DQG 6 RXWSXW  7KHVH DUH VWDWXV associated operations
VLJQDOV XVHG WR VSHFLI\ WKH NLQG RI
operation being performed. The status S1 S0 States
signals combine with I/O signals to 0 0 Halt
govern various operations; they are 0 1 Write
OLVWHG LQ 7DEOH  ,I ERWK 6 DQG 6 1 0 Read
are low, the operation of the processor 1  )HWFK
tends to halt. If S0 is low and S1 is
high, the processor reads data. If S0 is high and S1 is low, the processor
writes data onto a memory or I/O device. If both S0 and S1 are high, the
fetch operation is performed.
7KHVFKHPDWLFUHSUHVHQWDWLRQRIWKHEXVVWUXFWXUHVKRZQLQ)LJH[SODLQV

s
how the movement of data within the computer is accomplished by a series of

es
EXVHV$GGUHVVLQIRUPDWLRQGDWDDQGFRQWUROVLJQDOVKDYHWREHFDUULHGDURXQG
inside the microprocessor as well as in the external system. Hence, the buses are

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present both internally and externally.
YL  ,QWHUUXSWV7KHVHVLJQDOVDUHXVHGWRPDNHWKHPLFURSURFHVVRUUHVSRQGWRKLJK
it y
priority externally initiated signals. When an interrupt signal is detected by the
rs
processor, it suspends the execution of the current program and executes the
ve

SURJUDPFRUUHVSRQGLQJWRWKHLQWHUUXSWVLJQDOLQVWHDG)LYHLQWHUUXSWVLJQDOV
,175567567567DQG7UDS DUHDYDLODEOHWRIDFLOLWDWHWKH
ni

SURFHVVRUWRUHFHLYHDQGDFNQRZOHGJHWKHLQWHUUXSWFDOORISHULSKHUDOV7KH
U

SURFHVVRUDFFHSWVWKUHHPRUHH[WHUQDOO\LQLWLDWHGVLJQDOV²5(6(7,1,
d

Hold, and Ready as inputs. The following points explain these signals in
EULHI
or

D  ,175 LQSXW  ,W LV D JHQHUDOSXUSRVH LQWHUUXSW UHTXHVW VLJQDO ,W LV DQ
xf

active high signal.

O

(b) ,17$ RXWSXW ,WLVXVHGWRDFNQRZOHGJHDQLQWHUUXSW,WLVDQDFWLYHORZ

signal.
F  5HVWDUWLQWHUUXSWV LQSXW 7KHVHDUHYHFWRUHGLQWHUUXSWVWKDWWUDQVIHUWKH

$ $GGUHVVEXV
$

Memory Input
 Real
Output
MPU world
data
D7 Data bus
D0
Control bus

Fig. 1.8 6FKHPDWLFUHSUHVHQWDWLRQRIWKHEXVVWUXFWXUH

© Oxford University Press. All rights reserved.

22 Microprocessors and Interfacing
SURJUDPFRQWUROWRVSHFL¿FPHPRU\ORFDWLRQV7KH\KDYHKLJKHUSULRULW\
WKDQ,175LQWHUUXSWV7KHSULRULW\RUGHULV567567DQG567

G  7UDS LQSXW ,WLVDQRQPDVNDEOHLQWHUUXSWLHLWFDQQRWEHVWRSSHGRU
RYHUULGGHQE\DQ\FRPPDQG,WKDVWKHKLJKHVWSULRULW\DPRQJDOO
interrupts.
(e) 5(6(7 ,1 LQSXW :KHQ WKH VLJQDO RQ WKLV SLQ JRHV ORZ WKH SURJUDP
counter is set to zero and the processor is reset. It is an active low signal.
I  5(6(7287 RXWSXW 7KLVVLJQDOFDQEHXVHGWRUHVHWRWKHUGHYLFHVWKDW
are connected to the processor. It is an active high signal.
J  +ROG LQSXW  7KLV VLJQDO LQGLFDWHV WKDW D SHULSKHUDO VXFK DV D GLUHFW
PHPRU\DFFHVV '0$ FRQWUROOHULVUHTXHVWLQJWKHXVHRIWKHDGGUHVV
and data buses.
K  +/'$ RXWSXW ,WLVDQDFNQRZOHGJHVLJQDOWKDWLVVHQWLQUHVSRQVHWR
the Hold request. During the Hold state, the peripheral (I/O) devices

s
get control over the data and address buses for data transfer to and from

es
PHPRU\7KLVRSHUDWLRQLVFDOOHGGLUHFWPHPRU\DFFHVV '0$ '0$

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is useful when high-speed peripherals want to transfer data to and from
memory. The processor does not intervene during this period.
it y
L  5HDG\ LQSXW  ,W LV D VLJQDO WKDW VHUYHV WR GHOD\ WKH PLFURSURFHVVRU
rs
read/write signals until a slow-responding peripheral is ready to send or
accept data. If this signal goes low, then the processor is allowed to wait
ve

IRUDQLQWHJUDOQXPEHURIFORFNF\FOHVXQWLO5HDG\EHFRPHVKLJK7KH
5HDG\VLJQDOPXVWEHV\QFKURQL]HGZLWKWKHSURFHVVRUFORFN
ni
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; 1  VCC
d

;  39 HOLD
or

'0$
RESET OUT 3  +/'$
Serial   V *1'
xf

SOD 37 CLK (OUT)

I/O
signals SID   5(6(7,1 ;7$/
O

Higher-order
75$3   5($'< ;; VCCVSS address bus
567 7  IO/M $
567  33 S1 $
567 9  RD SID Multiplexed
 lower-order
,175 10 31 WR SOD
75$3 address/data
,17$ 11 30 $/( 567 bus
$'
$'   S0 567
$' 13  $ 567
,175
$'
$/(

$'   $ ,17$ S1
$'   $ 5($'< S0
HOLD IO/M
$'   $ +/'$
$' 17  $ RESET RD
$'   $ ,1 WR
$' 19  $
VSS   $ RESET OUT CLK (OUT)
(a) (b)

Fig. 2.7 GHWDLOV D 3LQGLDJUDP E 6LJQDOJURXSV

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 23
 7KHW\SLFDOSLQOD\RXWDQGVLJQDOJURXSVRIWKHPLFURSURFHVVRUDUHVKRZQ
LQ)LJV D DQG E UHVSHFWLYHO\7KHLVDYDLODEOHZLWKSLQVDVD
GXDOLQOLQHSDFNDJH ',3 
 ,QWHOKDVSLQVRSHUDWHVDW 0+]FORFNIUHTXHQF\DQGUHTXLUHV V
for power supply.
1.11.5.4 Serial I/O Signals
There are two signals to implement serial transmission. They are serial input data
(SID) and serial output data (SOD). The data bits are sent over a single line, one
bit at a time, in serial transmission.
(i) 6,' LQSXW  7KH ELW GDWD RQ WKLV OLQH LV ORDGHG LQ WKH VHYHQWK ELW RI WKH
accumulator whenever a RIM instruction is executed.
(ii) 62' RXWSXW  7KH RXWSXW 62' LV VHW RU UHVHW DV VSHFL¿HG E\ WKH 6,0
instruction.
5,0DQG6,0LQVWUXFWLRQVKDYHEHHQH[SODLQHGLQGHWDLOLQ&KDSWHU

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es
1.11.5.5 Power Supply and System Clock
7KH IROORZLQJ SLQV DUH DYDLODEOH LQ WKH  FKLS WR SURYLGH SRZHU DQG FORFN

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VLJQDOWRWKHSURFHVVRU
(i) ; ; LQSXW $ PLFURSURFHVVRU QHHGV D VTXDUH ZDYH FORFN  VLJQDO WR
it y
HQVXUHWKDWDOOLQWHUQDORSHUDWLRQVDUHV\QFKURQL]HG$FU\VWDORU5±&RU/±&
rs

QHWZRUNLVFRQQHFWHGWRWKHVHWZRSLQV7KHFU\VWDOIUHTXHQF\LVLQWHUQDOO\
ve

divided by two to give the operating system frequency. There are three
advantages in increasing the frequency of a crystal—as frequency increases,
ni

the crystal size becomes smaller, and the crystal becomes lighter and cheaper.
U

7KHUHIRUHFORFNFLUFXLWVLQFOXGHDGLYLGHE\WZRFLUFXLWVRWKDWDGRXEOH
d

frequency crystal can be used. So, to run the microprocessor at 3 MHz, a

 0+] FU\VWDO VKRXOG EH FRQQHFWHG WR WKH ; DQG ; SLQV7KH FU\VWDO LV
or

SUHIHUUHG DV D FORFN VRXUFH EHFDXVH RI LWV KLJK VWDELOLW\ ODUJH 4 TXDOLW\
xf

IDFWRU DQGDEVHQFHRIIUHTXHQF\GULIWLQJZLWKDJLQJ:LWKRXWDFORFNVLJQDO
O

the microprocessor cannot execute any program.

(ii) &/. RXWSXW 7KLVRXWSXWFORFNSLQLVXVHGWRSURYLGHWKHFORFNVLJQDOWRWKH
rest of the system.
3RZHUVXSSOLHV VCC² V supply; VSS—ground reference.

1.12 MICROPROCESSOR INSTRUCTIONS

Every microprocessor has its own instruction set. Based on the design of the
$/8DQGWKHGHFRGLQJXQLWPLFURSURFHVVRUPDQXIDFWXUHUVJHQHUDOO\OLVWRXWWKH
instructions for every microprocessor manufactured. The instruction set consists
of both assembly language mnemonics and the corresponding machine code.
7KHSXUSRVHRIWKHLQVWUXFWLRQVHWLVWRIDFLOLWDWHWKHGHYHORSPHQWRIHI¿FLHQW
programs by the users. The instruction set is based on the architecture of the
processor. So to understand the instruction set of a processor, it is necessary to
understand the basic architecture of the microprocessor and the user-accessible

© Oxford University Press. All rights reserved.

24 Microprocessors and Interfacing
UHJLVWHUVLQLW$Qinstruction is a bit pattern that is decoded inside a microprocessor
WRSHUIRUPDVSHFL¿FIXQFWLRQ7KHDVVHPEO\ODQJXDJHPQHPRQLFVDUHWKHFRGHVIRU
these binary patterns so that the user can easily understand the functions performed
by these instructions. The entire group of instructions that a microprocessor
can handle is called its instruction set; this determines the microprocessor’s
IXQFWLRQDOLW\7KH,QWHOSURFHVVRUKDVLWVRZQVHWRILQVWUXFWLRQVOLVWHGERWK
LQPQHPRQLFVDQGPDFKLQHFRGHDOVRFDOOHGDVREMHFWFRGH$VWKHLVDQ
ELWSURFHVVRUWKHPDFKLQHFRGHVIRUWKHLQVWUXFWLRQVDUHDOVRELWVZLGH
7KH V\QWD[ IRU  LQVWUXFWLRQV PD\ FRQWDLQ RQH RU PRUH RI WKH IROORZLQJ
QRWDWLRQV
5 ELWUHJLVWHU $%&'(+DQG/ 
Rs = Source register
}
5G 'HVWLQDWLRQUHJLVWHU $%&'(+DQG/
Rp = Register pair (BC, DE, HL, and SP)
3 3RUWDGGUHVV ELWELQDU\QXPEHURUWZRKH[GLJLWV

s
ELW ELWGDWDRUWZRKH[GLJLWV

es
ELW ELWGDWDDGGUHVVRUIRXUKH[GLJLWV

Pr
( ) = Contents of
it y
1.13 CLASSIFICATION OF INSTRUCTIONS
rs
0LFURSURFHVVRU LQVWUXFWLRQV FDQ EH FODVVL¿HG EDVHG RQ SDUDPHWHUV VXFK DV
ve

functionality, length, and operand addressing.

ni

1.13.1 Based on Functionality

U

%DVHGRQWKHIXQFWLRQDOLW\WKHLQVWUXFWLRQVDUHFODVVL¿HGLQWRWKHIROORZLQJ¿YH
FDWHJRULHV
d
or

 L  'DWDWUDQVIHU FRS\ RSHUDWLRQV LL  $ULWKPHWLFRSHUDWLRQV

(iii) Logical operations (iv) Branching operations
xf

(v) Machine control operations

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1.13.1.1 Data Transfer (Copy) Operations

This group of instructions copies data from a location called source register to
another location called destination register. Generally, the contents of the source
UHJLVWHU DUH QRW PRGL¿HG$OWKRXJK WKH WHUP data transfer is used for the copy
operation, it is misleading because it implies that the contents of the source
memory location are destroyed. The various types of data transfer are listed in
Table 1.3 along with examples of each type.
Table 1.3 Types of data transfer
Type Example
7UDQVIHUULQJGDWDEHWZHHQRQHUHJLVWHU 029$'²&RSLHVWKHFRQWHQWRI
and another register D to the accumulator
6WRULQJDGDWDE\WHLQDUHJLVWHURU 09,&+²/RDGVUHJLVWHU&ZLWK 
PHPRU\ORFDWLRQ WKHGDWD+
(Contd)

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 25
Table 1.3 Types of data transfer (Contd)
Type Example
7UDQVIHUULQJGDWDEHWZHHQDPHPRU\ /'$+²/RDGVWKHFRQWHQWVRI
ORFDWLRQDQGDUHJLVWHU PHPRU\ORFDWLRQ+LQWKHDFFXPXODWRU
7UDQVIHUULQJGDWDEHWZHHQDQ,2GHYLFH ,13257²7UDQVIHUVGDWDIURPDQLQSXW
and the accumulator device to the accumulator

1.13.1.2 Arithmetic Operations

$ULWKPHWLFRSHUDWLRQVLQFOXGHDGGLWLRQVXEWUDFWLRQLQFUHPHQWDQGGHFUHPHQW$V
WKHKDVDQDFFXPXODWRURULHQWHG$/8RQHRIWKHGDWDXVHGLQWKHDULWKPHWLF
operations is stored in the accumulator; the result is also stored in the accumulator.
$ULWKPHWLFDQGORJLFDORSHUDWLRQVFDQQRWEHH[HFXWHGZLWKRXWWKHDFFXPXODWRU
$GGLWLRQ $''  7KH DGGLWLRQ LQVWUXFWLRQV RI WKH  DGG WKH FRQWHQWV RI
a register or memory location with the contents of the accumulator. The result

s
es
LV VWRUHG LQ WKH DFFXPXODWRU 7KH ,QWHO  LQVWUXFWLRQ VHW VXSSRUWV WZR W\SHV
RI DGGLWLRQ LQVWUXFWLRQV²ZLWK DQG ZLWKRXW DGGLWLRQ RI WKH FDUU\ ÀDJ FRQWHQW WR

Pr
WKH OHDVW VLJQL¿FDQW ELW RI WKH QXPEHUV7KH LQVWUXFWLRQ VHW DOVR VXSSRUWV ELW
it y
addition, i.e., the content of the HL register pair can be added to that of another
register pair and the result stored in the HL register pair.
rs

6XEWUDFWLRQ 68%  7KH LQVWUXFWLRQ VHW RI WKH  VXSSRUWV WZR W\SHV RI
ve

VXEWUDFWLRQ²ZLWK ERUURZ DQG ZLWKRXW ERUURZ /LNH DGGLWLRQ WKH VXEWUDFWLRQ

ni

operation also uses the accumulator as reference, i.e., it subtracts the content of a
register or memory location from that of the accumulator and stores the result in
U

the accumulator.
d

Increment/Decrement These operations can be used to increment or decrement

or

WKHFRQWHQWVRIDQ\UHJLVWHUUHJLVWHUSDLURUPHPRU\ORFDWLRQ8QOLNHWKHDULWKPHWLF
xf

and logical operations, the increment and decrement operations need not be based
O

upon the accumulator.

1.13.1.3 Logical Operations
Logical instructions are also accumulator-oriented, i.e., they require one of the
operands to be placed in the accumulator. The other operand can be any register or
memory location. The result is stored in the accumulator. The operations that use
WZRRSHUDQGVDUHORJLFDO$1'25DQG(;257KHRSHUDWLRQWKDWXVHVDVLQJOH
RSHUDQG LHWKHDFFXPXODWRU LVWKHORJLFDOFRPSOHPHQWRU127RSHUDWLRQ
7KHLQVWUXFWLRQVHWRIWKHVXSSRUWVURWDWLRQRIWKHGDWDVWRUHGLQDFFXPXODWRU
The data can be rotated left or right, through the carry or without the carry.
7KHPRVWLPSRUWDQWLQVWUXFWLRQLVWKHFRPSDUHLQVWUXFWLRQ7KLVLQVWUXFWLRQ
is used to compare register or memory content with the accumulator content. The
UHVXOWRIFRPSDULVRQVXFKDVHTXDOWRJUHDWHUWKDQRUOHVVWKDQLVUHÀHFWHGLQWKH
ÀDJUHJLVWHUELWV
1.13.1.4 Branching Operations
Branching instructions are important for programming a microprocessor. These

© Oxford University Press. All rights reserved.

26 Microprocessors and Interfacing
instructions can transfer control of execution from one memory location to another,
HLWKHUFRQGLWLRQDOO\RUXQFRQGLWLRQDOO\%UDQFKLQJFDQWDNHSODFHLQWKHIROORZLQJ
WZRZD\V
 L  ([HFXWLRQFRQWUROFDQQRWUHWXUQWRWKHSRLQWRIEUDQFKLQJ([DPSOH-XPS

 (ii) Execution control can return to the point of branching, which is stored by the
instructions

([DPSOH6XEURXWLQHFDOOLQVWUXFWLRQV
1.13.1.5 Machine Control Operations
These instructions can be used to control the execution of other instructions. They
include halting the operation of the microprocessor, interrupting program execution,
HWF'HWDLOHGH[SODQDWLRQVIRULQVWUXFWLRQVDUHJLYHQLQ6HFWLRQ

1.13.2 Based on Length

%DVHG RQ WKH OHQJWK RI WKH PDFKLQH ODQJXDJH FRGH  LQVWUXFWLRQV FDQ EH
FODVVL¿HGLQWRWKHIROORZLQJWKUHHW\SHV

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es
(i) One-byte instructions (ii) Two-byte instructions
(iii) Three-byte instructions

Pr
$VVHPEO\ ODQJXDJH LQVWUXFWLRQV VKRXOG EH FRQYHUWHG LQWR PDFKLQH FRGH IRU
it y
storage and execution by the processor. So the length of the machine language
code instructions determines the length of the program. This in turn determines the
rs

amount of memory required for the program.

ve

1.13.2.1 One-byte Instructions

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Instructions that require only one byte in machine language are called one-byte
U

instructions. These instructions just have the machine code or opcode alone to
represent the operation to be performed. The common examples are the instructions
d
or

that have their operands within the processor itself. Some examples of one-byte
LQVWUXFWLRQVDUHJLYHQLQ7DEOH(YHQWKRXJKWKHLQVWUXFWLRQ$''0DGGVWKH
xf

content of a memory location to that of the accumulator, its machine code requires
O

only one byte. Table 1.4 2QHE\WHLQVWUXFWLRQV

Let us now understand the
instruction MOV Rd, Rs. This Opcode Operand Machine code/Opcode/
instruction copies the contents of Hex code
source register Rs to destination 029 $% 
register Rd. (Rd Å Rs) $'' 0 
It is coded as 01dddsss. Here, ;5$ $ $)
ddd is the binary code of one of the
seven general-purpose registers that is the destination of the data and sss is the
binary code of the source register.
Example:
MOV A, B (coded as 01111000 = 78H)
1.13.2.2 Two-byte Instructions
Instructions that require two bytes in machine code are called as two-byte
LQVWUXFWLRQV 7KH ¿UVW E\WH RI WKH WZRE\WH LQVWUXFWLRQV LV WKH RSFRGH ZKLFK

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 27
VSHFL¿HV WKH RSHUDWLRQ WR EH SHUIRUPHG 7KH VHFRQG E\WH LV WKH ELW RSHUDQG
ZKLFKLVHLWKHUDQELWQXPEHURUDQDGGUHVV6RPHFRPPRQH[DPSOHVRIWZR
E\WHLQVWUXFWLRQVDUHOLVWHGLQ7DEOH
Table 1.5 7ZRE\WHLQVWUXFWLRQV
Opcode Operand Machine code/Opcode/Hex code Byte description
 09, $)+ ( )LUVWE\WH
   ) 6HFRQGE\WH
 $', )+ & )LUVWE\WH
   ) 6HFRQGE\WH
 ,1 + '% )LUVWE\WH
    6HFRQGE\WH

The instruction is stored in two consecutive memory locations.

s
MVI R, data—(R data)

es
Example:

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MVI A, 32H (coded as 3E 32 in two contiguous bytes)
This is an example of immediate addressing.it y
7KHIROORZLQJWZRLQVWUXFWLRQVDUHDOVRH[DPSOHVRIWZRE\WHLQVWUXFWLRQV
rs
 L  $',GDWD $ $GDWD 
 LL  287SRUW ZKHUHSRUWLVDQELWGHYLFHDGGUHVV 3RUW  $ 6LQFHWKHE\WH
ve

is not the data itself, but points directly to where it is located, this is called
ni

GLUHFWDGGUHVVLQJ)RUDGHWDLOHGDFFRXQWRIDGGUHVVLQJPRGHVVHH6HFWLRQ
U

1.13.3.
d

1.13.2.3 Three-byte Instructions

or

Instructions that require three bytes in machine code are called three-byte
LQVWUXFWLRQV,QPDFKLQHODQJXDJHWKH¿UVWE\WHRIWKHWKUHHE\WHLQVWUXFWLRQV
xf

LVWKHRSFRGHZKLFKVSHFL¿HVWKHRSHUDWLRQWREHSHUIRUPHG7KHQH[WWZRE\WHV
O

UHIHUWRWKHELWRSHUDQGZKLFKLVHLWKHUDELWQXPEHURUWKHDGGUHVVRID
memory location. Some common examples of three-byte instructions are listed in
7DEOH
Table 1.6 7KUHHE\WHLQVWUXFWLRQV
Opcode Operand Machine code/Opcode/Hex code Byte description

 -03 + & )LUVWE\WH

   6HFRQGE\WH
90 Third byte
 /'$ + $ )LUVWE\WH
    6HFRQGE\WH
    7KLUGE\WH
 /;, ++  )LUVWE\WH
    6HFRQGE\WH
    7KLUGE\WH

© Oxford University Press. All rights reserved.

28 Microprocessors and Interfacing

7KHLQVWUXFWLRQ/;,5SELWGDWDFDQEHH[SODLQHGDVIROORZV
5SLVRQHRIWKHSDLUVRIUHJLVWHUV%&'(RU+/ZKLFKDUHXVHGDVELW
UHJLVWHUV7KHWZRGDWDE\WHVDUHWREHVWRUHGDVDELWQXPEHULQ/DQG+LQ
VHTXHQFH /;, + + LV FRGHG DV + + + LQ WKUHH E\WHV 7KLV LV DQ
example of immediate addressing.)
,QH[HFXWLQJWKHLQVWUXFWLRQ/'$DGGUWKHDFFXPXODWRULVORDGHGZLWKWKHPHPRU\
FRQWHQWRIWKHDGGUHVVJLYHQLQWKHLQVWUXFWLRQ$GGULVDELWDGGUHVV/'$+
LVFRGHGDV$+++ 7KLVLVDQH[DPSOHRIGLUHFWDGGUHVVLQJ

1.13.3 Addressing Modes in Instructions

Every instruction in a program has to operate on data. The process of specifying
the data to be operated on by the instruction is called addressing (I¿FLHQW
software development for the microprocessor requires complete familiarity with
the addressing mode employed for each instruction. )RUH[DPSOHWKHLQVWUXFWLRQV
029%$DQG09,$+DUHXVHGWRFRS\GDWDIURPDVRXUFHWRDGHVWLQDWLRQ

s
,QWKHVHLQVWUXFWLRQVWKHVRXUFHFDQEHDUHJLVWHURUDQELWQXPEHU +WR))+ 

es
the destination is a register. The source and destination are operands. The various

Pr
formats for specifying operands are called addressing modes7KHKDVWKH
IROORZLQJ¿YHW\SHVRIDGGUHVVLQJ it y
(i) Immediate addressing (ii) Memory direct addressing
(iii) Register direct addressing (iv) Indirect addressing
rs

(v) Implied or implicit addressing

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1.13.3.1 Immediate Addressing

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Immediate addressing transfers the Instruction

U

operand given in the instruction—a byte

Opcode Operand
or word—to the destination register or
d
or

memory location. The operand is part of

the instruction. The format for immediate Fig. 1.10 )RUPDWRILPPHGLDWH
xf

DGGUHVVLQJLVJLYHQLQ)LJ addressing
O

Example:
MVI A, 9AH
(a) The operand is part of the instruction.
(b) The operand is stored in the register mentioned in the instruction.
Example:
ADI 05H
D  $GG+WRWKHFRQWHQWVRIWKHDFFXPXODWRU
E  +LVWKHRSHUDQG
Immediate addressing has no memory reference to fetch data. It executes faster,
but has limited data range.
1.13.3.2 Memory Direct Addressing
Memory direct addressing moves a byte or word between a memory location and
register. The memory location address is given in the instruction. The instruction
set does not support memory-to-memory transfer. Memory direct addressing is
LOOXVWUDWHGLQ)LJ
© Oxford University Press. All rights reserved.
 Microprocessors—Evolution and Introduction to 8085 29

Instruction
2SFRGH0HPRU\DGGUHVV$ Memory

$
Operand

Fig. 1.11 )RUPDWRIPHPRU\GLUHFWDGGUHVVLQJ

Example:
LDA 850FH
7KLVLQVWUXFWLRQLVXVHGWRORDGWKHFRQWHQWVRIWKHPHPRU\ORFDWLRQ)+LQWKH

s
accumulator.

es
Example:

Pr
STA 9001H
This instruction is used to store the contents of the accumulator in the memory
it y
address 9001H.
rs
In these instructions, the memory address of the operand is given in the instruction.
ve

Direct addressing is also used for data transfer between the processor and
LQSXWRXWSXWGHYLFHV)RUH[DPSOHWKH,1LQVWUXFWLRQLVXVHGWRUHFHLYHGDWDIURP
ni

the input port and store it in the accumulator; the OUT instruction is used to send
U

the data from the accumulator to the output port.

d

Example:
or

IN 00H and OUT 01H

xf

1.13.3.3 Register Direct Addressing

O

Register direct addressing transfers a copy of a byte or word from the source
register to the destination register. The operand is in the register named in the
instruction. It executes very fast, has very limited register space, and requires
good assembly programming. The operand is within in the processor itself; so the
H[HFXWLRQLVIDVWHU5HJLVWHUGLUHFWDGGUHVVLQJLVLOOXVWUDWHGLQ)LJ

Instruction
Opcode Register R Registers

R
Operand

Fi
Fig. 1 12 ))RUPDWRIUHJLVWHUGLUHFWDGGUHVVLQJ
1.12 I L GL GG L

© Oxford University Press. All rights reserved.

30 Microprocessors and Interfacing
Example:
MOV Rd, Rs
MOV B, C
It copies the contents of register C to register B.
Example:
ADD B
It adds the contents of register B to the accumulator and saves it in the accumulator.
1.13.3.4 Indirect Addressing
Indirect addressing transfers a byte or word between a register and a memory
location. The address of a memory location is stored in a register and that register
LVVSHFL¿HGLQWKHLQVWUXFWLRQ7KLVLVLOOXVWUDWHGLQ)LJ
In indirect addressing, the effective address is calculated by the processor using
WKH FRQWHQWV RI WKH UHJLVWHU VSHFL¿HG LQ WKH LQVWUXFWLRQ7KLV W\SH RI DGGUHVVLQJ
HPSOR\VVHYHUDODFFHVVHV²WZRDFFHVVHVWRUHWULHYHWKHELWDGGUHVVDQGDIXUWKHU

s
access (or accesses) to retrieve the data which is to be loaded in the register.

es
Example:

Pr
MOV A, M it y
Here, the data is in the memory location pointed to by the contents of the HL pair.
The data is moved to the accumulator.
rs
ve

Instruction
Opcode Register address R
ni

Memory
U

Registers
d
or

Memory address
to operand Operand
R
xf
O

Fig. 1.13 )RUPDWRILQGLUHFWDGGUHVVLQJ

1.13.3.5 Implied or Implicit Addressing
,QLPSOLHGDGGUHVVLQJPRGHWKHLQVWUXFWLRQLWVHOIVSHFL¿HVWKHGDWDWREHRSHUDWHG
XSRQ )RU H[DPSOH &0$ FRPSOHPHQWV WKH FRQWHQWV RI WKH DFFXPXODWRU 1R
VSHFL¿FGDWDRURSHUDQGLVPHQWLRQHGLQWKHLQVWUXFWLRQ

1.14 INSTRUCTION SET OF 8085

7KH  PLFURSURFHVVRU LQVWUXFWLRQ VHW KDV  RSHUDWLRQ FRGHV DQG 
LQVWUXFWLRQV ,W LV FRPSDWLEOH ZLWK WKDW RI LWV SUHGHFHVVRU WKH $ EXW KDV
WZR DGGLWLRQDO LQVWUXFWLRQV²6,0 VHW LQWHUUXSW PDVN  DQG 5,0 UHDG LQWHUUXSW
PDVN ²UHODWHGWRVHULDO,27KHFRPSOHWHLQVWUXFWLRQVHWLVOLVWHGLQ$SSHQGL[
ZLWKDGGLWLRQDOLQIRUPDWLRQVXFKDVQXPEHURIFORFNVWDWHVUHTXLUHGIRUH[HFXWLRQ
DQGWKHÀDJVDIIHFWHG

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 31

1.14.1 Format of Assembly Language Instructions and Programs

$VVHPEO\ ODQJXDJH SURJUDPV DUH ZULWWHQ IRU SHUIRUPLQJ VSHFL¿F IXQFWLRQV
converted into machine language code, and then stored in the memory of the
microprocessor-based system. The conversion of an assembly language program
into machine language code is called assembling; the application that performs this
WDVNLVFDOOHGDVVHPEOHU7KLVFRQYHUVLRQRUDVVHPEOLQJFDQDOVREHGRQHPDQXDOO\
by the programmers. To facilitate the process of assembling, the assembly language
SURJUDPVDUHZULWWHQLQDVSHFL¿FIRUPDWDVVKRZQLQ)LJ
Memory address Machine code/Opcode Label Mnemonics with operands Comments

Fig. 1.14 )RUPDWIRUZULWLQJDVVHPEO\ODQJXDJHSURJUDPV

In general, the assembly language mnemonics with their operands are written
¿UVW7KHDGGUHVVZKHUHWKHLQVWUXFWLRQVDUHVWRUHGLVJLYHQDGXPP\QDPHFDOOHG
label. The purpose of labels is to give the correct branch addresses in instructions.

s
es
Labels are separated from mnemonics with a colon.
The comments column is essential for any program as it helps the programmer

Pr
understand the logic of the program at any point in time. Without comments, it is
GLI¿FXOWWRXQGHUVWDQGDQDVVHPEO\ODQJXDJHSURJUDP&RPPHQWVDUHVHSDUDWHG
it y
from the mnemonics with a semicolon.
7KH ¿UVW WZR FROXPQV FRUUHVSRQG WR WKH SK\VLFDO PHPRU\ DGGUHVV DQG WKH
rs

DFWXDOPDFKLQHFRGH7KHVHWZRFROXPQVDUH¿OOHGLQDIWHUFRPSOHWLQJWKHDVVHPEO\
ve

language programming. These columns must contain only binary numbers, but for
ni

HDV\XQGHUVWDQGLQJKH[DGHFLPDOQXPEHUVDUHXVHG)RUPDQXDODVVHPEOLQJWKHVH
WZR FROXPQV DUH ¿OOHG LQ E\ WKH SURJUDPPHU $Q DVVHPEOHU FDQ JHQHUDWH WKHVH
U

columns automatically.
d

$QH[DPSOHRIWKHDVVHPEO\ODQJXDJHSURJUDPIRUPDWLVJLYHQLQ7DEOH
or

Table 1.7 6DPSOHDVVHPEO\ODQJXDJHSURJUDP

xf
O

Memory Machine code/ Label Mnemonics Comments

address Opcode with operands
 ( 67$57 09,$)+ /RDGGDWDLQWKHDFFXPXODWRU
 )
   $GGUHVVRIWKHQH[WPHPRU\
location

7KHLQVWUXFWLRQLQ7DEOHPRYHVWKHGDWD)+WRWKHDFFXPXODWRU
1.14.2 Data Transfer Instructions
Data transfer instructions are used to transfer data between two registers in the
microprocessor or between a peripheral device and the microprocessor. Some
instructions and their features are given in the following points. The complete list
ZLWKH[SODQDWLRQVLVJLYHQLQ7DEOH
L  09,LQVWUXFWLRQLVXVHGIRUVWRULQJELWGDWDLQDPLFURSURFHVVRUUHJLVWHU
LL  /;,LQVWUXFWLRQLVXVHGIRUVWRULQJELWGDWDLQDUHJLVWHUSDLU

© Oxford University Press. All rights reserved.

32 Microprocessors and Interfacing
(iii) In direct addressing mode, MOV instruction is used for data transfer between
registers. In indirect addressing mode, MOV is used for data transfer between
DPHPRU\ORFDWLRQDQGDUHJLVWHU,IWKHLQVWUXFWLRQKDV0LQWKHRSHUDQG¿HOG
the memory location pointed to by the HL pair is considered for data transfer.
Table 1.8 Data transfer instructions
Mnemonics Tasks performed on Addressing Instruction Example
execution mode length
09,5ELW 0RYHVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 09,%)+
to the register
/;,5SELW /RDGVWKHELWGDWDLQ ,PPHGLDWH 7KUHHE\WHV /;,%$)+
the register pair
0295G5V &RSLHVWKHGDWDIURP 5HJLVWHU 2QHE\WH 029$%
the source register to direct
the destination register

s
/'$ELW /RDGVWKHDFFXPXODWRU 0HPRU\ 7KUHHE\WHV /'$)+

es
with the data from the direct

Pr
memory location
indicated by the
 ELWDGGUHVV
it y
/+/'ELW /RDGVWKH+DQG/ 0HPRU\ 7KUHHE\WHV /+/'$+
rs
registers directly from direct
ve

the two consecutive

memory locations
ni

indicated by the
 ELWDGGUHVV
U

67$ELW 6WRUHVWKHFRQWHQWVRI 0HPRU\ 7KUHHE\WHV 67$+

d

the accumulator in the direct

or

memory location
indicated by the
xf

 ELWDGGUHVV
O

6+/'ELW 6WRUHVWKHFRQWHQWVRI 0HPRU\ 7KUHHE\WHV 6+/')+

the H and L registers direct
in two consecutive
memory locations
indicated by the
 ELWDGGUHVV
PUSH Rp Pushes the contents of Register One byte PUSH B
the register pair onto direct
 DVWDFN
POP Rp Pops the top two memory Register One byte POP H
 ORFDWLRQVRIWKHVWDFN GLUHFW
onto a register pair
287ELW 2XWSXWVWKHGDWDLQWKH ,2 7ZRE\WHV 287+ 
accumulator to the port
indicated by the
 ELWDGGUHVV
(Contd)

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 33
Table 1.8 Data transfer instructions (Contd)
Mnemonics Tasks performed on Addressing Instruction Example
execution mode length
,1ELW ,QSXWVWKHGDWDIURPWKH ,2 7ZRE\WHV ,1+ 
 SRUWLQGLFDWHGE\WKH
 ELWDGGUHVVWRWKH
 DFFXPXODWRU
0295G0 &RSLHVWKHFRQWHQWVRI ,QGLUHFW 2QHE\WH 029%0
 WKHPHPRU\ORFDWLRQ
 SRLQWHGWRE\WKH+/
 UHJLVWHUSDLUWR
 WKHUHJLVWHU
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or

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34 Microprocessors and Interfacing
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LQ ¿UVWRXW /,)2  RU ¿UVWLQ ODVWRXW ),/2  DUUD\ 7KH WRS RI WKH VWDFN
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WKH PLFURSURFHVVRU 386+ LQVWUXFWLRQ ZLOO VWRUH WKH UHJLVWHU SDLU JLYHQ LQ
WKHLQVWUXFWLRQWRWKHWRSWZRPHPRU\ORFDWLRQVRIWKHVWDFN6LPLODUO\323
LQVWUXFWLRQZLOOFRS\WKHODVWWZRE\WHVVWRUHGLQWKHVWDFNWRWKHUHJLVWHUSDLU
PHQWLRQHGLQWKHLQVWUXFWLRQ&DUHPXVWEHWDNHQLQXVLQJWKHVHLQVWUXFWLRQVDV
WKHVWDFNLVFRQ¿JXUHGDVD/,)2DUUD\$QRWKHULQVWUXFWLRQWRVWRUHGDWDLQWKH
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ZLWKWKHFRQWHQWVRIWKH+/UHJLVWHUSDLU
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LQVWUXFWLRQZLOOFRS\WKHFRQWHQWVRIWKH+/UHJLVWHUSDLUWRWKHVWDFNSRLQWHU
 L[  ,1DQG287LQVWUXFWLRQVXVHELWSRUWDGGUHVVHVDVRSHUDQG,1LQVWUXFWLRQ
LVXVHGWRJHWGDWDIURPWKHLQSXWSRUWDQGWKHGDWDREWDLQHGLVVWRUHGLQWKH
DFFXPXODWRU287LQVWUXFWLRQLVXVHGWRLVVXHGDWDIURPWKHDFFXPXODWRUWR

s
DQRXWSXWSRUW

es
 [  ;&+* LQVWUXFWLRQ LV XVHG WR H[FKDQJH WKH FRQWHQWV RI WKH +/ DQG '(

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UHJLVWHUSDLUV
it y
1.14.3 Arithmetic Instructions
rs
7KHDULWKPHWLFLQVWUXFWLRQVVXSSRUWHGE\WKHDUHDGGLWLRQVXEWUDFWLRQDQG
WKHLUYDULDQWV7KHDULWKPHWLFLQVWUXFWLRQVDUHOLVWHGLQ7DEOH
ve
ni

Table 1.9 Arithmetic instructions

U

Mnemonics Tasks performed on Addressing Instruction Example

execution mode length
d
or

$',ELW $GGVWKHELWGDWDWR ,PPHGLDWH 7ZRE\WHV $',+

 WKHFRQWHQWVRIWKH
xf

 DFFXPXODWRU
O

$&,ELW $GGVWKHELWGDWDDQG ,PPHGLDWH 7ZRE\WHV $&,)+

 WKHFDUU\ÀDJWRWKH
 FRQWHQWVRIWKH
 DFFXPXODWRU
68,ELW 6XEWUDFWVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 68,$+
 IURPWKHFRQWHQWVRIWKH
 DFFXPXODWRU
6%,ELW 6XEWUDFWVWKHELWGDWD ,PPHGLDWH 7ZRE\WHV 6%,&+
 DQGWKHERUURZIURPWKH
 FRQWHQWVRIWKH
 DFFXPXODWRU
$''5 $GGVWKHFRQWHQWVRIWKH 5HJLVWHU 2QHE\WH $''&
 UHJLVWHUWRWKHFRQWHQWV GLUHFW
 RIWKHDFFXPXODWRU
(Contd)

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 35
Table 1.9 $ULWKPHWLFLQVWUXFWLRQV (Contd)
Mnemonics Tasks performed on Addressing Instruction Example
execution mode length
$'&5 $GGVWKHFRQWHQWVRIWKH 5HJLVWHU 2QHE\WH $'&(
register and the carry to direct
the contents of the
accumulator
SUB R Subtracts the contents of Register One byte SUB B
the register from that of direct
the accumulator
SBB R Subtracts the contents Register One byte SBB C
of the register and the direct
borrow from that of the
accumulator
'$'5S $GGVWKHFRQWHQWVRIWKH Register 2QHE\WH '$'%

s
es
register pair to that of the direct
H and L registers

Pr
,155 ,QFUHPHQWVWKHUHJLVWHU Register 2QHE\WH ,15%
by 1 it y direct
,1;5S ,QFUHPHQWVWKHUHJLVWHU Register 2QHE\WH ,1;%
pair by 1 direct
rs

DCR R Decrements the register Register One byte DCR E

ve

by 1 direct
'&;5S 'HFUHPHQWVWKHUHJLVWHU 2QHE\WH '&;'
ni

Register
pair by 1 direct
U

$''0 $GGVWKHFRQWHQWVRIWKH ,QGLUHFW 2QHE\WH $''0

d

memory location pointed

or

to by the HL register pair

to that of the accumulator
xf

$'&0 $GGVWKHFRQWHQWVRIWKH ,QGLUHFW 2QHE\WH $'&0

O

memory location pointed

to by the HL register pair
and the carry to that of
the accumulator
SUB M Subtracts the contents of Indirect One byte SUB M
the memory location
pointed to by the HL
register pair from that
of the accumulator
SBB M Subtracts the borrow and Indirect One byte SBB M
the contents of the
memory location pointed
to by the HL pair from
that of the accumulator
(Contd)

© Oxford University Press. All rights reserved.

36 Microprocessors and Interfacing
Table 1.9 $ULWKPHWLFLQVWUXFWLRQV (Contd)
Mnemonics Tasks performed on Addressing Instruction Example
execution mode length
,150 ,QFUHPHQWVWKHPHPRU\ ,QGLUHFW 2QHE\WH ,150
location pointed to by the
HL register pair by 1
DCR M Decrements the memory Indirect One byte DCR M
location pointed to by the
HL register pair by 1
'$$ &RQYHUWVWKHFRQWHQWVRI ,PSOLFLW 2QHE\WH '$$
the accumulator from
binary to BCD (Decimal-
 $GMXVW$FFXPXODWRU

7KHIROORZLQJSRLQWVOLVWVRPHNH\IHDWXUHVRIDULWKPHWLFRSHUDWLRQV

s
 L  )RUDULWKPHWLFRSHUDWLRQVRQHRIWKHGDWDPXVWEHVWRUHGLQWKHDFFXPXODWRU

es
and the other given or addressed in the instruction.

Pr
 LL  $GGZLWKFDUU\ LQVWUXFWLRQV DUH XVHG IRU PXOWLE\WH DQG KLJKHURUGHU E\WH
addition. it y
(iii) Similarly, subtract-with-borrow instructions are used in multi-byte and
rs
higher-order byte subtraction.
(iv) Increment and decrement instructions can be operated not only on the
ve

accumulator, but also on other registers including memory locations.

 Y  7KHFRQWHQWVRIDUHJLVWHUSDLUFDQEHLQFUHPHQWHGRUGHFUHPHQWHGXVLQJ,1;
ni

DQG'&;LQVWUXFWLRQV
U

 YL  '$$ LV WKH  LQVWUXFWLRQ WKDW VXSSRUWV %&' DGGLWLRQ7KH DGGLWLRQ RI
d

%&'GDWDLVGRQHOLNHELQDU\DGGLWLRQXVLQJWKH$''LQVWUXFWLRQ'$$LV
or

used to convert the result of the binary addition of BCD numbers into a BCD
xf

number. This instruction cannot be used to directly convert binary numbers

O

into BCD numbers.

1.14.4 Logical Instructions

7KH PRVW LPSRUWDQW ORJLFDO LQVWUXFWLRQV VXSSRUWHG E\ WKH  DUH$1' 25
(;25DQG1277KHFRPSOHWHOLVWLVJLYHQLQ7DEOH
Table 1.10 Logical instructions
Mnemonics Tasks performed on execution Addressing Instruction Example
mode length
$1,ELW 7KHELWGDWDLVORJLFDOO\$1'HG ,PPHGLDWH 7ZRE\WHV $1,)+
with the contents of the accumulator.
;5,ELW 7KHELWGDWDLVORJLFDOO\(;25HG ,PPHGLDWH 7ZRE\WHV ;5,+
with the contents of the accumulator.
25,ELW 7KHELWGDWDLVORJLFDOO\25HG ,PPHGLDWH 7ZRE\WHV 25,+
with the contents of the accumulator.
(Contd)

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 37
Table 1.10 Logical instructions (Contd)
Mnemonics Tasks performed on execution Addressing Instruction Example
mode length
$1$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH $1$&
 ORJLFDOO\$1'HGZLWKWKHFRQWHQWV GLUHFW
of the accumulator.
;5$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH ;5$'
 ORJLFDOO\(;25HGZLWKWKHFRQWHQWV GLUHFW
of the accumulator.
25$5 7KHFRQWHQWVRIWKHUHJLVWHUDUH 5HJLVWHU 2QHE\WH 25$(
logically ORed with the contents direct
of the accumulator.
$1$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH $1$0
location pointed to by the HL
 UHJLVWHUSDLULVORJLFDOO\$1'HG

s
es
with the contents of the accumulator.
;5$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH ;5$0

Pr
location pointed to by the HL
 UHJLVWHUSDLULVORJLFDOO\(;25HG
it y
with the contents of the accumulator.
rs
25$0 7KHFRQWHQWVRIWKHPHPRU\ ,QGLUHFW 2QHE\WH 25$0
location pointed to by the HL
ve

register pair is logically ORed

ni

with the contents of the accumulator.

U

RLC Rotates the bits of the accumulator Implicit One byte RLC
left by one position
d

RRC Rotates the bits of the accumulator Implicit One byte RRC
or

right by one position

xf

5$/ 5RWDWHVWKHELWVRIWKHDFFXPXODWRU ,PSOLFLW 2QHE\WH 5$/

O

left by one position, through the carry

5$5 5RWDWHVWKHELWVRIWKHDFFXPXODWRU ,PSOLFLW 2QHE\WH 5$5
right by one position, through the carry
&3,ELW &RPSDUHVWKHELWGDWDZLWKWKH ,PPHGLDWH 7ZRE\WHV &3,))+
contents of the accumulator
CMP R Compares the contents of the register Register One byte CMP B
with that of the accumulator direct
CMP M Compares the contents of the memory Indirect One byte CMP M
location pointed to by the HL register
pair with that of the accumulator
&0$ &RPSOHPHQWVWKHFRQWHQWVRIWKH ,PSOLFLW 2QHE\WH &0$
accumulator
CMC Complements the carry Implicit One byte CMC
STC Sets the carry Implicit One byte STC

© Oxford University Press. All rights reserved.

38 Microprocessors and Interfacing
)RUORJLFDORSHUDWLRQVRQHRIWKHGDWDPXVWEHVWRUHGLQWKHDFFXPXODWRUDQGWKH
other given or addressed in the instruction. Logical operations can be performed
with immediate data, data stored in a register, or indirectly addressed memory
location content.
Besides the instructions already mentioned, two types of rotate instructions
DUH DYDLODEOH LQ WKH  2QH VHW²5/& DQG 55&²URWDWHV WKH DFFXPXODWRU
contents within itself. The RLC instruction shifts the accumulator content left by
RQHELW,QWKHSURFHVVWKHPRVWVLJQL¿FDQWELWRIWKHDFFXPXODWRUEHFRPHVWKH
OHDVWVLJQL¿FDQWELW7KH55&LQVWUXFWLRQVKLIWVWKHDFFXPXODWRUFRQWHQWULJKWE\
one bit.
 7KHRWKHUVHWRIURWDWHLQVWUXFWLRQV²5$/DQG5$5²URWDWHVWKHDFFXPXODWRU
FRQWHQW DORQJ ZLWK WKH FDUU\ ÀDJ 7KH 5$/ LQVWUXFWLRQ VKLIWV WKH DFFXPXODWRU
FRQWHQWOHIWE\RQHELWDQGLQWKHSURFHVVWKHPRVWVLJQL¿FDQWELWZLOOEHVKLIWHGWR
WKHFDUU\ÀDJDQGWKHFDUU\ÀDJFRQWHQWZLOOEHVKLIWHGWRWKHOHDVWVLJQL¿FDQWELWRI
the accumulator.

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 7KHLQVWUXFWLRQVHWRIWKHVXSSRUWVDFRPSDUHLQVWUXFWLRQIRUFRPSDULQJ

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the magnitude of two binary numbers. The compare instructions are used to

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CPI instruction uses immediate addressing and CMP uses registers or indirectly
it y
addressed memory location for comparing with the accumulator. The result of the
FRPSDUHLQVWUXFWLRQLVLQGLFDWHGLQWKHÀDJUHJLVWHUDVIROORZV
rs

 ,I> $ íRSHUDQG@ LH $  RSHUDQGWKH]HURÀDJLVVHW

ve

 ,I> $ íRSHUDQG@LH $ RSHUDQGWKHFDUU\ÀDJLVVHW

 ,I> $ íRSHUDQG@!LH $ !RSHUDQGWKH]HURDQGFDUU\ÀDJVDUHUHVHW
ni
U

1.14.5 Branching Instructions

d
or

Branching instructions are used to transfer the program execution to a different

address. Branching instructions are of two types—jump instructions and
xf

subroutine instructions. The jump instructions merely transfer the execution from
O

one location in the program to another, whereas the subroutine instructions in the
main program transfer execution to a new location and also return to the main
SURJUDP 5HWXUQ LQVWUXFWLRQV DUH XVHG IRU WKLV SXUSRVH7KH EUDQFKLQJ FDQ WDNH
SODFH XQFRQGLWLRQDOO\ RU FRQGLWLRQDOO\ EDVHG RQ WKH ÀDJ FRQGLWLRQV VKRZQ LQ
Table 1.11. PCHL instruction is a special instruction used to branch to the address
stored in the HL register pair.
RST nLVWKHUHVWDUWLQVWUXFWLRQVXSSRUWHGE\WKH8SRQH[HFXWLRQRIWKH
RST n instruction, the program execution will be transferred to the address given
by n î)RUH[DPSOH567LQVWUXFWLRQZLOOWUDQVIHUWKHH[HFXWLRQWRWKHDGGUHVV
+ZKLFKLVWKHKH[DGHFLPDOHTXLYDOHQWRI LQGHFLPDOIRUP 
 ,QPDFKLQHFRGHRURSFRGHWKHELWRUKH[GLJLWDGGUHVVHVLQWKHEUDQFKLQJ
instructions are given such that the lower-order byte of the address follows the
KLJKHURUGHUE\WH)RUH[DPSOH-03+LVFRGHGDV&7KHRSFRGHIRU
-03&LVVWRUHG¿UVWIROORZHGE\DQGWKHQE\

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 39
Table 1.11 Branching instructions
Mnemonics Tasks performed on Instruction Example
execution length
-03ELW -XPSXQFRQGLWLRQDOO\ 7KUHHE\WHV -03
-&ELW -XPSLIFDUU\LVVHW 7KUHHE\WHV -&
-1&ELW -XPSRQQRFDUU\ 7KUHHE\WHV -1&
-3ELW -XPSRQSRVLWLYH 7KUHHE\WHV -3
-0ELW -XPSRQPLQXV 7KUHHE\WHV -0
-=ELW -XPSRQ]HUR 7KUHHE\WHV -=
-1=ELW -XPSRQQR]HUR 7KUHHE\WHV -1=
-3(ELW -XPSRQSDULW\HYHQ 7KUHHE\WHV -3(
-32ELW -XPSRQSDULW\RGG 7KUHHE\WHV -32
&$//ELW &DOOXQFRQGLWLRQDOO\ 7KUHHE\WHV &$//
&&ELW &DOORQFDUU\ 7KUHHE\WHV &&
&1&ELW &DOORQQRFDUU\ 7KUHHE\WHV &1&

s
&3ELW &DOORQSRVLWLYH 7KUHHE\WHV &3

es
&0ELW &DOORQPLQXV 7KUHHE\WHV &0
&=ELW &DOORQ]HUR 7KUHHE\WHV &=

Pr
&1=ELW &DOORQQR]HUR
it y 7KUHHE\WHV &1=
&3(ELW &DOORQSDULW\HYHQ 7KUHHE\WHV &3(
&32ELW &DOORQSDULW\RGG 7KUHHE\WHV &32
rs
RET Return unconditionally One byte RET
ve

RC Return on carry One byte RC

51& 5HWXUQRQQRFDUU\ 2QHE\WH 51&
ni

RP Return on positive One byte RP

U

RM Return on minus One byte RM

RZ Return on zero One byte RZ
d

51= 5HWXUQRQQR]HUR 2QHE\WH 51=

or

RPE Return on parity even One byte RPE

xf

RPO Return on parity odd One byte RPO

PCHL Copy HL contents to One byte PCHL
O

the program counter

567 5HVWDUW 2QHE\WH 567

1.14.6 Machine Control Instructions

Machine control instructions are used to control the microprocessor execution
DQGIXQFWLRQLQJDQGDUHOLVWHGLQ7DEOH7KH\DUHH[SODLQHGLQGHWDLOLQWKH
IROORZLQJSRLQWV
 L  123PHDQVQRRSHUDWLRQ:KHQWKLVLQVWUXFWLRQLVH[HFXWHGQRWKLQJLVGRQH
no changes occur in the contents of the registers. The program counter alone
is incremented to fetch and execute the next instruction.
(ii) HLT instruction is used to halt the execution of the program. The operation
of the microprocessor is suspended when HLT instruction is executed. The
only way to exit the halt state is to apply the hardware reset signal.

© Oxford University Press. All rights reserved.

40 Microprocessors and Interfacing
(iii) Interrupts are disabled and enabled using DI and EI signals, respectively.
Once the DI instruction has been executed, the processor ignores any
interrupt request received. To enable interrupts again, the EI instruction has
to be executed.
(iv) The SIM instruction is used to send serial data on the serial output data
(SOD) line of the microprocessor and the RIM instruction is used to receive
serial data on the serial input data (SID) line of the processor. The SIM and
RIM instructions are also associated with the setting and reading of interrupt
PDVNVIRU567KDUGZDUHLQWHUUXSWV
Table 1.12 Machine control instructions
Mnemonics Tasks performed on execution Addressing Instruction
mode length
123 1RRSHUDWLRQ ,PSOLFLW 2QHE\WH
HLT Halts the microprocessor execution Implicit One byte

s
es
DI Disables interrupts Implicit One byte
EI Enables interrupts Implicit One byte

Pr
5,0 5HDGVLQWHUUXSWPDVN ,PSOLFLW 2QHE\WH
6,0 6HWVLQWHUUXSWPDVN it y ,PSOLFLW 2QHE\WH

1.15 SAMPLE PROGRAMS

rs
ve

1. Write an assembly language program to add two numbers.

ni

The program given in Table 1.13 uses immediate addressing for the two data to be
DGGHG7KHGDWDWREHDGGHGDUHVWRUHGLQPHPRU\ORFDWLRQV+DQG+
U

7KHVXPLVVWRUHGLQWKHPHPRU\ORFDWLRQ+7KLVSURJUDPDVVXPHVWKDWQR
d

carry is generated from the addition.

or

Table 1.13 3URJUDPIRUDGGLQJWZRELWQXPEHUV

xf
O

Memory Machine code/ Labels Mnemonics with Comments

address Opcode operands
 ( 67$57 09,$+ /RDGWKH¿UVWQXPEHULQ
    WKHDFFXPXODWRU
 &  $',+ $GGWKHVHFRQGQXPEHUZLWK
    WKHFRQWHQWVRIWKHDFFXPXODWRU
   67$+ 6WRUHWKHVXPLQWKHPHPRU\
    ORFDWLRQ+
  
   +/7 7HUPLQDWHSURJUDPH[HFXWLRQ

 :ULWHDQDVVHPEO\ODQJXDJHSURJUDPWRDGGWZRQXPEHUVRIELWVHDFK
This program also uses immediate addressing for loading the data in the processor
UHJLVWHUV7KHVXPLVVWRUHGLQWKHPHPRU\ORFDWLRQV+DQG+DVVKRZQ
LQ7DEOH

© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 41
Table 1.14 3URJUDPIRUDGGLQJWZRELWQXPEHUV
Memory Machine Labels Mnemonics with Comments
address code/ operands
Opcode
  67$57 /;,+)+ /RDGWKH¿UVWELWQXPEHULQ
 )   WKH+/UHJLVWHUSDLU
 
   /;,%$+ /RDGWKHQH[WQXPEHULQWKH%&
 $   UHJLVWHUSDLU
  
   '$'% $GGWKHWZRQXPEHUVXVLQJ
double addition instruction.
   6+/'+ 6WRUHWKHUHVXOWLQWKH+/SDLULQ
    WKHPHPRU\ORFDWLRQV+DQG
    +

s
$   +/7 7HUPLQDWHSURJUDPH[HFXWLRQ

es
Pr
3. Write an assembly language program to add the two numbers stored in the
PHPRU\ORFDWLRQV+DQG+DQGVWRUHWKHUHVXOWLQ+
it y
This program uses indirect addressing instructions to load the numbers to be
rs
added in the processor registers. The carry, if generated, is ignored. The program
LVVKRZQLQ7DEOH
ve

Table 1.15 3URJUDPIRUDGGLQJWZRQXPEHUVIURPPHPRU\

ni
U

Memory Machine Labels Mnemonics with Comments

address code/ operands
d

Opcode
or

  67$57 /;,++ ,QLWLDOL]H+/UHJLVWHUSDLUWRSRLQW

xf

    WRWKHPHPRU\ORFDWLRQRIWKH

O

    ¿UVWQXPEHU

 (  029$0 /RDGWKH¿UVWQXPEHULQWKH
accumulator.
   ,1;+ ,QFUHPHQWWKH+/SDLUWRSRLQWWR
the memory location of the next
number.
   $''0 $GGWKHWZRQXPEHUV
   ,1;+ ,QFUHPHQWWKH+/SDLUWRSRLQWWR
the next memory location.
   0290$ 6WRUHWKHFRQWHQWVRIWKH
accumulator in the memory location
pointed to by the HL register pair.
   +/7 7HUPLQDWHSURJUDPH[HFXWLRQ

© Oxford University Press. All rights reserved.

42 Microprocessors and Interfacing

1.16 INSTRUCTION EXECUTION

7KH  PLFURSURFHVVRU LV GHVLJQHG WR IHWFK WKH LQVWUXFWLRQ SRLQWHG WR E\ WKH
program counter, and then decode and execute the instruction within the processor.
,IQHFHVVDU\IXUWKHURSHUDQGIHWFKWDNHVSODFHEHIRUHFRPSOHWLQJWKHH[HFXWLRQ
(DFKLQVWUXFWLRQDVZHKDYHDOUHDG\VHHQKDVWZRSDUWV²RSHUDWLRQFRGH NQRZQ
DVRSFRGH DQGRSHUDQG7KHRSFRGHLVDFRPPDQGVXFKDV$''DQGWKHRSHUDQG
is an object to be operated on, such as a byte or the contents of a register.
Instruction cycleLVWKHWLPHWDNHQE\WKHSURFHVVRUWRFRPSOHWHWKHH[HFXWLRQ
RIDQLQVWUXFWLRQ$QLQVWUXFWLRQF\FOHFRQVLVWVRIRQHWRVL[PDFKLQHF\FOHV
Machine cycle is the time required to complete one operation—accessing either
WKHPHPRU\RUDQ,2GHYLFH$PDFKLQHF\FOHFRQVLVWVRIWKUHHWRVL[7VWDWHV
T-state LVWKHWLPHFRUUHVSRQGLQJWRRQHFORFNSHULRG7KH7VWDWHLVWKHEDVLF
XQLWXVHGWRFDOFXODWHWKHWLPHWDNHQIRUH[HFXWLRQRILQVWUXFWLRQVDQGSURJUDPVLQ
a processor.
7RH[HFXWHDSURJUDPWKHSHUIRUPVYDULRXVRSHUDWLRQVVXFKDVRSFRGHIHWFK

s
es
operand fetch, and memory read/write or I/O read/write. The microprocessor’s
H[WHUQDOFRPPXQLFDWLRQIXQFWLRQFDQEHGLYLGHGLQWRWKUHHFDWHJRULHV

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(i) Memory read/write (ii) I/O read/write
 LLL  ,QWHUUXSWUHTXHVWDFNQRZOHGJH
it y
rs

POINTS TO REMEMBER
ve

x The microprocessor is an electronic circuit that functions as the central processing

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x The microprocessor is the controlling element in a computer system. The

unit (CPU) of a computer, providing computational control.
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microprocessor performs data transfers, does simple arithmetic and logical

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x The basic operation of the microprocessor is to fetch instructions stored in the
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x Microprocessors are used in almost all advanced electronic systems.

memory and execute them one by one in sequence.
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x Microcontrollers are advanced forms of microprocessors, with memory and ports

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present within the chip.

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microprocessor.

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x The microprocessor is a semiconductor device consisting of electronic logic
circuits manufactured using either large-scale integration (LSI) or very large-scale
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x $EXV is a collection of wires connecting two or more chips.
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devices using three buses—address bus, data bus, and control bus.

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© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 43

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x The microprocessor operations related to data manipulation can be summarized in
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(i) Transferring data
(ii) Performing arithmetic operations
(iii) Performing logical operations

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(iv) Testing for a given condition and altering the program sequence

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registers, or implicit in the opcode. The method of specifying an operand (directly,
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The instructions are executed in steps of machine cycles and each machine cycle
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KEY TERMS
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The output of an operation is also stored in the accumulator. The accumulator is

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Address bus This bus carries the binary number (i.e., the address) used to access
a memory location. Binary data can then be written into or read from the addressed
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bits.
Addressing mode It is the method of specifying the data to be operated on by the
instruction.
Bus It is a group of conducting lines that carry data, address, and control signals
Clock speed This determines how many instructions per second the processor can
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Control bus This bus has various lines for coordinating and controlling
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Data bus This bus carries data in binary form between the microprocessor and
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DMA controller ,WLVXVHGWRWDNHFRQWURORIWKHV\VWHPEXVE\SODFLQJDKLJKVLJQDO
on the Hold pin.
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the status of the instruction executed most recently.

© Oxford University Press. All rights reserved.

44 Microprocessors and Interfacing
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signal.
Immediate addressing It transfers the operand given in the instruction—a byte or
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to be operated on.
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location addressed by another register.
Instruction cycle It is the time required to execute an instruction.
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input/output instructions it is high; for memory reference instructions it is low.
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sequence can be resumed.

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Machine cycle It is the time required to access the memory or input/output devices.

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Operand It is the data on which the operation is performed.
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287 This instruction is used to move data from the accumulator to an I/O port.
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Ready It is an input signal to the processor. It is used by the memory or I/O devices
to get extra time for data transfer or to introduce wait states in the bus cycles.
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Register direct addressing It transfers a copy of a byte or word from a source

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register to a destination register.

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for execution. The execution time is represented in T-states.

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REVIEW QUESTIONS
1. What is the main function of a computer?
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11. What are the basic units of a microprocessor?
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© Oxford University Press. All rights reserved.

 Microprocessors—Evolution and Introduction to 8085 45
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address lines?
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17. What is the role of CPU in a computer?
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other interrupts?
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33. When and where is the Ready signal used?

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46 Microprocessors and Interfacing
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THINK AND ANSWER

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possible to write subroutines? How would the subroutine be called? How would

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© Oxford University Press. All rights reserved.