5 4 3 2 1

D D

m
LCFC Confidential

co
s.
ic
S360 Lucienne M/B Schematics Document

at
C C

em
AMD FP6 Lucienne with DDR4

ch
2020-12-01

kS
REV:1.0
oo
eb

B B
ot
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/02/27 Deciphered Date 2020/02/27 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S360 Lucienne
Date: Friday, December 04, 2020 Sheet 1 of 110
5 4 3 2 1
 A B C D E

S360 Lucienne M/B Schematics

Memory BUS (DDR4)

PCI-Express Channel A DDR4-SO-DIMM X1
NGFF SSD1
4x Gen3 Page 14
PEIe GPP[3:0]
Page 22 1.2V DDR4 3200MT/s UP TO 16G x 1

HDMI Conn. HDMI x4 Lane Port1 Memory BUS (DDR4)

1

Channel B DDR4 DRAM DOWN 1

Page 19

1.2V DDR4 3200MT/s 4pcs x16 Page 15

eDP Conn
USB 2.0_2
Int. Camera USB Port2
USB 2.0 Port2 eDP x2 Lane port0 USB 3.0 1x
USB 2.0 1x USB 2.0 Port4

m
Int. DMIC Conn. USB 3.0 Port4 Page 20

Page 17 AMD FP6 APU

co
Type-C data Function
LUCIENNE USB 3.0 1x__0
Type-C Conn
Redriver for 17'' USB 2.0 1x__0 USB 2.0 Port0 Type-C MUX
SATA HDD SATA Gen3 USB3.1 Gen1

s.
PS8527CTQ&
SATA Port2
PI3EQX6741STZDEX Co_lay UMA USB 3.0 Port0 RTS5448
Page 20
Page 30

ic
NGFF Card PCIe 1x
WLAN&BT

at
Key E USB2.0 _7
2 PCIe Port4 2

USB 2.0 Port6 Page 27

em
USB 2.0_2
DMIC_CLK/DAT

Finger Print USB 2.0 _6

h
I2C_1 BUS
USB 2.0 Port7 Page 32 Touch Pad

Sc
Page 32

Touch Screen I2C_0

Share with LPC
USB 2.0 Port3 Page 17
ok 32MB
SPI BUS SPI ROM
W74M12JWSSIQ
1.8V SOP8
o
Audio SPK Conn. Page 08
Combo Jack Codec HD Audio
eb

HP&Mic Combo Conn. Realtek ALC3287

50 TPM (Remove)
USB2.0_4
ot

3 USB2.0 Connect NPCT750LADYX 3

USB2.0_5 Page 29
SD/MMC Conn. C&R
Realtek RTS5146-GR
N

PCIE0

Hall sensor
AH1912(Intel)
EC SMBUS
Battery
IT8227VG-128-CX Page 38
PWR BUTTON/Novo button SMBUS
Page 31
PWR LED
Finger printer diaplay LED
S360_IO Board 24Pin Connect Charger
Page 39

Int.KBD Thermistor
USB2.0 Connect Page 32 Page 25
Thermal Sensor
LAN_RJ45 F75303M_MSOP10
Page 25
RTL8111H_CG

4
Hall sensor 4

AH1912(Intel)

PWR BUTTON/Novo button

PWR LED
Finger printer diaplay LED Title
Security Classification LC Future Center Secret Data
V14/V15 IO Board_36Pin Connect Issued Date 2013/08/15 Deciphered Date 2013/08/15 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S360 Lucienne 0.3

Date: Friday, December 04, 2020 Sheet 2 of 110

A B C D E
 5 4 3 2 1

B+
Richtek +5VALW/8A
RT6258CGQUF
UQFN12_3X3
Adaptor Converter +5VLP/ 100mA
D
EC_ON_5VALW_R EN FOR SYSTEM PGOOD D

NA

Silergy +3VLP/ 100mA

SY8386BRHC
QFN16_2P5X2P5 +3VALW Richtek +1.8VS/2A
Converter +3VALW/ 6A RT8068AZQW

m
EC_ON_3VALW_R EN
FOR SYSTEM PGOOD Convertor
ALW_PWRGD FOR +1.8VS
SUSP_N EN

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s.
ic
TI
BQ24780SRUYR

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C
Battery Charger C

m
Switch Mode
LCFC +1.2V/10A
LV5028

e
SYSON_VDDQ S5 PMIC +0.6VS/1A

ch
SUSP_N S3
FOR SYS
POK_VDDQ
SMBus
+5VALW

kS
+0.75VALW/6A
EC_0.75VALW_EN EN
PGOOD 0.75VALW_PG

oo
+5VALW +1.8VALW/3A

Battery EC_ON_1.8VALW EN PGOOD

Li-ion eb
3S1P +3VALW
+2.5V/1A
ot
B B
EC_VPP_PWREN EN
N

Richtek VDDC_VDD/44A
RT3663BRGQW
WQFN52_6X6 VDDCR_SOC/13A
APU_SVI2 VIDs controller
EC_VR_ON EN FOR CPU CORE&SOC CPU_VR_READY
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S360_ALC
Date: Friday, December 04, 2020 Sheet 3 of 110
5 4 3 2 1
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

Power Plane HSIO Matrix

+5VS
+3VS
B+ +3VALW +1.2V +1.8VS
HSIO PORT Function
0 Type-C USB2.0 Port 0
+0.75VS Type-c Port
+3VL +5VALW +2.5V_DDR 1 USB3.0_P1
+0.6VS
2 Carmera
1
+5VL 1
+1.8VALW 3 Touch Screen Change to I2C
+VDDC_VDD
+0.75VALW 4 USB2.0 Port(For DB USB2.0)
State +VDDCR_SOC USB2.0 5 Cardread USB3.0 Port
6 FingerPrint
7 BT
S0 O O O O O
0 Type-C USB3.0 Port 0
S0Ix

om
1 USB3.0_P1
USB3.0 4 NC
5 NC
S3 O O O X X 0 eDP 2*Lane

.c
1 HDMI
S3 DisPlay 2 NC
O O O X X

s
Battery only 3 NC

ic
PCIE0 LAN Follow AT Define ok_0610
S5 S4 PCIE1 WLAN
AC Only O O X X X PCIE2/SATA0 SATA HDD

at
PCIE3/SATA1 N/A
2
S5 S4 PCIE/ PCIE4 N/A
2

Battery only O X X X X SATA

m
PCIE5 N/A
PCIE6 N/A
S5 S4 PCIE7 N/A

e
AC & Battery X X X X X PCIE8/SATA2

ch
don't exist PCIE9/SATA3
SSD
PCIE10
PCIE11

kS
SMBUS Control Table OK
Source
EC EC SMBus0 address PCH SML0 address PD I2C3 address
PCH

oo
IT8227C
Device Address Device Address Device Address
EC_SMB_0 EC_SMB_1 EC_SMB_3 EC_SMB_4 I2C0 I2C1 I2C2/SMBUS DGPU Re-Timer TBD Re-Timer TBD
Slave
+3VS +3VL_EC +3VL_EC +3VL_EC 1.8VS/3.3VS 1.8VS/3.3VS 1.8VS/3.3VS Thermal Sensor(NCT7718W)
eb
Thermal Sensor(NCT7719W) 1001_101xb
DGPU
TOF

Memory
X X X X X X X X EC SMBus1 address PCH SML1 address
ot

Down
3 Device Address Device Address 3

SODIMM V Smart Battery 0x16 PD TBD

3VS
N

Charger 0x12
BATT
X V X X X X X X
+3VL_EC

Charger
X V X X X X X X
+3VL_EC EC SMBus3 address PCH ISH I2C0 address
Device Address Device Address
WLAN
X X X X X X X X IMVP9 TOF

PMIC
X X V X X X X X
PMIC 0x34 Accelerometer(MB) 001 1000b
+3VL_EC Accelerometer(DB) 001 1001b
Light Sensor 1000 100xb
X X X X X X X X
EC SMBus4 address
Thermal V X X X X X X X Device Address
Sensor +3VS
PD TBD

LPC&TS
X X X X V
+3VS_CPU X X X
4 TP
X X X X X V X X 4

3VS
X X X X X X X X
X X X X X X X X
Security Classification LCFC Highly Confidential Information Title
S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Notes_PWR Map/SMBUS/HSIO
Date: Friday, December 04, 2020 Sheet 4 of 110
A B C D E
 5 4 3 2 1

To HDMI DDC

+3VS
RPC2
CPU_HDMI_DDC_CLK 1 4
UC1D CPU_HDMI_DDC_DATA 2 3

D11 A22 CPU_DP_ENBKL 2.2K_0404_4P2R_5%

47 CPU_EDP_TX0_P DP0_TXP0 DP_BLON
B11 D23 CPU_ENVDD
47 CPU_EDP_TX0_N DP0_TXN0 DP_DIGON
C23 CPU_EDP_PWM
DP_VARY_BL
C11
eDP 47 CPU_EDP_TX1_P
A11 DP0_TXP1
D12
47 CPU_EDP_TX1_N DP0_TXN1 DP0_AUXP CPU_EDP_AUX_P 47
B12
DP0_AUXN CPU_EDP_AUX_N 47
D D10 C12 D
DP0_TXP2 DP0_HPD CPU_EDP_HPD 47
B10
DP0_TXN2
J20 To EDP panel
DP1_AUXP CPU_HDMI_DDC_CLK 50
D9 K20
B9 DP0_TXP3 DP1_AUXN
L21 CPU_HDMI_DDC_DATA 50 HDMI
DP0_TXN3 DP1_HPD CPU_HDMI_HPD 50 +3VS
G23 L19
50 CPU_HDMI_TX2_P DP1_TXP0 DP2_AUXP
H23 M19
50 CPU_HDMI_TX2_N DP1_TXN0 DP2_AUXN
M20
DP2_HPD
F22 UC2 @
50 CPU_HDMI_TX1_P DP1_TXP1
G22 M14 1 5
50 CPU_HDMI_TX1_N DP1_TXN1 DP3_AUXP CPU_DP_ENBKL OE VCC
L14 2
HDMI

m
+1.8VALW DP3_AUXN A
G21 L16 3 4
50 CPU_HDMI_TX0_P DP1_TXP2 DP3_HPD GND Y EC_ENBKL 79
H21
50 CPU_HDMI_TX0_N DP1_TXN2
B23 CPU_DP_STEREOSYNC SN74LV1T125DCKR_SC70-5
CPU_RST_N DP_STEREOSYNC
RC94 1 2 4.7K_0402_5% F20
CPU_PW ROK 50 CPU_HDMI_CLK_P DP1_TXP3

co
RC95 1 2 4.7K_0402_5% G20
50 CPU_HDMI_CLK_N DP1_TXN3 CPU_DP_ENBKL EC_ENBKL
RC92 1 @ 2 0_0402_5%

2
+1.8VS RC93

s.
100K_0402_5%

RC97 1 @ 2 300_0402_5% CPU_PW ROK

1
RC98 2 1 1K_0402_5% CPU_DP_STEREOSYNC

ic
PD FOR CUSTOMER
PU FOR INTERNAL
BB6 CPU_TEST4 Test_Point_16MIL 1 @ TC1

at
TEST4
BD5 CPU_TEST5 Test_Point_16MIL 1 @ TC2 +1.8VS
TEST5
AG12 RPC100
TEST6 CPU_TEST15 1 8
C +3VS C
G25 CPU_TEST14 CPU_TEST17 2 7

em
TEST14
K25 CPU_TEST15 CPU_TEST14 3 6 LCD Power IC can change for PCH_ENVDD for cost down
TEST15
F25 CPU_TEST16 CPU_TEST16 4 5
CPU_THERMTRIP_N TEST16
RC328 2 1 1K_0402_5% F26 CPU_TEST17 +3VS
TEST17
10K_0804_8P4R_5% UC3
H26 CPU_TEST31 Test_Point_16MIL 1 @ TC4 @ 1 5
CPU_SID TEST31 CPU_ENVDD OE VCC
RPC102 8 1 2
CPU_SIC A
7 2 3 4

ch
CPU_ALERT_N GND Y ENVDD 47
6 3 AK9 CPU_TEST41 Test_Point_16MIL 1 @ TC5
CPU_PROCHOT_R_N TEST41
5 4
AP3 AK21 SN74LV1T125DCKR_SC70-5
24 CPU_TDI TDI ANALOGIO_0
1/16W _1K_5%_8P4R_0804 AU1 AG21 @
24 CPU_TDO TDO ANALOGIO_1
AR2

S
24 CPU_TCK TCK
AU3
24 CPU_TMS TMS
AR4
24 CPU_TRST_N TRST_L
AT2

ok
CPU_DP_STEREOSYNC 24 CPU_DBREQ_N DBREQ_L +0.75VS
RC112 2 @ 1 1K_0402_5% Follow CRB change to 196/1%
RC104 1 HDT@ 2 0_0402_5% 0201 to 0402,Because 0402 size no LBG symbol CPU_ENVDD RC298 1 @ 2 0_0402_5% ENVDD
24 CPU_RST_R_N
CC37 1 @2 56P_50V_J_NPO_0201 CPU_RST_N CPU_RST_N AW3 P3 SMU_ZVDDP RC105 1 2 196_0402_1%
RESET_L SMU_ZVDD
AW4
24,95 CPU_PW ROK PWROK
CC38 1 @2 56P_50V_J_NPO_0201 CPU_PW ROK
2 0_0402_5% CPU_SIC

bo
RC106 1 @ B22
77,79 EC_SMB_CK0 SIC
CC40 1 2 27P_25V_J_NPO_0201 CPU_SVC 1 2 0_0402_5% CPU_SID D22
@

77,79 EC_SMB_DA0 RC107 @

CPU_ALERT_N SID
C22 AK7 VDDP_S5_SENSE
ALERT_L VDDP_S5_SENSE
CC41 1 2 27P_25V_J_NPO_0201 CPU_SVD AN9 AK12 CPU_VDDP_RUN_FB_H 1 @
@

TC8
79 CPU_THERMTRIP_N THERMTRIP_L VDDP_SENSE
RC108 1 @ 2 0_0402_5% CPU_PROCHOT_R_N B25 J23 VDDCR_SOC_VCC_SENSE
79 CPU_PROCHOT_N PROCHOT_L VDDCR_SOC_SENSE VDDCR_SOC_VCC_SENSE 95
CC42 1 2 27P_25V_J_NPO_0201 CPU_SVT K22 VDDCR_VCC_SENSE
@

VDDCR_SENSE VDDCR_VCC_SENSE 95

e
J21
VDDIO_MEM_S3_SENSE
RC109 1 @ 2 0_0402_5% CPU_SVC_R D25
95 CPU_SVC SVC0
RC110 1 @ 2 0_0402_5% CPU_SVD_R C25 J22 VDDCR_VSS_SENSE

ot
95 CPU_SVD SVD0 VSS_SENSE_A VDDCR_VSS_SENSE 95
RC111 1 @ 2 0_0402_5% CPU_SVT_R A25 FP6 REV0.92 AJ12 VSS_SENSEB 1 @
95 CPU_SVT SVT0 PART 3/13 VSS_SENSE_B
CRB reserve SVC SVD 27pf TC9
B B
AMD-RENOIR-FP6_BGA1140 VDDCR_SOC_VCC_SENSE 1 @ TC10
VDDCR_VCC_SENSE 1 @ TC11
N @
VDDP_S5_SENSE
VDDCR_VSS_SENSE
1 @
1 @
TC12
TC13
+1.8VS +3VS
UC4
1 5
OE VCC
2

CPU_EDP_PWM 2
A
RC330 3 4
GND Y PANEL_PW M 47

2
39.2_0402_1%
@ RC103
100K_0402_5% SN74LV1T125DCKR_SC70-5
1

CPU_TEST31
M_TEST CONNECTION TBD

1
2

RC331
39.2_0402_1%
@
1

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(1/16):(DDI/EDP/TBT)
Date: Friday, December 04, 2020 Sheet 7 of 110
5 4 3 2 1
 5 4 3 2 1

D D

UC1B

DDRA_MA0 AK26
25 DDRA_MA0 DDRA_MA1 MA_ADD0/RSVD DDRA_DQ0
AG24 K27
25 DDRA_MA1 DDRA_MA2 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 DDRA_DQ1 DDRA_DQ0 25
AG23 L26
25 DDRA_MA2 DDRA_MA3 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 DDRA_DQ2 DDRA_DQ1 25
AG26 N26
25 DDRA_MA3 DDRA_MA4 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 DDRA_DQ3 DDRA_DQ2 25
AG27 N27
25 DDRA_MA4 DDRA_MA5 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 DDRA_DQ4 DDRA_DQ3 25
AF21 G27
25 DDRA_MA5 DDRA_MA6 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 DDRA_DQ5 DDRA_DQ4 25

m
AF22 H27
25 DDRA_MA6 DDRA_MA7 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 DDRA_DQ6 DDRA_DQ5 25
AF25 M27
25 DDRA_MA7 DDRA_MA8 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 DDRA_DQ7 DDRA_DQ6 25
AF24 N24
25 DDRA_MA8 DDRA_MA9 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 DDRA_DQ7 25
AE21
25 DDRA_MA9 DDRA_MA10 MA_ADD9/RSVD DDRA_DQ8
AL21 L23
25 DDRA_MA10 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 DDRA_DQ8 25

co
DDRA_MA11 AF27 N21 DDRA_DQ9
25 DDRA_MA11 DDRA_MA12 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 DDRA_DQ10 DDRA_DQ9 25
AE23 T21
25 DDRA_MA12 DDRA_MA13 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 DDRA_DQ11 DDRA_DQ10 25
AM23 T22
25 DDRA_MA13 DDRA_MA14_WE_N MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 DDRA_DQ12 DDRA_DQ11 25
AM21 M22
25 DDRA_MA14_WE_N DDRA_MA15_CAS_N MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 DDRA_DQ13 DDRA_DQ12 25
AL27 L24
25 DDRA_MA15_CAS_N DDRA_MA16_RAS_N MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 DDRA_DQ14 DDRA_DQ13 25
AL24 R21
25 DDRA_MA16_RAS_N MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 DDRA_DQ15 DDRA_DQ14 25

s.
R23
MA_DATA15/MAA_DATA3 DDRA_DQ15 25
DDRA_BA0 AL22 P24 DDRA_DQ16
25 DDRA_BA0 DDRA_BA1 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 DDRA_DQ17 DDRA_DQ16 25
AK27 R26
25 DDRA_BA1 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 DDRA_DQ18 DDRA_DQ17 25

ic
T27
DDRA_BG0 MA_DATA18/MAA_DATA21 DDRA_DQ19 DDRA_DQ18 25
AE27 V27
25 DDRA_BG0 DDRA_BG1 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 DDRA_DQ20 DDRA_DQ19 25
AE26 P25
25 DDRA_BG1 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 DDRA_DQ21 DDRA_DQ20 25
P27
DDRA_ACT_N MA_DATA21/MAA_DATA18 DDRA_DQ22 DDRA_DQ21 25
AD22 V23

at
25 DDRA_ACT_N MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 DDRA_DQ23 DDRA_DQ22 25
T25
DDRA_MA_DM0 MA_DATA23/MAA_DATA22 DDRA_DQ23 25
L27
25 DDRA_MA_DM0 DDRA_MA_DM1 MA_DM0/MAA_DM1 DDRA_DQ24
C N23 W22 C
25 DDRA_MA_DM1 DDRA_MA_DM2 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 DDRA_DQ25 DDRA_DQ24 25
R27 Y23
25 DDRA_MA_DM2 DDRA_MA_DM3 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 DDRA_DQ26 DDRA_DQ25 25
Y24 AC24

m
25 DDRA_MA_DM3 DDRA_MA_DM4 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 DDRA_DQ27 DDRA_DQ26 25
AP27 AC23
25 DDRA_MA_DM4 DDRA_MA_DM5 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 DDRA_DQ28 DDRA_DQ27 25
AW23 V21
25 DDRA_MA_DM5 DDRA_MA_DM6 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 DDRA_DQ29 DDRA_DQ28 25
AT21 W21
25 DDRA_MA_DM6 DDRA_MA_DM7 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 DDRA_DQ30 DDRA_DQ29 25
AV18 AA24
25 DDRA_MA_DM7 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 DDRA_DQ31 DDRA_DQ30 25
W24 AA22

e
MA_DM8/RSVD_52 MA_DATA31/MAA_DATA25 DDRA_DQ31 25
DDRA_DQS0_P M25 AP26 DDRA_DQ32
25 DDRA_DQS0_P DDRA_DQS0_N MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 DDRA_DQ33 DDRA_DQ32 25
M24 AN24

ch
25 DDRA_DQS0_N DDRA_DQS1_P MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 DDRA_DQ34 DDRA_DQ33 25
P22 AR25
25 DDRA_DQS1_P DDRA_DQS1_N MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 DDRA_DQ35 DDRA_DQ34 25
P21 AU26
25 DDRA_DQS1_N DDRA_DQS2_P MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 DDRA_DQ36 DDRA_DQ35 25
T24 AN25
25 DDRA_DQS2_P DDRA_DQS2_N MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 DDRA_DQ37 DDRA_DQ36 25
R24 AN27
25 DDRA_DQS2_N DDRA_DQS3_P MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 DDRA_DQ38 DDRA_DQ37 25
AA21 AR27
25 DDRA_DQS3_P DDRA_DQS3_N MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 DDRA_DQ39 DDRA_DQ38 25
Y21 AU27

kS
25 DDRA_DQS3_N DDRA_DQS4_P MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 DDRA_DQ39 25
AP23
25 DDRA_DQS4_P DDRA_DQS4_N MA_DQS_H4/MAB_DQS_H2 DDRA_DQ40
AP24 AV25
25 DDRA_DQS4_N DDRA_DQS5_P MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 DDRA_DQ41 DDRA_DQ40 25
AW22 AW25
25 DDRA_DQS5_P DDRA_DQS5_N MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 DDRA_DQ42 DDRA_DQ41 25
AV22 AV20
25 DDRA_DQS5_N DDRA_DQS6_P MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 DDRA_DQ43 DDRA_DQ42 25
AT20 AW20
25 DDRA_DQS6_P DDRA_DQS6_N MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 DDRA_DQ44 DDRA_DQ43 25
AR20 AV27
25 DDRA_DQS6_N MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 DDRA_DQ44 25

o
DDRA_DQS7_P AR18 AW26 DDRA_DQ45
25 DDRA_DQS7_P DDRA_DQS7_N MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 DDRA_DQ46 DDRA_DQ45 25
AT18 AU21
25 DDRA_DQS7_N MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 DDRA_DQ47 DDRA_DQ46 25
Y26 AW21
MA_DQS_H8/RSVD_58 MA_DATA47/MAB_DATA25 DDRA_DQ47 25
Y27

25 DDRA_CLK0_P
DDRA_CLK0_P
DDRA_CLK0_N
bo
AJ25
AJ24
MA_DQS_L8/RSVD_59

MA_CLK_H0/MAA_CKT
MA_DATA48/MAB_DATA11
MA_DATA49/MAB_DATA10
AT22
AP21
AN19
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ48
DDRA_DQ49
25
25
25 DDRA_CLK0_N DDRA_CLK1_P MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 DDRA_DQ51 DDRA_DQ50 25
AJ22 AN18
25 DDRA_CLK1_P DDRA_CLK1_N MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 DDRA_DQ52 DDRA_DQ51 25
AJ21 AU23
25 DDRA_CLK1_N MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDRA_DQ53 DDRA_DQ52 25
AR22
MA_DATA53/MAB_DATA13 DDRA_DQ53 25
e
AN20 DDRA_DQ54
MA_DATA54/MAB_DATA9 DDRA_DQ55 DDRA_DQ54 25
AP19
MA_DATA55/MAB_DATA8 DDRA_DQ55 25
DDRA_DQ56
ot

AT19
DDRA_CS0_N MA_DATA56/MAB_DATA6 DDRA_DQ57 DDRA_DQ56 25
AL25 AW18
B 25 DDRA_CS0_N DDRA_CS1_N MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 DDRA_DQ58 DDRA_DQ57 25 B
AM26 AU16
25 DDRA_CS1_N MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 DDRA_DQ59 DDRA_DQ58 25
AW16
MA_DATA59/MAB_DATA3 DDRA_DQ60 DDRA_DQ59 25
AW19
MA_DATA60/MAB_DATA4 DDRA_DQ61 DDRA_DQ60 25
AU19
N

MA_DATA61/MAB_DATA5 DDRA_DQ62 DDRA_DQ61 25

AP16
MA_DATA62/MAB_DATA1 DDRA_DQ63 DDRA_DQ62 25
AT16
DDRA_CKE0 MA_DATA63/MAB_DATA0 DDRA_DQ63 25
AD24
25 DDRA_CKE0 DDRA_CKE1 MA_CKE0/MAA_CA1
AD25 W27
25 DDRA_CKE1 MA_CKE1/MAA_CA0 MA_CHECK0/RSVD_54
W25
MA_CHECK1/RSVD_53
AC26
MA_CHECK2/RSVD_68
AC27
DDRA_ODT0 MA_CHECK3/RSVD_69
AM24 V26
25 DDRA_ODT0 DDRA_ODT1 MA_ODT0/MAB_CA3 MA_CHECK4/RSVD_49
AM27 V24
25 DDRA_ODT1 MA_ODT1/MAB_CA4 MA_CHECK5/RSVD_48
AA27
MA_CHECK6/RSVD_63
+1.2V AA25
MA_CHECK7/RSVD_62
+1.2V
DDRA_ALERT_N AE24
25 DDRA_ALERT_N MA_ALERT_L/TEST31A DDRA_PAR
AK24
MA_PAROUT/RSVD DDRA_PAR 25
RC113 2 1 1K_0201_5% DDRA_EVENT_N AK23
DDR4_A_DRAMRST_N MA_EVENT_L
AD27 AN21
25 DDR4_A_DRAMRST_N MA_RESET_L M_DDR4
FP6 REV0.92 AN22
PART 1/13 M_LPDDR4

25 DDRA_EVENT_N
AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(2/16):(DDR4-Chanel-A)
Date: Friday, December 04, 2020 Sheet 8 of 110
5 4 3 2 1
 5 4 3 2 1

D D

UC1C

DDRB_MA0 AM29
26 DDRB_MA0 DDRB_MA1 MB_ADD0/RSVD DDRB_DQ0
AH31 C27
26 DDRB_MA1 DDRB_MA2 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 DDRB_DQ1 DDRB_DQ0 26
AJ30 A28
26 DDRB_MA2 DDRB_MA3 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 DDRB_DQ2 DDRB_DQ1 26
AH29 F29
26 DDRB_MA3 DDRB_MA4 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 DDRB_DQ3 DDRB_DQ2 26
AG32 F31
26 DDRB_MA4 DDRB_MA5 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 DDRB_DQ4 DDRB_DQ3 26
AG30 B27
26 DDRB_MA5 DDRB_MA6 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 DDRB_DQ5 DDRB_DQ4 26
AG31 D27
26 DDRB_MA6 DDRB_MA7 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 DDRB_DQ6 DDRB_DQ5 26
AF30 E32
26 DDRB_MA7 DDRB_MA8 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 DDRB_DQ7 DDRB_DQ6 26
AG29 F30
26 DDRB_MA8 DDRB_MA9 MB_ADD8/RSVD MB_DATA7/MBA_DATA14 DDRB_DQ7 26
AF29

m
26 DDRB_MA9 DDRB_MA10 MB_ADD9/RSVD DDRB_DQ8
AM30 H31
26 DDRB_MA10 DDRB_MA11 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 DDRB_DQ9 DDRB_DQ8 26
AF31 H30
26 DDRB_MA11 DDRB_MA12 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 DDRB_DQ10 DDRB_DQ9 26
AE32 K31
26 DDRB_MA12 DDRB_MA13 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 DDRB_DQ11 DDRB_DQ10 26
AP30 L30
26 DDRB_MA13 DDRB_MA14_WE_N MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDRB_DQ12 DDRB_DQ11 26
AP31 G30

co
26 DDRB_MA14_WE_N DDRB_MA15_CAS_N MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 DDRB_DQ13 DDRB_DQ12 26
AP29 H29
26 DDRB_MA15_CAS_N DDRB_MA16_RAS_N MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 DDRB_DQ14 DDRB_DQ13 26
AN29 K30
26 DDRB_MA16_RAS_N MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 DDRB_DQ15 DDRB_DQ14 26
K29
MB_DATA15/MBA_DATA3 DDRB_DQ15 26
DDRB_BA0 AN31 N32 DDRB_DQ16
26 DDRB_BA0 DDRB_BA1 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 DDRB_DQ17 DDRB_DQ16 26
AM32 N29

s.
26 DDRB_BA1 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 DDRB_DQ18 DDRB_DQ17 26
P30
DDRB_BG0 MB_DATA18/MBA_DATA20 DDRB_DQ19 DDRB_DQ18 26
AD29 L32
26 DDRB_BG0 DDRB_BG1 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 DDRB_DQ20 DDRB_DQ19 26
AD31 L31
26 DDRB_BG1 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 DDRB_DQ21 DDRB_DQ20 26
M30

ic
DDRB_ACT_N MB_DATA21/MBA_DATA16 DDRB_DQ22 DDRB_DQ21 26
AD30 L29
26 DDRB_ACT_N MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 DDRB_DQ23 DDRB_DQ22 26
N31
DDRB_MB_DM0 MB_DATA23/MBA_DATA23 DDRB_DQ23 26
C30
26 DDRB_MB_DM0 DDRB_MB_DM1 MB_DM0/MBA_DM1 DDRB_DQ24
H32 R30
26 DDRB_MB_DM1 DDRB_DQ24 26

at
DDRB_MB_DM2 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 DDRB_DQ25
M29 R32
26 DDRB_MB_DM2 DDRB_MB_DM3 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 DDRB_DQ26 DDRB_DQ25 26
T29 V30
26 DDRB_MB_DM3 DDRB_MB_DM4 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 DDRB_DQ27 DDRB_DQ26 26
C AU30 V32 C
26 DDRB_MB_DM4 DDRB_MB_DM5 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 DDRB_DQ28 DDRB_DQ27 26
BD28 P29
26 DDRB_MB_DM5 DDRB_MB_DM6 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 DDRB_DQ29 DDRB_DQ28 26
BB23 P31
26 DDRB_MB_DM6 DDRB_MB_DM7 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 DDRB_DQ30 DDRB_DQ29 26

em
BD20 U31
26 DDRB_MB_DM7 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 DDRB_DQ31 DDRB_DQ30 26
W31 U29
MB_DM8/RSVD_57 MB_DATA31/MBA_DATA24 DDRB_DQ31 26
DDRB_DQS0_P E29 AT29 DDRB_DQ32
26 DDRB_DQS0_P DDRB_DQS0_N MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 DDRB_DQ33 DDRB_DQ32 26
D28 AU32
26 DDRB_DQS0_N DDRB_DQS1_P MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 DDRB_DQ34 DDRB_DQ33 26
J31 AW31
26 DDRB_DQS1_P DDRB_DQS1_N MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 DDRB_DQ35 DDRB_DQ34 26
J29 AW30
26 DDRB_DQS1_N DDRB_DQS2_P MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 DDRB_DQ36 DDRB_DQ35 26
N30 AR30
26 DDRB_DQS2_P DDRB_DQS2_N MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 DDRB_DQ37 DDRB_DQ36 26
M31 AT31

ch
26 DDRB_DQS2_N DDRB_DQS3_P MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 DDRB_DQ38 DDRB_DQ37 26
T30 AV30
26 DDRB_DQS3_P DDRB_DQS3_N MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 DDRB_DQ39 DDRB_DQ38 26
T31 AW29
26 DDRB_DQS3_N DDRB_DQS4_P MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22 DDRB_DQ39 26
AU29
26 DDRB_DQS4_P DDRB_DQS4_N MB_DQS_H4/MBB_DQS_H2 DDRB_DQ40
AU31 AY29
26 DDRB_DQS4_N DDRB_DQS5_P MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 DDRB_DQ41 DDRB_DQ40 26
BA27 AY32
26 DDRB_DQS5_P DDRB_DQS5_N MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 DDRB_DQ42 DDRB_DQ41 26
BB27 BC27

kS
26 DDRB_DQS5_N DDRB_DQS6_P MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 DDRB_DQ43 DDRB_DQ42 26
BC23 BB26
26 DDRB_DQS6_P DDRB_DQS6_N MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 DDRB_DQ44 DDRB_DQ43 26
BA23 BC25
26 DDRB_DQS6_N DDRB_DQS7_P MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 DDRB_DQ45 DDRB_DQ44 26
BC20 BA25
26 DDRB_DQS7_P DDRB_DQS7_N MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 DDRB_DQ46 DDRB_DQ45 26
BA20 BB30
26 DDRB_DQS7_N MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 DDRB_DQ47 DDRB_DQ46 26
Y32 BA28
MB_DQS_H8/RSVD_61 MB_DATA47/MBB_DATA31 DDRB_DQ47 26
Y30

oo
MB_DQS_L8/RSVD_60 DDRB_DQ48
BA24
DDRB_CLK0_P MB_DATA48/MBB_DATA11 DDRB_DQ49 DDRB_DQ48 26
AJ31 BC24
26 DDRB_CLK0_P DDRB_CLK0_N MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDRB_DQ50 DDRB_DQ49 26
AK30 BC22
26 DDRB_CLK0_N MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 DDRB_DQ51 DDRB_DQ50 26
AK32 BA22
MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 DDRB_DQ52 DDRB_DQ51 26
AL31 BB25
MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 DDRB_DQ53 DDRB_DQ52 26
BD25
MB_DATA53/MBB_DATA13 DDRB_DQ54 DDRB_DQ53 26
BB22
eb
MB_DATA54/MBB_DATA9 DDRB_DQ55 DDRB_DQ54 26
BD22
MB_DATA55/MBB_DATA8 DDRB_DQ55 26
BA21 DDRB_DQ56
DDRB_CS0_N MB_DATA56/MBB_DATA4 DDRB_DQ57 DDRB_DQ56 26
AN30 BC21
26 DDRB_CS0_N MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 DDRB_DQ58 DDRB_DQ57 26
AR31 BC18
MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 DDRB_DQ59 DDRB_DQ58 26
BB18
DDRB_DQ59 26
ot

MB_DATA59/MBB_DATA3 DDRB_DQ60
BB20
B MB_DATA60/MBB_DATA6 DDRB_DQ61 DDRB_DQ60 26 B
BB21
MB_DATA61/MBB_DATA7 DDRB_DQ62 DDRB_DQ61 26
BB19
MB_DATA62/MBB_DATA1 DDRB_DQ63 DDRB_DQ62 26
BA18
DDRB_CKE0 MB_DATA63/MBB_DATA0 DDRB_DQ63 26
AC31
26 DDRB_CKE0 MB_CKE0/MBA_CA1
AC29 W30
N

MB_CKE1/MBA_CA0 MB_CHECK0/RSVD_56
W29
MB_CHECK1/RSVD_55
AA30
MB_CHECK2/RSVD_65
AB29
DDRB_ODT0 MB_CHECK3/RSVD_67
AP32 V29
26 DDRB_ODT0 MB_ODT0/MBB_CA3 MB_CHECK4/RSVD_50
AR29 V31
MB_ODT1/MBB_CA4 MB_CHECK5/RSVD_51
AA29
MB_CHECK6/RSVD_64
AA31
+1.2V MB_CHECK7/RSVD_66
DDRB_ALERT_N AE30
26 DDRB_ALERT_N MB_ALERT_L/TEST31B DDRB_PAR
AM31
DDR_B_EVENT_N MB_PAROUT/RSVD DDRB_PAR 26
RC114 1 2 1K_0402_5% AL30
DDR4_B_DRAMRST_N MB_EVENT_L
AC32 FP6 REV0.92
26 DDR4_B_DRAMRST_N MB_RESET_L PART 9/13

AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(3/16):(DDR4-Chanel-B)
Date: Friday, December 04, 2020 Sheet 9 of 110
5 4 3 2 1
 5 4 3 2 1

STRAP PINS SYS_RESET#

1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
PCH_SPI_CLK 0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
GENERATE INTERNAL CLOCKS ONLY
RC131 1 2 33_0402_5% CPU_LPC_RST_R_N
24,79 CPU_LPC_RST_N
D 1:NORMAL RESET MODE(DEFAULT) D
1

2
CC44
150P_25V_J_NPO_0402 SYS_RESET# 0:SHORT RESET MODE

+3VS_CPU +1.8VS +1.8VALW

+3VALW_CPU
RPC132 1 4 SSD_CLKREQ4_N
WLAN_CLKREQ1_N

2
2 3

2
RC137 RC144
10K_0404_4P2R_5% RC143 10K_0402_5% 10K_0402_5%

m
10K_0201_5%
LAN_CLKREQ_N

1
RC339 1 LAN@ 2 10K_0402_5%
@

1
SPI_CLK
12 SYS_RESET_N
UC1F

co
REQ2 LAN_CLKREQ_N -------> ID4

1
REQ5 ID4-------->LAN_CLKRE_N
RC139 RC146
Michael Modify_0727 AR13 @ 2K_0201_1% @ 2K_0201_1%
WLAN_CLKREQ1_N AP10 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
REQ1:WLAN REQ1 71 WLAN_CLKREQ1_N CLK_REQ1_L/AGPIO115
AR15
12 BOARD_ID4

2
CLK_REQ2_L/AGPIO116

s.
AT14
12 BOARD_ID5 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
AN11
63 SSD_CLKREQ4_N LAN_CLKREQ_N CLK_REQ4_L/OSCIN/EGPIO132
REQ4:SSD REQ4 AN13
78 LAN_CLKREQ_N AN15 CLK_REQ5_L/EGPIO120
REQ5 12 BOARD_ID2 CLK_REQ6_L/EGPIO121

ic
REQ5:LAN FP_RESETN
AW14 RC340 1 @ 2 0_0402_5%
EGPIO70 FP_RESETN_R 65
BB13 CPU_LPCPD_N 24
AF11 LPC_PD_L/AGPIO21
BA16 CPU_LPC_AD0 RC147 1 2 10_0402_5% LPC_ESPI_IO0 24,79
AF12 GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104
BA15 CPU_LPC_AD1 RC148 1 2 10_0402_5% +3VS_CPU

at
GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 LPC_ESPI_IO1 24,79
BC13 CPU_LPC_AD2 RC149 1 2 10_0402_5% LPC_ESPI_IO2 24,79
RC141 1 @ 2 0_0402_5% CLK_PCIE_WLAN_P AG4 LAD2/ESPI1_DATA2/EGPIO106
BB14 CPU_LPC_AD3 RC150 1 2 10_0402_5% LPC_ESPI_CS_N RC158 1 @ 2 10K_0402_5%
71 CLK_PCIE_WLAN_R_P CLK_PCIE_WLAN_N GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 CPU_LPCCLK0 LPC_ESPI_IO3 24,79 KBRST_N
CLK1 WLAN RC152 1 @ 2 0_0402_5% AG2 BB15 RC153 2 1 1/16W_3.3_1%_0402 LPC_ESPI_CLK 24,79 RC160 1 @ 2 10K_0402_5%
71 CLK_PCIE_WLAN_R_N GPP_CLK1N LPCCLK0/EGPIO74
BD13 CPU_LPC_CLKRUN_N RC154 1 LPC@ 2 0_0402_5% LPC_CLKRUN_N 24
C AG3 LPC_CLKRUN_L/AGPIO88
BA12 CPU_WLAN_OFF_R_N RC427 1 @ 2 10_0402_5% LDRQ0_N RC162 1 2 10K_0402_5% C

em
AG1 GPP_CLK2P LPCCLK1/EGPIO75
BC15 SERIRQ CPU_WLAN_OFF_N 12,71
GPP_CLK2N SERIRQ/AGPIO87 SERIRQ 24,79 change CPU_WLAN_OFF_N CPU_UART0_RXD
BA13 LPC_ESPI_CS_N 24,79 EGPIO75 to AGPIO89_0921 SIT RC165 1 @ 2 10K_0402_5%
AF2 LFRAME_L/EGPIO109 CPU_UART0_TXD RC166 1 @ 2 10K_0402_5%
AF4 GPP_CLK3P
BC12 CPU_LPC_RST_R_N CPU_TOUCH_EN RC304 1 @ 2 10K_0402_5%
GPP_CLK3N LPC_RST_L/AGPIO32
AU12 CPU_TOUCH_EN_R RC303 1 @ 2 0_0402_5% TOUCH_PANEL_RST_N_R RC306 1 @ 2 10K_0402_5%
RC163 1 @ 2 0_0402_5% CLK_PCIE_SSD_P AH2 AGPIO68
AP4 CPU_TOUCH_EN 47,79
63 CLK_PCIE_SSD_R_P CLK_PCIE_SSD_N GPP_CLK4P LPC_PME_L/AGPIO22 EC_PCH_SCI_N 79 EC Control TS_EN_0813
CLK4 SSD RC164 1 @ 2 0_0402_5% AH4
63 CLK_PCIE_SSD_R_N GPP_CLK4N

ch
CLK_PCIE_LAN_P RC337 1 @ 2 0_0402_5% CLK_LAN_P AJ2
78 CLK_PCIE_LAN_P CLK_PCIE_LAN_N 1 2 0_0402_5% CLK_LAN_N AJ4 GPP_CLK5P
BA11 CPU_EGPIO67 1 @ +1.8VALW
CLK5 LAN RC338 @ TC15
78 CLK_PCIE_LAN_N GPP_CLK5N SPI_ROM_REQ/EGPIO67
BB11
SPI_ROM_GNT/EGPIO76
AF8
GPP_CLK6P/WIFIBT_CLKP
AF9 AT15 KBRST_N 79
+3VS +3VALW_CPU GPP_CLK6N/WIFIBT_CLKN ESPI_RESET_L/KBRST_L/AGPIO129
BC11 CPU_SPI_TPM_CS_N RC178 1 @ 2 10K_0402_5%
LDRQ0_N 24

kS
ESPI_ALERT_L/LDRQ0_L/EGPIO108
TC16 1 Test_Point_16MIL 48M_OSC AK1
X48M_OSC CPU_SPI_CLK_R CPU_SPI_CLK
BC10 RC173 1 2 10_0402_5%
SPI_CLK/ESPI_CLK
BA10 CPU_SPI_D1_R RC174 1 @ 2 0_0402_5% +3VALW_CPU
X48M_X1 SPI_DI/ESPI_DATA CPU_SPI_D0_R CPU_SPI_D1 27,79
1

BB3 BB8 RC176 1 @ 2 0_0402_5%

RC194 RC196 X48M_X1 SPI_DO
BA9 CPU_SPI_D2_R RC177 1 @ 2 0_0402_5% CPU_SPI_D0 27,79
0_0402_5% 0_0402_5% SPI_WP_L/ESPI_DAT2
BC8 CPU_SPI_D3_R RC179 1 @ 2 0_0402_5% CPU_SPI_D2 27 EC_PCH_SCI_N RC183 1 @ 2 10K_0402_5%
SPI_HOLD_L/ESPI_DAT3
BD11 CPU_SPI_CS1_R_N RC180 1 @ 2 0_0402_5% CPU_SPI_D3 27

oo
X48M_X2 BA5 SPI_CS1_L
BC9 BOARD_ID3 CPU_SPI_CS1_N 27,79
BOARD_ID3 12
2

X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30
BB10
@ @ SPI_CS3_L/AGPIO31 CPU_SPI_TPM_CS_N +1.8VALW_SPI
BD8
SPI_TPM_CS_L/AGPIO29
UC5_PWR

CPU_SPI_CS1_N RC335 1 2 10K_0402_5%

RSVD_71 AG10 CPU_SPI_D1 RC336 1 2 10K_0402_5%

eb
RSVD_70 AG9 RSVD_71
2 RSVD_70
CC53 RC185 SUS CLK Follow S750 Confirm no Need
0.1U_6.3V_K_X5R_0201 CPU_SPI_D2 RC186 1 @ 2 10K_0402_5%
RC185 1 @ 2 0_0402_5% RTCCLK AW10 CPU_SPI_D3 RC187 1 @ 2 10K_0402_5%
1 63,71 SUSCLK_32K RTCCLK
@ UC5
5 1 X32K_X1 AY1 BA17 CPU_UART0_RXD

ot
Vcc OE X32K_X1 EGPIO141/UART0_RXD
BC16 CPU_UART0_TXD
EGPIO143/UART0_TXD CPU_SPI_TPM_CS_N
2 RTCCLK BD15 BOARD_ID1 12 CC45 1 2 22P_0201_25V8
IN_A EGPIO142/UART0_RTS_L/UART1_RXD
RC189 BC17 @
B SUSCLK_32K 4 3 1 2 X32K_X2 AY4 EGPIO140/UART0_CTS_L/UART1_TXD
BB16 TOUCH_PANEL_RST_N_R RC305 1 @ 2 0_0402_5% CPU_LPC_RST_N RC190 2 1 100K_0402_5% B
OUT_Y GND
20M_0402_5% X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR TOUCH_PANEL_RST_N 47
YC1
N FP6 REV0.92
PART 5/13
M74VHC1GT125DF2G_SC70-5 1 2
@
32.768KHZ_9PF_X1A000141000200 AMD-RENOIR-FP6_BGA1140
1 1 @ RSVD_71 RC192 1 @ 2 0_0402_5%
CC46 CC47 RSVD_70 RC193 1 @ 2 0_0402_5%
9P_50V_B_NPO_0402 9P_50V_B_NPO_0402
2 2 LPC_ESPI_CLK CC49 1 2 22P_0201_25V8
RF_NS@
KBRST_N CC50 2 1 150P_25V_J_COG_0201
EMC_NS@
CPU_LPCCLK0 1EMC_NS@ 2 LPCCLK0_N CC51 1 2 22P_0201_25V8
RC197 0_0402_5% EMC_NS@
48MHz/10pF Crystal X48M_X1 SPI_CLK 1 SPI_CLK_RC CC52 1
2 EMC_NS@ 2 10P_0201_25V8G
+3VALW_CPU RC198 10_0402_5% EMC_NS@
X48M_X2

2
RC199 1 2 1M_0402_5%
YC2
CPU_SPI_CLK 3 1 SPI_CLK 27,79
1 4
OSC1 NC2

2 3 QC5 LSI1012XT1G_SC-89-3
NC1 OSC2
RC195 1 @ 2 0_0201_5%
1 1
48MHZ_10PF_7V48000017
CC54 CC55
5.6P_50V_C_NPO_0402 5.6P_50V_C_NPO_0402
2 2

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(5/16):SPI/ESPI/SMB/CL
Date: Friday, December 04, 2020 Sheet 11 of 110
5 4 3 2 1
 5 4 3 2 1

+3VS

+3VS_CPU
CPU_WAKE_N RC345 1 LAN@ 2 0_0402_5% EC_WAKE_N 78,79
CPU_I2C0_SCL_R RPC295 1 4 CPU_I2C1_SCL_R RPC201 1 4
CPU_I2C0_SDA_R 2 3 CPU_I2C1_SDA_R 2 3
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%
V14V15 For LAN EC to APU
Note: RC345 Can't Modify 0R +3VS_CPU
CPU_I2C2_SCL_R RPC203 1 4
SYS_RESET_N DC4 1 @ 2 RB521CM-30T2R_VMN2M-2 CPU_PWR_GOOD UC1E CPU_I2C2_SDA_R 2 3
AM3 0~2=> 1.8VS or 3.3VS 2.2K_0404_4P2R_5%
SFH_IPIO271
AT4 I2C3=>1.8ALW or 3.3VALW
D SFH_IPIO272 D
AM1
SFH_IPIO273
AJ8 TOUCH_PANEL_INTR_R_N RC313 1 TS@ 2 10K_0402_5%
SFH_IPIO274
AW7 EC_PCH_SMI_N RC317 1 2 10K_0201_5%
SFH_IPIO39
AU2
CPU_PLT_RST_N AP6 SFH_IPIO41
CPU_PLT_RST1_N AT13 PCIE_RST0_L/EGPIO26
AP14 CPU_I2C0_SCL_R RC124 1 @ 2 0_0402_5%
CPU_RSMRST_N CPU_I2C0_SCL 24,47
AR8 PCIE_RST1_L/EGPIO27 I2C0_SCL/EGPIO145
AN14 CPU_I2C0_SDA_R RC125 1 @ 2 0_0402_5% For LPC and touch panel
RSMRST_L I2C0_SDA/EGPIO146 CPU_I2C0_SDA 24,47
RC218 1 @ 2 0_0402_5% PBTN_OUT_R_N AT12 AP2 CPU_I2C1_SCL_R RC216 1 @ 2 0_0402_5% +3VALW_CPU
79 PBTN_OUT_N CPU_I2C1_SCL 83
RC219 1 @ 2 0_0402_5% CPU_PWR_GOOD AW2 PWR_BTN_L/AGPIO0 I2C1_SCL/EGPIO147
AN3 CPU_I2C1_SDA_R RC220 1 @ 2 0_0402_5% For Touchpad
79 EC_SYS_PWROK PWR_GOOD I2C1_SDA/EGPIO148 CPU_I2C1_SDA 83
AL2
11 SYS_RESET_N CPU_WAKE_N AW12 SYS_RESET_L/AGPIO1
AN12 CPU_I2C2_SCL_R RC222 1 @ 2 0_0402_5% CPU_I2C3_SCL RPC213 1 4
WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SMBUS0_I2C_SCL
AP12 CPU_I2C2_SDA_R 1 2 0_0402_5% SMB_CLK_S1 25 CPU_I2C3_SDA 2 3
RC224 @ For SODIMM_A Channel
I2C2_SDA/EGPIO114/SMBUS0_I2C_SDA SMB_DATA_S1 25
RC226 1 @ 2 0_0402_5% CPU_PM_SLP_S3_N AT11 @ 2.2K_0404_4P2R_5%

m
79 PM_SLP_S3_N RC228 1 @ 2 0_0402_5%CPU_PM_SLP_S5_N AV11 SLP_S3_L
AM9 CPU_I2C3_SCL_R RC229 1 @ 2 0_0402_5% CPU_I2C3_SCL
24,79 PM_SLP_S5_N SLP_S5_L I2C3_SCL/AGPIO19/SMBUS1_I2C_SCL
AM10 CPU_I2C3_SDA_R RC230 1 @ 2 0_0402_5% CPU_I2C3_SDA CPU_WAKE_N RC334 1 LAN@ 2 10K_0201_5%
AW13 I2C3_SDA/AGPIO20/SMBUS1_I2C_SDA Reserved 2.2k pull +3VALW PBTN_OUT_N RC333 1 2 10K_0201_5%
S0A3_GPIO/AGPIO10
D24 CPU_SFH1_SCL
SFH1_SCL CPU_SFH1_SDA
BA8 B24
79 AC_PRESENT

co
CPU_LOW_BAT_N AV6 AC_PRES/AGPIO23 SFH1_SDA CPU_SATA_DEVSLP2 RC223 1 @ 2 10K_0402_5%
LLB_L/AGPIO12 AC_PRESENT RC225 1 2 10K_0402_5%
BB7 CPU_SSD_RST_N RC227 1 @ 2 10K_0402_5%
BOARD_ID8 AW8 AGPIO3
BA6 CPU_SSD_SATA_PCIE_DET1_N 1RC235 @ 2 0_0402_5% CPU_LOW_BAT_N RC231 1 @ 2 10K_0402_5%
EGPIO42 AGPIO4/SATAE_IFDET SSD_SATA_PCIE_DET1_N 63 CPU_PWR_GOOD RC233 1 @ 2 10K_0402_5%
ADD Reserved Board_ID8_SIT0928 AK10 CPU_SATA_DEVSLP2_R RC238 1 @ 2 0_0402_5% CPU_PM_SLP_S3_N RC318 1 @ 2 2.2K_0402_5%
AGPIO5/DEVSLP0
BC6 NUM_LED_N CPU_SATA_DEVSLP2 63 CPU_PM_SLP_S5_N

s.
NUM_LED_N 79,81 RC319 1 @ 2 2.2K_0402_5%
AGPIO6/DEVSLP1
AW15 BOARD_ID0 CAPS_LED_N RC332 1 @ 2 10K_0201_5%
SATA_ACT_L/AGPIO130 CPU_SFH1_SCL RC236 1 @ 2 4.7K_0402_5%
AG6 AU4 PCH_TP_INT_R_N RC320 1 @ 2 0_0402_5% PCH_TP_INT_N 79,83
CPU_SFH1_SDA RC237 1 @ 2 4.7K_0402_5%
ACP_WOV_CLK AGPIO9
AP7 CPU_SSD_RST_R_N

ic
AG7 RC244 1 @ 2 0_0402_5%
AJ6 ACP_WOV_MIC0_MIC1_DATA AGPIO40
AV13 CPU_SSD_RST_N 63 PCH_TP_INT_N RC294 1 @ 2 10K_0201_5%
ACP_WOV_MIC2_MIC3_DATA AGPIO69
BB12 PCH_SMI_N RC434 1 @ 2 0_0402_5%
For EMI CPU_HDA_BITCLK
CPU_HDA_BITCLK AN6 AGPIO86/SPI_CLK2 EC_PCH_SMI_N 79
AZ_BITCLK/TDM_BCLK_MIC
1 RC300 1 @ 2 0_0402_5% CPU_HDA_SDIN0_R AL6 CPU_RSMRST_N RC251 2 @ 1 100K_0402_5%

at
66 HDA_SDIN0 CPU_HDA_SDIN1 AZ_SDIN0/CODEC_GPI CPU_PWR_GOOD
TC17 @ 1 Test_Point_16MIL CPU_HDA_SDIN2
AM7 AU7 RC252 2 1 100K_0402_5%
CC27 @ 1 Test_Point_16MIL AJ9 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT
AR11 CPU_BEEP_R RC248 1 @ 2 0_0402_5% CPU_PLT_RST1_N RC321 1 @ 2 10K_0402_5%
TC18 CPU_HDA_RST_N CPU_BEEP 66
56P_50V_J_NPO_0201 AM6 AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK/ACP_WOV_MIC4_MIC5_DATA SPKR/AGPIO91
AW11 CAPS_LED_R_N RC301 1 @ 2 0_0402_5% HDA_BITCLK_AUDIO CC56 1 2 33P_50V_J_NPO_0201
2 EMC_NS@ CPU_HDA_SYNC AN8 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11 CAPS_LED_N 79,81 EMC_NS@
C C
CPU_HDA_SDOUT AZ_SYNC/TDM_FRM_MIC
AK6 AV15 TOUCH_PANEL_INTR_R_N RC432 1 @ 2 0_0402_5% TOUCH_PANEL_INTR_N 47
CPU_PWR_GOOD CC57 1 2 0.1u_0201_10V6K
Close to PCH

m
AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89
AU14 APU_WLAN_OFF_R_N RC431 1 @ 2 0_0402_5% AGPIO89: Change TOUCH_PANEL_INTR_N to AGPIO89 PIN
SYS_RESET_N CC58 1@ 2 1U_0402_6.3V6K
AM4 GENINT2_L/AGPIO90 CPU_WLAN_OFF_N 11,71
SW_MCLK/TDM_BCLK_BT AGPIO90: Change CPU_WLAN_OFF_N to AGPIO90 PIN PM_SLP_S3_N
AL3 CC59 1@ 2 2200P_25V_K_X7R_0201
RPC259 BOARD_ID7 AM2 SW_DATA0/TDM_DOUT_BT
AT10 PCH_SMI_N1 RC433 1 @ 2 0_0201_5% EC_PCH_SMI_N PM_SLP_S5_N CC60 1@ 2 2200P_25V_K_X7R_0201
BOARD_ID6 AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84
AL4 FP6 REV0.92 AU10 CPU_BT_OFF_R_N RC309 1 @ 2 0_0402_5%
CPU_BT_OFF_N 71

he
1 8 CPU_HDA_SYNC AGPIO8/FCH_ACP_I2S_LRCLK_BT PART 4/13 FANOUT0/AGPIO85
66 HDA_SYNC_AUDIO CPU_HDA_RST_N
@ 1Test_Point_16MIL 2 7
TC70 CPU_HDA_BITCLK
3 6 AMD-RENOIR-FP6_BGA1140
66 HDA_BITCLK_AUDIO 4 5 CPU_HDA_SDOUT
66 HDA_SDOUT_AUDIO @
1/16W_33_5%_8P4R_0804 ADD Reserved Board_ID8_SIT0924
+3VS +1.8VALW Follow S550_ARE

c
+3VALW_CPU

kS
+3VALW_CPU
+3VS

RC261 1 2 1/20W_33_5%_0201 CPU_PLT_RST_N

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
63,71,78 PLT_RST_N

2
For Memory

RC263

RC264

RC265

RC266

RC429
oo
2

1 1 S14S15@

@
RC262 CC61
@
CC25
150P_25V_J_NPO_0402 BOARD_ID4,5 Follow S750
100K_0402_5%

10K_0402_5%

10K_0402_5%
USE S750 Reserved ID

1
2

1
100P_0402_50V8J @ @ @ @
2 2 RC424 RC170 BOARD_ID0 BOARD_ID8

RC322

RC323
1

17@ TS@ 10K_0402_5% 10K_0402_5% 11 BOARD_ID1

Reserved cc25 Follow L350_ARH, Solve With lan ,PLT Test glitch_0803 FP@

eb
11 BOARD_ID2
V14V15@
11 BOARD_ID3

2
11 BOARD_ID4
11 BOARD_ID5
BOARD_ID6

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
AGPIO8 +3VALW : ID6

ot
BOARD_ID7

RC272

RC273

RC274

RC275

RC430
B B
AGPIO7 +3VLAW: ID7
+3VL 10K_0402_5%

10K_0402_5%

10K_0402_5%
2

1
2
+1.8VALW RC426 RC171 @ @ @ @ @

RC326

RC327
N
2

@ 1415@ NOTS@ NOFP@ 10K_0402_5%

RC269 S360@
10U 6.3V M X5R 0402

1/20W_1M_1%_0201 1

1
2

CC63

1
RC270
1

RC271 1 @ 2 0_0402_5% 10K_0402_5%

2
Board ID[0,1,2,3] Memory Stuff R
1

1 2 CPU_RSMRST_N
79 EC_RSMRST_N_R IDO AGPIO130 S0_3.3V
@ DC5 1
RB521CM-30T2R_VMN2M-2 CC65 0000 Samsung 4G
3

RC272,RC273,RC274,RC275
0.1U_6.3V_K_X5R_0201 0 14"15" RC326
2 ID4 AGPIO116 S0_3.3V ID1 EGPIO142 S0_3.3V
1 Board ID[4] 0001 Samsung 8G RC272,RC273,RC274,RC266
@ QC6 1 17"
2

LSK3541G1ET2L_VMT3
ID5 EGPIO131 S0_3.3V 0010 SMART 4GB RC272,RC273,RC265,RC275 ID2 EGPIO121 S0_3.3V
0 NOTS@
Board ID[5]
0111 Micron 4G RC272,RC264,RC265,RC266
ID6 AGPIO8 +3VALW 1 TS@ ID3 AGPIO30 +1.8VALW
0101 Micron 8G RC272,RC264,RC274,RC266
0 NOFP@
ID7 AGPIO7 +3VALW Board ID[6]
0110 Reserved RC272,RC264,RC265,RC275
1 FP@
ID8 EGPIO42 S5_3.3V
1000 Hynix 4G RC263,RC273,RC274,RC275
0 S360@
Board ID[7]
1001 Hynix 8G RC263,RC273,RC274,RC266 DDP?
1 V14V15@
A A
1010 Reserved RC263,RC273,RC265,RC275 Hynix SDP 8GB
0
Board ID[8]
1111 DIMM_ONLY
1 S14S15@

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(6/16:I2C/ISH/UART/GPIO
Date: Friday, December 04, 2020 Sheet 12 of 110
5 4 3 2 1

10 Reserved RC263,RC273,RC265,RC275
 5 4 3 2 1

UC1A

F4 G13
P_GFX_TXP0 P_GFX_RXP0
F2 F13
P_GFX_TXN0 P_GFX_RXN0

F3 J14
P_GFX_TXP1 P_GFX_RXP1
E4 H14
P_GFX_TXN1 P_GFX_RXN1

E1 G15
P_GFX_TXP2 P_GFX_RXP2
C1 F15
P_GFX_TXN2 P_GFX_RXN2

D5 J15
P_GFX_TXP3 P_GFX_RXP3
E6 K15
P_GFX_TXN3 P_GFX_RXN3

D
C6 H16 D
P_GFX_TXP4 P_GFX_RXP4
D6 J16
P_GFX_TXN4 P_GFX_RXN4

B6 F18
P_GFX_TXP5 P_GFX_RXP5
C7 G18
P_GFX_TXN5 P_GFX_RXN5

D8 J18
P_GFX_TXP6 P_GFX_RXP6
B8 K18
P_GFX_TXN6 P_GFX_RXN6

C8 H19
P_GFX_TXP7 P_GFX_RXP7
A8 G19
P_GFX_TXN7 P_GFX_RXN7

LAN@
V14V15 78 PCIE_PTX_C_DRX0_P
PCIE_PTX_C_DRX0_P
PCIE_PTX_C_DRX0_N
CC911
CC912
2
2
1 0.1U_6.3V_K_X5R_0201
1 0.1U_6.3V_K_X5R_0201
PCIE_PTX_DRX0_P
PCIE_PTX_DRX0_N
L3
L1 P_GPP_TXP0 P_GPP_RXP0
G11
F11
PCIE_PRX_DTX0_P
PCIE_PRX_DTX0_N PCIE_PRX_DTX0_P 78
LAN

m
78 PCIE_PTX_C_DRX0_N P_GPP_TXN0 P_GPP_RXN0 PCIE_PRX_DTX0_N 78
LAN LAN@
L4 J10

WLAN
71
71
PCIE_CTX_DRX1_P
PCIE_CTX_DRX1_N
SATA_PTX_DRX0_P
L2 P_GPP_TXP1
P_GPP_TXN1
P_GPP_RXP1
P_GPP_RXN1
H10

SATA_PRX_DTX0_P
PCIE_CRX_DTX1_P
PCIE_CRX_DTX1_N
71
71 WLAN
M4 G8
HDD

co
61 SATA_PTX_DRX0_P SATA_PTX_DRX0_N P_GPP_TXP2/SATA0_TXP P_GPP_RXP2/SATA0_RXP SATA_PRX_DTX0_N SATA_PRX_DTX0_P 61
M2 F8
HDD 61 SATA_PTX_DRX0_N
N3
P_GPP_TXN2/SATA0_TXN

P_GPP_TXP3/SATA1_TXP
P_GPP_RXN2/SATA0_RXN

P_GPP_RXP3/SATA1_RXP
G6
SATA_PRX_DTX0_N 61

N1 F7
P_GPP_TXN3/SATA1_TXN P_GPP_RXN3/SATA1_RXN

s.
T2 M9
P_GPP_TXP4 P_GPP_RXP4
T4 M8
P_GPP_TXN4 P_GPP_RXN4

ic
R1 L7
P_GPP_TXP5 P_GPP_RXP5
R3 L6
P_GPP_TXN5 P_GPP_RXN5

P2 K7

at
P_GPP_TXP6 P_GPP_RXP6
P4 K8
P_GPP_TXN6 P_GPP_RXN6

C
N2 H6 C
P_GPP_TXP7 P_GPP_RXP7
N4 H7
P_GPP_TXN7 P_GPP_RXN7

m
K2 L9
63 PCIE_CTX_DRX8_P P_GPP_TXP8/SATA2_TXP P_GPP_RXP8/SATA2_RXP PCIE_CRX_DTX8_P 63
K4 L10
63 PCIE_CTX_DRX8_N P_GPP_TXN8/SATA2_TXN P_GPP_RXN8/SATA2_RXN PCIE_CRX_DTX8_N 63

he
J4 K11
63 PCIE_CTX_DRX9_P P_GPP_TXP9/SATA3_TXP P_GPP_RXP9/SATA3_RXP PCIE_CRX_DTX9_P 63
J2 J11

SSD
63

63
PCIE_CTX_DRX9_N

PCIE_CTX_DRX10_P
H3
P_GPP_TXN9/SATA3_TXN

P_GPP_TXP10
P_GPP_RXN9/SATA3_RXN

P_GPP_RXP10
J12
PCIE_CRX_DTX9_N

PCIE_CRX_DTX10_P
63

63
SSD
H1 H12
63 PCIE_CTX_DRX10_N P_GPP_TXN10 P_GPP_RXN10 PCIE_CRX_DTX10_N 63

Sc
H4 J13
63 PCIE_CTX_DRX11_P P_GPP_TXP11 P_GPP_RXP11 PCIE_CRX_DTX11_P 63
H2 K13
63 PCIE_CTX_DRX11_N P_GPP_TXN11 P_GPP_RXN11 PCIE_CRX_DTX11_N 63
FP6 REV0.92
PART 2/13

AMD-RENOIR-FP6_BGA1140

k
@

oo UC1H
eb
AC6 AA1
52 USB20_0_P USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2 USBC0_TX1_P 52
USB20 P0 For Type-C USB 2.0 port AC7 AA3
52 USB20_0_N USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2 USBC0_TX1_N 52
AA8 AA2
57 USB20_1_P USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3 USBC0_RX1_P 52
USB20 P1 For USB3.0 Port AA9 AA4
57 USB20_1_N USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3 USBC0_RX1_N 52
ot

B
USB20 P2 For camera 47
47
USB20_2_P
USB20_2_N
Y10
Y9 USB2_DP
USB2_DN
USBC0_TX2P/DP2_TXP1
USBC0_TX2N/DP2_TXN1
AC2
AC4
TYPE C 1 B

Y7 AC1
USB3_DP USBC0_RX2P/DP2_TXP0
Y6 AC3
N

USB3_DN USBC0_RX2N/DP2_TXN0

AE1
USB1_TXP
AE3 USB30_TX1_P 57
USB20 P4 I/O USB2.0 AC9 USB1_TXN USB30_TX1_N 57
78
78
USB20_4_P
USB20_4_N
AC10 USBC4_DP/USB4_DP
USBC4_DN/USB4_DN USB1_RXP
USB1_RXN
AD8
AD9
USB30_RX1_P
USB30_RX1_N
57
57
TYPE A charge function
AA11
78 USB20_5_P USB5_DP
IO Board for Card reader AA12
78 USB20_5_N USB5_DN
S360 USB P5 Note: RC347/348 Can't modify 0R
W8
65 USB20_6_P USB6_DP
W9 V3
65 USB20_6_N USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2
USB P6 Finger print V1
USBC4_TX1N/USB4_TXN/DP3_TXN2
W11
71 USB20_7_P USB7_DP
USB P7 BT W12 U4
71 USB20_7_N USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3
U2
+1.8VALW USBC4_RX1N/USB4_RXN/DP3_TXN3
USBC_I2C_SCL AL9 W2
USBC_I2C_SCL USBC4_TX2P/DP3_TXP1
W4
USBC_I2C_SDA USBC4_TX2N/DP3_TXN1
RP3 @ AL8
USBC_I2C_SCL USBC_I2C_SDA
4 1 SVT_change RC341 Stuff to unstuff_1202 W1
USBC_I2C_SDA USBC4_RX2P/DP3_TXP0
3 2 0_0402_5% W3
TYPEC_OCP_N USBC4_RX2N/DP3_TXN0
OC0 Type-c RC341 1 @ 2 TYPEC_OCP_R_N AE9
52 TYPEC_OCP_N USB_OC0_L/AGPIO16
4.7K_0404_4P2R_5% OC1 USB20 AE10 AD2
58 USB_OC1_N USB_OC1_L/AGPIO17 USB5_TXP
OC2 USB30 AE6 AD4
57 USB_OC2_N USB_OC2_L/AGPIO18 USB5_TXN
AE7
81 KB_FN_LED_N USB_OC3_L/AGPIO24
AD12
USB5_RXP
AD11
USB5_RXN

FP6 REV0.92
+3VALW_CPU PART 10/13
A RPC279 A
AMD-RENOIR-FP6_BGA1140
1 4 USB_OC2_N
@
2 3 USB_OC1_N

10K_0404_4P2R_5%
RC302 2 @ 1 10K_0402_5% KB_FN_LED_N

RC342 2 1 10K_0402_5% TYPEC_OCP_R_N

Security Classification LCFC Highly Confidential Information Title
S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
SVT_change RC342 Pull up to RC341 PIN1 to PIN2, AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(8/16): PCIE/USB/SATA
Date: Friday, December 04, 2020 Sheet 14 of 110
5 4 3 2 1
 5 4 3 2 1

D D

om
UC1I

UC1G
D21 A18
CAM0_CSI2_CLOCKP CAM0_CLK

c
A20
CAM0_CSI2_CLOCKN
N7 P8 C18

s.
AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK CAM0_I2C_SCL
R7 R9 D18 B17
AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS CAM0_CSI2_DATAP0 CAM0_I2C_SDA
N6 R6 B18
AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA CAM0_CSI2_DATAN0
T6 D17

ic
AGPIO259/WIFIBT_BT_CLK CAM0_SHUTDOWN
C19
CAM0_CSI2_DATAP1
D20
CAM0_CSI2_DATAN1

at
R10 P9 C21
AGPIO260/WIFIBT_QSPI_DATA0 AGPIO270/WIFIBT_RFIC_WAKEUP CAM0_CSI2_DATAP2
T12 T9 B21
C AGPIO261/WIFIBT_QSPI_DATA1 EGPIO271/WIFIBT_BUCKEN CAM0_CSI2_DATAN2 C
P12 T8

em
AGPIO262/WIFIBT_QSPI_DATA2 EGPIO266/WIFIBT_FLOW
P11 C20
AGPIO263/WIFIBT_QSPI_DATA3 CAM0_CSI2_DATAP3
T11 B20
AGPIO264/WIFIBT_QSPI_CLK CAM0_CSI2_DATAN3
P6
AGPIO265/WIFIBT_QSPI_SS
V7 C15 A13
WIFIBT_DATA_RXP CAM1_CSI2_CLOCKP CAM1_CLK
V6 A15

ch
WIFIBT_DATA_RXN CAM1_CSI2_CLOCKN
B13
CAM1_I2C_SCL
V9 D16 D13
WIFIBT_DATA_TXP CAM1_CSI2_DATAP0 CAM1_I2C_SDA
V10 B16
WIFIBT_DATA_TXN CAM1_CSI2_DATAN0
C14

kS
CAM1_SHUTDOWN
FP6 REV0.92 D15
PART 12/13 CAM1_CSI2_DATAP1
B15 C16
CAM1_CSI2_DATAN1 CAM_PRIV_LED
FP6 REV0.92 C13
PART 13/13 CAM_IR_ILLU
AMD-RENOIR-FP6_BGA1140

oo
@
AMD-RENOIR-FP6_BGA1140
@

eb
B
ot B
N

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
CPU(9/16): CSI-2/CNVI 0.3

Date: Friday, December 04, 2020 Sheet 15 of 110

5 4 3 2 1
 5 4 3 2 1

+1.8VS
+1.8VALW

+3VS +3VS_CPU Delete 22U 0603 and place PWR portion under SOC
D +VDDCR_CPU D
CC72 CC73 CC74 CC75 CC76 CC77 RC329 1 @ 2 0_0603_SP
22UC_6.3VC_MC_X5RC_0603

1 BU 1 BO 1 1 BU 1 BO 1 All BU(on bottom side under SOC)

UC1J
TDC 44A
TDC 13A

22U_4V_M_X5R_0402
EDC 70A Need discuss if space enough ,reserves others component
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@

@
BO
2 BO 2 2 2 2 2 EDC 17A N16
VDDCR_SOC_1 VDDCR_1
G7
N18 G10
VDDCR_SOC_2 VDDCR_2
N20 G12
VDDCR_SOC_3 VDDCR_3
P17 G14

m
VDDCR_SOC_4 VDDCR_4
P19 H8
VDDCR_SOC_5 VDDCR_5 +VDDCR_CPU
R18 H11
VDDCR_SOC_6 VDDCR_6
R20 H15
VDDCR_SOC_7 VDDCR_7
T19 K6

o
VDDCR_SOC_8 VDDCR_8
U18 K12
VDDCR_SOC_9 VDDCR_9
U20 K14
+1.8VALW +1.8VS VDDCR_SOC_10 VDDCR_10

c
V19 L8 1
+3VALW_CPU VDDCR_SOC_11 VDDCR_11
W18 M7

s.
+3VS_CPU +1.2V VDDCR_SOC_12 VDDCR_12
W20 M10 CC79
VDDCR_SOC_13 VDDCR_13
Y19 N14 180P_50V_J_NPO_0402
VDDCR_SOC_14 VDDCR_14
P7 2
VDDCR_15
P10
VDDCR_16

2
CC84 CC80 CC81 CC83 CC86 CC87 P13
6A VDDCR_17

c
RC280 P15
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1 1 BO 1 Rongfu Request
BO VDDCR_18
BU BU @ 0_0402_5% AC20 R8

ti
VDDIO_MEM_S3_1 VDDCR_19 All BU(on bottom side under SOC)
BO AC28 R14
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDIO_MEM_S3_2 VDDCR_20
AD23 R16
@

@
BO
2 2 2 2 2 2

1
VDDIO_MEM_S3_3 VDDCR_21
AD26 T7
+VDDCR_SOC VDDIO_MEM_S3_4 VDDCR_22
AD28 T10
VDDIO_MEM_S3_5 VDDCR_23
AD32 T13

a
RC281 1 @ 2 +VDDIO_AZ AE20 VDDIO_MEM_S3_6 VDDCR_24
T15
VDDIO_MEM_S3_7 VDDCR_25
0_0402_5% CC89 AE22 T17
VDDIO_MEM_S3_8 VDDCR_26
1 CC88 AE25 U14

22U_4V_M_X5R_0402
1

1U_0402_6.3V6K
VDDIO_MEM_S3_9 VDDCR_27 +VDDCR_SOC
BO AE28 U16
VDDIO_MEM_S3_10 VDDCR_28
AF23 V13

em
VDDIO_MEM_S3_11 VDDCR_29
BU change to BO AF26 V15
2 2 AF28 VDDIO_MEM_S3_12 VDDCR_30
V17
VDDIO_MEM_S3_13 VDDCR_31
AF32 W7
VDDIO_MEM_S3_14 VDDCR_32
C AG20 W10 C
+0.75VALW VDDIO_MEM_S3_15 VDDCR_33
AG22 W14 1 1
VDDIO_MEM_S3_16 VDDCR_34
AG25 W16
VDDIO_MEM_S3_17 VDDCR_35

ch
AG28 Y8 CC90 CC91
VDDIO_MEM_S3_18 VDDCR_36
AJ20 Y13 1U_0402_6.3V6K 180P_50V_J_NPO_0402
AJ23 VDDIO_MEM_S3_19 VDDCR_37
Y15 2 2
VDDIO_MEM_S3_20 VDDCR_38
AJ26 Y17
VDDIO_MEM_S3_21 VDDCR_39
AJ28 AA7
VDDIO_MEM_S3_22 VDDCR_40
CC92 CC93 CC94 CC95 AJ32 AA10
AK22 VDDIO_MEM_S3_23 VDDCR_41
AA14 All BU(on bottom side under SOC)

S
1 1 1 1 VDDIO_MEM_S3_24 VDDCR_42
BO BU BU BU AK25 AA16
VDDIO_MEM_S3_25 VDDCR_43
@ AK28 AA18
22U_4V_M_X5R_0402

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VDDIO_MEM_S3_26 VDDCR_44
AL23 AB13
@

k
2 2 2 2 AL26 VDDIO_MEM_S3_27 VDDCR_45
AB15
VDDIO_MEM_S3_28 VDDCR_46
AL28 AB17
VDDIO_MEM_S3_29 VDDCR_47
AL32 AB19

oo
VDDIO_MEM_S3_30 VDDCR_48
AM22 AC14
VDDIO_MEM_S3_31 VDDCR_49
AM25 AC16
VDDIO_MEM_S3_32 VDDCR_50
AM28 AC18
VDDIO_MEM_S3_33 VDDCR_51
AN28 AD7
+0.75VS +0.75VALW +3VALW_CPU +1.8VALW +1.8VS +3VS_CPU +1.2V AN32 VDDIO_MEM_S3_34 VDDCR_52
AD10
VDDIO_MEM_S3_35 VDDCR_53
AP28 AD13
VDDIO_MEM_S3_36 VDDCR_54
AR32 AD15
1A

b
VDDIO_MEM_S3_37 VDDCR_55 +1.2V
AD17 FP6 VDDIO_MEM_S3 change 9BU to 7BU REV0.81
VDDCR_56
AC21 AD19 FP6 VDDIO_MEM_S3 change 7BU to 9BU REV0.82
VDDIO_VPH_1 VDDCR_57
AD21 AE8
2A 2A 0.25A 0.5A 2A 0.25A

e
VDDIO_VPH_2 VDDCR_58
AE14
+VDDIO_AZ 0.2A AP9 VDDCR_59
AE16 CC97 CC98 CC99 CC100 CC101 CC102 CC103 CC104 CC105 CC133 CC107 CC108

ot
VDDIO_AUDIO VDDCR_60
AE18
VDDCR_61
AL18 AF7
VDD_33_1 VDDCR_62
AM17 AF10 1 1 1 1 1 1 1 1 1 1 1 1

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402
VDD_33_2 VDDCR_63
AF13

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_0402_6.3V6K

1U_0402_6.3V6K
VDDCR_64

180P_50V_J_NPO_0402
AL20 AF15
VDD_18_1 VDDCR_65
AM19 AF17 @ @ @
VDD_18_2 VDDCR_66
AF19 2 2 2 2 2 2 2 2 2 2 2 2
VDDCR_67
AL19 AG14

N
VDD_18_S5_1 VDDCR_68
AM18 AG16
VDD_18_S5_2 VDDCR_69
AG18
B VDDCR_70 B
AL17 AH13
VDD_33_S5_1 VDDCR_71
AM16 AH15 @ @
VDD_33_S5_2 VDDCR_72
AH17
VDDCR_73
AL11 AH19
VDDP_S5_1 VDDCR_74
AL12 AJ7
VDDP_S5_2 VDDCR_75
AM12 AJ10
VDDP_S5_3 VDDCR_76
AJ14
VDDCR_77
M15 AJ16 All BU(on bottom side under SOC)
VDDP_1 VDDCR_78
M16 AJ18
VDDP_2 VDDCR_79 +1.2V
+RTC_LDO +3V_RTC M18
VDDP_3 VDDCR_80
AK13
AK15
VDDCR_81 +1.2V
AK17 DECOUPLING BETWEEN PROCESSOR AND DIMMs
VDDCR_82
AK19 ACROSS VDDIO AND VSS SPLIT
VDDCR_83
1K_0402_5% 2 1 RC283 AJ11
VDDBT_RTC_G
CC132 CC106
0.1A FP6 REV0.92
1

JCMOS1 PART 6/13 CC111 CC112 CC113 CC114 CC115 CC116

@ 1 1 CC134 CC135 CC136
AMD-RENOIR-FP6_BGA1140 1 1 1 1 1

22U_4V_M_X5R_0402

22U_4V_M_X5R_0402
2

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
SHORT PADS CC109 CC110 @ 1 1 1 1 1 1
1U_0402_6.3V6K 0.22U_6.3V_K_X5R_0201
2 2 @ @ @
2 2 2 2 2

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

2 2 2 2 2 2

+0.75VS BU change to BO BU change to BO

CC117 CC118 CC119 CC120 CC121 CC122 CC123 CC124 CC125 CC126 CC127
1 1 1 1 1 1 1 @ 1 1 1 1
22U_4V_M_X5R_0402

22UC_6.3VC_MC_X5RC_0603

BO BO BU BU BU BU BO BO BO BO BU All BU(on bottom side under SOC)

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_50V_J_NPO_0402

4x0.22UF (0402)+2x180PF(0402)
2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(13/16): CPU Power(2/2)
Date: Friday, December 04, 2020 Sheet 18 of 110
5 4 3 2 1
 5 4 3 2 1

D D

UC1M

UC1K UC1L V5 AE13

VSS_122 VSS_184
V8 AE15
VSS_123 VSS_185
AM20 K28 AR14 BD19 V11 AE17
VSS_310 VSS_60 VSS_246 VSS_305 VSS_124 VSS_186
A3 K32 AR16 BD21 V14 AE19
VSS_1 VSS_61 VSS_247 VSS_306 VSS_125 VSS_187
A5 L5 AR19 BD23 V16 AF1

m
VSS_2 VSS_62 VSS_248 VSS_307 VSS_126 VSS_188
A7 L13 AR21 BD26 V18 AF3
VSS_3 VSS_63 VSS_249 VSS_308 VSS_127 VSS_189
A10 L15 AR26 BD30 V20 AF5
VSS_4 VSS_64 VSS_250 VSS_309 VSS_128 VSS_190
A12 L18 AR28 V22 AF14
VSS_5 VSS_65 VSS_251 VSS_129 VSS_191
A14 L20 AT23 V25 AF16

co
VSS_6 VSS_66 VSS_252 VSS_130 VSS_192
A16 L25 AU5 V28 AF18
VSS_7 VSS_67 VSS_253 VSS_131 VSS_193
A19 L28 AU8 W5 AF20
VSS_8 VSS_68 VSS_254 VSS_132 VSS_194
A21 M1 AU11 W13 AG5
VSS_9 VSS_69 VSS_255 VSS_133 VSS_195
A23 M3 AU13 W15 AG8
VSS_10 VSS_70 VSS_256 VSS_134 VSS_196
A26 M5 AU15 W17 AG11
VSS_11 VSS_71 VSS_257 VSS_135 VSS_197

s.
A30 M21 AU18 AV8 W19 AG13
VSS_12 VSS_72 VSS_258 RSVD_46 VSS_136 VSS_198
C3 M23 AU20 BD18 W23 AG15
VSS_13 VSS_73 VSS_259 RSVD_47 VSS_137 VSS_199
C10 M26 AU22 AV3 W26 AG17
VSS_14 VSS_74 VSS_260 RSVD_45 VSS_138 VSS_200
C32 M28 AU25 AU6 W28 AG19

ic
VSS_15 VSS_75 VSS_261 RSVD_44 VSS_139 VSS_201
E7 M32 AU28 AR6 W32 AH14
VSS_16 VSS_76 VSS_262 RSVD_43 VSS_140 VSS_202
E8 N5 AV1 AR3 Y1 AH16
VSS_17 VSS_77 VSS_263 RSVD_42 VSS_141 VSS_203
E10 N8 AV5 AP1 Y3 AH18
VSS_18 VSS_78 VSS_264 RSVD_41 VSS_142 VSS_204
E11 N11 AV7 AN16 Y5 AH20

at
VSS_19 VSS_79 VSS_265 RSVD_40 VSS_143 VSS_205
E12 N13 AV10 AN4 Y11 AJ1
VSS_20 VSS_80 VSS_266 RSVD_39 VSS_144 VSS_206
E13 N15 AV12 AN2 Y14 AJ3
C VSS_21 VSS_81 VSS_267 RSVD_38 VSS_145 VSS_207 C
E14 N17 AV14 AM14 Y16 AJ5
VSS_22 VSS_82 VSS_268 RSVD_37 VSS_146 VSS_208
E15 N22 AV16 AM13 Y18 AJ13
VSS_23 VSS_83 VSS_269 RSVD_36 VSS_147 VSS_209

em
E16 N25 AV19 AL29 Y20 AJ15
VSS_24 VSS_84 VSS_270 RSVD_35 VSS_148 VSS_210
E18 N28 AV21 AL15 Y22 AJ17
VSS_25 VSS_85 VSS_271 RSVD_34 VSS_149 VSS_211
E19 P1 AV23 AL14 Y25 AJ19
VSS_26 VSS_86 VSS_272 RSVD_33 VSS_150 VSS_212
E20 P5 AV26 AL13 Y28 AK5
VSS_27 VSS_87 VSS_273 RSVD_32 VSS_151 VSS_213
E21 P14 AV28 AK3 AA5 AK8
VSS_28 VSS_88 VSS_274 RSVD_31 VSS_152 VSS_214
E22 P16 AV32 AJ29 AA13 AK11
VSS_29 VSS_89 VSS_275 RSVD_30 VSS_153 VSS_215
E23 P18 AW5 AJ27 AA15 AK14
VSS_30 VSS_90 VSS_276 RSVD_29 VSS_154 VSS_216

ch
E25 P20 AW28 AF6 AA17 AK16
VSS_31 VSS_91 VSS_277 RSVD_28 VSS_155 VSS_217
E26 P23 AY6 AE12 AA19 AK18
VSS_32 VSS_92 VSS_278 RSVD_27 VSS_156 VSS_218
E27 P26 AY7 AD6 AA23 AK20
VSS_33 VSS_93 VSS_279 RSVD_26 VSS_157 VSS_219
F5 P28 AY8 AD3 AA26 AL1
VSS_34 VSS_94 VSS_280 RSVD_25 VSS_158 VSS_220
F19 P32 AY10 AC30 AA28 AL5
VSS_35 VSS_95 VSS_281 RSVD_24 VSS_159 VSS_221
F21 R5 AY11 AC12 AA32 AL7

kS
VSS_36 VSS_96 VSS_282 RSVD_23 VSS_160 VSS_222
F23 R11 AY12 AB31 AB2 AL10
VSS_37 VSS_97 VSS_283 RSVD_22 VSS_161 VSS_223
F28 R13 AY13 AA20 AB4 AL16
VSS_38 VSS_98 VSS_284 RSVD_21 VSS_162 VSS_224
G1 R15 AY14 AA6 AB14 AM5
VSS_39 VSS_99 VSS_285 RSVD_20 VSS_163 VSS_225
G3 R17 AY15 Y12 AB16 AM8
VSS_40 VSS_100 VSS_286 RSVD_19 VSS_164 VSS_226
G5 R19 AY16 W6 AB18 AM11

oo
VSS_41 VSS_101 VSS_287 RSVD_18 VSS_165 VSS_227
G16 R22 AY18 V12 AB20 AM15
VSS_42 VSS_102 VSS_288 RSVD_17 VSS_166 VSS_228
G26 R25 AY19 R12 AC5 AN1
VSS_43 VSS_103 VSS_289 RSVD_16 VSS_167 VSS_229
G28 R28 AY20 N19 AC8 AN5
VSS_44 VSS_104 VSS_290 RSVD_15 VSS_168 VSS_230
G32 T1 AY21 N12 AC11 AN7
VSS_45 VSS_105 VSS_291 RSVD_14 VSS_169 VSS_231
H5 T3 AY22 N10 AC13 AN10
VSS_46 VSS_106 VSS_292 RSVD_13 VSS_170 VSS_232
H13 T5 AY23 N9 AC15 AN23
eb
VSS_47 VSS_107 VSS_293 RSVD_12 VSS_171 VSS_233
H18 T14 AY25 M13 AC17 AN26
VSS_48 VSS_108 VSS_294 RSVD_11 VSS_172 VSS_234
H20 T16 AY26 M12 AC19 AP5
VSS_49 VSS_109 VSS_295 RSVD_10 VSS_173 VSS_235
H22 T18 AY27 M11 AC22 AP8
VSS_50 VSS_110 VSS_296 RSVD_9 VSS_174 VSS_236
H25 T20 BB1 M6 AC25 AP13
VSS_51 VSS_111 VSS_297 RSVD_8 VSS_175 VSS_237
H28 T23 BB32 L12 AD1 AP15
VSS_52 VSS_112 VSS_298 RSVD_7 VSS_176 VSS_238
J19 T26 BD3 K19 AD5 AP18
ot

VSS_53 VSS_113 VSS_299 RSVD_6 VSS_177 VSS_239

B K1 T28 BD7 F16 AD14 AP20 B
VSS_54 VSS_114 VSS_300 RSVD_5 VSS_178 VSS_240
K3 T32 BD10 F14 AD16 AP25
VSS_55 VSS_115 VSS_301 RSVD_4 VSS_179 VSS_241
K5 U13 BD12 F12 AD18 AR1
VSS_56 VSS_116 VSS_302 RSVD_3 VSS_180 VSS_242
K16 U15 BD14 F10 AD20 AR5
VSS_57 VSS_117 VSS_303 RSVD_2 VSS_181 VSS_243
N

K21 U17 BD16 C26 AE5 AR7

VSS_58 VSS_118 VSS_304 RSVD_1 VSS_182 VSS_244
K26 U19 AE11 AR12
VSS_59 VSS_119 VSS_183 VSS_245
V2
VSS_120
V4 FP6 REV0.92 FP6 REV0.92
VSS_121 PART 11/13 PART 8/13
FP6 REV0.92
PART 7/13 AMD-RENOIR-FP6_BGA1140
AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140 @
@ @

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CPU(15/16): GND
Date: Friday, December 04, 2020 Sheet 21 of 110
5 4 3 2 1
 5 4 3 2 1

LPC ROM EMULATOR HEADER

+3VALW_CPU +3VS_CPU

2
LPC@
LPC@ RC285
RC284 0_0201_5%
0_0402_5%

1
D D
Test_Point_32MIL TC23 1 @
11,79 LPC_ESPI_CLK
Test_Point_32MIL TC24 1 @
11,79 LPC_ESPI_CS_N LPC_RST_N
RC286 1 LPC@ 2 0_0201_5% Test_Point_32MIL TC25 1 @ @ 1 TC26 Test_Point_32MIL PM_SLP_S5_LPC_CON_N RC287 1 @ 2 0_0201_5%
11,79 CPU_LPC_RST_N PM_SLP_S5_N 12,79
Test_Point_32MIL TC27 1 @ @ 1 TC28 Test_Point_32MIL
11,79 LPC_ESPI_IO3 +3VS_CPU_LPC Test_Point_32MIL LPC_ESPI_IO2 11,79
TC29 1 @ @ 1 TC30 Test_Point_32MIL
LPC_ESPI_IO1 11,79
Test_Point_32MIL TC31 1 @
11,79 LPC_ESPI_IO0 SMB_CK0_LPC_CON
RC299 1 LPC@ 2 0_0201_5% Test_Point_32MIL TC32 1 @ @ 1 TC33 Test_Point_32MIL SMB_SDA0_LPC_CON RC289 1 LPC@ 2 0_0201_5%
12,47 CPU_I2C0_SCL +3ALW_CPU_LPC Test_Point_32MIL CPU_I2C0_SDA 12,47
TC34 1 @ @ 1 TC35 Test_Point_32MIL
SERIRQ 11,79
@ 1 TC36 Test_Point_32MIL
LPC_CLKRUN_N 11
Test_Point_32MIL TC37 1 @ @ 1 TC38 Test_Point_32MIL
11 CPU_LPCPD_N LDRQ0_N 11
1 1
CC128 CC129
0.1U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201
LPC@ 2 2 LPC@

m
+3VALW_CPU

co
RC290 1 LPC@ 2 10K_0201_5% CPU_LPCPD_N

+3VS_CPU

s.
RC291 1 @ 2 10K_0201_5% CPU_LPCPD_N
RC292 1 LPC@ 2 10K_0201_5% LPC_CLKRUN_N

2LPCCLK_CON1 LPC_ESPI_CLK

ic
CC130 1 @ 2 33_0402_5%
@ 15P_25V_J_NPO_0201 RC293

at
C C

m
c he
HDT Debug Header

kS
注意下这句话

oo RC3152 RC3153 should be put on APU side to reduce stub when MP

eb
+1.8VALW +1.8VALW

1
2
3
4

2
ot

B B
RPC294 RC295
1K_0201_5%
1/16W_1K_5%_8P4R_0804
HDT@ HDT@
8
7
6
5

1
N

+1.8VALW
New HDT conn
JHDT1
1
1
2
2
3
3 CPU_TCK 7
4
4 CPU_TMS 7
5
5 CPU_TDI 7
6
6 CPU_TDO 7
7
7 CPU_PWROK 7,95
8
8 CPU_DBREQ_R_N RC296 CPU_RST_R_N 7
9 1 HDT@ 2 33_0402_5%
9 CPU_TRST_R_N RC297 CPU_DBREQ_N 7
10 1 HDT@ 2 33_0402_5%
10 CPU_TRST_N 7
13 11
GND1 11
14 12 1
GND2 12
CC131
HIGHS_FC1AF121-1151H 0.01U_6.3V_K_X7R_0201
ME@ HDT@
2

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. XDP
Date: Friday, December 04, 2020 Sheet 24 of 110
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 8
DDRA_MA[0..13]
DDRA_MA[0..13] 8

DDRA_MA_DM[0..7]
DDRA_MA_DM[0..7] 8
Chage JDDR1 Symbol DC011412251 to SP011508260_Follow L340 API_0628 +1.2V +1.2V

JDDR1A JDDR1B
Swap Table
1 2 DDRA_MA3 131 132 DDRA_MA2
DDRA_DQ12 VSS_1 VSS_2 DDRA_DQ13 DDRA_MA1 A3 A2 DDRA_EVENT_N
3 4 133 134 Pin Name Net Name
DQ5 DQ4 A1 EVENT_n DDRA_EVENT_N 8
5 6 0~7 135 136
DDRA_DQ9 VSS_3 VSS_4 DDRA_DQ8 DDRA_CLK0_P VDD_9 VDD_10 DDRA_CLK1_P
7 8 137 138 DQ0 DDRA_DQ6
DQ1 DQ0 8 DDRA_CLK0_P DDRA_CLK0_N CK0_t CK1_t DDRA_CLK1_N DDRA_CLK1_P 8
9 10 139 140 DQ1 DDRA_DQ5
D
DDRA_DQS1_N VSS_5 VSS_6 DDRA_MA_DM1 8 DDRA_CLK0_N CK0_c CK1_c DDRA_CLK1_N 8 D
11 12 141 142
8 DDRA_DQS1_N DDRA_DQS1_P 13 DQS0_C DM0_n/DBIO_n/NC
14 DDRA_PAR 143 VDD_11 VDD_12
144 DDRA_MA0 DQ2 DDRA_DQ2
8 DDRA_DQS1_P DQS0_t VSS_7 DDRA_DQ10 8 DDRA_PAR Parity A0 DQ3 DDRA_DQ3
15 16
DDRA_DQ11 VSS_8 DQ6
17
DQ7 VSS_9
18 DQ4 DDRA_DQ4
19 20 DDRA_DQ14 DDRA_BA1 145 146 DDRA_MA10 DQ5 DDRA_DQ0
DDRA_DQ15 VSS_10 DQ2 8 DDRA_BA1 BA1 A10/AP
21 22 147 148 DQ6 DDRA_DQ1
DQ3 VSS_11 DDRA_DQ0 DDRA_CS0_N VDD_13 VDD_14 DDRA_BA0
23 24 149 150
DDRA_DQ4 25
VSS_12 DQ12
26 8 DDRA_CS0_N DDRA_MA14_WE_N 151
CS0_n BA0
152 DDRA_MA16_RAS_N DDRA_BA0 8 DQ7 DDRA_DQ7
DQ13 VSS_13 DDRA_DQ5 8 DDRA_MA14_WE_N WE_n/A14 RAS_n/A16 DDRA_MA16_RAS_N 8 DQS#0 DDRA_DQS#0
27 28 153 154
VSS_14 DQ8 VDD_15 VDD_16
DDRA_DQ2 29
DQ9 VSS_15
30
8 DDRA_ODT0
DDRA_ODT0 155
ODT0 CAS_n/A15
156 DDRA_MA15_CAS_N
DDRA_MA15_CAS_N 8
DQS0 DDRA_DQS0
31 32 DDRA_DQS0_N DDRA_CS1_N 157 158 DDRA_MA13
DDRA_MA_DM0 VSS_16 DQS1_c DDRA_DQS0_P DDRA_DQS0_N 8 8 DDRA_CS1_N CS1_n A13
33 34 159 160 DQ8 DDRA_DQ13
35
DM1_n/DBl1_n/NC DQS1_t
36 DDRA_DQS0_P 8 DDRA_ODT1 161
VDD_17 VDD_18
162 +VREF_CA
DDRA_DQ3 37 VSS_17 VSS_18
38 DDRA_DQ1 8 DDRA_ODT1 163 ODT1 C0/CS2_n/NC
164
DQ9 DDRA_DQ9
39
DQ15 DQ14
40 165
VDD_19 VREFCA
166 DDRA0_SA2 DQ10 DDRA_DQ14
VSS_19 VSS_20 C1/CS3_n/NC SA2 DQ11 DDRA_DQ10

m
DDRA_DQ6 41 42 DDRA_DQ7 167 168
DQ10 DQ11 DDRA_DQ36 VSS_53 VSS_54 DDRA_DQ32
43
VSS_21 VSS_22
44 169
DQ37 DQ36
170 DQ12 DDRA_DQ12
DDRA_DQ20 45 46 DDRA_DQ21 171 172 DQ13 DDRA_DQ8
DQ21 DQ20 DDRA_DQ37 VSS_55 VSS_56 DDRA_DQ33
47 48 173 174 DQ14 DDRA_DQ15
DDRA_DQ16 VSS_23 VSS_24 DDRA_DQ17 DQ33 DQ32
49 50 175 176
DQ15 DDRA_DQ11

co
DQ17 DQ16 DDRA_DQS4_N VSS_57 VSS_58 DDRA_MA_DM4
51 52 177 178
DDRA_DQS2_N 53 VSS_25 VSS_26
54 DDRA_MA_DM2 8 DDRA_DQS4_N DDRA_DQS4_P 179 DQS4_c DM4_n/DBl4_n/NC
180 DQS#1 DDRA_DQS#1
8 DDRA_DQS2_N DDRA_DQS2_P 55
DQS2_c DM2_n/DBl2_n/NC
56 8 DDRA_DQS4_P 181
DQS4_t VSS_59
182 DDRA_DQ34 DQS1 DDRA_DQS1
8 DDRA_DQS2_P 57 DQS2_t VSS_27
58 DDRA_DQ23 DDRA_DQ38 183 VSS_60 DQ39
184
DDRA_DQ19 VSS_28 DQ22 DQ38 VSS_61 DDRA_DQ35
59 60 185 186 DQ16 DDRA_DQ20
DQ23 VSS_29 DDRA_DQ22 DDRA_DQ39 VSS_62 DQ35
61 62 187 188 DQ17 DDRA_DQ21
DDRA_DQ18 VSS_30 DQ18 DQ34 VSS_63 DDRA_DQ41

s.
63 64 189 190
65
DQ19 VSS_31
66 DDRA_DQ29 DDRA_DQ44 191
VSS_64 DQ45
192 DQ18 DDRA_DQ22
DDRA_DQ28 67 VSS_32 DQ28
68 193 DQ44 VSS_65
194 DDRA_DQ40 DQ19 DDRA_DQ19
DQ29 VSS_33 VSS_66 DQ41
69
VSS_34 DQ24
70 DDRA_DQ25 DDRA_DQ45 195
DQ40 VSS_67
196 DQ20 DDRA_DQ16
DDRA_DQ24 DDRA_DQS5_N

ic
71 72 197 198 DQ21 DDRA_DQ17
73 DQ25 VSS_35
74 DDRA_DQS3_N DDRA_MA_DM5 199 VSS_68 DQS5_c
200 DDRA_DQS5_P DDRA_DQS5_N 8
DDRA_MA_DM3 VSS_36 DQS3_c DDRA_DQS3_P DDRA_DQS3_N 8 DM5_n/DBl5_n/NC DQS5_t DDRA_DQS5_P 8 DQ22 DDRA_DQ23
75 76 201 202
77 DM3_n/DBl3_n/NC DQS3_t
78 DDRA_DQS3_P 8 DDRA_DQ46 203 VSS_69 VSS_70
204 DDRA_DQ43 DQ23 DDRA_DQ18
DDRA_DQ30 79
VSS_37 VSS_38
80 DDRA_DQ26 205
DQ46 DQ47
206 DQS#2 DDRA_DQS#2

at
DQ30 DQ31 VSS_71 VSS_72
81
VSS_39 VSS_40
82 DDRA_DQ47 207
DQ42 DQ43
208 DDRA_DQ42 DQS2 DDRA_DQS2
DDRA_DQ31 83 84 DDRA_DQ27 209 210
C DQ26 DQ27 VSS_73 VSS_74 C
85 86 DDRA_DQ52 211 212 DDRA_DQ49 DQ24 DDRA_DQ28
87
89
VSS_41
CB5/NC
VSS_42
CB4/NC
88
90
Sodimm follow L340_API_0703 DDRA_DQ53
213
215
DQ52
VSS_75
DQ53
VSS_76
214
216 DDRA_DQ48 DQ25 DDRA_DQ29

m
+1.2V +1.2V 91 VSS_43 VSS_44
92 +1.2V 217 DQ49 DQ48
218 DQ26 DDRA_DQ31
240_0402_1% 93 CB1/NC CB0/NC
94 DDRA_DQS6_N 219 VSS_77 VSS_78
220 DDRA_MA_DM6 DQ27 DDRA_DQ27
1 2 DDRA_DQS8_N 95
VSS_45 VSS_46
96 8 DDRA_DQS6_N DDRA_DQS6_P 221
DQS6_c DM6_n/DBl6_n/NC
222 DQ28 DDRA_DQ24
RD273 @
1 2 DDRA_DQS8_P 97 DQS8_c DM8_n/DBI8_n/NC
98 8 DDRA_DQS6_P 223 DQS6_t VSS_79
224 DDRA_DQ51
RD274 @
DQS8_t VSS_47 VSS_80 DQ54
DQ29 DDRA_DQ25
99 100 DDRA_DQ54 225 226 DQ30 DDRA_DQ30

he
VSS_48 CB6/NC DQ55 VSS_81 DDRA_DQ55
101 102 227 228
240_0402_1%
103 CB2/NC VSS_49
104 for MEM_MB_RST# overshoot issue DDRA_DQ50 229 VSS_82 DQ50
230 DQ31 DDRA_DQ26
105 VSS_50 CB7/NC
106 231 DQ51 VSS_83
232 DDRA_DQ61 DQS#3 DDRA_DQS#3
CB3/NC VSS_51 VSS_84 DQ60
107
VSS_52 RESET_n
108 DDR4_A_DRAMRST_R_N DDRA_DQ56 233
DQ61 VSS_85
234 DQS3 DDRA_DQS3
DDRA_CKE0 109 110 DDRA_CKE1 235 236 DDRA_DQ57
8 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 8 DDRA_DQ60 VSS_86 DQ57
111 112 237 238 DQ32 DDRA_DQ33

0.1U_6.3V_K_X5R_0201

Sc
DDRA_BG1 VDD_1 VDD_2 DDRA_ACT_N DQ56 VSS_87 DDRA_DQS7_N
113 114 239 240
8 DDRA_BG1 DDRA_BG0 115 BG1 ACT_n
116 DDRA_ALERT_N DDRA_ACT_N 8 1
DDRA_MA_DM7 241 VSS_88 DQS7_c
242 DDRA_DQS7_P DDRA_DQS7_N 8 DQ33 DDRA_DQ37
8 DDRA_BG0
117 BG0 ALERT_n
118
DDRA_ALERT_N 8
243 DM7_n/DBl7_n/NC DQS7_t
244 DDRA_DQS7_P 8 DQ34 DDRA_DQ34
DDRA_MA12 119 VDD_3 VDD_4
120 DDRA_MA11 DDRA_DQ58 245 VSS_89 VSS_90
246 DDRA_DQ62 DQ35 DDRA_DQ38
CD120
DDRA_MA9 121 A12 A11
122 DDRA_MA7 2 247 DQ62 DQ63
248 DQ36 DDRA_DQ32
A9 A7 DDRA_DQ63 VSS_91 VSS_92 DDRA_DQ59
123 124 @ 249 250 DQ37 DDRA_DQ36
DDRA_MA8 VDD_5 VDD_6 DDRA_MA5 DQ58 DQ59

k
125 126 251 252 DQ38 DDRA_DQ35
DDRA_MA6 A8 A5 DDRA_MA4 +VDDSPD SMB_CLK_S1 VSS_93 VSS_94 SMB_DATA_S1
127 128 253 254
129 A6 A4
130 12 SMB_CLK_S1 255 SCL SDA
256 DDRA0_SA0 SMB_DATA_S1 12 DQ39 DDRA_DQ39
VDD_7 VDD_8 VDDSPD SA0 DQS#4 DDRA_DQS#4

oo
257 258
+2.5V VPP_1 Vtt DDRA0_SA1 +0.6VS
1 1 259
VPP_2 SA1
260 DQS4 DDRA_DQS4
CD28 CD29 1
ARGOS_D4AS0-26001-1P60 1U_0402_6.3V6K 0.1U_6.3V_K_X5R_0201 CD121 261 262 DQ40 DDRA_DQ44
GND_1 GND_2
ME@ 22P_50V_J_NPO_0402 DQ41 DDRA_DQ40
2 2
RF RF_NS@
2
ARGOS_D4AS0-26001-1P60
+2.5V +2.5VS DQ42 DDRA_DQ47
ME@
eb
DQ43 DDRA_DQ43
DDR4_A_DRAMRST_N RD288 1 @ 2 0_0402_5% DDR4_A_DRAMRST_R_N 3 1 DQ44 DDRA_DQ41

D
8 DDR4_A_DRAMRST_N
QD1 DQ45 DDRA_DQ45
LP2301ALT1G_SOT23-3 DQ46 DDRA_DQ46
+3VS +VDDSPD

G
DQ47 DDRA_DQ42

2
+1.2V RD271 1 @ 2 0_0402_5%
+2.5VS @ DQS#5 DDRA_DQS#5
ot

B B
50,84 SUSP
DQS5 DDRA_DQS5
+1.2V
1

RD272 1 @ 2 0_0402_5%
RD73
+VREF_CA
DQ48 DDRA_DQ48
1K_0402_1% DQ49 DDRA_DQ49
1

SODIMM EMC&RF
N

DQ50 DDRA_DQ55
RD258
15mil DQ51 DDRA_DQ50
2

1K_0402_1%
DQ52 DDRA_DQ52
1000P 25V K X7R 0201
0.1U_6.3V_K_X5R_0201
1

Layout Note: Place near JDDR1

@ DQ53 DDRA_DQ53
1U_0402_6.3V6K
2

RD74 1 1 1 DQ54 DDRA_DQ54

DDRA_ALERT_N 1K_0402_1%
+1.2V DQ55 DDRA_DQ51
CD262

CD116

CD117

DQS#6 DDRA_DQS#6
2

2 2 2 DQS6 DDRA_DQS6
DQ56 DDRA_DQ60
27P_25V_J_NPO_0201

27P_25V_J_NPO_0201 DQ57 DDRA_DQ56

1 1 DQ58 DDRA_DQ63
CD58 CD64
EMC_NS@ EMC_NS@ DQ59 DDRA_DQ59
DQ60 DDRA_DQ61
2 2
DQ61 DDRA_DQ57
CD60=>CD64 DQ62 DDRA_DQ58
DQ63 DDRA_DQ62
+3VS +3VS +3VS DQS#7 DDRA_DQS#7
DQS7 DDRA_DQS7
1

RD67 RD71 RD131 +1.2V

10K_0402_5% 10K_0402_5% 10K_0402_5%

@ @ @
2

DDRA0_SA0 DDRA0_SA1 DDRA0_SA2

1 1 1 1 1
1

CD19 CD260 CD12 CD348 CD349

A RD68 RD130 RD132 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 A
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% RF_NS@ RF_NS@ RF_NS@ RF_NS@ RF_NS@
2 2 2 2 2
2

RF

SPD Address = A0H Security Classification LC Future Center Secret Data Title
Issued Date 2013/08/15 Deciphered Date 2013/08/15 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S360 Lucienne
Date: Friday, December 04, 2020 Sheet 25 of 110
5 4 3 2 1
 5 4 3 2 1

DDRB_BG1_R RD69 2 @ 1 0_0201_5% DDRB_BG1 DDRB_DQ[0..63]

DDRB_BG1 9 DDRB_DQ[0..63] 9
UD5 UD6
+1.2V
DDRB_MA0 DDRB_DQ1 DDRB_MA0 DDRB_DQ19
RD69 DDP

1
P3 G2 P3 G2
9 DDRB_MA0 DDRB_MA1 A0 DQL0 DDRB_DQ7 DDRB_MA1 A0 DQL0 DDRB_DQ18 DRAM@
P7 F7 P7 F7 RD72 DRAM@
9 DDRB_MA1 DDRB_MA2 R3 A1 DQL1 H3 DDRB_DQ5 DDRB_MA2 R3 A1 DQL1 H3 DDRB_DQ22 DDRB_CLK0_N 2 3
@ 0_0201_5% CD35 1 2 0.1U_10V_K_X7R_0402
9 DDRB_MA2 DDRB_MA3 A2 DQL2 DDRB_DQ6 DDRB_MA3 A2 DQL2 DDRB_DQ16 DDRB_CLK0_P
N7 H7 Byte 0 N7 H7 Byte 2 RD72 SDP 1 4
9 DDRB_MA3 DDRB_MA4 A3 DQL3 DDRB_DQ0 DDRB_MA4 A3 DQL3 DDRB_DQ20
N3 H2 N3 H2 RPD11 1/20W_39_5%_4P2R_0404
9 DDRB_MA4 DDRB_MA5 DDRB_DQ3 DDRB_MA5 DDRB_DQ17

2
A4 DQL4 A4 DQL4
P8 H8 P8 H8 CD163=>CD35
9 DDRB_MA5 DDRB_MA6 A5 DQL5 DDRB_DQ4 DDRB_MA6 A5 DQL5 DDRB_DQ21
P2 J3 P2 J3
9 DDRB_MA6 DDRB_MA7 A6 DQL6 DDRB_DQ2 DDRB_MA7 A6 DQL6 DDRB_DQ23
R8 J7 R8 J7
9 DDRB_MA7 DDRB_MA8 A7 DQL7 DDRB_DQ13 DDRB_MA8 A7 DQL7 DDRB_DQ24
R2 A3 R2 A3 Note: CLK termination must match the CLK reference plane.
9 DDRB_MA8 DDRB_MA9 R7 A8 DQU0 B8 DDRB_DQ15 DDRB_MA9 R7 A8 DQU0 B8 DDRB_DQ26
9 DDRB_MA9 DDRB_MA10 A9 DQU1 DDRB_DQ8 DDRB_MA10 A9 DQU1 DDRB_DQ29 +0.6VS
M3 C3 M3 C3
9 DDRB_MA10 DDRB_MA11 A10/AP DQU2 DDRB_DQ9 DDRB_MA11 A10/AP DQU2 DDRB_DQ31 UD5_DDRB_UZQ
T2 C7 Byte 1 T2 C7 Byte 3
9 DDRB_MA11 DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ12 DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ25 DDRB_CKE0 2 DRAM@ 3
RPD1 1/20W_39_5%_4P2R_0404
9 DDRB_MA12 DDRB_MA13 T8 A12/BC_N DQU4
C8 DDRB_DQ11 DDRB_MA13 T8 A12/BC_N DQU4
C8 DDRB_DQ30 DDRB_MA14_WE_N 1 4
D D
9 DDRB_MA13 A13 DQU5 D3 DDRB_DQ14 A13 DQU5 D3 DDRB_DQ28 UD6_DDRB_UZQ
DDRB_MA14_WE_N L2 DQU6
D7 DDRB_DQ10 DDRB_MA14_WE_N L2 DQU6
D7 DDRB_DQ27 +0.6VS
9 DDRB_MA14_WE_N DDRB_MA15_CAS_N WE_N/A14 DQU7 DDRB_MA15_CAS_N WE_N/A14 DQU7 DDRB_BA0
M8 M8 RPD2 1 DRAM@ 4 1/20W_39_5%_4P2R_0404
9 DDRB_MA15_CAS_N DDRB_MA16_RAS_N L8 CAS_N/A15 +1.2V DDRB_MA16_RAS_N L8 CAS_N/A15 +1.2V UD7_DDRB_UZQ DDRB_BG0 2 3
9 DDRB_MA16_RAS_N RAS_N/A16 RAS_N/A16 DRAM@
D1 D1
DDRB_CLK0_N K8 VDD1 J1 DDRB_CLK0_N K8 VDD1 J1 DDRB_MA5 RPD10 2 3 1/20W_39_5%_4P2R_0404
9 DDRB_CLK0_N DDRB_CLK0_P CK_C VDD2 DDRB_CLK0_P CK_C VDD2 UD8_DDRB_UZQ DDRB_MA13 DDRB_MA11
K7 L1 K7 L1 1 4 RPD3 1 DRAM@ 4 1/20W_39_5%_4P2R_0404
9 DDRB_CLK0_P CK_T VDD3 CK_T VDD3 DDRB_MA8
R1 R1 2 3
DDRB_CKE0 K2 VDD4 B3 DDRB_CKE0 K2 VDD4 B3

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201

1/20W_240_1%_0201
9 DDRB_CKE0 CKE VDD5 CKE VDD5
G7 G7
DDRB_DQS0_N DDRB_DQS2_N DDRB_MA0

1
F3 VDD6 B9 F3 VDD6 B9 2 DRAM@ 3
9 DDRB_DQS0_N 9 DDRB_DQS2_N RPD4 1/20W_39_5%_4P2R_0404
DDRB_DQS0_P G3 DQSL_C VDD7
J9 DDRB_DQS2_P G3 DQSL_C VDD7
J9 DDRB_MA6 RD536 1 DRAM@ 2 1/20W_39_5%_0201 DDRB_PAR 1 4

RD82

RD88

RD94

RD102
9 DDRB_DQS0_P DDRB_DQS1_N DQSL_T VDD8 9 DDRB_DQS2_P DDRB_DQS3_N DQSL_T VDD8 DDRB_MA7
A7 L9 A7 L9 RD534 1 DRAM@ 2 1/20W_39_5%_0201
9 DDRB_DQS1_N DDRB_DQS1_P DQSU_C VDD9 9 DDRB_DQS3_N DDRB_DQS3_P DQSU_C VDD9
B7 T9 B7 T9
9 DDRB_DQS1_P DQSU_T VDD10 9 DDRB_DQS3_P DQSU_T VDD10 DDRB_MA2 RPD5 2 DRAM@ 3 1/20W_39_5%_4P2R_0404
DDRB_MB_DM1 DDRB_MB_DM3 DDRB_MA4

2
E2 A1 E2 A1 1 4
9 DDRB_MB_DM1 9 DDRB_MB_DM3

m
DDRB_MB_DM0 E7 NF/UDM_N/UDBI_N VDDQ1
C1 DDRB_MB_DM2 E7 NF/UDM_N/UDBI_N VDDQ1
C1 DDRB_MA15_CAS_N RD528 1 DRAM@ 2 1/20W_39_5%_0201
9 DDRB_MB_DM0 NF/LDM_N/LDBI_N VDDQ2 9 DDRB_MB_DM2 NF/LDM_N/LDBI_N VDDQ2 DDRB_MA16_RAS_N RD544
G1 G1 @ @ @ @ 1 DRAM@ 2 1/20W_39_5%_0201
DDRB_BA0 N2 VDDQ3 F2 DDRB_BA0 N2 VDDQ3 F2 DDRB_MA10 RPD6 2 DRAM@ 3 1/20W_39_5%_4P2R_0404
9 DDRB_BA0 DDRB_BA1 BA0 VDDQ4 DDRB_BA1 BA0 VDDQ4 DDRB_ACT_N
RF N8 J2 N8 J2 1 4
9 DDRB_BA1 BA1 VDDQ5 BA1 VDDQ5
F8 F8
DDRB_ACT_N L3 VDDQ6
J8 DDRB_ACT_N L3 VDDQ6
J8 DDRB_BG1_R 1 @ 2
9 DDRB_ACT_N
RD103 1/20W_39_5%_0201 RD103 DDP

co
DDRB_CS0_N L7 ACT_N VDDQ7
A9 DDRB_CS0_N L7 ACT_N VDDQ7
A9 DDRB_ODT0 RPD7 2 DRAM@ 3 1/20W_39_5%_4P2R_0404
9 DDRB_CS0_N DDRB_ALERT_N P9 CS_N VDDQ8 D9 DDRB_ALERT_N P9 CS_N VDDQ8 D9 DDRB_BA1 1 DRAM@ 2 DDRB_CS0_N 1 4
RD106 1/20W_39_5%_0201
9 DDRB_ALERT_N ALERT_N VDDQ9 +2.5V ALERT_N VDDQ9 +2.5V
G9 G9
DDRB_BG0 M2 VDDQ10 DDRB_BG0 M2 VDDQ10 RD233 RD232 RD231 RD228 will install different
9 DDRB_BG0
DDRB_ODT0
BG0
VPP1
B1
DDRB_ODT0
BG0
VPP1
B1 value base on SDP or DDP.control by Virtual symbol RD128=>RD536 DDRB_MA3
DDRB_MA12
RPD8 1 DRAM@ 4 1/20W_39_5%_4P2R_0404
K3 R9 K3 R9 RD129=>RD534 2 3
9 DDRB_ODT0 ODT VPP2 +VREF_CA_MD ODT VPP2 +VREF_CA_MD
DDRB_PAR DDRB_PAR +1.2V RD139=>RD528
T3 M1 T3 M1

s.
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1U_0402_6.3V6K

1U_0402_6.3V6K
9 DDRB_PAR PAR VREFCA PAR VREFCA RD140=>RD544 DDRB_MA1 2 DRAM@ 3
1 1 1 1 RPD9 1/20W_39_5%_4P2R_0404
RD97 1 2 10K_0201_5% TEN_UD5 N9 E1 RD98 1 2 10K_0201_5% TEN_UD6 N9 E1 RD229=>RD103 DDRB_MA9 1 4

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

CD38

CD39

1000P 25V K X7R 0201

CD42

CD43
TEN VSS1
K1 TEN VSS1
K1 RD143=>RD106

0.1U_6.3V_K_X5R_0201
DDR4_B_DRAMRST_R_N 1 1 DDR4_B_DRAMRST_R_N 1 1 Swap Table

1
P1 VSS2 N1 P1 VSS2 N1 RD149,RD110

CD36

CD37

CD40

CD41
DRAM@ DRAM@ 1
RESET_N VSS3
DRAM@ 2 2 RESET_N VSS3
DRAM@2 2

ic
T1 T1
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
DRAM@ CD60 RD123
F1 VSS4 B2 F1 VSS4 B2 DRAM@ DRAM@ 1K_0402_1% +VREF_CA_MD Pin Name Net Name
VSSQ1 VSS5
1 H1 G8 DRAM@ 2 DRAM@2 1 H1 VSSQ1 VSS5
G8 DRAM@ 2 2 DRAM@
A2 VSSQ2 VSS6
K9 A2 VSSQ2 VSS6
K9 2
DRAM@
15mil DQ0 DDRB_DQ3
CD44

CD45

2
D2 VSSQ3 VSS8 D2 VSSQ3 VSS8
VSSQ4 DDP_VSS_1 VSSQ4 DDP_VSS_2 DQ1 DDRB_DQ6
E3 T7 1 2 E3 T7 1 @ 2

0.1U_6.3V_K_X5R_0201
@

1000P 25V K X7R 0201

at
2 2 DQ2 DDRB_DQ2

1
A8 VSSQ5 VSS7 A8 VSSQ5 VSS7

1U_0402_6.3V6K
@ RD107 0_0201_5% @ RD108
D8 VSSQ6
D8 VSSQ6
0_0201_5% RD125 DQ3 DDRB_DQ0
VSSQ7 DDRB_BG1_R VSSQ7 DDRB_BG1_R 1 1 1 DQ4 DDRB_DQ7
E8 M9 E8 M9

@
1K_0402_1%
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
DRAM@ +1.2V DQ5 DDRB_DQ5

CD522

CD524

CD412
C VSSQ9 UD5_DDRB_UZQ VSSQ9 UD6_DDRB_UZQ C
H9 E9 H9 E9 DQ6 DDRB_DQ4

2
VSSQ10 VSS10 F9 VSSQ10 VSS10 F9 2 2 2
1/20W_240_1%_0201

1/20W_240_1%_0201
ZQ5 ZQ6 DQ7 DDRB_DQ1

em
ZQ ZQ DDRB_ALERT_N RD66 1 DRAM@ 2 1/20W_1K_1%_0201 DQS#0 DDRB_DQS#0
1

1
DQS0 DDRB_DQS0
UD1
RD111

RD112
K4AAG165WA-BCWE_FBGA96 K4AAG165WA-BCWE_FBGA96 RD86==>RD66
@ @ CD2=>CD60 DQ8 DDRB_DQ9
RD276=>RD123 DQ9 DDRB_DQ11
2

2
RD277=>RD125 DQ10 DDRB_DQ12
CD357=>CD522 DQ11 DDRB_DQ8
DRAM@ DRAM@ CD358=>CD524
RD107,RD108,RD119,RD120 DDP DQ12 DDRB_DQ15

h
CD359=>CD412 DQ13 DDRB_DQ13
DQ14 DDRB_DQ14
DQ15 DDRB_DQ10
DQS#1 DDRB_DQS#1

Sc
DQS1 DDRB_DQS1
EMC&RF CAP UD1
CD271=>CD556 DQ16 DDRB_DQ7
CD266=>CD540 CD272=>CD552 DQ17 DDRB_DQ3
CD267=>CD553 CD273=>CD538 DQ18 DDRB_DQ4
+1.2V CD268=>CD554 CD274=>CD551 DQ19 DDRB_DQ0

k
UD7 CD269=>CD549
UD8
CD275=>CD541 DQ20 DDRB_DQ6
DDRB_MA0 P3 G2 DDRB_DQ36 CD270=>CD555 CD276=>CD539 DQ21 DDRB_DQ5
DDRB_MA1 P7 A0 DQL0 F7 DDRB_DQ39 DDRB_MA0 P3 G2 DDRB_DQ56 CD277=>CD550 DQ22 DDRB_DQ2

oo
DDRB_MA2 R3 A1 DQL1
H3 DDRB_DQ37 DDRB_MA1 P7 A0 DQL0
F7 DDRB_DQ61
DDRB_MA3 A2 DQL2 DDRB_DQ34 DDRB_MA2 A1 DQL1 DDRB_DQ60
DQ23 DDRB_DQ1
N7 H7 Byte 4 R3 H3 DQS#2 DDRB_DQS#2
DDRB_MA4 N3 A3 DQL3 H2 DDRB_DQ32 DDRB_MA3 N7 A2 DQL2 H7 DDRB_DQ59
DDRB_MA5 A4 DQL4 DDRB_DQ35 DDRB_MA4 A3 DQL3 DDRB_DQ57
Byte 7 CD540 1 CD553 1 CD554 1 CD549 1 CD555 1 CD556 1 CD552 1 CD538 1 CD551 1 CD541 1 CD539 1 CD550 1
DQS2 DDRB_DQS2
P8 H8 N3 H2

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201

47P_25V_J_NPO_0201

47P_25V_J_NPO_0201

27P_25V_J_NPO_0201
DDRB_MA6 P2 A5 DQL5 J3 DDRB_DQ33 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ62 UD2

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
DDRB_MA7 R8 A6 DQL6
J7 DDRB_DQ38 DDRB_MA6 P2 A5 DQL5
J3 DDRB_DQ63 DQ24 DDRB_DQ15
DDRB_MA8 R2 A7 DQL7
A3 DDRB_DQ46 DDRB_MA7 R8 A6 DQL6
J7 DDRB_DQ58 2 2 2 2 2 2 2 2 2 2 2 2
DDRB_MA9 A8 DQU0 DDRB_DQ43 DDRB_MA8 A7 DQL7 DDRB_DQ49 DQ25 DDRB_DQ11
R7 B8 R2 A3
DQ26 DDRB_DQ12

eb
DDRB_MA10 M3 A9 DQU1
C3 DDRB_DQ47 DDRB_MA9 R7 A8 DQU0
B8 DDRB_DQ50
DDRB_MA11 T2 A10/AP DQU2 C7 DDRB_DQ42 DDRB_MA10 M3 A9 DQU1 C3 DDRB_DQ48 DQ27 DDRB_DQ8
DDRB_MA12 A11 DQU3 DDRB_DQ40
Byte 5 DDRB_MA11 A10/AP DQU2 DDRB_DQ51 DQ28 DDRB_DQ13
M7 C2 T2 C7 Byte 6
DDRB_MA13 T8 A12/BC_N DQU4
C8 DDRB_DQ45 DDRB_MA12 M7 A11 DQU3
C2 DDRB_DQ52 +1.2V DQ29 DDRB_DQ9
A13 DQU5 D3 DDRB_DQ41 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ55 DQ30 DDRB_DQ14
DDRB_MA14_WE_N L2 DQU6
D7 DDRB_DQ44 A13 DQU5
D3 DDRB_DQ53
DDRB_MA15_CAS_N WE_N/A14 DQU7 DDRB_MA14_WE_N DQU6 DDRB_DQ54
DQ31 DDRB_DQ10
M8 L2 D7 DQS#3 DDRB_DQS#3
DDRB_MA16_RAS_N L8 CAS_N/A15 +1.2V DDRB_MA15_CAS_N M8 WE_N/A14 DQU7
DQS3 DDRB_DQS3

ot
RAS_N/A16
D1 DDRB_MA16_RAS_N L8 CAS_N/A15 +1.2V

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
B DDRB_CLK0_N K8 VDD1 J1 RAS_N/A16 D1 CD352 1 CD353 1 CD354 1 CD355 1 CD356 1 UD2 B
DDRB_CLK0_P K7 CK_C VDD2
L1 DDRB_CLK0_N K8 VDD1
J1
CK_T VDD3 DDRB_CLK0_P CK_C VDD2
DQ32 DDRB_DQ6
R1 K7 L1

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
DDRB_CKE0 VDD4 CK_T VDD3 DQ33 DDRB_DQ7
K2 B3 R1
CKE VDD5
G7 DDRB_CKE0 K2 VDD4
B3 2 2 2 2 2 DQ34 DDRB_DQ2
DDRB_DQS4_N F3 VDD6 B9 CKE VDD5 G7 DQ35 DDRB_DQ1
9
9
9
9

9
DDRB_DQS4_N
DDRB_DQS4_P
DDRB_DQS5_N
DDRB_DQS5_P

DDRB_MB_DM5
DDRB_DQS4_P
DDRB_DQS5_N
DDRB_DQS5_P

DDRB_MB_DM5
DDRB_MB_DM4
G3
A7
B7

E2
E7
DQSL_C
DQSL_T
DQSU_C
DQSU_T

NF/UDM_N/UDBI_N
VDD7
VDD8
VDD9
VDD10

VDDQ1
J9
L9
T9

A1
C1
9
9
9
9
N
DDRB_DQS7_N
DDRB_DQS7_P
DDRB_DQS6_N
DDRB_DQS6_P
DDRB_DQS7_N
DDRB_DQS7_P
DDRB_DQS6_N
DDRB_DQS6_P

DDRB_MB_DM6
F3
G3
A7
B7

E2
DQSL_C
DQSL_T
DQSU_C
DQSU_T
VDD6
VDD7
VDD8
VDD9
VDD10
B9
J9
L9
T9

A1
DQ36
DQ37
DQ38
DQ39
DQS#4
DDRB_DQ5
DDRB_DQ3
DDRB_DQ4
DDRB_DQ0
DDRB_DQS#4
9 DDRB_MB_DM4 NF/LDM_N/LDBI_N VDDQ2 G1
9 DDRB_MB_DM6 DDRB_MB_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DQS4 DDRB_DQS4
DDRB_BA0 N2 VDDQ3
F2
9 DDRB_MB_DM7 NF/LDM_N/LDBI_N VDDQ2
G1 +1.2V +0.6VS UD3
DDRB_BA1 N8 BA0 VDDQ4
J2 DDRB_BA0 N2 VDDQ3
F2 +2.5V DQ40 DDRB_DQ9
BA1 VDDQ5 F8 DDRB_BA1 N8 BA0 VDDQ4 J2
DDRB_ACT_N VDDQ6 BA1 VDDQ5 DQ41 DDRB_DQ15
L3 J8 F8

180P_50V_J_NPO_0402
DDRB_CS0_N L7 ACT_N VDDQ7 A9 DDRB_ACT_N L3 VDDQ6 J8
DQ42 DDRB_DQ12
DDRB_ALERT_N P9 CS_N VDDQ8
D9 DDRB_CS0_N L7 ACT_N VDDQ7
A9 DQ43 DDRB_DQ14
ALERT_N VDDQ9 +2.5V DDRB_ALERT_N CS_N VDDQ8 1 1 DQ44 DDRB_DQ11
G9 P9 D9 CD507

CD568
DDRB_BG0 1 1 1 1
M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V CD506 CD504 CD508 CD505 22P_50V_J_NPO_0402 DQ45 DDRB_DQ13
BG0
B1 DDRB_BG0 M2 VDDQ10
22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 22P_50V_J_NPO_0402 RF_NS@ DQ46 DDRB_DQ10
DDRB_ODT0 K3 VPP1 R9 BG0 B1 RF_NS@ RF_NS@ RF_NS@ RF_NS@ @2 2
ODT VPP2 DDRB_ODT0 VPP1 2 2 2 2
DQ47 DDRB_DQ8
+VREF_CA_MD K3 R9
DDRB_PAR ODT VPP2 +VREF_CA_MD
DQS#5 DDRB_DQS#5
T3 M1
1U_0402_6.3V6K
0.1U_6.3V_K_X5R_0201

PAR VREFCA DDRB_PAR T3 M1 DQS5 DDRB_DQS5

1U_0402_6.3V6K
UD3

0.1U_6.3V_K_X5R_0201
1 1
RD1171 2 10K_0201_5% TEN_UD7 N9 E1 PAR VREFCA
0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

CD48

CD51

1 1
TEN VSS1 K1 RD1181 2 10K_0201_5% TEN_UD8 N9 E1 DQ48 DDRB_DQ11

0.1U_6.3V_K_X5R_0201
1000P 25V K X7R 0201

CD52

CD53
DDR4_B_DRAMRST_R_N VSS2 1 1 TEN VSS1
P1 N1 K1
CD49

CD50

DRAM@ 1 1 DQ49 DDRB_DQ13

RESET_N VSS3
T1 2 2 DDR4_B_DRAMRST_R_N P1 VSS2
N1
0.1U_6.3V_K_X5R_0201

CD54

CD55
DRAM@ DRAM@ DQ50 DDRB_DQ8
VSS4 RESET_N VSS3 2 DRAM@ 2
4700P_25V_K_X7R_0201

F1 B2 T1
H1 VSSQ1 VSS5
G8 2 2 DRAM@ F1 VSS4
B2 DRAM@ DQ51 DDRB_DQ14
1
A2 VSSQ2 VSS6 K9 DRAM@ H1 VSSQ1 VSS5 G8 2 2
CD133=>CD506 DQ52 DDRB_DQ9
CD56

VSSQ3 VSS8 DRAM@ 1 VSSQ2 VSS6 DRAM@

D2 A2 K9 DRAM@ CD153=>CD504 DQ53 DDRB_DQ15
E3 VSSQ4
T7 DDP_VSS_3
1 @ 2 DRAM@ D2 VSSQ3 VSS8
DQ54 DDRB_DQ12
CD57

2 A8 VSSQ5 VSS7 E3 VSSQ4 T7 DDP_VSS_4 1 @ 2

CD263=>CD508
@ RD119 0_0201_5% CD264=>CD505 DQ55 DDRB_DQ10
VSSQ6 2 VSSQ5 VSS7
D8 A8 RD120 0_0201_5% DQS#6 DDRB_DQS#7
E8 VSSQ7 M9 DDRB_BG1_R D8 VSSQ6 CD205=>CD568
C9 VSSQ8 VSS9
E8 VSSQ7
M9 DDRB_BG1_R +1.2V +0.6VS CD265=>CD507 DQS6 DDRB_DQS7
H9 VSSQ9
E9 UD7_DDRB_UZQ C9 VSSQ8 VSS9 UD4
VSSQ10 VSS10 F9 ZQ7 H9 VSSQ9 E9 UD8_DDRB_UZQ
ZQ VSSQ10 VSS10
DQ56 DDRB_DQ5
F9
1/20W_240_1%_0201

1/20W_240_1%_0201
ZQ8 DQ57 DDRB_DQ1
ZQ 1 2 0.22U_6.3V_K_X5R_0201
CD362 DQ58 DDRB_DQ2
1

@
K4AAG165WA-BCWE_FBGA96 CD363 1 2 0.22U_6.3V_K_X5R_0201 DQ59 DDRB_DQ0
RD121

RD122

A
@ DRAM@ K4AAG165WA-BCWE_FBGA96 @ DQ60 DDRB_DQ7 A

@ DRAM@ CD364 1 2 0.22U_6.3V_K_X5R_0201 DQ61 DDRB_DQ3

DRAM@ DQ62 DDRB_DQ6
2

DQ63 DDRB_DQ4
DQS#7 DDRB_DQS#6
DQS7 DDRB_DQS6
UD4

DDR4_B_DRAMRST_N Security Classification LC Future Center Secret Data Title

RD104 1 @ 2 0_0402_5% DDR4_B_DRAMRST_R_N
9 DDR4_B_DRAMRST_N
Issued Date 2013/08/15 Deciphered Date 2013/08/15 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
S360 Lucienne 0.3

Date: Friday, December 04, 2020 Sheet 26 of 110

5 4 3 2 1
 5 4 3 2 1

TABLE of TPM (U9801)

Vendor P/N LCFC P/N
Nuvoton NPCT750LABYX SA00008KS20
ST Micro ST33HTPH2E32AHC0 SA000089E20
NOTE:
Check timing sequence in SDV phase.

D 5 ms < t D
NOTE:
1) It is recommended to connect the TPM to the system's
standby voltage to improve performance.
0 < t 2) SPI_RST# must be asserted for at least 5 msec after
VSB power-up.
VSB 3) VSB may come up anytime before VDD power-up,
but not after VDD power-up.
4) SPI_RST# may be asserted together with VDD power
VDD negation, but should not at any point exceed 0.5V
1 ms < t above the VDD power level.

SPI_RST#

m
co
TABLE

Pin TCG Nuvoton ST Micro

s.
No PTP Spec (v38) NPCT750LABYX ST33HTPH2E32AHC0

ic
1 VDD VSB NC
2 GND NC GND
3 NC NC NC
4 GPIO GPIO/PP PP

at
5 NC NC NC
6 GPIO GPIO3 NC
C
7 GPIO NC GPIO C

8 VDD VHIO NC

m
9 NC NC NC

he
10 NC NC NC
11 NC NC NC
12 NC NC NC
13 GPIO GPIO4 NC
14 NC NC NC

Sc
15 NC NC NC
16 GND GND NC

k
17 SPI_RST# RST# SPI_RST#
18 SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
19 SPI_CLK SCLK SPI_CLK

oo
20 SPI_CS# SCS#/GPIO5 SPI_CS#
21 MOSI MOSI/GPIO7 MOSI
22 VDD VHIO VPS
23 GND GND NC
24 MISO MISO MISO
eb 25 NC NC NC
26 NC NC NC
ot
27 NC NC NC
B 28 NC NC NC B
29 SDA/GPIO1 SDA/GPIO1 NC
30 SDA/GPIO0 SDA/GPIO0 NC
N

31 NC NC NC
32 NC NC NC

SPI ROM
Used RPMC BIOS ROM
+1.8VALW _SPI +1.8VALW

UB1
ROM_SPI_CS1_N 1 8 RB2 1 2
ROM_SPI_D1 /CS VCC ROM_SPI_D3
0.085 A @
2 7 0_0402_5%
ROM_SPI_D2 DO(IO1) /RST(IO3) ROM_SPI_CLK
3 6
/WP(IO2) CLK ROM_SPI_D0
4 5
ROM_SPI_CS1_N GND DI(IO0)
RB13 1 @ 2 0_0402_5% 1 1
11,79 CPU_SPI_CS1_N ROM_SPI_D0
RB11 1 @ 2 0_0402_5% W 74M12JWSSIQ_SO8 @
11,79 CPU_SPI_D0 ROM_SPI_D1
RB12 1 @ 2 0_0402_5% 16M CB2 CB1
11,79 CPU_SPI_D1 ROM_SPI_CLK
RB10 1 @ 2 0_0402_5% 5.6P_50V_D_NPO_0402 0.1u_0201_10V6K
11,79 SPI_CLK ROM_SPI_D2 2 2
RB21 1 @ 2 0_0402_5%
11 CPU_SPI_D2 ROM_SPI_D3
RB22 1 @ 2 0_0402_5%
11 CPU_SPI_D3 +1.8VALW _SPI
UB2
ROM_SPI_CS1_N 1 8
/CS VCC
A ROM_SPI_D1 ROM_SPI_D3 A
2 7
IO1 IO3
ROM_SPI_D2 3 6 ROM_SPI_CLK
IO2 CLK

4 5 ROM_SPI_D0
GND IO0

9
PAD_GND
@

W 74M25JWZEIQ_W SON8_8X6
32M Security Classification LC Future Center Secret Data Title
Issued Date 2018/8/9 Deciphered Date 2018/8/9 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SPI ROM
Date: Friday, December 04, 2020 Sheet 27 of 110
5 4 3 2 1
 5 4 3 2 1

LCD EDP Display DMIC BOARD POWER

LCD Power Circuit Follow Intel S360ITL_0610 LED Power Follow Intel S360ITL_0610 Camera DMIC
+3VS B+ +LEDVDD
FV1
+LCDVDD +LCDVDD_CON
W=60mils +3VS
1 1 2 +3VS_CAMERA +3VS_MIC
CV1
0.1U_6.3V_K_X5R_0201 UV1 FA2 W=80mils W=40mils
5 1 1 2 0_0603_SP 1 2 1 2 0_0603_SP

0.1U_25V_K_X5R_0201
@ @ 1 3A_32V_0497003PKRHF 1 1 @
2 IN OUT

10U_25V_M_X5R_0603

0.1U_25V_K_X5R_0201
EMC_NS@
RV1 CV5 CV6 CV7 RI507 1 1
2 @ 3A_32V_ERBRD3R00X CA96 CA97
GND
CV2 1 CV3 1 CV4 1 10U 6.3V M X5R 0402 0.1U_6.3V_K_X5R_0201
4 3 2 2 2 RI329 1 2 1/10W_0_5%_0603

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

33P_50V_J_NPO_0201
@ EMC_NS@
7 ENVDD EN OCB 2 2
@ @
1
D 2 2 2 D
2

SY6288C20AAC_SOT23-5 1 1
RV29 CA93
100K_0201_5% CA94 .047U_16V_K_X5R_0201
High Active 2A
@ CA95
0.1U_6.3V_K_X5R_0201 10U 6.3V M X5R 0402 2 EMC_NS@
2 2
1

+3VS
Intel APU--->EC-->Pannel_0610
Reserved APU--->Pannel

1
+3VS
RV3

om
1/20W_4.7K_5%_0201
@ RV8 1 @ 2 100K_0201_5% EDP_AUX_CON_N

2
EC_BKOFF_N RV2 1 @ 20_0201_5% DISPOFF_N RV9 1 @ 2 EDP_AUX_CON_P
79 EC_BKOFF_N
100K_0201_5% JEDP1
+3VS 1
+LEDVDD 1
RV7 2 1 100K_0201_5% CPU_EDP_HPD 2
2
3

.c
3
2
4
4
RV5 5
DISPOFF_N 5
1K_0201_5% 6
INVT_PWM 6
@ 7

s
CPU_EDP_HPD 7
8
7 CPU_EDP_HPD 8
1

PANEL_PWM RV4 1 @ 20_0201_5% INVT_PWM 9

7 PANEL_PWM CPU_EDP_AUX_P 9
CV8 1 2 0.1u_0201_10V6KEDP_AUX_CON_P 10

ic
7 CPU_EDP_AUX_P 10
1

CPU_EDP_AUX_N CV9 1 2 0.1u_0201_10V6KEDP_AUX_CON_N 11

7 CPU_EDP_AUX_N 11
RV6 12
CPU_EDP_TX0_P 12
100K_0201_5% RI101 1 @ 2 0_0402_5% CV10 1 2 0.1u_0201_10V6KEDP_TX0_CON_P 13
7 CPU_EDP_TX0_P CPU_EDP_TX0_N 13
CV11 1 2 0.1u_0201_10V6KEDP_TX0_CON_N 14

at
7 CPU_EDP_TX0_N 14
LI101 EMC_NS@ 15
15
2

USB20_2_N 1 2 USB20_2_CON_N CPU_EDP_TX1_P CV12 1 2 0.1u_0201_10V6KEDP_TX1_CON_P 16

14 USB20_2_N 1 2 7 CPU_EDP_TX1_P CPU_EDP_TX1_N 16
C CV13 1 2 0.1u_0201_10V6KEDP_TX1_CON_N 17 C
7 CPU_EDP_TX1_N 17
18
USB20_2_P USB20_2_CON_P USB20_2_CON_N 18
4 3 19
For Camera

m
14 USB20_2_P 4 3 USB20_2_CON_P 19
20
EMC close to connector EXC24CH900U_4P
DMIC_CLK_CON
21 20
21
RI102 1 @ 2 0_0402_5% RA82 1 @ 2 0_0201_5% 22
DMIC_DAT_CON DMIC_CLK_CON DISPOFF_N INVT_PWM 66 CODEC_DMIC_CLK DMIC_DAT_CON 22
RA80 1 2 0_0201_5% 23
For DMIC 66 CODEC_DMIC_DAT
@
24 23

he
24
25
+3VS_MIC 25
1 1 1 1 26
100P_0402_50V8J

100P_0402_50V8J

26
27
+3VS_CAMERA 27
CA84 CA87 CV14 CV15 28
28
EMC_NS@ EMC_NS@ 470P_0402_50V_X7R_0402 470P_50V_K_X7R_0201 29 31
2 2 2 2 EMC_NS@ +LCDVDD_CON 29 GND1
EMC_NS@ 30 32
30 GND2

Sc
HIGHS_FC5AF301-3181H
ME@

ok
Touch Screen
o
eb
Touch Panel Power_Follow s750_0705
ot

B B
+3VS +3VS_TS
N

RV902
1 @ 2 0_0603_SP

1 1
CV901 TS@ CV902 TS@
1U_6.3V_M_X5R_0201 0.1U_6.3V_K_X5R_0201
2 2

confirm Pin define with ME

+3VS_TS
JTS1
1
1
2
TOUCH_PANEL_RST_N 2
3
11 TOUCH_PANEL_RST_N TOUCH_PANEL_INTR_N 3
4
12 TOUCH_PANEL_INTR_N CPU_TOUCH_EN 4
intel is PCH_TS_STOP 5
11,79 CPU_TOUCH_EN 5
6
CPU_I2C0_SDA Touch_I2C0_SDA 6
RV903 1 @ 2 0_0402_5% 7
12,24 CPU_I2C0_SDA CPU_I2C0_SCL Touch_I2C0_SCL 7
APU=>I2C0 RV904 1 @ 2 0_0402_5% 8
12,24 CPU_I2C0_SCL 8
9
9
10
10
11
GND1
12
TOUCH_PANEL_RST_N GND2
100P 25V J NPO 0201

100P 25V J NPO 0201

1
EMC_NS@

1
EMC_NS@

HIGHS_WS83100-S0171-HF
A ME@ A
2 2
CV33

CV34
100K_0201_5%
2

RV907

Intel no EMC cap,need to check with EMC_0705

@
1

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C eDP_DDI/CAM/DMIC/ISH 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, December 04, 2020 Sheet 47 of 110
5 4 3 2 1
 5 4 3 2 1

Folllow Y550 A+N_0724

HDMI Power +3VS
+3VS

1
RV500

1
+5VS +5VS_HDMI_F +5VS_HDMI
QV501
LP2301ALT1G_SOT-23-3
HPD 4.7K_0402_5%
RV501
100K_0402_5%

2
FV501 CPU_HDMI_HPD
1 3 1 2 7 CPU_HDMI_HPD

2
6
1 2 D
1.1A_8V_1206L110THYR CC1279
Q505A 2
Ihold:1.1A,Itrip:2.2A, CV501 10U 6.3V M X5R 0402

G
G
2
0.1u_0201_10V6K @
25,84 SUSP Rmax:0.21ohm 2 1

3
D S D D
2N7002KDWH_SOT363-6

1
5 HDMI_DET
G
Q505B

1
S
2N7002KDWH_SOT363-6 RV502

4
Reserved 10U CAP than common design_0630 100K_0402_5%

R910=>RV500

2
R202=>RV501
R257=>RV502
Q43=>QV505

RV518,RV521.RV524,RV515 Follow S50&550_ARE 270R

m
RV516 2 @ 1 0_0402_5% HDMI_TX0_CON_P

LV502 EXC24CH900U_4P

co
HDMI_TX0_DP_C 4 3 +5VS_HDMI
4 3
RV518
EMC_CMC@ 270_0402_1%
HDMI_TX0_DN_C 1 2 EMC@
1 2

2
1
CPU_HDMI_TX0_P CV502 1 2 0.1u_0201_10V6K HDMI_TX0_DP_C
7 CPU_HDMI_TX0_P

2
RPV501
CPU_HDMI_TX0_N CV503 1 HDMI_TX0_DN_C HDMI_TX0_CON_N

s.
2 0.1u_0201_10V6K RV517 2 @ 1 0_0402_5% 2.2K_0404_4P2R_5%
7 CPU_HDMI_TX0_N +5VS_HDMI
CPU_HDMI_TX1_P CV504 1 2 0.1u_0201_10V6K HDMI_TX1_DP_C JHDMI1
7 CPU_HDMI_TX1_P

3
4
CPU_HDMI_TX1_N CV505 1 HDMI_TX1_DN_C DDPB_CLK_U

ic
2 0.1u_0201_10V6K 18 15
7 CPU_HDMI_TX1_N +5V_Power SCL DDPB_DATA_U
16
CPU_HDMI_TX2_P CV506 1 HDMI_TX2_DP_C HDMI_TX1_CON_P SDA
2 0.1u_0201_10V6K RV519 2 @ 1 0_0402_5%
7 CPU_HDMI_TX2_P HDMI_TX0_CON_P 7
CPU_HDMI_TX2_N CV507 1 HDMI_TX2_DN_C HDMI_TX0_CON_N TMDS_Data0+
2 0.1u_0201_10V6K LV503 EXC24CH900U_4P 9 13

at
7 CPU_HDMI_TX2_N TMDS_Data0- CEC

1
HDMI_TX1_DP_C 4 3 HDMI_TX1_CON_P 4 17
CPU_HDMI_CLK_P CV508 1 HDMI_CLK_DP_C 4 3 HDMI_TX1_CON_N TMDS_Data1+ DDC/CEC_Ground HDMI_DET
2 0.1u_0201_10V6K RV521 6 19
7 CPU_HDMI_CLK_P HDMI_TX2_CON_P TMDS_Data1- Hot_Plug_Detect
C EMC_CMC@ 270_0402_1% 1 C
CPU_HDMI_CLK_NCV509 1 HDMI_CLK_DN_C HDMI_TX1_DN_C HDMI_TX2_CON_N TMDS_Data2+
2 0.1u_0201_10V6K 1 2 EMC@ 3
7 CPU_HDMI_CLK_N 1 2 TMDS_Data2-

m
2
8 14
HDMI_TX1_CON_N TMDS_Data0_Shield Utility
RV520 2 @ 1 0_0402_5% 5
TMDS_Data1_Shield
2
TMDS_Data2_Shield

20

e
GND1
11 21
HDMI_CLK_CON_P TMDS_Clock_Shield GND2
+3VS 10 22
HDMI_CLK_CON_N TMDS_Clock+ GND3
12 23

ch
TMDS_Clock- GND4

RV522 2 @ 1 0_0402_5% HDMI_TX2_CON_P

2

LV504 EXC24CH900U_4P
G

ALLTO_C128AF-K1935-L

1
HDMI_TX2_DP_C 4 3
4 3 ME@
RV524

kS
EMC_CMC@ 270_0402_1%
1 6 DDPB_DATA_U HDMI_TX2_DN_C 1 2 EMC@
S

7 CPU_HDMI_DDC_DATA 1 2
D

common desing: Rtmds 470R, On CAP with Common choke_0630

2
L2N7002KDW1T1G_SOT363-6
QV503A RV523 2 @ 1 0_0402_5% HDMI_TX2_CON_N
HDMI_TX0_CON_P RV504 1 2 499_0402_1%

o
5

HDMI_TX0_CON_N RV505 1 2 499_0402_1%

G

bo HDMI_TX1_CON_P RV506 1 2 499_0402_1%

4 3 DDPB_CLK_U RV513 2 @ 1 0_0402_5% HDMI_CLK_CON_P HDMI_TX1_CON_N RV507 1 2 499_0402_1%

S

7 CPU_HDMI_DDC_CLK
D

LV501 EXC24CH900U_4P HDMI_TX2_CON_P RV508 1 2 499_0402_1%

QV503B

1
HDMI_CLK_DP_C 4 3
L2N7002KDW1T1G_SOT363-6 4 3 HDMI_TX2_CON_N
RV515 RV509 1 2 499_0402_1%
e
EMC_CMC@ 270_0402_1%
HDMI_CLK_DN_C 1 2 EMC@ HDMI_CLK_CON_P RV510 1 2 499_0402_1%
1 2

2
HDMI_CLK_CON_N
ot

RV511 1 2 499_0402_1%
RV514 2 @ 1 0_0402_5% HDMI_CLK_CON_N
B B

1
QV504 D
2
+3VS
Need to APU Pull highg R G
EMC
N

S L2N7002KWT1G_SOT323-3

3
RV512 1 @ 2
100K_0402_5%

EMC

DV501 DV502 DV503

HDMI_TX1_CON_N 1 1 10 9 HDMI_TX1_CON_N HDMI_DET 1 1 10 9 HDMI_DET HDMI_CLK_CON_P 1 1 10 9 HDMI_CLK_CON_P

HDMI_TX1_CON_P 2 2 9 8 HDMI_TX1_CON_P DDPB_CLK_U 2 2 9 8 DDPB_CLK_U HDMI_CLK_CON_N 2 2 9 8 HDMI_CLK_CON_N

HDMI_TX2_CON_N 4 4 7 7 HDMI_TX2_CON_N DDPB_DATA_U 4 4 7 7 DDPB_DATA_U HDMI_TX0_CON_P 4 4 7 7 HDMI_TX0_CON_P

HDMI_TX2_CON_P 5 5 6 6 HDMI_TX2_CON_P +5VS_HDMI 5 5 6 6 +5VS_HDMI HDMI_TX0_CON_N 5 5 6 6 HDMI_TX0_CON_N

3 3 3 3 3 3

8 8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9

EMC_NS@ EMC_NS@ EMC_NS@

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HDMI_CONN
Date: Friday, December 04, 2020 Sheet 50 of 110
5 4 3 2 1
 5 4 3 2 1

+5VALW VBUS_P0
1 1
CU19 CU20
220P_25V_K_X7R_0201 220P_25V_K_X7R_0201

47U_6.3V_M_X5R_0805_H1.25
1 UU2

150U_B2_6.3VM_R35M
2 2

10U_0805_25V6K

4.7U_0805_25V6-K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K
1 1 1 1 1 1 1
CU1 + CU2 CU3 CU4 CU5 CU6 CU7 CU8 10K_0402_5% 2 @ 1 RU5 23 12 TYPEC_CC1
NC CC1 TYPEC_CC2 TYPEC_CC1 53
@ @ 14
D CC2 TYPEC_CC2 53 D
2 2 2 2 2 2 2 2 CU11 1 2 0.33U 10V K X5R 0402 USBC0_RX1_C_N 5 8 MUX_TX1_P CU15 1 2 0.1U_6.3V_K_X5R_0201 MUX_USBC0_TX1_P
14 USBC0_RX1_N USBC0_RX1_C_P SSRX_1N/2P C_TX1_1P/2N MUX_TX1_N CU16 1 MUX_USBC0_TX1_P 53
CU12 1 2 0.33U 10V K X5R 0402 4 9 2 0.1U_6.3V_K_X5R_0201 MUX_USBC0_TX1_N
14 USBC0_RX1_P SSRX_1P/2N C_TX1_1N/2P MUX_USBC0_TX1_N 53
CU13 1 2 0.22U_6.3V_K_X5R_0402 USBC0_TX1_C_N 7 2 MUX_USBC0_RX1_P
14 USBC0_TX1_N SSTX_1N/2P C_RX1_1P/2N MUX_USBC0_RX1_P 53
CU14 1 2 0.22U_6.3V_K_X5R_0402 USBC0_TX1_C_P 6 3 MUX_USBC0_RX1_N
14 USBC0_TX1_P SSTX_1P/2N C_RX1_1N/2P MUX_USBC0_RX1_N 53
11 MUX_TX2_P CU17 1 2 0.1U_6.3V_K_X5R_0201 MUX_USBC0_TX2_P
C_TX2_1P/2N MUX_TX2_N CU18 1 MUX_USBC0_TX2_P 53
10 2 0.1U_6.3V_K_X5R_0201 MUX_USBC0_TX2_N
TYPEC_M1 RU6 C_TX2_1N/2P MUX_USBC0_TX2_N 53
2 @ 1 0_0402_5%TYPEC_M1_R 21
79 TYPEC_M1 RP_SEL_M1
24 MUX_USBC0_RX2_P
+5VALW +5V_MUX TYPEC_M0 RU7 C_RX2_1P/2N MUX_USBC0_RX2_P 53
2 @ 1 0_0402_5%TYPEC_M0_R 22 1 MUX_USBC0_RX2_N
79 TYPEC_M0 RP_SEL_M0 C_RX2_1N/2P MUX_USBC0_RX2_N 53
+3V_MUX
TYPEC_OCP_N 16
RU3 2 @ 1 0_0402_5% VBUS_P0 OCP_DET
LDO_3V3
20 +5V_MUX
+3VALW +3V_MUX VBUS_EN RU34 1 2 10K_0402_1% VBUS_R_EN 15 RU11 1 2 0_0402_5%
change RU34 0R to 10K, @

om
+5VS VBUS_EN
ADD EC control Power ouput_SIT 0921 19 RU12 2 @ 1 0_0402_5%
5V_IN
@ RU8 1 2 1/16W_6.2K_1%_0402TYPEC_REXT 18 13 Use 5V Mode ,Follow L350_ARH_0725
REXT VCON_IN
RU1 1 2 0_0402_5% RU4 1 @ 2 0_0402_5%
RU9 1 2 200K_0402_1% VMON 17 25
+3VS VMON E-PAD

2
1 2 0_0402_5%

0.1u_0201_10V6K

10U_0603_10V6K
RU2 @ 1

1
RU10 CU21 CU22

.c
RTS5448-GR_QFN24_4X4
10K_0402_1%
3.4A

2
2
4.7U_0402_6.3V6M

1
1

CU9 CU10

s
0.1u_0201_10V6K +5VALW VBUS_P0
2

2 UU1

ic
5 1 Close Pin19
IN OUT
VBUS_EN 2
Close Pin20 GND

at
RU608 1 2 0_0402_5% 4 3 RU33 1 NPI@ 2
EN FLAG TYPEC_OCP_N 14
0_0402_5%
C G517G1TO1U_TSOT-23-5 C

QU1 add reserved MUX power control_0926

1
D

m
RU607 1 @ 2 0_0402_5% 2
52,79 EC_VBUS_EN G @
+5VL +5VALW +5V_MUX
2N7002KW_SOT323-3 S
QU3
3

e
LP2301ALT1G_SOT-23-3
@
3 1

D
ch

2
RU40

G
2
@ 100K_0402_5%

1
kS
EC_VBUS_EN RU39 1 2 0_0402_5% RU37 1 2 10K_0201_5%

@ @
+3V_MUX +3V_MUX
Rp configuration
Rp:3A (now)

oo
1
2

1
CU28
QU2 @ 0.1U_6.3V_K_X5R_0201
RU13 RU15 M1 M0 Note @ SSM3K15AMFV_2-1L1B
2
10K_0402_5% 10K_0402_5% 2
Rp:900mA 0 1 RU14/RU15 mount 52,79 EC_VBUS_EN
1

TYPEC_M1_R TYPEC_M0_R
1

3
2
Rp:1.5A 1 0
eb
RU13/RU16 mount
CU27
2

Rp:3.0A 1 1 RU13/RU15 mount @ RU38 @ 0.1U_6.3V_K_X5R_0402

100K_0402_5% 2
RU14 RU16

1
10K_0402_5% 10K_0402_5%
@ @
ot
1

B B

+3VALW
UU3
N

CU25 1 2 0.1U_6.3V_K_X5R_02018 7
+3V_MUX VCC NC

For C_VBUS CU26 1 @ 2 1U_6.3V_M_X5R_0201

USB20_0_R_P 2 3
power switch enable pin HSD+ D+ USB20_0_P 14
2

@
USB20_0_R_N 6 5
HSD- D- USB20_0_N 14
RU17
10K_0402_5% Power switch enable pin Note
@ 1 4
OE# GND
1

VBUS_EN Low Active RU17 mount 84 TYPEC_USB2_ON_N

2

High Active RU18 mount TS3USB31ERSER_UQFN8_1P5X1P5

@
RU18
100K_0402_5%
1

USB20_0_R_P RU21 2 1 0_0201_5% USB20_0_P

53 USB20_0_R_P
USB20_0_R_N RU22 2 1 0_0201_5% USB20_0_N
53 USB20_0_R_N
+3V_MUX
PU AT CPU side _0725
For C_VBUS
power switch OCP pin
2

RU19
10K_0402_5% Power switch OCP pin Note
1

TYPEC_OCP_N Low Active RU19 mount

2

High Active RU20 mount

A A
RU20
10K_0402_5%
@
1

SVT change RU19 unstuff to stuff for solve DC S5 to S0 U DISK LOSS_1204

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_MUX_PortA
Date: Friday, December 04, 2020 Sheet 52 of 110
5 4 3 2 1
 5 4 3 2 1

L350_ARH/L340_API/YOGA530 ALL use COMMON CHOCK_0725

D D

RU23 1 2 0_0402_5%
EMC_NS@

LU5 EMC@
USB20_0_R_P 1 2 USB20_0_CON_P
52 USB20_0_R_P 1 2

USB20_0_R_N 4 3 USB20_0_CON_N
52 USB20_0_R_N 4 3

EXC24CH900U_4P

RU24 1 2 0_0402_5%
EMC_NS@

GND1
GND2
GND3
GND4
VBUS_P0 VBUS_P0
RU25 2 @ 1 0_0402_5% RU29 2 @ 1 0_0402_5% JUC1

GND5
GND6
GND7
GND8
co
A1 B12
GND1 GND4
LU4 EMC_NS@ LU1 EMC_NS@
MUX_USBC0_TX1_N 1 2 USBC0_TX1_CON_N MUX_USBC0_TX2_N 1 2 USBC0_TX2_CON_N USBC0_TX1_CON_P A2 B11 USBC0_RX1_CON_P
52 MUX_USBC0_TX1_N 1 2 52 MUX_USBC0_TX2_N 1 2 SSTXp1 SSRXp1
USBC0_TX1_CON_N A3 B10 USBC0_RX1_CON_N
MUX_USBC0_TX1_P USBC0_TX1_CON_P MUX_USBC0_TX2_P USBC0_TX2_CON_P SSTXn1 SSRXn1
4 3 4 3
52 MUX_USBC0_TX1_P 4 3 52 MUX_USBC0_TX2_P 4 3

s.
A4 B9
Vbus1 Vbus4
EXC24CH900U_4P EXC24CH900U_4P
TYPEC_CC1 A5 B8
CC1 SBU2
RU26 2 @ 1 0_0402_5% RU30 2 @ 1 0_0402_5%
USB20_0_CON_P USB20_0_CON_N

ic
A6 B7
Dp1 Dn2
USB20_0_CON_N A7 B6 USB20_0_CON_P
Dn1 Dp2
RU31 2 @ 1 0_0402_5%
RU27 2 @ 1 0_0402_5% A8 B5 TYPEC_CC2

at
SBU1 CC2

C EXC24CH900U_4P A9 B4 C
EXC24CH900U_4P MUX_USBC0_RX2_N USBC0_RX2_CON_N Vbus2 Vbus3
4 3
MUX_USBC0_RX1_N USBC0_RX1_CON_N 52 MUX_USBC0_RX2_N 4 3 USBC0_RX2_CON_NA10 USBC0_TX2_CON_N
4 3 B3
52 MUX_USBC0_RX1_N 4 3 SSRXn2 SSTXn2

m
MUX_USBC0_RX2_P 1 2 USBC0_RX2_CON_P USBC0_RX2_CON_PA11 B2 USBC0_TX2_CON_P
MUX_USBC0_RX1_P USBC0_RX1_CON_P 52 MUX_USBC0_RX2_P 1 2 SSRXp2 SSTXp2
1 2
52 MUX_USBC0_RX1_P 1 2 LU2 EMC_NS@ A12 B1
LU3 EMC_NS@ GND2 GND3

GND10
GND9
RU32 2 @ 1 0_0402_5%

he
RU28 2 @ 1 0_0402_5%

GND6
GND5
ATOB_066-12A1-3211
ME@

c
VBUS_P0 USB20_0_CON_P

kS
USB20_0_CON_N
1

AZ5725-01F.R7GR_DFN1006P2X2

DU1
USBC0_TX1_CON_P 9 10 1 1 USBC0_TX1_CON_P DU3
1

1
EMC_NS@

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2
USBC0_TX1_CON_N 8 9 2 2 USBC0_TX1_CON_N DU4 DU5

1
USBC0_RX2_CON_N 7 7 4 4 USBC0_RX2_CON_N

oo
2

USBC0_RX2_CON_P 6 6 5 5 USBC0_RX2_CON_P
2

2
3 3

2
EMC_NS@ EMC_NS@
eb
8

AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

DU2 TYPEC_CC2 TYPEC_CC1

52 TYPEC_CC2 52 TYPEC_CC1
ot

B USBC0_TX2_CON_P USBC0_TX2_CON_P B
9 10 1 1

1
1

USBC0_TX2_CON_N 8 9 2 USBC0_TX2_CON_N
220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
2 DU7
AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

1
DU6 CU23 1 CU24 1
1

USBC0_RX1_CON_N 7 7 4 4 USBC0_RX1_CON_N
N

EMC_NS@ EMC_NS@
USBC0_RX1_CON_P 6 6 5 5 USBC0_RX1_CON_P EMC_NS@ EMC_NS@
2 2 2
3 3
2

2
2

AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

EMC Require stuff on frist phase , SDV output report Remove==>0804

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TYPEC_CONN_PortB
Date: Friday, December 04, 2020 Sheet 53 of 110
5 4 3 2 1
 A B C D E

USB3.0 PORT
+5VALW

+USB_VCCA

+USB_VCCA
1 JUA1
1 @ CU601
1U_10V_M_X5R_0201 UU601
+USB_VCCA close to USB Conn USB30_TX1_CON_P 9
1

2 StdA_SSTX+
5 1 1 1
IN OUT USB30_TX1_CON_N VBUS
8

150U_B2_6.3VM_R35M
1 1 StdA_SSTX-
+ USB20_1_CON_P

CU608
2 3
GND D+
@ CU602 CU603 7
EC_USB_ON_N 2 GND_DRAIN
58,79 EC_USB_ON_N @ 1EN_USB3 4 3 USB_OC2_N 100U_1206_6.3V6M 1U_0402_16V6K USB20_1_CON_N 2 10
RU35 0_0402_5%
ENB OCB USB_OC2_N 14 2 2 2 @ USB30_RX1_CON_P 6 D- GND_2
11
StdA_SSRX+ GND_3
4 12

m
USB30_RX1_CON_N GND_1 GND_4
SY6288D20AAC_SOT23-5 5 13
StdA_SSRX- GND_5

Low Active 2A

co
ALLTO_C19043-10905-L
ME@
Common Circuit only CU602,CU603
Add Reserved CU606 150U CAP_0628

s.
ic
at
2 EMC close to USB Conn 2

em
RU601 1 @ 2 0_0402_5%

EXC24CH900U_4P
USB20_1_P 4 3 USB20_1_CON_P DU601
14 USB20_1_P 4 3 USB30_RX1_CON_N USB30_RX1_CON_N
10 1

ch
NC1 Line-1
USB20_1_N 1 2 USB20_1_CON_N USB30_RX1_CON_P 9 2 USB30_RX1_CON_P
14 USB20_1_N 1 2 NC2 Line-2
LU601 EMC@ USB30_TX1_CON_N 7 4 USB30_TX1_CON_N

kS
NC3 Line-3

RU602 1 @ 2 0_0402_5% USB30_TX1_CON_P 6 5 USB30_TX1_CON_P

NC4 Line-4

oo
GND1

RU603 2 @ 1 0_0402_5% 8
GND2

CU604 AZ1143-04F-R7G_DFN2510P10E10

eb
0.33U 10V K X5R 0402 EXC24CH900U_4P EMC@
USB30_RX1_P 1 2 USB30_RX1_C_P 4 3 USB30_RX1_CON_P
14 USB30_RX1_P 4 3

3
14 USB30_RX1_N
USB30_RX1_N 1
ot 2 USB30_RX1_C_N 1
1 2
2 USB30_RX1_CON_N
USB20_1_CON_P 3
CU605 LU602 EMC_NS@ +USB_VCCA
USB20_1_CON_N
N
0.33U 10V K X5R 0402
RU604 2 @ 1 0_0402_5%

2
DU602 DU603

1
RU605 2 @ 1 0_0402_5%

CU606
0.22U_6.3V_K_X5R_0402 EXC24CH900U_4P
USB30_TX1_P 1 2 USB30_TX1_C_P 4 3 USB30_TX1_CON_P

2
14 USB30_TX1_P 4 3

3
AZ5725-01F.R7GR_DFN1006P2X2 AZ5515-02FPR7GR_DFN1006P3X
USB30_TX1_N 1 2 USB30_TX1_C_N 1 2 USB30_TX1_CON_N EMC_NS@ EMC@
14 USB30_TX1_N 1 2

CU607 LU603 EMC_NS@

0.22U_6.3V_K_X5R_0402
RU606 2 @ 1 0_0402_5%

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
USBA_PortA 0.3

Date: Friday, December 04, 2020 Sheet 57 of 110

A B C D E
 5 4 3 2 1

USB2.0 Port and CMC&TVS&CAP MOVE to SUB Board

D D

USB2.0 PORT
+5VALW

1
+USB_VCCB
@ CU401
1U_10V_M_X5R_0201
2 UU401

om
5 1
IN OUT

2
GND
EC_USB_ON_N RU36 2 @ 1 EN_USB2 4 3 USB_OC1_N
57,79 EC_USB_ON_N ENB OCB USB_OC1_N 14
0_0402_5%

SY6288D20AAC_SOT23-5

.c
Low Active 2A

s
the diffrent with Base:

ic
1.S540 No USB2.0 only,S360&V14V15 have

at
C C

m e
ch
kS
oo
eb
ot

B B
N

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. USBA_PortB
Date: Friday, December 04, 2020 Sheet 58 of 110
5 4 3 2 1
 5 4 3 2 1

HDD Power
HDD Without Redriver
+5VS +5VS_HDD

JK1 RK1 0_0201_5% CK8

1 2 SATA_PTX_DRX0_P SATA_NRE@ 1 2SATA_PTX_DRX0_R_P SATA_NRE@ 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_P
1 2 14,61 SATA_PTX_DRX0_P

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

10U_0603_10V6K

10U_0603_10V6K

0.1u_0201_10V6K

33P_0402_50V8J

33P_0402_50V8J
D JUMP_43X39 1 1 1 1 1 1 1 D
@ CK1 CK2 CK3 CK4 CK5 CK6 CK7 RK2 0_0201_5% CK9
@ @ SATA_PTX_DRX0_N SATA_NRE@ 1 2SATA_PTX_DRX0_R_N SATA_NRE@ 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_DRX0_CON_N
14,61 SATA_PTX_DRX0_N
@ RF_NS@ RF_NS@
2 2 2 2 2 2 2
RK3 0_0201_5% CK10
SATA_PRX_DTX0_N SATA_NRE@ 1 2SATA_PRX_DTX0_R_N SATA_NRE@ 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_N
14,61 SATA_PRX_DTX0_N

RK4 0_0201_5% CK11

SATA_PRX_DTX0_P SATA_NRE@ 1 2SATA_PRX_DTX0_R_P SATA_NRE@ 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_DTX0_CON_P

om
14,61 SATA_PRX_DTX0_P

.c
+3VS

s
ic
1
HDD with Redriver Only For 17' Type RK5

at
C
4.7K_0402_5%
S_8527@ CO-design with PI3EQX6741STZDEX C
SA000060400, S IC PI3EQX6741STZDEX TQFN SATA REDRIVER, A.2

m
RK23 1 @ 21/20W_4.7K_5%_0201 +3VS

@ UK1

he
CK14 1 2 0.1u_0201_10V6K SATA_RE_EN 7 10 +5VS_HDD
EN VDD1
20 1
VDD2 JHDD1

1
SATA_PTX_DRX0_P SATA_RE@ CK15 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX0_P 1
14,61 SATA_PTX_DRX0_P SATA_PTX_DRX0_N SATA_RE@ A_INP
14,61 SATA_PTX_DRX0_N CK16 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX0_N 2 6 REXT CK12 CK13 1

Sc
A_INN REXT 1
16 DEW 0.1u_0201_10V6K 0.01U_0201_10V6K 2
DEW 2

2
SATA_PRX_DTX0_P SATA_RE@ CK17 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX0_P 5 SATA_RE@ 2 SATA_RE@ 3
14,61 SATA_PRX_DTX0_P SATA_PRX_DTX0_N SATA_RE@ CK18 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX0_N 4
B_OUTP
9 A_DE 4
3
14,61 SATA_PRX_DTX0_N B_OUTN A_DE
8 B_DE SATA_PRX_DTX0_CON_P 5 4
A_EQ1 B_DE SATA_PRX_DTX0_CON_N 5
17 6

ok
A_EQ2 A_EQ1 SATA_R_PTX0_P SATA_PTX_DRX0_CON_P 6
18 15 SATA_RE@ CK19 1 2 0.01U_6.3V_K_X7R_0201 7
B_EQ1 A_EQ2 A_OUTP SATA_R_PTX0_N SATA_PTX_DRX0_CON_N SATA_PTX_DRX0_CON_N 7
19 14 SATA_RE@ CK20 1 2 0.01U_6.3V_K_X7R_0201 8 12
B_EQ2 B_EQ1 A_OUTN SATA_PTX_DRX0_CON_P 8 GND2
13 9
B_EQ2 SATA_R_PRX0_P SATA_PRX_DTX0_CON_P 9
RK22 1S_8527@ 2 11 SATA_RE@ CK21 1 2 0.01U_6.3V_K_X7R_0201 10 11

o
S_RE_GND B_INP SATA_R_PRX0_N SATA_PRX_DTX0_CON_N 10 GND1
0_0201_5% 3 12 SATA_RE@ CK22 1 2 0.01U_6.3V_K_X7R_0201
GND1 B_INN
21
EPAD
+3VS
RK31 1 S_6741@2
1/20W_4.7K_5%_0201
eb PS8527CTQFN20GTR2A2_TQFN20_4X4 ME@
HIGHS_FC5AF101-2931H

S_8527@
S_8527@
1/20W_4.7K_5%_0201 2 RK6 1 A_EQ1 1/20W_4.7K_5%_0201 2 RK7 1 @
ot
B B
1/20W_4.7K_5%_0201 2 RK24 1 @ 1/20W_4.7K_5%_0201 2 RK25 1 S_6741@

PS8257CTQ : EQ Follow S350_ARE Stuff_0717

N

2 RK8 1 A_EQ2 2 RK9 1 @

REXT：external res for output swiing adjustment
1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201
S_8527@
10K_0201_5% 2 RK26 1 @
it canbe left open or tie to GND,internally generated bias
1/20W_4.7K_5%_0201
S_8527@
2 RK10 1 B_EQ1 1/20W_4.7K_5%_0201 2 RK11 1 S_8527@ current be used and the output is as default swing setting;
1/20W_4.7K_5%_0201 2 RK33 1 @ 1/20W_4.7K_5%_0201 2 RK27 1 S_6741@
the pin canbe connected 4.99k to GND,the output swing
1/20W_4.7K_5%_0201 2 RK12 1 @ B_EQ2 1/20W_4.7K_5%_0201 2 RK13 1 S_8527@ willbe at the default value with Reference to the ex RES
1/20W_4.7K_5%_0201 2 RK32 1 @ 0_0201_5% 2 RK28 1 S_6741@

1/20W_4.7K_5%_0201 2 RK14 1 @ REXT 4.99K_0402_1% 1 RK15 2 S_8527@

DEW:De-emphasis width setting for A&B
1/20W_4.7K_5%_0201 2 RK16 1 @ DEW 1/20W_4.7K_5%_0201 2 RK17 1 @

1/20W_4.7K_5%_0201 2 RK18 1 A_DE 1/20W_4.7K_5%_0201 2 RK19 1 @

@
1/20W_4.7K_5%_0201 2 RK29 1 @
A A

1/20W_4.7K_5%_0201 2 RK20 1 B_DE 1/20W_4.7K_5%_0201 2 RK21 1 @

@ Title
10K_0201_5% 2 RK30 1 S_6741@
Security Classification LCFC Highly Confidential Information
Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
HDD 0.3

Date: Friday, December 04, 2020 Sheet 61 of 110

5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_SSD RK230 1 @ 2 0_0402_5%

Need short
J6 @ Min 3A
2 1
2 1
+3VS_SSD
JUMP_43X79

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
+3VS_SSD

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 2

12P_50V_J_NPO_0201
CK209

CK210

CK211

CK212

RF_NS@ CK217
1
CK219 CK220

1
@ @ 0.01U_6.3V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
D 2 2 2 2 2 1 @ RK232 D
EMC@ 2 10K_0402_5%

5
Change CK219 unstuff to 0.01F stuff SVT EMC Require_20201203 UK201
@

VCC

2
12,71,78 PLT_RST_N 1
IN1 SSD_RST_N
4
OUT
12 CPU_SSD_RST_N 2
IN2

GND
1
Power Follow S750_0630 MC74VHC1G08DFT2G_SC70-5

3
RK231
10K_0402_5%

2
co
+3VS_SSD
JSSD1

s.
76
GND15

1 2

ic
GND1 3.3V_1
3 4
PCIE_CRX_DTX11_N GND2 3.3V_2
5 6
14 PCIE_CRX_DTX11_N PCIE_CRX_DTX11_P PERn3 N/C_2
7 8
14 PCIE_CRX_DTX11_P PERp3 N/C_3

at
9 10
PCIE_CTX_C_DRX11_N GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V)
0.22U_6.3V_K_X5R_0201 1 2 CK201 11 12
14 PCIE_CTX_DRX11_N PCIE_CTX_C_DRX11_P PETn3 3.3V_3
0.22U_6.3V_K_X5R_0201 1 2 CK202 13 14
14 PCIE_CTX_DRX11_P PETp3 3.3V_4
C 15 16 C
PCIE_CRX_DTX10_N GND4 3.3V_5
17 18

em
14 PCIE_CRX_DTX10_N PCIE_CRX_DTX10_P PERn2 3.3V_6
19 20
14 PCIE_CRX_DTX10_P PERp2 N/C_4
21 22
PCIE_CTX_C_DRX10_N GND5 N/C_5
0.22U_6.3V_K_X5R_0201 1 2 CK203 23 24
14 PCIE_CTX_DRX10_N PCIE_CTX_C_DRX10_P PETn2 N/C_6
0.22U_6.3V_K_X5R_0201 1 2 CK204 25 26
14 PCIE_CTX_DRX10_P PETp2 N/C_7
27 28 TP377
PCIE_CRX_DTX9_N GND6 N/C_8 PLP_FDBK#
29 30 Test_Point_16MIL 1

ch
14 PCIE_CRX_DTX9_N PCIE_CRX_DTX9_P PERn1 N/C_9
31 32
14 PCIE_CRX_DTX9_P PERp1 N/C_10
33 34
PCIE_CTX_C_DRX9_N GND7 N/C_11
0.22U_6.3V_K_X5R_0201 1 2 CK205 35 36
14 PCIE_CTX_DRX9_N PCIE_CTX_C_DRX9_P PETn1 N/C_12 SATA_DEVSLP1
0.22U_6.3V_K_X5R_0201 1 2 CK206 37 38 DK202 2 @ 1 RB521CM-30T2R_VMN2M-2
14 PCIE_CTX_DRX9_P PETp1 DEVSLP(O) CPU_SATA_DEVSLP2 12
39 40

kS
PCIE_CRX_DTX8_P GND8 N/C_13
14 PCIE_CRX_DTX8_P 41 42
PCIE_CRX_DTX8_N PERn0/SATA-B+ N/C_14
14 PCIE_CRX_DTX8_N 43 44
PERp0/SATA-B- N/C_15
45 46
PCIE_CTX_C_DRX8_N GND9 N/C_16
0.22U_6.3V_K_X5R_0201 1 2 CK207 47 48
14 PCIE_CTX_DRX8_N PCIE_CTX_C_DRX8_P PETn0/SATA-A- N/C_17 SSD_RST_N
0.22U_6.3V_K_X5R_0201 1 2 CK208 49 50
14 PCIE_CTX_DRX8_P

oo
PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C SSD_CLKREQ4_R_N
51 52
CLK_PCIE_SSD_R_N GND10 CLKREQ#(I/O)(0/3.3V) or N/C PEWAKE_N
53 54 1
11 CLK_PCIE_SSD_R_N CLK_PCIE_SSD_R_P REFCLKn PEW AKE#(I/O)(0/3.3V) or N/C
55 56 TP378
11 CLK_PCIE_SSD_R_P REFCLKp N/C_18
57 58
GND11 N/C_19

SSD_DET
67
69
71
eb
N/C_1
PEDET(NC-PCIe/GND-SATA)
SUSCLK(32kHz)(O)(0/3.3)
3.3V_7
68
70
72
+3VS_SSD
SSD_SUSCLK_CON RK225 1 @ 2 0_0402_5%
SUSCLK_32K 11,71
ot
GND12 3.3V_8
73 74
GND13 3.3V_9
B 75 B
GND14
77
GND16
N

ARGOS_NASM0-S6705-TSH4
ME@

Change CK215 0.1U unstuff to 0.01F stuff SVT EMC Require_20201203

+3VALW_CPU
+3VS_SSD

SSD_DET# +3VS_SSD +3VS SATA_DEVSLP1 RK205 1 @ 2 10K_0201_5%

0--SATA
2

RK233
2.2K_0402_5% @ 1--PCIE
2

EMC@
RK237
1

10K_0402_5% @ SSD_DET CK215 1 2 0.01U_6.3V_K_X7R_0201

1
3

RK234
1

1 @ 2 0_0402_5% SSD_DET SSD_CLKREQ4_R_N SATA_DEVSLP1 RK203 2 @ 1 10K_0201_5%

12 SSD_SATA_PCIE_DET1_N SSD_CLKREQ4_N 11
@ QK202
2
2

2 LSK3541G1ET2L_VMT3
RK235
A EMC_NS@ CK221 @ 20K_0402_5% RK238 1 @ 2 0_0402_5% A
0.01U_6.3V_K_X7R_0201
1
1

Confirm wheather unStuff is default PCIE?

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. SSD
Date: Friday, December 04, 2020 Sheet 63 of 110
5 4 3 2 1
 5 4 3 2 1

FingerPrint USB2.0===>APU USB2.0_6

FP Power Control
RI8 1 @ 2 0_0402_5%

FP_PWR
+3VL LI1 EMC_NS@
QI3 LP2301ALT1G_SOT-23-3 USB20_6_N 1 2 USB20_6_CON_N
D 14 USB20_6_N 1 2 D
1FPR_PWR_OUT

10U 6.3V M X5R 0402

3 RI5 1 @ 2 0_0402_5%

D
FP@ 1 USB20_6_P 4 3 USB20_6_CON_P
14 USB20_6_P

0.1u_0201_10V6K
4 3

1
CI2 CI5
+3VL @ EXC24CH900U_4P

G
2
CI1 1 1 FP@

2
2

1
0.047U_0402_16V_X7R_0402 CI3 RI9 1 @ 2 0_0402_5%
RI2 FP@ 0.1U_6.3V_K_X5R_0201
1/20W_200K_5%_0201 @

m
FP@ 2 2
2
@

co
RI4 1 20_0201_5% FPR_PWR_EN_R RI6 1 @ 2 FPR_PWR_EN
0_0201_5%
FPR_PWR_EN_N
1

s.
RI3 1
100K_0201_5% CI4

ic
FP@ 0.1U_6.3V_K_X5R_0201
@ FP_PWR JFP1
2

2 10
FP_PWR

at
GND2
9
GND1
1

8
C 8 C

1
USB20_6_CON_N

em
7
USB20_6_CON_P 7
RI7 6
6
79 FPR_PWR_EN 2 QI1 330_0402_1% 5
FPR_DELINK_R 5
SSM3K15AMFV_2-1L1B FP@ 4
79 FPR_DELINK_R GPIO_AL0_R 4
FP@ 3
79 GPIO_AL0_R 3
3

12
1

FP_RESETN_R 2

ch
11 FP_RESETN_R GPIO_SCL_R 2
RI1 QI2 1
79 GPIO_SCL_R 1
100K_0201_5% SSM3K15AMFV_2-1L1B
FP@ FPR_PWR_EN_N_R 2 FP@ HIGHS_FC5AF081-2931H

kS
ME@
2

oo
eb
EMC ot
B
close to Conn B
N
USB20_6_CON_N
DI1 FP_PWR
FPR_DELINK_R10 1 FPR_DELINK_R USB20_6_CON_P
NC1 Line-1 FPR_DELINK_R GPIO_AL0_R FP_RESETN_R
RI12 1 @ 2
GPIO_AL0_R 9 2 GPIO_AL0_R 1/20W_4.7K_5%_0201
NC2 Line-2
1

DI2

1
FP_RESETN_R 7 4 FP_RESETN_R
NC3 Line-3
RI10 RI11 RI13
GPIO_SCL_R 6 5 GPIO_SCL_R 100K_0201_5% 1/20W_47K_1%_0201 1/20W_4.7K_5%_0201
NC4 Line-4
@ FP@ @
3
GND1

2
8
3

GND2

AZ1143-04F-R7G_DFN2510P10E10 AZ5515-02FPR7GR_DFN1006P3X
EMC_FP@ EMC_FP@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FPR 0.3

Date: Friday, December 04, 2020 Sheet 65 of 110

5 4 3 2 1
 5 4 3 2 1

the diffrent with Base MODULE:

1.Module no ra3 to DVDD_IO,S360&V14&V15 reserve
2.Module no ra5 CA21 to EC_BEEP,S360&V14&V15 reserve
Note: DVDD-IO must be equal to or smaller than DVDD
DVDD_IO
+3VALW +3VS DVDD

DVDD_IO
RA3 1 @ 2 0_0402_5% RA1 1 @ 2 0_0402_5% +1.8V_AUDIO
DVDD +5VD +5VA
Analog power for DACs, ADCs

10U 6.3V M X5R 0402

CA3 CA6 CA4 CA5
+1.8VALW

2.2U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CD@ 1

+5VD
D 1 1 2 D

0.1U_6.3V_K_X5R_0201
2 CA1 2 CA2

+5VA
RA6 1 2 0_0402_5%

2.2U_0402_6.3V6M
@
2 2 1 2
1 1

18

46

41

40

20
3
UA1

DVDD

DVDD-IO

PVDD2

PVDD1

AVDD1

CPVDD/AVDD2
Close to Pin7 2 SPKR_MUTE_N RA16 1 @ 2 0_0402_5% EC_MUTE_N
PDB EC_MUTE_N 79
14 HDA_BITCLK_AUDIO
69 HPOUT_L HPOUT_L BCLK HDA_BITCLK_AUDIO 12
27
HPOUT-L HDA_SYNC_AUDIO
15
HPOUT_R SYNC HDA_SYNC_AUDIO 12
26

m
69 HPOUT_R HPOUT-R
47 RA7 2 @ 1 100K_0402_1%
+5VD MIC2_VREFOL JD2 +3VS
28
+5VS +5VA +5VS 69 MIC2_VREFOL MIC2-VREFO-L PLUG_IN
48 JSENSE RA8 1 @ 2 0_0402_5%
MIC2_VREFOR JD1 PLUG_IN 69
29
69 MIC2_VREFOR MIC2-VREFO-R
Note: need to configuration 1*JD mode by verb table

co
RA111 @ 2 0_0402_5% LA1 1 2 1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN

10U_10V_M_X5R_0402

10U_10V_M_X5R_0402
BLM15PD600SN1D_2P
4 DMIC_DATA_R RA9 1 2 0_0402_5% CODEC_DMIC_DAT
1U_10V_M_X5R_0201

0.1u_0201_10V6K

0.1u_0201_10V6K
EMC_NS@ @
RING2_CONN GPIO0/DMIC-DATA12 CODEC_DMIC_DAT 47
30
0.1u_0201_10V6K

1 1 2 2 MIC2-L/RING2
1 2 0_0603_SP 69 RING2_CONN 5 DMIC_CLK_R RA101 2 0_0402_5% CODEC_DMIC_CLK

CA10

CA11

CA12

CA13
1 1 RA13 @ @
RING3_CONN GPIO1/DMIC-CLK CODEC_DMIC_CLK 47
31
CA9

s.
69 RING3_CONN MIC2-R/SLEEVE
6
CA8

2 2 1 1 PC_BEEP I2C-DATA
34
2 2 PCBEEP
7
I2C-CLK
Intel support WOV,,, RA9/RA10 unsfuff, DMIC Connect PCH_0701

ic
+5VA
8
VDD_STB NC1
RA12 1 2 10K_0402_5% 33
5VSTB
9

at
NC2
LINE2-R 35
69 LINE2-R LINE2-R
10
NC3
C CA8~CA13 change 6.3V to 10V _0725 LINE2-L 36 C
69 LINE2-L LINE2-L
11
NC4

em
12
NC5
+1.8V_AUDIO
+1.8VS CA14 1 2 1U_6.3V_M_X5R_0201 CBP 23 45 SPK_R+
CBP SPK-OUT-R+ SPK_R+ 69
RA2 1 @ 2 0_0402_5% CBN 24 44 SPK_R-
CBN SPK-OUT-R- SPK_R- 69
43 SPK_L-
SPK-OUT-L- SPK_L- 69

ch
42 SPK_L+
SPK-OUT-L+ SPK_L+ 69
2.2U_0402_6.3V6M 2 1 CA15 MIC2-CAP 32
MIC2-CAP
13
DC DET/EAPD
2.2U_0402_6.3V6M 2 1 CA16 VREF 38
VREF

2.2U_0402_6.3V6M 1 2 CA17 LDO3-CAP 19 16 SDATA_IN RA14 2 1 33_0402_5% HDA_SDIN0

kS
LDO3-CAP SDATA-IN HDA_SDIN0 12
2.2U_0402_6.3V6M 1 2 CA18 LDO2-CAP 21 17 HDA_SDOUT_AUDIO
LDO2-CAP SDATA-OUT HDA_SDOUT_AUDIO 12
2.2U_0402_6.3V6M 1 2 CA19 LDO1-CAP 39
LDO1-CAP
25 CPVEE
CPVEE
Follow Intel, beep need to confirm_0701 2

oo

Thermal Pad
CA20
1U_6.3V_M_X5R_0201

AVSS1

AVSS2
1

ALC3287-CG_MQFN48_6X6

37

22

49
eb
ot

B
Note: power beep function is removed from BIOS spec B
N

RA211 @ 2 0_0402_5%
CPU_BEEP RA18 1 2 4.7K_0402_5% PC_BEEP1_R CA22 1 2 PC_BEEP
12 CPU_BEEP
1

0.1U_6.3V_K_X5R_0201 RA261 @ 2 0_0402_5%

RA19
10K_0402_5%
@ RA271 @ 2 0_0402_5%
2

RA291 @ 2 0_0402_5%

RA83 1EMC_NS@ 2 0_0402_5%

HDA_SYNC_AUDIO
RA84 1EMC_NS@ 2 0_0402_5%
HDA_SDOUT_AUDIO
RA28 CODEC_DMIC_CLK HPOUT_L
HDA_BITCLK_AUDIO_R1 2 HDA_BITCLK_AUDIO
1/16W_27_5%_0402 EMC_NS@ CODEC_DMIC_DAT HPOUT_R
HDA_SDIN0 GND GNDA
22P_0201_258J
CA33

22P_0201_258J
CA34

33P_50V_J_NPO_0201
CA35 EMC_NS@

33P_50V_J_NPO_0201
CA36 EMC_NS@

CA31 EMC@
100P 25V J NPO 0201

CA32 EMC_NS@
100P 25V J NPO 0201

CA91
1000P 25V K X7R 0201

CA92
1000P 25V K X7R 0201

1 1 1 1 1 1 1 1

CA91, CA92 Is it necessary to reserve

2 2 2 2 2 2 2 2
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

A A
CA31 EMC Neli Require staff_0805

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Audio_Codec
Date: Friday, December 04, 2020 Sheet 66 of 110
5 4 3 2 1
 5 4 3 2 1

Follow s750 Bead

JSPK1 Speaker
SPK_R+ RA88 1 2 BLM15PX800SN1D_2P EMC@ SPK_R+_CONN 1
66 SPK_R+ SPK_R- SPK_R-_CONN 1
66 SPK_R- RA89 1 2 BLM15PX800SN1D_2P EMC@ 2
SPK_L+ SPK_L+_CONN 2
RA90 1 2 BLM15PX800SN1D_2P EMC@ 3 5
66 SPK_L+ SPK_L- SPK_L-_CONN 3 GND1
RA91 1 2 BLM15PX800SN1D_2P EMC@ 4 6
66 SPK_L- 4 GND2
D D

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201
HIGHS_WS33041-S0191-HF

220P_25V_K_X7R_0201
CA27

220P_25V_K_X7R_0201
CA28

220P_25V_K_X7R_0201
CA29

220P_25V_K_X7R_0201
CA30
CA23 EMC@

CA24 EMC@

CA25 EMC@

CA26 EMC@
2 2 2 2 2 2 2 2 ME@

1 1 1 1 1 1 1 1

CD@

CD@

CD@

m CD@
co
For EMC Near CODEC
the diffrent with Base MODULE: For EMC Near Conn.
1.S360&V14&V15 RA86&RA87 VALUE different with module,

s.
ic
2.for EMC TVS EMC_NS@ type different with module

at
3.GND type different
4.module no CA37&CA41 part circuit,,S360&V14&V15 reserve
C C

m
JHP1
Audio Jack

e
ch
MIC2_VREFOL RA31 2 1 2.2K_0402_5% RING2_CONN 3 G/M
66 MIC2_VREFOL HPOUT_L RA86 1 2 56_0402_5% HPOUT_L_R 1 L
RA30 1 @ 2HPOUT_L_R_C CA37 1 2 @ HPOUT_L_R 66 HPOUT_L
0_0402_5% 470P_50V_K_X7R_0201 LINE2-L CA38 1 2 1U_6.3V_M_X5R_0201 PLUG_IN 5

kS
66 LINE2-L 5
@
RA15 1 @ 2 100K_0402_1% LINE2-R CA40 1 2 1U_6.3V_M_X5R_0201 6
66 LINE2-R 6
@
HPOUT_R RA87 1 2 56_0402_5% HPOUT_R_R 2

oo
66 HPOUT_R R
MIC2_VREFOR RA36 2 1 2.2K_0402_5% RING3_CONN 4
66 MIC2_VREFOR M/G
RA35 1 @ 2HPOUT_R_R_C CA41 1 2 @ HPOUT_R_R

100P 25V J NPO 0201

100P 25V J NPO 0201

0_0402_5% 470P_50V_K_X7R_0201 7

eb
MS

CA42 EMC_NS@
100P 25V J NPO 0201

CA43 EMC_NS@
100P 25V J NPO 0201

CA44

CA45
1 1 1 1
RA85 1 @ 2 10K_0402_5% ATOB_063-RT04-0601
ME@
2 2 2 2
ot

EMC@

EMC@
B
RING3_CONN
Conector list USE 063-RT04-0701 B
66 RING3_CONN RING2_CONN
N
66 RING2_CONN HPOUT_L_R
HPOUT_R_R
PLUG_IN
66 PLUG_IN
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
1

1
47P_25V_J_NPO_0201
CA39

1 DA7 DA3 DA4 DA5 DA2

1

1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC@

2
EMC_NS@

2
2

For EMI
A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Audio_SPK/Jack 0.3

Date: Friday, December 04, 2020 Sheet 69 of 110

5 4 3 2 1
 A B C D E

1 1

m
co
s.
ic
S360_AUC

at
2 Card reader Circuit MOVE to SUB Board S360 2

USB2.0 on SUB Board

em
ch
kS
oo
eb
3 3
ot
N

4 4

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Card Reader
Date: Friday, December 04, 2020 Sheet 70 of 110
A B C D E
 A B C D E

Mini-Express Card(WLAN/WiMAX)
Copy Wlan common design
+3VS +3V_WLAN

1 1

RN1 1 @ 2 0_0603_SP

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1 1 1 1

CN1

CN2

CN3

CN4

CN5

CN6
@ @ @ @ @
2 2 2 2 2 2

+3V_WLAN

m
Close to Pin2/Pin4 Close to Pin72/Pin74 JWLAN1

1 2
USB20_7_P USB20_7_CON_P GND1 3.3VAUX1
RN34 1 @ 2 0_0402_5% 3 4
14 USB20_7_P USB20_7_N USB20_7_CON_N USB_D+ 3.3VAUX2
RN35 1 @ 2 0_0402_5% 5 6
14 USB20_7_N USB_D- LED1#
7 8

co
GND2 PCM_CLK/I2S_SCK
9 10
SDIO_CLK PCM_SYNC/I2S_WS
11 12
SDIO_CMD PCM_IN/I2S_SD_IN
13 14
SDIO_DATA0 PCM_OUT/I2S_SD_OUT
15 16
SDIO_DATA1 LED#2
17 18
SDIO_DATA2 GND11
19 20

s.
SDIO_DATA3 UART_WAKE#
21 22
SDIO_WAKE# UART_RXD
23
SDIO_RESET#

ic
KEY E
25 PIN24~PIN31 NC PIN 24
27 26

at
29 28
2 31 30 2

33 32
PCIE_CTX_C_DRX1_P GND3 UART_TXD
0.1U_6.3V_K_X5R_0201 1 2 CN8 35 34
14 PCIE_CTX_DRX1_P PCIE_CTX_C_DRX1_N PETP0 UART_CTS
1 2 CN9 37 36

m
0.1U_6.3V_K_X5R_0201
14 PCIE_CTX_DRX1_N PETN0 UART_RTS CL_RST_N_WLAN EC_TX
39 38 RN15 1 @ 2 0_0201_5%
GND4 VENDOR_DEFINED1 CL_DAT_WLAN EC_RX
41 40 RN16 1 @ 2 0_0201_5%
14 PCIE_CRX_DTX1_P PERP0 VENDOR_DEFINED2
43 42
14 PCIE_CRX_DTX1_N PERN0 VENDOR_DEFINED3
45 44
GND5 COEX3
47 46

he
11 CLK_PCIE_WLAN_R_P REFCLKP0 COEX2
49 48
11 CLK_PCIE_WLAN_R_N REFCLKN0 COEX1 SUSCLK_R
51 50 RN17 1 @ 2 0_0201_5%
WLAN_CLKREQ_Q_N GND6 SUSCLK WLAN_PERST_N SUSCLK_32K 11,63
RN7 1 @ 2 53 52 RN11 1 @ 2 0_0201_5%
11 WLAN_CLKREQ1_N CLKREQ0# PERST0# BT_OFF_N_R PLT_RST_N 12,63,78
0_0402_5% 55 54 RN18 2 1 1K_0201_5%
79 EC_WLAN_WAKE_N PEWAKE0# W_DISABLE2# WLAN_OFF_N CPU_BT_OFF_N 12
57 56 RN19 1 @ 20_0201_5%
GND7 W_DISABLE1# CPU_WLAN_OFF_N 11,12

Sc
59 58 WLAN_SMB_DATA RN20 1 @ 2 0_0201_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK EC_RX 79
61 60 RN21 1 @ 20_0201_5%
RSRVD/PETN1 I2C_CLK EC_TX 79
63 62
GND8 ALERT#
65 64 REFCLK0 1 TP107
RSRVD/PERP1 RSRVD
67 66 Test_Point_12MIL
RERVD/PERN1 UIM_SWP/PERST1#

k
69 68
GND9 UIM_POWER_SNK/CLKREQ1# +3V_WLAN
71 70
RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1#
73 72
RSRVD/REFCLKN1 3.3VAUX3
75 74

oo 77
GND10

GND15

ARGOSY_NASE0-S6701-TSH4
3.3VAUX4

GND14
76
eb
3 +3V_WLAN 3
ot

WLAN_OFF_N RPN1 1 4
CPU_BT_OFF_N 2 3
N

10K_0404_4P2R_5% +3VALW

EC_WLAN_WAKE_N RN31 1 @ 2 10K_0402_5%

WLAN_SMB_CLK RN22 1 2 100K_0201_5%

4 4

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. WLAN
Date: Friday, December 04, 2020 Sheet 71 of 110
A B C D E
 5 4 3 2 1

D D

m
co
s.
ic
LAN Circuit MOVE to SUB Board in V360 DB V14V15

at
C C

m
he
Sc
ok
e bo
ot

B B
N

A
Security Classification LCFC Highly Confidential Information Title A

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
A 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LAN_Chipset
Date: Friday, December 04, 2020 Sheet 73 of 110
5 4 3 2 1
 5 4 3 2 1

APU Thermal Sensor Follow S750_ARH_0701 Close to Charger

REMOTE1+

1
QS302

C
2
Thermal Sensor
B
1
CS304 @ LMBT3904WT1G_SOT323-3

placed nearby SO-DIMM 100P_0402_50V8J

E
2

3
D D
US301 REMOTE1-
+3VS

Refer S540-ARE RS301 1 @ 2 0_0402_5% +3VS_THU1 1 10 SEN_SMB_CK0_R RS302 1 @ 2

VCC SCL EC_SMB_CK0 7,79
0_0402_5%
REMOTE1+ 2 9 SEN_SMB_DA0_R RS303 1 @ 2
DP1 SDA EC_SMB_DA0 7,79
0_0402_5%
1
CS301 REMOTE1- 3 8 Close APU
DN1 ALERT#

0.1U_6.3V_K_X5R_0402 REMOTE2+ 4 7 F75303M_THERM# RS304 1 @ 2 10K_0402_5% REMOTE2+

2 DP2 THERM# +3VS
REMOTE2- 5 6
DN2 GND

1
QS301
Close to U1

C
F75303M_MSOP10 1 2 B
REMOTE1+ REMOTE2+ CS305 LMBT3904WT1G_SOT323-3

m
@
Address 1001_101xb 100P_0402_50V8J

E
1 1 2
CS302 CS303 Internal pull up 1.2K to 1.5V

3
2200P_25V_K_X7R_0201 2200P_25V_K_X7R_0201 R for initial thermal shutdown temp REMOTE2-

co
2 2

REMOTE1- REMOTE2-

REMOTE2+/-:
Trace width/space:10/10 mil

s.
Trace length:<8"
+3VALW
Near Air outlet

ic

1
RS305

at
C 13.7K_0402_1% C

2
NTC_V2

em

1
RS306
100K_0402_1%_NCP15WF104F03RC
over temperature threshold:
RSET=3*RTMH

2
92+/-30C

2
ch
Hysteresis temperature threshold. RS315
0_0402_5%
RS307
0_0402_5%
RHYST=(RSET*RTML)/(3*RTML-RSET) @
+5VL +5VL
+5VL 56+/-30C

1
+3VL

kS
HW thermal sensor

2
1 EC_AGND
CS306 RS309 RS310
@
0.1u_0201_10V6K

21.5K_0402_1%
2

21.5K_0402_1%
@ @
RS308 2
10K_0402_5%

1
oo
@
US302 @
1 8 TMSNS1
1

DS301 VCC TMSNS1

3 2 7 PHYST1 RS313 1 @ 2 10K_0402_5%

91 EC_ON_3VALW GND RHYST1

@ 1 TMSNS_OT 3 6 TMSNS2 RS312 1 @ 2 0_0402_5% NTC_V2

NTC_V2 79
eb

OT1 TMSNS2

2 4 5 PHYST2 RS311 1 @ 2 10K_0402_5%

79,92 EC_ON_5VALW_R OT2 RHYST2

BAT54CW_SOT323-3 G718TM1U_SOT23-8

B B
ot

FAN Follow Intel_0701

N

FAN
+5VS +5VS_FAN1 +5VS_FAN1

JFAN1
RF1 1 @ 2 0_0603_SP 79 EC_FAN1_PWM 1
1
79 EC_FAN1_SPEED 2
2
3
3
4
4
1 1 1
CF1 CF2 CF3 5
GND1
10U_0603_10V6K 10U_0603_10V6K 0.1u_0201_10V6K 6
GND2
@ @
2 2 2
HIGHS_WS33040-S0351-HF
ME@

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Sensor
Date: Friday, December 04, 2020 Sheet 77 of 110
5 4 3 2 1
 5 4 3 2 1

FPC+cable+Wire Intel Record

3VALW for LED&V360 Lanchip Power；

3VS for S360 Card Reader，V360 ISOLATE_N

V14V15: USB2.0 LAN S360: USB2.0 C&R

D
USB2.0_1 For USB2.0 Connector； D
USB2.0_6 For S360 Card Reader +USB_VCCB JIO1 +USB_VCCB
JIO2
1 37 1
1 GND1 1
2 38 2
2 GND2 2
3 3
AMD Record USB2.0_4 For USB2.0 Connector； 4 3
4
4 3
4
USB2.0_5 For S360 Card Reader +3VALW
5
6 5
6 +3VALW
5
6 5
6
7 7
7 7
8 8
+3VS 8 +3VS 8
9 9
9 9
10 10
+3VL LID_0D_SW_N 10 +3VL LID_0D_SW_N 10
11 11
78,79 LID_0D_SW_N ON/OFFBTN_N 11 78,79 LID_0D_SW_N ON/OFFBTN_N 11
12 12
78,80 ON/OFFBTN_N NOVO_N_SW 12 78,80 ON/OFFBTN_N NOVO_N_SW 12
13 13

m
78,80 NOVO_N_SW FPR_LED_AMBER_N 13 78,80 NOVO_N_SW FPR_LED_AMBER_N 13
14 14
78,79 FPR_LED_AMBER_N PWR_LED_WIT_N 14 78,79 FPR_LED_AMBER_N PWR_LED_WIT_N 14
15 15
78,79 PWR_LED_WIT_N 15 78,79 PWR_LED_WIT_N 15
For IO USB2.0 16 16
USB20_4_N 16 USB20_4_N 16
17 17
14,78 USB20_4_N USB20_4_P 17 14,78 USB20_4_N USB20_4_P 17
18 18

co
14,78 USB20_4_P 18 14,78 USB20_4_P 18
19 19
USB20_5_P USB20_5_P_R 19 USB20_5_P_R 19
RC347 1 CR@ 2 0_0402_5% 20 20
14 USB20_5_P USB20_5_N USB20_5_N_R 20 USB20_5_N_R 20
For IO C&R S360 RC348 1 CR@ 2 0_0402_5% 21 21 25
14 USB20_5_N LAN_PWR_ON_N 21 LAN_PWR_ON_N 21 GND1
22 22 26
78,79 LAN_PWR_ON_N EC_WAKE_N 22 78,79 LAN_PWR_ON_N EC_WAKE_N 22 GND2
23 23
12,78,79 EC_WAKE_N 23 12,78,79 EC_WAKE_N 23
PIN23 Intel is PCH_LAN_WAKE_N 24 24

s.
PCIE_PRX_DTX0_N 24 24
AMD IO Boad Reserd 0R to this PIN:EC_WAKE_N(EC&APU)_0708 25
14 PCIE_PRX_DTX0_N PCIE_PRX_DTX0_P 25
26 CF50241D0R0-05-NH
14 PCIE_PRX_DTX0_P 26
27 ME@
PCIE_PTX_C_DRX0_N 27
28

ic
14 PCIE_PTX_C_DRX0_N PCIE_PTX_C_DRX0_P 28
For LAN 29
14 PCIE_PTX_C_DRX0_P 29
30
CLK_PCIE_LAN_N 30
31
11 CLK_PCIE_LAN_N CLK_PCIE_LAN_P 31
32
11 CLK_PCIE_LAN_P

at
32
33
LAN_CLKREQ_N 33
34
11 LAN_CLKREQ_N EC_LAN_WAKE_N 34
C EC_LAN_WAKE_N: Lan to EC GPJ7 For V360 35 C
79 EC_LAN_WAKE_N PLT_RST_N 35
36
12,63,71 PLT_RST_N 36

em
20_0402_5% 1

20_0402_5% 1

20_0402_5% 1

20_0402_5% 1
HIGHS_FC5AF361-1151H

RL24
0_0402_5%
RL25

RL23

RL22

RL21
ME@

2
V14V15@ V14V15@ S360@ S360@

ch
V14V15@

kS
oo
eb
ot

B B
N

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Sub Board CONN
Date: Friday, December 04, 2020 Sheet 78 of 110
5 4 3 2 1
 5 4 3 2 1

+3VL +3VL_EC +3VL_EC +3VL_EC_R +3VS VCC_LPC_ESPI +1.8VALW VCC_FSPI

RE5 1 @ 2 0_0603_SP RE2 1 @ 2 0_0603_SP RE3 1 @ 2 0_0402_5% RE4 1 @ 2 0_0402_5%

CE1
0.1U_6.3V_K_X5R_0201

CE7
0.1U_6.3V_K_X5R_0201

CE2
0.1U_6.3V_K_X5R_0201

CE3
0.1U_6.3V_K_X5R_0201

CE8
0.1U_6.3V_K_X5R_0201

CE4
0.1U_6.3V_K_X5R_0201

CE5
0.1U_6.3V_K_X5R_0201
1 1 1 1 1 1 1 1

CE6
1000P_50V_K_X7R_0201
@ @

0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201
2 2 2 2 2 2 2 2

CE9
1

CE10
1
RE8 1 @ 2 0_0603_SP
2
2
D D

EC_AGND

Note:_20201104
SA00008Q310 VCC_LPC_ESPI VCC_FSPI
S IC IT8227VG-128/CX BGA 128P CONTROLLER
+3VL_EC +3VL_EC_R

+3VS

EC_FAN1_PWM_R RE9 2 @ 1 10K_0402_5%

UE1 PCH_EC_ENBKL RE116 2 @ 1 10K_0402_5%

EC_FAN1_SPEED 1 2 10K_0201_5%
Used LPC Intetface RE11

D10

K10
IT8227VG-128-CX_VFBGA128

D4
D5

K4

E6
E9

E4
J5
EC_TP_ON_R RE120 1 @ 2 10K_0201_5%

om
1 2 0_0402_5% EC_ESPI_IO0 K1 A10
RE19 @ For Thermal Sensor

VCC

AVCC
VFSPI
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

VSTBY(PLL)
11,24 LPC_ESPI_IO0 1 2 0_0402_5% EC_ESPI_IO1 J2 EIO0/LAD0/GPM0(3) SMCLK0/GPF2
B10 EC_SMB_CK0 7,77
RE20 @
11,24 LPC_ESPI_IO1 1 2 0_0402_5% EC_ESPI_IO2 J1 EIO1/LAD1/GPM1(3) SMDAT0/GPF3
B3 EC_SMB_DA0 7,77
RE24 @ SM BUS
11,24 LPC_ESPI_IO2 1 2 0_0402_5% EC_ESPI_IO3 H2 EIO2/LAD2/GPM2(3) SMCLK1/GPC1
B2 EC_SMB_CK1 87,89
11,24 LPC_ESPI_IO3
RE25 @
EC_ESPI_RST_N M4 EIO3/LAD3/GPM3(3) SMDAT1/GPC2
B1 TE5 1 @
EC_SMB_DA1 87,89 For Charger/Battery FOR PMIC 5028
+3VL_EC
EC_ESPI_CLK ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3)
RE27 1 @ 2 0_0402_5% K2 C1 EC_TOUCH_EN_R RE129 1 @ 2 0_0201_5% GPF6 add Type-c Load switch control_0921
11,24 LPC_ESPI_CLK EC_ESPI_CS_N ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) CPU_TOUCH_EN 11,47
RE22 1 @ 2 0_0402_5% H1 RPE8
11,24 LPC_ESPI_CS_N ECS#/LFRAME#/GPM5(3) EC_SMB_CK3 4 1 2.2K_0404_4P2R_5%
EC_SMB_DA3 3 2

c
RE46 1 @ 2 0_0402_5% PCH_EC_ENBKL F1
7 EC_ENBKL G2 GA20/GPB5(3)
A11 EC_ON_APU_ALW_R RE34 1 2 0_0402_5% EC_USB_ON_N RE148 1 2 100K_0201_5%
11,24 SERIRQ SERIRQ @
EC_SMI_N ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 PBTN_OUT_N EC_ON_APU_ALW 84
RE115 1 @ 2 0_0402_5% L2 LPC B11

s.
12 EC_PCH_SMI_N EC_SCI_N PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 PBTN_OUT_N 12
RE36 1 @ 2 0_0402_5% N4 PS/2 D9 EC_CAPS_LED_R_N RE111 1 @ 2 0_0402_5% GPF5 S750_ARH use EC_USM ,Pull 3/5_ECUSM
11 EC_PCH_SCI_N EC_WRST_N L1 ECSCI#/GPD3 PS2CLK2/GPF4
B9 EC_USM_3VALW_R RE81 1 2 0_0402_5% CAPS_LED_N 12,81 LAN_WAKE_N_R 1 LAN@ 2 10K_0201_5%
@ S360 use EC_ESM_3VALW,,, RE149
1 2 0_0402_5% KBRST_R_N H4 WRST# PS2DAT2/GPF5 EC_USM_3VALW 91
RE98 @
11 KBRST_N KBRST#/GPB6(3) 5VALW use other PIN

IT8227 EC_TP_EN_N 1 @ 2 100K_0402_5%

ic
RE150
M5 FPR_LED_AMBER_N Follow intel_0707
PWM0/GPA0
N5 EC_FPR_LED_AMBER_NRE136 1 FP@ 2 0_0201_5% PWR_LED_WIT_N 78
Note:RE136 can not modify OR
VFBGA
PWM1/GPA1 FPR_LED_AMBER_N 78
M6
EC_RTCRST E5 PWM2/GPA2
N6 BATT_LOW_LED 80
+3VL_EC
EC_TP_EN_N D2 CRX0/GPC0 PWM3/GPA3
K6 EC_FAN1_PWM_R RE10 1 2 0_0402_5% EC_KB_BKL_EN 81
CIR @

at
83 EC_TP_EN_N CTX0/TMA0/GPB2(3) SMCLK5/PWM4/GPA4
J6 PM_SLP_S5_N EC_FAN1_PWM 77 EC_SMB_CK1 1 4 2.2K_0404_4P2R_5%
RPE3
SMDAT5/PWM5/GPA5 PM_SLP_S5_N 12,24 EC_SMB_DA1 2 3
C
EC_PROCHOT
PWM C
GPD5 FUNCTION Follow Intels360_ITL B13
DAC4/DCD0#/GPJ4(3) LID_0D_SW_N
TE4 @ 1 D1 M11 RE12 1 2 100K_0402_5%
EC_LAN_PWR_ON FDIO3/DSR0#/GPG6 TACH0A/GPD6(3)
M12 EC_USM_5VALW_R RE141 EC_FAN1_SPEED 77 EC_ON_3VALW_R
RE135 1 @ 2 0_0201_5% N7 1 @ 2 0_0402_5% RE37 1 @ 2 100K_0402_5%

em
78 LAN_PWR_ON_N GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) EC_USM_5VALW 92 EC_ON_5VALW_R
RE139 1 @ 20_0201_5% => RE38 1 2 100K_0402_5%
65 FPR_PWR_EN C12 C2 EC_FPR_DELINK 2 0_0201_5% FPR_DELINK_R EC_ON_1.8VALW
RE15 1 @ => RE39 1 2 100K_0402_5%
95 EC_VR_ON DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3)
E1 SUSP_N FPR_DELINK_R 65 EC_ON_APU_ALW_R 1 2
TMRI1/GPC6(3) SUSP_N 84,93,96 FPR_DELINK_R Follow Intel_0707 RE40 @ 100K_0402_5%
M1
71 EC_TX M2 TXD/SOUT0/LPCPD#/GPE6 EC_R_VBUS_EN 1 2 100K_0402_5%
RE152 @
71 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) NUM_LED_N 1 2 100K_0402_5%
RE44
F10 A5 NOVO_N @
89 ADP_I EC_APU_OCPL ADC5/DCD1#/GPI5(3) GPE4 PM_SLP_S3_N NOVO_N 80
RE99 NC P_APU_OCPL power Reserved95 RE99 1 @ 2 0_0402_5% F12 UART port N1
P_APU_OCPL 1 2 0_0402_5% PSYS_R E13 ADC6/DSR1#/GPI6(3)
WAKE UP RI1#/GPD0(3)
N3 EC_USB_ON_N PM_SLP_S3_N 12
RE49 @
89 PSYS ADC7/CTS1#/GPI7(3) RI2#/GPD1 EC_USB_ON_N 57,58

ch
RE151 1 2 0_0402_5% EC_R_VBUS_EN N8
52 EC_VBUS_EN
@
EC_BATT_CHG_LED RTS1#/GPE5 GPD1 Follow Intel s360 ITL
RE42 1 @ 2 0_0402_5% K7
80 BATT_CHG_LED EC_SYS_PWROK F4 PWM7/RIG1#/GPA7
A1 EC_ON_5VALW_R
12
93
EC_SYS_PWROK
EC_SMB_DA3
EC_SMB_DA3
EC_SMB_CK3
D7
E8
FDIO2/DTR1#/SBUSY/GPG1/ID7
CTX1/SOUT1/GPH2/SMDAT3/ID2
RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
PWRSW/GPB3
B4
A2 EC_ON_3VALW_R
EC_ON_5VALW_R
ON/OFF_N 80
77,92
GPG2
For PMIC LV5028 93 EC_SMB_CK3 CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4
A3 LID_0D_SW_N_EC RE54 1 @ 2 0_0402_5% EC_ON_3VALW_R 91 when mirror, GPG2 pull high
SPI_CLK_R GPB1 LID_0D_SW_N 78 when no mirror, GPG2 pull low
RE125 1 @ 20_0201_5% B5 A4 ACIN +3VL_EC
11,27 SPI_CLK EC_SPI_CS0_R_N FSCK GPB0
RE126 1 20_0201_5% A7

kS
@
11,27 CPU_SPI_CS1_N EC_SPI_SI_R FSCE# EC_0.75VALW_EN
RE127 1 @ 20_0201_5% B6 EXTERNAL SERIAL FLASH GPG2 RE45 1 2 100K_0402_5%
11,27 CPU_SPI_D0 EC_SPI_SO_R FMOSI EC_0.75VALW_EN 93
RE128 1 @ 20_0201_5% A6 G10
11,27 CPU_SPI_D1 FMISO ADC0/GPI0(3)
G13 NTC_V1_R RE114 1 LAN@ 2 0_0402_5% V14V15 EC to APU For LAN RE47 1 @ 2 10K_0402_5%
K13 ADC1/GPI1(3)
G12 BATT_TEMP_EC 1 2 EC_WAKE_N 12,78
KSO16 RE52 @ 0_0402_5% Note:RE114 can't modify OR
J10 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3)
F9 NTC_V2_R 1 2 BATT_TEMP 87,89
KSO17 RE69 @ 0_0402_5%
EC_VPP_PWREN M7 KSO17/SMISO/GPC5(3) ADC3/GPI3(3)
F13 NTC_V2 77
RE113 1 @ 2 0_0402_5%
93 EC_VPP_PWREN PWM6/SSCK/GPA6 ADC4/GPI4(3) CPU_VR_READY_EC 1 2 EC_WLAN_WAKE_N 71
RE77 @ 0_0402_5%
CPU_VR_READY 95

GPG0
HW strapping. When EC power on, can not be high
***** GPG2
GPG0

KSO0
KSO1
KSO2
KSO3
***** E7
E2

M8
J7
N9
M9
SSCE0#/GPG2
SSCE1#/GPG0

KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
SPI ENABLE
oo A/D D/A
TACH2A/GPJ0
TACH2B/GPJ1
DAC2/TACH0B/GPJ2(3)
DAC3/TACH1B/GPJ3(3)
E12
D13
D12
C13
EC_MUTE_N
EC_TP_ON_R
EC_BKOFF_N
RE133 1 @ 2 0_0201_5% ALW_PWRGD
0.75VALW_PG
EC_MUTE_N
EC_TP_ON_R
EC_BKOFF_N
79,91
93
66
83
47
ALW_PWRGD is +3VALW PWRGD_0708
EC_ON_3VALW_R

EC_0.75VALW_EN

SUSP_N
RE119

RE57
1 @

1
2 100K_0402_5%

2 100K_0402_5%

KSO4 K8 RE60 1 2 100K_0402_5%

eb
KSO4/PD4
KSO[0..17] KSO5 J8
81 KSO[0..17] N10 KSO5/PD5 EC_BKOFF_N 2 1 10K_0402_5%
KSO6 RE64
KSO6/PD6
KSO7 M10
KSO7/PD7 EC_VR_ON
KSO8 N11 EC_LAN_WAKE_N Follow s360 intel_0707 RE117 1 2 100K_0402_5%
KSO8/ACK#
KSI[0..7] KSO9 K9
81 KSI[0..7] N12 KSO9/BUSY BATT_LOW_LED 1 2 100K_0402_5%
KSO10 RE118 @
KSO10/PE LAN_WAKE_N_R
KSO11 N13 G1 RE134 1 @ 2 0_0201_5% V360: LAN to EC For LAN
M13 KSO11/ERR# GPJ7
F2 EC_AC_PRESENT 1 2 0_0402_5% EC_LAN_WAKE_N 78 EC_ON_5VALW_R 1 2 100K_0402_5%
KSO12 CLOCK RE74 @ => RE17 @
ot

L12 KSO12/SLCT GPJ6 AC_PRESENT 12

KSO13
KSO13 EC_VPP_PWREN
B +3VL_EC KSO14 L13 RE130 1 2 100K_0201_5% B
KSO14
KSO15 K12 KBMX B12 NUM_LED RE48 1 @ 2 0_0402_5% NUM_LED_N NUM_LED_N 12,81 NUM_LED_N Follow S550_are,
KSO15 EGCLK/GPE3
A12 EC_TP_INT_R_N RE109 1 @ 2 0_0402_5% Now reserved
EC_USM_3VALW RE131 1 2 100K_0402_5%
EGCS#/GPE2
A13 GPIO_AL0 PCH_TP_INT_N 12,83
RE138 1 @ 2 0_0201_5%
EGAD/GPE1 GPIO_AL0_R 65 SYSON_VDDQ
1

KSI0 J12 GPIO_AL0_R Follow Intel_0707 RE132 1 2 100K_0201_5%

N

KSI0/STB#
1

RE94 KSI1 J13

KSI1/AFD# CPU_PROCHOT_N
DE3 100K_0201_5% KSI2 J9 N2 RE147 1 @ 2 100K_0201_5%
H12 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0
M3 TYPEC_M1 52
RB521CS-30GT2RA_VMN2-2 @ KSI3
KSI3/SLIN# SMDAT4/L80LLAT/GPE7 TYPEC_M0 52
2

KSI4 H9 GPIO GPG0 RE145 1 @ 2 100K_0201_5%

KSI4
2

H10 J4 GPIO_SCL RE137 1 2 0_0201_5%

EC_WRST_N
KSI5
KSI5 GPH7
@
PIMC_PWR_EN GPIO_SCL_R 65 GPIO_SCL_R Follow Intel_0707 EC_ON_1.8VALW
KSI6 H13 B7 RE146 1 @ 2 100K_0402_5%
G9 KSI6 ID6/GPH6
A8 EC_CPU_THERMTRIP_N 1 2 0_0402_5% PIMC_PWR_EN 93
1U_6.3V_M_X5R_0201

1 KSI7 RE65 @
WRST# MIN 10us KSI7 ID5/GPH5
B8 SYSON_VDDQ CPU_THERMTRIP_N 7
CE23

ID4/GPH4
A9 EC_ON_1.8VALW SYSON_VDDQ 93
ID3/GPH3
D8 EC_RSMRST_N EC_ON_1.8VALW 93 EC_USM_5VALW
RE80 1 @ 2 0_0201_5% RE142 1 2 100K_0402_5%
VCORE

2 CLKRUN#/ID0/GPH0 EC_RSMRST_N_R 12
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5
D6
F5

H5
G4
G5

E10

K5 VCOREVCC

H_PROCHOT_N For PMIC H_PROCHOTH(Power reserved)_0708

RE140 1 @ 2 0_0402_5% EC_AGND
93 H_PROCHOT_N
2
RE88 1 @ 2 0_0402_5% CPU_PROCHOT_N 7 CE11
89 VR_HOT_N
0.1U_6.3V_K_X5R_0201
1 +3V_RTC +3VL_EC CPU_VR_READY CE12 1 2 EMC_NS@ 0.1U_6.3V_K_X5R_0201
EC_PROCHOT RE58
1

1 @ 2 0_0402_5% 1
PCH_TP_INT_N CE13 1 2 EMC_NS@ 0.01U_6.3V_K_X7R_0201
@ CE16
PM_SLP_S5_N

2
RE90 47P_25V_J_NPO_0201 RE112 1 @ 2 0_0201_5% CE14 1 2 EMC_NS@ 1000P_50V_K_X7R_0201
2
EC_PROCHOT_R

1/20W_100_5%_0201 EMC_NS@ RE143

2

100K_0201_5% PM_SLP_S3_N CE15 1 2 EMC_NS@ 1000P_50V_K_X7R_0201

3
+3VL EC_RSMRST_N CE24 1 2 EMC_NS@ 1000P_50V_K_X7R_0201

1
PIMC_PWR_EN
ACIN RE89 1 2 100K_0402_5% EC_RTCRST 1 BATT_TEMP CE19 1 2 EMC_NS@ 100P 25V J NPO 0201
1

2
ACIN 89 QE2 ACIN CE20 1 2 EMC_NS@ 100P 25V J NPO 0201
1

D RE92 L2SK3541M3T5G_SOT723-3
EC_PROCHOT 2 @ @ 10K_0201_5% @ RE144 ON/OFF_N CE21 1 2 EMC_NS@ 1U_6.3V_M_X5R_0201
G QE4 2 100K_0402_5%
L2N7002KWT1G_SOT323-3 @ EC_ESPI_RST_N CE22 1 2 EMC_NS@ 220P_25V_K_X7R_0201
2

1
S
A A
3

CPU_THERMTRIP_N CE45 1 @ 2 100P_50V_J_NPO_0201

EMC_NS@
EC_ESPI_CLK RE103 1 2 10_0402_5% CE48 1 2 10P_0201_25V8G
EMC_NS@

For ESD
RE82 1 @ 2 0_0201_5% ALW_PWRGD_R DE1 1 @ 2 EC_RSMRST_N_R
1 2 0_0402_5% EC_ESPI_RST_N 79,91 ALW_PWRGD
RE96 @
11,24 CPU_LPC_RST_N
RB521CM-30T2R_VMN2M-2

Security Classification LCFC Highly Confidential Information Title

Used for surprise shutdown Power sequence S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EC
Date: Friday, December 04, 2020 Sheet 79 of 110
5 4 3 2 1
 5 4 3 2 1

NOVO BUTTON PWR BUTTON

Nove button:follow S750 RI504 0R , Intel 2.2k

+3VL

+3VL

1
1
RI503
RI501 100K_0402_5%
100K_0402_5%

2
D D
RI504 1 @ 2 0_0201_5%
79 ON/OFF_N ON/OFFBTN_N 78

2
78 NOVO_N_SW RI502 1 @ 2 0_0201_5%
NOVO_N 79

2
SHORT PADS

SHORT PADS
JBT1

JBT2
@ @

1
don't short
One for each side

RI403 1 2 1/16W_560_1%_0402

m
+5VALW
LOW LED/CHG_LED Follow LED_0705
PWM
LED BATT_LOW_LED 1
LEDI1
2 BATT_LOW_LED_N_R RI401 1 @ 2 470_0402_5%

co
79 BATT_LOW_LED +3VALW

AZ5123-01F.R7GR_DFN1006P2X2
BATT_LOW_LED L-C192JFCT-LCFC_SUPER_AMBER

1 DI401
1

EMC_NS@

s.
2

ic
2

GPIO

at
LEDI2
C BATT_CHG_LED 1 2 BATT_CHG_LED_N_R RI402 1 2 1/16W_560_1%_0402 C
79 BATT_CHG_LED +5VALW

BATT_CHG_LED L-C192WDT-LCFC_WHITE

m
1

DI402
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@

he
2
2

Sc
ok
bo
Power LED
check S750_ARH IO Board_0705
e
ot

B B
N

Grudual 1s on ,Gradual 1s off ,2s off

LED State LED Behavior

State White_on(battery： 21%~100%)

System on
(Same as the 500ms on,500ms off(battery： 0%~20%)
power button
LED) Standby
LID closed
System off OFF

Battery only OFF

Charging Amber_on(battery： 1%~90%)

A Charging A
White_on(battery： 91%~100%)

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LED/Button
Date: Friday, December 04, 2020 Sheet 80 of 110
5 4 3 2 1
 5 4 3 2 1

K/B Connector KSI[0..7]

KSI[0..7] 79
KSO[0..17]
KSO[0..17] 79
KB Backlight Connector +5VS +VCC_KB_LED

RI206 1 2 100_0402_1%
+3VS
JKB1 RI201 1 @ 2 0_0603_SP
RI207 1 @ 2 0_0402_5% PWR_CAPS_LED 1
+3VALW CAPS_LED_N_CON 1
2

0.1u_0201_10V6K
2
KSO15 3

CI201
3 1
KSO10 4
4
KSO11 5
5
KSO14 6 @
6 2
KSO13 7
D 7 D
KSO12 8
8 +VCC_KB_LED
KSO3 9
9
KSO6 10 JKBL1
10
KSO8 11 6
11 GND2
KSO7 12 5
12 GND1
KSO4 13
13
KSO2 14 4
14 4
KSI0 15 3
15 3
KSO1 16 2
16 EC_KB_BKL_Q_EN LED_KB_C 2
KSO5 17 RI203 1 @ 2 0_0603_SP 1
17 1
KSI3 18
18
KSI2 19 HIGHS_FC1AF040-1201H
19 1
KSO0 20 ME@
20 D
KSI5 21 EC_KB_BKL_EN
21 2
KSI4 22 79 EC_KB_BKL_EN KBL@
22 G
KSO9 23

om
23 S
KSI6 24
24

1
KSI7 25 3
25 QI201
KSI1 26 RI202
26 PJA138K_SOT23-3
KSO16 27 KBL@ 100K_0402_5%
27
KSO17 28
NUM_LED_N_CON 28
29
29

2
30
PWR_Fnlk_LED 30
RI213 1 2 100_0402_1% 31

.c
+3VS 31
+3VALW RI214 1 @ 2 0_0402_5% 32
Fnlk_LED_N_CON 32
33 36
33 GND2
34 35
34 GND1

s
HIGHSTAR_FC8AF341-3201H
ME@

ic
the diffrent with module:

at
C
1.modulel No 15 KB,S360&V14V15 have C

m
K/B Connector

e
+3VS +3VALW +3VALW_KBD

ch
CAPS_LED_N_CON NUM_LED_N_CON PWR_CAPS_LED Fnlk_LED_N_CON
RI508 1 @ 2 0_0402_5%

kS
RI509 1 @ 2 0_0402_5%

100P_0402_50V8J

100P 25V J NPO 0201

100P_0402_50V8J

100P_0402_50V8J
1 1 1 1
CI206 CI207
EMC_NS@ EMC_NS@ CI208 CI310
EMC_NS@ EMC_NS@
2 2 2 2

Fnlk_LED#_Follow S550_are_0706
+3VALW_KBD
oo +3VALW_KBD
eb
1

1
RI72 RI518
10K_0402_5% 10K_0402_5%

@ @
2

2
ot

RI217 1 @ 2 0_0402_5% Fnlk_LED_N_CON RI519 1 @ 2 0_0402_5% CAPS_LED_N_CON

B B
1

1
D D
14 KB_FN_LED_N
KB_FN_LED_N 2 QI14
12,79 CAPS_LED_N
CAPS_LED_N 2 QI203 close to Conn
N

G 2N7002KW_SOT323-3 G 2N7002KW_SOT323-3

EMC
1

1 @ S 1 @ S
3

3
RI73 RI520
CI209 100K_0402_5% CI313 100K_0402_5%
EMC_NS@ EMC_NS@ CAPS_LED_N_CON NUM_LED_N_CON Fnlk_LED_N_CON
2 100P_50V_J_NPO_0201 @ 2 100P_50V_J_NPO_0201 @
2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
1

1
DI201 DI202 DI203

1
EMC@

EMC@

EMC@
ADD Number LED

2
+3VALW_KBD

2
1

RI512
10K_0402_5%
@ CI209/CI313/CI311 unstuff_SIT_1003
2

RI513 1 @ 2 0_0402_5% NUM_LED_N_CON

1

D
NUM_LED_N 2 QI44
12,79 NUM_LED_N G 2N7002KW_SOT323-3
1

A 1 @ S A
3

RI514
CI311 100K_0402_5%
EMC_NS@
2 100P_50V_J_NPO_0201 @
2

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KB/KBBL CONN
Date: Friday, December 04, 2020 Sheet 81 of 110
5 4 3 2 1
 5 4 3 2 1

(the diffrent with Base MODULE:

Touch Pad 1.Module no RI306,S360&V14&V15 Rerserve) Intel 备注
Need support wake up by touch pad
Follow latest UE spec

+3VALW TP_PWR

TP_PWR
D
+3VS RI301 1 @ 2 1/10W_0_5%_0603 D
JTP1
1
PCH_I2C1_SCL_TP 1
RI306 1 @ 2 0_0603_SP RI305 1 @ 2 0_0201_5% 2
12 CPU_I2C1_SCL PCH_I2C1_SDA_TP 2
RI304 1 @ 2 0_0201_5% 3
12 CPU_I2C1_SDA 3
4
4
1 5
5
CI309 6
TP_INT_N 6
0.1U_6.3V_K_X5R_0201 RI303 1 @ 2 0_0201_5% 7
12,79 PCH_TP_INT_N TP_ON 7
RI302 1 @ 2 0_0201_5% 8
2 79 EC_TP_ON_R 8
9

0.01U_0201_10V6K
GND1
10

om
1 GND2
TP_PWR
EMC@

CI314
HIGHS_FC5AF081-2931H
2
ME@
RI506 1 2 10K_0201_5% PCH_TP_INT_N

.c
ADD CK314 SVT EMC Require_20201203

s
PCH_I2C1_SCL_TP

ic
TP_PWR PCH_I2C1_SDA_TP
TP_Power Reserved_0725

2
at

100P 25V J NPO 0201

CI301

AZ5123-01F.R7GR_DFN1006P2X2
DI301

100P 25V J NPO 0201

CI302

AZ5123-01F.R7GR_DFN1006P2X2
DI302
1 1

2
C C
1

m
+3VALW

CI306
0.1U_6.3V_K_X5R_0201

EMC_NS@

EMC@

EMC_NS@

EMC@
LP2301ALT1G_SOT23-3
2 2
QI5 3 1 2

1
S

e
0.01U_0201_10V6K

1
1 @ 1
CI304

G
2

ch
0.1u_0201_10V6K @

@
@ 2 2

CI305
EC_TP_EN_N @
RI307 1 2 4.7K_0402_5%
79 EC_TP_EN_N

kS
1 1
CI303 C188
0.01U_25V_K_X5R_0201 @ 0.1u_0201_10V6K
@
2 2

oo
Reserved for S5 Close TP_PWR_0725
eb
Follow S750_ARH ,S750_ARH APU USE S5 Power, SO Reserve Mosfet_0708 TP If use +3VALW powrer ,need to levelshift_need to check_0702
AUP VS +3VS TP_PWR
ot

TP_PWR
B B

2
1
RPI1
N

2.2K_0404_4P2R_5%
2

5
G
10K_0201_5%

3
4
RI308

@
2

@
G

CPU_I2C1_SDA RI510 1 2 0_0402_5% 4 3 PCH_I2C1_SDA_TP

S
1

D
PCH_TP_INT_N 1 3 TP_INT_N @ QI4B

2
2N7002KDWH_SOT363-6
D

G
@

QI6 @
L2N7002KWT1G_SOT323-3
CPU_I2C1_SCL RI511 1 2 0_0402_5% 1 6 PCH_I2C1_SCL_TP
S

D
@ QI4A 2N7002KDWH_SOT363-6
@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
TouchPad CONN 0.3

Date: Friday, December 04, 2020 Sheet 83 of 110

5 4 3 2 1
 A B C D E

3VS/5VS

+3VALW

+5VL +5VALW
1
CR1 +3VS
UR1

1
1U_6.3V_M_X5R_0201 J3 @
2 +3VS_LS

1
1 14 1 2 RR3
VIN1_1 VOUT1_2 1 2
2 13 1 RR4
VIN1_2 VOUT1_1
CR3 JUMP_43X79 100K_0402_5% @ 100K_0402_5%
RR1 1 @ 2 0_0201_5% 3VSON 3 12 3VS_CT1
1 2 1000P_50V_K_X7R_0201 @ CR4
1 79,84,93,96 SUSP_N 1

2
ON1 CT1
0.1U_6.3V_K_X5R_0201
2

2
+5VALW 4 11 SUSP
VBIAS GND 25,50 SUSP
CR7
RR2 1 @ 2 0_0201_5% 5VSON 5 10 5VS_CT2
1 2 1000P_50V_K_X7R_0201
ON2 CT2
+5VS
6 9 J5
7 VIN2_1 VOUT2_2
8 +5VS_LS 1 2
VIN2_2 VOUT2_1 1 2

0.01U_6.3V_K_X7R_0201
CR12

0.01U_6.3V_K_X7R_0201
CR13
1 1 1

1
15 JUMP_43X79 D
GPAD
@ CR14 79,84,93,96 SUSP_N 2 QR1
@ 0.1u_0201_10V6K
TPS22976DPUR_WSON_2X3 G L2N7002KWT1G_SOT323-3
2 2 +5VALW 2
@ @ S

3
1
CR15

m
1U_10V_M_X5R_0201
2

QR1 change 2N7002 footprint SOT363-6 to sot323-3

co
TO +3VALW_APU

s.
+3VALW_CPU
+3VALW need to short

ic
@
+3VL J9 1 2 JUMP_43X39
1 2

@
QC15
LP2301ALT1G_SOT-23-3

at
3 1

D
2
2 2

RR6

G
2
100K_0402_5%

em
1

RR26 1 @ 2 RR7 1 2 10K_0201_5%

52 TypeC_USB2_ON_N
0_0402_5%
@

1
1

CR20

ch
QR2 @ 0.1U_6.3V_K_X5R_0201
SSM3K15AMFV_2-1L1B
2 2
79 EC_ON_APU_ALW
1
3
2

CR19

kS
RR5 @ 0.1U_6.3V_K_X5R_0402
100K_0402_5% 2
1

oo
TO +0.75VS eb
AON6324
VDS=30V VGS=+_12V, ID=85A,
Rds=2.8mohm @ VGS=10V
+0.75VALW QR3 +0.75VS +/- 5% 2A VGS(th)=2.25V Max
+/- 2% AON6324_DFN8-5
ot

3 3
1
2 1 1
1 5 3 CR26
0.01U_6.3V_K_X7R_0201

CR21 CR25 @ 1U_0402_6.3V6K

10U_0603_6.3V6M 10U_0603_6.3V6M
N

2 2
1

@ 1 1
2
4

CR22 CR24 RR12

0.1U_6.3V_K_X5R_0201 470_0603_5%
@ @ +5VALW @
2 2
2

RR11
+0.75VS_GATE_R 1 @ 2 1 @ 20.75VS_GATE 1 2 10K_0402_5%
RR8 0_0402_5% RR9 0_0402_5%
1

1 D D
CR23 RR10 2 QR4 SUSP 2 QX24
0.01U_25V_K_X5R_0201 1M_0402_5% G L2N7002KWT1G_SOT323-3 G L2N7002KWT1G_SOT323-3
@
2 S S
2

For DisCharge
+5VALW +3VALW

+0.6VS +0.75VS +1.8VS +5VS +3VS

+3VALW +5VALW
+5VALW +5VALW +5VALW
CR30
1

RR13 1 2 1 1 1
1

4
470_0603_5% RR17 @ 1 1 1 CR16 CR17 CR18 4
RR14 RR15 RR16 470_0603_5% 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K
470_0603_5% 470_0603_5% 470_0603_5% 0.1U_6.3V_K_X5R_0201 CR27 CR28 CR29 @ @ @
2 2 2
2

0.047U_10V_K_X5R_0201 0.047U_10V_K_X5R_0201 0.047U_10V_K_X5R_0201

@ 2 2 2
2

@ @ @ @
2

@
@ @ @
1

D @ QX23 D
1

QX5 2 SUSP QX9 D D QX14 D SUSP 2

G SUSP 2 SUSP 2 SUSP 2 G +5VALW
G G QX12 G EMC
CR31
S L2N7002KWT1G_SOT323-3 L2N7002KWT1G_SOT323-3 S L2N7002KWT1G_SOT323-3
3

S L2N7002KWT1G_SOT323-3 S S L2N7002KWT1G_SOT323-3 1 2
@
3

@
@ @
0.1U_6.3V_K_X5R_0201
Security Classification LCFC Highly Confidential Information Title
S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DCDC_SYSTEM PWR
Date: Friday, December 04, 2020 Sheet 84 of 110
A B C D E
 5 4 3 2 1

CPU Memory Shielding PCB Fedical Mark PAD

FD1 FD2 FD3

1
1

1
@ @ @

FD4 FD5 FD6

D D

1
@ @ @

GPU

m
co
s.
ic
Hole
Shielding

at
NH1 H5
C HOLEA HOLEA C
H2===>H5 SH9 SH8 SH11 SH10

m
@ @ ME@ ME@ ME@ ME@
1

1 1 1 1
1 1 1 1
PAD_O8P0X7P0D8P0X7P0N PAD_O7P4X5P8D4P4X2P8

he
SPRING_FINGER_4P4X0P8 SPRING_FINGER_4P4X0P8 SPRING_FINGER_4P4X0P8 SPRING_FINGER_4P4X0P8

H8 H4 H6 H2 H3
HOLEA HOLEA HOLEA HOLEA HOLEA

Sc
@ @ @ @ @
1

PAD_CT4P6D2P8 PAD_CT7P0B6P0D3P5 PAD_CT7P0B6P0D3P4 PAD_CT7P0B6P0D3P4 PAD_CT7P0B6P0D3P4

k
oo
H5===>H6 H6==>H2 H7===>H3
H3===>H8

H7 H9 H10 H11 H12

HOLEA HOLEA HOLEA HOLEA HOLEA
eb
@ @ @ @ @
1

PAD_CT7P0B6P0D3P4 PAD_C7P0D2P8 PAD_CT8P0B7P0D3P4

PAD_C6P0D3P3 PAD_CT8P0D5P0
ot

B H8===>H7 B
N

NH13 NH14 NH15 NH16 H17

HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @
1

PAD_C6P5D6P5N PAD_C6P5D6P5N PAD_O2P5X3P0D2P5X3P0N

PAD_O3P0X2P5D3P0X2P5N
PAD_D4P0X3P0

H18
HOLEA

@
1

PAD_CT6P0B7P0D2P8

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Hole/Shielding
Date: Friday, December 04, 2020 Sheet 86 of 110
5 4 3 2 1
 5 4 3 2 1

JBATT1
HIGHS_WS33081-S120C-1H
VBAT 10A JUMP_43X118

1 PJ101 @
1
2
2
3 EC_SMCA 1 2 100_0402_1%
1
1 2
2 BATT+
PR100 EC_SMB_CK1 79,89
D 3 EC_SMDA D
4 PR101 1 2 100_0402_1%
4 EC_SMB_DA1 79,89
5
5 RTC_VCC_BAT
9 6 1 2 0_0402_5%
10 GND1 6
7 @
11 GND2 7

3
8 PR102
12 GND3 8 RTC_VCC PD100
GND4

1
ME@ PC100 PC101
1000P_0402_50V_X7R_0402 0.01U_0402_25V_X7R_0402

2
Just reserved for RTC integrated into Battery
EMC@ EMC@

om
AZC199-02S.R7G_SOT23-3

1
EMC_NS@

@ PR105 100K_0402_1%
1 2
+3VALW

PR103 AT suggest default pull 3VL for no RTC 7/27

2S1P polymer battery
BATT_TEMP_IN 1 2
voltage level: +6V ~

.c
+3VL
100K_0402_1%
8.8 V

s
PR104 1 2 10K_0402_5%
BATT_TEMP 79,89
3S1P polymer battery

ic
voltage level: +9V ~
13.05 V

at
1
PD101
AZ5215-01F_DFN1006P2E2
C EMC_NS@ C

m
2

he
Sc
ok
+3VL

+RTC_LDO
o Del RES
eb
2
RTC_VCC
1
JRTC1
3 VCCRTC_D3 2 PR107 1 1
1
2
ot

2
PD102 1K_0603_5% 3
B GND1 B
2

PC102 BAT54CW_SOT323-3 4
GND2
1U_0402_6.3V6K
@ Just reserved for RTC integrated into Battery,Remove RTC Connector
1

HIGHS_WS33020-S0351-HF
N

ME@
RTC_VCC 20MIL
+3VL 20MIL
VCCRTC 20MIL

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_DCIN/RTC
Date: Friday, December 04, 2020 Sheet 87 of 110
5 4 3 2 1
 5 4 3 2 1

D D

CHARGER_IN
3.5A HCB2012KF-121T50_0805
3.5A
JDCIN1
PL200
1 ADPIN 1 2
1
2 EMC@
GND1
3

om
GND2

SPHV24-01ETG-C_SOD882-2
4
GND3
5 HCB2012KF-121T50_0805

PD200
1
GND4

1
6 PL201
GND5

2
1000P_0402_50V_X7R_0402
7 1 2
GND6

470P_0402_50V_X7R_0402

470P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402
EMC@

EMC@ PC200

PC201

PC202

EMC@ PC203

PC204

PC205

PC206

PC207

PC208
2

2
HIGHS_PJSSR26-D1005-1H

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
EMC_NS@

EMC@

EMC@
ME@

.c
2

s
ic
at
C C

e m
ch
kS
oo
eb
ot

B B
N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/11/06 Deciphered Date 2019/11/05 S360_ALC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_ACIN
Date: Friday, December 04, 2020 Sheet 88 of 110
5 4 3 2 1
 A B C D

B+ EMC reserved @7/30

0.1U_25V_K_X7R_0402

0.1U_25V_K_X7R_0402

0.1U_25V_K_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402

1000P_0402_50V_X7R_0402
EMC_NS@ PC5450

EMC_NS@ PC5451

EMC_NS@ PC5452

EMC_NS@ PC5453

EMC_NS@ PC5454

EMC_NS@ PC5455
1 1 1

1
2

2
2 2 2

CHARGER_IN
PQ5400 PQ5401
ADIN2
1 1

AONS32314_DFN8-5 AONR32340C_DFN8-5
ADIN1
PR5425
1 1 0.01_1206_1%
2 2 S1
S2 D
5 B+
5 3 3 1 4

0.01U_50V_K_X7R_0402
S3

6800P_25V_K_X7R_0402
2 3

G
470P_0402_50V_X7R_0402

220P_0402_50V_X7R_0402

470P_0402_50V_X7R_0402

680P_0402_50V_X7R_0402
0.022U_0402_25V_X7R_0402

4700P_0402_50V7-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
CHG_ACDRV_R_S

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
2 2 1

1
PC5479

PC5481

PC5482

PC5483

PC5484

PC5485

PC5486

EMC_NS@

PC5487

EMC_NS@

EMC_NS@
1

PC5480

PC5488
PR5426

2
4.7_0603_5% 1 1 2

5
2
PQ5402
CHG_ACDRV_R
AON6324_DFN8-5
1 2

m
CHG_BATDRV 2 1 CHG_BATDRV_R 4
PC5489 @

2
0.1U_25V_K_X5R_0402 09/09 NC MEC part PR5427 0_0402_5%
PC5490
0.1U_25V_K_X5R_0402 PC5491

1
0.1U_25V_K_X5R_0402

3
2
1
PR5428

co
499K_0402_1% PC5492
0.01U_0402_25V_X7R_0402

1
CHARGER_IN BATT+

2
BAT54CW_SOT323-3
PD5400

s.
2

3
B+

CHG_ACN
CHG_ACP
1/10W_4.02K_1%_0603

ic
CHARGER_IN

22U_B2_25VM_R100M
1/10W_4.02K_1%_0603
1

0.1U_25V_K_X5R_0402
PR5429

PR5430

EMC_NS@
CHG_VCC_R 1

10_1206_5%

PC5493
2

PC5494
+

PR5431
CHG_VDD

2
at
PR5432 1U_25V_K_X5R_0402 PU5400
7.15K_0402_1% 44.2K_0402_1% 4.7U_10V_K_X5R_0402 2

ACN
ACP
1 2 PC5496
PC5497
CHG_VCC28

1
PR5433 2 1 24 1 2

2
VCC REGN
PQ5403
2 1 2 CHG_ACDET 6 4 2

ACDET
PC5498 PR5434 PC5499 AON7380_DFN8-5
CHG_BTST 2CHG_BTST_R2

em
0.01U_0402_25V_X7R_0402 25 1 1
CHG_CMSRC BTST
2.2_0603_5% 0.047U_0402_25V_X7R_0402 PL5400
PR5435
0.01_1206_1% 6A
CHG_ACDRV CHG_HIDRV
BATT+

3
2
1
3 26 2.2UH_PCMB063T-2R2MS_8A_20%
CMSRC HIDRV 1 2 CHG_CHG
1 4

5
4

1
ACDRV 2 3

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
27 CHG_PHASE_S PR5438
PHASE
1/8W_2.2_5%_0805 1 1 1 1
PR5439 2 1 0_0402_5% CHG_ACOK 5

PC5400

PC5401

PC5402

PC5403
79 ACIN
@ ACOK
PQ5404 EMC_NS@
4

ch
1 0_0402_5% CHG_SMB_SDA

2
PR5440 2 @ 11 AON7380_DFN8-5

470P_0201_25V_X7R_0201
79,87 EC_SMB_DA1 SDA 23 CHG_LODRV CHG_PHASE_R 2 2 2 2

1
LODRV
1 0_0402_5% CHG_SMB_SCL

2
PR5441 2 12 22

PC5405
@ PC5404

3
2
1
79,87 EC_SMB_CK1 SCL GND
1000P_0402_50V_X7R_0402

2
BQ24780SRUYR_QFN28_4X4 EMC_NS@

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
1 0_0402_5% CHG_IADP

1
PR5442 2 @ 7 29 @
79 ADP_I IADP PAD
CHG_IDCHG CHG_BATDRV

2
kS
8 18

PC5406

PC5407
IDCHG BATDRV
9 PR5443 10_0603_5% charge：
100P_0402_50V8J

100P_0402_50V8J
CHG_BATSRC

1
79 PSYS PMON 17 2 1
max current=5.8A

100P_0402_50V8J
20K_0402_1%
BATSRC

0.1U_25V_K_X5R_0402
CHG_SRP CHG_SRP_R
2

2
20 2 1
volatge=2S
PC5408

PC5409

2
10 SRP

PR5445

PC5410
PR5444 10_0603_5%
79 VR_HOT_N
fsw=800K/REG0x12[9:8] = 01

2
PROCHOT#

PC5411
1

1
13

oo
1
CMPIN

1
14

BATPRES#
TB_STAT#
@ CMPOUT 19 CHG_SRN 2 1 CHG_SRN_R
CHG_ILIM 21 SRN
PR5447 10_0603_5%
ILIM
PR5460

2
1 2
+3VL

16

15
PR5448
AT suggest default pull 3VL for no RTC 7/27 1/16W_133K_1%_0402

eb
0_0402_5%

PR5449
CHG_ILIM_R @ PR5450
2CHG_TB_STAT_N

1
+3VALW @1 2 1
BATT_TEMP 79,87
30K_0402_1%
1/16W_133K_1%_0402

1
09/19 PR331 change from 147K to 133K

2
PR5451
100K_0402_1%

ot PC5412

2
0.01U_0402_25V_X7R_0402
3 3

ACDECT setting 17.2V

N
Charge current limit HW=7A
DC discharge limit =28A
Discharge current limit HW=9A during Turbo boost

IDPM V(ILIM) PR5320

IND IN USE PR5333 # of CELL VCELL_PRES PR5322
500mA 1.2V 402K
4
1.0A 1.4V 332K 1uH 93K 1-CELL 1.5V 301K 4

1.5A 1.6V 280K 2.2uH 137K LOGIC 2-CELL 2.4V 150K

2.0A 1.8V 237K LOGIC
LOGIC 3.3uH 169K 3-CELL 3.3V 82K
3.0A 2.2V 174K
3.25A 162K 4-CELL 4.5V 33.2K
2.3V
4.0A 2.6V 162K
VILIM=1V+40x(VACP-VACN)=1+40xIDPMxRAC Title
Security Classification LC Future Center Secret Data
Issued Date 2019/11/06 Deciphered Date 2019/11/05 S360_ALC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
PWR_CHARGER 0.3

Date: Friday, December 04, 2020 Sheet 89 of 110

A B C D
 A B C D

1 1

+3VALW

m
1
PR6006
100K_0402_5%

B+

co
2
PJ6001 PU6001 P_+3VALW_PWRGD 2 1
@

@ ALW_PWRGD 79

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402
2 1 P_+3VALW_VIN_S 2 7 PR6010 0_0402_5%
2 1 IN1 PG P_+3VALW_BST1
3 1 2
22U_B2_25VM_R100M

IN2 BS
JUMP_43X79 1 1 1 1 1 4 PC6005

EMC_NS@
IN3
1

PL6001

SY8386BRHC_QFN16_2P5X2P5
0.1U_25V_K_X7R_0402
0.1U_25V_K_X5R_0402
+ 5
PC6020

PC6001

PC6002

PC6003

PC6015

PC6016
LX1

s.
@ 6 15 2.2UH_PCMB063T-2R2MS_8A_20% PJ6002

@
GND1 LX2
2

2 2 2 2 14 16 P_+3VALW_LX_S 1 2 +3VALW_P 2 1
2 GND2 LX3 2 1 +3VALW

1
17
GND3

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR6008 JUMP_43X79

2
ic
1/8W_2.2_5%_0805
EC_ON_3VALW 2 1 P_+3VALW_EN 9 11 +3VALW_P
PR6001
@
0_0402_5% P_+3VALW_VIN_S 1 2 P_+3VALW_EN28 EN1 OUT EMC_NS@ 1 1 1 1 1 1 PJ6004
@ JUMPER

PC6009

PC6010

PC6011

PC6012

PC6013

PC6014
EN2

1 2

1
@ 10 P_+3VALW_FF P_+3VALW_LX_R
PR6011 FF
0.1U_25V_K_X5R_0402

at
10K_0402_5% 2 2 2 2 2 2
1

12
100mA PC6007
PC6004

TEST

1
13 1000P_0402_50V_X7R_0402 @ @
+3VLP 3VALW:
2 2
LDO

2
change 68K to 34.8K PR6002 EMC_NS@
2

TDC=6A
adjust EN1=1.3V 34.8K_0402_1% 1

1M_0402_5%
PR6004

em
2

PC6006
OCP=8A

2
P_+3VALW_USM_REF 4.7U_6.3V_K_X5R_0402
OVP=120%
2 1 2 P_+3VALW_FF_C 1 2 P_+3VALW_FF_R
SSM3K15AMFV_2-1L1B
1

USM mode: 1V <EN1<1.6V

PFM mode: 2V <EN1
PC6008
1000P_25V_K_X7R_0402
PR6007
1K_0402_1% Fsw=600KHz
PQ6001

2 PJ6003

@
79 EC_USM_3VALW 2 1
+3VLP +3VL

ch
2 1
3

JUMP_43X39

kS
+5VALW oo
eb
1

+3VL PR6016
100K_0402_5%
1

ot
2

3 PR6015 EC_ON_3VALW 3

100K_0402_5%
SSM3K15AMFV_2-1L1B
1

EC_ON_3VALW 77
2

79 EC_ON_3VALW_R
PQ6002

1M_0402_1%

2
PR6018
3

PR6017 1 2 0_0402_5%
@

4 4

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C PWR_3VALW 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, December 04, 2020 Sheet 91 of 110
A B C D
 5 4 3 2 1

B+ JUMP_43X79
PJ5701
D P_+5VALW_VIN_S D

0.01U_0402_25V_X7R_0402
2 1
2 1
PU5701

1
@

EMC_NS@
RT6258CGQUF_UQFN12_3X3 PR5703

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402
5 1 P_+5VALW_BST2 1P_+5VALW_BST_R 1 2

PC5702
1 1 1 1 VIN BOOT
PC5701
PC5713

2
10_0603_5% 0.1U_25V_K_X7R_0402 PL5701

PC5703

PC5704

PC5725

PC5726
1 2 P_+5VALW_VCC 11 2 1.5UH_PCMB063T-1R5MS_10A_20% JUMP_43X79
2 2 2 2 6258C_AGND VCC LX1
PJ5702
3 P_+5VALW_LX_S 1 2 +5VALW_P 2 1
1U_0402_6.3V6K LX2 2 1 +5VALW

2
2 1 P_+5VALW_EN 6 10 +5VALW_P PR5702 PJ5704
@
@ EN VOUT

2
77,79 EC_ON_5VALW_R 1/8W_2.2_5%_0805

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR5710 @ @ JUMPER

1
0_0402_5% PC5717 EMC_NS@ 1 @ 2P_+5VALW_FF_RAMP
1 2 P_+5VALW_FF_C
820P_0402_25V7 PR5704

PC5705

PC5706

PC5707

PC5708

PC5720

PC5721
m
1

1 2
0.1U_10V_K_X7R_0402 P_+5VALW_PWRGD 7 9 P_+5VALW_FF P_+5VALW_LX_R PR5707 1K_0402_1%
PGOOD FF

2
1

1
PC5710 10K_0402_1%
1
USM mode: 0.8V <EN1<1.7V PR5712
@ PC5709
1000P_0402_50V_X7R_0402
PC5715
100P_0402_50V8J

2
PFM mode: 2.3V <EN1 68K_0402_1% 12 8 EMC_NS@

co
LDO5 AGND 6258C_AGND
4
PGND
2

P_+5VALW_USM_REF
1

PQ5701
100mA

s.
+5VLP
2
79 EC_USM_5VALW SSM3K15AMFV_2-1L1B +5VALW 1
PC5711 PJ5705

ic
1 2
4.7U_6.3V_K_X5R_0402
Vset=5.1V±1%
3

2
Design Current:8A

1
JUMPER
PR5701 @ @
OCP: Min:9A, Max:11.8A

at
100K_0402_1%
6258C_AGND
OVP=(1.15~1.25)*Vout
C 2
JUMP_43X79
Fsw=750Khz C

m
PJ5703
2 1
+5VLP 2 1 +5VL
@

he
k Sc
oo
eb
ot

B B
N

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C PWR_5VALW 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, December 04, 2020 Sheet 92 of 110
5 4 3 2 1
 5 4 3 2 1

PR7201 2 1 0_0402_5% P_PMIC_VDDQ_EN

79 SYSON_VDDQ
@
SYSON-1.2VEN
PC7201 2 1 0.1U_0402_10V6-K

@
SUSP_N PR7202 2 1 0_0402_5% P_PMIC_VTT_EN
79,84,96 SUSP_N
@

D D
PC7202 2 1 0.1U_0402_10V6-K

@
PR7203 2 1 0_0402_5% P_PMIC_+1.8VALW_EN
79 EC_ON_1.8VALW
@
100k pull high for support 1.8V SPI mirror code

PC7203 2 1 0.1U_0402_10V6-K P_PMIC_VCC_30

@
10_0603_5%
P_PMIC_+0.75ALW_EN
PR7206 Need pull hight to 3VL
PR7204 2 @ 1 0_0402_5% 1 2 PR7207 2 @ 1 0_0402_5%
79 EC_0.75VALW_EN +5VL PIMC_PWR_EN 79

need 100K pull down at EE side 2 1 1 2

2 1 0.1U_0402_10V6-K

@
PC7204

@
PC7206 PC7207
2.2U_10V_K_X5R_0402 0.1U_0402_10V6-K

m
P_PMIC_+2.5V_EN

P_PMIC_VSYS_10
PR7205 2 @ 1 0_0402_5% PR7208
79 EC_VPP_PWREN 1 2
EC-2.5VEN +1.2V_B+

P_PMIC_EN
10_0402_5%
PC7205 2 1 0.1U_0402_10V6-K 1 2

co
PC7208
1U_25V_K_X5R_0402

28

27

41
9
VCC

PMIC_EN

GND
VSYS
PR7209 1 2P_PMIC_LDO1_EN 29 25 P_PMIC_EC_SMB_DA3_10 PR7211 2 @ 1 0_0402_5%
EN_LDO1 SDA EC_SMB_DA3 79
10K_0402_5%

s.
P_PMIC_+2.5V_EN 1 26 P_PMIC_EC_SMB_CK3_10 PR7212 2 1 0_0402_5%
EN_LDO2 SCL @
P_PMIC_+0.75ALW_EN 11 24 P_PMIC_ALERT_N PR7213 1 2 0_0402_5%

@
EN_V1P0A OT H_PROCHOT_N 79
P_PMIC_+1.8VALW_EN 16 22 P_PMIC_APUALW_PWRGD PR7214 2 1 100K_0402_5%

P_PMIC_+0.75VALW_LX
+3VALW

ic
EN_V1P8A PG_V1P0A
@

P_PMIC_1.8VALW_LX
P_PMIC_VDDQ_EN 31 21 PR7225 1 2 0_0402_5%
EN_VDDQ PG_V1P8A 0.75VALW_PG 79
@

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
P_PMIC_VTT_EN 36 23

@
PJ7201

10U_0603_6.3V6M10U_0603_6.3V6M

10U_0603_6.3V6M10U_0603_6.3V6M
1 2 P_PMIC_+0.75VALW_VIN EN_VTT PG_VDDQ
+5VALW

0.1U_25V_K_X5R_0402
1 2 PL7201 79 EC_SMB_CK3

EMC_NS@

@
PJ7211

at
JUMP_43X39 12 P_PMIC_+0.75VALW_LX 1 2 +0.75VALW_P 2 1
2 2
+0.75VALW

1
7 LX_V1P0A1 13 2 1

PC7209

PC7240

PC7210
8 VIN_V1P0A1 LX_V1P0A2 14
VIN_V1P0A2 LX_V1P0A3 15
0.47UH_PCMB063T-R47MS_18A_20% 1 1 1 1 1 1 JUMP_43X79 0.75VALW:

PC7218

PC7219

PC7220

PC7221

PC7222

PC7217
TDC=6A

2
C 1 1 LX_V1P0A4 C
OCP=10A

4.7_0603_5%

4.7_0603_5%
2

2
10

EMC_NS@

EMC_NS@
@
PJ7202 @
1 2 P_PMIC_1.8VALW_VIN VO_V1P0A 2 2 2 2 2 2 OVP=120%

@
+5VALW 2 2

0.1U_25V_K_X5R_0402

m
1 2
Fsw=1M

PC7211

PC7241

EMC_NS@

PR7219

PR7220
P_PMIC_1.8VALW_LX PL7202

1
17

PC7212

@
JUMP_43X39 PJ7212
19 LX_V1P8A1 18 1 2 +1.8VALW_P 2 1
+1.8VALW

P_+0.75VALW_LX_R 1

P_+1.8VALW_LX_R 1
1 1 VIN_V1P8A LX_V1P8A2
1UH_ WQPIG4018HC-1R0M_3.8A_20%
2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
2
20
VO_V1P8A
JUMP_43X79
1.8VALW:
+1.2V_P APU_VDD18=2A(TDC)
+1.2V_P 1 1

e
33 P_PMIC_+1.2V_UG_30 TDC=3A

PC7223

PC7224
2
→ 38 VIN_VTT
UGATE_VDDQ
32 P_PMIC_+1.2V_BST_30 1 2 P_PMIC_+1.2V_BST_R 1 2
OCP=6A
PC7213 @
OVP=120%

22UC_6.3VC_MC_X5RC_0603
BS_VDDQ 2 2
← 39
10U_0603_6.3V6M PR7215 0_0603_SP PC7216
Fsw=1M

ch
1

680P_0402_50V_X7R_0402

680P_0402_50V_X7R_0402
VTT 34 P_PMIC_+1.2V_LX_30 0.1U_25V_K_X7R_0402
LX_VDDQ

EMC_NS@

EMC_NS@
@
PJ7207
P_PMIC_+1.2V_LG_30

1
2 1 40 35

PC7226

PC7227
+0.6VSP +0.6VSP
+0.6VS 2 1 VSNS_VTT LGATE_VDDQ
37 +1.2V_P
JUMP_43X39 1 PR7210
P_PMIC_VDDQ_CS_1030

2
1 2 VSNS_VDDQ

PC7214
CS_VDDQ

kS
1/16W_33K_1%_0402
2
5 6
VIN_LDO1 LDO1

@
PJ7206
PJ7203
@ 3 +2.5V_P 1 2
+2.5V

oo
P_PMIC_+2.5V_VIN

24.9K_0402_1%
1 2 4 LDO2 1 2
+3VALW

1
1 2 VIN_LDO2

10U 6.3V M X5R 0402

2 JUMP_43X39
FB_LDO2

PR7216
JUMP_43X39 2 2.5V:
1
TDC=1A

PC7215
PC7225
PU7201
10U_0603_6.3V6M FB=0.75V

2
LV5028RPC_QFN40_5X5 1
2 P_PMIC_+2.5V_FB_10

eb

10.5K_0402_1%
1

PR7217
2
B ot +1.2V_B+
B
N

@
PJ7204
1 2
1 2 B+
JUMP_43X39

0.1U_25V_K_X5R_0402

22U_B2_25VM_R100M
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
EMC_NS@
1

PC7228
5
1 1
PQ7201 +

PC7229

PC7230

PC7250
AONR32340C_DFN8-5

2
2 2 2
P_PMIC_+1.2V_UG_30 4 @
G

S3
S2
S1
0.47UH_PCMB063T-R47MS_18A_20% @
PL7203 PJ7205
P_PMIC_+1.2V_LX_30 +1.2V_P

3
2
1
1 2 2 1
2 1 +1.2V

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
5

2
JUMP_43X118

AON7380_DFN8-5
PR7218
1/8W_4.7_5%_0805

PQ7202
EMC_NS@ 1.2V:
1 1 1 1 1 1
P_PMIC_+1.2V_LG_30 TDC=10A

1
4

PC7231

PC7236

PC7233

PC7234

PC7235

PC7232
P_PMIC_+1.2V_LX_R OCP=20A
2 2 2 2 2 2
OVP=120%

@
@
Fsw=1M

1
PC7237

3
2
1
680P_0402_50V_X7R_0402
EMC_NS@

2
A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
PWR_SysPMIC 1.0

Date: Friday, December 04, 2020 Sheet 93 of 110

5 4 3 2 1
 5 4 3 2 1

D D

EE Side Channel A SODIMM EE Side Channel B MD

Follow S350_ARE_0803 +1.2V
Add 2PCS Reserved ,Follow S750_ARH_0803 Add 2PCS Reserved ,Follow S750_ARH_0803
Add 2PCS Reserved ,Follow S750_ARH_0803 +2.5V +0.6VS

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1

m
CD569 CD570 CD571 CD572 CD575 CD576 CD573 CD574
@ @ @ @ @ @ @ @
2 2 2 2 2 2 2 2

co
CD350==>CD569
CD351==>CD570
ADD CD571, CD572_0803

s.
ADD CD575,CD576_0803
ADD CD573,CD574_0804

ic
Layout Note: Place near DRAM
[email protected]

at
+1.2V
C C
+1.2V
follow SCL 20pcs 0.22uf
follow CRB 6pcs 0.1uf

m
180P_50V_J_NPO_0402

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 CD486 CD496 CD476 CD472 CD489 CD474 CD485 CD493 CD482 CD497
CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD59 CD61 CD62 CC211
@ @ @ @

he
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2

DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
[email protected] CD154==>CD486 CD152==>CD474

Sc
CD155==>CD496 CD150==>CD485
+1.2V CD142==>CD476 CD158==>CD493 +1.2V
CD127==>CD472 CD143==>CD482
+1.2V CD141==>CD489 CD137==>CD497

ok
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 CD490 CD466 CD481 CD499 CD479 CD487 CD471 CD478 CD495 CD498 CD467 CD468 CD469 CD470
CD261 CD63 CD66 CD67 @ @ @ @
@ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2
bo
DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@
CD215==>CD467
CD218==>CD468
e
CD174==>CD490 CD172==>CD487 CD212==>CD469
CD173==>CD466 CD171==>CD471 CD211==>CD470
CD169==>CD481 CD175==>CD478
ot

B CD165==>CD499 CD168==>CD495 B
+0.6VS CD167==>CD479 CD166==>CD498
+2.5V +0.6VS +0.6VS
follow CRB 1pcs 4.7uf + 1pcs 0.1uf
follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf
follow SCL 10pcs 0.22uf
N
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

4.7U_0402_6.3V6M

180P_50V_J_NPO_0402
1U_0402_6.3V6K

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201

0.22U_6.3V_K_X5R_0201
1 1 1 1
CD249 CD251 CD250 CD248 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ @ CD122 CD123 CD124 CD68 CD492 CD488 CD465 CD473 CD477 CD480 CD500 CD475 CD491 CD494 CD483 CD484 CD577 CD578 CD579
2 2 2 2

DRAM@

DRAM@

DRAM@

DRAM@

DRAM@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@ DRAM@

CD245=>CD480
CC206=>CD68 CD146==>CD492 CD246==>CD500
CD148==>CD488 CD244==>CD475 CD259=>CD483 ADD 3PCS 0.22UF _0810
CD139==>CD465 CD243=>CD491 CD252==>CD484
CD138==>CD473 CD242==>CD494
CD201==>CD477

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_Memory Decouping
Date: Friday, December 04, 2020 Sheet 94 of 110
5 4 3 2 1
 5 4 3 2 1

JUM P_43 X118

PJ1 010@
1 2
1 2

PL1 010
@ BLM 18KG 300T N1D_ 2P
+CP U_VDD_VIN 1 2
B+
PL1 011

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
@ BLM 18KG 300T N1D_ 2P

0.1U_25V_K_X5R_0402
1 2
D D

22U_B2_25VM_R100M
EMC@
1 1 1 1

PC1021

PC1022

PC1023
+

PC1024
5
2 2 2
2

AON6380_DFN8-5
@ @

PQ1001
P_V DDCR_CPU_UG1 _30 4

3
2
1
PL1 001
0.1 5UH_CM M E 063T -R15M S0R90 5_38 A_20%
P_V DDCR_CPU_PH1 _30 1 2
+VDDCR_CPU
@ @

2
0_0805_5%
PJ1 001 PJ1 002

PR1055
AON6324_DFN8-5
JUM PER JUM PER

1
P_V DDCR_CPU_PH1 _JUM P1

PQ1002
P_V DDCR_CPU_LG1 _30

2
4 Base on 25W config
P_V DDCR_CPU_PH1 _R

1
PR1 056
APU_VDDCR
2K_ 0402 _1% FSW=400KHz

1000P_0402_50V_X7R_0402
Slew rate:12.5mv/us

PC1026
3
2
1
PC1 027 TDC=44A EDC=70A

2
OCP=105A

2
1 2
OVP=VID+300mV
0.1 U_25V _K_X 5R_04 02 Load Line=0.7mohm
Ripple:+/-20mv

m
P_V DDCR_CPU_ISEN1P_1 0 MAX AC: VID_VDDC +95mv
100 K_04 02_1% 1/1 6W_2.2_1% _0402
MIN AC: VID_VDDC -80mv
PR1 030 PR1 031
P_CPU_VCC_20 PU1 001
P_CPU_T ONSE T _10 1 2 P_CPU_T ONSE T _R 2 1 +CPU_VDD_VIN
Fsw_Max 413K 1

PR1 001 1 2 10_ 0603_ 5% 28 4 PC1 012

+5VALW VCC TONSET
0.1 U_25V _K_X 5R_04 02
PC1 001 2 1 2.2 U_10V _K_X 5R_04 02 2
P_V DDCR_CPU_ISEN1N_1 0

co
PR1 002 1 2 2.2 _0603 _5% P_CPU_P VCC_ 20 50 PR1 032
PC1 013
+5VALW PVCC
46 P_V DDCR_CPU_BOO T 1_3 0 2 1 P_V DDCR_CPU_BOO T 1_R 2 1 P_V DDCR_CPU_PH1 _30
2 1 BOOT1
PC1 002 2.2 U_10V _K_X 5R_04 02
47 P_V DDCR_CPU_UG1 _30
PR1 003 2.2 _0603 _5%
1 2 P_CPU_T ONSE T A_R P_CPU_T ONSE T A_1 040 UGATE1 0.2 2U_25 V_K_ X7R_0 402
PR1 004 2 1 100 K_04 02_1%
+CPU_VDD_VIN
1 Fsw_Max 411K
TONSETA
PHASE1
48 P_V DDCR_CPU_PH1 _30 +CPU_VDD_VIN
1/1 6W_2.2_1% _0402 PC1 003

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
0.1 U_25V _K_X 5R_04 02

22U_B2_25VM_R100M
1
2
P_V DDCR_SOC_PH1 _30 P_V DDCR_SOC_BOO T 1_R 1 1 1
1 2 1 2 P_V DDCR_SOC_BOO T 1_3 0 42 49 P_V DDCR_CPU_LG1 _30 +

EMC@
PC1028

PC1029

PC1030

PC1025
BOOTA1 LGATE1
P_V DDCR_SOC_UG1 _30 43

5
s.
PC1 004 PR1 005
UGATEA1 2 2 2 2
0.2 2U_25 V_K_ X7R_0 402 2.2 _0603 _5%
P_V DDCR_SOC_PH1 _30 44

AON6380_DFN8-5
PHASEA1 8 P_V DDCR_CPU_ISEN1P_1 0
ISEN1P @ @
change 0603 to 0402 7/17

PQ1003
7 P_V DDCR_CPU_ISNE 1N_R_10 P_V DDCR_CPU_ISEN1N_1 0 P_V DDCR_CPU_UG2 _30
PR1 033 2 1 1/1 6W_73 2_1% _0402 4
ISEN1N
1
P_V DDCR_SOC_LG1 _30 45 PC1 014
0.1 U_25V _K_X 5R_04 02

ic
LGATEA1
PC1 015

3
2
1
PR1 034 2 PL1 002
2 P_V DDCR_CPU_BOO T 2_3 0 2 1 P_V DDCR_CPU_BOO T 2_R 2 1 P_V DDCR_CPU_PH2 _30
0.1 5UH_CM M E 063T -R15M S0R90 5_38 A_20%
P_V DDCR_SOC_ISEN1P_1 0 36 BOOT2 P_V DDCR_CPU_PH2 _30 1 2
P_V DDCR_SOC_ISEN1N_1 0 P_V DDCR_SOC_ISEN1N_R_10
ISENA1P
UGATE2
1 P_V DDCR_CPU_UG2 _30
2.2 _0603 _5%
0.2 2U_25 V_K_ X7R_0 402
+VDDCR_CPU
1 2 35 @ @
P_V DDCR_CPU_PH2 _30

2
ISENA1N 52
0.1U_25V_K_X5R_0402

0_0805_5%
PHASE2
1 PR1 006 PJ1 003 PJ1 004

PR1057
AON6324_DFN8-5
1/1 6W_73 2_1% _0402 JUM PER JUM PER
PC1005

at

1
51 P_V DDCR_CPU_LG2 _30 P_V DDCR_CPU_PH2 _JUM P2

PQ1004
P_V DDCR_CPU_LG2 _30

2
2 LGATE2 4
P_V DDCR_CPU_PH2 _R

1
PR1 058
C 5 P_V DDCR_CPU_ISEN2P_1 0 2K_ 0402 _1% C

1000P_0402_50V_X7R_0402
ISEN2P

1
41

PC1031
P_V DDCR_CPU_ISNE 2N_R_10 P_V DDCR_CPU_ISEN2N_1 0

3
2
1
PWMA2 6 PR1 035 2 1 1/1 6W_73 2_1% _0402
PC1 032

2
ISEN2N
1

2
PC1 016 1 2
0.1 U_25V _K_X 5R_04 02

m
0.1 U_25V _K_X 5R_04 02
10K _040 2_1% 2
PR1 007
1 2 P_V DDCR_SOC_ISEN2N 33 P_V DDCR_CPU_ISEN2P_1 0
+5VALW ISENA2P 3 P_V DDCR_CPU_PWM 3_10
NOT USE,Connect to 5VALW PWM3
34
ISENA2N

330 P_04 02_50 V_X7R_040 2 56P _50V _J_NP O_04 02

PC1 006 PC1 007
1 2 1 2 P_S OC_COM P _10

he
30
COMPA
9 P_V DDCR_CPU_ISEN3P_1 0 P_V DDCR_CPU_ISEN2N_1 0
10K _040 2_1% 47.5K_04 02_1%
ISEN3P
7 VDDCR_S OC_V CC_S ENSE PR1 010 1 2 1/1 6W_10 _1%_ 0402 1 PR1 008 2 1 PR1 009 2
10 P_V DDCR_CPU_ISNE 3N_R_10 P_V DDCR_CPU_ISEN3N_1 0
PR1 036 2 1 1/1 6W_73 2_1% _0402
ISEN3N
VDDCR_SOC_VSS_SENSE merge with VDDCR_VSS_SENSE P_V DDCR_SOC_FB_ 10 31 1
PC1 017
FBA
0.1 U_25V _K_X 5R_04 02
2
P_V DDCR_SOC_VSE NA 32
+VDDCR_SOC PR1 011 1 2 100 _0402 _1%
VSENA
COMP
13 P_V DDCR_CPU_COM P_10
PC1 018
1 2 1
PC1 019
2 +CPU_VDD_VIN
56P _50V _J_NP O_04 02 220 P_04 02_50 V_X7R_040 2

Sc

0.1U_25V_K_X5R_0402
VDD/DOC offset 0mV PR1 037 PR1 038
PR1 012 2 @ 1 10K _040 2_1% 1 2 1 2

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402

4.7U_25V_M_X5R_0402
P_CPU_VCC_20 1 1 1 1 1

EMC@
P_V DDCR_SOC_OFS _10
PR1 013 1 2 10K _040 2_1% 24 34.8K_04 02_1% 10K _040 2_1%

PC1035

PC1036

PC1037

PC1045

PC1046
P_V DDCR_CPU_FB_ 10

5
OFSA 12
P_V DDCR_CPU_OFS _10 FB 2 2 2 2 2
P_CPU_VCC_20 PR1 014 2 @ 1 10K _040 2_1% 23
OFS

AON6380_DFN8-5
PR1 015 1 2 10K _040 2_1%
PR1 039 1 2 40.2_040 2_1%
+VDDCR_CPU

PQ1005
P_CPU_S ET 1_ H 1 1K_ 0402 _1% P_CPU_S ET 1_ 10
P_CPU_VCC_20 PR1 016 2 1 124 K_04 02_1% PR1 017 2 PR1 059 4
P_CPU_S ET 1_ L P_V DDCR_CPU_VSE N
OPR SET VDD/SOC: PR1 018 2 1 20.5K_04 02_1% PR1 019 2 1 200 _0402 _1% 25 11 PR1 040 1 2 1/1 6W_10 _1%_ 0402 2.2 _0603 _5% PC1 034
SET1 VSEN VDDCR_V CC_S ENSE 7 P_Driver_ VCC PR1 061
1 2 0.2 2U_25 V_K_ X5R_0 402
OCP_TDC≠OCP_SPIKE P_CPU_S ET 2_ H 1 60.4_040 2_1%P_CPU_CET 2_ 1026
+5VALW P_V DDCR_CPU_BOO T 3 2 1 P_V DDCR_CPU_BOO
1 T 3_R

2
P_CPU_VCC_20 PR1 020 1 2 33.2K_04 02_1% PR1 021 2 4 2
VID up compensate LL 18mv

ok
1 2 P_CPU_S ET 2_ L 1 2 SET2 BOOT
PC1 117 PC1 033 2 1 1U_040 2_10V 6K 8
P_V DDCR_CPU_UG3 _30

3
2
1
Ramp 100%/QRTH 39mV PR1 022 110_ 0402 _1% PR1 023 1/1 6W_8.45K_1 %_04 02 100 0P_0 402_5 0V_X7 R_04 02
P_V DDCR_CPU_PWM 3_10
VCC 3 2.2 _0603 _5% PL1 003

1
5 UGATE
Offset disable P_CPU_RGND_ 10 PWM P_V DDCR_CPU_PH3 _30
0.1 5UH_CM M E 063T -R15M S0R90 5_38 A_20%
53 14 PR1 041 1 2 1/1 6W_10 _1%_ 0402 @ 2 1 2
OCP trigger delay 10ms GND RGND VDDCR_V SS_S ENSE 7 P_Driver_ VCC 1 2 P_Driver_ EN 1
EN
PHASE
P_V DDCR_CPU_LG3 _30
+VDDCR_CPU
100K（>1%）*20uA=2V, for internal analog circuits @ PR1 042 1 2 40.2_040 2_1% PR1 060 7 @ @
P_CPU_IBIAS_ 10

2
LGATE
PR1 024 1 2 100 K_04 02_1% PR1 043 1 20_040 2_5% 0_0 402_5 % 6

0_0805_5%
EC_ VR_O N 79 GND1 9
Connect to output Cap GND PJ1 005 PJ1 006

PR1062
P_CPU_E N_10 GND2

AON6324_DFN8-5
Pull up with +1.8VALW follow CRB 29 37 PC1 118 1 2 0.1 U_10V _K_X 5R_04 02 JUM PER JUM PER

1
IBIAS EN
+1.8VALW PR1 025 1 2 2.2 _0603 _5% PU1 002
2 1 P_CPU_V DDIO _20 18 P_V DDCR_CPU_PH3 _JUM P3
PC1 008 1U_ 0402 _6.3V 6K
→ PH1 002 RT 9 610CGQW_ WDFN8_2X 2

PQ1006
1P_V DDCR_SOC_IM O N_R_ S2

2
VDDIO 2 1 4
P_V DDCR_CPU_PH3 _R

1
Pull up with +1.8VALW follow CRB P_CPU_P WROK
1/1 6W_23 .2K_1 %_04 02 PR1 046
7,2 4 CPU_PWROK
2 @ 1 19
→ P_V DDCR_SOC_IM O N_10
bo
PR1 044 100 K_04 02_1% _NCP 15WF104F0 3RC
1P_V DDCR_SOC_IM O N_R
6.4 9K_04 02_1% PR1 063

1
PWROK 17 2 2 1
PR1 026 0_ 0402_ 5% 2K_ 0402 _1%

PC1038
IMONA
20 PR1 047 20K_ 0402 _1%

1000P_0402_50V_X7R_0402
7 CPU_SVC

3
2
1
1 2PC1 SVC
@009
0.1 U_25V _K_X 5R_04 02 PH1 001
P_V DDCR_CPU_IM O N_10 1P_V DDCR_CPU_IM O2N_R 1P_V DDCR_CPU_IM O N_R_S2 PC1 039

2
21 15 2 1
7 CPU_SVD 1 2 @ 0.1 U_25V _K_X 5R_04 02 SVD IMON
1 2
PC1 010 PR1 048
22 PR1 045 100 K_04 02_1% _NCP 15WF104F0 3RC 12.4K_04 02_1%
7 CPU_SVT 1 2 @ 0.1 U_25V _K_X 5R_04 02 SVT
2 1
PC1 011 7.3 2K_04 02_1% 0.1 U_25V _K_X 5R_04 02
38 PR1 049 14 K_04 02_1%
PGOODA
+3VS PR1 027 2 1 10K _040 2_1% POR,Vdiv=2150mV:current gain ratio 25%
39 P_V DDCR_CPU_ISEN3P_1 0
79 CPU_VR_ READY
P_A PU_O CP_L
← PGOOD
P_CPU_S ET 3_ 20
after POR,V064 clamp voltage =0.64V
APU_VCC_L 2
+1.8VS PR1 028 1 @ 2 10K _040 2_1% 27 16 2 1 1
P_CPU_VCC_20
OCP_L V064/SET3

PR1 029 1 @ 2 0_0 402_5 % PR1 050 PR1 051

e
79 P_A PU_O CPL
330 _0402 _1% 26.1K_04 02_1%

19.6K_0402_1%
RT 3 663B RGQW_WQ FN52_ 6X6

2
PR1 052
0_0 402_5 %

PR1053
P_V DDCR_CPU_ISEN3N_1 0
1
ot

@ P_CPU_S ET 3_ R P_CPU_S ET 3_ S

1
2
B B
0.022U_0402_25V_X7R_0402
2

1/16W_340_1%_0402
PC1020

PR1054
1

+CPU_VDD_VIN
N

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402
1 1 1

PC1041

PC1042
EMC@
PC1040
5
2 2 2

AON6380_DFN8-5
PQ1007
P_V DDCR_SOC_UG1 _30 4

3
2
1
PL1 004
0.3 6UH_P CM B0 63T -R36M S 3R20 5_20A _20%
P_V DDCR_SOC_PH1 _30 1 2
+VDDCR_SOC
@ @

2
0_0805_5%
PJ1 007 PJ1 008

PR1064
AON6324_DFN8-5
JUM PER JUM PER

1
P_V DDCR_SOC_PH1 _JUM P1

PQ1008
P_V DDCR_SOC_LG1 _30

2
4
P_V DDCR_SOC_PH1 _R

4.75K_0402_1%
VDDCR_SOC
FSW=300KHz

PR1065
1

PC1043
Slew rate :12.5mv/us

1000P_0402_50V_X7R_0402
3
2
1
PC1 044 TDC=13A EDC=17A

2
OCP=26A
1 2
OVP=VID+300mA
0.1 U_25V _K_X 5R_04 02 Loadline=2.1mohm
Ripple:+/-20mv
P_V DDCR_SOC_ISEN1P_1 0
PR1 066 MAX AC: VID_VDDCR_SOC +70mv
1 2 MIN AC: VID_VDDCR_SOC -40mv
1/1 6W_1.87K_1 %_04 02

P_V DDCR_SOC_ISEN1N_1 0

A A

Security Clas s ification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Do cum e nt Num ber Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
E
PWR_CPU Controller 1.0

Date: Friday , December 04, 2020 She et 95 of 1 10

5 4 3 2 1
 5 4 3 2 1

D D

m
co
+3VALW

100K_0402_1%
2

s.
PR8101
@

ic
PL8101

1
PJ8101 PJ8102

+3VALW
2
2 1
1 P_+1.8VS_VIN
P_+1.8VS_PG
P_+1.8VS_LX 1 2 +1.8VS_P 2
2 1
1 +1.8VS
@ 1UH_ WQPIG4018HC-1R0M_3.8A_20% @

4.7_0603_5%
10U_0603_6.3V6M

10U_0603_6.3V6M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39 JUMP_43X79

at
PR8104
2 2

2200P_25V_K_X7R_0402
1/16W_102K_1%_0402
EMC_NS@
PC8101

PC8102

0.1U_25V_K_X5R_0402
4

EMC_NS@

EMC_NS@
C 1 C

68P_0402_50V8J
1

1
10 1

PC8108

PC8109
1 1

PG
PVIN2 LX1

1 1
1 1

1
P_+1.8VS_LX_R

PR8105

PC8105

PC8106

PC8107
em
9 2
PVIN1 LX2

2
2

2
8 3 2 2

PC8104
SVIN1 LX3

2
680P_0402_50V_X7R_0402
EMC_NS@
PR8102
79,84,93 SUSP_N 1 2 P_+1.8VS_EN 5 6 P_+1.8VS_FB
EN FB

GND

NC

ch
1/16W_16K_1%_0402
0.47U_0402_25V6K

1/16W_51K_1%_0402
PU8101

7
11
2

1
1 RT8068AZQW_WDFN10_3X3
1M_0402_1%
PR8103

PC8103

PR8106
2

kS
1

2
@

oo
eb
ot

B B
N

A A

Security Classification LCFC Highly Confidential Information Title

S360_ALC
Issued Date 2012/07/01 Deciphered Date 2014/07/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_1.8VS
Date: Friday, December 04, 2020 Sheet 96 of 110
5 4 3 2 1
 A
B
C
D

2
1
PC1085
22UC_6.3VC_MC_X5RC_0603

2
1
PC1086
+VDDCR_CPU

22UC_6.3VC_MC_X5RC_0603

5
5

2
1
PC1087
22UC_6.3VC_MC_X5RC_0603

@
2
1
PC1088
22UC_6.3VC_MC_X5RC_0603

2
1
2
1
PC1089 PC1073
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

@
2
1
2
1
PC1090 PC1074
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1
PC1091 PC1075
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1
PC1092 PC1076
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
+

2
1
2
1
PC1063
PC1093 PC1077 330U_2.5V_M_B2_ESR9M_H1.9
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1
@ 2
1
+

PC1094 PC1078 2 1 PC1064

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 330U_2.5V_M_B2_ESR9M_H1.9
PC1069

2
1
2
1
2
1
+

0.1U_25V_K_X5R_0402
PC1095 PC1079 EMC_NS@ PC1065
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 2 1 330U_2.5V_M_B2_ESR9M_H1.9

2
1
2
1
PC1070
2
1
+

PC1096 PC1080 0.1U_25V_K_X5R_0402

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 EMC_NS@ PC1066
2 1 330U_2.5V_M_B2_ESR9M_H1.9

2
1
2
1

@
@
PC1097 PC1081 PC1071
2
1
+

22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 0.1U_25V_K_X5R_0402

EMC_NS@ PC1067

2
1
2
1

@
2 1 330U_D2_2V_Y
PC1098 PC1082
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 PC1072
2
1
+

0.1U_25V_K_X5R_0402

2
1
2
1

EMC_NS@ PC1068
PC1099 PC1083 330U_2.5V_M_B2_ESR9M_H1.9
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

2
1
2
1

PC1100 PC1084
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603

4
4

+VDDCR_SOC

2
1

PC1110
22UC_6.3VC_MC_X5RC_0603
2
1

PC1111
22UC_6.3VC_MC_X5RC_0603
2
1
2
1
2
1
+

PC1112 PC1103 PC1101

N
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 470U_D2_2VM_R4.5M
2
1
2
1
2
1
+

PC1113 PC1104
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603 PC1102
330U_D2_2V_Y
2
1
2
1

PC1114 PC1105
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

ot
@

PC1115 PC1106
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
2
1
2
1

PC1116 PC1107
22UC_6.3VC_MC_X5RC_0603 22UC_6.3VC_MC_X5RC_0603
eb
2
1

PC1108
22UC_6.3VC_MC_X5RC_0603
2
1

PC1109
22UC_6.3VC_MC_X5RC_0603
oo
kS

3
3

ch
e m
at
ic
s.
co
2

m
2

Issued Date
Security Classification
2012/07/01
Deciphered Date
LCFC Highly Confidential Information
2014/07/01

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size

Date:
Title

1
1

Document Number
S360_ALC

Friday, December 04, 2020

Sheet
98
PWR_CUP Decouping
of
110
Rev
1.0
A
B
C
D
 A B C D E

1 1

m
co
LCFC Confidential

s.
ic
at
2 2

HS561(NS-D522) IO Schematics Document

em
Card Reader +hall sensor+FPLED+Button

ch
kS
2020-09
oo REV:0.2
eb

3 3
ot
N

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Cover Page 0.2

Date: Monday, September 21, 2020 Sheet 1 of 11

A B C D E
 5 4 3 2 1

Virtual Symbol_EE BOM Structure

D D
BOM Structure Description
@ Un-stuff
ZZZ1
ME@ For ME part
PCB PCB 21P NS-D522 REV0 IO/B EMC@ For EMC part

m
DA600018Q0S
EMC_NS@ For EMC un-stuff part

o
NPI@ For NPI Phase part

. c
s
a tic
em
C C

c h
kS
o o
e b
ot
B B

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Notes_For BOM 0.2

Date: Monday, September 21, 2020 Sheet 2 of 11

5 4 3 2 1
 5 4 3 2 1

Novo switch ON/OFF switch

NOVO_N_SW
D SW1 D
1 3 ON/OFFBTN_N
A B

1
SW2 2 4
A1 B1

1
4

1
DI510 5 6

1
5 AZ5123-01F.R7GR_DFN1006P2X2 GND1 GND2 DI501
EMC@ 1 EVQPLHA15_4P AZ5123-01F.R7GR_DFN1006P2X2
NTC325-EKJ-A160T_3P EMC@

2
CI510
1U_6.3V_M_X5R_0201

2
m
3

2
2 EMC_NS@ CI501 1 2 220P_0402_50V_X7R_0402

2
co
s.
ic
at
C C

m
he
IO CONN

Sc
+USB_VCCB
JIO1

ok
1
2 1
3 2
3
FOR S360 Plastic
4
4

o
5
+3VALW
6 5
6
USB2.0
Novo BTN

eb
7
8 7
+3VS 8

+3VL
9
10 9
10
PWR LED
LID_0D_SW_N 11
FPR AMBER&WHITE LED
B [4] LID_0D_SW_N
ot 11 B
ON/OFFBTN_N 12
[3] ON/OFFBTN_N
[3]
[5]
NOVO_N_SW
FPR_LED_AMBER_N
NOVO_N_SW
FPR_LED_AMBER_N
13
14
12
13 HALL Sensor
SD card
N
PWR_LED_WIT_N 15 14
[5] PWR_LED_WIT_N 15
16
USB20_1_N 17 16

MB
USB2.0 P4 [6] USB20_1_N USB20_1_P 18 17
USB2.0 [6] USB20_1_P
USB20_6_P
19
20
18
19
[7] USB20_6_P USB20_6_N 21 20 25 1415 17 IO Common ,connector list type con irm OK，
USB2.0 P5 CR [7] USB20_6_N
22
23
21
22
GND1
GND2
26 PIN1 location ok,but wait the layout brd finna confirml.0610
24 23
24
SP010024L0G CF50241D0R0-05-NH
CF50241D0R0-05-NH
ME@

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
IO CON/Power Button 0.2

Date: Monday, September 21, 2020 Sheet 3 of 11

5 4 3 2 1
 5 4 3 2 1

D D

m
co
s.
LID switch

ic
LID_0D_SW_R_N 2 0_0201_5% LID_0D_SW_N

at
RS1 1 NPI@
C LID_0D_SW_N [3] C

US1
+3VL 1

em
OUTPUT 1
2
3 GND CS2
4 NC 100P 25V J NPO 0201
5 VDD 2 @
EPAD
1

ch
CS1 AH1912-FA-7 X1-DFN1216
0.1U_6.3V_K_X5R_0201
2

kS
oo
B

eb B
ot
N

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Hall sensor 0.2

Date: Monday, September 21, 2020 Sheet 4 of 11

5 4 3 2 1
 A B C D E F G H

1 1

POWER_LED LENSE
LEDI5
+3VALW RI404 1 2 220_0402_1% PWR_LED_N_R 2 1 PWR_LED_WIT_N
PWR_LED_WIT_N [3]

1
L-C192WDT-LCFC_WHITE

1
DI404 DI405

om
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@ EMC@

2
2

c
s.
ic
EMC Request: Modify DI405 Stuff, DI404 unstuff_SIT0927

at
2 2

em
FP_LED
LEDI4

ch
RI405 1 2 220_0402_1% PWR_LED_WIT_N_R 2 1 PWR_LED_WIT_N
+3VALW

kS
RI406 1 2 220_0402_1% PWR_LED_AMBER_N_R 3 4 FPR_LED_AMBER_N
FPR_LED_AMBER_N [3]
1

1
oo
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2
B2972UDBS05P-000114_AMBER-WHITE
1

1
DI408 DI409 DI406 DI407
EMC@ EMC@ EMC@ EMC@

eb
2

2
3 3
2

2
ot
N

EMC Request: add DI408/DI409 SIT_0927

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
FP LED 0.2

Date: Sunday, September 27, 2020 Sheet 5 of 11

A B C D E F G H
 A B C D E F G H

1
USB2.0 CONN 1

APU Port 4
Power Switch place In The MB
For ESD
close to USB Conn

m
+USB_VCCB USB20_1_CON_N

co
USB20_1_CON_P +USB_VCCB
RU4011 2 0_0402_5%

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ JUA2

2
1

AZC199-02S.R7G_SOT23-3

s.
VBUS

1
LU401 EMC@ USB20_1_CON_N 2
USB20_1_P 4 3 USB20_1_CON_P USB20_1_CON_P 3 D-
[3] USB20_1_P 1 1 1 1

1
4 3 4 D+ 5

100U_1206_6.3V6M

470P_0402_50V_X7R_0402

1U_0402_16V6K

1U_0402_16V6K
DU401 DU402 CU402 CU404 CU405 CU403

ic
EMC_NS@ EMC@ GND GND1 6
USB20_1_N 1 2 USB20_1_CON_N @ @ GND2 7
[3] USB20_1_N 1 2 2 2 2 2 GND3

at
8
2 GND4 2

2
EXC24CH900U_4P
ALLTO_C147L3-40439-L

2
RU4021 2 0_0402_5% ME@

em
EMC_NS@
EVT上件CMC,EMC 需求

1
ch
1415 17 IO Common ,connector list type con irm OK，
ALLTOP DC23300HW00 C147L3-40439-L

kS
.0610

oo
3

eb 3
ot
N

4 4

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
USB2.0 CONN 0.2

Date: Monday, September 21, 2020 Sheet 6 of 11

A B C D E F G H
 5 4 3 2 1

Card Reader 2

APU Port 5 500mA CM1

1U_6.3V_M_X5R_0201
UM1

RM11 1EMC_NS@ 2 0_0402_5% 1

+3VS AV18 1 24
D RM11 2 1/16W_6.2K_1%_0402 RREF 2 AV18 48MHz_In 23 SD_D2_R D
LM1 EMC@ USB20_6_R_N 3 RREF SP10 22 SD_D3_R
USB20_6_N 1 2 USB20_6_R_N NPI@ USB20_6_R_P 4 DM SP9 21
[3] USB20_6_N 1 2 +3VS_IN DP SP8 SD_CMD_R
RM2 1 2 0_0402_5% 5 20
6 3V3_IN_1 SP7 19

4.7U_0402_6.3V6M
USB20_6_P 4 3 USB20_6_R_P CARD_3V3 7 3V3_IN_2 SP6 18 SD_CLK_R

0.1u_0201_10V6K
[3] USB20_6_P 4 3 1 1 CARD_3V3 SP5
CM3 CM2 8 17
EXC24CH900U_4P GPIO 9 3V3_IN_3 SP4 16 SDREG CM41 2 1U_6.3V_M_X5R_0201
SD_CD_N 10 GPIO SDREG 15
2 2 SD_CD# MS_INS#

1
RM12 1 2 0_0402_5% SD_WP 11 14 SP3 RM4 1 @ 2 0_0402_5%
EMC_NS@ RM3 SD_D1_R 12 SP1 SP3 13 SD_D0_R
SD_DAT1 SP2

om
25
Diffrence with Common design module:EVT Stuff CMC,EMC request
@ 0_0402_5%
GND

2
RTS5146-GR_QFN24_4X4

c
s.
ic
FOR EMI
SD_D0_R RM5 1 NPI@ 2 0_0402_5% SD_D0

at
C C

CM5 1 2 5.6P_50V_D_NPO_0402
EMC_NS@

em
SD_D1_R RM6 1 NPI@ 2 0_0402_5% SD_D1

CM6 1 2 5.6P_50V_D_NPO_0402
EMC_NS@

ch
SD_D2_R RM7 1 NPI@ 2 0_0402_5% SD_D2

CM7 1 2 5.6P_50V_D_NPO_0402

kS
EMC_NS@
CARD_3V3
SD_D3_R RM8 1 NPI@ 2 0_0402_5% SD_D3 JREAD1
CARD_3V3 SD_D3 1
Close to Connector SD_CMD CD/DAT3

oo
CM8 1 2 5.6P_50V_D_NPO_0402 2
EMC_NS@ DM1 3 CMD
400mA VSS1

1
4

AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
SD_CMD_RRM9 1 NPI@ 2 0_0402_5% SD_CMD SD_CLK 5 VDD

1
6 CLK

eb
CM9 1 2 5.6P_50V_D_NPO_0402 SD_D0 7 VSS2
1 1 DAT0
SD_D1 8

4.7U_0402_6.3V6M

0.1u_0201_10V6K
EMC_NS@ CM11 CM12
SD_D2 9 DAT1
B B
SD_CLK_R RM10 1 NPI@ 2 0_0402_5% SD_CLK DAT2

2
@
ot
2 2

2
CM10 1 2 5.6P_50V_D_NPO_0402 SD_CD_N 10 12
EMC_NS@ SD_WP 11 CARDDETECT SH1 13
WRITEPROTECT SH2
N
14
SH3 15
SH4

T-SOL_5-251301001000-6_NR
ME@

1415 17 IO Common ,connector list type con irm OK，

TAISOL SP07000WG00 5-251301001000-6
.0610

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Card Reader 0.2

Date: Monday, September 21, 2020 Sheet 7 of 11

5 4 3 2 1
 5 4 3 2 1

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4
D D

1
@ @ @ @

Hole

m
co
H1 H2 H3

s.
HOLEA HOLEA HOLEA

ic
1

at
C C

PAD_D2P5 PAD_C2P5D2P5N PAD_D2P5

em
@ @ @

ch
kS
oo
B

eb B
ot
N

A A

Security Classification LCFC Highly Confidential Information Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 S360-ALC-IO DB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Hole/Shielding 0.2

Date: Wednesday, September 23, 2020Sheet 10 of 11

5 4 3 2 1