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Large-Scale
Field-Programmable
Analog Arrays

By J ENNIFER H ASLER , Senior Member IEEE

ABSTRACT | Large-scale field-programmable analog array lution [1] enabled further separation of roles to address
(FPAA) devices could enable ubiquitous analog or mixed-signal the increasing complexity resulting from Moore’s law
low-power sensor to processing devices similar to the ubiqui- scaling [2]–[4]. Digital microprocessors (µP) are ubiqui-
tous implementation of the existing field-programmable gate tous from embedded applications to general-purpose (GP)
array (FPGA) devices. Design tools enable high-level synthesis computing. Programmability enables changing parame-
to gate/transistor design targeting today’s FPGA devices and ters or coefficients in a particular algorithm. Changing the
the opportunity for analog or mixed-signal applications with stored matrix of weights for a vector–matrix multiplication
FPAA devices. This discussion will illustrate the FPAA concepts (VMM) is an example of programmability. Configurability
and FPAA history. The development of FPAAs enables the enables changing the data flow, topology, as well as the
development of multiple potential metrics, and these metrics order or operations. Changing the program for an µP is an
illustrate future FPAA device directions. The system-on-chip example of configurability. Field-programmable gate array
(SoC) FPAA devices illustrate the IC capabilities, computa- (FPGA) devices, programmable and configurable gate-level
tion, tools, and resulting hardware infrastructure. SoC FPAA digital devices, enabled digital designers’ design capabili-
device generation has enabled analog computing with levels ties from gate- to system-level designs. FPGAs are ubiq-
of abstraction for application design. uitous digital computing devices found everywhere over
the last two decades, arising from their initial conception
KEYWORDS | Analog-digital integrated circuits, analog inte-
(1980) and commercialization (mid-1980s) [5].
grated circuits, CMOS integrated circuits, field-programmable
Modifying the parameters or control flow requires sig-
analog arrays (FPAAs), field-programmable gate arrays
nificant changes, such as soldering new components
(FPGAs).
In contrast to digital computation, analog functionality
is considered to be a fixed function. Although digital
computation is considered programmable and config-
I. P O T E N T I A L O P P O R T U N I T Y O F P R O -
urable, where a user can just sit at their laptop and
GRAMMABLE AND CONFIGURABLE
execute many programs, analog computation is believed
ANALOG DEVICES
to require building custom physical hardware (see Fig. 1).
The programmability and configurability of digital com-
Typically, engineers see that digital computing requires
putation have been the primary capability enabling the
writing code, and analog functions require soldering a
decades rise of digital computation. Programmability and
printed circuit board (PCB). Analog elements could include
configurability enabled one group to build machines and
physical devices, sensors, actuators, or other devices oper-
another group to program those machines. The VLSI revo-
ating over real or integer values. As these structures are
the other in most systems, the components that are not
Manuscript received December 31, 2018; revised August 6, 2019; accepted programmed such as digital components. The early neu-
October 17, 2019. romorphic design began to change this viewpoint utilizing
The author is with the School of Electrical and Computer Engineering (ECE),
Georgia Institute of Technology, Atlanta, GA 30332-250 USA (e-mail: several hand-tuned parameters (see [6]), and it only prac-
[email protected]). tically changed with the invention of the first long-term
Digital Object Identifier 10.1109/JPROC.2019.2950173 analog memory element in 1994 [7].

0018-9219 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Hasler: Large-Scale Field-Programmable Analog Arrays

starting from its introduction in 2002 [9]. Early FPGAs

(e.g., 1980s), such as early programmable analog arrays
(see [10]–[12]) and early commercial devices (see
EPAC [13] or Anadigm [14]), were useful for glue logic
and functions and small occasional computations. Analog
computing techniques result in 1000× improvement in
power or energy efficiency and a 100× improvement
in area efficiency, compared to digital computation as
Mead originally predicted [15]. For example, an FPAA
implemented a command-word acoustic classifier (spectral
classification) with hand-tuned weights, achieving
command-word recognition in less than 23 µW with
standard digital interfaces (see Fig. 2) [16]. The full
classification results in less than 1 µJ per classification
(or inference), which has 1000× improvement over
similar digital neuromorphic solutions requiring roughly
1 mJ or higher for just an inference (see [17]).
This article illustrates the capabilities of these FPAA
devices and the opportunities possible with these FPAA
devices. Looking over the range, FPAA approaches show a
move toward computing and signal processing devices (see
Section II), including improving approaches in memory
(see Section II-A), architectures (see Section II-B), and
process scaling (see Section II-C). One can evaluate a
number of metrics for previous, current, and future FPAA
device directions, giving a roadmap for scaling these sys-
tems to larger architectures (see Section II-D). The system-
on-chip (SoC) FPAA concept and family illustrate both the
most advanced FPAA family of devices (see Section IV)
Fig. 1. Large-scale FPAAs enable configurable and programmable
built to date as well as the most advanced tool and
computation utilizing both analog and digital techniques. Classical
digital techniques are ubiquitous and powerful because of
hardware infrastructure (see Section V) developed to date.
parameter programmability and control-flow configurability (e.g., µP Any future FPAA device would likely need to build an
and FPGAs). Classical analog techniques are considered fixed and infrastructure or fit within the existing infrastructure. The
are built custom for a particular application. The typical perception existing tool approaches directly extend to larger chips,
of analog techniques requires significant changes in soldering new
smaller IC processes, and a number of chips for a given
components to modifying the parameters or control flow. Dense
analog memories enable both programmable and configurable
system. The SoC FPAA device family enabling analog sys-
techniques for analog and digital approaches. tem function makes answering questions in analog com-
puting [18] and abstraction, numerics, and architecture
complexity (summarized in Section IV) [19]–[21] both
The hope for programmable and configurable analog possible and necessary for application design.
and mixed-signal devices has been at least as strong if
not stronger than the original drive for digital reconfig- II. P R O G R A M M A B L E AND CONFIG-
urability. An equivalent analog and mixed-signal concept URABLE ANALOG DEVICE HISTORY
could enable the ubiquitous low-power sensor to process- FPGA and FPAA are combinations of components and con-
ing devices. Many perceive analog design as an artistic nections between these components (see Fig. 3) and off-
skill and community; utilizing artists on a large scheduled chip communication. FPGAs could have a number of I/O
project requires careful handling. Having design tools, lines that typically can be programmed to be inputs or out-
enabling the efficient high-level synthesis of mixed-signal puts (see Fig. 3). FPAA I/O lines could transmit or receive
components would greatly improve application opportuni- analog or digital signals as well as direct connection lines
ties as well as reduce potential schedule risk. typical of analog circuits. FPGAs are composed of logic
Current programmable and configurable devices and routing between these devices (see Fig. 3). The logic
(see Fig. 2) have the potential to transform low- is referred to as a configurable logic block (CLB) that
power embedded system design, much the way FPGAs is typically implemented as lookup tables with flip-flop
transformed physical digital implementations (see Fig. 1). registers. FPAAs can also have digital logic and routing
Large-scale field-programmable analog arrays (FPAAs) between digital components. Most FPGAs store the device
look toward analog system applications and computa- state using SRAM elements, with a small minority of
tion [8], similar to the focus of FPGAs for over 20 years, devices using floating-gate (FG) storage techniques; the

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 2. SoC large-scale FPAA device showing a command-word speech recognition (spectrum classification). We show the high-level block
diagram of the SoC FPAA device (left), a typical measurement setup and computational block diagram for command-word speech
recognition, and measured input and classifier output response classifying the word dark in the TIMIT database phrase. The SoC FPAA
includes a processor, as well as analog (A) and digital (D) blocks in the routing infrastructure. This analog computation (<23 µW) is radically
different from the class of expected analog operations.

energy required for SRAM storage in modern processes ratioed capacitors or transistors. These approaches enabled
(100 mW–1 W) can limit some FPGA applications. switching between a few amplifiers or filters, giving the
FPAAs have analog components as well as routing user a few parameters to tune a particular analog function.
between analog and digital components (see Fig. 3). As a result, these devices rarely reached large-scale con-
The routing between analog and digital blocks could figurable systems, and were only used by analog designers
occur between the blocks of devices, with converters because the devices did not have the capabilities to be used
between these blocks, or more finely connected hetero- at a higher level of integration. These approaches are used
geneous analog and digital component populations. The as glue components for analog systems and continue to
components are often organized into regions called com- generate commercial interest (e.g., Anadigm) partially as
putational analog blocks (CABs). CAB components vary the hope of analog reconfigurable systems.
considerably between implementations but often include One SRAM-based FPAA approach reaches a large-scale
nFET and pFET transistors, transconductance amplifiers size for implementing the solutions of nonlinear ordinary
[TA or operational transconductance amplifier (OTA)], differential equations (ODEs) [25]–[27]. The original IC
other amplfiers, passives (e.g., capacitors), as well as more resulted in 400 configurable circuit components (e.g., mul-
complicated elements (e.g., multipliers), starting from the tipliers and integrators) in 100-mm2 area (250-nm CMOS)
earliest devices (see [10]–[14] and [22]–[24]). Once FPAA utilizing 16 CABs organized with 25 components in a
ideas exist, one needs to consider questions of what FPAA smaller crossbar array in each CAB. Roughly, one program-
memory to use (see Section II-A), of what FPAA architec- mable parameter, set by a DAC- or DAC-type structure,
ture to use (see Section II-B), of the impact of FPAA scaling is included with each component. An updated CAB with 20
to smaller CMOS linewidths (see Section II-C), and of how (4 × 5 array, four integrators) components with additional
FPAA implementations compare (see Section II-D). digital infrastructure to access and reuse the computing
infrastructure through DACs, analog-to-digital converters
A. FPAA Memory Techniques (ADCs), SRAM, and SPI interface in 3.7 mm × 3.9 mm
The memory technology for FPAA devices heavily (65-nm CMOS) area [26]. These devices are used for
impacts the application complexity, area, and energy effi- the solution of general ODEs [25], as well as iterative
ciency. The combination of CAB complexity, as well as the solutions of linear ODE systems generated from linear
memory technology used, categorizes the types of FPAA partial differential equations (PDEs) [27].
devices (see Fig. 4). Early FPAA approaches (see [10]–[14] Analog FG devices provide the memory elements for
and [22]–[24]), whether from research or commercial FPAA devices. Section III focuses on FG devices because
sources, utilized SRAMs or similar registers. Analog para- of their significant impact on FPAA devices, different from
meters require a digital-to-analog converter (DAC) for the SRAM heavy implementations for FPGA devices. FG
each parameter in one form or another, implemented as elements set the parameters for computational elements

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Hasler: Large-Scale Field-Programmable Analog Arrays

FPAA [16], utilizing 600 000 programmable parameters

in 350-nm CMOS. The fabric switches use a single FG
pFET device that can be programmed in an analog manner,
enabling computation in routing fabric as well as CAB ele-
ments [39]. These techniques enable 1000× improvement
in computational energy efficiency compared to custom
digital [40], retaining the custom analog computation
improvement [41] even though systems are compiled on
an FPAA. Section IV discusses further the SoC capabilities
and infrastructure.

B. FPAA Architecture Designs

The capability of memory devices for configurable sys-
tems has enabled a wide range of FPAA architectures (see
Fig. 5). Component and routing architectures distinguish
between different FPAA devices, following some similar
paths and lessons learned from FPGA devices. Memory
elements’ crossbar can enable selectivity similar to digital
configurability (see Fig. 5), where the routing might be an
extended crossbar between all the components and out-
puts. Early FPAA approaches typically used these schemes
(see [9]–[12]).
Another approach uses the computational elements for
routing to decrease the area and load capacitance from
large crossbar arrays. The classic approach utilized OTAs
as the computation and routing in a hexagonal routing
Fig. 3. FPAA and FPGAs are related forms of configurable pattern [42]–[45]. These approaches have resulted in the
technologies, where FPGAs are typically a combination of logic gates
highest frequency response for a given IC process by this
and routing, where FPAAs also include analog components in
simple routing structure [42], [44]. Using switches in a
addition to logic gates and routing. These structures can be
programmed and reprogrammed several times depending on the crossbar as computation seems to take a related approach
user’s requirements. to these concepts, utilizing switches for computation as
needed [39].
Fig. 5 also shows the routing architecture for a Manhat-
tan routing scheme. Manhattan routing is typical of FPGAs,
(e.g., OTAs) while using SRAM or similar digital registers as well as in some form for modern FPAAs (see [16], [25],
for routing [28]–[32]. Programmable subthreshold and and [32]). Manhattan FPAA architecture connects CABs
above-threshold current sources are routinely programmed and CLBs through connection (C) and switch (S) blocks.
over six orders of magnitude (e.g., 30 pA–30 µA) with The CABs or CLBs are the buildings, the C blocks enable
better than 1% accuracy at all values, including sub-
threshold current levels [33]. One recent approach enables
FPAA devices targeted for analog at the boundary between
analog designers and system designers [30]. FG elements
are primarily used for setting current and voltage sources
for traditional analog circuits with good performance over
the programming range, providing an excellent framework
for system-level analog designers to utilize these systems;
80 CABs with roughly 260 circuits are controlled through
296 FG device memories for spectral analysis functions.
The required FG programmable voltages are provided
through on-chip charge pumps [34].
Analog FG devices provide both the FPAA memory ele-
ments and the FPAA routing elements. The chip stores
Fig. 4. Complexity comparison between FPAA implementations.
the parameters as well as configuration as nonvolatile
FG parameters and switches allow larger and more complex FPAA
analog and digital values. Starting from the earliest of structures. Enabling SoC infrastructure with FPAA devices utilizes
these approaches in 2002 [9], these techniques con- and manages the larger computation, assisting access to most of
tinued to develop (see [35]–[38]) to the current SoC the available computation.

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 5. FPAA (and FPGA) routing architectures. Simple crossbar: CABs are simply components made up of different configurable elements
(A1, A2, . . . ) (Manhattan, simple crossbar internally). Element-to-element routing: routing through the computational devices, such as OTAs,
to potentially decrease routing parasitics. Element-to-element routing is typically arranged in geometrical patterns, hexagonal or
rectangular. Manhattan routing: multilevel routing architecture connecting CABs and/or CLBs, which have their own connection patterns
(e.g., crossbar), through a set of connection blocks (C blocks) to the higher level interconnection which are routed through the (S blocks).

the street and street access for the routing, and the S blocks very wide bandwidth RF computation. FG approaches have
are the intersections between these routing, allowing to go no apparent limitations in FinFET or silicon on insulator
straight or make turns. This routing scheme is typical of the (SOI) although the capacitor structures modify, given the
earlier Xlinix architectures (e.g., Virtex 2 or 3). VPR/VTR technology capabilities. Therefore, although an FPAA can
[46] can place and route for these architectures. These have a significant performance at a large process node
techniques can allow for a number of unique CAB compo- (e.g., 350-nm CMOS), the opportunities only improve in
nents, such as detailed biologically modeled neurons [47], terms of improved bandwidth, higher energy efficiency,
a technique roughly repeated recently for simpler neurons
using digital computation [48].

C. FPAA IC Process and Frequency Scaling

FPAA operating frequency for a particular Manhattan
architecture, similar to other architectures, is ideally an
inverse as a quadratic function of the minimum IC process
linewidth. Decreasing the minimum linewidth quadrati-
cally decreases the capacitance, typically resulting in an
inversely proportional improvement in energy efficiency
and ideally the same improvement in fabric operating
frequency. One expects the number of parameters to
increase by inverse of the square of the process linewidth.
FG-based routing follows the ideal scaling as the FG
switches are typically programmed to the maximum con-
ductance value [49]. Fig. 6 shows the operating band-
width of a Manhattan architecture, similar to the SoC
FPAA architecture, based on modeling and experimental
data (350, 130, and 40 nm) [49]. This FPAA architecture
Fig. 6. Scaling of FPAA architectures using FG device fabric to
in the 350-nm process operates at 50-MHz bandwidth, anchored from data in 350-, 130-, and 40-nm CMOS, bandwidth is
while in 45 nm, this architecture is capable of 4-GHz from dc to −3-dB corner frequency. Bandwidth of FPAA architectures
bandwidth. A 7-, 10-, or 14-nm FPAA design would enable is a quadratic function of minimum process dimension.

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Hasler: Large-Scale Field-Programmable Analog Arrays

Table 1 FPAA Comparison Table for Significant and Updated FPAA Devices

Fig. 7. FPAA devices are plotted as the percentage of control path implemented versus analog parameter density. Recent FPAA ICs
effectively maximize both parameters. Analog parameter density is the number of analog parameters per mm2 , normalized to a 1-µm
process. Analog parameters directly set the complexity possible by the particular FPAA device.

and higher density similar to the improvements seen from 2.0-µm to 40-nm CMOS (see Section II-C), we nor-
in FPGAs. malize the metrics by this parameter. We define analog
parameter density as the number of programmable para-
D. Metric Comparisons of FPAA Devices meters per mm2 , normalized to a 1-µm CMOS node.
Comparing FPAA devices shows the computational pos- Analog parameter density determines critically the IC
sibilities for multiple architectures from experimental data computation complexity, particularly when using routing
from the current generation of FPAA devices. Table 1 as computation. Fig. 7 shows that the FG-based FPAAs
shows another comparison among FPAA devices in a table enable ≈1000 parameter density improvement, particu-
form, and Fig. 7 plots various FPAA devices showing the larly when used for routing, as will be discussed further
percentage of control path implemented versus analog in Section III providing increased computation on a single
parameter density. Fig. 7 shows the two metrics from device.
many published FPAA devices [9]–[14], [16], [22]–[25], An FPAA should have a large number of programmable
[28]–[32], [35]–[38], [42]–[45], [50]–[58]. parameters, as well as having the infrastructure to get
Because physical implementations of these FPAA devices data communicated to these processing devices. Our sec-
show the quadratic scaling of operating frequency with ond metric describes the amount of control flow (mostly
the inverse of minimum channel linewidth for devices digital) relative to the amount of analog and digital data

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Hasler: Large-Scale Field-Programmable Analog Arrays

characterizes baseline performance of these devices, start-

ing from its initial introduction [64]. The transistor gate
is capacitively coupled by one or multiple capacitors.
Recent ferroelectric capacitors further enable FG circuit
capabilities (see [65]); FG techniques can utilize any
process improvements. The FG charge is modified by
the combination of transistor hot-electron injection and
electron tunneling through a separate tunneling capacitor
(see [33]). The tunneling and hot-electron injection volt-
ages (e.g., 12 and 6 V, respectively, for 350-nm CMOS)
are easily handled through the process (see [33]) and
can be generated on-chip using charge-pump circuits [34].
Handling high-voltage signals, signals higher than the
applied external power supply, can be easily handled on-
chip. High-voltage handling can sit with precision analog
circuits, including not affecting the long-term behavior of
these FG analog circuits. Decades of FG circuit designs
that include memory devices demonstrate this high-voltage
Fig. 8. Single-poly cross-section typical for FG devices. Double design.
poly is used as available, but this device is available in a wide range With typical ESD protection I/O pads, even if higher
of IC processes (e.g., 130 and 45 nm [49]). Practical devices often
voltages for non-FG programming pins are applied, the
have additional process-dependent modifications.
overall IC can be designed to not be affected by these
higher voltages. Practical devices have additional improve-
ments; some are process dependent (e.g., covered by
flow capability. Getting data to all the processors can be NDAs). Process nodes below 350-nm CMOS use the thicker
a primary limitation for a series of application spaces, insulator for all devices, including pFETs. Process nodes
such as image processing, where data do not always arrive below 65 nm use thicker HfO2 insulators for MOSFETs,
in the desired order for the computation. Recent RASP- including pFETs, including for bulk, SOI, and FinFET
based FPAA designs (see [16], [26], [37], and [38]) have
started to focus on improving this second metric. The SoC
FPAA is a strong example (discussed further in Section IV)
optimizing both metrics; the SoC FPAA is nearly 600 000×
parameter density improvement to the closest high utiliza-
tion structure (i.e., PSoC5) [50].

III. F G D E V I C E S A S M E M O R Y A N D
COMPUTING ELEMENTS FOR
F PA A D E S I G N
FG devices will be considered briefly in the context for
FPAA device design, given its huge impact on these archi-
tectures. The original FG circuit concept in the standard
CMOS process [7] enabled nonvolatile parameter storage,
computed using that parameter, and used the compu-
tation potentially modifying (or learning) the long-term
parameter. These concepts were built on a long history
on FG device development, starting from the initial dis-
covery of an MOS FG device [59], [60]) and early uses
of FG devices to store analog quantities (see [61] and
[62]). These devices were the original crossbar compu-
tation. Other nonvolatile devices with the same analog
programmability, selectivity, and density could make a sim-
ilar impact, although non-Si substitute technology seems
unlikely to satisfy these requirements in the near-term
future (see [63]).
Fig. 9. FG switches in the connection (C) blocks, the switch (S)
Fig. 8 shows the top-level (e.g., layout) generic view blocks, and the local routing are a single pFET FG transistor
of a single-poly (standard CMOS) FG device. This core programmed to be a closed switch over the entire fabric signal
structure is used in every FG test structure since it swing of 0–2.5 V [58].

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 10. Using FG parameters results in significantly higher parameter density (100× or larger). We compare between FG parameters and
its next closest solution, having an n-bit DAC at every device. Optimistically, a DAC grows by a factor of 2 for an increase of 1 bit. At 8-bit DAC
precision, 100 FG parameters are smaller than 1 DAC for 350-nm CMOS. We assume an increase for a DAC of 2× for 1 bit. Typically, the cost
will increase at a higher level. Handling mismatch is a key risk for any analog (as well as digital) system; only programmability makes analog
computation practical in a system (including high-precision ADCs).

devices. Sometimes this thicker insulator device is used above or below the power supply rail. The FG pFET is
for I/O devices, so the IC directly interfaces to board-level a standard pFET device whose gate terminals are not
infrastructure. Economic constraints strongly encourage connected to signals except through capacitors (e.g., no dc
multiple gate insulator thicknesses. One should never put path to a fixed potential). With no dc path to a fixed poten-
contacts on the FG node to avoid lower retention rates. tial, stored FG charge results in an FG voltage that can
FG devices have demonstrated long-term (ten-year be inside or outside the power supply rails. The maximum
lifetime) across multiple IC processes from 2-µm to 40- FG voltage is limited by the programming scheme for the
nm linewidths [66]–[68] as well as have shown precision device [58]. To program an OFF-switch, the pFET FG gate is
targeted (re)programming of heterogeneous arrangements set well above Vdd , setting the transistor in accumulation,
of FG devices (see [33]); FG devices have been used for effectively conducting no current (e.g., <1 pA) throughout
high-matching analog circuits [69], including references the entire operating range [84]. To program an ON switch,
[67], amplifiers [66], sensor interfaces [70], filters [71], the pFET FG gate is set well below GND, setting the
[72], and data converters [73]–[75], enabling dense high transistor above threshold throughout the entire operating
signal-to-noise ratio (SNR) devices. FG devices have range [84]. Fig. 9 shows the measured ON -switch resis-
demonstrated multiple commercially qualified and sold tance for a 2.5-V supply for a pFET with its gate at GND
devices. FG devices have been used in acoustic [76] and and an FG pFET with the FG programmed below GND.
imaging [77], [78], utilizing energy-efficient (1000× ver- This maximum ON conductance is roughly independent
sus custom digital) signal processing [79] as VMM [41], on process minimum channel length. The conductance
filterbanks [71], Gaussian mixture models (GMMs) [80], is set by velocity saturation of electrons/holes for the
support vector machine [81], VMM+Winner-Take-All MOSFET channel [49]. These devices allow for nearly ideal
(WTA) classifiers [82], and adaptive filters [83]. switches, including in a crossbar array configuration (see
A single FG pFET can approximate an ideal switch in Fig. 9), and do not constrain the FG voltage that can be
FPAA routing crossbar (see Fig. 9). One might be surprised programmed between the ON and OFF states. Although
that a single pFET operates as a good switch, because of one might consider the nonlinear behavior if using this
traditional wisdom states that an nFET can only pass lower switch as a resistor, typically the resistance is significantly
signal values, while a pFET can only pass higher signal val- smaller than other circuit elements. One typically can
ues. Transmission (T)-gates use a parallel combination of ignore these nonlinear behaviors and often can ignore the
an nFET and pFET with a CMOS inverter for a good switch resistances entirely.
throughout all power supply rails. A T-gate is programmed FG elements provide a dense analog nonvolatile para-
digitally, either ON or OFF, controlled by a stored digital meter integrated within a computational fabric, a memory
value. Digital storage limits the computing opportunities element for both parameters and routing. The alternative
of this T-gate switch. to using FG memory elements is using a DAC or DAC device
A single pFET device is a good switch over the (e.g., capacitor bank) for every parameter. Dynamically
entire operating range, because the FG voltage can exist storing voltages on a capacitor and refreshing from a

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Hasler: Large-Scale Field-Programmable Analog Arrays

far higher precision (>14 bit [33]). FG device comparison

only improves for scaled-down technologies. Fig. 7 shows
that the FG-based FPAAs enable ≈1000 parameter den-
sity improvement, providing increased computation on a
single device.
Using FG parameters explains the 1000× advantage of
using FG devices for parameters and routing (see Fig. 7).
Only using FG for parameters, and not routing, improves
the density metric from 0.55 parameters per normalized
mm2 using DACs [25] to 2.8 parameters per normalized
mm2 using FG parameters [32]. The full advantage is
not apparent because of the large amount of resulting
routing that only connects devices but is not useful for
computation. On average, utilizing FG routing improves
parameter density by 200× in area.
These FG pFET retains its analog programming range,
unlike T-gate switches, not constraining analog computa-
tion in the crossbar array (see Fig. 9). Because the array
FG pFET can be programmed anywhere between the OFF
and ON states, the resulting device still is an operational
transistor for multiple uses, including a current source, cas-
code element, or a resistor. These FG pFETs are integrated
into a crossbar network, typical of VMM topologies [40].
One effectively gets crossbar computations, originally
described in FG devices [7]. for free in an FPAA approach.
The FPAA computes in the colocated memory space
Fig. 11. FPGA and FPAA computing architectures. A basic FPGA
includes CLBs and routing to connect the CLBs and I/O for a
of switches.
particular computation. Larger FPGAs are more structured forms of Computation in FPAA fabric represents a dramatic
these blocks. Practical FPGAs are only efficient with VMM support departure from classical FPGA architectures. (see Fig. 11).
for signal processing and matrix algebra computations (e.g., deep
NN), implemented through specialized rows of multipliers (often
with adders) and specialized local memory for cycling through
required VMM coefficients. These additions improve many FPGA
computations while eliminating area for additional CLBs. A basic
FPAA also includes CABs or CLB and routing. At a high level, the two
approaches look similar. A closer look shows that the FG-enabled
routing crossbar is excellent switches, as well as enabling VMM in
the routing as a result of analog programming. Unlike FPGAs, all
switches in some FG-enabled FPAA devices are potential places of
computation. For FPAAs, switches are not dead weight. FG stores a
charge, Q, at the floating node, allowing storage of analog voltages
that can be inside or outside the power supplies (GND and Vdd ).

single DAC results in higher complexity and energy for

these operations. Fig. 10 shows the significant oppor-
tunities of programmable FG analog concepts compared
to alternative approaches, a DAC for every parameter.
The DAC approach is a set of ratioed current source
transistors (and similar to ratioed capacitors), where the
number of devices doubles for each increasing bit to
minimize mismatch; in practice, the situation is prac-
tically less favorable to the DAC design. The FG area
requires infrastructure [33] for FG programming. If one
only needs 2–8 parameters, then 6–8-bit DAC area is
similar to the resulting FG area. FPAA devices practically Fig. 12. Analog and digital computation are typically separated
through data converters. Reinvestigating this assumptions shows
require thousands, if eventually not millions to billions of
many systems that are a combination of analog and digital,
parameters. For 1-mm2 die area in 350-nm CMOS, 220 including data converters. Recent FPAA ICs, including the SoC FPAA
6-bit DACs take a similar area to 16 000 FG parameters IC, enable utilization of analog and digital configurable components,
(see Fig. 10). The FG device in this process is capable of where components are positioned near each other.

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Fig. 13. SoC FPAA IC. (a) Functional block diagram illustrating the resulting computational blocks and resulting routing architecture. The
infrastructure control includes a µP developed from an open-source MSP 430 processor [86], as well as on-chip structures that include the
on-chip DACs, current-to-voltage conversion, and voltage measurement, to program each FG device. Eight, four-input Boolean logic element
(BLE) lookup tables with a latch comprise the CLB blocks. Transconductance amplifiers, transistors, capacitors, switches, as well as other
elements comprise the CAB blocks. (b) Table of important SoC FPAA IC parameters. (c) Summary of application complexity of analog and
digital elements. The chip has 98 CLBs and 98 CABs.

Many FPGA architectures are optimized for VMM opera- interdigitates analog and digital computation at a fine-
tions as a fundamental computation and signal processing grain level in the same routing fabric. Classically, one
operation. GPU architectures are optimized for similar assumes that analog and digital computations are widely
computations. These FPGAs are specialized with multiplier separated, communicating through ADCs and DACs (see
units as well as specialized memory blocks to enable Fig. 12). Many operations, such as classifiers, require
efficient VMM computations, cycling through memory for analog and digital logic together. An N -bit ADC is a
different matrix coefficients. In the FPAA with FG switches, specialized simple classifier identifying an incoming signal
the switches are not the dead weight to connect com- with one of 2N levels. This classification occurs by utiliz-
ponents [39], but they are computing memory elements ing one or multiple comparators using analog inputs and
greatly increasing the potential computation available in digital outputs (see Fig. 12). Analog computation often
an FPAA. The FG FPAA does not require these special- requires digital control flow, again typical in ADC concepts.
izations, but rather VMM computations are computed in These examples show the need and simplicity of integrat-
routing fabric. The boundary computations of the VMM ing these spaces. From the experience compiling a number
computation primarily set the architecture complexity, and of systems in earlier FPAA designs, some FPAA designs
the VMM is nearly free in as a unique routing pattern. started integrating digital infrastructure control [37], as
Other computations can be implemented in the rout- well as interdigitated analog and digital fabric [38]. The
ing infrastructure (see [85]). Further routing infrastruc- SoC FPAA fully integrated analog and digital columns,
ture improvements can enable additional computation enabling analog and digital signals routed on the same
advantages. fabric (see Fig. 12).
Fig. 13 shows and summarizes the SoC FPAA IC [16].
IV. S o C F P A A I C A N D R E P R E S E N T A - This SoC FPAA utilizes a configurable fabric integrating
T I V E A P P L I C AT I O N S analog (A → CAB) and digital (D → CLB) components,
The SoC FPAA IC represents the most complex FPAA and specialized blocks, as well as an on-chip µP, SRAM memory,
the first FPAA to be a complete SoC [16]. The SoC FPAA and digital I/O communication ports [see Fig. 13(a)].

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 14. Use of T-gates in FPAA fabric for rapid reconfigurability. (a) Circuit diagram of the digital-enabled routing fabric using a set of
T-gate switches to dynamically reconfigure the SoC FPAA fabric. (b) Simple circuit compilation using this SoC FPAA fabric for a compiled
physically unclonable function (PUF) element. Mismatch in the indirect FG programming infrastructure creates the unique code.

Fig. 13(b) shows the table of parameters for the result- originally started in [37]. The I/O lines for the added
ing SoC FPAA. Analog FG enables both analog and dig- T-gate row and the shift register signals are available
ital functionality within the Manhattan geometry. The through the routing fabric. These volatile switches are
CAB devices are typical of earlier CAB designs, being found directly at the interface between the C block
combinations of transistors, OTAs, FG transistors, OTAs, and the local interconnect; depending on the desired
capacitors, T-gates, current mirrors, and signal-by-signal higher level of abstraction, these switches may be con-
multipliers (see [35]–[37] and [84]). The low-power sidered as part of either block. One simple applica-
programmable and configurable FPGA fabric, streamlines tion of this technique is enabling a scan chain for
the routing of analog and digital signals through a con- either digital or analog circuit debugging. Fig. 14 shows
tinuous fabric. Fig. 13(c) shows the representative cir- the added routing structure component that enables
cuits compiled and experimentally measured [16], as rapid reconfigurability in the FPAA fabric. These tech-
well as a summary of the resources used in each case. niques minimize the amount of intermediate data stor-
The hardware platform directly maps to compiler tools age required for many computations, enabling data flow
(see Section V). techniques for analog processing. Intermediate data stor-
The processor supplements the digital processing system age often requires the largest power and complexity
capability and increases overall implementation flexibility; system cost. The rapid fabric reconfigurability can
portions of a problem can be mapped to reconfigurable change between programmed aspects in a single clock
analog, reconfigurable digital, or a GP digital processor. cycle or asynchronous request–acknowledge loop. SoC
The FPAA employs an open-source MSP 430 microproces- FPAA shift register control signals are directed by locally
sor (µP) [86] with on-chip structures for 7-bit signal routed signals in the fabric, thus determining the control-
DACs, a ramp ADC, memory-mapped GP IO, and related ling clock (Clk) and data signals [see Fig. 14(a)]. Data
components [see Fig. 13(a)]. The processor is able to stored in the FG fabric would be as optimal as data stored
send information to and from the array through memory- in an off-chip nonvolatile memory without the complexity
mapped I/O special-purpose peripherals. These peripher- of loading the resulting computation.
als include 16 memory-mapped 7-bit signal DACs for the The SoC FPAA, as well as earlier families of FG-enabled
architecture, allowing measurements to be performed on- FPAAs, demonstrated a number of core concepts. FPAA
chip, with the data taken by and stored in the processor, temperature behavior, modeling, and design [87]–[89] are
as well as additional DACs (and one 14-bit ramp ADC) for an essential issue for computation. FG circuits can be
the FG programming. programmable and can have weak functions of temper-
Additional digital control infrastructure in the routing ature. FG devices enable directly eliminating mismatch
fabric enables rapid reconfiguration of the analog data or setting desired targeting values in the configurable
path. The routing fabric is capable of partial rapid recon- structure. These FPAA devices demonstrated many on-
figurability, while using mostly FG devices, by adding an chip classifiers sensor-to-output ultralow power classifica-
additional set of switch configuration into the fabric. This tion [16], [82], [90]–[92], embedded machine learning
rapid reconfigurability comes by adding a row of T-gate for sensor-to-output classifiers [90], [91], robotics and
switches set by a shift register into the switch fabric, path planning [93]–[95], image processing [37], and

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Hasler: Large-Scale Field-Programmable Analog Arrays

Table 2 Measured Power Numbers for Compiled Command-Word Classi- development of sensors and their integration, greatly
fier Function improving the speed of sensor integration. Custom analog
circuit design tends to be the primary limitation for inte-
grated sensor development.

V. S o C F P A A T O O L S A N D H A R D W A R E
INFRASTRUCTURE
Ubiquitous use of FPAA devices requires an IC infrastruc-
ture and tools, as well as a user base who can utilize these
capabilities. The user of these technologies is more likely
to be system design and application engineers, individuals
who have not obtained a higher degree in analog IC design.
A set of user-friendly, high-level tools (e.g., graphical)
is enabling chip design to compile FPAA IC for a wide
range of energy-efficient applications integrating a number
of sensory modalities (acoustic and imaging), potentially
for context-aware applications (see Fig. 15). System-level
FPAA development requires these capabilities, particularly
because designers are used to similar tools for digital-based
design. Although these capabilities might have seemed
mostly theoretical a decade ago, a reasonable system
design time by a wide community requires these capabil-
ities. The success of these tools requires a framework for
analog computing [18].
This discussion will focus heavily on the SoC FPAA
design tools, infrastructure, and implications [16], because
it has developed and reported, by far, the largest amount
of tool and infrastructure discussion, to date (see Fig. 16).
Fig. 16 shows a high-level view of demonstrated SoC
FPAA infrastructure and tools, including FG programming,
device scaling, and PCB infrastructure, through system
enabling technologies as calibration and built-in self-test
methodologies and through high-level tools for design as
well as education (see [101]). Sections V-A–V-C discuss

Fig. 15. FPAA devices provide the ultralow energy/power

capability for future embedded system applications.

low-power biomedical implementations [96]–[98]. The

largest existing signal processing functions take a small
percentage of the available IC (≈12 CABs and minimal
CLB resources). Table 2 shows the energy breakdown for
an FPAA device for the application in Fig. 2. FPAA devices
as potential applications for embedded Internet of Things
(IoT) and remote sensor nodes are capable of secure
operation, both in currently demonstrated capabilities such
as the implementation of PUF circuits [see Fig. 14(b)]
and implementable functions for secure embedded FPAA Fig. 16. SoC FPAA approach consists of key innovations in FPAA
hardware, innovations and developments in FPAA tool structure, as
devices [99].
well as innovations in the bridges between them. One typically
FPAA integration with sensors, including sensors fab- focuses on what circuit and system applications can be built on the
ricated on the FPAA fabric [57], [100], opens addi- FPAA platform, but every solution is built up for a large number of
tional new possibilities. FPAA devices can enable parallel components ideally abstracted away from the user.

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Hasler: Large-Scale Field-Programmable Analog Arrays

these capabilities, including FPAA tool framework (see tools give the user the ability to create, model, and sim-
Section V-A), FPAA infrastructure (see Section V-B), and ulate analog and digital designs. High-level design tools
FPAA education (see Section V-C). This tool framework is (see Fig. 16) have been essential to the SoC FPAA devel-
directly applicable to other FPAA devices (see [25], [32], opment [118]. High-level design tools, implemented in
and [45]), and we encourage an open community in these Scilab/Xcos, enable automated compilation to a switch list,
directions. The SoC FPAA tools and PCB infrastructure are the description of the programmed FPAA hardware [118].
openly available as open-source tools.1 A standard tool The tools designed to enable a noncircuits expert, such
and infrastructure platform enables faster utilization and as a system applications engineer, to investigate particular
development of next-generation FPAA applications. algorithms. Tools enable system-level design (level = 1)
and circuit-level design (level = 2) (see [87]), including
A. Analog Tools and the SoC FPAA Toolset both FPAA targeting and simulation [120]. Tools enable
Tools are essential for FPAA system design. While iden- physical noise modeling (see [87]) allowing for simulated
tifying every switch is easier than IC layout, design, prediction of the effect of noise on a compiled system as
verification, fabrication, and testing for analog IC engi- well as the resulting system SNR. The chip details are
neers, system designers will expect higher level capabili- specified in architecture files for analog-to-digital SoC.
ties. Most of these designers do not want to know about Analog block library is similar to a high-level software
transistors and analog transistor circuits, and yet, the tools definition or library. The graphical high-level tool uses
must enable efficient use by analog IC designers to enable a palette for available blocks that compile down to a
blocks for application designers. Tools are essential for combination of digital and analog hardware blocks, as
application-based system design using physical systems, well as software blocks on the resulting processor. The
given the modern comfort with structured and automated analog Scilab/Xcos system is a visual programming lan-
digital design from code to working application. guage in the same tradition as Simulink, building on
Digital design tools for FPGAs are widely accessible. aspects of visual programming languages [121], [122],
Well-established FPGA design tools include Simulink [102] and data flow languages [123], [124]. Abstracting ana-
compilation for Xlinix [103] and Altera FPGAs [104], log design for system designers increases the chance
[105] devices. FPGA manufacturers also have their of automation to be utilized. Graphical algorithms are
own toolset for Verilog/VHDL compilation to hardware. popular for graphical FPGA tools, such as the recent
Simulink, and to a lesser extent some open-source and independently developed open-source tool, Icestu-
tools (see [106]), provides the framework to input into dio [125]. The result is a rich set of analog and digital
Xlinix/Altera compilation tools, completely abstracting blocks similar to FPGAs when using graphical design tools
away the details from the user, by allowing both standard (see [102]).
Simulink blocks to compile to Verilog blocks to targetable This open-source tool platform creates an integrated
hardware, as well as support for specific blocks on that environment running in Scilab/Xcos integrating multiple
hardware platform. tools, such as x2c, with modified open-source digital place
In contrast, analog design tools have a brief history, and route (VPR [46]) tools. x2c converts high-level block
including theoretical analog automation tools, as well as description by the user to blif format, the input to the
early FPAA ICs [107]–[111]. Macromodeling techniques, modified VPR tool, utilizing vpr2swcs (scilab → blif), as
making a simplified algebraic or numerically simple ODE well as modified architecture file. The resulting tool uses
circuit model, remain a key framework for analog design analog, as well as mixed-signal, library of components.
(see [112] and [113]). Some techniques are coupled with A single Ubuntu 12.04 Virtual Machine (VM) abstracts the
digital tools for joint analog and digital system verifica- entire tool flow from the user, from Scilab/Xcos, device
tion [114], [115]. Labview is a nonopen-source approach library files, through sci2bliff, vpr2swcs, and modified VPR
for representing analog and digital components that do tools, by simply requiring pressing one button to bring up
have some aspects to connect to physical instruments the entire graphical working toolset.
(see [116]) and with an infrastructure that might be Tools open the space for abstraction. The multiple levels
adapted to create a similar flow. Custom analog IC design of analog abstraction in a typical implementation (see
has little additional tool support than low-level IC design Fig. 17) can be abstracted from the designer who only
tools. Many companies (see [117]) have tried to automate needs to use higher level blocks (blocks in measurement
the analog design process but failed because the solution setup of Fig. 17). Fig. 17 shows a typical use of the C4
was aimed for analog IC designers who are artistic critics block in an acoustic front end for creating subbanded
of other analog designs. outputs. The core computational chain, C4 Bandpass filter
Physical FPAA implementations drove the development + Amp Detect + LPF, all compiles into a single CAB.
for analog and mixed-signal design tools, particularly the FG elements (e.g., FG-enabled OTA elements), as well as
SoC FPAA implementation, as well as FPAA ICs leading tunable capacitor banks, enable this abstraction and can
up to the SoC FPAA devices [87], [118], [119]. These be tuned around mismatches (see [126]). The abstraction
includes computation and testing instrumentation blocks
1 Tools can be downloaded at hasler.ece.gatech.edu. into a single complete compiled system. This measurement

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 17. Tool blocks for acoustic subband computation: Bandpass filter bank, amplitude detection, and time window filtering for later
processing. Measuring this block introduces the amplitude detection and first-order LPF blocks, both requiring one OTA each. These three
elements make up a subband compute block. The structure requires the scanner block, targeted as a set of T-gate switches and shift register
in routing between the CABs and C block routing, to multiplex the multiple signals. The scanner is controlled by digital output block taking
µP signals into the CAB. The measure voltage block is a low-frequency (200 SPS) block utilizing the 14-bit ramp ADC in the programming
infrastructure [33] to connect with the digital system. The approximate gain from In through the ADC is nearly 1 and calibrated on-chip [126].

illustrates the measure voltage block, effectively a slow- A simple structure facilitates user integration and adop-
speed (200 SPS), high-resolution (14-bit) voltage mea- tion. The SoC FPAA programs the FG elements using the
surement. The structure uses the FG programming µP. A single data stream is downloaded to the processor
circuitry, including the 14-bit measurement ramp ADC, still that includes processor object code and programming data
available in the run mode. These blocks abstract further (e.g., the switch list from tool compilation); the final
as the subband processing stage as the front end of an processor data are its operational code after programming.
acoustic classifier (see [16]). The structure is simple enough to enable simple down-
With the higher level of abstraction, handling the code- loading code libraries (e.g., python and Java) to stream
sign issue between at least analog code, digital code, the device data as well as the TCL framework used by
and µP code becomes immediately apparent. Tools should the design tools. The primary hardware infrastructure is
enable designers to effectively and efficiently design µP IC controlled 6- and 12-V charge-pump ICs, as shown
through the large number of open questions in this in Fig. 18(a). Charge pumps for FPAAs, as already demon-
analog-to-digital codesign space. Digital-only Hardware- strated [30], reduces the board infrastructure further.
Software CoDesign is an established, although unsolved A history of on-chip FG programming development is
and currently researched, discipline (see [127]–[130]); presented in [33], some of it connected with programming
incorporating analog computation and signal processing FPAA devices.
adds a new dimension to codesign. The rest of the infrastructure should be simple to
minimize user challenges as well as complexities, and
B. SoC FPAA Hardware Infrastructure yet functional enough for the desired range of applica-
Infrastructure is essential for FPAA system design, as a tions. Fig. 18(a) shows a GP test infrastructure based on
critical aspect to use the IC developments and tool capa- earlier GP boards for earlier FPAA devices (see [132]).
bilities. Treating infrastructure design with the same atten- The board uses a single USB interface for power [see
tion as IC design eliminates unnecessary bottleneck for a Fig. 18(a)], a simple serial (8n1) debug interface into
user base, as well as the original designers, to innovate the chip, and an interface to other serial standards (e.g.,
using these devices. The goal of this section is to illus- SPI). Boards for specific applications will be optimized
trate the range of infrastructure possible with the existing along with required specifications while benefiting from
FPAA devices (see Fig. 18), primarily SoC FPAA devices a GP open reference design.2 The FPAA board looks
(see [131]), to encourage additional creativity for FPAA like simple digital peripheral using a standard digital
users to innovate using these devices.
Programming the FPAA IC sets the software and hard- 2 The boards developed at the Georgia Institute of Technology are
ware infrastructure for the FPAA board [see Fig. 18(a)]. openly available at http://hasler.ece.gatech.edu.

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Hasler: Large-Scale Field-Programmable Analog Arrays

Fig. 18. (a) Detailed picture of the SoC FPAA board. Top: process flow for chip-on-board (CoB) build for the resulting IC board. Bottom:
detailed block diagram for the SoC FPAA board. The FPAA control board primarily handles the USB to serial communication interface, the
programmable clock generator, as well as the multiple supply voltages, controlled by the FPAA, required for operation and programming of
the FPAA device. (b) Connecting the FPAA board to Android tablet. An OTG cable is used to handle USB I/O, allowing the device to recognize
the FTDI IC’s serial port. The tools described in this article allow programs to communicate at a high level with the FPAA µP. (c) Remote test
system based on FPAA devices that can be used within our current framework of high-level, open-source Xcos/Scilab tools. With a single
button click in the graphical tool, the system will e-mail the resulting targeting code for the FPAA device to a server location, to be picked up
by the remote system, which compiles, runs, and then e-mails back the target results.

communication interface (i.e., USB), allowing minimal developed Java code library [133]. The package makes use
(Linux) code for programming and operation for contin- of the Android API to access the device’s serial port, making
uous data processing. it easily portable to other devices. FPAA devices can be
The simple structure and range of coding languages available as a remote device, controlled through a simple
to program the FPAA enable a range of user experiences Unix platform using a Python code library [see Fig. 18(c)],
with this FPAA device. FPAA devices can be powered, operating using a POP e-mail server [134]. The high-level
programmed, and controlled through Android devices [see tools are the same for the remote system or in-hand system,
Fig. 18(b)] and therefore through a device app, using a where a user simply needs to choose a different button

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Hasler: Large-Scale Field-Programmable Analog Arrays

to “e-mail” the compiled structure, verses to “program”

the local device with the compiled structure. An e-mail
server enables a relatively stable remote platform capable
with nearly zero administrative overhead. These systems
go beyond simple one-way updating of FPGA software
for fielded devices [135]–[139], enabling user interaction
of programming and data analysis. This device illustrates
using an FPAA as a small IoT block.

C. SoC FPAA Hardware Impacting Engineering

Education
The availability of FPAA devices with an abstracted tool
flow and user infrastructure enabled educational oppor-
tunities. Education becomes essential to the long-term
viability of FPAA opportunities, in much the same way
that education was essential to the viability of FPGA of Fig. 19. Moving from classical discrete circuit concept toward
DSP processor opportunities over two decades ago, by system-level design, empowered by FPAA devices. A typical classical

empowering generations of students with the knowledge first junior-level transistor circuits course focuses on learning many
forms of a traditional audio amplifier. The focus is on design with
and framework to use these devices. These same stu-
discrete parts, where the transistor is the difficult element. The
dents greatly benefit using advanced technology to enable system-focused first junior-level course covers many of the same
learning about mixed-signal computation at several levels, circuit fundamentals and results in students designing a system
learning in a physically real system. Using FPAAs in the component (e.g., a ramp ADC). FPAA concepts empower the ability

classroom is a huge application area for any viable FPAA to move toward a system-level course as well as a hands-on circuits
course. The FPAA structure just requires a board connected (through
technology. The focus of this section is to overview the
USB) to a student laptop with our open-source VM.
FPAA use in educational experiences.
Commercial FPAA devices open a number of academic
institutions to develop their own FPAA educational appli- These techniques moved to other courses, including
cations. Anadigm’s FPAA devices have found their way into a first transistor circuit class (see Fig. 19) taken by
a range of applications over two decades. Anadigm FPAA undergraduate students in their third year (ECE 3400)4
devices have been used for class development (see [140]), in Fall 2016 [101], [147]. The course became a hands-
as well as part of academic development (see [141] and on, design, devices-to-systems course, resulting in a sig-
[142]). Anadigm has sufficient graphical tools for their nificant difference in how students approached circuit
designs for their small but effective FPAA devices, obtain- design. The classroom implementation only required FPAA
ing functional blocks with 90 dB of SNR [143]. As addi- boards, without any other technology, specialized labo-
tional commercial FPAAs are available, the capabilities and ratory spaces or additional human resources. This study
opportunities will increase exponentially. opened a number of undergraduate curriculum questions
FPAA hardware platforms have been central to hands- due to the change in circuit implementation medium from
on circuit courses at Georgia Tech (GT) for over a decade. discrete circuit design to configurable mixed-signal hard-
Neuromorphic Analog VLSI Circuits (ECE 6435)3 has ware [147]. The students heavily utilized remote FPAA
utilized FPAA devices since 2005 for its hands-on lab- system during this course to characterize and design a
oratory experiences (starting with [35]). These devices number of circuits (see Fig. 19). Several groups success-
initially significantly reduced the required significant fully designed and characterized a ramp ADC, includ-
bench infrastructure and before-class IC fabrication [144], ing full low-frequency linearity (INL and DNL). Previous
reducing the required generation equipment every few remote test systems that have to spend considerable time
years [145], and eventually eliminated the need for any in developing their hand-tailored configurable system for
additional test equipment other than an FPAA board using educational directions [148]–[153]; the FPAA tools elimi-
the SoC FPAA devices [131], [146]. The simple and acces- nate this issue.
sible laboratory framework is a student laptop-based setup
using an SoC FPAA device (through USB) and/or remote VI. F P A A S U M M A R Y , N E X T
SoC FPAA device designed through graphical Scilab/Xcos- D I R E C T I O N S , A N D L O N G-T E R M
based tools. The SoC FPAA, and resulting infrastructure, I M P L I C AT I O N S
creates a portable student user experience different from Current FPAAs have the potential to, as well as
any typical laboratory. started demonstrating the ability to, transform low-power

3 The course information is openly available at the website: http: 4 The course information is openly available at the website: http:

users.ece.gatech.edu/phasler/ECE6435. users.ece.gatech.edu/phasler/ECE3400.

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Hasler: Large-Scale Field-Programmable Analog Arrays

embedded system design, much the way FPGAs trans- be handled by analog circuits at the I/O pins or by more
formed physical–digital implementations. The history of specialized FPAA design at the edges or throughout the
FPAA approaches shows a move toward computing and routing fabric.
signal processing applications with sufficient metrics to One might wonder about the future of FPAA devices
open these opportunities toward computing applications. given current development, which we will discuss some
FPAAs, such as the SoC FPAA family, illustrate the system- potential perspectives in the rest of this section as well as
level capabilities, as well as tool and hardware infrastruc- directions to reach these opportunities. One can visualize a
ture opportunities. Design tools enable that design from world where analog and mixed-signal reconfigurability in
high-level synthesis to gate/transistor design is the real- various forms will be as common as digital reconfigurabil-
ity for digital applications today with FPGA devices ity today in all of its various forms (e.g., µP, FPGAs, and
and is appearing for analog or mixed-signal applica- GPUs). Even when custom analog and mixed-signal ICs
tions with FPAA devices. Large-scale FPAA devices already are designed in this future, some aspects of configurability
have the potential to empower ubiquitous analog or will still be used, just as custom digital designs still utilize
mixed-signal low-power sensor to processing devices sim- reconfigurability today.
ilar to the ubiquitous implementation of the existing FPAAs require commercial sources to fully unleash their
FPGA devices. technological impact. Anadigm’s steady commercial mar-
A usable programmable and configurable technology ket shows the extremely high interest and hope in config-
(e.g., SoC FPAA [16]) requires maturing analog/physical urable analog and mixed-signal opportunities, particularly
computing capabilities empowering this disruptive FPAA given their heroic efforts with a very limited configurable
technology toward commercial opportunities. Physical chip that could be replaced with less than $1 in parts.
computing, computing over real values versus integers, These chips have already used for initial prototyping
includes the space of analog, neuromorphic, quantum, and educational projects. Commercialization of SoC-type
and optical computing, unifying the mutual opportuni- FPAA ICs represents a generational improvement over the
ties between these areas. Physical computing framework’s existing capabilities. Many designs can be developed into
recent development has focused on analog techniques, industrially hardened IC products. Early use of system-
including starting the analog framework [18], demonstrat- level FPAA devices in education and research directions
ing and developing analog abstraction and hierarchy [19], shows numerous initial promising directions.
the development of analog architecture theory and algo- Families of FPAA devices, similar to FPGA devices, are
rithmic complexity [21], and the development of analog expected with a number of die sizes and optimizations
numerical analysis [20]. for energy consumption. Some FPAA devices should have
Related to the development of a physical computing specialized fabrics and components for particular compu-
framework, one asks about the SNR of FPAA components tations, such as embedded machine learning or neuro-
and the resulting computation. For simple FPAA devices morphic approaches (e.g., as in early work [47], [154]).
of isolated components of nontunable SNR with switch Specialized FPAA devices for special voltage and power
matrix connections (e.g., Anadigm), SNR metrics can be conditions, such as neural stimulators or RF transmit-
reasonably specified and estimated (see [142]). These sim- ters, could integrate with general FPAA devices. These
ple estimates are no longer applicable with advanced FPAA generic FPAA devices that can be electronically mea-
devices (e.g., SoC FPAA) due to programmable currents, sured at every node enable a trusted, secure, and legacy-
potential of fine-grain (e.g., transistor level) compilation, resistant computational platform. The existing FPAA
and use of routing fabric for computing and passive ele- devices can be adapted to secure small embedded network
ments. A circuit’s load capacitance is configurable to a wide devices [99].
range of possible sizes [16]. One can compile an FG OTA Scaling FPAA designs to state-of-the-art processes
amplifier with greater than 1-V linear range (2.5-V supply) enables computational problems beyond what is imagined
with a load capacitance greater than 10 pF, resulting in by current digital computing structures. Scaling opens up a
an SNR (thermal noise) greater than 100 dB (>16 bit). range of new architecture approaches between GPUs and
One can choose even parameters for some circuits to FPGAs in a uniquely mixed-signal manner. Scaling opens
achieve even larger values. Such a response does not FPAA designs to the complexity sizes of current GPUs (e.g.,
say that every circuit will achieve 16 bit or higher SNR, video and image processing), while offering far greater
but rather the SNR of the circuits compiled will depend energy efficiency per parallel operation, or the complexity
upon the particular design and only have slight limita- to directly compute a number of PDE computations (e.g.,
tions based on the infrastructure. A careful understanding charged particle computations) on a single device. Scaling
of the question is essential to set reasonable expecta- FPAA designs enable higher density (100× expected from
tions and communication. Typically, the issues that limit 350 to 40 nm), lower energy and power (100× lower
the operation of a particular FPAA design involve higher from 350 to 40 nm), as well as lower commercial cost
input voltage levels (Vdd = 2.5 V) or handling of high- per computation from the existing designs. Smaller CMOS
power levels using a particular design; these issues can linewidths (e.g., 40 nm) also enable RF signals through

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Hasler: Large-Scale Field-Programmable Analog Arrays

routing fabric [68]. The improvements assume the design computation. One can imagine a large user community
iterations to optimize the resulting designs. The technology developing a wide library of analog and digital components
risk in scaling is low, as devices and initial routing fabrics for these new devices. Analog component and system reuse
for FG and non-FG structures have been demonstrated will become a standard practice. The tools need to be
in the 40-nm CMOS range (see [26] and [68]). Pro- flexible enough to handle a wide range of architectures,
grammable techniques enable scaled-down analog design, including multiple ICs. These communities will be heavily
avoiding the difficulties that device mismatch creates for built through integrating FPAA devices into educational
analog IC design in scaled processes. Efforts and resources environments, whether in the classroom or in the research
enabling scaled CMOS FPAA implementations will have laboratory, following along the inspiration from the rise
many significant future applications. of DSPs and FPGA devices. Educational directions enable
Finally, one can envision a large community utilizing a community who can utilize analog signal processing
these FPAA devices, contributing to a number of commer- and computing effectively toward commercial opportuni-
cial and open-source communities, empowered through ties. Even IC design tools should be optimized to rapidly
common tool frameworks. These directions require the generate FPAA fabric and related infrastructure, as well
developing an FPAA user and developer community work- as optimization tools to take an existing FPAA design to
ing around common tools, particularly tools that enable optimize hardware solutions when necessary. Improved
system compilation including handling analog-to-digital tools decrease cost and open opportunities throughout the
codesign through device programming and system commercial process.

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Hasler: Large-Scale Field-Programmable Analog Arrays

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20 P ROCEEDINGS OF THE IEEE

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