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Lab Practice 6

The document discusses a lab practice on designing simple logic gates and functions using VHDL and FPGA. The objectives are to use CAD tools to design simple logic functions in VHDL and implement them on an FPGA development board. The practice involves designing simple gates, a majority function, and a 4-input logic function in VHDL, simulating them, and synthesizing them on an FPGA.

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Angel Hernández
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9 views

Lab Practice 6

The document discusses a lab practice on designing simple logic gates and functions using VHDL and FPGA. The objectives are to use CAD tools to design simple logic functions in VHDL and implement them on an FPGA development board. The practice involves designing simple gates, a majority function, and a 4-input logic function in VHDL, simulating them, and synthesizing them on an FPGA.

Uploaded by

Angel Hernández
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSIDAD AUTÓNOMA DE QUERÉTARO

Facultad de Ingeniería
Campus San Juan del Río

279 – CIRCUITOS LÓGICOS – LOGIC CIRCUITS


Lab Practice 6 – Simple gates and logic functions under
VHDL and FPGA

René de Jesús Romero Troncoso


IEEE Senior Member
Investigador Nacional nivel III por el S.N.I.
Académico Titular de la Academia de Ingeniería de México
Profesor Titular de la Facultad de Ingeniería de la UAQ
Logic Circuits Weekly schedule

Introduction
This Lab practice makes use of CAD-CAE tools for the design of logic gates and logic functions
under VHDL and FPGA.

Objectives
Use CAD-CAD tools for the design of simple logic functions under VHDL and their implementation
on FPGA development tools.

Equipment and materials


Quantity Part number Description and notes
1 PC
1 Aldec Active-HDL student edition HDL software for design and simulation
1 Intel-Altera Quartus II free edition HDL software for FPGA synthesis
1 Altera FPGA development board and FPGA platform to implement HDL designs
USB blaster

Development
1. Simple gates under VHDL and FPGA

Complete the design process to describe the circuit from figure 6.1 under VHDL including
simulation and FPGA synthesis. Report your results.

Figure 6.1. Simple gates.

2. Majority function under VHDL and FPGA

Complete the design process including VHDL description, simulation and FPGA synthesis of a 3-
input majority function. Report your results.

René de Jesús Romero Troncoso


Logic Circuits Weekly schedule

3. 4-input logic function under VHDL and FPGA

Repeat problem 2 for the logic function stated in equation 6.1.

∑ ( ) (6.1)

Questions
1. Check the output report from the synthesis in Quartus-II and find how many logic blocks
were used for the synthesis experiments in the practice.
2. Check the timing report from synthesis in Quartus-II to estimate the maximum output
delay from input to output for the synthesis experiments in the practice.

Resources
Aldec’s Active-HDL student edition www.aldec.com

Intel-Altera Quartus II free edition www.intel.com

The FPGA development board documentation can be found at the vendor web site. Terasic
development boards at www.terasic.com

René de Jesús Romero Troncoso

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