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Lab Practice 7

This document provides instructions for a lab practice on designing basic combinational logic circuits using VHDL and FPGA. Students are tasked with designing a 4-1 multiplexer, BCD to 7-segment decoder, parity generator and checker, comparator, full adder, and signed and unsigned multipliers. They are to complete the design process including VHDL description, simulation, and FPGA synthesis for each circuit.

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Angel Hernández
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7 views

Lab Practice 7

This document provides instructions for a lab practice on designing basic combinational logic circuits using VHDL and FPGA. Students are tasked with designing a 4-1 multiplexer, BCD to 7-segment decoder, parity generator and checker, comparator, full adder, and signed and unsigned multipliers. They are to complete the design process including VHDL description, simulation, and FPGA synthesis for each circuit.

Uploaded by

Angel Hernández
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSIDAD AUTÓNOMA DE QUERÉTARO

Facultad de Ingeniería
Campus San Juan del Río

279 – CIRCUITOS LÓGICOS – LOGIC CIRCUITS


Lab Practice 7 – Basic combinational building blocks under
VHDL and FPGA

René de Jesús Romero Troncoso


IEEE Senior Member
Investigador Nacional nivel III por el S.N.I.
Académico Titular de la Academia de Ingeniería de México
Profesor Titular de la Facultad de Ingeniería de la UAQ
Logic Circuits Lab practice

Introduction
This Lab practice makes use of CAD-CAE tools for the design of basic combinational building blocks
under VHDL and FPGA.

Objectives
Use CAD-CAD tools for the design of combinational building blocks under VHDL and their
implementation on FPGA development tools.

Equipment and materials


Quantity Part number Description and notes
1 PC
1 Aldec Active-HDL student edition HDL software for design and simulation
1 Intel-Altera Quartus II free edition HDL software for FPGA synthesis
1 Altera FPGA development board and FPGA platform to implement HDL designs
USB blaster

Development
1. 4-1 multiplexer

Complete the design process to describe a 4-1 multiplexer under VHDL including simulation and
FPGA synthesis. Report your results.

2. BCD to 7-segment decoder

Complete the design process including VHDL description, simulation and FPGA synthesis of a BCD
to 7-segment decoder. Design the decoder to show blank when an invalid input is placed. Check
the polarity of the 7-segment display on your FPGA development board to design the decoder
accordingly. Report your results.

3. Parity generator and parity checker

Make the VHDL description, simulation and FPGA synthesis for a 4-bit parity generator and a 4-bit
parity checker. Report your results.

4. Comparator

Repeat exercise 3 for a 2-bit comparator.

5. Full adder

Repeat exercise 3 for a 2-bit full adder with output flags.

René de Jesús Romero Troncoso


Logic Circuits Lab practice

6. Multiplier

Repeat exercise 3 for a signed 2-bit multiplier and then for an unsigned 2-bit multiplier.

Questions
1. Check the output report from the synthesis in Quartus-II and find the FPGA resources that
were used for the synthesis experiments in the practice.
2. Check the timing report from synthesis in Quartus-II to estimate the maximum output
delay from input to output for the synthesis experiments in the practice.

Resources
Aldec’s Active-HDL student edition www.aldec.com

Intel-Altera Quartus II free edition www.intel.com

The FPGA development board documentation can be found at the vendor web site. Terasic
development boards at www.terasic.com

René de Jesús Romero Troncoso

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