Roll No EE NATIONAL INSTITUTE OF TECHNOLOGY GOA Farmagudi, Ponda, Goa, 403401 Mech Programme Name: M.Tech-VLSI = End Semester Examinations, June-2022 Visi J vend Course Name: Mixed Si 1: Mixed Signal Design Course code: ECBO. 2 co se code: 24 Seen te: 8/6/2022 Gmessormezsoem > 2 a hour ao AN: = 5 values can be suitably assumed wi Plot the transfer curve for the following Quantizati lowing Quantization error graph shown in Fig. 1. Also calculate DNL and INL error at each of the transition points, Assume Vaes=I V. (8) vw Veer > ow Fig, 1. For the modulator shown in Fig. 2, calculate the Noise Transfer Function (NTF) and Signal ‘Transfer Function, Plot the NTF Vs Normalized Frequency for the derived NTF. (19) Fig.2. Capacitor spread in a binary weighted SAR DAC can be minimized by split array structure (Series capacitor). Design a 9 bit SAR ADC using 3 spit capacitor (4bit+3bit+2bit). Caleulate the node voltages (during decision of each bit) at split arrays as well as input of the comparator for the input (1) 0.2V (2) 0.7V (3) 0.923V with reference voltage | V. What is equivalent Digital outpit for above inputs? Derive an expression matching requirement of the eapacitors so thatthe INL and DNL should be less than 0.5 LSB. (20) 1e around Vref/4 or less for 90% time, modify the binary search Suppose input voltage will b B to MSB. (10) algorithm of a 5-bit SAR ADC which generates the digital code from LSnil inp rent gia the SUE. el in the dif 4. White designing a comparator, due to mismatch in Me te offset voltage of SmV] appears atthe output. Desi Non overlapping clock, capacitors 5. Design a9 bit ADC using 3 step A intermediate stages. What is output of D ali Vref=1V. Calculate the open loop gain of ‘the amplifier, inof.F always requires again of. Multistage ADCS ie Ppstine ADC aways eas Oy 5 1 is the Gain required in the stem evel, WIG, V, OAV, 0.7V. Given I stages (or ould be less than % LSB. pe (34343) in 8 {oF DAC for each stages ae Bean swing eteuit shown in Fi om ve sampling and 7 jgehes t0 ache 6 be used rhe ein of 2. Draw ihe amplieton of Sq S3 q Ss ct Yn x Vout S2 cz . of 100 Mz with a resolutions 3, ‘ADC output at 500 MHz with Ft yhown in Fig 4 operates at fS 7. Following System level ADC architectures oes at bits, power dissipation P= mW. However the targeted application requires Mee F bik cccchation Design a system level architecture to meet the desired specification, where ps a dissipation of 6 mW and required area are available. 1 Fig. 4. 1¢ comparator with provision for suppression of kick back noise as well as Fig 5. Propose a circuit which will 8. Design a continuous ti insensitivity to noise signal forthe following input conditions show work for any signal level for a supply voltage of 1.8 V. in 0.18U technology. Derive expression for (34344) hysteresis switching point, given 0.35,1.45, 0.9 are Vref voltage of the comparator. ‘ime (3) @ tine (6) ® Fig. 5,9. For logic circuit shown in Fig. 6, Draw the output waveform Voutl, Vout2, Vout3, Voutd for elk » Vout2, Vout3, Voutd for el input of | M Hz and Consider all inverter having an equal delay of 0.1 Micro See, NAND and NOR of 0.3 Micro Sec. [8] anf Veer ae epee pe x ae vo Fig.6 10, The following circuit shown in Fig. 7 represents switched eapacitor implementation of 8 large ae tor, Honever Clock phases are missing in the diagram. Place the clk phases appropriately caerat cguivatent resistance (between V and gnd) Req =10VCfs, where clocks are 0s, ‘overlapping. Derive the expression for same. [443] im cL CLK-A J CLK-B