SARDAR RAJA COLLEGE OF ENGINEERING

ALANGULAM
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

MICRO LESSON PLAN

SUBJECT NAME : DIGITAL PRINCIPLES AND SYSTEM DESIGN

SUBJECT CODE : CS 2202

SEMESTER : III

YEAR : II

STAFF NAME

KALIMUTHU V

AP/ECE DEPT
E-MAILID:[email protected]
 SUBJECT DESCRIPTION

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN LTPC

(Common to CSE & IT) 3104

AIM:

To provide an in-depth knowledge of the design of digital circuits and the use of
Hardware Description Language in digital system design.

OBJECTIVES:

 To understand different methods used for the simplification of Boolean functions

 To design and implement combinational circuits
 To design and implement synchronous sequential circuits
 To design and implement asynchronous sequential circuits
 To study the fundamentals of VHDL / Verilog HDL

TEXT BOOKS

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2007.

REFERENCES

1. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico Publishing

House, Cengage Earning, 5th ed, 2005.

2. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2007.

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN LTPC

(Common to CSE & IT) 3104

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES 8

Review of binary number systems - Binary arithmetic – Binary codes – Boolean algebra

and theorems - Boolean functions – Simplifications of Boolean functions using Karnaugh

map and tabulation methods – Implementation of Boolean functions using logic gates.

UNIT II COMBINATIONAL LOGIC 9

Combinational circuits – Analysis and design procedures - Circuits for arithmetic

operations - Code conversion – Introduction to Hardware Description Language (HDL)

UNIT III DESIGN WITH MSI DEVICES 8

Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable

logic - HDL for combinational circuits

UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC 10

Sequential circuits – Flip flops – Analysis and design procedures - State reduction and

state assignment - Shift registers – Counters – HDL for Sequential Circuits.

UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC 10

Analysis and design of asynchronous sequential circuits - Reduction of state and flow

tables – Race-free state assignment – Hazards. ASM Chart.

TUTORIAL= 15 TOTAL : 60 PERIODS

TEXT BOOKS

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2007.

REFERENCES

1. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico Publishing

House, Cengage Earning, 5th ed, 2005.

2. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2007.

 A/ V
WEEK T/ R
HOURS PAGE NO CLASS
NO TOPICS BOOK
NO

UNIT I BOOLEAN ALGEBRA AND LOGIC GATES

01 Review of binary number systems T1 1-8

02 Binary arithmetic T1 8-15
I
03 Binary codes T1 15-31
Boolean algebra
04 T1 31-34
and theorems
05 Boolean functions T1 40-60
Simplifications of Boolean functions
06 II using Karnaugh map and tabulation T1 63-80
methods
07 Implementation of Boolean functions
T1 80-112 yes
08 using logic gates
III
09 Tutorial

UNIT II COMBINATIONAL LOGIC

10
Combinational circuits T1 121-122 yes
11
IV
12
Combinational circuits Analysis T1 122-124
13
14 design procedures T1 124-127
15 Circuits for arithmetic
V T1
16 operations 128-142
17
Code conversion T1 142-154 Yes
18
Introduction to Hardware Description
19 T1 112-117
VI Language (HDL)
20
Tutorial
21

UNIT III DESIGN WITH MSI DEVICES

22
Decoders T1 142-146
23
VII
24
encoders T1 146-148
25
26
Multiplexers and demultiplexers T1 148-154 yes
27
28 Memory and programmable
T1 268-297
30 VIII logic
31

32 HDL for combinational circuits T1 154-167

IX
33
34
IX Tutorial
35

UNIT IV SYNCHRONOUS SEQUENTIAL LOGIC

36
Sequential circuits T1 172-177 yes
37
X
38
Flip flops T1 177-184
39
40
Analysis and design procedures T1 184-201
41
42
43 XI State reduction and
T1 201-213
44 state assignment
45
46
XII
47 Shift registers T1 223-247
48
49
Counters T1 248-263
50 XIII
51
258-
52
HDL for Sequential Circuits. T1 263,333-
53
344
54
XIV
55
Tutorial T1
56

UNIT V ASYNCHRONOUS SEQUENTIAL LOGIC

Analysis and design of asynchronous

57 T1 351-371 yes
sequential circuits
58 XV Reduction of state and flow
59 tables T1 371-377
60
61 Race-free state assignment T1 377-382
62
63 Hazards T1 382-387
64 XVI
65 ASM Chart R1 565-387
66
67 Tutorial

Note:

T1- M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2007.

R1- Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico Publishing

House, Cengage Earning, 5th ed, 2005.

 QUESTION BANK

UNIT I

BOOLEAN ALGEBRA AND LOGIC GATES

PART A (2 Marks)

1.Define the term digital.

2.What is meant by bit?

3.What is the best example of digital system?

4.Define byte?

5.List the number systems?

6.State the sequence of operator precedence in Boolean expression?

7.What is the abbreviation of ASCII and EBCDIC code?

8.What are the universal gates?

9.What are the different types of number complements?

10.Why complementing a number representation is needed?

11.How to represent a positive and negative sign in computers?

12.What is meant by Map method?

13.What is meant by two variable map?

14.What is meant by three variable map?

15.Which gate is equal to AND-inverter Gate?

16.Which gate is equal to OR-inverter Gate?

17.Bubbled OR gate is equal to--------------

18. Bubbled AND gate is equal to--------------

19.What is the use of Don’t care conditions?

20.Express the function f(x, y, z)=1 in the sum of minterms and a product of maxterms?

21.What is the algebraic function of Exclusive-OR gate and Exclusive-NOR gate?

22.What are the methods adopted to reduce Boolean function?

23.Why we go in for tabulation method?

24.State the limitations of karnaugh map.

25.What is tabulation method?

26.What are prime-implicants?

27.Explain or list out the advantages and disadvantages of K-map method?

28.List out the advantages and disadvantages of Quine-Mc Cluskey method?

29. Convert the (153.513)10 to Octal.

30. Simplify the following Boolean functions to a minimum number of literals

(a) (x y)(x y)

(b) xy xz yz .

31. Draw the logic diagram for the Boolean expression ((A B) C)D using

NAND gates.

32. Perform subtraction using 1’s complement (11010)2 – (10000)2.

PART B (16 Marks)

1. (a) Explain how you will construct an (n+1) bit Gray code from an n bit

Gray code (8)

(b) Show that the Excess – 3 code is self –complementing (8)

2. (a) Prove that (x1+x2).(x1’. x3’+x3) (x2’ + x1.x3) =x1’x2 (8)

(b) Simplify using K-map to obtain a minimum POS expression: (8)

(A’ + B’+C+D) (A+B’+C+D) (A+B+C+D’) (A+B+C’+D’) (A’+B+C’+D’)

(A+B+C’+D) (8)

3. Reduce the following equation using Quine McClucky method of

minimization F (A,B,C,D) = _m(0,1,3,4,5,7,10,13,14,15) (16)

4. (a) State and Prove idempotent laws of Boolean algebra. (8)

(b) using a K-Map ,Find the MSP from of F= _(0,4,8,12,3,7,11,15) +_d(5) (8)

5 (a) With the help of a suitable example ,explain the meaning of an redundant prime i
Implicant (8)

(b) Using a K-Map, Find the MSP form of F= _ (0-3, 12-15) + _d (7, 11) (8)

6 (a) Simplify the following using the Quine – McClusky minimization technique(8)

D = f(a,b,c,d) = _ (0,1,2,3,6,7,8,9,14,15).Does Quine –McClusky take care of don’t

care conditions? In the above problem, will you consider any don’t care conditions?

Justify your answer

(b) List also the prime implicants and essential prime implicants for the above case(8)

7 (a) Determine the MSP and MPS focus of F= _ (0, 2, 6, 8, 10, 12, 14, 15) (8)

(b) State and Prove Demorgan’s theorem(8)

8 Determine the MSP form of the Switching function

F = _ ( 0,1,4,5,6,11,14,15,16,17,20- 22,30,32,33,36,37,48,49,52,53,56,63) (8)

9. (a) Determine the MSP form of the Switching function(8)

F( a,b,c,d) =_(0,2,4,6,8) + _d(10,11,12,13,14,15)

(b) Find the Minterm expansion of f(a,b,c,d) = a’(b’+d) + acd’(8)

10 Simplify the following Boolean function by using the Tabulation Method

F= _ (0, 1, 2, 8, 10, 11, 14, 15)

11 State and Prove the postulates of Boolean algebra

12 (a) Find a Min SOP and Min POS for f = b’c’d + bcd + acd’ + a’b’c + a’bc’d

13 Find an expression for the following function usingQuine McCluscky method

F= _ (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30)

14 State and Prove the theorems of Boolean algebra with illustration

15 Find the MSP representation for

F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method

Draw the circuit of the minimal expression using only NAND gates

16 (a) Show that if all the gates in a two – level AND-OR gate networks are replaced by

NAND gates the output function does not change

(b) Why does a good logic designer minimize the use of NOT gates?
17 Simplify the Boolean function F(A,B,C,D) = _ m (1,3,7,11,15) + _d (0,2,5) .if don’t

care conditions are not taken care, What is the simplified Boolean function .What are

your comments on it? Implement both circuits

18 (a) Show that if all the gate in a two – level OR-AND gate network are replaced by
NOR gate, the output function does not change.

(b) Implement Y = (A+C) (A+D’) ( A+B+C’) using NOR gates only

19 (a) F3 = f(a,b,c,d) = _ (2,4,5,6)

F2 = f(a,b,c,d) = _ (2,3,,6,7)

F1 = f(a,b,c,d) = _ (2,5,6,7) .Implement the above Boolean functions

(i) When each is treated separately and

(ii)When sharing common term

(b) Convert a NOR with an equivalent AND gate

20 Implement the Switching function whose octal designation is 274 using NAND gates
only

21 Implement the Switching function whose octal designation is 274 using NOR gates
only

22 (a) Show that the NAND operation is not distributive over the AND operation

(b) Find a network of AND and OR gate to realize f(a,b,c,d) = _ m (1,5,6,10,13,14)

23 What is the advantages of using tabulation method? Determine the prime implicants
of the following function using tabulation method

F( W,X,Y,Z) = _(1,4,6,7,8,9,10,11,15)

23 (a) Explain about common postulates used to formulates various algebraic structures

(b) Given the following Boolean function F= A”C + A’B + AB’C + BC

Express it in sum of minterms & Find the minimal SOP expression

24 (a) (i) Simplify the following Boolean function F together with don’t-care

condition d, and then express the simplified function in sum of

minterms

F (w, x, y, z) = Σ(1,3,7,11,15) + Σd (0,2,5)

(ii) Implement the following Boolean function with NAND gates.

F (x, y, z) = (1,2,3,4,5,7)

25.Determine the prime-implicants of the Boolean function by using the

tabulation method.

F(w, x, y, z)=Σ(1,4,6,7,8,9,10,11,15)

26.Simplify the following Boolean expression using Quine McCluskey

method :

F = Σm (0, 9,15, 24, 29, 30) + d (8,11, 31) .

27.(i) Implement Boolean expression for EXOR gate using NAND and

NOR gates.

(ii) Prove that (AB + C + D)(C′ + D)(C′ + D + E) = ABC + D .

(iii) Using 2’s complement perform (42)10 – (68)10.

UNIT II
COMBINATIONAL LOGIC
PART A (2 Marks)

Define Positive Logic.

2.Define Negative Logic.

3 .List the characteristics of digital Ics

4 .What is propagation delay?

5.What is Noise margin?

6.What is power dissipation?

7.Why parity checker is needed?

8.What is meant by parity bit?

9.Why parity generator necessary?

10.What is IC?

11What are the needs for binary codes?

12.Mention the different type of binary codes?

13.List the advantages and disadvantages of BCD code?

14.What is meant by self-complementing code?

15.Mention the advantages of ASCII code?

16.What are the disadvantages of ASCII code?

17.What is the truth table?

18.Define figure of merit?

19.What are the two types of logic circuits for digital systems?

20.Define Combinational circuit.

21.Define sequential circuits.

22.What is a half-adder?

23.What is a full-adder?

24.What is half-subtractor?

25.What is a full-subtractor?

26.What is Binary parallel adder?

27. Distinguish between the combinational and sequential logic circuits.

28. What do you mean by HDL?

29. Perform 9’s and 10’s compliment subtraction between 18 and –24.

30. Draw the logic diagram for half adder.

PART B ( 16 Marks)

1. Design a 4 bit magnitude comparator to compare two 4 bit number

2. Construct a combinational circuit to convert given binary coded decimal number into
an Excess 3 code for example when the input to the gate is 0110 then the circuit
shouldgenerate output as 1001

3. Design a combinational logic circuit whose outputs are F1 = a’bc + ab’c and

F2 = a’ + b’c + bc’

4 (a) Draw the logic diagram of a *-bit 7483 adder

(b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor

5 (a) Draw a diode ROM, which translates from BCD 8421 to Excess 3 code

(b) Distinguish between Boolean addition and Binary addition

6. Realize a BCD to Excess 3 code conversion circuit starting from its truth table

7. (a) Design a full sub tractor

(b) How to it differ from a full sub tractor

8. Design a combinational circuit which accepts 3 bit binary number and converts its

Equivalent excess 3 codes

9 .Derive the simplest possible expression for driving segment “a” through ‘g’ in an 8421

BCD to seven segment decoder for decimal digits 0 through 9 .Output should be

active high (Decimal 6 should be displayed as 6 and decimal 9 as 9)

10. Write the HDL description of the circuit specified by the following Boolean function

(i) Y= (A+B+C) (A’+B’+C’)

(ii) F= (AB’ + A’B) (CD’+C’D)

(iii) Z = ABC + AB’ + A(D+B)

(iv) T= [(A+B} {B’+C’+D’)]

11 .Design 16 bit adder using 4 7483 ICs

12. (a) (i) Explain the gray code to binary converter with the necessary

diagram.

(ii) Design a half subtractor circuit.

23. With neat diagram explain BCD subtractor using 9’s and 10’s

complement method.

24. (a) Design a combinational logic diagram for BCD to Excess-3 code

converter.

25.(b) (i) Design a Full Adder circuit with necessary diagram.

(ii) Write the HDL description of the circuit specified by the following

Boolean function.

y C x AB C 
 UNIT III

DESIGN WITH MSI DEVICES

PART A (2 Marks)

1.What is BCD adder?

2.What is Magnitude Comparator?

3.What is decoder?

4.What is encoder?

5.Define Multiplexing?

6.What is Demultiplexer?

7.Give the truth table for a half adder.

8.Give the truth table for a half Subtractor.

9.From the truth table of a half adder derive the logic equation

10. From the truth table of a half subractor derive the logic equation

11.From the truth table of a full adder derive the logic equation

12.What is code conversion?

13.What is code converter?

14.What do you mean by analyzing a combinational circuit?

15.Give the applications of Demultiplexer.

16.Mention the uses of Demultiplexer.

17.Give other name for Multiplexer and Demultiplexer.

18.What is the function of the enable input in a Multiplexer?

19.Give the truth table for a full Subtractor.

20.Give the truth table for a full adder.

21.From the truth table of a full subtractor derive the logic equation

22.What is priority encoder?

23.Can a decoder function as a Demultiplexer?

24.List out the applications of multiplexer?

25.List out the applications of decoder?

26.List out the applications of comparators?

27.What are the applications of seven segment displays?

28.What is digital comparator?

29. List the types of ROM.

30.Differentiate ROM & PLD’s

31.What are the different types of RAM?

32.What are the types of arrays in RAM?

33.Explain DRAM?

34.Explain SRAM?

35.Differentiate volatile and non-volatile memory?

36.What are the terms that determine the size of a PAL?

37.What are the advantages of RAM?

38.What is VHDL?

39.What are the features of VHDL?

40 What is meant by memory decoding?

41.What is access and cycle time?

42. What is the difference between decoder and demultiplexer?

43. What is programmable logic array? How does it differ from ROM?

44. What is Multiplexer?

45. Define Encoder.

PART B(16 Marks)

1. Implement the switching function F= _(0,1,3,4,7) using a 4 input MUX and explain

2. Explain how will build a 64 input MUX using nine 8 input MUXs
3. State the advantages of complex MSI devices over SSI gates

4. Implement the switching function F(A,B,C) = _ ( ,2,4,5) using the DEMUX 74156

5. Implement the switching function F= _(0,1,3,4,12,14,15) using an 8 input MUX

6. Explain how will build a 16 input MUX using only 4 input MUXs

7. Explain the operation of 4 to 10 line decoder with necessary logic diagram

8. Draw a neat sketch showing implementation of Z1 = ab’d’e + a’b’c’e’ + bc + de ,

Z2 = a’c’e, Z3 = bc +de+c’d’e’+bd and Z4 = a’c’e +ce using a 5*8*4 PLA

9. Implement the switching functions:

Z1 = ab’d’e + a’b’c’e’ + bc + de ,

Z2 = a’c’e,

Z3 = bc +de+c’d’e’+bd and

Z4 = a’c’e +ce Using a 5*8*4 PLA

10. Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code
using ROM array

11.Design a combinational circuit using a ROM ,that accepts a 3- bit number and

generates an output binary number equal to the square of the given input number

12. (a) Explain with necessary diagram a BCD to 7 segment display decoder.

13. (i) Write the comparison between PROM, PLA, PAL.

(ii) Design a BCD to excess-3 code converter and implement using

PLA.

14. (i) Design a 3 to 8-line decoder with necessary diagram.

(ii) Implement the given Boolean function using 4 1 multiplexer.

F(x, y, z) 1, 2, 6, 7

15. We have found a minimum sum of products expression for each of two

function, F and G, minimizing them individually (no sharing)

F WYXYZ

G WXY XY WYZ .

(i) Implement them with a ROM. (8)

(ii) Implement them in the PLA using no more than four terms. (8)

UNIT IV

SYNCHRONOUS SEQUENTIAL LOGIC

PART A (2 Marks)

1.What is sequential circuit?

2.List the classifications of sequential circuit.

3.what is Synchronous sequential circuit?

4.What is clocked sequential circuits?

5.What is called latch?

6.List different types of flip-flops.

7.What do you mean by triggering of flip-flop.

8.What is an excitation table?

9.Give the excitation table of a JK flip-flop

10.Give the excitation table of a SR flip-flop

11.Give the excitation table of a T flip-flop

12.Give the excitation table of a D flip-flop

13.What is a characteristic table?

14.Give the characteristic equation of a SR flip-flop.

15.Give the characteristic equation of a D flip-flop.

16.Give the characteristic equation of a JK flip-flop.

17.Give the characteristic equation of a T flip-flop.

18.What is the difference between truth table and excitation table.

19.What is counter?

20.What is synchronous counter?

21.What is Asynchronous counter?

22 What is the difference between synchronous and asynchronous counter?

23.Name the different types of counter.

24 What is up counter?

25.What is down counter?

26.What is up/down counter?

27.What is a ripple counter?

28.What are the uses of a counter?

29.What is meant by modulus of a counter?

30.what is meant by natural count of a counter?

31.A ripple counter is a ------------ sequential counter.

32.What is a modulo counter?

33.A counter that counts from to T is called a modulo counter. True or False.

34.The number of flip-flops required for modulo-18 counter is -------

35.Form the truth table for 3-bit binary down counter.

36.What is a ring counter?

37.What is BCD counter?

38. What are the uses of a ring counter?

39.What is a register?

40.What is Johnson counter?

41. What is a shift register?

42. What is serial shifting?

43. What is parallel shifting?

44. Write the uses of a shift register.

45. What is a cycle counter?

46. Define state of sequential circuit?

47. Define state diagram.

48. What is the use of state diagram?

49. What is state table?

50. What is a state equation?

51.What is meant by race around condition?

52. Differentiate Flip-Flop from Latches.

53. Draw the excitation table and state diagram for JK and SR Flip-Flop.

54. Write down the difference between sequential and combinational circuits.

55. What is race around condition?

PART B(16 Marks)

1. Draw the state diagram and characteristics equation of T FF, D FF and JK FF

2 (a) What is race around condition? How is it avoided?

(b) Draw the schematic diagram of Master slave JK FF and input and output

waveforms.Discuss how it prevents race around condition

3. Explain the operation of JK and clocked JK flip-flops with suitable diagrams

4. Draw the state diagram of a JK flip- flop and D flip – flop

5. Design and explain the working of a synchronous mod – 3 counter

6. Design and explain the working of a synchronous mod – 7 counter

7. Design a synchronous counter with states 0,1, 2,3,0,1 …………. Using JK FF

8. Using SR flip flops, design a parallel counter which counts in the sequence

000,111,101,110,001,010,000 ………….

9. Using JK flip flops, design a parallel counter which counts in the sequence

000,111,101,110,001,010,000 ………….

10. (a) Discuss a decade counter and its working principle

(b) Draw as asynchronous 4 bit up-down counter and explain its working

11. (a) How is the design of combinational and sequential logic circuits possible with
PLA?

(b) Mention the two models in a sequential circuit and distinguish between them
12. Design a modulo 5 synchronous counter using JK FF and implement it. Construct its

timing diagram

13. A sequential machine has one input line where 0’s and 1’s are being incident. The

machine has to produce a output of 1 only when exactly two 0’s are followed by a ‘1’

or exactly two 1’s are followed by a ‘0’.Using any state assignment and JK

flipflop,synthesize the machine

14. Using D flip –flop ,design a synchronous counter which counts in the sequence

000, 001, 010, 011, 100, 1001,110,111,000

15. Using JK flip-flops, design a synchronous sequential circuit having one and one

output. the output of the circuit is a 1 whenever three consecutive 1’s are

observed. Otherwise the output is zero

16. Design a binary counter using T flip – flops to count in the following sequences:

(i) 000,001,010,011,100,101,110,111,000

(ii) 000,100,111,010,011,000

17 (a) Design a synchronous binary counter using T flip – flops

(b) Derive the state table of a serial binary adder

18. Design a 3 bit binary Up-Down counter

19. (i) Summarize the design procedure for synchronous sequential circuit

(ii) Reduce the following state diagram

20.Design and implement a Mod-5 synchronous counter using JK flip-flop.

Draw the timing diagram also.

21.(i) Explain the working of master slave JK flip-flop.

(ii) Draw the diagram for a 3 bit ripple counter.

22.Design a synchronous sequential circuit using JK flip-flop to generate the

following sequence and repeat.

0, 1, 2, 4, 5, 6

23. What is the aim of state reduction? Reduce the given state diagram and
Prove that the both state diagrams are equal.

UNIT V

ASYNCHRONOUS SEQUENTIAL LOGIC

PART A (2 Marks)

1. What is flow table?

2. What is primitive flow table?

3. Define race condition.

4. Define critical & non-critical race with example.

5. How can a race be avoided?

6. Define cycle and merging?

7. Give state – reduction procedure.

8. Define hazards.

9. Does Hazard occur in sequential circuit? If so what is the problem caused?

10. Give the procedural steps for determining the compatibles used for the purpose of

merging a flow table.

11. What are the types of hazards?

12.What is mealy and Moore circuit?

13.Differentiate Moore circuit and Mealy circuit?

13. How can the hazards in combinational circuit be removed?

14How does an essential hazard occur?

15.what is Timing diagram?

16.What is setup and hold time?

17.Define bit time and word time.

18.What is bi-directional shift register and unidirectional shift register?

19.Define equivalent state.

20.a shift register can be operated in all possible ways then it is called as-----------
21 What is gate delay?

22.Define state reduction algorithm.

23.What is meant by level triggering?

24.Write the uses of a shift register.

25. What is meant by flow table?

26. What are the problems involved in asynchronous circuits?

27. Define cycles?

28. Define primitive flow table?

29. Define merging?

30. What is meant by lockout condition?

31. What are the steps for design of asynchronous sequential circuit?

32. What is Race Conditions?

34. What happens when a Hazard happens in a logic circuit?

PART B (16 Marks)

1. What is the objective of state assignment in asynchronous circuit? Give hazard – free

realization for the following Boolean function f(A,B,C,D) = _M(0,2,6,7,8,10,12)

2. Summarize the design procedure for asynchronous sequential circuit

a. Discuss on Hazards and races

b. What do you know on hardware descriptive languages?

3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output
Z Wherever Y is 1, input X is transferred to Z .When Y is 0; the output does not change
for any change in X.Use SR latch for implementation of the circuit

4. Develop the state diagram and primitive flow table for a logic system that has 2
inputs,x and y and an output z.And reduce primitive flow table. The behavior of the
circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x
= 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous
state. The logic system has edge triggered inputs with out having a clock .the logic
system changes state on the rising edges of the 2 inputs. Static input values are not to
have any effect in changing the Z output 5. Design an asynchronous sequential circuit
with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to
Z.When Y is 0,the output does not change for any change in X.
6. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and
one output Z. An output z =1 is to occur only during the input state xy = 01 and then if
the only if the input state xy =01 is preceded by the input sequence.

7. A pulse mode asynchronous machine has two inputs. It produces an output whenever
two consecutive pulses occur on one input line only .The output remains at ‘1’ until a
pulse has occurred on the other input line. Draw the state table for the machine.

8.(a) How will you minimize the number of rows in the primitive state table of an
incompletely specified sequential machine

(b) State the restrictions on the pulse width in a pulse mode asynchronous sequential

machine

9. Construct the state diagram and primitive flow table for an asynchronous network that
has two inputs and one output. The input sequence X1X2 = 00,01,11 causes the output
to become 1.The next input change then causes the output to return to 0.No other inputs
will produce a 1 output

10. (i) Design a comparator.

(ii) Design a non sequential ripple counter which will go through the

states 3, 4, 5, 7, 8, 9, 10, 3, 4 .................. draw bush diagram also.

11. (i) Design a parity checker.

(ii) Design a sequential circuit with JK flip-flop.

12.With suitable example and diagram explain the hazards in combinational

and sequential logic circuits.

13. With necessary example and diagram explain the concept of reduction of

state and flow tables.

 ASSIGNMENT TOPICS

ASSIGNMENT-1

1 (i). Express the Boolean function F =A+B’C in sum of minterms

(ii) Express the Boolean function F=xy+x’z in production of maxterms.

2.Simplify the Boolean function F(A,B,C,D)= _(0,6,8,13,14) Together with the don’t

care condition d=_(2,4,10)and then express the simplified function in sum of

minterms.

3.Implement the Boolean function F(X,Y,Z)=(1,2,3,4,5,7)with NAND gates

4. Simplify the Boolean function F(A,B,C,D) =_(0,2,3,5,7,8,9,10,11,13,15)and find the

prime implicants and essential prime implicants

ASSIGNMENT-II

1.Draw the circuit for 3-to-8-decoder and implement the functions

F1(A,B,C)=II(0,1,3,7)

F2(A,B,C)=II(2,3,7) using 3-to-8-decoder

2.Draw the circuits for Decimal to BCD encoder, Octal-to-Binary encoder & Priority

encoder

ASSIGNMENT-III

1.Draw the PLA programming table with minterms

AB,AC,BC&A'B'C'

ASSIGNMENT-IV

1.Discuss in detail shift registers

 Block diagram of 4-bit shift register

 Serial transfer of information
  serial addition using shift register
 Universal shift register

ASSIGNMENT-V

1.write short notes on race-free state assignment

 Three row flowtable example

 Four row flowtable example
 shared row method
 Multiple row method