Chapter 8 Central Processor Unit (S08CPUV4)

8.5 HCS08 Instruction Set Summary

Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Operators
() = Contents of register or memory location shown inside parentheses
← = Is loaded with (read: “gets”)
& = Boolean AND
| = Boolean OR
⊕ = Boolean exclusive-OR
× = Multiply
÷ = Divide
: = Concatenate
+ = Add
– = Negate (two’s complement)
CPU registers
A = Accumulator
CCR = Condition code register
H = Index register, higher order (most significant) 8 bits
X = Index register, lower order (least significant) 8 bits
PC = Program counter
PCH = Program counter, higher order (most significant) 8 bits
PCL = Program counter, lower order (least significant) 8 bits
SP = Stack pointer
Memory and addressing
M = A memory location or absolute data, depending on addressing mode
M:M + 0x0001= A 16-bit value in two consecutive memory locations. The higher-order (most
significant) 8 bits are located at the address of M, and the lower-order (least
significant) 8 bits are located at the next higher sequential address.
Condition code register (CCR) bits
V = Two’s complement overflow indicator, bit 7
H = Half carry, bit 4
I = Interrupt mask, bit 3
N = Negative indicator, bit 2
Z = Zero indicator, bit 1
C = Carry/borrow, bit 0 (carry out of bit 7)
CCR activity notation
– = Bit not affected

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0 = Bit forced to 0
1 = Bit forced to 1
↕ = Bit set or cleared according to results of operation
U = Undefined after the operation
Machine coding notation
dd = Low-order 8 bits of a direct address 0x0000–0x00FF (high byte assumed to be 0x00)
ee = Upper 8 bits of 16-bit offset
ff = Lower 8 bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
pg = Page
rr = Relative offset
Source form
Everything in the source forms columns, except expressions in italic characters, is literal information that
must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a
literal expression. All commas, pound signs (#), parentheses, and plus signs (+) are literal characters.
n — Any label or expression that evaluates to a single integer in the range 0–7
opr8i — Any label or expression that evaluates to an 8-bit immediate value
opr16i — Any label or expression that evaluates to a 16-bit immediate value
opr8a — Any label or expression that evaluates to an 8-bit value. The instruction treats this 8-bit
value as the low order 8 bits of an address in the direct page of the 64-Kbyte address
space (0x00xx).
opr16a — Any label or expression that evaluates to a 16-bit value. The instruction treats this
value as an address in the 64-Kbyte address space.
oprx8 — Any label or expression that evaluates to an unsigned 8-bit value, used for indexed
addressing
oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a
16-bit address bus, this can be either a signed or an unsigned value.
page — Any label or expression that evaluates to a valid bank number for the PPAGE register.
For a 128-Kbyte deravative, any value between 0 and 7 is valid.
rel — Any label or expression that refers to an address that is within –128 to +127 locations
from the next address after the last byte of object code for the current instruction. The
assembler will calculate the 8-bit signed offset and include it in the object code for this
instruction.
Address modes
INH = Inherent (no operands)

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IMM = 8-bit or 16-bit immediate

DIR = 8-bit direct
EXT = 16-bit extended
IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment
(CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer with 8-bit offset
SP2 = Stack pointer with 16-bit offset
Table 8-2. HCS08 Instruction Set Summary (Sheet 1 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

ADC #opr8i IMM A9 ii 2

ADC opr8a DIR B9 dd 3
ADC opr16a EXT C9 hh ll 4
ADC oprx16,X ↕ IX2 D9 ee ff 4
Add with Carry A ← (A) + (M) + (C) ↕ ↕ – ↕ ↕
ADC oprx8,X IX1 E9 ff 3
ADC ,X IX F9 3
ADC oprx16,SP SP2 9ED9 ee ff 5
ADC oprx8,SP SP1 9EE9 ff 4
ADD #opr8i IMM AB ii 2
ADD opr8a DIR BB dd 3
ADD opr16a EXT CB hh ll 4
ADD oprx16,X ↕ IX2 DB ee ff 4
Add without Carry A ← (A) + (M) ↕ ↕ – ↕ ↕
ADD oprx8,X IX1 EB ff 3
ADD ,X IX FB 3
ADD oprx16,SP SP2 9EDB ee ff 5
ADD oprx8,SP SP1 9EEB ff 4
Add Immediate Value SP ← (SP) + (M)
AIS #opr8i – – – – – – IMM A7 ii 2
(Signed) to Stack Pointer M is sign extended to a 16-bit value
Add Immediate Value H:X ← (H:X) + (M)
AIX #opr8i (Signed) to Index – – – – – – IMM AF ii 2
M is sign extended to a 16-bit value
Register (H:X)
AND #opr8i IMM A4 ii 2
AND opr8a DIR B4 dd 3
AND opr16a EXT C4 hh ll 4
AND oprx16,X IX2 D4 ee ff 4
Logical AND A ← (A) & (M) 0 – – ↕ ↕ –
AND oprx8,X IX1 E4 ff 3
AND ,X IX F4 3
AND oprx16,SP SP2 9ED4 ee ff 5
AND oprx8,SP SP1 9EE4 ff 4
ASL opr8a DIR 38 dd 5
ASLA INH 48 1
ASLX Arithmetic Shift Left INH 58 1
C 0 ↕ – – ↕ ↕ ↕
ASL oprx8,X (Same as LSL) IX1 68 ff 5
ASL ,X b7 b0 IX 78 4
ASL oprx8,SP SP1 9E68 ff 6
ASR opr8a DIR 37 dd 5
ASRA INH 47 1
ASRX C INH 57 1
Arithmetic Shift Right ↕ – – ↕ ↕ ↕
ASR oprx8,X b7 b0
IX1 67 ff 5
ASR ,X IX 77 4
ASR oprx8,SP SP1 9E67 ff 6
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 – – – – – – REL 24 rr 3

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Table 8-2. HCS08 Instruction Set Summary (Sheet 2 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

DIR (b0) 11 dd 5
DIR (b1) 13 dd 5
DIR (b2) 15 dd 5
BCLR n,opr8a Clear Bit n in Memory Mn ← 0 – – – – – – DIR (b3)
DIR (b4)
17
19
dd
dd
5
5
DIR (b5) 1B dd 5
DIR (b6) 1D dd 5
DIR (b7) 1F dd 5
Branch if Carry Bit Set
BCS rel (Same as BLO) Branch if (C) = 1 – – – – – – REL 25 rr 3

BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – REL 27 rr 3

Branch if Greater Than or
BGE rel Equal To Branch if (N ⊕ V) = 0 – – – – – – REL 90 rr 3
(Signed Operands)
Waits For and Processes BDM
Enter Active Background
BGND if ENBDM = 1 Commands Until GO, TRACE1, or – – – – – – INH 82 5+
TAGGO
Branch if Greater Than
BGT rel Branch if (Z) | (N ⊕ V) = 0 – – – – – – REL 92 rr 3
(Signed Operands)
Branch if Half Carry Bit
BHCC rel Clear Branch if (H) = 0 – – – – – – REL 28 rr 3

Branch if Half Carry Bit

BHCS rel Set Branch if (H) = 1 – – – – – – REL 29 rr 3

BHI rel Branch if Higher Branch if (C) | (Z) = 0 – – – – – – REL 22 rr 3

Branch if Higher or Same
BHS rel (Same as BCC) Branch if (C) = 0 – – – – – – REL 24 rr 3

BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 – – – – – – REL 2F rr 3
BIL rel Branch if IRQ Pin Low Branch if IRQ pin = 0 – – – – – – REL 2E rr 3
BIT #opr8i IMM A5 ii 2
BIT opr8a DIR B5 dd 3
BIT opr16a EXT C5 hh ll 4
(A) & (M)
BIT oprx16,X ↕ – IX2 D5 ee ff 4
BIT oprx8,X Bit Test (CCR Updated but Operands 0 – – ↕ IX1 E5 ff 3
Not Changed)
BIT ,X IX F5 3
BIT oprx16,SP SP2 9ED5 ee ff 5
BIT oprx8,SP SP1 9EE5 ff 4
Branch if Less Than
BLE rel or Equal To Branch if (Z) | (N ⊕ V) = 1 – – – – – – REL 93 rr 3
(Signed Operands)
Branch if Lower
BLO rel (Same as BCS) Branch if (C) = 1 – – – – – – REL 25 rr 3

BLS rel Branch if Lower or Same Branch if (C) | (Z) = 1 – – – – – – REL 23 rr 3

Branch if Less Than
BLT rel Branch if (N ⊕ V ) = 1 – – – – – – REL 91 rr 3
(Signed Operands)
Branch if Interrupt Mask
BMC rel Clear Branch if (I) = 0 – – – – – – REL 2C rr 3

BMI rel Branch if Minus Branch if (N) = 1 – – – – – – REL 2B rr 3

Branch if Interrupt Mask
BMS rel Set Branch if (I) = 1 – – – – – – REL 2D rr 3

BNE rel Branch if Not Equal Branch if (Z) = 0 – – – – – – REL 26 rr 3

BPL rel Branch if Plus Branch if (N) = 0 – – – – – – REL 2A rr 3
BRA rel Branch Always No Test – – – – – – REL 20 rr 3

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Table 8-2. HCS08 Instruction Set Summary (Sheet 3 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

DIR (b0) 01 dd rr 5
DIR (b1) 03 dd rr 5
DIR (b2) 05 dd rr 5
Branch if Bit n in Memory
BRCLR n,opr8a,rel Clear Branch if (Mn) = 0 – – – – – ↕ DIR (b3)
DIR (b4)
07
09
dd
dd
rr
rr
5
5
DIR (b5) 0B dd rr 5
DIR (b6) 0D dd rr 5
DIR (b7) 0F dd rr 5
BRN rel Branch Never Uses 3 Bus Cycles – – – – – – REL 21 rr 3
DIR (b0) 00 dd rr 5
DIR (b1) 02 dd rr 5
DIR (b2) 04 dd rr 5
Branch if Bit n in Memory
BRSET n,opr8a,rel Set Branch if (Mn) = 1 – – – – – ↕ DIR (b3)
DIR (b4)
06
08
dd
dd
rr
rr
5
5
DIR (b5) 0A dd rr 5
DIR (b6) 0C dd rr 5
DIR (b7) 0E dd rr 5
DIR (b0) 10 dd 5
DIR (b1) 12 dd 5
DIR (b2) 14 dd 5
BSET n,opr8a Set Bit n in Memory Mn ← 1 – – – – – – DIR (b3)
DIR (b4)
16
18
dd
dd
5
5
DIR (b5) 1A dd 5
DIR (b6) 1C dd 5
DIR (b7) 1E dd 5
PC ← (PC) + 0x0002
push (PCL); SP ← (SP) – 0x0001
BSR rel Branch to Subroutine push (PCH); SP ← (SP) – 0x0001 – – – – – – REL AD rr 5
PC ← (PC) + rel
PC ← PC + 4
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
Push (PPAGE); SP ← (SP) – 0x0001 – – – – – – EXT
CALL page, opr16a Call Subroutine AC pghll 8
PPAGE ← page
PC ← Unconditional Address
CBEQ opr8a,rel Branch if (A) = (M) DIR 31 dd rr 5
CBEQA #opr8i,rel Branch if (A) = (M) IMM 41 ii rr 4
CBEQX #opr8i,rel Compare and Branch if Branch if (X) = (M) IMM 51 ii rr 4
CBEQ oprx8,X+,rel Equal Branch if (A) = (M) – – – – – – IX1+ 61 ff rr 5
CBEQ ,X+,rel Branch if (A) = (M) IX+ 71 rr 5
CBEQ oprx8,SP,rel Branch if (A) = (M) SP1 9E61 ff rr 6
CLC Clear Carry Bit C←0 – – – – – 0 INH 98 1
CLI Clear Interrupt Mask Bit I←0 – – 0 – – – INH 9A 1
CLR opr8a M ← 0x00 DIR 3F dd 5
CLRA A ← 0x00 INH 4F 1
CLRX X ← 0x00 INH 5F 1
CLRH Clear H ← 0x00 0 – – 0 1 – INH 8C 1
CLR oprx8,X M ← 0x00 IX1 6F ff 5
CLR ,X M ← 0x00 IX 7F 4
CLR oprx8,SP M ← 0x00 SP1 9E6F ff 6
CMP #opr8i IMM A1 ii 2
CMP opr8a DIR B1 dd 3
CMP opr16a EXT C1 hh ll 4
(A) – (M)
CMP oprx16,X Compare Accumulator IX2 D1 ee ff 4
(CCR Updated But Operands Not ↕ – – ↕ ↕ ↕ IX1
CMP oprx8,X with Memory E1 ff 3
Changed)
CMP ,X IX F1 3
CMP oprx16,SP SP2 9ED1 ee ff 5
CMP oprx8,SP SP1 9EE1 ff 4

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Table 8-2. HCS08 Instruction Set Summary (Sheet 4 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

COM opr8a M ← (M)= 0xFF – (M) DIR 33 dd 5

COMA A ← (A) = 0xFF – (A) INH 43 1
COMX Complement X ← (X) = 0xFF – (X)
0 – – ↕ ↕ 1 INH 53 1
COM oprx8,X (One’s Complement) M ← (M) = 0xFF – (M) IX1 63 ff 5
COM ,X M ← (M) = 0xFF – (M) IX 73 4
COM oprx8,SP M ← (M) = 0xFF – (M) SP1 9E63 ff 6
CPHX opr16a EXT 3E hh ll 6
(H:X) – (M:M + 0x0001)
CPHX #opr16i Compare Index Register ↕ ↕ IMM 65 jj kk 3
(CCR Updated But Operands Not ↕ – – ↕
CPHX opr8a (H:X) with Memory DIR 75 dd 5
Changed)
CPHX oprx8,SP SP1 9EF3 ff 6
CPX #opr8i IMM A3 ii 2
CPX opr8a DIR B3 dd 3
CPX opr16a EXT C3 hh ll 4
Compare X (Index (X) – (M)
CPX oprx16,X ↕ ↕ IX2 D3 ee ff 4
Register Low) with (CCR Updated But Operands Not ↕ – – ↕
CPX oprx8,X IX1 E3 ff 3
Memory Changed)
CPX ,X IX F3 3
CPX oprx16,SP SP2 9ED3 ee ff 5
CPX oprx8,SP SP1 9EE3 ff 4
Decimal Adjust
DAA Accumulator After ADD or (A)10 U – – ↕ ↕ ↕ INH 72 1
ADC of BCD Values
DBNZ opr8a,rel DIR 3B dd rr 7
DBNZA rel INH 4B rr 4
Decrement A, X, or M
DBNZX rel Decrement and Branch if
DBNZ oprx8,X,rel Not Zero Branch if (result) ≠ 0 – – – – – – INH
IX1
5B
6B
rr
ff rr
4
7
DBNZX Affects X Not H
DBNZ ,X,rel IX 7B rr 6
DBNZ oprx8,SP,rel SP1 9E6B ff rr 8
DEC opr8a M ← (M) – 0x01 DIR 3A dd 5
DECA A ← (A) – 0x01 INH 4A 1
DECX X ← (X) – 0x01 ↕ – – ↕ ↕ – INH 5A 1
Decrement
DEC oprx8,X M ← (M) – 0x01 IX1 6A ff 5
DEC ,X M ← (M) – 0x01 IX 7A 4
DEC oprx8,SP M ← (M) – 0x01 SP1 9E6A ff 6
A ← (H:A)÷(X)
DIV Divide H ← Remainder – – – – ↕ ↕ INH 52 6

EOR #opr8i IMM A8 ii 2

EOR opr8a DIR B8 dd 3
EOR opr16a EXT C8 hh ll 4
Exclusive OR
EOR oprx16,X IX2 D8 ee ff 4
Memory with A ← (A ⊕ M) 0 – – ↕ ↕ –
EOR oprx8,X IX1 E8 ff 3
Accumulator
EOR ,X IX F8 3
EOR oprx16,SP SP2 9ED8 ee ff 5
EOR oprx8,SP SP1 9EE8 ff 4
INC opr8a M ← (M) + 0x01 DIR 3C dd 5
INCA A ← (A) + 0x01 INH 4C 1
INCX X ← (X) + 0x01 INH 5C 1
Increment ↕ – – ↕ ↕ –
INC oprx8,X M ← (M) + 0x01 IX1 6C ff 5
INC ,X M ← (M) + 0x01 IX 7C 4
INC oprx8,SP M ← (M) + 0x01 SP1 9E6C ff 6
JMP opr8a DIR BC dd 3
JMP opr16a EXT CC hh ll 4
JMP oprx16,X Jump PC ← Jump Address – – – – – – IX2 DC ee ff 4
JMP oprx8,X IX1 EC ff 3
JMP ,X IX FC 3
JSR opr8a DIR BD dd 5
PC ← (PC) + n (n = 1, 2, or 3)
JSR opr16a EXT CD hh ll 6
Push (PCL); SP ← (SP) – 0x0001
JSR oprx16,X Jump to Subroutine Push (PCH); SP ← (SP) – 0x0001 – – – – – – IX2 DD ee ff 6
JSR oprx8,X IX1 ED ff 5
PC ← Unconditional Address
JSR ,X IX FD 5

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Table 8-2. HCS08 Instruction Set Summary (Sheet 5 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

LDA #opr8i IMM A6 ii 2

LDA opr8a DIR B6 dd 3
LDA opr16a EXT C6 hh ll 4
LDA oprx16,X Load Accumulator from IX2 D6 ee ff 4
A ← (M) 0 – – ↕ ↕ – IX1
LDA oprx8,X Memory E6 ff 3
LDA ,X IX F6 3
LDA oprx16,SP SP2 9ED6 ee ff 5
LDA oprx8,SP SP1 9EE6 ff 4
LDHX #opr16i IMM 45 jj kk 3
LDHX opr8a DIR 55 dd 4
LDHX opr16a EXT 32 hh ll 5
Load Index Register (H:X)
LDHX ,X H:X ← (M:M + 0x0001) 0 – – ↕ ↕ – IX 9EAE 5
from Memory
LDHX oprx16,X IX2 9EBE ee ff 6
LDHX oprx8,X IX1 9ECE ff 5
LDHX oprx8,SP SP1 9EFE ff 5
LDX #opr8i IMM AE ii 2
LDX opr8a DIR BE dd 3
LDX opr16a EXT CE hh ll 4
LDX oprx16,X Load X (Index Register IX2 DE ee ff 4
X ← (M) 0 – – ↕ ↕ – IX1
LDX oprx8,X Low) from Memory EE ff 3
LDX ,X IX FE 3
LDX oprx16,SP SP2 9EDE ee ff 5
LDX oprx8,SP SP1 9EEE ff 4
LSL opr8a DIR 38 dd 5
LSLA INH 48 1
LSLX Logical Shift Left C 0 ↕ – – ↕ ↕ ↕ INH 58 1
LSL oprx8,X (Same as ASL) b7
IX1 68 ff 5
b0
LSL ,X IX 78 4
LSL oprx8,SP SP1 9E68 ff 6
LSR opr8a DIR 34 dd 5
LSRA INH 44 1
LSRX ↕ – – 0 ↕ ↕ INH
0 C 54 1
Logical Shift Right
LSR oprx8,X b7
IX1 64 ff 5
b0
LSR ,X IX 74 4
LSR oprx8,SP SP1 9E64 ff 6
MOV opr8a,opr8a (M)destination ← (M)source DIR/DIR 4E dd dd 5
MOV opr8a,X+
MOV #opr8i,opr8a Move H:X ← (H:X) + 0x0001 in 0 – – ↕ ↕ – DIR/IX+
IMM/DIR
5E
6E
dd
ii dd
5
4
MOV ,X+,opr8a IX+/DIR and DIR/IX+ Modes IX+/DIR 7E dd 5
MUL Unsigned multiply X:A ← (X) × (A) – 0 – – – 0 INH 42 5
NEG opr8a M ← – (M) = 0x00 – (M) DIR 30 dd 5
NEGA A ← – (A) = 0x00 – (A) INH 40 1
NEGX Negate X ← – (X) = 0x00 – (X) ↕ INH 50 1
NEG oprx8,X (Two’s Complement) M ← – (M) = 0x00 – (M) – – ↕ ↕ IX1 60 ff 5
NEG ,X M ← – (M) = 0x00 – (M) IX 70 4
NEG oprx8,SP M ← – (M) = 0x00 – (M) SP1 9E60 ff 6
NOP No Operation Uses 1 Bus Cycle – – – – – – INH 9D 1
Nibble Swap
NSA A ← (A[3:0]:A[7:4]) – – – – – – INH 62 1
Accumulator
ORA #opr8i IMM AA ii 2
ORA opr8a DIR BA dd 3
ORA opr16a EXT CA hh ll 4
ORA oprx16,X Inclusive OR Accumulator ↕ – IX2 DA ee ff 4
A ← (A) | (M) 0 – – ↕
ORA oprx8,X and Memory IX1 EA ff 3
ORA ,X IX FA 3
ORA oprx16,SP SP2 9EDA ee ff 5
ORA oprx8,SP SP1 9EEA ff 4
Push Accumulator onto
PSHA Push (A); SP ← (SP) – 0x0001 – – – – – – INH 87 2
Stack
Push H (Index Register
PSHH Push (H); SP ← (SP) – 0x0001 – – – – – – INH 8B 2
High) onto Stack
Push X (Index Register
PSHX Push (X); SP ← (SP) – 0x0001 – – – – – – INH 89 2
Low) onto Stack

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Table 8-2. HCS08 Instruction Set Summary (Sheet 6 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

Pull Accumulator from

PULA SP ← (SP + 0x0001); Pull (A) – – – – – – INH 86 3
Stack
Pull H (Index Register
PULH SP ← (SP + 0x0001); Pull (H) – – – – – – INH 8A 3
High) from Stack
Pull X (Index Register
PULX SP ← (SP + 0x0001); Pull (X) – – – – – – INH 88 3
Low) from Stack
ROL opr8a DIR 39 dd 5
ROLA INH 49 1
ROLX ↕ INH
C 59 1
Rotate Left through Carry ↕ – – ↕ ↕
ROL oprx8,X IX1 69 ff 5
ROL ,X b7 b0 IX 79 4
ROL oprx8,SP SP1 9E69 ff 6
ROR opr8a DIR 36 dd 5
RORA INH 46 1
RORX Rotate Right through
↕ INH
C ↕ – – ↕ 56 1
ROR oprx8,X Carry ↕ IX1 66 ff 5
ROR ,X b7 b0 IX 76 4
ROR oprx8,SP SP1 9E66 ff 6
SP ← 0xFF
RSP Reset Stack Pointer (High Byte Not Affected) – – – – – – INH 9C 1

SP ← (SP) + 0x0001; Pull (PPAGE)

RTC Return fom CALL SP ← (SP) + 0x0001; Pull (PCH) – – – – – – INH 8D 7
SP ← (SP) + 0x0001; Pull (PCL)
SP ← (SP) + 0x0001; Pull (CCR)
SP ← (SP) + 0x0001; Pull (A)
RTI Return from Interrupt SP ← (SP) + 0x0001; Pull (X) ↕ ↕ ↕ ↕ ↕ ↕ INH 80 9
SP ← (SP) + 0x0001; Pull (PCH)
SP ← (SP) + 0x0001; Pull (PCL)
SP ← SP + 0x0001; Pull (PCH)
RTS Return from Subroutine SP ← SP + 0x0001; Pull (PCL) – – – – – – INH 81 6

SBC #opr8i IMM A2 ii 2

SBC opr8a DIR B2 dd 3
SBC opr16a EXT C2 hh ll 4
SBC oprx16,X ↕ – – ↕ ↕ ↕ IX2 D2 ee ff 4
Subtract with Carry A ← (A) – (M) – (C)
SBC oprx8,X IX1 E2 ff 3
SBC ,X IX F2 3
SBC oprx16,SP SP2 9ED2 ee ff 5
SBC oprx8,SP SP1 9EE2 ff 4
SEC Set Carry Bit C←1 – – – – – 1 INH 99 1
SEI Set Interrupt Mask Bit I←1 – – 1 – – – INH 9B 1
STA opr8a DIR B7 dd 3
STA opr16a EXT C7 hh ll 4
STA oprx16,X IX2 D7 ee ff 4
Store Accumulator in
STA oprx8,X M ← (A) 0 – – ↕ ↕ – IX1 E7 ff 3
Memory
STA ,X IX F7 2
STA oprx16,SP SP2 9ED7 ee ff 5
STA oprx8,SP SP1 9EE7 ff 4
STHX opr8a DIR 35 dd 4
STHX opr16a Store H:X (Index Reg.) (M:M + 0x0001) ← (H:X) 0 – – ↕ ↕ – EXT 96 hh ll 5
STHX oprx8,SP SP1 9EFF ff 5
Enable Interrupts:
Stop Processing
STOP I bit ← 0; Stop Processing – – 0 – – – INH 8E 2+
Refer to MCU
Documentation
STX opr8a DIR BF dd 3
STX opr16a EXT CF hh ll 4
STX oprx16,X Store X (Low 8 Bits of IX2 DF ee ff 4
STX oprx8,X Index Register) M ← (X) 0 – – ↕ ↕ – IX1 EF ff 3
STX ,X in Memory IX FF 2
STX oprx16,SP SP2 9EDF ee ff 5
STX oprx8,SP SP1 9EEF ff 4

MC9S08QE128 MCU Series Reference Manual, Rev. 2

162 Freescale Semiconductor
 Chapter 8 Central Processor Unit (S08CPUV4)

Table 8-2. HCS08 Instruction Set Summary (Sheet 7 of 7)

Bus Cycles1
Effect

Operand
Address

Opcode
on CCR

Mode
Source
Operation Description
Form
V H I N Z C

SUB #opr8i IMM A0 ii 2

SUB opr8a DIR B0 dd 3
SUB opr16a EXT C0 hh ll 4
SUB oprx16,X ↕ IX2 D0 ee ff 4
Subtract A ← (A) – (M) ↕ – – ↕ ↕
SUB oprx8,X IX1 E0 ff 3
SUB ,X IX F0 3
SUB oprx16,SP SP2 9ED0 ee ff 5
SUB oprx8,SP SP1 9EE0 ff 4
PC ← (PC) + 0x0001
Push (PCL); SP ← (SP) – 0x0001
Push (PCH); SP ← (SP) – 0x0001
Push (X); SP ← (SP) – 0x0001
SWI Software Interrupt Push (A); SP ← (SP) – 0x0001 – – 1 – – – INH 83 11
Push (CCR); SP ← (SP) – 0x0001
I ← 1;
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to
TAP CCR ← (A) ↕ ↕ ↕ ↕ ↕ ↕ INH 84 1
CCR
Transfer Accumulator to
TAX X ← (A) – – – – – – INH 97 1
X (Index Register Low)
Transfer CCR to
TPA A ← (CCR) – – – – – – INH 85 1
Accumulator
TST opr8a (M) – 0x00 DIR 3D dd 4
TSTA (A) – 0x00 INH 4D 1
TSTX (X) – 0x00 ↕ – INH 5D 1
TST oprx8,X Test for Negative or Zero (M) – 0x00 0 – – ↕ IX1 6D ff 4
TST ,X (M) – 0x00 IX 7D 3
TST oprx8,SP (M) – 0x00 SP1 9E6D ff 5
TSX Transfer SP to Index Reg. H:X ← (SP) + 0x0001 – – – – – – INH 95 2
Transfer X (Index Reg.
TXA A ← (X) – – – – – – INH 9F 1
Low) to Accumulator
TXS Transfer Index Reg. to SP SP ← (H:X) – 0x0001 – – – – – – INH 94 2
Enable Interrupts; Wait
WAIT I bit ← 0; Halt CPU – – 0 – – – INH 8F 2+
for Interrupt

1 Bus clock frequency is one-half of the CPU clock frequency.

MC9S08QE128 MCU Series Reference Manual, Rev. 2

Freescale Semiconductor 163