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MX 8M Plus Applications Processor
Reference Manual
Document Number: IMX8MPRM
Rev. 2, 02/2024
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 Product Overview ............................................................................................................................................................. 9
1.2 Target Applications............................................................................................................................................................9
1.3 Acronyms and Abbreviations............................................................................................................................................ 9
1.4 Architectural Overview....................................................................................................................................................12
Chapter 2
Memory Map
2.1 Memory system overview................................................................................................................................................23
2.2 Cortex-A53 Memory Map .............................................................................................................................................. 24
2.3 Cortex-M7 Memory Map.................................................................................................................................................26
2.4 DMA memory maps........................................................................................................................................................ 29
2.5 AIPS Memory Maps........................................................................................................................................................ 30
2.6 DAP Memory Map.......................................................................................................................................................... 36
2.7 Audio Processor Memory Map........................................................................................................................................38
2.8 HDMI_TX Subsystem Memory Map.............................................................................................................................. 38
Chapter 3
Security
3.1 System Security............................................................................................................................................................... 41
3.2 Resource Domain Controller (RDC)............................................................................................................................... 44
Chapter 4
Arm Platform and Debug
4.1 Arm Cortex A53 Platform (A53).....................................................................................................................................91
4.2 Arm Cortex M7 Platform (CM7).....................................................................................................................................98
4.3 Messaging Unit (MU).................................................................................................................................................... 100
4.4 Semaphore (SEMA4).....................................................................................................................................................144
4.5 On-Chip RAM Memory Controller (OCRAM).............................................................................................................162
4.6 Network Interconnect Bus System (NIC)...................................................................................................................... 165
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Section number Title Page
4.7 AHB to IP Bridge (AIPSTZ)......................................................................................................................................... 166
4.8 Shared Peripheral Bus Arbiter (SPBA)..........................................................................................................................189
4.9 TrustZone Address Space Controller (TZASC)............................................................................................................ 202
4.10 System Debug................................................................................................................................................................ 204
4.11 System Counter (SYS_CTR)......................................................................................................................................... 208
Chapter 5
Clocks and Power Management
5.1 Clock Control Module (CCM).......................................................................................................................................229
5.2 General Power Controller (GPC)...................................................................................................................................570
5.3 Crystal Oscillator (XTALOSC)..................................................................................................................................... 724
5.4 Thermal Monitoring Unit (TMU).................................................................................................................................. 728
Chapter 6
SNVS, Reset, Fuse, and Boot
6.1 System Boot................................................................................................................................................................... 747
6.2 Fusemap......................................................................................................................................................................... 814
6.3 On-Chip OTP Controller (OCOTP_CTRL)...................................................................................................................830
6.4 Secure Non-Volatile Storage (SNVS)........................................................................................................................... 874
6.5 System Reset Controller (SRC)..................................................................................................................................... 903
6.6 Watchdog Timer (WDOG)............................................................................................................................................ 975
Chapter 7
Interrupts and DMA
7.1 Interrupts and DMA Events........................................................................................................................................... 995
7.2 Smart Direct Memory Access Controller (SDMA)..................................................................................................... 1016
7.3 Enhanced Direct Memory Access (eDMA).................................................................................................................1263
7.4 Interrupt Request Steering (IRQ_STEER)...................................................................................................................1325
Chapter 8
Chip IO and Pinmux
8.1 External Signals and Pin Multiplexing........................................................................................................................ 1335
8.2 IOMUX Controller (IOMUXC)...................................................................................................................................1358
8.3 General Purpose Input/Output (GPIO)........................................................................................................................ 1986
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Section number Title Page
Chapter 9
External Memory
9.1 External Memory Overview........................................................................................................................................ 2005
9.2 DDR Controller (DDRC).............................................................................................................................................2007
9.3 DDR BLK_CTRL........................................................................................................................................................2181
9.4 DDR PHY (DDR_PHY).............................................................................................................................................. 2183
9.5 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)......................................................................................... 2194
9.6 62BIT Correcting ECC Accelerator (BCH).................................................................................................................2234
9.7 General Purpose Media Interface (GPMI)...................................................................................................................2297
Chapter 10
Mass Storage
10.1 Enhanced Configurable SPI (ECSPI).......................................................................................................................... 2355
10.2 FlexSPI Controller (FlexSPI).......................................................................................................................................2385
10.3 Ultra Secured Digital Host Controller (uSDHC)......................................................................................................... 2518
Chapter 11
Connectivity
11.1 HSIO BLK_CTRL....................................................................................................................................................... 2677
11.2 Universal Serial Bus Controller (USB)........................................................................................................................2699
11.3 Universal Serial Bus PHY (USB_PHY)...................................................................................................................... 3014
11.4 PCI Express (PCIe)...................................................................................................................................................... 3019
11.5 PCI Express PHY (PCIe_PHY)................................................................................................................................... 3395
11.6 Ethernet MAC (ENET)................................................................................................................................................ 3787
11.7 Ethernet Quality Of Service (ENET_QOS) ................................................................................................................3990
11.8 FlexCAN...................................................................................................................................................................... 5018
Chapter 12
Timers
12.1 General Purpose Timer (GPT)..................................................................................................................................... 5163
12.2 Pulse Width Modulation (PWM)................................................................................................................................. 5183
Chapter 13
Display, Imaging, and Camera
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Section number Title Page
13.1 Display, Imaging, and Camera Overview....................................................................................................................5195
13.2 MEDIA BLK_CTRL................................................................................................................................................... 5203
13.3 LCD Interface (LCDIF)............................................................................................................................................... 5275
13.4 Image Sensing Interface (ISI)...................................................................................................................................... 5306
13.5 MIPI CSI Host Controller (MIPI_CSI)........................................................................................................................5389
13.6 MIPI DSI Host Controller (MIPI_DSI)....................................................................................................................... 5438
13.7 MIPI D-PHY (MIPI_DPHY).......................................................................................................................................5511
13.8 LVDS Display Bridge (LDB)...................................................................................................................................... 5535
13.9 HDMI TX Controller................................................................................................................................................... 5538
13.10 HDMI TX PHY............................................................................................................................................................5821
13.11 HDMI TX BLK_CTRL............................................................................................................................................... 5868
13.12 HDMI TX Parallel Audio Interface (HTX_PAI).........................................................................................................5899
13.13 HDMI TX Parallel Video Interface (HTX_PVI)......................................................................................................... 5912
13.14 Image Signal Processor (ISP)...................................................................................................................................... 5936
13.15 DeWarp........................................................................................................................................................................ 5942
13.16 Machine Learning Neural Processing Unit (NPU)...................................................................................................... 5948
Chapter 14
Audio
14.1 Audio Overview...........................................................................................................................................................5985
14.2 AUDIO BLK_CTRL................................................................................................................................................... 5989
14.3 PDM Microphone Interface (MICFIL)........................................................................................................................6020
14.4 Synchronous Audio Interface (SAI)............................................................................................................................ 6066
14.5 Asynchronous Sample Rate Converter (ASRC).......................................................................................................... 6120
14.6 Enhanced Audio Return Channel (eARC)...................................................................................................................6206
14.7 Audio DSP (HiFi 4 DSP).............................................................................................................................................6275
Chapter 15
Graphics Processing Unit (GPU)
15.1 GPU Overview.............................................................................................................................................................6283
15.2 2D Graphics Processing Unit (GPU2D)...................................................................................................................... 6284
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Section number Title Page
15.3 3D Graphics Processing Unit (GPU3D)...................................................................................................................... 6298
Chapter 16
Video Processing Unit (VPU)
16.1 VPU G1 Decoder......................................................................................................................................................... 6307
16.2 VPU G2 Decoder......................................................................................................................................................... 6476
16.3 VPU VC8000E Encoder.............................................................................................................................................. 6712
16.4 VPU BLK_CTRL........................................................................................................................................................ 7331
Chapter 17
Low Speed Communication and Interconnects
17.1 I2C Controller (I2C).................................................................................................................................................... 7343
17.2 Universal Asynchronous Receiver/Transmitter (UART)............................................................................................ 7367
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Chapter 1
Introduction
1.1 Product Overview
This chapter introduces the architecture of the i.MX 8M Plus Applications Processor.
The i.MX 8M Plus family is a set of NXP products focused on machine learning
applications, combining state-of-art multimedia features with high-performance
processing optimized for low-power consumption.
The i.MX 8M Plus Applications Processor relies on a powerful fully coherent core
complex based on a quad Cortex-A53 cluster, a Cortex-M7 coprocessor, audio digital
signal processor, machine learning and graphics accelerators.
The i.MX 8M Plus provides additional computing resources and peripherals:
• Advanced security modules for secure boot, cipher acceleration and DRM support
• A wide range of audio interfaces
• Large set of peripherals that are commonly used in consumer/industrial markets
including USB , PCIe, Ethernet, and CAN
1.2 Target Applications
The i.MX 8M Plus Media Applications Processor targets applications on:
• Smart Homes, Buildings and Cities
• Machine Learning and Industrial Automation
• Consumer and Pro Audio/Voice Systems
1.3 Acronyms and Abbreviations
The table below contains acronyms and abbreviations used in this document.
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Acronyms and Abbreviations
Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AIPS Arm IP Bus
ALU Arithmetic Logic Unit
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
ASRC Asynchronous Sample Rate Converter
AXI Advanced eXtensible Interface
CA/CM Arm Cortex-A/Cortex-M
CAAM Cryptographic Acceleration and Assurance Module
CA53 Arm Cortex A53 Core
CAN Controller Area Network
CM7 Arm Cortex M7 Core
CPU Central Processing Unit
CSI CMOS Sensor Interface
CSU Central Security Unit
CTI Cross Trigger Interface
D-cache Data cache
DAP Debug Access Port
DDR Double data rate
DMA Direct memory access
DPLL Digital phase-locked loop
DRAM Dynamic random access memory
ECC Error correcting codes
ECSPI Enhanced Configurable SPI
LPSPI Low-power SPI
EDMA Enhanced Direct Memory Access
EIM External Interface Module
ENET Ethernet
EPIT Enhanced Periodic Interrupt Timer
EPROM Erasable Programmable Read-Only Memory
ETF Embedded Trace FIFO
ETM Embedded Trace Macrocell
FIFO First-In-First-Out
GIC General Interrupt Controller
GPC General Power Controller
GPIO General-Purpose I/O
GPR General-Purpose Register
GPS Global Positioning System
Table continues on the next page...
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Chapter 1 Introduction
Term Meaning
GPT General-Purpose Timer
GPU Graphics Processing Unit
GPV Global Programmers View
HAB High-Assurance Boot
I-cache Instruction cache
I2C or I2C Inter-Integrated Circuit
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
IOMUX Input-Output Multiplexer
IP Intellectual Property
IrDA Infrared Data Association
ISP Image Signal Processor
JTAG Joint Test Action Group (a serial bus protocol usually used for test purposes)
ELCDIF Liquid Crystal Display Interface
LDO Low-Dropout
LIFO Last-In-First-Out
LRU Least-Recently Used
LSB Least-Significant Byte
LUT Look-Up Table
LVDS Low Voltage Differential Signaling
MAC Medium Access Control
MCM Miscellaneous Control Module
ML Machine Learning
MMC Multimedia Card
MSB Most-Significant Byte
MT/s Mega Transfers per second
NPU Neural Processing Unit
OCRAM On-Chip Random-Access Memory
OCOTP On-Chip One-Time Programmable Controller
PCI Peripheral Component Interconnect
PCIe PCI express
PGC Power Gating Controller
PIC Programmable Interrupt Controller
PMU Power Management Unit
POR Power-On Reset
PSRAM Pseudo-Static Random Access Memory
PWM Pulse Width Modulation
PXP Pixel Pipeline
QoS Quality of Service
R2D Radians to Degrees
RISC Reduced Instruction Set Computing
Table continues on the next page...
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Architectural Overview
Term Meaning
ROM Read-Only Memory
RTOS Real-Time Operating System
Rx Receive
SAI Synchronous Audio Interface
SD Secure Digital
SDIO Secure Digital Input/Output
SDLC Synchronous Data Link Control
SDMA Smart DMA
SIM Subscriber Identification Module
SNVS Secure Non-Volatile Storage
SoC System-on-Chip
SPBA Shared Peripheral Bus Arbiter
SPDIF Sony Philips Digital Interface
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
SRC System Reset Controller
TFT Thin-Film Transistor
TPIU Trace Port Interface Unit
TSGEN Time Stamp Generator
Tx Transmit
TZASC TrustZone Address Space Controller
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
USDHC Ultra Secured Digital Host Controller
WDOG Watchdog
WLAN Wireless Local Area Network
WXGA Wide Extended Graphics Array
1.4 Architectural Overview
This section contains the i.MX 8M Plus architectural overview.
1.4.1 Block Diagram
The high-level block diagram is shown in the figure below.
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Chapter 1 Introduction
Battery Ctrl JTAG Crystal&
LPDDR4/DDR4
Device (IEEE1149.6) Clock Source
eMMC 5.0 Arm Cortex A53 Debug Clock & Reset
External Memory
FLASH MPCore Platform DAP PLLs
DDR Controller CPU3
CTIs CCM
SD/eMMC CPU2
NAND FLASH GPMI&BCH CPU1 SJC GPC
CPU0 SRC
QSPI I$ 32KB D$ 32KB
Quad SPI XTAL OSC
NEON CRYPTO
Flash
RC OSC
SCU & Timer Audio DSP Core
Internal Memory I$ 32KB D$ 48KB
L2 Cache 512 KB
OCRAM 576KB DTCM 64KB
AXI and AHB Switch Fabric
OCRAM_S 36KB Arm Cortex M7 AP Peripherals
OCRAM_A 256KB MMC/SD
Platform
ROM 256KB uSDHC(3) eMMC/eSD
Cortex-M7 Core
OCOTP
I$ 32KB D$ 32KB MMC/SD
Security NVIC FPU MPU USB 3.0 SDXC
CAAM Smart DMA (2)
(32KB RAM) TCM 256KB SDMA(3)
ENET Qos USB
CSU with TSN (dev/host)
OCOTP (eFuse)
AVB ENET 1Gbit Ethernet
SPBA(2) with TSN
SNVS(RTC) Multi-Core Unit PCIe v3.0
RDC MU
Shared Peripherals CAN-FD(2) 10/100/1000M
SEMAPHORE eCSPI(3) Ethernet
Display Interface I2C(6)
Graphics/Video SAI(6)
LVDS Display LCDIF(3) eCSPI(3) PCIe Bus
GPU UART(4)
LVDS PWM(4)
VPU PDM
MIPI Display MIPI DSI
Machine Learning UART(4)
MIPI CSI2(2)
NPU Timers GPIO(5x32)
Camera ISP(2)
WDOG(3) IOMUX
ISI Power Management
HDMI Display Temp Monitor GPT(6)
HDMI 2.0a
System Counter
Figure 1-1. Block Diagram
1.4.2 Features
1.4.2.1 Arm Cortex-A53 MPCore™ Platform
The i.MX 8M Plus Applications Processor is based on the Arm Cortex-A53 MPCore™
Platform, which has the following features:
• Quad symmetric Cortex-A53 processors, including:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
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Architectural Overview
• Media Processing Engine (MPE) with NEON technology supporting the
Advanced Single Instruction Multiple Data architecture
• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
• Support of 64-bit Armv8-A architecture
• 512 KB unified L2 cache
1.4.2.2 Arm Cortex-M7 Platform
The Cortex-M7 Core Platform includes the following:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• 256 KB TCM
Available customer applications include:
• Low power standby mode
• IoT device control
• ML applications
1.4.2.3 System Bus and Interconnect
System bus and interconnect include the following:
• Network interconnect (NoC) AXI arbiter
• Quality of service controller (QoSC) to configure priorities and limits of AXI
transcations
• Performance monitor (PERFMON) to monitor AXI bus activity
• Debug monitor (DBGMON) to record AXI transactions preceding a system reset
1.4.2.4 Clocking and Resets
Clocking and resets include:
• Clock control module (CCM) provides centralized clock generation and control
• Simplified clock tree structure
• Unified clock programming model for each clock root
• Multicore awareness for resource domains
• System reset controller (SRC) provides reset generation and distribution
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Chapter 1 Introduction
1.4.2.5 Interrupts and DMA
Interrupts and DMA include:
• 160 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller
(GIC) and Cortex-M7 nested vector interrupt controller (NVIC) for flexible interrupt
handling
• Three Smart direct memory access (SDMA) engines. Although these three engines
are identical to each other, they are integrated into the processor to serve different
peripherals.
• SDMA-1 is a general-purpose DMA engine which can be used by low speed
peripherals including UART, SPI and also others peripherals.
• SDMA-2 and SMDA-3 is used for audio interface, including SAI-1/2/3/5/6/7,
SPDIF and PDM audio input.
1.4.2.6 On-Chip Memory
The on-chip memory system consists of the following:
• Boot ROM (256KB)
• On-Chip RAM - OCRAM (576KB)
• Audio Processor System RAM - OCRAM_A (256KB)
• On-Chip RAM for State Retention - OCRAM_S (36KB)
1.4.2.7 External Memory Interface
The external memory interfaces supported on this chip include:
• 32-bit DRAM Interface:
• LPDDR4-4000
• DDR4-3200
• 8-bit NAND FLASH, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
• eMMC 5.1 FLASH (2 interfaces)
• SPI NOR FLASH (3 interfaces)
• FlexSPI FLASH with support for XIP (for example for use in a low-power mode
when DRAM is not accessible) and support for either one Octal SPI, or parallel read
mode of two identical Quad SPI FLASH devices
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Architectural Overview
1.4.2.8 Timers
The timers on this chip include:
• One local generic timer integrated into each Cortex-A53 CPU
• Global system counter with timer bus interface to Cortex-A53 MPCore generic
timers
• One local system timer (SysTick) integrated into the Cortex-M7 CPU
• Six general purpose timer (GPT) modules
• Three watchdog timer (WDOG) modules
• Four pulse width modulation (PWM) modules
1.4.2.9 Graphics Processing Unit (GPU)
The chip incorporates the following Graphics Processing Unit (GPU) features:
• One GPU for 2D and composition acceleration
• Supports multi-source composition
• Supports one-pass filter
• Supports tile format
• One GPU for 3D processing
• Two Shader Execution Units
• Supports OpenGL ES 1.1, 2.0, 3.0, 3.1
• Supports OpenCL 3.0
• Supports OpenVG 1.1
• Supports OpenGL 4.0
• Supports EGL 1.5
• Supports Vulkan 1.1
• Supports tile format
1.4.2.10 Video Processing Unit (VPU)
The chip incorporates the following Video Processing Unit (VPU) features:
• Video Decode:
• 1080p60 HEVC/H.265 Main, Main 10 (up to level 5.1) (VPU G2)
• 1080p60 VP9 Profile 0, 2 (VPU G2)
• 1080p60 VP8 (VPU G1)
• 1080p60 AVC/H.264 Baseline, Main, High decoder (VPU G1)
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Chapter 1 Introduction
• Video Encode:
• 1080p60 AVC/H.264 encoder
• 1080p60 HEVC/H.265 encoder
• TrustZone support
1.4.2.11 Machine Learning: NPU (Neural Processing Unit)
• 2.3 TOP/s Neural Network performance available for user applications
• Speech recognition (e.g., Deep Speech 2)
• Image recognition (e.g., ResNet-50)
• Object detection (e.g., MobileNet-SSD)
1.4.2.12 Display Interfaces
The chip has the following display support:
• Three LCDIF Display Controllers:
• One LCDIF drives MIPI DSI
• One LCDIF drives LVDS Tx
• One LCDIF drives HDMI Tx
• Support up to 1920x1200p60 display per LCDIF if no more than 2 instances
used simultaneously, or 2x 1080p60 + 1x 4kp30 on HDMI if all 3 instances used
simultaneously.
• Supports 8-bit / 16-bit / 18-bit / 24-bit / 32-bit pixel depth
• Supports one layer
• MIPI Interface:
• One 4-lane MIPI DSI interface
• Two 4-lane MIPI CSI interfaces
• One 4-lane or 8-lane LVDS interface
• ISI (Image Sensor Interface):
• The ISI is a simple camera interface that supports image processing and transfer
via a bus master interface for up to 2 cameras
• Two Camera ISP (Image Signal Processor):
• When one camera is used, supports up to 12MP@30fps or 4kp45
• When two cameras are used, each supports up to 1080p80
• HDMI 2.0a
• HDMI 2.0a Tx supporting one display
• Resolutions of: 740x480p60, 720x480p60, 1280x720p60, 1920x1080p60,
1920x1080p120, 3840x2160p30
• Audio support
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Architectural Overview
• 32 channel audio output support
• 1 S/PDIF audio eARC input support
1.4.2.13 Audio
Audio include the following:
• Audio DSP
• S/PDIF Input and Output, including a Raw Capture input mode
• Six external SAI (synchronous audio interface) modules supporting I2S, AC97,
TDM, codec/DSP and DSD interfaces, comprising one SAI with 8 TX and 8 RX
lanes, one SAI with 4 TX and 4 RX lanes, two SAI with 2 TX and 2 RX lanes, and
two SAI with 1 TX and 1 RX lanes.
• PDM Microphone Interface module which supports up to 8-microphones (4 lanes)
• Asynchronous Sample Rate Converter (ASRC) module which supports:
• Processing of up to 32 audio channels
• 4 context groups
• 8 kHz to 384 kHz sample rate
• 1/16 to 8x sample rate conversion ratio
1.4.2.14 General Connectivity Interfaces
The chip contains a rich set of general connectivity interfaces, including:
• One PCI Express (PCIe):
• Single lane supporting PCIe Gen 3
• Dual mode operation to function as root complex or endpoint
• Integrated PHY interface
• Supports L1 low power substate
• Two USB 3.0 Type C controllers with integrated PHY interface
• Backwards compatibility with USB 2.0
• Spread spectrum clock support
• Three Ultra Secure Digital Host Controller (uSDHC) interfaces
• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec
• SD/SDIO 3.01 compliance with 200 MHZ SDR signaling to support up to 100
MB/sec
• Support for SDXC (extended capacity)
• Two Ethernet controllers, capable of simultaneous operation
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Chapter 1 Introduction
• One Gigabit Ethernet controller with support for EEE, Ethernet AVB and
IEEE1588
• One Gigabit Ethernet controller with support for TSN, EEE, Ethernet AVB and
IEEE1588
• Two controller area network (FlexCAN) modules, each optionally supporting
flexible datarate (FD)
• Four universal asynchronous receiver/transmitter (UART) modules
• Six I2C modules
• Three SPI modules
1.4.2.15 Security
Security functions are enabled and accelerated by the following hardware:
• RDC – Resource Domain Controller:
• Supports 4 domains and up to 8 regions
• Arm TrustZone including the TZ architecture:
• Arm Cortex-A53 MPCore TrustZone support
• On-chip RAM (OCRAM) secure region protection using OCRAM controller
• High Assurance Boot (HAB)
• Cryptographic Acceleration and Assurance Module (CAAM)
• Support Widevine and PlayReady content protection
• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC)
algorithms
• Real-time integrity checker (RTIC)
• DRM support for RSA, AES, 3DES, DES
• True random number generation (RNG)
• Manufacturing protection support
• Secure Non-Volatile Storage (SNVS), including
• Secure Real Time Clock (SRTC)
• Secure JTAG Controller (SJC)
1.4.2.16 Multicore Support
Multicore support contains:
• Resource domain controller (RDC) to support isolation and safe sharing of system
resources
• Messaging unit (MU)
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Architectural Overview
• Hardware Semaphore (SEMA4)
• Shared bus topology
1.4.2.17 GPIO and Pin Multiplexing
• General-purpose input/output (GPIO) modules with interrupt capability
• Input/output multiplexing controller (IOMUXC) to provide centralized pad control
1.4.2.18 Power Management
The power management unit consists of:
• Temperature sensor with programmable trip points
• Flexible power domain partitioning with internal power switches to support efficient
power management
1.4.2.19 System Debug
The system debug features are:
• Arm CoreSight debug and trace architecture
• Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering
• Unified trace capability for Quad Cortex-A53 and Cortex-M7 CPUs
• Cross Triggering Interface (CTI)
• Support for 5-pin (JTAG) debug interfaces
1.4.3 Primary Boot Options
The i.MX 8M Plus supports the following boot devices:
• NAND FLASH (including SLC and MLC)
• SDIO / MMC / SDXC
• eSD 3.0/eMMC 5.1 (fast boot)
• SPI (serial FLASH)
• USB Serial Download
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Chapter 1 Introduction
The Quad-A53 core on i.MX 8M Plus is enabled during boot as the primary core to
handle the entire secure boot flow. The chip will always boot from the A53 core first, the
M7 core will be held in reset during the A53 boot and won’t run until it is enabled by the
A53 core. The image for the M7 core will be loaded into memory and authenticated by
the A53 core.
1.4.4 Endianness Support
This chip supports Little Endian mode only.
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Architectural Overview
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Chapter 2
Memory Map
2.1 Memory system overview
2.1.1 On-chip L1, L2 caches, TCM
Cortex-A53 MPcore Platform
• Level 1 Cache (4x per Cortex-A53 Core)
• Instruction (32 KB)
• Data (32 KB)
• Level 2 Cache, shared by the four Cortex-A53 cores:
• Unified instruction and data (512 KB)
Cortex M7 Platform
• Cache
• Instruction (32 KB)
• Data (32 KB)
• Tightly-Coupled-Memory
• DTCM (128KB)
• ITCM (128KB)
2.1.2 On-chip memories
• Boot ROM (256 KB)
• On-Chip RAM - OCRAM (576 KB)
• Audio Processor System RAM - OCRAM_A (256KB)
• On-Chip RAM for State Retention - OCRAM_S (36 KB)
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Cortex-A53 Memory Map
2.1.3 External L3 memories
The chip supports external memories, via the following memory interfaces / controllers:
• 32-bit DRAM Interface:
• LPDDR4-4000 and DDR4-3200
• 8-bit NAND FLASH, including support for Raw MLC/SLC devices, BCH ECC up to
62-bit, and ONFI 3.2 compliance (clock rates up to 100 MHz and data rates up to 200
MB/sec)
• eMMC 5.1 FLASH
• SPI NOR FLASH
• FlexSPI FLASH with support for XIP (for example for use in a low-power mode
when DRAM is not accessible) and support for one Octal SPI, or parallel read mode
of two identical Quad SPI FLASH devices.
2.2 Cortex-A53 Memory Map
Start Address End Address Region Size Description
1_0000_0000 2_3FFF_FFFF DDR Address 5120MB DDR Memory (All modules except M7)
4000_0000 FFFF_FFFF DDR Address 3072MB DDR Memory (All modules)
3F00_0000 3FFF_FFFF Reserved 16MB Reserved
3E00_0000 3EFF_FFFF Reserved 16MB Reserved
3DC0_0000 3DFF_FFFF DDRC 4MB DDR PHY (Broadcast)
3D80_0000 3DBF_FFFF DDRC 4MB DDR PERF_MON
3D40_0000 3D7F_FFFF DDRC 4MB DDR CTL
3D10_0000 3D3F_FFFF Reserved 3MB Reserved
3D00_0000 3D0F_FFFF DDRC 1MB DDR BLK_CTRL
3C00_0000 3CFF_FFFF DDRC 16MB DDR PHY
3B00_0000 3BFF_FFFF Audio DSP 16MB Audio DSP. See Audio Processor Memory Map.
3A00_0000 3AFF_FFFF Reserved 16MB Reserved
3890_0000 39FF_FFFF Reserved 23MB Reserved
3880_0000 388F_FFFF GIC 1MB GIC REG
3870_0000 387F_FFFF Reserved 1MB Reserved
3850_0000 386F_FFFF NPU 2MB NPU
3834_0000 384F_FFFF VPU 2MB VPU
3833_0000 383F_FFFF 2MB VPU BLK_CTRL
3832_0000 3842_FFFF 2MB VPU VC8000E Encoder
3831_0000 3841_FFFF 2MB VPU G2 Decoder
3830_0000 3830_FFFF 2MB VPU G1 Decoder
3820_0000 382F_FFFF USB2 REG 1MB USB2 REG
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Chapter 2 Memory Map
Start Address End Address Region Size Description
3810_0000 381F_FFFF USB1 REG 1MB USB1 REG
3801_0000 380F_FFFF Reserved 960KB Reserved
3800_8000 3800_FFFF GPU REG 32KB GPU2D REG
3800_0000 3800_7FFF GPU REG 32KB GPU3D REG
3600_0000 37FF_FFFF QSPI RX Buffers 32MB Reserved
3400_0000 35FF_FFFF 32MB QSPI1 RX Buffer
33C0_0000 33FF_FFFF PCIe REG 4MB Reserved
3380_0000 33BF_FFFF 4MB PCIe1 REG
3310_0000 337F_FFFF Reserved 7MB Reserved
3301_0000 330F_FFFF Reserved 960KB Reserved
3300_8000 3300_FFFF QSPI TX Buffers 32KB QSPI1 TX Buffer
3300_0000 3300_7FFF APBH DMA 32KB APBH DMA
32C0_0000 32FF_FFFF Periph (AIPS) 4MB AIPS-4. See IP listing on separate map.
3290_0000 32BF_FFFF Reserved 3MB Reserved
3280_0000 328F_FFFF Reserved 1MB Reserved
3270_0000 327F_FFFF Reserved 1MB Reserved
3260_0000 326F_FFFF Reserved 1MB Reserved
3250_0000 325F_FFFF Reserved 1MB Reserved
3240_0000 324F_FFFF Reserved 1MB Reserved
3230_0000 323F_FFFF Reserved 1MB Reserved
3220_0000 322F_FFFF Reserved 1MB Reserved
3210_0000 321F_FFFF Reserved 1MB Reserved
3200_0000 320F_FFFF Reserved 1MB Reserved
3100_0000 31FF_FFFF Reserved 16MB Reserved
30C0_0000 30FF_FFFF Periph (AIPS) 4MB AIPS-5. See IP listing on separate map.
3080_0000 30BF_FFFF 4MB AIPS-3. See IP listing on separate map.
3040_0000 307F_FFFF 4MB AIPS-2. See IP listing on separate map.
3000_0000 303F_FFFF 4MB AIPS-1. See IP listing on separate map.
2900_0000 2FFF_FFFF Reserved 112MB Reserved
2800_0000 28FF_FFFF A53 / DAP 16MB A53 / DAP
2000_0000 27FF_FFFF Reserved 128MB Reserved
1800_0000 1FFF_FFFF PCIe-1 128MB PCIe-1
0800_0000 17FF_FFFF QSPI 256MB QSPI
0400_0000 07FF_FFFF Reserved 64MB Reserved
0100_0000 03FF_FFFF Reserved 48MB Reserved
00C0_0000 00FF_FFFF Reserved 4MB Reserved
00B0_0000 00BF_FFFF Reserved 1MB Reserved
00A0_0000 00AF_FFFF OCRAM 1MB Reserved
0099_0000 009F_FFFF 448KB Reserved
0090_0000 0098_FFFF 576KB OCRAM
0084_0000 008F_FFFF Reserved 768KB Reserved
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NXP Semiconductors 25
Cortex-M7 Memory Map
Start Address End Address Region Size Description
0082_0000 0083_FFFF TCM 128KB Reserved
0080_0000 0081_FFFF 128KB DTCM
007E_0000 007F_FFFF 128KB ITCM
007C_0000 007D_FFFF 128KB Reserved
0070_0000 007B_FFFF Reserved 768KB Reserved
0060_0000 006F_FFFF Reserved 1MB Reserved
0050_0000 005F_FFFF Reserved 1MB Reserved
0040_0000 004F_FFFF Reserved 1MB Reserved
0020_0000 003F_FFFF Reserved 2MB Reserved
0019_0000 001F_FFFF Reserved 448KB Reserved
0018_9000 0018_FFFF OCRAM_S 28KB Reserved
0018_0000 0018_8FFF 36KB OCRAM_S
0011_0000 0017_FFFF Reserved 448KB Reserved
0010_8000 0010_FFFF CAAM 32KB Reserved
0010_0000 0010_7FFF 32KB CAAM (32K secure RAM)
0004_0000 000F_FFFF Reserved 768KB Reserved
0003_F000 0003_FFFF Boot ROM 4KB Boot ROM - Protected 4KB area
0000_0000 0003_EFFF 252KB Boot ROM
2.3 Cortex-M7 Memory Map
Start Address End Address Region Size Description
E010_0000 FFFF_FFFF Reserved 511MB Reserved
E000_0000 E00F_FFFF CM7 PPB 1MB CM7 PPB
D800_0000 DFFF_FFFF Reserved 128MB Reserved
D000_0000 D7FF_FFFF PCIe-1 128MB PCIe-1
C000_0000 CFFF_FFFF FLASH 256MB QSPI
4000_0000 BFFF_FFFF DDR Address 2048MB DDR Memory
3F00_0000 3FFF_FFFF Reserved 16MB Reserved
3E00_0000 3EFF_FFFF Reserved 16MB Reserved
3DC0_0000 3DFF_FFFF DDRC 4MB DDR PHY (Broadcast)
3D80_0000 3DBF_FFFF DDRC 4MB DDR PERF_MON
3D40_0000 3D7F_FFFF DDRC - CTL 4MB DDR - CTL
3D10_0000 3D3F_FFFF Reserved 3MB Reserved
3D00_0000 3D0F_FFFF DDRC 1MB DDR BLK_CTRL
3C00_0000 3CFF_FFFF DDRC 16MB DDR PHY
3B00_0000 3BFF_FFFF Audio DSP 16MB Audio DSP. See Audio Processor Memory Map.
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26 NXP Semiconductors
Chapter 2 Memory Map
Start Address End Address Region Size Description
3A00_0000 3AFF_FFFF Reserved 16MB Reserved
3890_0000 39FF_FFFF Reserved 23MB Reserved
3880_0000 388F_FFFF GIC 1MB GIC. Please refer to GIC for details on the
limitations for CM7 accessing GIC.
3870_0000 387F_FFFF Reserved 1MB Reserved
3850_0000 386F_FFFF NPU 2MB NPU
3834_0000 384F_FFFF VPU 2MB VPU
3833_0000 383F_FFFF 2MB VPU BLK_CTRL
3832_0000 3842_FFFF 2MB VPU VC8000E Encoder
3831_0000 3841_FFFF 2MB VPU G2 Decoder
3830_0000 3830_FFFF 2MB VPU G1 Decoder
3820_0000 382F_FFFF USB2 REG 1MB USB2 REG
3810_0000 381F_FFFF USB1 REG 1MB USB1 REG
3801_0000 380F_FFFF Reserved 960KB Reserved
3800_8000 3800_FFFF GPU REG 32KB GPU2D REG
3800_0000 3800_7FFF GPU REG 32KB GPU3D REG
3600_0000 37FF_FFFF QSPI RX Buffers 32MB Reserved
3400_0000 35FF_FFFF 32MB QSPI1 RX Buffer
33C0_0000 33FF_FFFF PCIe REG 4MB Reserved
3380_0000 33BF_FFFF 4MB PCIe1 REG
3310_0000 337F_FFFF Reserved 7MB Reserved
3301_0000 330F_FFFF Reserved 960KB Reserved
3300_8000 3300_FFFF QSPI TX Buffers 32KB QSPI1 TX Buffer
3300_0000 3300_7FFF APBH DMA 32KB APBH DMA
32C0_0000 32FF_FFFF Periph (AIPS) 4MB AIPS-4. See IP listing on separate map.
3290_0000 32BF_FFFF Reserved 3MB Reserved
3280_0000 328F_FFFF Reserved 1MB Reserved
3270_0000 327F_FFFF Reserved 1MB Reserved
3260_0000 326F_FFFF Reserved 1MB Reserved
3250_0000 325F_FFFF Reserved 1MB Reserved
3240_0000 324F_FFFF Reserved 1MB Reserved
3230_0000 323F_FFFF Reserved 1MB Reserved
3220_0000 322F_FFFF Reserved 1MB Reserved
3210_0000 321F_FFFF Reserved 1MB Reserved
3200_0000 320F_FFFF Reserved 1MB Reserved
3100_0000 31FF_FFFF Reserved 16MB Reserved
30C0_0000 30FF_FFFF Periph (AIPS) 4MB AIPS-5. See IP listing on separate map.
3080_0000 30BF_FFFF 4MB AIPS-3. See IP listing on separate map.
3040_0000 307F_FFFF 4MB AIPS-2. See IP listing on separate map.
3000_0000 303F_FFFF 4MB AIPS-1. See IP listing on separate map.
2900_0000 2FFF_FFFF Reserved 112MB Reserved
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NXP Semiconductors 27
Cortex-M7 Memory Map
Start Address End Address Region Size Description
2800_0000 28FF_FFFF A53/ DAP 16MB A53/ DAP
2400_0000 27FF_FFFF Reserved 64MB Reserved
2200_0000 23FF_FFFF Reserved 32MB Reserved
2100_0000 21FF_FFFF Reserved 16MB Reserved
2040_0000 20FF_FFFF Reserved 12MB Reserved
2030_0000 203F_FFFF CM7 ALIAS SYSTEM 1MB Reserved
2029_0000 202F_FFFF 448KB Reserved
2020_0000 2028_FFFF 576KB OCRAM
2019_0000 201F_FFFF 448KB Reserved
2018_9000 2018_FFFF 28KB Reserved
2018_0000 2018_8FFF 36KB OCRAM_S
2011_0000 2017_FFFF 448KB Reserved
2010_8000 2010_FFFF 32KB Reserved
2010_0000 2010_7FFF 32KB CAAM (32K secure RAM)
2006_0000 200F_FFFF Reserved 640KB Reserved
2002_0000 2005_FFFF Reserved 256KB Reserved
2000_0000 2001_FFFF DTCM 128KB DTCM
1FFE_0000 1FFF_FFFF Reserved 128KB Reserved
1000_0000 1FFD_FFFF CM7 ALIAS CODE 262016KB DDR Code alias
0800_0000 0FFF_FFFF 128MB QSPI Code alias
0400_0000 07FF_FFFF 64MB Reserved
0100_0000 03FF_FFFF Reserved 48MB Reserved
00C0_0000 00FF_FFFF Reserved 4MB Reserved
00B0_0000 00BF_FFFF Reserved 1MB Reserved
00A0_0000 00AF_FFFF OCRAM 1MB Reserved
0099_0000 009F_FFFF 448KB Reserved
0090_0000 0098_FFFF 576KB OCRAM
0082_8000 008F_FFFF Reserved 864KB Reserved
0082_0000 0082_7FFF Reserved 32KB Reserved
0080_0000 0081_FFFF Reserved 128KB Reserved
007E_0000 007F_FFFF Reserved 128KB Reserved
007D_8000 007D_FFFF Reserved 32KB Reserved
0070_0000 007D_7FFF Reserved 864KB Reserved
0060_0000 006F_FFFF Reserved 1MB Reserved
0050_0000 005F_FFFF Reserved 1MB Reserved
0040_0000 004F_FFFF Reserved 1MB Reserved
0020_0000 003F_FFFF Reserved 2MB Reserved
0019_0000 001F_FFFF Reserved 448KB Reserved
0018_9000 0018_FFFF OCRAM_S 28KB Reserved
0018_0000 0018_8FFF 36KB OCRAM_S
0011_0000 0017_FFFF Reserved 448KB Reserved
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28 NXP Semiconductors
Chapter 2 Memory Map
Start Address End Address Region Size Description
0010_8000 0010_FFFF CAAM 32KB Reserved
0010_0000 0010_7FFF 32KB CAAM (32K secure RAM)
0002_0000 000F_FFFF Reserved 896KB Reserved
0000_0000 0001_FFFF ITCM 128KB ITCM
2.4 DMA memory maps
The Smart DMA memory maps are defined in the following tables.
Table 2-1. SDMA1 Peripheral Memory Map
Address Peripheral
0xF000 SPBA
0xE000 Reserved for SDMA internal registers
0xD000 CAN_FD2
0xC000 CAN_FD1
0xB000 Reserved
0xA000 Reserved
0x9000 UART2
0x8000 UART3
0x7000 Reserved for SDMA internal registers
0x6000 UART1
0x5000 Reserved
0x4000 eCSPI3
0x3000 eCSPI2
0x2000 eCSPI1
0x1000 Reserved
0x0000 Reserved for SDMA internal memory
Table 2-2. SDMA2/3 Peripheral Memory Map
Address Peripheral
0xF000 SPBA
0xE000 Reserved for SDMA internal registers
0xD000 Reserved
0xC000 AUDIO XCVR RX (eARC)
0xB000 HDMI TX AUDLNK MST
0xA000 PDM (MICFIL)
0x9000 ASRC
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NXP Semiconductors 29
AIPS Memory Maps
Table 2-2. SDMA2/3 Peripheral Memory Map (continued)
Address Peripheral
0x8000 SAI7
0x7000 Reserved for SDMA internal registers
0x6000 SAI6
0x5000 SAI5
0x4000 Reserved
0x3000 SAI3
0x2000 SAI2
0x1000 SAI1
0x0000 Reserved for SDMA internal memory
2.5 AIPS Memory Maps
Table 2-3. AIPS1 Memory Map
Start Address End Address Region NIC Port Size
303F_0000 303F_FFFF AIPS-1 (s_b_0) Reserved 64KB
303E_0000 303E_FFFF CSU 64KB
303D_0000 303D_FFFF RDC 64KB
303C_0000 303C_FFFF SEMAPHORE2 64KB
303B_0000 303B_FFFF SEMAPHORE1 64KB
303A_0000 303A_FFFF GPC 64KB
3039_0000 3039_FFFF SRC 64KB
3038_0000 3038_FFFF CCM 64KB
3037_0000 3037_FFFF SNVS_HP 64KB
3036_0000 3036_FFFF ANA_PLL 64KB
3035_0000 3035_FFFF OCOTP_CTRL 64KB
3034_0000 3034_FFFF IOMUXC_GPR 64KB
3033_0000 3033_FFFF IOMUXC 64KB
3032_0000 3032_FFFF Reserved 64KB
3031_0000 3031_FFFF Reserved 64KB
3030_0000 3030_FFFF Reserved 64KB
302F_0000 302F_FFFF GPT3 64KB
302E_0000 302E_FFFF GPT2 64KB
302D_0000 302D_FFFF GPT1 64KB
302C_0000 302C_FFFF Reserved 64KB
302B_0000 302B_FFFF Reserved 64KB
302A_0000 302A_FFFF WDOG3 64KB
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30 NXP Semiconductors
Chapter 2 Memory Map
Table 2-3. AIPS1 Memory Map (continued)
Start Address End Address Region NIC Port Size
3029_0000 3029_FFFF WDOG2 64KB
3028_0000 3028_FFFF WDOG1 64KB
3027_0000 3027_FFFF ANA_OSC 64KB
3026_0000 3026_FFFF TMU (ANA_TSENSOR) 64KB
3025_0000 3025_FFFF Reserved 64KB
3024_0000 3024_FFFF GPIO5 64KB
3023_0000 3023_FFFF GPIO4 64KB
3022_0000 3022_FFFF GPIO3 64KB
3021_0000 3021_FFFF GPIO2 64KB
3020_0000 3020_FFFF GPIO1 64KB
301F_0000 301F_FFFF AIPS1_Configuration 64KB
3010_0000 301E_FFFF AIPS-1 Glob. Module Reserved 960KB
Enable
3000_0000 300F_FFFF Reserved 1024KB
Table 2-4. AIPS2 Memory Map
Start Address End Address Region NIC Port Size
307F_0000 307F_FFFF AIPS-2 (s_b_1) QoSC 64KB
307E_0000 307E_FFFF Reserved 64KB
307D_0000 307D_FFFF PERFMON2 64KB
307C_0000 307C_FFFF PERFMON1 64KB
307B_0000 307B_FFFF Reserved 64KB
307A_0000 307A_FFFF Reserved 64KB
3079_0000 3079_FFFF Reserved 64KB
3078_0000 3078_FFFF Reserved 64KB
3077_0000 3077_FFFF Reserved 64KB
3076_0000 3076_FFFF Reserved 64KB
3075_0000 3075_FFFF Reserved 64KB
3074_0000 3074_FFFF Reserved 64KB
3073_0000 3073_FFFF Reserved 64KB
3072_0000 3072_FFFF Reserved 64KB
3071_0000 3071_FFFF Reserved 64KB
3070_0000 3070_FFFF GPT4 64KB
306F_0000 306F_FFFF GPT5 64KB
306E_0000 306E_FFFF GPT6 64KB
306D_0000 306D_FFFF Reserved 64KB
306C_0000 306C_FFFF System_Counter_CTRL 64KB
306B_0000 306B_FFFF System_Counter_CMP 64KB
306A_0000 306A_FFFF System_Counter_RD 64KB
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NXP Semiconductors 31
AIPS Memory Maps
Table 2-4. AIPS2 Memory Map (continued)
Start Address End Address Region NIC Port Size
3069_0000 3069_FFFF PWM4 64KB
3068_0000 3068_FFFF PWM3 64KB
3067_0000 3067_FFFF PWM2 64KB
3066_0000 3066_FFFF PWM1 64KB
3065_0000 3065_FFFF Reserved 64KB
3064_0000 3064_FFFF Reserved 64KB
3063_0000 3063_FFFF Reserved 64KB
3062_0000 3062_FFFF Reserved 64KB
3061_0000 3061_FFFF Reserved 64KB
3060_0000 3060_FFFF Reserved 64KB
305F_0000 305F_FFFF AIPS2_configuration 64KB
3050_0000 305E_FFFF AIPS-2 Glob. Module Reserved 960KB
Enable
3040_0000 304F_FFFF Reserved 1024KB
Table 2-5. AIPS3 Memory Map
Start Address End Address Region NIC Port Size
30BF_0000 30BF_FFFF AIPS-3 (s_b_2) ENET2_TSN 64KB
30BE_0000 30BE_FFFF ENET1 64KB
30BD_0000 30BD_FFFF SDMA1 64KB
30BC_0000 30BC_FFFF Reserved 64KB
30BB_0000 30BB_FFFF QSPI 64KB
30BA_0000 30BA_FFFF Reserved 64KB
30B9_0000 30B9_FFFF Reserved 64KB
30B8_0000 30B8_FFFF Reserved 64KB
30B7_0000 30B7_FFFF Reserved 64KB
30B6_0000 30B6_FFFF uSDHC3 64KB
30B5_0000 30B5_FFFF uSDHC2 64KB
30B4_0000 30B4_FFFF uSDHC1 64KB
30B3_0000 30B3_FFFF Reserved 64KB
30B2_0000 30B2_FFFF Reserved 64KB
30B1_0000 30B1_FFFF Reserved 64KB
30B0_0000 30B0_FFFF Reserved 64KB
30AF_0000 30AF_FFFF Reserved 64KB
30AE_0000 30AE_FFFF I2C6 64KB
30AD_0000 30AD_FFFF I2C5 64KB
30AC_0000 30AC_FFFF SEMAPHORE_HS 64KB
30AB_0000 30AB_FFFF MU_1_B (A53, M7) 64KB
30AA_0000 30AA_FFFF MU_1_A (A53,M7) 64KB
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32 NXP Semiconductors
Chapter 2 Memory Map
Table 2-5. AIPS3 Memory Map (continued)
Start Address End Address Region NIC Port Size
30A9_0000 30A9_FFFF Reserved 64KB
30A8_0000 30A8_FFFF IRQ_STEER (Audio 64KB
Processor)
30A7_0000 30A7_FFFF Reserved 64KB
30A6_0000 30A6_FFFF UART4 64KB
30A5_0000 30A5_FFFF I2C4 64KB
30A4_0000 30A4_FFFF I2C3 64KB
30A3_0000 30A3_FFFF I2C2 64KB
30A2_0000 30A2_FFFF I2C1 64KB
30A1_0000 30A1_FFFF Reserved 64KB
30A0_0000 30A0_FFFF Reserved 64KB
309F_0000 309F_FFFF AIPS3_Configuration 64KB
3094_0000 309E_FFFF AIPS-3 Glob. Module Reserved 704KB
Enable 1
3090_0000 3093_FFFF CAAM 256KB
308F_0000 308F_FFFF AIPS-3 (s_b_2, via SPBA1 64KB
SPBA) Glob. Module
308E_0000 308E_FFFF Reserved 64KB
Enable 0
308D_0000 308D_FFFF FlexCAN2 64KB
308C_0000 308C_FFFF FlexCAN1 64KB
308B_0000 308B_FFFF Reserved 64KB
308A_0000 308A_FFFF Reserved 64KB
3089_0000 3089_FFFF UART2 64KB
3088_0000 3088_FFFF UART3 64KB
3087_0000 3087_FFFF Reserved 64KB
3086_0000 3086_FFFF UART1 64KB
3085_0000 3085_FFFF Reserved 64KB
3084_0000 3084_FFFF eCSPI3 64KB
3083_0000 3083_FFFF eCSPI2 64KB
3082_0000 3082_FFFF eCSPI1 64KB
3081_0000 3081_FFFF Reserved 64KB
3080_0000 3080_FFFF Reserved 64KB
Table 2-6. AIPS4 Memory Map
Start Address End Address Region NIC Port Size
32FF_0000 32FF_FFFF AIPS-4 (s_h_10) Reserved 64KB
32FE_0000 32FE_FFFF Reserved 64KB
32FD_0000 32FD_FFFF HDMI_TX 64KB
32FC_0000 32FC_FFFF 64KB
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NXP Semiconductors 33
AIPS Memory Maps
Table 2-6. AIPS4 Memory Map (continued)
Start Address End Address Region NIC Port Size
See HDMI_TX
Subsystem Memory
Map for more
information.
32FB_0000 32FB_FFFF Reserved 64KB
32FA_0000 32FA_FFFF Reserved 64KB
32F9_0000 32F9_FFFF Reserved 64KB
32F8_0000 32F8_FFFF TZASC 64KB
32F7_0000 32F7_FFFF Reserved 64KB
32F6_0000 32F6_FFFF Reserved 64KB
32F5_0000 32F5_FFFF Reserved 64KB
32F4_0000 32F4_FFFF Reserved 64KB
32F3_0000 32F3_FFFF Reserved 64KB
32F2_0000 32F2_FFFF Reserved 64KB
32F1_0000 32F1_FFFF HSIO BLK_CTL 64KB
32F0_0000 32F0_FFFF PCIE_PHY1 64KB
32EF_0000 32EF_FFFF Reserved 64KB
32EE_0000 32EE_FFFF Reserved 64KB
32ED_0000 32ED_FFFF Reserved 64KB
32EC_0000 32EC_FFFF MEDIA BLK_CTL 64KB
32EB_0000 32EB_FFFF Reserved 64KB
32EA_0000 32EA_FFFF Reserved 64KB
32E9_0000 32E9_FFFF LCDIF2 64KB
32E8_0000 32E8_FFFF LCDIF1 64KB
32E7_0000 32E7_FFFF Reserved 64KB
32E6_0000 32E6_FFFF MIPI_DSI1 64KB
32E5_0000 32E5_FFFF MIPI_CSI2 64KB
32E4_0000 32E4_FFFF MIPI_CSI1 64KB
32E3_0000 32E3_FFFF IPS Dewarp 64KB
32E2_0000 32E2_FFFF ISP2 64KB
32E1_0000 32E1_FFFF ISP1 64KB
32E0_0000 32E0_FFFF ISI 64KB
32DF_0000 32DF_FFFF AIPS4_configuration 64KB
32D0_0000 32DE_FFFF AIPS-4 Glob. Module Reserved 960KB
Enable
32C0_0000 32CF_FFFF Reserved 1024KB
Table 2-7. AIPS5 Memory Map
Start Address End Address Region NIC Port Size
30FF_0000 30FF_FFFF AIPS-5 Reserved 64KB
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34 NXP Semiconductors
Chapter 2 Memory Map
Table 2-7. AIPS5 Memory Map (continued)
Start Address End Address Region NIC Port Size
30FE_0000 30FE_FFFF Reserved 64KB
30FD_0000 30FD_FFFF Reserved 64KB
30FC_0000 30FC_FFFF Reserved 64KB
30FB_0000 30FB_FFFF Reserved 64KB
30FA_0000 30FA_FFFF Reserved 64KB
30F9_0000 30F9_FFFF Reserved 64KB
30F8_0000 30F8_FFFF Reserved 64KB
30F7_0000 30F7_FFFF Reserved 64KB
30F6_0000 30F6_FFFF Reserved 64KB
30F5_0000 30F5_FFFF Reserved 64KB
30F4_0000 30F4_FFFF Reserved 64KB
30F3_0000 30F3_FFFF Reserved 64KB
30F2_0000 30F2_FFFF Reserved 64KB
30F1_0000 30F1_FFFF Reserved 64KB
30F0_0000 30F0_FFFF Reserved 64KB
30EF_0000 30EF_FFFF Reserved 64KB
30EE_0000 30EE_FFFF Reserved 64KB
30ED_0000 30ED_FFFF Reserved 64KB
30EC_0000 30EC_FFFF Reserved 64KB
30EB_0000 30EB_FFFF Reserved 64KB
30EA_0000 30EA_FFFF Reserved 64KB
30E9_0000 30E9_FFFF MU_3_B (M7, Audio 64KB
Processor)
30E8_0000 30E8_FFFF MU_3_A (M7, Audio 64KB
Processor)
30E7_0000 30E7_FFFF MU_2_B (A53, Audio 64KB
Processor
30E6_0000 30E6_FFFF MU_2_A (A53, Audio 64KB
Processor)
30E5_0000 30E5_FFFF eDMA Channels[31:16] 64KB
at 4KB/ch
30E4_0000 30E4_FFFF eDMA Channels[15:0] 64KB
at 4KB/ch
30E3_0000 30E3_FFFF eDMA Management 64KB
Page
30E2_0000 30E2_FFFF AUDIO BLK_CTRL 64KB
30E1_0000 30E1_FFFF SDMA2 64KB
30E0_0000 30E0_FFFF SDMA3 64KB
30DF_0000 30DF_FFFF AIPS5_Configuration 64KB
30D0_0000 30DE_FFFF AIPS-5 Glob. Module Reserved 960KB
Enable 1
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NXP Semiconductors 35
DAP Memory Map
Table 2-7. AIPS5 Memory Map (continued)
Start Address End Address Region NIC Port Size
30CF_0000 30CF_FFFF AIPS-5 (via SPBA) SPBA2 64KB
Glob. Module Enable 0
30CE_0000 30CE_FFFF Reserved 64KB
30CD_0000 30CD_FFFF Reserved 64KB
30CC_0000 30CC_FFFF AUDIO XCVR RX 64KB
(eARC)
30CB_0000 30CB_FFFF HDMI TX AUDLNK 64KB
MSTR
30CA_0000 30CA_FFFF PDM (MICFIL) 64KB
30C9_0000 30C9_FFFF ASRC 64KB
30C8_0000 30C8_FFFF SAI7 64KB
30C7_0000 30C7_FFFF Reserved 64KB
30C6_0000 30C6_FFFF SAI6 64KB
30C5_0000 30C5_FFFF SAI5 64KB
30C4_0000 30C4_FFFF Reserved 64KB
30C3_0000 30C3_FFFF SAI3 64KB
30C2_0000 30C2_FFFF SAI2 64KB
30C1_0000 30C1_FFFF SAI1 64KB
30C0_0000 30C0_FFFF Reserved 64KB
2.6 DAP Memory Map
Table 2-8. DAP Memory Map Table
Start Address End Address Size Allocation
28C0_A000 28FF_FFFF 4056KB Reserved
28C0_9000 28C0_9FFF 4KB HUGO_CXCTI1
28C0_8000 28C0_8FFF 4KB HUGO_CXCTI0
28C0_7000 28C0_7FFF 4KB CXTPIU
28C0_6000 28C0_6FFF 4KB CXTMC_ETR
28C0_5000 28C0_5FFF 4KB ATB_REPLICATOR
28C0_4000 28C0_4FFF 4KB CXTMC_ETB
28C0_3000 28C0_3FFF 4KB HUGO_ATB_FUNNEL
28C0_2000 28C0_2FFF 4KB CXTSGEN_READ
28C0_1000 28C0_1FFF 4KB CXTSGEN_CTRL
28C0_0000 28C0_0FFF 4KB HUGO ROM Table
28B5_0000 28BF_FFFF 704KB Reserved
28B4_0000 28B4_FFFF 64KB Reserved
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36 NXP Semiconductors
Chapter 2 Memory Map
Table 2-8. DAP Memory Map Table (continued)
Start Address End Address Size Allocation
28B3_0000 28B3_FFFF 64KB Reserved
28B2_0000 28B2_FFFF 64KB Reserved
28B1_0000 28B1_FFFF 64KB Reserved
28A5_0000 28B0_FFFF 768KB Reserved
28A4_0000 28A4_FFFF 64KB Reserved
28A3_0000 28A3_FFFF 64KB Reserved
28A2_0000 28A2_FFFF 64KB Reserved
28A1_0000 28A1_FFFF 64KB Reserved
2895_0000 28A0_FFFF 768KB Reserved
2894_0000 2894_FFFF 64KB Reserved
2893_0000 2893_FFFF 64KB Reserved
2892_0000 2892_FFFF 64KB Reserved
2891_0000 2891_FFFF 64KB Reserved
2885_0000 2890_FFFF 768KB Reserved
2884_0000 2884_FFFF 64KB Reserved
2883_0000 2883_FFFF 64KB Reserved
2882_0000 2882_FFFF 64KB Reserved
2881_0000 2881_FFFF 64KB Reserved
2880_0000 2880_FFFF 64KB Audio Processor Debug
2875_0000 287F_FFFF 704KB Reserved
2874_0000 2874_FFFF 64KB MP4-CPU3 Trace
2873_0000 2873_FFFF 64KB MP4-CPU3 PMU
2872_0000 2872_FFFF 64KB MP4-CPU3 CTI
2871_0000 2871_FFFF 64KB MP4-CPU3 Debug
2865_0000 2870_FFFF 768KB Reserved
2864_0000 2864_FFFF 64KB MP4-CPU2 Trace
2863_0000 2863_FFFF 64KB MP4-CPU2 PMU
2862_0000 2862_FFFF 64KB MP4-CPU2 CTI
2861_0000 2861_FFFF 64KB MP4-CPU2 Debug
2855_0000 2860_FFFF 768KB Reserved
2854_0000 2854_FFFF 64KB MP4-CPU1 Trace
2853_0000 2853_FFFF 64KB MP4-CPU1 PMU
2852_0000 2852_FFFF 64KB MP4-CPU1 CTI
2851_0000 2851_FFFF 64KB MP4-CPU1 Debug
2845_0000 2850_FFFF 768KB Reserved
2844_0000 2844_FFFF 64KB MP4-CPU0 Trace
2843_0000 2843_FFFF 64KB MP4-CPU0 PMU
2842_0000 2842_FFFF 64KB MP4-CPU0 CTI
2841_0000 2841_FFFF 64KB MP4-CPU0 Debug
Table continues on the next page...
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Audio Processor Memory Map
Table 2-8. DAP Memory Map Table (continued)
Start Address End Address Size Allocation
2840_0000 2840_FFFF 64KB MP4 ROM Table
2801_0000 283F_FFFF 4032KB Reserved
2800_0000 2800_FFFF 64KB DAP ROM Table
2.7 Audio Processor Memory Map
This section includes the Audio Processor Memory Map portion of the System Memory
Map.
Table 2-9. Audio Processor Memory Map
Start Address End Address Size Allocation
3B77_0000 3BFF_FFFF 8768KB Reserved
3B74_0000 3B76_FFFF 192KB Reserved
3B70_0000 3B73_FFFF 256KB Audio Processor System RAM (OCRAM_A)
3B6F_8800 3B6F_FFFF 30KB Reserved
3B6F_8000 3B6F_87FF 2KB Audio Processor Local Memory (Instr Ram0)
3B6F_0000 3B6F_7FFF 32KB Audio Processor Local Memory (Data Ram1)
3B6E_8000 3B6E_FFFF 32KB Audio Processor Local Memory (Data Ram0)
3B00_0000 3B6E_7FFF 7072KB Reserved
2.8 HDMI_TX Subsystem Memory Map
The HDMI_TX subsystem address space is configured as shown in the table below.
Table 2-10. HDMI_TX Subsystem Memory Map
Start Address End Address Region Size Description
32FD_8000 32FD_FFFF HDMI TX Controller & 32KB 0xFF00-0xFFFF - HDMI TX PHY
PHY
0x8000-0xFE31 - HDMI TX Controller
32FD_4000 32FD_7FFF Reserved 16KB Reserved
32FD_3000 32FD_3FFF HDMI TX TRNG 4KB HDMI TX TRNG
32FD_2000 32FD_2FFF Reserved 4KB Reserved
32FD_1000 32FD_1FFF Reserved 4KB Reserved
32FD_0000 32FD_0FFF Reserved 4KB Reserved
Table continues on the next page...
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Chapter 2 Memory Map
Table 2-10. HDMI_TX Subsystem Memory Map (continued)
Start Address End Address Region Size Description
32FC_F000 32FC_FFFF Reserved 4KB Reserved
32FC_E000 32FC_EFFF Reserved 4KB Reserved
32FC_D000 32FC_DFFF Reserved 4KB Reserved
32FC_C000 32FC_CFFF Reserved 4KB Reserved
32FC_7000 32FC_BFFF Reserved 20KB Reserved
32FC_6000 32FC_6FFF LCDIF3 4KB -
32FC_5000 32FC_5FFF Reserved 4KB Reserved
32FC_4800 32FC_4FFF BLK_CTRL 4KB HDMI TX Parallel Audio Interface (HTX_PAI)
32FC_4000 32FC_47FF 4KB HDMI TX Parallel Video Interface (HTX_PVI)
32FC_3000 32FC_3FFF Reserved 4KB Reserved
32FC_2000 32FC_2FFF IRQ_STEER 4KB -
32FC_1000 32FC_1FFF Reserved 4KB Reserved
32FC_0000 32FC_0FFF BLK_CTRL 4KB HDMI TX BLK_CTRL
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HDMI_TX Subsystem Memory Map
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Chapter 3
Security
3.1 System Security
3.1.1 Overview
The security system modules are described in the sections below.
NOTE
This chapter provides a brief overview of the security features
that are available for this chip. Please refer to the chip's
Security Reference Manual for additional details on the security
features.
3.1.2 Central Security Unit (CSU)
The chip uses the CSU to manage security for all masters/slaves that don’t directly
support security like the CPU core.
3.1.3 Cryptographic Acceleration and Assurance Module (CAAM)
CAAM is the chip's cryptographic acceleration and assurance module, which serves as
NXP's cryptographic acceleration and offloading hardware to create a modular and
scalable acceleration and assurance engine. It also implements block encryption
algorithms, stream cipher algorithms, hashing algorithms, public key algorithms, run-
time integrity checking, a secure memory controller, and a hardware random number
generator.
CAAM supports the following key features:
• PKHA block to support Public Key Cryptography with RSA 4096 and ECC
algorithms
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System Security
• 3 Job Rings
• RTIC (real time integrity checking)
• AES, DES, 3DES support
• Widevine cipher text stealing (AES-CBC-CTS mode)
• PlayReady content protection
In order to provide better video content protection, CAAM also supports the domain
based resource protection.
3.1.4 Secure Non-Volatile Storage (SNVS)
Secure Non-Volatile Storage (SNVS) is a companion logic block to the Cryptographic
Acceleration and Assurance Module (CAAM). This block is the chip's central reporting
point for security-relevant events, such as the success or failure of boot software
validation and the detection of potential security compromises. This security event
information allows the SNVS to determine whether the chip is in a trustworthy state.
3.1.5 On-Chip OTP Controller (OCOTP_CTRL)
The OCOPT_CTRL is used to control the 8K bit OTP in the chip. It supports:
• Register interface to allow SW to read, override or program the fuse.
• Flexible permission control to the fuse, including read-protect, override-protect,
program-protect, and lock.
• Programming sequence to allow single bit to be programmed individually, and also
allow the non-programmed bit to be programmed later.
For the 8K bits fuse, following bits are reserved for various IP requirements:
• Fuse control to disable each of the four Arm Cortex A53 cores.
• Fuse control to disable individual IP modules such as MIPI, ENET, USB, etc.
3.1.6 Resource Domain Controller (RDC)
The chip uses domain based resource control architecture for the memory/peripheral
resource sharing and isolation between the Quad-core Cortex A53 platform, Cortex M7
core, and other bus masters. RDC supports flexible configuration on IP’s access
permission, each individual IP can, for example, be configured as A-core only or M-core
only. RDC also supports multiple regions with flexible access permission control for each
memory space. The memory region access control is defined in the table below. The
security and exclusive support for DRAM will be done by the TZASC and the DRAM
controller itself.
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Chapter 3 Security
NOTE
The RDC and TrustZone features are completely independent
of each other but will be used together.
Table 3-1. Memory Region Access Control
Memory Space Regions Supported Granularity Security Support Exclusive Support
DEBUG (DAP) 4 regions 4K Bytes Enable -
FlexSPI 8 regions 4K Bytes Enable Disable
OCRAM 5 regions 128 Bytes Disable Enable
OCRAM_S 5 regions 128 Bytes Disable Enable
Cortex-M7 TCM 5 regions 128 Bytes Enable Disable
GIC 4 regions 4K Bytes Enable -
GPUMIX 8 regions 4K Bytes Enable -
DRAM 8 regions 4K Bytes Enabled by TZASC Enabled by NoC
DDRC (DRAM registers) 5 regions 4K Bytes Enable Disable
HSIOMIX (PCIe and USB) 8 regions 4K Bytes Enable -
VPUMIX 4 regions 4K Bytes Enable Disable
MLMIX (NPU) 4 regions 4K Bytes Enable -
Audio Processor TCM 4 regions 4K Bytes Enable Disable
OCRAM_A 5 regions 128 Bytes Disable Disable
NOTE
The Security Support column in the table indicates if the
Trustzone Secure-World attribute is supported for the
respective memory space.
3.1.7 TrustZone
TrustZone security architecture is supported in the chip. For on-chip RAM, both
OCRAM/OCRAM_S have TrustZone access control support through its TZ wrapper
logic. One region with configurable address range of the OCRAM/OCRAM_S can be set
to TZ access only. DRAM has a dedicated TZASC block that can support up to 16
configurable memory regions.
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Resource Domain Controller (RDC)
3.2 Resource Domain Controller (RDC)
3.2.1 Overview
The Resource Domain Controller (RDC) provides robust support for the isolation of
destination memory mapped locations such as peripherals and memory to a single cluster,
a bus master, or set of clusters and bus masters.
3.2.1.1 Block Diagram
Many of today's processors have multiple clusters for increased performance and
flexibility. In some cases, the clusters serve different functions (for example, user level
applications versus real time machine control) and in such cases the software for each
cluster may be developed by different providers.
Figure 3-1. Dedicated and Shared Peripherals
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Chapter 3 Security
For efficiency reasons the code on the clusters may share chip resources such as
peripherals and memory. The sharing of chip resources between the somewhat
independent processing domains allows for the opportunity of data collisions where
information stored in peripherals or memory by a process on one cluster is overwritten by
software running on another cluster. Without careful collaboration between the two
operating systems inadvertent malfunction or degradation in performance may result.
The RDC provides a mechanism to allow boot time configuration code to establish
resource domains by assigning clusters, bus masters, peripherals and memory regions to
domain identifiers. Once configured, bus transactions are monitored to restrict accesses
initiated by clusters and bus masters to their respective peripherals and memory.
For shared peripherals, the RDC provides a semaphore-based locking mechanism to
provide for temporary exclusivity while the domain software uses the peripheral. Once
the software of one domain has finished the task and finished with the peripheral then it
may release the semaphore making the peripheral available to the other domain.
3.2.1.2 Features
Resource domain subsystem has the following features:
• Assignment of clusters, bus masters, peripherals, and memory regions to a resource
domain
• Fixed memory resolution of 128 Bytes for small address spaces and 4 KB for large
address spaces
• Four resource domain identifiers (DIDs)
• Memory read/write access controls for each resource domain and region
• Optional semaphore-based, hardware-enforced exclusive access of shared peripherals
to a resource domain
• Prioritized access permissions for overlapping memory regions
• Automatic restoration of resource domain access permissions to memory regions in
the power-down domain
3.2.2 Functional Description
The RDC is the central location for creation of isolated resource domains and for the
enablement of semaphore-based access also known as “safe sharing”. Configuration
software assigns one of resource domain identifiers to each cluster and bus master, and
allocates each memory region and peripheral to one or more resource domains.
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Resource Domain Controller (RDC)
Memory Read or Write access privileges for each resource domain are declared for each
memory region. In addition, the software configuration determines which shared
peripherals (those peripherals allocated to more than one domain) require safe sharing by
setting the semaphore-required configuration for each peripheral.
The RDC configuration information is sent to the fabric ports, memories gaskets,
semaphore controller, and peripherals to control access based on domain assignments.
The fabric uses the domain identifier associated with each port to include this information
along with the bus transaction. When the slave gasket encounters a bus transaction, it
makes a comparison of the transaction domain ID to the RDC-provided list of allowed
domains. If the transaction domain ID is on the list, then access may be permitted.
DEXSC OCRAM
D0 Core
main
fabric TZASC DDRC
DEXSC
switch
D1 Core fabric
SPBA Periph
DSEC AHB Slave
switch CAAM
DEXSC Secure RAM
fabric
D0 Periph
D1 Periph
SEMA42
AIPS-TZ (Shared)
Allowed Gate
Domains Locks
RDC
(D0 TZ
Locked)
Peripheral Permissions
Memory Region Bounds
Master to Domain Assignment
Figure 3-2. Example RDC Connections
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Chapter 3 Security
For shared peripherals, RDC permits more than one domain access to a single peripheral.
RDC also provides three ways to control synchronized use of shared peripherals. These
methods include hardware-enforced synchronization, software-based semaphores, or no
synchronization. The latter may be suitable for well-tuned multi-cluster operating
systems that handle synchronization in the cluster platform, for instance.
For hardware-enforced synchronization, also known as "safe sharing", ownership of the
peripheral must be claimed in the semaphore controller before access is allowed to the
shared peripheral. Each shared peripheral has a corresponding Peripheral Domain Access
Permissions (PDAP) register. When the Semaphore Required (SREQ) bit in a PDAP
register is set, a master cannot access this shared peripheral until obtaining a semaphore.
During the time that the domain has the semaphore in possession, its bus masters have
exclusive access to the peripheral.
When the semaphore is released, then no domain masters have access until the semaphore
is obtained again. When the SREQ bit is set, RDC module does not allow masters to
obtain semaphores of peripherals to which the domain is not allocated; the master must
have designated access in the D-bits of the corresponding PDAP register (for example,
D1R bit set for Domain 1 access of the shared peripheral). There is a one-to-one mapping
between the semaphore controller gate and the resource domain controller peripheral. The
mapping of PDAP registers and peripherals can be found in the Peripheral Map section of
the RDC chapter.
3.2.2.1 Domain ID
The RDC provides for an isolation of domain resources by use of an identifier called the
Domain ID (DID). A cluster and its resources including memory, bus masters, and
peripherals are all associated with a single DID. When software or a DMA attempts to
access a peripheral or memory, the corresponding bus transaction includes the DID along
with the other bus control information such as Read, Write, and privilege mode.
3.2.2.2 Resource Assignment
The RDC allows assignment of peripherals and memories to one or more domains while
each bus master or cluster is placed in one of several domains. The masters are assigned a
domain in the Master Domain Assignment (MDA) register. A peripheral is given R/W
access permissions to each domain in the PDAP register. Memory regions are bound by
address space in start and end registers, i.e. MRSA and MREA. Each memory region is
assigned one or more allowed domains and R/W permissions in the Memory Region
Control (MRC) register. Memory regions must be enabled before the permissions are
active. Otherwise the permissions are not restricted.
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Resource Domain Controller (RDC)
The RDC itself should be isolated to ensure that only a trustworthy resource manager can
configure the RDC registers. This process may either be present initially during secure
boot, or during the runtime in the secure world, for example. If the operating system does
not support a runtime trusted execution, then during the secure boot process the RDC
configuration can be locked to prevent further modification after the operating systems
are running.
NOTE
The CCM supports multi-cluster awareness based on resource
domain assignments programmed into the RDC. Refer to the
CCM chapter regarding the relationship between cluster
resource domains and their respective CCM resources. Failing
to follow the proper sequence when updating the resource
domain assignments of the cluster can result in clocks being
inadvertently gated.
3.2.2.3 Safe Sharing
For shared peripherals, the RDC can be configured to require a domain to obtain a
semaphore lock before access to the peripheral is allowed. This feature helps prevent
collisions from processes on separate clusters that may want to use the same peripheral at
the same time. The RDC sends a list of eligible domains to the semaphore module for
each gate/peripheral. The eligible domains are those that are set in the peripheral domain
access permissions (PDAP) registers. There is a one-to-one correspondence between
semaphore gates and peripherals so each gate in the semaphore block represents a
peripheral. The RDC receives semaphore locks from the hardware semaphore module
(SEMA42). A semaphore lock is acquired when a cluster or bus master from a given
domain requests a lock for a particular gate. The semaphore module compares the
request's domain ID against the list of eligible domain IDs. If the domain ID is on the list
and the lock is available then the lock is set and a signal is sent back to the RDC module
indicating a lock has been acquired for a particular gate and a domain ID the lock belongs
to. The RDC then restricts access to the corresponding peripheral to only transactions
originating from the domain that has the lock. Another domain, though on the shared list
to access the peripheral, must then wait until the lock is released before acquiring the lock
and gaining access to the peripheral. To enable this feature of hardware enforcement for
the semaphore locks, the SREQ bit is set in the RDC resource register.
If the SREQ is set, then when a process determines it needs a shared peripheral, it must
first lock the resource in the semaphore module. Once the resource is locked, the
semaphore module sends a signal to the RDC indicating the domain has access to the
resource. The RDC will then set the access permissions to allow that domain access to the
peripheral.
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Chapter 3 Security
For a domain to acquire a lock on a peripheral, the domain must have been assigned to
the peripheral in the RDC Peripheral Domain Access Permissions register (PDAP). The
semaphore module only allows safe-sharing locks for those domains that are assigned to
the peripheral. The semaphore module does not consider the access type (Read or Write)
when allowing domains to acquire locks.
The SEMA42 module implements hardware-enforced semaphores as an IPS-mapped
slave peripheral device. The feature set includes:
• Module definition supporting 64 hardware-enforced gates in a multi-processor
configuration, where up to 15 processors can be supported; cpX is meant to represent
cluster processor X
• Gates appear as an n-entry byte-size array with read and write accesses (n = 64).
• Processors lock gates by writing "Master_index" to the appropriate gate and
must read back the gate value to verify the lock operation was successful.
The Master_index value for the processors can be found in the Master Index
Allocation table, which can be found in the AIPSTZ block. Also note that
after locking, the gate register contains the master_id value of the locking
processor (in the field GTFSM ), and also the value of the locking domain
(in the field LDOM ).
• Once locked, the gate is unlocked by a write of zeroes from the locking
processor.
• The number of implemented gates is specified by a hardware configuration
define.
• Each hardware gate appears as a 16-state, 4-bit state machine.
• 16-state implementation
if gate = 0x0, then state = unlocked
if gate = 0x1, then state = locked by processor (master_index) 0
if gate = 0x2, then state = locked by processor (master_index) 1
…
if gate = 0xF, then state = locked by processor (master_index) 14
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Resource Domain Controller (RDC)
• Uses the logical bus master number (master_index) as a reference attribute
plus the specified data patterns to validate all write operations.
• Once locked, the gate can (and must) be unlocked by a write of zeroes from
the locking processor.
• Secure reset mechanisms are supported to clear the contents of individual gates,
as well as a clear_all capability.
• Memory-mapped IPS slave peripheral platform module
• Interface to the IPS bus for programming-model accesses
3.2.2.4 Resource Domain Control and Security Considerations
Conceptually, the RDC configuration is independent of the processor privilege mode and
security domain. It is intended to allow for isolation between cluster processing
environments to prevent collisions and increase reliability. Access between resource
domains is mutually exclusive and each domain should be in control of its own privilege
modes and access rights.
However, it is important to realize multi-cluster processors may have a multiple resource
domains but only one overarching security domain. Chip security controls reside in one
resource domain. In this configuration, a domain can affect at least one level of access
privileges in the other domain. This may be acceptable but clarity and care is needed to
ensure expected functionality.
Figure 3-3. Access Control to Memory
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Chapter 3 Security
Therefore, access to the security controls should be restricted to the most trustworthy
operating mode of the cluster and privilege levels should be coordinated to ensure that
shared peripherals and memory regions are accessible by both clusters. For instance, if a
memory region is designated for secure accesses then all domain masters that share that
region must have secure privileges.
3.2.2.5 Modes of Operation
The RDC provides access controls to the resource domain subsystem. When the device is
in a low power mode then some memory regions in the subsystem may be powered off.
RDC responds to the impacted memory regions by automatically reconfiguring the
memory regions once power returns and blocking access to those memory regions until
the reconfiguration process is complete.
3.2.2.5.1 Low Power Modes
The RDC loads configuration information for memory regions (MRSA, MRSE, MRC)
into access control mechanisms (gaskets) at the memory interface. The location of this
configuration information may reside inside power domains that lose power during sleep
modes for energy savings. To restore configuration information upon return from sleep
mode, the RDC receives a global power control signal indicating power is restored. The
RDC then automatically reconfigures the memory regions with the configuration
information.
During reconfiguration, access is blocked to the previously powered down memories.
When the RDC completes reconfiguration it issues an interrupt and allows access to the
memory regions. Only the powered down regions are blocked during the reconfiguration.
Memory regions in the "always-on" power domain (still powered during sleep mode)
remain available according to the programmed access rights. If no memory regions were
enabled then the powered down regions are available immediately when power is
restored.
The figure below shows the Global Power Control signal which RDC uses to invalidate
the configuration upon deassertion and to restore the configuration when re-asserted. The
configuration is valid and bus transactions allowed once the memory regions have been
restored.
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Resource Domain Controller (RDC)
Higher Power
Memory ON
Global Power
RDC
Control
Configuration Memory Region
Invalid Restoration Interface
System Bus
Memory Regions
Higher Power
Memory
Figure 3-4. Memory Restoration Signaling
3.2.3 External Signals
RDC has no external signals pinned out.
3.2.4 Programming Interface
This section provides product specific details describing the mapping of resources -
peripherals, bus masters, and memory regions - to corresponding resource domain
controls RDC registers.
The RDC and RDC_SEMA42 register maps are combined in this chapter. The base
address for the one RDC map and two SEMA42 maps are each separated by 4KB. While
there are two SEMA42 submodules and therefore two sets of SEMA42 registers, this
chapter describes one. Please refer to the peripheral memory map for the base addresses
of the RDC and SEMA42 modules.
3.2.4.1 Master Assignment Registers
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Table 3-2. Master Assignment Mapping
Master RDC MDA Register
Arm Cortex A53 Platform RDC_MDA0
Arm Cortex M7 Platform RDC_MDA1
PCIE_CTRL1 RDC_MDA2
SDMA3(p) RDC_MDA3
SDMA3(b) RDC_MDA4
LCDIF1 RDC_MDA5
ISI RDC_MDA6
NPU RDC_MDA7
Coresight RDC_MDA8
DAP RDC_MDA9
CAAM RDC_MDA10
SDMA1(p) RDC_MDA11
SDMA1(b) RDC_MDA12
APBHDMA RDC_MDA13
RAWNAND RDC_MDA14
uSDHC1 RDC_MDA15
uSDHC2 RDC_MDA16
uSDHC3 RDC_MDA17
AUDIO PROCESSOR RDC_MDA18
USB1 RDC_MDA19
USB2 RDC_MDA20
Reserved RDC_MDA21
ENET1_TX RDC_MDA22
ENET1_RX RDC_MDA23
SDMA2(p), SDMA2(b), SDMA2 to SPBA2 RDC_MDA24
SDMA3 to SPBA2 RDC_MDA25
SDMA1 to SPBA1 RDC_MDA26
LCDIF2 RDC_MDA27
HDMI_TX RDC_MDA28
ENET2 (QoS TSN) RDC_MDA29
GPU3D RDC_MDA30
GPU2D RDC_MDA31
VPU G1 RDC_MDA32
VPU G2 RDC_MDA33
VPU VC8000E RDC_MDA34
AUDIO_EDMA RDC_MDA35
ISP1 RDC_MDA36
ISP2 RDC_MDA37
DEWARP RDC_MDA38
GIC500 RDC_MDA39
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Resource Domain Controller (RDC)
3.2.4.2 Peripheral Mapping
Each peripheral has a corresponding resource domain assignment register in the RDC and
semaphore lock register in the RDC_SEMA42 module. The following table shows
allocation of the RDC_PDAP and RDC_SEMAPHOREx_GATE registers for peripheral
resource domain assignment.
NOTE
Access control of the RDC registers can be programmed using
the respective PDAP register. The default setting of the PDAP
register for the RDC allows access from all domains. Use
caution when restricting access of the RDC registers to avoid
conditions where access to the RDC registers is needed but no
master is assigned to a domain with access rights to the RDC.
Table 3-3. RDC Peripheral Mapping
Peripheral RDC PDAP register RDC_SEMA42 block/gate register
GPIO1 RDC_PDAP00 SEMA42 B1 / G0
GPIO2 RDC_PDAP01 SEMA42 B1 / G1
GPIO3 RDC_PDAP02 SEMA42 B1 / G2
GPIO4 RDC_PDAP03 SEMA42 B1 / G3
GPIO5 RDC_PDAP04 SEMA42 B1 / G4
MU_2_A (A53, Audio Processor) RDC_PDAP05 SEMA42 B1 / G5
ANA_TSENSOR RDC_PDAP06 SEMA42 B1 / G6
ANA_OSC RDC_PDAP07 SEMA42 B1 / G7
WDOG1 RDC_PDAP08 SEMA42 B1 / G8
WDOG2 RDC_PDAP09 SEMA42 B1 / G9
WDOG3 RDC_PDAP10 SEMA42 B1 / G10
OCRAM RDC_PDAP11 SEMA42 B1 / G11
OCRAM_S RDC_PDAP12 SEMA42 B1 / G12
GPT1 RDC_PDAP13 SEMA42 B1 / G13
GPT2 RDC_PDAP14 SEMA42 B1 / G14
GPT3 RDC_PDAP15 SEMA42 B1 / G15
MU_2_B (A53, Audio Processor) RDC_PDAP16 SEMA42 B1 / G16
Reserved RDC_PDAP17 SEMA42 B1 / G17
MU_3_A (M7, Audio Processor) RDC_PDAP18 SEMA42 B1 / G18
IOMUXC RDC_PDAP19 SEMA42 B1 / G19
IOMUXC_GPR RDC_PDAP20 SEMA42 B1 / G20
Table continues on the next page...
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Chapter 3 Security
Table 3-3. RDC Peripheral Mapping (continued)
Peripheral RDC PDAP register RDC_SEMA42 block/gate register
OCOTP_CTRL RDC_PDAP21 SEMA42 B1 / G21
ANA_PLL RDC_PDAP22 SEMA42 B1 / G22
SNVS_HP RDC_PDAP23 SEMA42 B1 / G23
CCM RDC_PDAP24 SEMA42 B1 / G24
SRC RDC_PDAP25 SEMA42 B1 / G25
GPC RDC_PDAP26 SEMA42 B1 / G26
SEMAPHORE1 RDC_PDAP27 SEMA42 B1 / G27
SEMAPHORE2 RDC_PDAP28 SEMA42 B1 / G28
RDC RDC_PDAP29 SEMA42 B1 / G29
CSU RDC_PDAP30 SEMA42 B1 / G30
MU_3_B (M7, Audio Processor) RDC_PDAP31 SEMA42 B1 / G31
ISI RDC_PDAP32 SEMA42 B1 / G32
ISP1 RDC_PDAP33 SEMA42 B1 / G33
ISP2 RDC_PDAP34 SEMA42 B1 / G34
IPS Dewarp RDC_PDAP35 SEMA42 B1 / G35
MIPI_CSI1 RDC_PDAP36 SEMA42 B1 / G36
HSIOMIX BLK_CTL RDC_PDAP37 SEMA42 B1 / G37
PWM1 RDC_PDAP38 SEMA42 B1 / G38
PWM2 RDC_PDAP39 SEMA42 B1 / G39
PWM3 RDC_PDAP40 SEMA42 B1 / G40
PWM4 RDC_PDAP41 SEMA42 B1 / G41
System_Counter_RD RDC_PDAP42 SEMA42 B1 / G42
System_Counter_CMP RDC_PDAP43 SEMA42 B1 / G43
System_Counter_CTRL RDC_PDAP44 SEMA42 B1 / G44
I2C5 RDC_PDAP45 SEMA42 B1 / G45
GPT6 RDC_PDAP46 SEMA42 B1 / G46
GPT5 RDC_PDAP47 SEMA42 B1 / G47
GPT4 RDC_PDAP48 SEMA42 B1 / G48
MIPI_CSI2 RDC_PDAP49 SEMA42 B1 / G49
MIPI_DSI1 RDC_PDAP50 SEMA42 B1 / G50
MEDIAMIX BLK_CTL RDC_PDAP51 SEMA42 B1 / G51
LCDIF1 RDC_PDAP52 SEMA42 B1 / G52
eDMA Management Page RDC_PDAP53 SEMA42 B1 / G53
eDMA Channels[15:0] at 4KB/ch RDC_PDAP54 SEMA42 B1 / G54
eDMA Channels[31:16] at 4KB/ch RDC_PDAP55 SEMA42 B1 / G55
TZASC RDC_PDAP56 SEMA42 B1 / G56
I2C6 RDC_PDAP57 SEMA42 B1 / G57
CAAM RDC_PDAP58 SEMA42 B1 / G58
LCDIF2 RDC_PDAP59 SEMA42 B1 / G59
Table continues on the next page...
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NXP Semiconductors 55
Resource Domain Controller (RDC)
Table 3-3. RDC Peripheral Mapping (continued)
Peripheral RDC PDAP register RDC_SEMA42 block/gate register
PERFMON1 RDC_PDAP60 SEMA42 B1 / G60
PERFMON2 RDC_PDAP61 SEMA42 B1 / G61
NOC BLK_CTL RDC_PDAP62 SEMA42 B1 / G62
QoSC RDC_PDAP63 SEMA42 B1 / G63
LVDS1 RDC_PDAP64 SEMA42 B2 / G0
LVDS2 RDC_PDAP65 SEMA42 B2 / G1
I2C1 RDC_PDAP66 SEMA42 B2 / G2
I2C2 RDC_PDAP67 SEMA42 B2 / G3
I2C3 RDC_PDAP68 SEMA42 B2 / G4
I2C4 RDC_PDAP69 SEMA42 B2 / G5
UART4 RDC_PDAP70 SEMA42 B2 / G6
HDMI_TX RDC_PDAP71 SEMA42 B2 / G7
IRQ_STEER (Audio Processor) RDC_PDAP72 SEMA42 B2 / G8
SDMA2 RDC_PDAP73 SEMA42 B2 / G9
MU_1_A (A53,M7) RDC_PDAP74 SEMA42 B2 / G10
MU_1_B (A53, M7) RDC_PDAP75 SEMA42 B2 / G11
SEMAPHORE_HS RDC_PDAP76 SEMA42 B2 / G12
Reserved RDC_PDAP77 SEMA42 B2 / G13
SAI1 RDC_PDAP78 SEMA42 B2 / G14
SAI2 RDC_PDAP79 SEMA42 B2 / G15
SAI3 RDC_PDAP80 SEMA42 B2 / G16
CAN_FD1 RDC_PDAP81 SEMA42 B2 / G17
SAI5 RDC_PDAP82 SEMA42 B2 / G18
SAI6 RDC_PDAP83 SEMA42 B2 / G19
uSDHC1 RDC_PDAP84 SEMA42 B2 / G20
uSDHC2 RDC_PDAP85 SEMA42 B2 / G21
uSDHC3 RDC_PDAP86 SEMA42 B2 / G22
PCIE_PHY1 RDC_PDAP87 SEMA42 B2 / G23
HDMI TX AUDLNK MSTR RDC_PDAP88 SEMA42 B2 / G24
CAN_FD2 RDC_PDAP89 SEMA42 B2 / G25
SPBA2 RDC_PDAP90 SEMA42 B2 / G26
QSPI RDC_PDAP91 SEMA42 B2 / G27
AUDIO BLK_CTRL RDC_PDAP92 SEMA42 B2 / G28
SDMA1 RDC_PDAP93 SEMA42 B2 / G29
ENET1 RDC_PDAP94 SEMA42 B2 / G30
ENET2_TSN RDC_PDAP95 SEMA42 B2 / G31
Reserved RDC_PDAP96 SEMA42 B2 / G32
ASRC RDC_PDAP97 SEMA42 B2 / G33
eCSPI1 RDC_PDAP98 SEMA42 B2 / G34
Table continues on the next page...
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56 NXP Semiconductors
Chapter 3 Security
Table 3-3. RDC Peripheral Mapping (continued)
Peripheral RDC PDAP register RDC_SEMA42 block/gate register
eCSPI2 RDC_PDAP99 SEMA42 B2 / G35
eCSPI3 RDC_PDAP100 SEMA42 B2 / G36
SAI7 RDC_PDAP101 SEMA42 B2 / G37
UART1 RDC_PDAP102 SEMA42 B2 / G38
Reserved RDC_PDAP103 SEMA42 B2 / G39
UART3 RDC_PDAP104 SEMA42 B2 / G40
UART2 RDC_PDAP105 SEMA42 B2 / G41
PDM (MICFIL) RDC_PDAP106 SEMA42 B2 / G42
AUDIO XCVR RX (eARC) RDC_PDAP107 SEMA42 B2 / G43
Reserved RDC_PDAP108 SEMA42 B2 / G44
SDMA3 RDC_PDAP109 SEMA42 B2 / G45
Reserved RDC_PDAP110 SEMA42 B2 / G46
SPBA1 RDC_PDAP111 SEMA42 B2 / G47
Reserved RDC_PDAP112 SEMA42 B2 / G48
3.2.4.3 Memory Region Map
The number of memories with domain isolation support varies per device. The number of
memory regions for a particular memory and the size of those regions varies per memory
gasket. Each region of memory has a set of registers to define the boundaries of the
region based on start and end addresses, a control register to set the domain access
permissions and enable the region, and a status register to determin if access was denied
to a region.
For this device, refer to the table below to determine the memories with domain support,
the number of regions for each memory, the region resolution, the identifying numbers
for the sets of memory region registers, and the addresses of the RDC registers to access
the sets of Memory Region registers.
Table 3-4. Memory Region Mapping
Memory/Port # of Regions Region Memory Region Register Address Needs right-shift
Resolution Register Set Range by 1-bit1
Number (e.g.
MRSA, MREA,
MRC, MRVS)
DEBUG (DAP) 4 4 KB 0-3 0x800 - 0x83C Yes
FLEXSPI 8 4 KB 4 - 11 0x840 - 0x8BC No
OCRAM 5 128 B 12 - 16 0x8C0 - 0x90C Yes
OCRAM_S 5 128 B 17 - 21 0x910 - 0x95C Yes
Table continues on the next page...
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NXP Semiconductors 57
Resource Domain Controller (RDC)
Table 3-4. Memory Region Mapping (continued)
Memory/Port # of Regions Region Memory Region Register Address Needs right-shift
Resolution Register Set Range by 1-bit1
Number (e.g.
MRSA, MREA,
MRC, MRVS)
M7 TCM 5 128 B 22 - 26 0x960 - 0x9AC No
GIC 4 4 KB 27 - 30 0x9B0 - 0x9EC Yes
GPU 8 4 KB 31 - 38 0x9F0 - 0xA6C Yes
DRAM 8 4 KB 39 - 46 0xA70 - 0xAEC No
DDRC (REG) 5 4 KB 47 - 51 0xAF0 - 0xB3C Yes
PCIe1, USB1, and 8 4 KB 52 - 59 0xB40 - 0xBBC No
USB2
VPU 4 4 KB 60 - 63 0xBC0 - 0xBFC Yes
NPU 4 4 KB 64 - 67 0xC00 - 0xC3C Yes
AUDIO 4 4 KB 68 - 71 0xC40 - 0xC7C Yes
PROCESSOR
OCRAM_A 5 128 B 72 - 76 0xC80 - 0xCCC Yes
1. Whether or not the actual start/end address needs right-shift by 1-bit, then filled into MRSA and MREA.
3.2.5 RDC Memory Map/Register Definition
RDC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0000 Version Information (RDC_VIR) 32 R 04D7_2284h 3.2.5.1/72
303D_0024 Status (RDC_STAT) 32 R/W 0000_0100h 3.2.5.2/73
303D_0028 Interrupt and Control (RDC_INTCTRL) 32 R/W 0000_0000h 3.2.5.3/74
303D_002C Interrupt Status (RDC_INTSTAT) 32 R/W See section 3.2.5.4/74
303D_0200 Master Domain Assignment (RDC_MDA0) 32 R/W 0000_0000h 3.2.5.5/75
303D_0204 Master Domain Assignment (RDC_MDA1) 32 R/W 0000_0000h 3.2.5.5/75
303D_0208 Master Domain Assignment (RDC_MDA2) 32 R/W 0000_0000h 3.2.5.5/75
303D_020C Master Domain Assignment (RDC_MDA3) 32 R/W 0000_0000h 3.2.5.5/75
303D_0210 Master Domain Assignment (RDC_MDA4) 32 R/W 0000_0000h 3.2.5.5/75
303D_0214 Master Domain Assignment (RDC_MDA5) 32 R/W 0000_0000h 3.2.5.5/75
303D_0218 Master Domain Assignment (RDC_MDA6) 32 R/W 0000_0000h 3.2.5.5/75
303D_021C Master Domain Assignment (RDC_MDA7) 32 R/W 0000_0000h 3.2.5.5/75
303D_0220 Master Domain Assignment (RDC_MDA8) 32 R/W 0000_0000h 3.2.5.5/75
303D_0224 Master Domain Assignment (RDC_MDA9) 32 R/W 0000_0000h 3.2.5.5/75
303D_0228 Master Domain Assignment (RDC_MDA10) 32 R/W 0000_0000h 3.2.5.5/75
Table continues on the next page...
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58 NXP Semiconductors
Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_022C Master Domain Assignment (RDC_MDA11) 32 R/W 0000_0000h 3.2.5.5/75
303D_0230 Master Domain Assignment (RDC_MDA12) 32 R/W 0000_0000h 3.2.5.5/75
303D_0234 Master Domain Assignment (RDC_MDA13) 32 R/W 0000_0000h 3.2.5.5/75
303D_0238 Master Domain Assignment (RDC_MDA14) 32 R/W 0000_0000h 3.2.5.5/75
303D_023C Master Domain Assignment (RDC_MDA15) 32 R/W 0000_0000h 3.2.5.5/75
303D_0240 Master Domain Assignment (RDC_MDA16) 32 R/W 0000_0000h 3.2.5.5/75
303D_0244 Master Domain Assignment (RDC_MDA17) 32 R/W 0000_0000h 3.2.5.5/75
303D_0248 Master Domain Assignment (RDC_MDA18) 32 R/W 0000_0000h 3.2.5.5/75
303D_024C Master Domain Assignment (RDC_MDA19) 32 R/W 0000_0000h 3.2.5.5/75
303D_0250 Master Domain Assignment (RDC_MDA20) 32 R/W 0000_0000h 3.2.5.5/75
303D_0254 Master Domain Assignment (RDC_MDA21) 32 R/W 0000_0000h 3.2.5.5/75
303D_0258 Master Domain Assignment (RDC_MDA22) 32 R/W 0000_0000h 3.2.5.5/75
303D_025C Master Domain Assignment (RDC_MDA23) 32 R/W 0000_0000h 3.2.5.5/75
303D_0260 Master Domain Assignment (RDC_MDA24) 32 R/W 0000_0000h 3.2.5.5/75
303D_0264 Master Domain Assignment (RDC_MDA25) 32 R/W 0000_0000h 3.2.5.5/75
303D_0268 Master Domain Assignment (RDC_MDA26) 32 R/W 0000_0000h 3.2.5.5/75
303D_026C Master Domain Assignment (RDC_MDA27) 32 R/W 0000_0000h 3.2.5.5/75
303D_0270 Master Domain Assignment (RDC_MDA28) 32 R/W 0000_0000h 3.2.5.5/75
303D_0274 Master Domain Assignment (RDC_MDA29) 32 R/W 0000_0000h 3.2.5.5/75
303D_0278 Master Domain Assignment (RDC_MDA30) 32 R/W 0000_0000h 3.2.5.5/75
303D_027C Master Domain Assignment (RDC_MDA31) 32 R/W 0000_0000h 3.2.5.5/75
303D_0280 Master Domain Assignment (RDC_MDA32) 32 R/W 0000_0000h 3.2.5.5/75
303D_0284 Master Domain Assignment (RDC_MDA33) 32 R/W 0000_0000h 3.2.5.5/75
303D_0288 Master Domain Assignment (RDC_MDA34) 32 R/W 0000_0000h 3.2.5.5/75
303D_028C Master Domain Assignment (RDC_MDA35) 32 R/W 0000_0000h 3.2.5.5/75
303D_0290 Master Domain Assignment (RDC_MDA36) 32 R/W 0000_0000h 3.2.5.5/75
303D_0294 Master Domain Assignment (RDC_MDA37) 32 R/W 0000_0000h 3.2.5.5/75
303D_0298 Master Domain Assignment (RDC_MDA38) 32 R/W 0000_0000h 3.2.5.5/75
303D_029C Master Domain Assignment (RDC_MDA39) 32 R/W 0000_0000h 3.2.5.5/75
303D_0400 Peripheral Domain Access Permissions (RDC_PDAP0) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0404 Peripheral Domain Access Permissions (RDC_PDAP1) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0408 Peripheral Domain Access Permissions (RDC_PDAP2) 32 R/W 0000_00FFh 3.2.5.6/76
303D_040C Peripheral Domain Access Permissions (RDC_PDAP3) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0410 Peripheral Domain Access Permissions (RDC_PDAP4) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0414 Peripheral Domain Access Permissions (RDC_PDAP5) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0418 Peripheral Domain Access Permissions (RDC_PDAP6) 32 R/W 0000_00FFh 3.2.5.6/76
303D_041C Peripheral Domain Access Permissions (RDC_PDAP7) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0420 Peripheral Domain Access Permissions (RDC_PDAP8) 32 R/W 0000_00FFh 3.2.5.6/76
Table continues on the next page...
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NXP Semiconductors 59
Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0424 Peripheral Domain Access Permissions (RDC_PDAP9) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0428 Peripheral Domain Access Permissions (RDC_PDAP10) 32 R/W 0000_00FFh 3.2.5.6/76
303D_042C Peripheral Domain Access Permissions (RDC_PDAP11) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0430 Peripheral Domain Access Permissions (RDC_PDAP12) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0434 Peripheral Domain Access Permissions (RDC_PDAP13) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0438 Peripheral Domain Access Permissions (RDC_PDAP14) 32 R/W 0000_00FFh 3.2.5.6/76
303D_043C Peripheral Domain Access Permissions (RDC_PDAP15) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0440 Peripheral Domain Access Permissions (RDC_PDAP16) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0444 Peripheral Domain Access Permissions (RDC_PDAP17) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0448 Peripheral Domain Access Permissions (RDC_PDAP18) 32 R/W 0000_00FFh 3.2.5.6/76
303D_044C Peripheral Domain Access Permissions (RDC_PDAP19) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0450 Peripheral Domain Access Permissions (RDC_PDAP20) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0454 Peripheral Domain Access Permissions (RDC_PDAP21) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0458 Peripheral Domain Access Permissions (RDC_PDAP22) 32 R/W 0000_00FFh 3.2.5.6/76
303D_045C Peripheral Domain Access Permissions (RDC_PDAP23) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0460 Peripheral Domain Access Permissions (RDC_PDAP24) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0464 Peripheral Domain Access Permissions (RDC_PDAP25) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0468 Peripheral Domain Access Permissions (RDC_PDAP26) 32 R/W 0000_00FFh 3.2.5.6/76
303D_046C Peripheral Domain Access Permissions (RDC_PDAP27) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0470 Peripheral Domain Access Permissions (RDC_PDAP28) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0474 Peripheral Domain Access Permissions (RDC_PDAP29) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0478 Peripheral Domain Access Permissions (RDC_PDAP30) 32 R/W 0000_00FFh 3.2.5.6/76
303D_047C Peripheral Domain Access Permissions (RDC_PDAP31) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0480 Peripheral Domain Access Permissions (RDC_PDAP32) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0484 Peripheral Domain Access Permissions (RDC_PDAP33) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0488 Peripheral Domain Access Permissions (RDC_PDAP34) 32 R/W 0000_00FFh 3.2.5.6/76
303D_048C Peripheral Domain Access Permissions (RDC_PDAP35) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0490 Peripheral Domain Access Permissions (RDC_PDAP36) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0494 Peripheral Domain Access Permissions (RDC_PDAP37) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0498 Peripheral Domain Access Permissions (RDC_PDAP38) 32 R/W 0000_00FFh 3.2.5.6/76
303D_049C Peripheral Domain Access Permissions (RDC_PDAP39) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04A0 Peripheral Domain Access Permissions (RDC_PDAP40) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04A4 Peripheral Domain Access Permissions (RDC_PDAP41) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04A8 Peripheral Domain Access Permissions (RDC_PDAP42) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04AC Peripheral Domain Access Permissions (RDC_PDAP43) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04B0 Peripheral Domain Access Permissions (RDC_PDAP44) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04B4 Peripheral Domain Access Permissions (RDC_PDAP45) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04B8 Peripheral Domain Access Permissions (RDC_PDAP46) 32 R/W 0000_00FFh 3.2.5.6/76
Table continues on the next page...
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60 NXP Semiconductors
Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_04BC Peripheral Domain Access Permissions (RDC_PDAP47) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04C0 Peripheral Domain Access Permissions (RDC_PDAP48) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04C4 Peripheral Domain Access Permissions (RDC_PDAP49) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04C8 Peripheral Domain Access Permissions (RDC_PDAP50) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04CC Peripheral Domain Access Permissions (RDC_PDAP51) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04D0 Peripheral Domain Access Permissions (RDC_PDAP52) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04D4 Peripheral Domain Access Permissions (RDC_PDAP53) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04D8 Peripheral Domain Access Permissions (RDC_PDAP54) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04DC Peripheral Domain Access Permissions (RDC_PDAP55) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04E0 Peripheral Domain Access Permissions (RDC_PDAP56) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04E4 Peripheral Domain Access Permissions (RDC_PDAP57) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04E8 Peripheral Domain Access Permissions (RDC_PDAP58) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04EC Peripheral Domain Access Permissions (RDC_PDAP59) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04F0 Peripheral Domain Access Permissions (RDC_PDAP60) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04F4 Peripheral Domain Access Permissions (RDC_PDAP61) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04F8 Peripheral Domain Access Permissions (RDC_PDAP62) 32 R/W 0000_00FFh 3.2.5.6/76
303D_04FC Peripheral Domain Access Permissions (RDC_PDAP63) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0500 Peripheral Domain Access Permissions (RDC_PDAP64) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0504 Peripheral Domain Access Permissions (RDC_PDAP65) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0508 Peripheral Domain Access Permissions (RDC_PDAP66) 32 R/W 0000_00FFh 3.2.5.6/76
303D_050C Peripheral Domain Access Permissions (RDC_PDAP67) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0510 Peripheral Domain Access Permissions (RDC_PDAP68) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0514 Peripheral Domain Access Permissions (RDC_PDAP69) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0518 Peripheral Domain Access Permissions (RDC_PDAP70) 32 R/W 0000_00FFh 3.2.5.6/76
303D_051C Peripheral Domain Access Permissions (RDC_PDAP71) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0520 Peripheral Domain Access Permissions (RDC_PDAP72) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0524 Peripheral Domain Access Permissions (RDC_PDAP73) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0528 Peripheral Domain Access Permissions (RDC_PDAP74) 32 R/W 0000_00FFh 3.2.5.6/76
303D_052C Peripheral Domain Access Permissions (RDC_PDAP75) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0530 Peripheral Domain Access Permissions (RDC_PDAP76) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0534 Peripheral Domain Access Permissions (RDC_PDAP77) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0538 Peripheral Domain Access Permissions (RDC_PDAP78) 32 R/W 0000_00FFh 3.2.5.6/76
303D_053C Peripheral Domain Access Permissions (RDC_PDAP79) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0540 Peripheral Domain Access Permissions (RDC_PDAP80) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0544 Peripheral Domain Access Permissions (RDC_PDAP81) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0548 Peripheral Domain Access Permissions (RDC_PDAP82) 32 R/W 0000_00FFh 3.2.5.6/76
303D_054C Peripheral Domain Access Permissions (RDC_PDAP83) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0550 Peripheral Domain Access Permissions (RDC_PDAP84) 32 R/W 0000_00FFh 3.2.5.6/76
Table continues on the next page...
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NXP Semiconductors 61
Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0554 Peripheral Domain Access Permissions (RDC_PDAP85) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0558 Peripheral Domain Access Permissions (RDC_PDAP86) 32 R/W 0000_00FFh 3.2.5.6/76
303D_055C Peripheral Domain Access Permissions (RDC_PDAP87) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0560 Peripheral Domain Access Permissions (RDC_PDAP88) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0564 Peripheral Domain Access Permissions (RDC_PDAP89) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0568 Peripheral Domain Access Permissions (RDC_PDAP90) 32 R/W 0000_00FFh 3.2.5.6/76
303D_056C Peripheral Domain Access Permissions (RDC_PDAP91) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0570 Peripheral Domain Access Permissions (RDC_PDAP92) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0574 Peripheral Domain Access Permissions (RDC_PDAP93) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0578 Peripheral Domain Access Permissions (RDC_PDAP94) 32 R/W 0000_00FFh 3.2.5.6/76
303D_057C Peripheral Domain Access Permissions (RDC_PDAP95) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0580 Peripheral Domain Access Permissions (RDC_PDAP96) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0584 Peripheral Domain Access Permissions (RDC_PDAP97) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0588 Peripheral Domain Access Permissions (RDC_PDAP98) 32 R/W 0000_00FFh 3.2.5.6/76
303D_058C Peripheral Domain Access Permissions (RDC_PDAP99) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0590 Peripheral Domain Access Permissions (RDC_PDAP100) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0594 Peripheral Domain Access Permissions (RDC_PDAP101) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0598 Peripheral Domain Access Permissions (RDC_PDAP102) 32 R/W 0000_00FFh 3.2.5.6/76
303D_059C Peripheral Domain Access Permissions (RDC_PDAP103) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05A0 Peripheral Domain Access Permissions (RDC_PDAP104) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05A4 Peripheral Domain Access Permissions (RDC_PDAP105) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05A8 Peripheral Domain Access Permissions (RDC_PDAP106) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05AC Peripheral Domain Access Permissions (RDC_PDAP107) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05B0 Peripheral Domain Access Permissions (RDC_PDAP108) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05B4 Peripheral Domain Access Permissions (RDC_PDAP109) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05B8 Peripheral Domain Access Permissions (RDC_PDAP110) 32 R/W 0000_00FFh 3.2.5.6/76
303D_05BC Peripheral Domain Access Permissions (RDC_PDAP111) 32 R/W 0000_00FFh 3.2.5.6/76
303D_0800 Memory Region Start Address (RDC_MRSA0) 32 R/W Undefined 3.2.5.7/77
303D_0804 Memory Region End Address (RDC_MREA0) 32 R/W Undefined 3.2.5.8/79
303D_0808 Memory Region Control (RDC_MRC0) 32 R/W 0000_00FFh 3.2.5.9/80
303D_080C Memory Region Violation Status (RDC_MRVS0) 32 R/W 0000_0000h 3.2.5.10/81
303D_0810 Memory Region Start Address (RDC_MRSA1) 32 R/W Undefined 3.2.5.7/77
303D_0814 Memory Region End Address (RDC_MREA1) 32 R/W Undefined 3.2.5.8/79
303D_0818 Memory Region Control (RDC_MRC1) 32 R/W 0000_00FFh 3.2.5.9/80
303D_081C Memory Region Violation Status (RDC_MRVS1) 32 R/W 0000_0000h 3.2.5.10/81
303D_0820 Memory Region Start Address (RDC_MRSA2) 32 R/W Undefined 3.2.5.7/77
303D_0824 Memory Region End Address (RDC_MREA2) 32 R/W Undefined 3.2.5.8/79
303D_0828 Memory Region Control (RDC_MRC2) 32 R/W 0000_00FFh 3.2.5.9/80
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
62 NXP Semiconductors
Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_082C Memory Region Violation Status (RDC_MRVS2) 32 R/W 0000_0000h 3.2.5.10/81
303D_0830 Memory Region Start Address (RDC_MRSA3) 32 R/W Undefined 3.2.5.7/77
303D_0834 Memory Region End Address (RDC_MREA3) 32 R/W Undefined 3.2.5.8/79
303D_0838 Memory Region Control (RDC_MRC3) 32 R/W 0000_00FFh 3.2.5.9/80
303D_083C Memory Region Violation Status (RDC_MRVS3) 32 R/W 0000_0000h 3.2.5.10/81
303D_0840 Memory Region Start Address (RDC_MRSA4) 32 R/W Undefined 3.2.5.7/77
303D_0844 Memory Region End Address (RDC_MREA4) 32 R/W Undefined 3.2.5.8/79
303D_0848 Memory Region Control (RDC_MRC4) 32 R/W 0000_00FFh 3.2.5.9/80
303D_084C Memory Region Violation Status (RDC_MRVS4) 32 R/W 0000_0000h 3.2.5.10/81
303D_0850 Memory Region Start Address (RDC_MRSA5) 32 R/W Undefined 3.2.5.7/77
303D_0854 Memory Region End Address (RDC_MREA5) 32 R/W Undefined 3.2.5.8/79
303D_0858 Memory Region Control (RDC_MRC5) 32 R/W 0000_00FFh 3.2.5.9/80
303D_085C Memory Region Violation Status (RDC_MRVS5) 32 R/W 0000_0000h 3.2.5.10/81
303D_0860 Memory Region Start Address (RDC_MRSA6) 32 R/W Undefined 3.2.5.7/77
303D_0864 Memory Region End Address (RDC_MREA6) 32 R/W Undefined 3.2.5.8/79
303D_0868 Memory Region Control (RDC_MRC6) 32 R/W 0000_00FFh 3.2.5.9/80
303D_086C Memory Region Violation Status (RDC_MRVS6) 32 R/W 0000_0000h 3.2.5.10/81
303D_0870 Memory Region Start Address (RDC_MRSA7) 32 R/W Undefined 3.2.5.7/77
303D_0874 Memory Region End Address (RDC_MREA7) 32 R/W Undefined 3.2.5.8/79
303D_0878 Memory Region Control (RDC_MRC7) 32 R/W 0000_00FFh 3.2.5.9/80
303D_087C Memory Region Violation Status (RDC_MRVS7) 32 R/W 0000_0000h 3.2.5.10/81
303D_0880 Memory Region Start Address (RDC_MRSA8) 32 R/W Undefined 3.2.5.7/77
303D_0884 Memory Region End Address (RDC_MREA8) 32 R/W Undefined 3.2.5.8/79
303D_0888 Memory Region Control (RDC_MRC8) 32 R/W 0000_00FFh 3.2.5.9/80
303D_088C Memory Region Violation Status (RDC_MRVS8) 32 R/W 0000_0000h 3.2.5.10/81
303D_0890 Memory Region Start Address (RDC_MRSA9) 32 R/W Undefined 3.2.5.7/77
303D_0894 Memory Region End Address (RDC_MREA9) 32 R/W Undefined 3.2.5.8/79
303D_0898 Memory Region Control (RDC_MRC9) 32 R/W 0000_00FFh 3.2.5.9/80
303D_089C Memory Region Violation Status (RDC_MRVS9) 32 R/W 0000_0000h 3.2.5.10/81
303D_08A0 Memory Region Start Address (RDC_MRSA10) 32 R/W Undefined 3.2.5.7/77
303D_08A4 Memory Region End Address (RDC_MREA10) 32 R/W Undefined 3.2.5.8/79
303D_08A8 Memory Region Control (RDC_MRC10) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08AC Memory Region Violation Status (RDC_MRVS10) 32 R/W 0000_0000h 3.2.5.10/81
303D_08B0 Memory Region Start Address (RDC_MRSA11) 32 R/W Undefined 3.2.5.7/77
303D_08B4 Memory Region End Address (RDC_MREA11) 32 R/W Undefined 3.2.5.8/79
303D_08B8 Memory Region Control (RDC_MRC11) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08BC Memory Region Violation Status (RDC_MRVS11) 32 R/W 0000_0000h 3.2.5.10/81
303D_08C0 Memory Region Start Address (RDC_MRSA12) 32 R/W Undefined 3.2.5.7/77
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 63
Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_08C4 Memory Region End Address (RDC_MREA12) 32 R/W Undefined 3.2.5.8/79
303D_08C8 Memory Region Control (RDC_MRC12) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08CC Memory Region Violation Status (RDC_MRVS12) 32 R/W 0000_0000h 3.2.5.10/81
303D_08D0 Memory Region Start Address (RDC_MRSA13) 32 R/W Undefined 3.2.5.7/77
303D_08D4 Memory Region End Address (RDC_MREA13) 32 R/W Undefined 3.2.5.8/79
303D_08D8 Memory Region Control (RDC_MRC13) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08DC Memory Region Violation Status (RDC_MRVS13) 32 R/W 0000_0000h 3.2.5.10/81
303D_08E0 Memory Region Start Address (RDC_MRSA14) 32 R/W Undefined 3.2.5.7/77
303D_08E4 Memory Region End Address (RDC_MREA14) 32 R/W Undefined 3.2.5.8/79
303D_08E8 Memory Region Control (RDC_MRC14) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08EC Memory Region Violation Status (RDC_MRVS14) 32 R/W 0000_0000h 3.2.5.10/81
303D_08F0 Memory Region Start Address (RDC_MRSA15) 32 R/W Undefined 3.2.5.7/77
303D_08F4 Memory Region End Address (RDC_MREA15) 32 R/W Undefined 3.2.5.8/79
303D_08F8 Memory Region Control (RDC_MRC15) 32 R/W 0000_00FFh 3.2.5.9/80
303D_08FC Memory Region Violation Status (RDC_MRVS15) 32 R/W 0000_0000h 3.2.5.10/81
303D_0900 Memory Region Start Address (RDC_MRSA16) 32 R/W Undefined 3.2.5.7/77
303D_0904 Memory Region End Address (RDC_MREA16) 32 R/W Undefined 3.2.5.8/79
303D_0908 Memory Region Control (RDC_MRC16) 32 R/W 0000_00FFh 3.2.5.9/80
303D_090C Memory Region Violation Status (RDC_MRVS16) 32 R/W 0000_0000h 3.2.5.10/81
303D_0910 Memory Region Start Address (RDC_MRSA17) 32 R/W Undefined 3.2.5.7/77
303D_0914 Memory Region End Address (RDC_MREA17) 32 R/W Undefined 3.2.5.8/79
303D_0918 Memory Region Control (RDC_MRC17) 32 R/W 0000_00FFh 3.2.5.9/80
303D_091C Memory Region Violation Status (RDC_MRVS17) 32 R/W 0000_0000h 3.2.5.10/81
303D_0920 Memory Region Start Address (RDC_MRSA18) 32 R/W Undefined 3.2.5.7/77
303D_0924 Memory Region End Address (RDC_MREA18) 32 R/W Undefined 3.2.5.8/79
303D_0928 Memory Region Control (RDC_MRC18) 32 R/W 0000_00FFh 3.2.5.9/80
303D_092C Memory Region Violation Status (RDC_MRVS18) 32 R/W 0000_0000h 3.2.5.10/81
303D_0930 Memory Region Start Address (RDC_MRSA19) 32 R/W Undefined 3.2.5.7/77
303D_0934 Memory Region End Address (RDC_MREA19) 32 R/W Undefined 3.2.5.8/79
303D_0938 Memory Region Control (RDC_MRC19) 32 R/W 0000_00FFh 3.2.5.9/80
303D_093C Memory Region Violation Status (RDC_MRVS19) 32 R/W 0000_0000h 3.2.5.10/81
303D_0940 Memory Region Start Address (RDC_MRSA20) 32 R/W Undefined 3.2.5.7/77
303D_0944 Memory Region End Address (RDC_MREA20) 32 R/W Undefined 3.2.5.8/79
303D_0948 Memory Region Control (RDC_MRC20) 32 R/W 0000_00FFh 3.2.5.9/80
303D_094C Memory Region Violation Status (RDC_MRVS20) 32 R/W 0000_0000h 3.2.5.10/81
303D_0950 Memory Region Start Address (RDC_MRSA21) 32 R/W Undefined 3.2.5.7/77
303D_0954 Memory Region End Address (RDC_MREA21) 32 R/W Undefined 3.2.5.8/79
303D_0958 Memory Region Control (RDC_MRC21) 32 R/W 0000_00FFh 3.2.5.9/80
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
64 NXP Semiconductors
Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_095C Memory Region Violation Status (RDC_MRVS21) 32 R/W 0000_0000h 3.2.5.10/81
303D_0960 Memory Region Start Address (RDC_MRSA22) 32 R/W Undefined 3.2.5.7/77
303D_0964 Memory Region End Address (RDC_MREA22) 32 R/W Undefined 3.2.5.8/79
303D_0968 Memory Region Control (RDC_MRC22) 32 R/W 0000_00FFh 3.2.5.9/80
303D_096C Memory Region Violation Status (RDC_MRVS22) 32 R/W 0000_0000h 3.2.5.10/81
303D_0970 Memory Region Start Address (RDC_MRSA23) 32 R/W Undefined 3.2.5.7/77
303D_0974 Memory Region End Address (RDC_MREA23) 32 R/W Undefined 3.2.5.8/79
303D_0978 Memory Region Control (RDC_MRC23) 32 R/W 0000_00FFh 3.2.5.9/80
303D_097C Memory Region Violation Status (RDC_MRVS23) 32 R/W 0000_0000h 3.2.5.10/81
303D_0980 Memory Region Start Address (RDC_MRSA24) 32 R/W Undefined 3.2.5.7/77
303D_0984 Memory Region End Address (RDC_MREA24) 32 R/W Undefined 3.2.5.8/79
303D_0988 Memory Region Control (RDC_MRC24) 32 R/W 0000_00FFh 3.2.5.9/80
303D_098C Memory Region Violation Status (RDC_MRVS24) 32 R/W 0000_0000h 3.2.5.10/81
303D_0990 Memory Region Start Address (RDC_MRSA25) 32 R/W Undefined 3.2.5.7/77
303D_0994 Memory Region End Address (RDC_MREA25) 32 R/W Undefined 3.2.5.8/79
303D_0998 Memory Region Control (RDC_MRC25) 32 R/W 0000_00FFh 3.2.5.9/80
303D_099C Memory Region Violation Status (RDC_MRVS25) 32 R/W 0000_0000h 3.2.5.10/81
303D_09A0 Memory Region Start Address (RDC_MRSA26) 32 R/W Undefined 3.2.5.7/77
303D_09A4 Memory Region End Address (RDC_MREA26) 32 R/W Undefined 3.2.5.8/79
303D_09A8 Memory Region Control (RDC_MRC26) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09AC Memory Region Violation Status (RDC_MRVS26) 32 R/W 0000_0000h 3.2.5.10/81
303D_09B0 Memory Region Start Address (RDC_MRSA27) 32 R/W Undefined 3.2.5.7/77
303D_09B4 Memory Region End Address (RDC_MREA27) 32 R/W Undefined 3.2.5.8/79
303D_09B8 Memory Region Control (RDC_MRC27) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09BC Memory Region Violation Status (RDC_MRVS27) 32 R/W 0000_0000h 3.2.5.10/81
303D_09C0 Memory Region Start Address (RDC_MRSA28) 32 R/W Undefined 3.2.5.7/77
303D_09C4 Memory Region End Address (RDC_MREA28) 32 R/W Undefined 3.2.5.8/79
303D_09C8 Memory Region Control (RDC_MRC28) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09CC Memory Region Violation Status (RDC_MRVS28) 32 R/W 0000_0000h 3.2.5.10/81
303D_09D0 Memory Region Start Address (RDC_MRSA29) 32 R/W Undefined 3.2.5.7/77
303D_09D4 Memory Region End Address (RDC_MREA29) 32 R/W Undefined 3.2.5.8/79
303D_09D8 Memory Region Control (RDC_MRC29) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09DC Memory Region Violation Status (RDC_MRVS29) 32 R/W 0000_0000h 3.2.5.10/81
303D_09E0 Memory Region Start Address (RDC_MRSA30) 32 R/W Undefined 3.2.5.7/77
303D_09E4 Memory Region End Address (RDC_MREA30) 32 R/W Undefined 3.2.5.8/79
303D_09E8 Memory Region Control (RDC_MRC30) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09EC Memory Region Violation Status (RDC_MRVS30) 32 R/W 0000_0000h 3.2.5.10/81
303D_09F0 Memory Region Start Address (RDC_MRSA31) 32 R/W Undefined 3.2.5.7/77
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 65
Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_09F4 Memory Region End Address (RDC_MREA31) 32 R/W Undefined 3.2.5.8/79
303D_09F8 Memory Region Control (RDC_MRC31) 32 R/W 0000_00FFh 3.2.5.9/80
303D_09FC Memory Region Violation Status (RDC_MRVS31) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A00 Memory Region Start Address (RDC_MRSA32) 32 R/W Undefined 3.2.5.7/77
303D_0A04 Memory Region End Address (RDC_MREA32) 32 R/W Undefined 3.2.5.8/79
303D_0A08 Memory Region Control (RDC_MRC32) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A0C Memory Region Violation Status (RDC_MRVS32) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A10 Memory Region Start Address (RDC_MRSA33) 32 R/W Undefined 3.2.5.7/77
303D_0A14 Memory Region End Address (RDC_MREA33) 32 R/W Undefined 3.2.5.8/79
303D_0A18 Memory Region Control (RDC_MRC33) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A1C Memory Region Violation Status (RDC_MRVS33) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A20 Memory Region Start Address (RDC_MRSA34) 32 R/W Undefined 3.2.5.7/77
303D_0A24 Memory Region End Address (RDC_MREA34) 32 R/W Undefined 3.2.5.8/79
303D_0A28 Memory Region Control (RDC_MRC34) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A2C Memory Region Violation Status (RDC_MRVS34) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A30 Memory Region Start Address (RDC_MRSA35) 32 R/W Undefined 3.2.5.7/77
303D_0A34 Memory Region End Address (RDC_MREA35) 32 R/W Undefined 3.2.5.8/79
303D_0A38 Memory Region Control (RDC_MRC35) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A3C Memory Region Violation Status (RDC_MRVS35) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A40 Memory Region Start Address (RDC_MRSA36) 32 R/W Undefined 3.2.5.7/77
303D_0A44 Memory Region End Address (RDC_MREA36) 32 R/W Undefined 3.2.5.8/79
303D_0A48 Memory Region Control (RDC_MRC36) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A4C Memory Region Violation Status (RDC_MRVS36) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A50 Memory Region Start Address (RDC_MRSA37) 32 R/W Undefined 3.2.5.7/77
303D_0A54 Memory Region End Address (RDC_MREA37) 32 R/W Undefined 3.2.5.8/79
303D_0A58 Memory Region Control (RDC_MRC37) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A5C Memory Region Violation Status (RDC_MRVS37) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A60 Memory Region Start Address (RDC_MRSA38) 32 R/W Undefined 3.2.5.7/77
303D_0A64 Memory Region End Address (RDC_MREA38) 32 R/W Undefined 3.2.5.8/79
303D_0A68 Memory Region Control (RDC_MRC38) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A6C Memory Region Violation Status (RDC_MRVS38) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A70 Memory Region Start Address (RDC_MRSA39) 32 R/W Undefined 3.2.5.7/77
303D_0A74 Memory Region End Address (RDC_MREA39) 32 R/W Undefined 3.2.5.8/79
303D_0A78 Memory Region Control (RDC_MRC39) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A7C Memory Region Violation Status (RDC_MRVS39) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A80 Memory Region Start Address (RDC_MRSA40) 32 R/W Undefined 3.2.5.7/77
303D_0A84 Memory Region End Address (RDC_MREA40) 32 R/W Undefined 3.2.5.8/79
303D_0A88 Memory Region Control (RDC_MRC40) 32 R/W 0000_00FFh 3.2.5.9/80
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
66 NXP Semiconductors
Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0A8C Memory Region Violation Status (RDC_MRVS40) 32 R/W 0000_0000h 3.2.5.10/81
303D_0A90 Memory Region Start Address (RDC_MRSA41) 32 R/W Undefined 3.2.5.7/77
303D_0A94 Memory Region End Address (RDC_MREA41) 32 R/W Undefined 3.2.5.8/79
303D_0A98 Memory Region Control (RDC_MRC41) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0A9C Memory Region Violation Status (RDC_MRVS41) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AA0 Memory Region Start Address (RDC_MRSA42) 32 R/W Undefined 3.2.5.7/77
303D_0AA4 Memory Region End Address (RDC_MREA42) 32 R/W Undefined 3.2.5.8/79
303D_0AA8 Memory Region Control (RDC_MRC42) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0AAC Memory Region Violation Status (RDC_MRVS42) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AB0 Memory Region Start Address (RDC_MRSA43) 32 R/W Undefined 3.2.5.7/77
303D_0AB4 Memory Region End Address (RDC_MREA43) 32 R/W Undefined 3.2.5.8/79
303D_0AB8 Memory Region Control (RDC_MRC43) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0ABC Memory Region Violation Status (RDC_MRVS43) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AC0 Memory Region Start Address (RDC_MRSA44) 32 R/W Undefined 3.2.5.7/77
303D_0AC4 Memory Region End Address (RDC_MREA44) 32 R/W Undefined 3.2.5.8/79
303D_0AC8 Memory Region Control (RDC_MRC44) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0ACC Memory Region Violation Status (RDC_MRVS44) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AD0 Memory Region Start Address (RDC_MRSA45) 32 R/W Undefined 3.2.5.7/77
303D_0AD4 Memory Region End Address (RDC_MREA45) 32 R/W Undefined 3.2.5.8/79
303D_0AD8 Memory Region Control (RDC_MRC45) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0ADC Memory Region Violation Status (RDC_MRVS45) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AE0 Memory Region Start Address (RDC_MRSA46) 32 R/W Undefined 3.2.5.7/77
303D_0AE4 Memory Region End Address (RDC_MREA46) 32 R/W Undefined 3.2.5.8/79
303D_0AE8 Memory Region Control (RDC_MRC46) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0AEC Memory Region Violation Status (RDC_MRVS46) 32 R/W 0000_0000h 3.2.5.10/81
303D_0AF0 Memory Region Start Address (RDC_MRSA47) 32 R/W Undefined 3.2.5.7/77
303D_0AF4 Memory Region End Address (RDC_MREA47) 32 R/W Undefined 3.2.5.8/79
303D_0AF8 Memory Region Control (RDC_MRC47) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0AFC Memory Region Violation Status (RDC_MRVS47) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B00 Memory Region Start Address (RDC_MRSA48) 32 R/W Undefined 3.2.5.7/77
303D_0B04 Memory Region End Address (RDC_MREA48) 32 R/W Undefined 3.2.5.8/79
303D_0B08 Memory Region Control (RDC_MRC48) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B0C Memory Region Violation Status (RDC_MRVS48) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B10 Memory Region Start Address (RDC_MRSA49) 32 R/W Undefined 3.2.5.7/77
303D_0B14 Memory Region End Address (RDC_MREA49) 32 R/W Undefined 3.2.5.8/79
303D_0B18 Memory Region Control (RDC_MRC49) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B1C Memory Region Violation Status (RDC_MRVS49) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B20 Memory Region Start Address (RDC_MRSA50) 32 R/W Undefined 3.2.5.7/77
Table continues on the next page...
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NXP Semiconductors 67
Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0B24 Memory Region End Address (RDC_MREA50) 32 R/W Undefined 3.2.5.8/79
303D_0B28 Memory Region Control (RDC_MRC50) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B2C Memory Region Violation Status (RDC_MRVS50) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B30 Memory Region Start Address (RDC_MRSA51) 32 R/W Undefined 3.2.5.7/77
303D_0B34 Memory Region End Address (RDC_MREA51) 32 R/W Undefined 3.2.5.8/79
303D_0B38 Memory Region Control (RDC_MRC51) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B3C Memory Region Violation Status (RDC_MRVS51) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B40 Memory Region Start Address (RDC_MRSA52) 32 R/W Undefined 3.2.5.7/77
303D_0B44 Memory Region End Address (RDC_MREA52) 32 R/W Undefined 3.2.5.8/79
303D_0B48 Memory Region Control (RDC_MRC52) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B4C Memory Region Violation Status (RDC_MRVS52) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B50 Memory Region Start Address (RDC_MRSA53) 32 R/W Undefined 3.2.5.7/77
303D_0B54 Memory Region End Address (RDC_MREA53) 32 R/W Undefined 3.2.5.8/79
303D_0B58 Memory Region Control (RDC_MRC53) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B5C Memory Region Violation Status (RDC_MRVS53) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B60 Memory Region Start Address (RDC_MRSA54) 32 R/W Undefined 3.2.5.7/77
303D_0B64 Memory Region End Address (RDC_MREA54) 32 R/W Undefined 3.2.5.8/79
303D_0B68 Memory Region Control (RDC_MRC54) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B6C Memory Region Violation Status (RDC_MRVS54) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B70 Memory Region Start Address (RDC_MRSA55) 32 R/W Undefined 3.2.5.7/77
303D_0B74 Memory Region End Address (RDC_MREA55) 32 R/W Undefined 3.2.5.8/79
303D_0B78 Memory Region Control (RDC_MRC55) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B7C Memory Region Violation Status (RDC_MRVS55) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B80 Memory Region Start Address (RDC_MRSA56) 32 R/W Undefined 3.2.5.7/77
303D_0B84 Memory Region End Address (RDC_MREA56) 32 R/W Undefined 3.2.5.8/79
303D_0B88 Memory Region Control (RDC_MRC56) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B8C Memory Region Violation Status (RDC_MRVS56) 32 R/W 0000_0000h 3.2.5.10/81
303D_0B90 Memory Region Start Address (RDC_MRSA57) 32 R/W Undefined 3.2.5.7/77
303D_0B94 Memory Region End Address (RDC_MREA57) 32 R/W Undefined 3.2.5.8/79
303D_0B98 Memory Region Control (RDC_MRC57) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0B9C Memory Region Violation Status (RDC_MRVS57) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BA0 Memory Region Start Address (RDC_MRSA58) 32 R/W Undefined 3.2.5.7/77
303D_0BA4 Memory Region End Address (RDC_MREA58) 32 R/W Undefined 3.2.5.8/79
303D_0BA8 Memory Region Control (RDC_MRC58) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0BAC Memory Region Violation Status (RDC_MRVS58) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BB0 Memory Region Start Address (RDC_MRSA59) 32 R/W Undefined 3.2.5.7/77
303D_0BB4 Memory Region End Address (RDC_MREA59) 32 R/W Undefined 3.2.5.8/79
303D_0BB8 Memory Region Control (RDC_MRC59) 32 R/W 0000_00FFh 3.2.5.9/80
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Chapter 3 Security
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0BBC Memory Region Violation Status (RDC_MRVS59) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BC0 Memory Region Start Address (RDC_MRSA60) 32 R/W Undefined 3.2.5.7/77
303D_0BC4 Memory Region End Address (RDC_MREA60) 32 R/W Undefined 3.2.5.8/79
303D_0BC8 Memory Region Control (RDC_MRC60) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0BCC Memory Region Violation Status (RDC_MRVS60) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BD0 Memory Region Start Address (RDC_MRSA61) 32 R/W Undefined 3.2.5.7/77
303D_0BD4 Memory Region End Address (RDC_MREA61) 32 R/W Undefined 3.2.5.8/79
303D_0BD8 Memory Region Control (RDC_MRC61) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0BDC Memory Region Violation Status (RDC_MRVS61) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BE0 Memory Region Start Address (RDC_MRSA62) 32 R/W Undefined 3.2.5.7/77
303D_0BE4 Memory Region End Address (RDC_MREA62) 32 R/W Undefined 3.2.5.8/79
303D_0BE8 Memory Region Control (RDC_MRC62) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0BEC Memory Region Violation Status (RDC_MRVS62) 32 R/W 0000_0000h 3.2.5.10/81
303D_0BF0 Memory Region Start Address (RDC_MRSA63) 32 R/W Undefined 3.2.5.7/77
303D_0BF4 Memory Region End Address (RDC_MREA63) 32 R/W Undefined 3.2.5.8/79
303D_0BF8 Memory Region Control (RDC_MRC63) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0BFC Memory Region Violation Status (RDC_MRVS63) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C00 Memory Region Start Address (RDC_MRSA64) 32 R/W Undefined 3.2.5.7/77
303D_0C04 Memory Region End Address (RDC_MREA64) 32 R/W Undefined 3.2.5.8/79
303D_0C08 Memory Region Control (RDC_MRC64) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C0C Memory Region Violation Status (RDC_MRVS64) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C10 Memory Region Start Address (RDC_MRSA65) 32 R/W Undefined 3.2.5.7/77
303D_0C14 Memory Region End Address (RDC_MREA65) 32 R/W Undefined 3.2.5.8/79
303D_0C18 Memory Region Control (RDC_MRC65) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C1C Memory Region Violation Status (RDC_MRVS65) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C20 Memory Region Start Address (RDC_MRSA66) 32 R/W Undefined 3.2.5.7/77
303D_0C24 Memory Region End Address (RDC_MREA66) 32 R/W Undefined 3.2.5.8/79
303D_0C28 Memory Region Control (RDC_MRC66) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C2C Memory Region Violation Status (RDC_MRVS66) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C30 Memory Region Start Address (RDC_MRSA67) 32 R/W Undefined 3.2.5.7/77
303D_0C34 Memory Region End Address (RDC_MREA67) 32 R/W Undefined 3.2.5.8/79
303D_0C38 Memory Region Control (RDC_MRC67) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C3C Memory Region Violation Status (RDC_MRVS67) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C40 Memory Region Start Address (RDC_MRSA68) 32 R/W Undefined 3.2.5.7/77
303D_0C44 Memory Region End Address (RDC_MREA68) 32 R/W Undefined 3.2.5.8/79
303D_0C48 Memory Region Control (RDC_MRC68) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C4C Memory Region Violation Status (RDC_MRVS68) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C50 Memory Region Start Address (RDC_MRSA69) 32 R/W Undefined 3.2.5.7/77
Table continues on the next page...
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Resource Domain Controller (RDC)
RDC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303D_0C54 Memory Region End Address (RDC_MREA69) 32 R/W Undefined 3.2.5.8/79
303D_0C58 Memory Region Control (RDC_MRC69) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C5C Memory Region Violation Status (RDC_MRVS69) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C60 Memory Region Start Address (RDC_MRSA70) 32 R/W Undefined 3.2.5.7/77
303D_0C64 Memory Region End Address (RDC_MREA70) 32 R/W Undefined 3.2.5.8/79
303D_0C68 Memory Region Control (RDC_MRC70) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C6C Memory Region Violation Status (RDC_MRVS70) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C70 Memory Region Start Address (RDC_MRSA71) 32 R/W Undefined 3.2.5.7/77
303D_0C74 Memory Region End Address (RDC_MREA71) 32 R/W Undefined 3.2.5.8/79
303D_0C78 Memory Region Control (RDC_MRC71) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C7C Memory Region Violation Status (RDC_MRVS71) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C80 Memory Region Start Address (RDC_MRSA72) 32 R/W Undefined 3.2.5.7/77
303D_0C84 Memory Region End Address (RDC_MREA72) 32 R/W Undefined 3.2.5.8/79
303D_0C88 Memory Region Control (RDC_MRC72) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C8C Memory Region Violation Status (RDC_MRVS72) 32 R/W 0000_0000h 3.2.5.10/81
303D_0C90 Memory Region Start Address (RDC_MRSA73) 32 R/W Undefined 3.2.5.7/77
303D_0C94 Memory Region End Address (RDC_MREA73) 32 R/W Undefined 3.2.5.8/79
303D_0C98 Memory Region Control (RDC_MRC73) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0C9C Memory Region Violation Status (RDC_MRVS73) 32 R/W 0000_0000h 3.2.5.10/81
303D_0CA0 Memory Region Start Address (RDC_MRSA74) 32 R/W Undefined 3.2.5.7/77
303D_0CA4 Memory Region End Address (RDC_MREA74) 32 R/W Undefined 3.2.5.8/79
303D_0CA8 Memory Region Control (RDC_MRC74) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0CAC Memory Region Violation Status (RDC_MRVS74) 32 R/W 0000_0000h 3.2.5.10/81
303D_0CB0 Memory Region Start Address (RDC_MRSA75) 32 R/W Undefined 3.2.5.7/77
303D_0CB4 Memory Region End Address (RDC_MREA75) 32 R/W Undefined 3.2.5.8/79
303D_0CB8 Memory Region Control (RDC_MRC75) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0CBC Memory Region Violation Status (RDC_MRVS75) 32 R/W 0000_0000h 3.2.5.10/81
303D_0CC0 Memory Region Start Address (RDC_MRSA76) 32 R/W Undefined 3.2.5.7/77
303D_0CC4 Memory Region End Address (RDC_MREA76) 32 R/W Undefined 3.2.5.8/79
303D_0CC8 Memory Region Control (RDC_MRC76) 32 R/W 0000_00FFh 3.2.5.9/80
303D_0CCC Memory Region Violation Status (RDC_MRVS76) 32 R/W 0000_0000h 3.2.5.10/81
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Chapter 3 Security
3.2.5.1 Version Information (RDC_VIR)
The VIR provides version information including the number of domains, number of
master slots, number of peripheral slots, and number of memory regions.
Address: 303D_0000h base + 0h offset = 303D_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R NRGN NPER NMSTR NDID
Reserved
W
Reset 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0
RDC_VIR field descriptions
Field Description
31–28 This field is reserved.
Reserved
27–20 Number of Memory Regions
NRGN
Indicates the number of memory regions in this instance of the RDC.
19–12 Number of Peripherals
NPER
Indicates the number of peripherals that can be isolated or safe-shared.
11–4 Number of Masters
NMSTR
Indicates the number of masters supported by this instance of RDC.
NDID Number of Domains
Indicates the number of domain IDs supported by this instance of the RDC. For example, value '0010'
means the actual number of domains is 2.
3.2.5.2 Status (RDC_STAT)
Address: 303D_0000h base + 24h offset = 303D_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PDS Reserved DID
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
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Resource Domain Controller (RDC)
RDC_STAT field descriptions
Field Description
31–9 This field is reserved.
Reserved
8 Power Domain Status
PDS
Indicates if the "Power Down" memory regions are powered and available. Power Down memory regions
are only those memory regions susceptible to power outage for power savings are unavailable if this is
zero. "Always-On" memory regions remain available. Always On memory regions are those regions that
are not powered down unless the entire SoC is powered down. This signal remains low until all access
controls have been restored to the domain.
0 Power Down Domain is OFF
1 Power Down Domain is ON
7–4 This field is reserved.
Reserved
DID Domain ID
The Domain ID of the core or bus master that is reading this. The value is different for requests from
different domains.
3.2.5.3 Interrupt and Control (RDC_INTCTRL)
Address: 303D_0000h base + 28h offset = 303D_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCI_EN
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDC_INTCTRL field descriptions
Field Description
31–1 This field is reserved.
Reserved
0 Restoration Complete Interrupt
RCI_EN
Interrupt generated when the RDC has completed restoring state to a recently re-powered memory
regions.
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Chapter 3 Security
RDC_INTCTRL field descriptions (continued)
Field Description
0 Interrupt Disabled
1 Interrupt Enabled
3.2.5.4 Interrupt Status (RDC_INTSTAT)
Indication of Interrupt Pending for State Restoration
Address: 303D_0000h base + 2Ch offset = 303D_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INT
Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDC_INTSTAT field descriptions
Field Description
31–1 This field is reserved.
Reserved
0 Interrupt Status
INT
Indicates state of interrupt signal for state restoration. This is that status of the interrupt enabled in
RDC_INTCTRL. Write one to interrupt status to clear it.
0 No Interrupt Pending
1 Interrupt Pending
3.2.5.5 Master Domain Assignment (RDC_MDAn)
Address: 303D_0000h base + 200h offset + (4d × i), where i=0d to 39d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
LCK Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved DID
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Resource Domain Controller (RDC)
RDC_MDAn field descriptions
Field Description
31 Assignment Lock
LCK
0 Not Locked
1 Locked
30–2 This field is reserved.
Reserved
DID Domain ID
Indicates the domain to which the Master is assigned
00 Master assigned to Processing Domain 0
01 Master assigned to Processing Domain 1
10 Master assigned to Processing Domain 2
11 Master assigned to Processing Domain 3
3.2.5.6 Peripheral Domain Access Permissions (RDC_PDAPn)
Address: 303D_0000h base + 400h offset + (4d × i), where i=0d to 111d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SREQ
LCK Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved D3R D3W D2R D2W D1R D1W D0R D0W
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RDC_PDAPn field descriptions
Field Description
31 Peripheral Permissions Lock
LCK
When set prevents further modification of the Peripheral Domain Access Permissions (sticky bit until reset)
0 Not Locked
1 Locked
30 Semaphore Required
SREQ
When set the hardware semaphore state enforces the semaphore lock. If a domain has access
permissions and a semaphore has locked a shared peripheral then only the domain holding the
semaphore signal can access this peripheral.
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Chapter 3 Security
RDC_PDAPn field descriptions (continued)
Field Description
0 Semaphores have no effect
1 Semaphores are enforced
29–8 This field is reserved.
Reserved
7 Domain 3 Read Access
D3R
0 No Read Access
1 Read Access Allowed
6 Domain 3 Write Access
D3W
0 No Write Access
1 Write Access Allowed
5 Domain 2 Read Access
D2R
0 No Read Access
1 Read Access Allowed
4 Domain 2 Write Access
D2W
0 No Write Access
1 Write Access Allowed
3 Domain 1 Read Access
D1R
0 No Read Access
1 Read Access Allowed
2 Domain 1 Write Access
D1W
0 No Write Access
1 Write Access Allowed
1 Domain 0 Read Access
D0R
0 No Read Access
1 Read Access Allowed
0 Domain 0 Write Access
D0W
0 No Write Access
1 Write Access Allowed
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Resource Domain Controller (RDC)
3.2.5.7 Memory Region Start Address (RDC_MRSAn)
NOTE
The DDR space is 33-bit width. The RDC memory region
registers are 32-bit width. The RDC configuration is the most
significant bits in the DDR address space (32:1). To set the start
address for this configuration, the MRSA value should be
shifted 1-bit and added to the DDR base address. The example
below illustrates how to calculate the proper start and end
address value. Please refer to the Memory Map for the actual
DDR base address.
Start Address: 0x5000_0000
End Address: 0xAE00_0000
DDR Base Address: 0x4000_0000
Calculating MRSA value:
0x5000_0000 - 0x4000_0000 = 0x1000_0000 // Desired Start - DDR Base
0x1000_0000 / 2 = 0x800_0000 // Right-shift 1 bit
MRSA Value: 0x800_0000
Calculating MREA value:
0xAE00_0000 - 0x4000_0000 = 0x6E00_0000 // Desired End - DDR Base
0x6E00_0000 / 2 = 0x3700_0000 // Right-shift 1 bit
MREA Value: 0x3700_0000
Figure 3-5. Calculating Address Value Example
Address: 303D_0000h base + 800h offset + (16d × i), where i=0d to 76d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
SADR Reserved
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
• x = Undefined at reset.
RDC_MRSAn field descriptions
Field Description
31–7 Start address for memory region
SADR
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Chapter 3 Security
RDC_MRSAn field descriptions (continued)
Field Description
Lower bound (inclusive) modulo the defined granularity byte size of a region. The region size (granularity)
is defined for each Memory/Port in the Memory Region Map section. Region boundaries are aligned to the
minimum possible region size for the Memory/Port.
Reserved This field is reserved.
3.2.5.8 Memory Region End Address (RDC_MREAn)
NOTE
The DDR space is 33-bit width. The RDC memory region
registers are 32-bit width. The RDC configuration is the most
significant bits in the DDR address space (32:1). To set the start
address for this configuration, the MRSA value should be
shifted 1-bit and added to the DDR base address. The example
below illustrates how to calculate the proper start and end
address value. Please refer to the Memory Map for the actual
DDR base address.
Start Address: 0x5000_0000
End Address: 0xAE00_0000
DDR Base Address: 0x4000_0000
Calculating MRSA value:
0x5000_0000 - 0x4000_0000 = 0x1000_0000 // Desired Start - DDR Base
0x1000_0000 / 2 = 0x800_0000 // Right-shift 1 bit
MRSA Value: 0x800_0000
Calculating MREA value:
0xAE00_0000 - 0x4000_0000 = 0x6E00_0000 // Desired End - DDR Base
0x6E00_0000 / 2 = 0x3700_0000 // Right-shift 1 bit
MREA Value: 0x3700_0000
Figure 3-6. Calculating Address Value Example
Address: 303D_0000h base + 804h offset + (16d × i), where i=0d to 76d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EADR Reserved
Reset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
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Resource Domain Controller (RDC)
• x = Undefined at reset.
RDC_MREAn field descriptions
Field Description
31–7 Upper bound for memory region
EADR
Upper bound (exclusive) modulo the defined granularity byte size of a region. The region size (granularity)
is defined for each Memory/Port in the Memory Region Map section. Region boundaries are aligned to the
minimum possible region size for the Memory/Port.
Reserved This field is reserved.
3.2.5.9 Memory Region Control (RDC_MRCn)
Address: 303D_0000h base + 808h offset + (16d × i), where i=0d to 76d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
LCK ENA Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved D3R D3W D2R D2W D1R D1W D0R D0W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RDC_MRCn field descriptions
Field Description
31 Region Lock
LCK
Locks all region fields from further modification except ENA, which can be set but not reset after LCK is
set. LCK is a sticky bit.
0 No Lock. All fields in this register may be modified.
1 Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
30 Region Enable
ENA
Activates the memory region. If the region is not activated then the permissions and address boundaries
have not affect and the region will be fully accessible.
0 Memory region is not defined or restricted.
1 Memory boundaries, domain permissions and controls are in effect.
29–8 This field is reserved.
Reserved
7 Domain 3 Read Access to Region
D3R
0 Processing Domain 3 does not have Read access to the memory region
1 Processing Domain 3 has Read access to the memory region
6 Domain 3 Write Access to Region
D3W
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Chapter 3 Security
RDC_MRCn field descriptions (continued)
Field Description
0 Processing Domain 3 does not have Write access to the memory region
1 Processing Domain 3 has Read access to the memory region
5 Domain 2 Read Access to Region
D2R
0 Processing Domain 2 does not have Read access to the memory region
1 Processing Domain 2 has Read access to the memory region
4 Domain 2 Write Access to Region
D2W
0 Processing Domain 2 does not have Write access to the memory region
1 Processing Domain 2 has Write access to the memory region
3 Domain 1 Read Access to Region
D1R
0 Processing Domain 1 does not have Read access to the memory region
1 Processing Domain 1 has Read access to the memory region
2 Domain 1 Write Access to Region
D1W
0 Processing Domain 1 does not have Write access to the memory region
1 Processing Domain 1 has Write access to the memory region
1 Domain 0 Read Access to Region
D0R
0 Processing Domain 0 does not have Read access to the memory region
1 Processing Domain 0 has Read access to the memory region
0 Domain 0 Write Access to Region
D0W
0 Processing Domain 0 does not have Write access to the memory region
1 Processing Domain 0 has Write access to the memory region
3.2.5.10 Memory Region Violation Status (RDC_MRVSn)
Address: 303D_0000h base + 80Ch offset + (16d × i), where i=0d to 76d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R VADR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R VADR AD VDID
Reserved
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDC_MRVSn field descriptions
Field Description
31–5 Violating Address
VADR
Table continues on the next page...
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NXP Semiconductors 79
Resource Domain Controller (RDC)
RDC_MRVSn field descriptions (continued)
Field Description
The address of the denied access. The first access violation is captured. Subsequent violations are
ignored until the status register is cleared. Contents are cleared upon reading the register. Clearing of
contents occurs only when the status is read by the memory region's associated domain ID (s).
4 Access Denied
AD
Access to a memory region denied. This bit is cleared when this bit is written by one of the allowed
domains.
3–2 This field is reserved.
Reserved
VDID Violating Domain ID
The domain ID of the denied access. The first access violation is captured. Subsequent violations are
ignored until the status register is cleared. Contents are cleared upon reading the register.
00 Processing Domain 0
01 Processing Domain 1
10 Processing Domain 2
11 Processing Domain 3
3.2.6 RDC SEMA42 Memory Map/Register Definition
Only Supervisor Mode accesses are allowed on these registers. User accesses generate an
error termination.
RDC_SEMAPHORE memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_0000 Gate Register (RDC_SEMAPHORE1_GATE0) 8 R/W 00h 3.2.6.1/86
303B_0001 Gate Register (RDC_SEMAPHORE1_GATE1) 8 R/W 00h 3.2.6.1/86
303B_0002 Gate Register (RDC_SEMAPHORE1_GATE2) 8 R/W 00h 3.2.6.1/86
303B_0003 Gate Register (RDC_SEMAPHORE1_GATE3) 8 R/W 00h 3.2.6.1/86
303B_0004 Gate Register (RDC_SEMAPHORE1_GATE4) 8 R/W 00h 3.2.6.1/86
303B_0005 Gate Register (RDC_SEMAPHORE1_GATE5) 8 R/W 00h 3.2.6.1/86
303B_0006 Gate Register (RDC_SEMAPHORE1_GATE6) 8 R/W 00h 3.2.6.1/86
303B_0007 Gate Register (RDC_SEMAPHORE1_GATE7) 8 R/W 00h 3.2.6.1/86
303B_0008 Gate Register (RDC_SEMAPHORE1_GATE8) 8 R/W 00h 3.2.6.1/86
303B_0009 Gate Register (RDC_SEMAPHORE1_GATE9) 8 R/W 00h 3.2.6.1/86
303B_000A Gate Register (RDC_SEMAPHORE1_GATE10) 8 R/W 00h 3.2.6.1/86
303B_000B Gate Register (RDC_SEMAPHORE1_GATE11) 8 R/W 00h 3.2.6.1/86
Table continues on the next page...
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Chapter 3 Security
RDC_SEMAPHORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_000C Gate Register (RDC_SEMAPHORE1_GATE12) 8 R/W 00h 3.2.6.1/86
303B_000D Gate Register (RDC_SEMAPHORE1_GATE13) 8 R/W 00h 3.2.6.1/86
303B_000E Gate Register (RDC_SEMAPHORE1_GATE14) 8 R/W 00h 3.2.6.1/86
303B_000F Gate Register (RDC_SEMAPHORE1_GATE15) 8 R/W 00h 3.2.6.1/86
303B_0010 Gate Register (RDC_SEMAPHORE1_GATE16) 8 R/W 00h 3.2.6.1/86
303B_0011 Gate Register (RDC_SEMAPHORE1_GATE17) 8 R/W 00h 3.2.6.1/86
303B_0012 Gate Register (RDC_SEMAPHORE1_GATE18) 8 R/W 00h 3.2.6.1/86
303B_0013 Gate Register (RDC_SEMAPHORE1_GATE19) 8 R/W 00h 3.2.6.1/86
303B_0014 Gate Register (RDC_SEMAPHORE1_GATE20) 8 R/W 00h 3.2.6.1/86
303B_0015 Gate Register (RDC_SEMAPHORE1_GATE21) 8 R/W 00h 3.2.6.1/86
303B_0016 Gate Register (RDC_SEMAPHORE1_GATE22) 8 R/W 00h 3.2.6.1/86
303B_0017 Gate Register (RDC_SEMAPHORE1_GATE23) 8 R/W 00h 3.2.6.1/86
303B_0018 Gate Register (RDC_SEMAPHORE1_GATE24) 8 R/W 00h 3.2.6.1/86
303B_0019 Gate Register (RDC_SEMAPHORE1_GATE25) 8 R/W 00h 3.2.6.1/86
303B_001A Gate Register (RDC_SEMAPHORE1_GATE26) 8 R/W 00h 3.2.6.1/86
303B_001B Gate Register (RDC_SEMAPHORE1_GATE27) 8 R/W 00h 3.2.6.1/86
303B_001C Gate Register (RDC_SEMAPHORE1_GATE28) 8 R/W 00h 3.2.6.1/86
303B_001D Gate Register (RDC_SEMAPHORE1_GATE29) 8 R/W 00h 3.2.6.1/86
303B_001E Gate Register (RDC_SEMAPHORE1_GATE30) 8 R/W 00h 3.2.6.1/86
303B_001F Gate Register (RDC_SEMAPHORE1_GATE31) 8 R/W 00h 3.2.6.1/86
303B_0020 Gate Register (RDC_SEMAPHORE1_GATE32) 8 R/W 00h 3.2.6.1/86
303B_0021 Gate Register (RDC_SEMAPHORE1_GATE33) 8 R/W 00h 3.2.6.1/86
303B_0022 Gate Register (RDC_SEMAPHORE1_GATE34) 8 R/W 00h 3.2.6.1/86
303B_0023 Gate Register (RDC_SEMAPHORE1_GATE35) 8 R/W 00h 3.2.6.1/86
303B_0024 Gate Register (RDC_SEMAPHORE1_GATE36) 8 R/W 00h 3.2.6.1/86
303B_0025 Gate Register (RDC_SEMAPHORE1_GATE37) 8 R/W 00h 3.2.6.1/86
303B_0026 Gate Register (RDC_SEMAPHORE1_GATE38) 8 R/W 00h 3.2.6.1/86
303B_0027 Gate Register (RDC_SEMAPHORE1_GATE39) 8 R/W 00h 3.2.6.1/86
303B_0028 Gate Register (RDC_SEMAPHORE1_GATE40) 8 R/W 00h 3.2.6.1/86
303B_0029 Gate Register (RDC_SEMAPHORE1_GATE41) 8 R/W 00h 3.2.6.1/86
303B_002A Gate Register (RDC_SEMAPHORE1_GATE42) 8 R/W 00h 3.2.6.1/86
303B_002B Gate Register (RDC_SEMAPHORE1_GATE43) 8 R/W 00h 3.2.6.1/86
303B_002C Gate Register (RDC_SEMAPHORE1_GATE44) 8 R/W 00h 3.2.6.1/86
303B_002D Gate Register (RDC_SEMAPHORE1_GATE45) 8 R/W 00h 3.2.6.1/86
303B_002E Gate Register (RDC_SEMAPHORE1_GATE46) 8 R/W 00h 3.2.6.1/86
303B_002F Gate Register (RDC_SEMAPHORE1_GATE47) 8 R/W 00h 3.2.6.1/86
303B_0030 Gate Register (RDC_SEMAPHORE1_GATE48) 8 R/W 00h 3.2.6.1/86
303B_0031 Gate Register (RDC_SEMAPHORE1_GATE49) 8 R/W 00h 3.2.6.1/86
Table continues on the next page...
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NXP Semiconductors 81
Resource Domain Controller (RDC)
RDC_SEMAPHORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303B_0032 Gate Register (RDC_SEMAPHORE1_GATE50) 8 R/W 00h 3.2.6.1/86
303B_0033 Gate Register (RDC_SEMAPHORE1_GATE51) 8 R/W 00h 3.2.6.1/86
303B_0034 Gate Register (RDC_SEMAPHORE1_GATE52) 8 R/W 00h 3.2.6.1/86
303B_0035 Gate Register (RDC_SEMAPHORE1_GATE53) 8 R/W 00h 3.2.6.1/86
303B_0036 Gate Register (RDC_SEMAPHORE1_GATE54) 8 R/W 00h 3.2.6.1/86
303B_0037 Gate Register (RDC_SEMAPHORE1_GATE55) 8 R/W 00h 3.2.6.1/86
303B_0038 Gate Register (RDC_SEMAPHORE1_GATE56) 8 R/W 00h 3.2.6.1/86
303B_0039 Gate Register (RDC_SEMAPHORE1_GATE57) 8 R/W 00h 3.2.6.1/86
303B_003A Gate Register (RDC_SEMAPHORE1_GATE58) 8 R/W 00h 3.2.6.1/86
303B_003B Gate Register (RDC_SEMAPHORE1_GATE59) 8 R/W 00h 3.2.6.1/86
303B_003C Gate Register (RDC_SEMAPHORE1_GATE60) 8 R/W 00h 3.2.6.1/86
303B_003D Gate Register (RDC_SEMAPHORE1_GATE61) 8 R/W 00h 3.2.6.1/86
303B_003E Gate Register (RDC_SEMAPHORE1_GATE62) 8 R/W 00h 3.2.6.1/86
303B_003F Gate Register (RDC_SEMAPHORE1_GATE63) 8 R/W 00h 3.2.6.1/86
303B_0042 Reset Gate Write (RDC_SEMAPHORE1_RSTGT_W) 16 R/W 0000h 3.2.6.2/87
303B_0042 Reset Gate Read (RDC_SEMAPHORE1_RSTGT_R) 16 R/W 0000h 3.2.6.3/88
303C_0000 Gate Register (RDC_SEMAPHORE2_GATE0) 8 R/W 00h 3.2.6.1/86
303C_0001 Gate Register (RDC_SEMAPHORE2_GATE1) 8 R/W 00h 3.2.6.1/86
303C_0002 Gate Register (RDC_SEMAPHORE2_GATE2) 8 R/W 00h 3.2.6.1/86
303C_0003 Gate Register (RDC_SEMAPHORE2_GATE3) 8 R/W 00h 3.2.6.1/86
303C_0004 Gate Register (RDC_SEMAPHORE2_GATE4) 8 R/W 00h 3.2.6.1/86
303C_0005 Gate Register (RDC_SEMAPHORE2_GATE5) 8 R/W 00h 3.2.6.1/86
303C_0006 Gate Register (RDC_SEMAPHORE2_GATE6) 8 R/W 00h 3.2.6.1/86
303C_0007 Gate Register (RDC_SEMAPHORE2_GATE7) 8 R/W 00h 3.2.6.1/86
303C_0008 Gate Register (RDC_SEMAPHORE2_GATE8) 8 R/W 00h 3.2.6.1/86
303C_0009 Gate Register (RDC_SEMAPHORE2_GATE9) 8 R/W 00h 3.2.6.1/86
303C_000A Gate Register (RDC_SEMAPHORE2_GATE10) 8 R/W 00h 3.2.6.1/86
303C_000B Gate Register (RDC_SEMAPHORE2_GATE11) 8 R/W 00h 3.2.6.1/86
303C_000C Gate Register (RDC_SEMAPHORE2_GATE12) 8 R/W 00h 3.2.6.1/86
303C_000D Gate Register (RDC_SEMAPHORE2_GATE13) 8 R/W 00h 3.2.6.1/86
303C_000E Gate Register (RDC_SEMAPHORE2_GATE14) 8 R/W 00h 3.2.6.1/86
303C_000F Gate Register (RDC_SEMAPHORE2_GATE15) 8 R/W 00h 3.2.6.1/86
303C_0010 Gate Register (RDC_SEMAPHORE2_GATE16) 8 R/W 00h 3.2.6.1/86
303C_0011 Gate Register (RDC_SEMAPHORE2_GATE17) 8 R/W 00h 3.2.6.1/86
303C_0012 Gate Register (RDC_SEMAPHORE2_GATE18) 8 R/W 00h 3.2.6.1/86
303C_0013 Gate Register (RDC_SEMAPHORE2_GATE19) 8 R/W 00h 3.2.6.1/86
303C_0014 Gate Register (RDC_SEMAPHORE2_GATE20) 8 R/W 00h 3.2.6.1/86
303C_0015 Gate Register (RDC_SEMAPHORE2_GATE21) 8 R/W 00h 3.2.6.1/86
Table continues on the next page...
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Chapter 3 Security
RDC_SEMAPHORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303C_0016 Gate Register (RDC_SEMAPHORE2_GATE22) 8 R/W 00h 3.2.6.1/86
303C_0017 Gate Register (RDC_SEMAPHORE2_GATE23) 8 R/W 00h 3.2.6.1/86
303C_0018 Gate Register (RDC_SEMAPHORE2_GATE24) 8 R/W 00h 3.2.6.1/86
303C_0019 Gate Register (RDC_SEMAPHORE2_GATE25) 8 R/W 00h 3.2.6.1/86
303C_001A Gate Register (RDC_SEMAPHORE2_GATE26) 8 R/W 00h 3.2.6.1/86
303C_001B Gate Register (RDC_SEMAPHORE2_GATE27) 8 R/W 00h 3.2.6.1/86
303C_001C Gate Register (RDC_SEMAPHORE2_GATE28) 8 R/W 00h 3.2.6.1/86
303C_001D Gate Register (RDC_SEMAPHORE2_GATE29) 8 R/W 00h 3.2.6.1/86
303C_001E Gate Register (RDC_SEMAPHORE2_GATE30) 8 R/W 00h 3.2.6.1/86
303C_001F Gate Register (RDC_SEMAPHORE2_GATE31) 8 R/W 00h 3.2.6.1/86
303C_0020 Gate Register (RDC_SEMAPHORE2_GATE32) 8 R/W 00h 3.2.6.1/86
303C_0021 Gate Register (RDC_SEMAPHORE2_GATE33) 8 R/W 00h 3.2.6.1/86
303C_0022 Gate Register (RDC_SEMAPHORE2_GATE34) 8 R/W 00h 3.2.6.1/86
303C_0023 Gate Register (RDC_SEMAPHORE2_GATE35) 8 R/W 00h 3.2.6.1/86
303C_0024 Gate Register (RDC_SEMAPHORE2_GATE36) 8 R/W 00h 3.2.6.1/86
303C_0025 Gate Register (RDC_SEMAPHORE2_GATE37) 8 R/W 00h 3.2.6.1/86
303C_0026 Gate Register (RDC_SEMAPHORE2_GATE38) 8 R/W 00h 3.2.6.1/86
303C_0027 Gate Register (RDC_SEMAPHORE2_GATE39) 8 R/W 00h 3.2.6.1/86
303C_0028 Gate Register (RDC_SEMAPHORE2_GATE40) 8 R/W 00h 3.2.6.1/86
303C_0029 Gate Register (RDC_SEMAPHORE2_GATE41) 8 R/W 00h 3.2.6.1/86
303C_002A Gate Register (RDC_SEMAPHORE2_GATE42) 8 R/W 00h 3.2.6.1/86
303C_002B Gate Register (RDC_SEMAPHORE2_GATE43) 8 R/W 00h 3.2.6.1/86
303C_002C Gate Register (RDC_SEMAPHORE2_GATE44) 8 R/W 00h 3.2.6.1/86
303C_002D Gate Register (RDC_SEMAPHORE2_GATE45) 8 R/W 00h 3.2.6.1/86
303C_002E Gate Register (RDC_SEMAPHORE2_GATE46) 8 R/W 00h 3.2.6.1/86
303C_002F Gate Register (RDC_SEMAPHORE2_GATE47) 8 R/W 00h 3.2.6.1/86
303C_0030 Gate Register (RDC_SEMAPHORE2_GATE48) 8 R/W 00h 3.2.6.1/86
303C_0031 Gate Register (RDC_SEMAPHORE2_GATE49) 8 R/W 00h 3.2.6.1/86
303C_0032 Gate Register (RDC_SEMAPHORE2_GATE50) 8 R/W 00h 3.2.6.1/86
303C_0033 Gate Register (RDC_SEMAPHORE2_GATE51) 8 R/W 00h 3.2.6.1/86
303C_0034 Gate Register (RDC_SEMAPHORE2_GATE52) 8 R/W 00h 3.2.6.1/86
303C_0035 Gate Register (RDC_SEMAPHORE2_GATE53) 8 R/W 00h 3.2.6.1/86
303C_0036 Gate Register (RDC_SEMAPHORE2_GATE54) 8 R/W 00h 3.2.6.1/86
303C_0037 Gate Register (RDC_SEMAPHORE2_GATE55) 8 R/W 00h 3.2.6.1/86
303C_0038 Gate Register (RDC_SEMAPHORE2_GATE56) 8 R/W 00h 3.2.6.1/86
303C_0039 Gate Register (RDC_SEMAPHORE2_GATE57) 8 R/W 00h 3.2.6.1/86
303C_003A Gate Register (RDC_SEMAPHORE2_GATE58) 8 R/W 00h 3.2.6.1/86
303C_003B Gate Register (RDC_SEMAPHORE2_GATE59) 8 R/W 00h 3.2.6.1/86
Table continues on the next page...
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Resource Domain Controller (RDC)
RDC_SEMAPHORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
303C_003C Gate Register (RDC_SEMAPHORE2_GATE60) 8 R/W 00h 3.2.6.1/86
303C_003D Gate Register (RDC_SEMAPHORE2_GATE61) 8 R/W 00h 3.2.6.1/86
303C_003E Gate Register (RDC_SEMAPHORE2_GATE62) 8 R/W 00h 3.2.6.1/86
303C_003F Gate Register (RDC_SEMAPHORE2_GATE63) 8 R/W 00h 3.2.6.1/86
303C_0042 Reset Gate Write (RDC_SEMAPHORE2_RSTGT_W) 16 R/W 0000h 3.2.6.2/87
303C_0042 Reset Gate Read (RDC_SEMAPHORE2_RSTGT_R) 16 R/W 0000h 3.2.6.3/88
3.2.6.1 Gate Register (RDC_SEMAPHOREx_GATEn)
Each semaphore gate is implemented in a 4-bit finite state machine, right-justified in a
byte data structure. The hardware uses the logical bus master number (master_index) in
conjunction with the data patterns to validate all attempted write operations. Only
processor bus masters can modify the gate registers. Once locked, a gate can (and must)
be opened (unlocked) by the locking processor core.
Multiple gate values can be read in a single access, but only a single gate can be updated
via a write operation at a time. Attempted writes with a data value that is neither the
unlock value nor the appropriate lock value (master_index + 1) are simply treated as "no
operation" and do not affect any gate state. Attempts to write multiple gates in a single
aligned access with a size larger than an 8-bit (byte) reference generate an error
termination and do not allow any gate state changes. Processor dex values can be found
in AIPSTZ Memory Map/Register Definition.
Address: Base address + 0h offset + (1d × i), where i=0d to 63d
Bit 7 6 5 4 3 2 1 0
Read 0 LDOM
GTFSM
Write
Reset 0 0 0 0 0 0 0 0
RDC_SEMAPHOREx_GATEn field descriptions
Field Description
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Read-only bits. They indicate which domain had currently locked the gate.
LDOM
00 The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
01 The gate has been locked by domain 1.
10 The gate has been locked by domain 2.
11 The gate has been locked by domain 3.
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Chapter 3 Security
RDC_SEMAPHOREx_GATEn field descriptions (continued)
Field Description
GTFSM Gate Finite State Machine.
The state of the gate reflects the last processor that locked it, which can be useful during system debug.
The hardware gate is maintained in a 16-state implementation, defined as:
0000 The gate is unlocked (free).
0001 The gate has been locked by processor with master_index = 0.
0010 The gate has been locked by processor with master_index = 1.
0011 The gate has been locked by processor with master_index = 2.
0100 The gate has been locked by processor with master_index = 3.
0101 The gate has been locked by processor with master_index = 4.
0110 The gate has been locked by processor with master_index = 5.
0111 The gate has been locked by processor with master_index = 6.
1000 The gate has been locked by processor with master_index = 7.
1001 The gate has been locked by processor with master_index = 8.
1010 The gate has been locked by processor with master_index = 9.
1011 The gate has been locked by processor with master_index = 10.
1100 The gate has been locked by processor with master_index = 11.
1101 The gate has been locked by processor with master_index = 12.
1110 The gate has been locked by processor with master_index = 13.
1111 The gate has been locked by processor with master_index = 14.
3.2.6.2 Reset Gate Write (RDC_SEMAPHOREx_RSTGT_W)
Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the RDC Semaphores module implements
a "secure" reset mechanism that allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the RDC_SEMA42RSTGT memory location.
The least significant byte (RDC_SEMA42RSTGT[RSTGDP]) must be 0xE2; the
most significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the
RDC_SEMA42RSTGT location. For this write, the lower byte
(RDC_SEMA42RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the upper byte (RDC_SEMA42RSTGT[RSTGTN]) specifies the
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NXP Semiconductors 85
Resource Domain Controller (RDC)
gate(s) to be reset. This gate field can specify a single gate be cleared, or else that all
gates are to be cleared. If the same processor writes incorrect data on the second
access or another processor performs the second write access, the special gate reset
sequence is aborted and no error signal will be asserted.
3. Reads of the RDC_SEMA42RSTGT location return information on the 2-bit state
machine (RDC_SEMA42RSTGT[RSTGSM]) that implements this function, the bus
master performing the reset (RDC_SEMA42RSTGT[RSTGMS]), and the gate
number(s) last cleared (RDC_SEMA42RSTGT[RSTGTN]). Reads of the
RDC_SEMA42RSTGT register do not affect the secure reset finite state machine in
any manner.
Address: Base address + 42h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0
RSTGTN
Write RSTGDP
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDC_SEMAPHOREx_RSTGT_W field descriptions
Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates.
RSTGDP Reset Gate Data Pattern. This write-only field is accessed with the specified data patterns on the two
consecutive writes to enable the gate reset mechanism. For the first write, RSTGDP = 0xE2 while the
second write requires RSTGDP = 0x1D.
3.2.6.3 Reset Gate Read (RDC_SEMAPHOREx_RSTGT_R)
Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the RDC Semaphores module implements
a "secure" reset mechanism that allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
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1. A processor performs a 16-bit write to the RDC_SEMA42RSTGT memory location.
The least significant byte (RDC_SEMA42RSTGT[RSTGDP]) must be 0xE2; the
most significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the
RDC_SEMA42RSTGT location. For this write, the lower byte
(RDC_SEMA42RSTGT[RSTGDP]) is the logical complement of the first data
pattern (0x1D) and the upper byte (RDC_SEMA42RSTGT[RSTGTN]) specifies the
gate(s) to be reset. This gate field can specify a single gate be cleared, or else that all
gates are to be cleared. If the same processor writes incorrect data on the second
access or another processor performs the second write access, the special gate reset
sequence is aborted and no error signal will be asserted.
3. Reads of the RDC_SEMA42RSTGT location return information on the 2-bit state
machine (RDC_SEMA42RSTGT[RSTGSM]) that implements this function, the bus
master performing the reset (RDC_SEMA42RSTGT[RSTGMS]), and the gate
number(s) last cleared (RDC_SEMA42RSTGT[RSTGTN]). Reads of the
RDC_SEMA42RSTGT register do not affect the secure reset finite state machine in
any manner.
Address: Base address + 42h offset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 RSTGSM RSTGMS
RSTGTN
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RDC_SEMAPHOREx_RSTGT_R field descriptions
Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates.
7–6 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
5–4 Reset Gate Finite State Machine. Reads of the RDC_SEMA42RSTGT register return the encoded state
RSTGSM machine value. Note the RSTGSM = 10 state is valid for only a single machine cycle, so it is impossible
for a read to return this value. The reset state machine is maintained in a 2-bit, 3-state implementation,
defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is
performed, this machine returns to the idle (waiting for first data pattern write) state. The "01" state
persists for only one clock cycle. Software will never be able to observe this state.
11 This state encoding is never used and therefore reserved.
Table continues on the next page...
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Resource Domain Controller (RDC)
RDC_SEMAPHOREx_RSTGT_R field descriptions (continued)
Field Description
RSTGMS Reset Gate Bus Master. This 4-bit read-only field records the logical number of the bus master performing
the gate reset function. The reset function requires that the two consecutive writes to this register must be
initiated by the same bus master to succeed. This field is updated each time a write to this register occurs.
The association between system bus master port numbers, the associated bus master device, and the
logical processor number is SoC-specific.
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Arm Platform and Debug
4.1 Arm Cortex A53 Platform (A53)
4.1.1 Overview
The Cortex-A53 cluster is a mid-range, low-power processor that implements the
ARMv8-A architecture. The Cortex-A53 cluster has four cores, each with an L1 memory
system and a single shared L2 cache that has a set of additional functions, which are
included in a single APR region.
The core supports debug through real-time trace via ETM, and static debug via JTAG.
The core platform supports static debug through the debug logic to SoC. This includes
the capability of real-time trace via ARM's CoreSight ETM modules. The CTI and CTM
modules allow cross-triggering of internal and external trigger sources.
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Arm Cortex A53 Platform (A53)
4.1.1.1 Block Diagram
Quad A53
Cortex
Cortex A53
A53 Counter
CortexMPCore
A53
CortexMPCore
A53
MPCore
MPCore CPU0
CPU0
Timer events
CPU0
CPU0 Neon Interrupts
I$ I$
Neon
Neon
I$ 32K D$
Neon
I$ I$
I$32K32K D$
I$32K32K D$ 32K
I$ 32K D$ 32K
32K 32K
32K 32K Clocks
Resets
Snoop Control Unit
(SCU) Config
L2 Cache
(512KB) APB
ATB
CTM
AXI3 master
Interface
Figure 4-1. Cortex-A53 Block Diagram
4.1.1.2 Features
• 4x cores
• L1 instruction cache 32K
• L1 data cache 32K with SECDED
• Advanced SIMD (NEON) per core
• Crypto extension per core
• AMBA AXI3 interface
• No ACP is included
• utilizes the ARMv8 debug map
• 512KB of L2 Cache
• 512KB with Single-bit Error Correct and Double-bit Error Detect (SECDED)
• Input latency 2 cycles
• Output latency 2 cycles
• SCU-L2 cache protection
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The configuration of the bus, cores and memory are detailed in the sections below. The
core revision is CORTEXA53-r0p4-52rel0.
4.1.2 Functional Description
4.1.2.1 Platform sub-blocks
The sections below discuss the high-level overview of the ARM® Cortex®-A53 Platform
components.
4.1.2.1.1 ARM Cortex-A53 MPCore Processor
The information presented in this section focuses on the design aspects of the ARM
Cortex-A53 MPCore in the AP subsystem. The Cortex-A53 processor is a mid-range,
low-power processor that implements the ARMv8-A architecture. The A53 complex has
four cores, each with an L1 memory system and a single shared L2 cache.
The ARM Cortex-A53 MPCore processor consists of:
• Tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting
the four cores within the cluster providing cluster memory coherency, and a
configurable coherent external interface supporting AMBA4 bus architecture.
• The Cortex-A53 implements the ARM Generic Interrupt Controller v3 (GICv3)
architecture.
4.1.2.1.2 Advanced SIMD (Neon)
The Cortex-A53 processor supports the Advanced SIMD and Scalar Floating-point
instructions in the A64 instruction set, and the Advanced SIMD and VFP instructions in
the A32 and T32 instruction sets.
The ARMv8 architecture eliminates the concept of version numbers for Advanced SIMD
and Floating-point in the AArch64 execution state.
4.1.2.1.3 Generic Interrupt Controller (GIC)
The Generic Interrupt Controller (GIC) supports and manages interrupts in the cluster.
The GIC provides registers for managing:
• Interrupt sources
• Interrupt behavior
• Interrupt routing to one or more cores
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Arm Cortex A53 Platform (A53)
The Cortex-A53 processor implements the GIC CPU interface as described in the
Generic Interrupt Controller (GICv4) architecture. This interfaces with an external GICv3
or GICv4 interrupt distributor component within the system. The GICv4 architecture
supports:
• Two security states
• Interrupt virtualization
• Software-generated Interrupts (SGIs)
• Message Based Interrupts
• System register access
• Memory-mapped register access
• Interrupt masking and prioritization
• Cluster environments
• Wake-up events in power management environments
The GIC includes interrupt grouping functionality that supports:
• Signaling interrupt groups to the target core using either the IRQ or the FIQ
exception request, based on software configuration
• A unified scheme for handling the priority of Group 0 and Group 1 interrupts.
NOTE
GIC-500 supports limited backwards compatibility with GICv2.
When GIC-500 is in backwards compatibility mode, only
Cortex-A53 processors can access registers in GIC region,
while Cortex-M7 and other masters in the system, including the
Debug Access Port (DAP), can not. Cortex-A53 processors,
Cortex-M7 and DAP can access GIC region when GIC-500 is
not in backwards compatibility mode.
4.1.2.1.4 L1 Cache
The L1 instruction memory system has the following features:
• 32KB Instruction Cache
• Instruction side cache line length of 64 bytes
• 2-way set associative L1 Instruction cache
• 128-bit read interface to the L2 memory system
• 32KB Data Cache
• Data side cache line length of 64 bytes
• 4-way set associative L1 Data cache
• 256-bit write interface to the L2 memory system
• 128-bit read interface to the L2 memory system
• Read buffer that services the Data Cache Unit (DCU), the Instruction Fetch Unit
(IFU) and the TLB
• 64-bit read path from the data L1 memory system to the datapath
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• 128-bit write path from the datapath to the L1 memory system
• Support for three outstanding data cache misses
• Merging store buffer capability. This handles writes to:
• Device memory
• Normal Cacheable memory
• Normal Non-cacheable memory
• Data side prefetch engine
4.1.2.1.5 L2 Cache
The L2 cache consists of an integrated Snoop Control Unit (SCU), connecting four cores
within the A53 cluster. The SCU also has duplicate copies of the L1 Data cache tags for
coherency support. The L2 memory system interfaces to the external memory system
through an AMBA 128-bit bus. The tightly-coupled L2 cache includes the following
features:
• 1MB shared cache size
• AMBA AXI3 interface
• Fixed line length of 64 bytes
• Physically indexed and tagged cache
• 16-way set-associative cache structure
• No ACP support
• ECC/parity support
4.1.2.2 Power
There are several power states supported by the A53 Core Complex. Supported primary
states are listed below:
• Run – At least one of 4 cores is running. The other cores may either be running,
clock gated, or powered down.
• L2 only coherent – The L2 is powered up and servicing snoops. The cores are
stopped (either powered down or clock gated). In this state the cache is retained
coherent to the system.
• L2 only non-coherent – Both cores are stopped and powered down, the logic in the
L2 controller are retaining the arrays only. In this state the L2 is not coherent, and as
a result, the other AP cores must also be stopped.
• Cluster Off – The L2 has been flushed from the L2 only coherent state, using the
HW flush mechanism (no core required). Then the cluster is fully powered off
including the L2 arrays.
The power supply for the cluster is separated into two regions. The first is the control
domain and second is for the remainder of the cluster (core and cluster domains). These
regions are listed below:
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Arm Cortex A53 Platform (A53)
• Control domain – The AON control domain contains the controls for powering up
and down the rest of the core. The control domain is always powered on first and
powered off last.
• Core domains – The core domains contains the whole core. The supply for the core
domains is the same as the cluster domain, but require separate power down
switches.
• Cluster domain – The cluster domain contains the rest of the cluster outside of the
cores, which includes the shared logic of the L2 memory. The supply for the cluster
power domain is the same as the core domains, but does not require power switches
as it's shut down externally.
Isolation cells are required between each of these domains and is controlled by the signals
on the control domain. These cells are necessary to force the output signal to be isolated
to null values when the local power shuts down.
4.1.2.2.1 Power States
4.1.2.2.1.1 Cluster power up sequence
This chapter describes Cortex A53 Cluster power Up Sequence where the SCU is
controlling it. WFI wake-up events is received by the SCU through the steer controller
sitting in the DBLOG subsystem.
1. For each core in the Cluster nCPUPORESET is asserted LOW
2. Then the nL2RESET is asserted LOW and L2RSTDISABLE is hold LOW
3. The switches are forced open during voltage ramp-up
4. SCU turns on power regulator supplying Cortex-A53 cluster
5. SCU waits for power being stabilized
6. Switches are controlled by SCU through low and high fan-out chains
7. SCU reloads repair configuration of memories used for L2 Cache
8. SCU sets BIAS value according to the targeted operating point of the cluster
9. SCU locks the PLL at targeted frequency
10. SCU performs SSI-ACE power-up sequence
11. SCU disables isolation cells of the cluster
12. By SCU, ACINACTM is asserted to 0 which indicated that snoop interface is active
and participating to coherency
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13. SCU starts the lead core. Other cores are started upon request
4.1.2.2.1.2 Individual core power up sequence
The Power up sequence is controlled by SCU and the following are the steps:
1. SCU shall check internally for identifying which core shall be woken-up.
2. SCU shall check nCPUPORESET of the core is LOW
3. SCU turns on power domain of the core
a. Turn on the logic
b. Turn on the memories
4. SCU reloads repair configuration of memories used for caches
5. SCU sets BIAS value to according to operating point of the cluster
6. SCU disables isolation cells of the core
7. SCU sets reset nCPUPORESET HIGH of the core
8. CPU starts-up. It has to set the CPUECTLR.SMPEN bit to 1 to enable snooping into
the core
9. SCU controls the assertion of DBGPWRDUP to HIGH to allow external debug
access to the core
10. If required use software to restore the state of the core as it was prior to power-down
4.1.2.3 Clocking
The A53 platform is provided a main processor clock that supplies the component clocks
to the cluster components, including CoreSight debug components. The maximum
frequency targets are specified in the chip datasheet.
The cores are intended to support up to 1.8 GHz dependent on forward bias within the
operating temperature range. Please see the datasheet for more information. The clocks
are described in the table below:
Table 4-1. A53 Clocks
Clock Signal Clock Name Frequency Description
Main Clock CLKIN Target Main input clock.
APB Clock PCLKENDBG CLKIN/4 APB clock controls the timing on the debug port.
Fixed frequency ratio to main frequency.
AXI3 Bus Clock ACLKENM CLKIN/2 AXI3 Interface bus clock.
ATB Clock ATCLKEN CLKIN/4 ATB clock provides the clocks or outgoing trace.
This clock needs to be reasonably high to enable
sending samples out, but also needs to be the
same as CNTCLKEN. Link to same signal as
CNTCLKEN (1:4 core frequency fixed ratio).
Table continues on the next page...
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Arm Cortex M7 Platform (CM7)
Table 4-1. A53 Clocks (continued)
Input Counter Clock CNTCLKEN CLKIN/4 Input counter clock. Timing is identical to debug
port. The frequency is a fixed ratio (1:4) with the
core clock. The same signal may be used for
both inputs.
4.2 Arm Cortex M7 Platform (CM7)
4.2.1 Overview
The Cortex-M7 platform features a single Arm®Cortex®-M7 processor in this chip. The
Arm®Cortex®-M7 processor is a highly efficient, high-performance, embedded
processor that features low interrupt latency, low-cost debug, and has backwards
compatibility with existing Cortex-M profile processors. The processor has an in-order
super-scalar pipeline by which many instructions can be dual-issued, including load/load
and load/store instruction pairs because of multiple memory interfaces.
Memory interfaces that the processor supports include:
• Tightly-Coupled Memory (TCM)
• Harvard instruction and data caches and AXI master (AXIM) interface
The Arm Cortex-M7 Platform supports the following:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Floating Point Unit (FPU) with support for the FPv5 architecture
• Internal Trace (TRC)
The number of IRQs supported for this chip is 160. In addition, it supports various
components composing the Arm CoreSight debug/Trace system, such as ETM and CTI.
NOTE
This chip supports up to 16 interrupt priority levels, i.e. it
implements bits [7:4] of each NVIC Interrupt Priority Register.
4.2.1.1 Block Diagram
A block diagram for the Cortex-M7 is given below:
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AHBS
32-bit
Cortex-M7TM
64 KB
DTCM0
128 KB TCU
ITCM 64 KB
DTCM1
AHBD
32-bit NVIC FPU MPU ATB
FPB DWT ITM
32 KB 32 KB
BIU
I-cache D-cache
AXIM
Figure 4-2. Cortex-M7 Platform Block Diagram
4.2.1.2 Features
The Cortex-M7 platform in this chip has the following features.
• 1× Cortex M7 processor: architecture Arm v7E-M
• floating point unit (FPU) FPv5 including single and double precision
• bus interface 64-bit AMBA AXI3, 32-bit AMBA AHB slave port, AMBA AHB
debug interface for CoreSight components
• 32 KB instruction / 32 KB data L1 caches
• 128 KB ITCM / 128 KB DTCM
• 16 regions of MPU
• non-maskable (NMI) + 160 IRQs
• 16 interrupt priority levels (4-bits)
• sleep (WAIT) and deep sleep (STOP) power modes
• full debug with 8 breakpoints and 4 watchpoints
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Messaging Unit (MU)
4.2.2 Functional Description
4.2.2.1 Clocks
Table 4-2. Arm Cortex-M7 Clocks
Clock Name Description
ARM_M7_CLK_ROOT M7 core clock
4.3 Messaging Unit (MU)
4.3.1 Overview
The Messaging Unit (MU) module enables two processors within the SoC to
communicate and coordinate by passing messages (e.g. data, status and control) through
the MU interface. The MU also provides the ability for one processor to signal the other
processor using interrupts.
Because the MU manages the messaging between processors, the MU uses different
clocks (from each side of the different peripheral buses). Therefore, the MU must
synchronize the accesses from one side to the other. The MU accomplishes
synchronization using two sets of matching registers (Processor A-facing, Processor B-
facing).
4.3.1.1 Block Diagram
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Processor A Processor B
Messaging Unit (MU)
Processor A side Processor B side
TX / RX TX / RX
Registers Registers
Status and Status and
Processor A Processor B
Control Control
Peripheral Peripheral
Bus Registers Registers Bus
Sync and Sync and
Control Control
Registers Registers
Generate Generate
Interrupts Interrupts
Interrupts to Interrupts to
Processor A Processor B
interrupt interrupt
controller controller
Figure 4-3. MU Block Diagram
4.3.1.2 Features
The MU includes the following features:
• Messaging control by interrupts or by polling
• Symmetrical processor interfaces with each side supporting the following:
• Four general-purpose interrupt requests reflected to the other side
• Three general-purpose flags reflected to the other side 1
• Four receive registers with maskable interrupt
• Four transmit registers with maskable interrupt
• The above interrupts can also be used for waking up the other processor from low-
power mode.
NOTE
MU chapter references to Processor A correspond to Core
Complex 0 and references to Processor B correspond to Core
Complex 1 in this device.
1. For example, MUA (Processor A) can set the flag to MUB (Processor B), and MUB(Processor A) can set the
flag to MUA(Processor A).
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Messaging Unit (MU)
4.3.2 Functional Description
Table 4-3. Major Features of the MU
Major Feature Description
Interprocessor Interrupts • The MU has 12 interrupt sources on each side (Processor A-side, Processor B-
side) that are used for signaling the other processor. The interrupts can be used
for notification of RX/TX events and general-purpose signaling between the
processors.
MU Reset • The Processor A can issue a reset to the entire MU, using a control bit (MUR) in
the Processor A Control Register (ACR).
• The MUR bit is a self-clearing bit.
Status and Control Communications • The MU provides a way for the two core complexes to communicate using the
between Core Complexes status and control registers present on both the Processor B and Processor A
sides of the MU.
• The status register of one MU side reflects the status of the other MU side.
• The control register is used for control operations, such as enabling an interrupt
and sending an interrupt to the other processor.
Synchronized Message Transfers • The transfer of data messages between core complexes uses transmit empty
between Core Complexes and receive full flags provided on both sides of the MU.
• The update of these transmit and receive flags is accomplished using a
synchronization mechanism. There is inherent latency between updating the flag
on one side and reflecting its status on other side. For more about latency, see
Event Update Timing
Accessing Shared Memory Directly • For sending data or messages from one MU-side to the other MU-side, the MU
and Avoiding Collisions provides 4 transmit registers and 4 receive registers on each side of the MU.
• The Processor A or Processor B can access shared memory resources of the
SoC directly. However, to avoid simultaneous access to shared memory by both
core complexes, the MU provides a method (to prevent simultaneous access)
using interrupts and transmit-receive registers for both processors. See
Messaging Examples for more information.
Support for Different Clocks in the • The heart of the MU module is the event control mechanism, which synchronizes
Two Core Complexes the access of one MU-side to the other MU-side, because these two MU-sides
can operate using different clocks.
• Formulated event update latency.
Memory-Mapped Registers • The MU is connected as a peripheral under the Peripheral bus on both sides—on
the Processor A-side, the Processor A Peripheral Bus, and on the Processor B-
side, the Processor B Peripheral Bus.
4.3.2.1 Operating Modes
The MU operates in one of two modes: Run or low power.
4.3.2.2 Low Power Modes
This section describes the low power operating modes of the MU module.
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4.3.2.2.1 Low Power Clocks and Synchronization
The Processor B and the Processor A clocks operate at different frequencies and from
different sources. The MU design does not assume any frequency relationship between
the Processor A and the Processor B clocks. Be aware, however, that the frequency
relationship affects the MU’s throughput performance.
The data buffers and control logic of each MU-side operate with its corresponding clock.
4.3.2.2.2 Processor Low Power Modes
The Processors have four power modes:
• Run
• WAIT
• STOP
• SUSPEND, can also be called DSM (Deep Sleep Mode)
The Processor can be awakened from a low-power mode by any enabled Processor side
MU interrupt, as reflected in the xSR “status” register (RF0–3, TE0–3, GIP0–3 bits are
set) and enabled in the xCR control register. Using these bits, the Processor can actively
control when to wake the other Processor.
While the Processor is in STOP mode (such that the xSR register bits cannot be updated
with events), special logic drives the enabled MU interrupts directly from the other
Processor-side (instead of from the xSR register).
While the Processor is in STOP mode, the asynchronous MU interrupt will be asserted to
wake the Processor:
• If any transmit data register of the transmitter Processor-side is full, because of a
write to it (transmit data register); that is, its “empty” bit in the xSR register is
cleared while its corresponding receive interrupt is enabled on the receiver
Processor-side.
• If any receive data register of the receiver Processor-side is empty, because of a read
on the other Processor -side; that is, its “full” bit in the xSR register is cleared while
its corresponding transmit interrupt is enabled on the transmitter Processor-side.
• If any general purpose interrupt bit is set in the xCR register on the other Processor-
side while the corresponding interrupt is enabled on the Processor-side.
The logic enables the other Processor to operate independently while the Processor is in
any power mode (including STOP). However, the Processor power mode change protocol
should be handled with care regarding:
• The interrupts that are enabled on the Processor-side
• The events that could be triggered by the other Processor-side
• The compatibility with the other Processor protocol of entering STOP mode
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Messaging Unit (MU)
If the Processor is in STOP mode and an event on the other Processor is triggered, the EP
bit (in the xSR register) will remain high until the Processor wakes up.
Before entering STOP mode, the Processor programmer should verify that the EP bit (in
the xSR register) is cleared. This check is needed to ensure that all pending updates from
the Processor, including the power mode change when STOP or WAIT is executed, will
be updated in the xSR register.
• If the other Processor is in STOP mode or DSM mode, the EP bit (in the xSR
register) may be stuck high; in this case, the Processor need not check the EP bit
before entering STOP mode.
4.3.2.3 Processor A Side Memory-Mapping
The messaging, control, and status registers of the Processor A-side for the MU are
mapped to the Processor A memory as a regular peripheral. The Peripheral bus data is 32
bits wide inside the MU module.
4.3.2.4 Processor B Side Memory-Mapping
The messaging, control, and status registers of the Processor B-side for the MU are
mapped to the Processor B memory as a regular peripheral. The Peripheral bus data is 32
bits wide inside the MU module.
4.3.2.5 MU Messaging
The MU provides 32-bit status and control registers to the Processor B and Processor A
sides for control operations (such as interrupts and reset), and for status checking of the
other MU-side.
For messaging, the MU has four, 32-bit write-only transmit registers and four, 32-bit
read-only receive registers on the Processor B and Processor A-sides. These registers are
used for sending messages to each other. These messages can also be controlled using the
3 general purpose flags provided in the control and status registers of either MU-side.
4.3.2.5.1 Programmer Model
The messaging logic is used in conjunction with external memory. There are various
messaging methods, which can be used to implement a messaging protocol. Some of
these messages can mean “a message of N words has just been written, starting at offset
X in the memory,” or “a previous data block that was sent has just been read.” Having the
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messaging logic independent from the memory array does not restrict users to a
predefined hardware protocol. On the other hand, the software needed to manage the
messaging is short and straightforward.
Most of the messaging mechanisms are symmetric; they are duplicated and are available
on both the Processor B-side and the Processor A-side. The messaging mechanisms are:
• Four, 32-bit write-only transmit registers, which are each reflected in four, read-only
receive registers in the other processor’s side. Users can use these registers to transfer
32-bit word messages or frame information of messages written to the shared
memory (number of words, initial address, and message type code).
• A write to a transmit register on the transmitter side clears a “transmitter empty” bit
in the Status Register on the transmitter side, and sets a “receiver full” bit in the
Status Register on the receiver side. The setting of the bit at the receiver side can
optionally trigger an interrupt at the receiver side (maskable receive interrupt).
• A read of one of the receive registers at the receiver side clears the “receiver full” bit
in the Status Register at the receiver side, and sets the “transmitter empty” bit in the
Status Register on the transmitter side. The setting of the “transmitter empty” bit can
optionally trigger an interrupt at the transmitter side (maskable transmit interrupt).
• Four general purpose flags are reflected in the Status Register on the receiver side
• A read/write access to any reserved location and a write to a read-only register on the
Processor A-side of the MU will generate a module transfer error acknowledge to the
Processor A.
• A read/write access to any reserved location and write to a read-only register on the
Processor B-side of the MU will generate a module transfer error acknowledge to the
Processor B.
4.3.2.5.2 Messaging Examples
The following are messaging examples:
• Passing short messages: Transmit register(s) can be used to pass short messages
from one to four words in length. For example, when a four-word message is desired,
only one of the registers needs to have its corresponding interrupt enable bit set at the
receiver side; the message’s first three words are written to the registers whose
interrupt is masked, and the fourth word is written to the other register (which
triggers an interrupt at the receiver side).
• Passing frame information: Transmit registers can be used to pass frame
information for long messages written to the shared system memory. Such frame
information normally includes a start address, number of words, and perhaps a
message type code.
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Messaging Unit (MU)
• Passing event notices and requests: Events and requests that do not include data
words can be signaled from the Processor B to the Processor A using the general
interrupts, such as acknowledging that a long message was read from the shared
system memory.
• Passing fixed length data: Formatted data with a fixed length can be written in
predetermined locations in the shared memory. A processor can use a general
interrupt (Processor A or Processor B) to signal the other processor that the data is
ready.
• Passing announcements: The three flags can be used by a processor to announce its
current program state or other billboard messages to the other processor.
Figure 4-4 shows the MU registers schematic.
Processor Other
Processor
Messaging Unit (MU)
xCR xSR
xSR xCR
xRR0-3 xTR0-3
xTR0-3 xRR0-3
Figure 4-4. MU Registers
4.3.2.6 Event Update Timing
Each processor’s MU messaging side (Processor B or Processor A) has a hardware
mechanism to send “event update requests” to the other processor’s side. An “event” is
considered when any information change should be reflected at the Status Register of the
receiving processor. The event update latency is the delay between the event being ready
at one processor and the resulting update at the Status Register of the other processor.
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• The minimum event latency is “1 clock of the sending side” + “2 1/2 clocks of the
receiving side”. The minimum case is if there is no event pending when the new
event occurs. See clocking chapter for this device for more information about clock
sources.
• The maximum event latency is “6 clocks of the sending side” + “6 1/2 clocks of the
receiving side.” The maximum case is if the event occurred just after a previous
event was sent to the other side. The event update latency will vary between the
above-mentioned minimum and maximum latencies, depending on the time at which
the subsequent event is triggered.
4.3.2.7 Reset
The MU has two sources of reset, and each reset has a different function from the MU or
system perspective.
• One asynchronous system that is connected to both sides of the MU interface.
• One programmable hardware reset (MUR bit) in the ACR register (on the Processor
A-side).
Table 4-4. MU programmable resets
Reset Description
Processor A MU reset • Processor A MU Reset bit (MUR) of the ACR register
• The MUR reset affects the messaging section on both the Processor A and the
Processor B sides. The MUR reset causes all control and status registers to
return to their default values and all internal states to be cleared.
• It is up to the Processor A software to decide whether to use the MUR reset or
not.
• The instruction immediately following assertion of the MUR bit should not write to
MU registers. Such a write may be overwritten by the reset sequence and the
register will remain with the reset value. Wait at least one instruction (after
assertion of the MUR bit) before attempting a write to MU registers.
After issuing MUR bit reset events, the Processor A programmer can verify that the reset
sequence on the Processor B-side has ended, by checking the RS bit in the ASR register.
NOTE
MUR bit assertion is a delicate operation because it affects the
other side’s registers asynchronously. MUR bit assertion may
cause unpredictable behavior if, for example, the Processor B is
concurrently testing an MU register bit (TE bit in Processor B
SR register). Before asserting the MUR bit, it should be verified
that the Processor B is not presently engaged in an MU
signalling activity.
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4.3.2.8 Interrupts
The MU controls the Processor B interrupt requests to the Processor A, and the Processor
A interrupt requests to the Processor B. This section describes all the interrupts that the
module generates.
4.3.2.8.1 Interrupts to the Processors
There are 12 interrupt sources from the MU to the Processors:
• Four receive interrupts for each of the receive registers: Asserted when the Processor
receive full bits (xSR[RFn]) are set and the xCR[RIEn] bits enabled
• Four transmit interrupts for each of the transmit registers: Asserted when the
Processor transmit empty bits (xSR[TEn]) are set and the xCR[TIEn] bits enabled
• Four general purpose interrupts: Asserted when the xSR[GIPn] bits are set and the
xCR[GIEn] bits enabled
All the interrupts are maskable in the Processor Control Register (xCR). The MU does
not assume any internal priority of these interrupts. Multiple interrupts (for example,
Receive 0 and Receive 1 interrupts or any of the transmit and general purpose interrupts)
can be asserted at one time. The priority of these interrupts should be resolved by the
interrupt controller at the chip level.
The General Purpose Interrupt Pending bits (GIP0, GIP1, GIP2 and GIP3) should be
cleared by the software (as part of the interrupt service routine) to de-assert the request to
the interrupt controller.
4.3.2.8.2 General Purpose Interrupt Clearing Sequence
When a Processor writes to the general interrupt bit (GIR), the write event is
synchronized to the other Processor clock to set the general interrupt request pending bit
(GIP). When the GIP bit is set, and if the general purpose interrupt is enabled on the
receiving Processor side (GIE bit is set), then the transmitting Processor general purpose
interrupt is issued to the receiving Processor. The receiving Processor clears this interrupt
by writing a “1” on the GIP bit. The interrupt is de-asserted as soon as the GIP bit is
written. The write event of the GIP bit is synchronized to the other Processor clock. The
synchronized signal clears the GIR bit. The software should not write the GIR bit again
until the GIR bit is cleared.
4.3.2.9 Interrupt Messaging Protocols
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4.3.2.9.1 Messaging Protocols using Interrupts
The example below describes a four-word messaging sequence sent by the Processor to
the other Processor.
In this example, the first, second, and third receive interrupts are disabled, and the fourth
receive interrupt is enabled. We write registers sequentially for n = 0, 1, 2, 3. For n = 0, 1,
2, the interrupts are disabled, therefore no interrupt will go to the other core complex
(although interrupt conditions occur). For n = 3, the interrupt is enabled, and the last
Receive Interrupt request is generated.
1. Write Sequence
• The Processor writes the message information sequentially to its Transmit
Registers 0, 1, 2.
• When the write to the Transmit Register 3 occurs, the RF3 bit of the xSR is set
after synchronization, and it immediately trigger the Receive 3 interrupt to the
other Processor.
2. Read Sequence
• The other Processor receives the Receive 3 interrupt and starts reading the
message transferred from the receive registers.
• After Receive Register 3 is read, the interrupt bit is cleared.
Figure 4-5 shows the programmer’s model of a messaging protocol using transmit and
receive registers. Use Table 4-5 and Figure 4-5 to understand the generalized protocol
sequence.
Table 4-5. Interrupt Messaging Protocol (Generalized)
Sequence Action Description
1 Processor A Data write A data write to the ATRn register by Processor A is
immediately reflected in the Processor B BRRn register.
2 Clear Tx Empty bit and Set Rx Full The data write to the ATRn register
bit • Clears the transmitter empty bit (TEn) in the Processor
A Transmit Status Register
• Sets the receiver full bit (RFn) in the Processor B
Receive Status Register
3 Generate Receive Interrupt request The setting of the receiver full bit (RFn) in the Receive Status
Register generates a Receive Interrupt request to Processor
B.
4 Processor B Data read After receiving the Receive Interrupt request, Processor B
performs a data read of the BRRn register.
5 Clear Rx Full bit and Set Tx Empty Reading the data out of the BRRn register
bit • Clears the receiver full bit (RFn) in the Processor B
Receive Status Register
• Sets the transmitter empty bit (TEn) in the Processor A
Transmit Status Register
6 Generate Transmit Interrupt request The setting of the transmitter empty bit (TEn) in the Transmit
Status Register generates a Transmit Interrupt request to
Processor A.
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Messaging Unit (MU)
Processor A Processor B
Messaging Unit (MU)
Data write Transmitter side Receiver side Data read
Registers
Registers
1 4
Tx Status Rx Status
2 5
read from 4th TEn clear
RFn write from 4th
set Rx Full
Tx Empty
receive register set clear transmit register
triggers interrupt triggers interrupt
Tx Control Rx Control
6 TIEn Interrupt Interrupt RIEn 3
Enable Enable
Transmit Receive
interrupt interrupt
request request
Figure 4-5. Messaging Model Using Transmit and Receive Registers
NOTE
The Transmit registers can be used to pass frame information
on long messages written to the shared memory. Such frame
information would typically include an initial address, number
of words, and perhaps a message type code.
The messaging hardware can be used by software to implement messaging protocols for a
wide array of message types. Full support is given for both interrupt and polling
management schemes.
4.3.2.9.2 Messaging Protocols using Event Interrupts
Events and requests that do not include data words can be signaled from the Processor B
to the Processor A using the two general interrupts.
Formatted data with a fixed length can be written in predetermined locations in the shared
memory. A processor can use a general purpose interrupt to signal the other processor
that the data is ready.
The three flags can be used by a processor to announce to the other processor the
program state it is currently in, or to announce similar messages.
Table 4-6 and Figure 4-6 describe the event sequence when the Processor triggers an
interrupt.
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Table 4-6. Interrupt Messaging Protocol (Generalized)
Sequence Action Description
1 Processor A sets General Interrupt Processor A sets its associated General Interrupt request bit
request bit (GIRn = 1) in the control register (ACR).
2 General Interrupt Request Pending The General Interrupt Request Pending status bit (GIPn) in
status bit is set the status register (BSR) is set to "1"
3 General Interrupt request to Setting the GIPn bit generates the General Interrupt request
Processor B is generated to Processor B (Interrupt Request Enable bit, GIEn, must be
set for Processor B)
4 Processor B reads status register The Processor B reads the GIPn bit in the BSR register.
5 Processor B services the interrupt -
6 Processor B sets GIPn bit to clear The Processor B writes "1" to the corresponding GIPn bit to
interrupt clear the interrupt
7 GIRn bit is cleared Setting the GIPn bit to "1" clears the General Interrupt request
bit (GIRn) in the Processor A control register (ACR).
Processor A Processor B
Messaging Unit (MU)
4
Control Status Read GIPn bit
Services
5
Interrupt
1 GIRn 2 GIPn
set set int pend 6
int req 7 clear Write "1" to clear
General Purpose
ACR BSR
Interrupt Request
Register Register
OR'd with other
requests
Control
Interrupt 3 General Purpose
GIEn
Enable Interrupt Request
BCR
Register
Figure 4-6. Messaging Model Using a General Purpose Interrupt
4.3.2.10 Exclusive Access to Shared Memory
The MU can be used to signal one processor about its current access to the shared
memory, so that the data is not overwritten by the other processor during the exclusive
memory access period.
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Messaging Unit (MU)
The following tables describe the signaling protocol that the Processor A uses to inform
the Processor B about its current access (write) to the shared memory, assuming that the
set of bits and registers (GIR0 bit, BRR0 register, BTR0 register, GIR0 bit, ARR0
register, ATR0 register) are reserved to support exclusive access to the shared memory
protocol.
Table 4-7. How the Processor A Performs an Exclusive Access to Shared Memory
Sequence Action Description
1 Processor A sends GIRn request to When the Processor A wants to perform an exclusive access
Processor B using Processor A to the shared memory, the Processor A sends an GIR0
control register request to the Processor B.
2 Processor A sends an exclusive- The Processor A will send an exclusive-access request
access request using a transmit data (command, location, and length of target access) to
register (ATRn) Processor B using a selected transmit data register (ATR0).
3 Processor A waits for a dedicated The Processor A waits for a dedicated interrupt (as an
interrupt from Processor B acknowledgement) triggered by the Processor B before
proceeding.
4 Processor A accesses shared After receiving a dedicated interrupt from the Processor B,
memory Processor A proceeds.
Table 4-8. How the Processor B Scans for Transaction Information
Sequence Action Description
1 Processor B receives an interrupt -
from a receive data register (BRRn)
2 Processor B reads the receive data -
register (BRRn)
3 Processor B scans the receive data For transaction information (whether Processor A has
register contents requested an exclusive-access)
Table 4-9. How the Processor B Accepts Exclusive Access by Processor A
Sequence Action Description
1 Processor B triggers a dedicated Processor B acknowledges the Processor A request by
interrupt triggering a dedicated interrupt (ack) to the Processor A.
2 Processor B sends a code message Along with the acknowledge interrupt, the Processor B sends
to Processor A a code message to the Processor A through the selected
transmit register (BTRn). The message informs the Processor
A that it can exclusively access the shared memory.
Table 4-10. How the Processor B Rejects Exclusive Access by Processor A
Sequence Action Description
1 Processor B ignores Processor A If the Processor B does not want to give go-ahead permission
request for exclusive access to the Processor A, Processor B ignores the exclusive access
request.
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4.3.2.11 Packet Data Transfers
The following example describes the packet transfer sequence between the Processor B
and Processor A subsystems:
Table 4-11. Packet Data Transfer Sequence
Action Sequence Description
Processor B requests DMA 1 The Processor B sends a DMA request to initiate the packet data
transfer
DMA data transfer 2 DMA acknowledges.
3 DMA starts transferring data from the specified Processor B location
to the specified shared memory
4 DMA interrupts the Processor B to signal that the packet transfer
has finished.
Processor B informs Processor A 5 Using an MU Processor B-side transmit register, the Processor B
that data is in shared memory sends a packet information message to the Processor A to inform
the Processor A of the arrival of new packet data that is stored in
shared memory . The message contains the command, location,
and length of packet data information.
Processor A receives interrupt 6 The Processor A receives an interrupt (assuming its corresponding
Processor A MU-side receive interrupt is enabled), and the pending
processing task becomes active and processes packet data from
memory.
Processor A reads data, writes data 7 The Processor A reads or processes packet data from shared
memory.
8 The Processor A writes the result from packet processing to a
separate buffer.
Processor A informs Processor B 9 After the processing of the packet data finishes, the Processor A
that transfer is finished informs the Processor B (using the MU Processor A-side transmit
register, ATRn).
Processor A sends interrupt to 10 The Processor B receives the next interrupt from the Processor A, in
Processor B (request for more data) which the Processor A requests more packet data.
4.3.3 External Signals
There are no Messaging Unit signals directly available at the chip boundary of the SoC.
4.3.4 Initialization
The MU is used for two processors to communicate by passing messages. Below are
examples for passing messages:
1. Interrupt mode
• Processor A:
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• write ATR0;
• ACR.TIEn[0] = 1;
• wait for transmit register empty interrupt;
• Processor B:
• BCR.RIEn[0] = 1;
• wait for receive register full interrupt;
• read BRR0;
2. Polling mode
• Processor A:
• write ATR0;
• while(ASR.TEn[0] != 1) ;
• Processor B:
• while(BSR.RFn[0] != 1) ;
• read BRR0;
See Application Information for details regarding software restrictions.
4.3.5 Application Information
This section describes certain software restrictions when accessing the MU.
4.3.5.1 General Restrictions
This section lists the restrictions that apply to both the sides (Processor A, Processor B)
of the MU.
4.3.5.1.1 Write-After-Write to a Transmit Register
A write to a transmit register signals the receiver side that data is ready for retrieval.
• Writing to the transmit register again without verifying that the data was retrieved is
prohibited, because the transmitter side has no way of knowing the exact time that
the receiver will attempt to retrieve the data.
• Before attempting to write the transmit register again, the transmitter side should
wait for a “Transmitter Empty” interrupt, or should poll the “Transmitter Empty” bit
in the Status Register.
• Failure to follow this restriction may result in the wrong data being read on the
receiver side of the MU.
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4.3.5.1.2 Read-After-Read from a Receive Register
A read of a receive register signals the transmitter side that data can be written to that
register. In the same way, the receiver processor should not read a receive register before
receiving a “Receiver Full” interrupt or polling the “Receiver Full” bit in the Status
Register.
• Reading the receive register again without verifying that the data was written is
prohibited, because the receiver side has no way of knowing the exact time that the
transmitter will attempt to write the data.
• Before attempting to read the receive register again, the receiver side should wait for
a “Receiver Full” interrupt, or should poll the “Receiver Full” bit in the Status
Register.
• Failure to follow this restriction may result in the wrong data being written on the
transmitter side of the MU.
4.3.5.2 Processor Restrictions
This section lists the restrictions that apply each side of the processor in the MU.
4.3.5.2.1 Before Entering Low Power Mode
Before entering Low Power mode, the Processor should verify that the Processor Event
Pending (EP) bit in the Status Register is cleared.
• If the Event Pending bit (EP) is still set to “1”, then the Processor should wait and
poll the EP bit until it is cleared, before executing the low power mode instruction.
• Note that if the other Processor is in Low Power mode, the EP bit may be stuck high.
In this case, the other Processor clock must be turned ON to get the EP bit cleared
before the Processor can enter Low Power mode.
• To discover which power mode the other Processor is in, the Processor can check the
Power Mode bits in the xSR register.
4.3.5.2.2 Before Setting a General Interrupt Request Bit (GIR0–3)
Before setting a General Interrupt Request bit (GIR0–3), verify the GIRn bit is cleared,
which means that a general interrupt is not pending. Generally, setting the GIRn bit while
the bit is set to “1” will be ignored, but in some cases it may issue a second interrupt.
This restriction is meant to prevent this indeterministic behavior.
4.3.5.2.3 Reset Bit Restrictions
The reset bit (MUR, BHR) restrictions are:
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• Before asserting the MUR bit in the ACR register, verify that the Processor B-side is
not engaged in some MU activity.
• Do not write to an MU register in the instruction immediately after the assertion of
the MUR bit in the ACR register, because the written data can be overridden by the
reset value.
4.3.6 MU Processor A-side Memory Map/Register Definition
4.3.6.1 MUA register descriptions
This section contains the detailed register descriptions for the Processor A-side MU
registers.
4.3.6.1.1 MUA memory map
MUA base address: 30AA_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Processor A Transmit Register 0 (ATR0) 32 RW 0000_0000
4 Processor A Transmit Register 1 (ATR1) 32 RW 0000_0000
8 Processor A Transmit Register 2 (ATR2) 32 RW 0000_0000
C Processor A Transmit Register 3 (ATR3) 32 RW 0000_0000
10 Processor A Receive Register 0 (ARR0) 32 RO 0000_0000
14 Processor A Receive Register 1 (ARR1) 32 RO 0000_0000
18 Processor A Receive Register 2 (ARR2) 32 RO 0000_0000
1C Processor A Receive Register 3 (ARR3) 32 RO 0000_0000
20 Processor A Status Register (ASR) 32 RW 00F0_0080
24 Processor A Control Register (ACR) 32 RW 0000_0000
4.3.6.1.2 Processor A Transmit Register 0 (ATR0)
Use Processor A Transmit Register 0 (ATR0, 32-bit, write-only) to transmit a message or
data to the Processor B.
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• Users can only write to the ATR0 register when the TE0 bit in ASR register is set to
"1".
• Reading the ATR0 register returns all zeros.
4.3.6.1.2.1 Offset
Register Offset
ATR0 0h
4.3.6.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ATR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ATR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.2.3 Fields
Field Description
31-0 ATR0
ATR0 Processor A Transmit Register 0. (Write-only)
• Data written to the ATR0 register is reflected on the Processor B-side in the Processor B Receive
Register 0 (BRR0). The ATR0 and BRR0 registers are not double-buffered—a write to the ATR0
register overrides the data readable at the BRR0 register.
• A write to the transmit register clears a "transmitter empty" bit (TE0) in the Processor A Status
Register (ASR) on the transmitter side, and sets a "receiver full" bit (RF0) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 0 on the Processor B-side).
• Any write to the ATR0 register will update all status information.
4.3.6.1.3 Processor A Transmit Register 1 (ATR1)
Use Processor A Transmit Register 1 (ATR1, 32-bit, write-only) to transmit a message or
data to the Processor B.
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• Users can only write to the ATR1 register when the TE1 bit in ASR register is set to
"1".
• Reading the ATR1 register returns all zeros.
4.3.6.1.3.1 Offset
Register Offset
ATR1 4h
4.3.6.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ATR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ATR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.3.3 Fields
Field Description
31-0 ATR1
ATR1 Processor A Transmit Register 1. (Write-only)
• Data written to the ATR1 register is reflected on the Processor B-side in the Processor B Receive
Register 1 (BRR1). The ATR1 and BRR1 registers are not double-buffered—a write to the ATR1
register overrides the data readable at the BRR1 register.
• A write to the transmit register clears a "transmitter empty" bit (TE1) in the Processor A Status
Register (ASR) on the transmitter side, and sets a "receiver full" bit (RF1) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 1 on the Processor B-side).
• Any write to the ATR1 register will update all status information.
4.3.6.1.4 Processor A Transmit Register 2 (ATR2)
Use Processor A Transmit Register 2 (ATR2, 32-bit, write-only) to transmit a message or
data to the Processor B.
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• Users can only write to the ATR2 register when the TE2 bit in ASR register is set to
"1".
• Reading the ATR2 register returns all zeros.
4.3.6.1.4.1 Offset
Register Offset
ATR2 8h
4.3.6.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ATR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ATR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.4.3 Fields
Field Description
31-0 ATR2
ATR2 Processor A Transmit Register 2. (Write-only)
• Data written to the ATR2 register is reflected on the Processor B-side in the Processor B Receive
Register 2 (BRR2). The ATR2 and BRR2 registers are not double-buffered—a write to the ATR2
register overrides the data readable at the BRR2 register.
• A write to the transmit register clears a "transmitter empty" bit (TE2) in the Processor A Status
Register (ASR) on the transmitter side, and sets a "receiver full" bit (RF2) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 2 on the Processor B-side).
• Any write to the ATR2 register will update all status information.
4.3.6.1.5 Processor A Transmit Register 3 (ATR3)
Use Processor A Transmit Register 3 (ATR3, 32-bit, write-only) to transmit a message or
data to the Processor B.
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• Users can only write to the ATR3 register when the TE3 bit in ASR register is set to
"1".
• Reading the ATR3 register returns all zeros.
4.3.6.1.5.1 Offset
Register Offset
ATR3 Ch
4.3.6.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
ATR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ATR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.5.3 Fields
Field Description
31-0 ATR3
ATR3 Processor A Transmit Register 3. (Write-only)
• Data written to the ATR3 register is reflected on the Processor B-side in the Processor B Receive
Register 3 (BRR3). The ATR3 and BRR3 registers are not double-buffered—a write to the ATR3
register overrides the data readable at the BRR3 register.
• A write to the transmit register clears a "transmitter empty" bit (TE3) in the Processor A Status
Register (ASR) on the transmitter side, and sets a "receiver full" bit (RF3) in the Processor B Status
Register (BSR) on the receiver side (optionally triggering an interrupt 3 on the Processor B-side).
• Any write to the ATR3 register will update all status information.
4.3.6.1.6 Processor A Receive Register 0 (ARR0)
Use Processor A Receive Register 0 (ARR0, 32-bit, read-only) to receive a message or
data from the Processor B.
• Data written to the BTR0 register is immediately reflected in the ARR0 register.
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• Users can only read the ARR0 register when the RF0 bit in the ASR register is set to
"1".
• Writing to the ARR0 register generates an error response to the Processor A.
4.3.6.1.6.1 Offset
Register Offset
ARR0 10h
4.3.6.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ARR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ARR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.6.3 Fields
Field Description
31-0 ARR0
ARR0 Processor A Receive Register 0. (Read-only)
• Reflects the data written to Processor B Transmit Register 0 (BTR0).
• Reading the ARR0 register clears the "receiver full" bit (RF0) in the Processor A Status Register
(ASR) on the receiver side, and sets the "transmitter empty" bit (TE0) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 0 on the Processor B-
side).
• Any read of the ARR0 register will update all status information.
4.3.6.1.7 Processor A Receive Register 1 (ARR1)
Use Processor A Receive Register 1 (ARR1, 32-bit, read-only) to receive a message or
data from the Processor B.
• Data written to the BTR1 register is immediately reflected in the ARR1 register.
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Messaging Unit (MU)
• Users can only read the ARR1 register when the RF1 bit in the ASR register is set to
"1".
• Writing to the ARR1 register generates an error response to the Processor A.
4.3.6.1.7.1 Offset
Register Offset
ARR1 14h
4.3.6.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ARR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ARR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.7.3 Fields
Field Description
31-0 ARR1
ARR1 Processor A Receive Register 1. (Read-only)
• Reflects the data written to Processor B Transmit Register 1 (BTR1).
• Reading the ARR1 register clears the "receiver full" bit (RF1) in the Processor A Status Register
(ASR) on the receiver side, and sets the "transmitter empty" bit (TE1) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 1 on the Processor B-
side).
• Any read of the ARR1 register will update all status information.
4.3.6.1.8 Processor A Receive Register 2 (ARR2)
Use Processor A Receive Register 2 (ARR2, 32-bit, read-only) to receive a message or
data from the Processor B.
• Data written to the BTR2 register is immediately reflected in the ARR2 register.
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• Users can only read the ARR2 register when the RF2 bit in the ASR register is set to
"1".
• Writing to the ARR2 register generates an error response to the Processor A.
4.3.6.1.8.1 Offset
Register Offset
ARR2 18h
4.3.6.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ARR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ARR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.8.3 Fields
Field Description
31-0 ARR2
ARR2 Processor A Receive Register 2. (Read-only)
• Reflects the data written to Processor B Transmit Register 1 (BTR2).
• Reading the ARR2 register clears the "receiver full" bit (RF2) in the Processor A Status Register
(ASR) on the receiver side, and sets the "transmitter empty" bit (TE2) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 2 on the Processor B-
side).
• Any read of the ARR2 register will update all status information.
4.3.6.1.9 Processor A Receive Register 3 (ARR3)
Use Processor A Receive Register 3 (ARR3, 32-bit, read-only) to receive a message or
data from the Processor B.
• Data written to the BTR3 register is immediately reflected in the ARR3 register.
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Messaging Unit (MU)
• Users can only read the ARR3 register when the RF3 bit in the ASR register is set to
"1".
• Writing to the ARR3 register generates an error response to the Processor A.
4.3.6.1.9.1 Offset
Register Offset
ARR3 1Ch
4.3.6.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ARR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ARR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.9.3 Fields
Field Description
31-0 ARR3
ARR3 Processor A Receive Register 3. (Read-only)
• Reflects the data written to Processor B Transmit Register 3 (BTR3).
• Reading the ARR3 register clears the "receiver full" bit (RF3) in the Processor A Status Register
(ASR) on the receiver side, and sets the "transmitter empty" bit (TE3) in the Processor B Status
Register on the transmitter side (optionally triggering a transmit interrupt 3 on the Processor B-
side).
• Any read of the ARR3 register will update all status information.
4.3.6.1.10 Processor A Status Register (ASR)
Use the Processor A Status Register (ASR, 32-bit, read-write) to show interrupt status
from the Processor B, general purpose flags, and to set dual function control-status bits.
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• Some dual-purpose bits are set by the MU logic, and cleared by the Processor A-side
programmer
• Other dual-purpose bits are set by the Processor A-side programmer, and cleared by
the MU logic.
4.3.6.1.10.1 Offset
Register Offset
ASR 20h
4.3.6.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GIPn RFn TEn Reserved
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
BRDIP
BRS
FUP
EP
Fn
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
4.3.6.1.10.3 Fields
Field Description
31-28 GIPn
GIPn For n = {0, 1, 2, 3} Processor A General Interrupt Request n Pending. (Read-Write)
• GIPn bit signals the Processor A that the GIRn bit in the BCR register on the Processor B-side was
set from "0" to "1". If the GIEn bit in the ACR register is set to "1", a General Interrupt n request is
issued.
• The GIPn bit is cleared by writing it back as "1". Writing "0", or writing "1" when the GIPn bit is
cleared is ignored. Use this feature in the interrupt routine, where the GIPn bit is cleared in order to
de-assert the interrupt request source at the interrupt controller. The proper bit clearing sequence
is: clear an Processor A register, set the desired bit in it (Processor A register), and write it to the
ASR register, thus clearing the GIPn bit.
• GIPn bit is cleared when the MU is reset.
0000 - Processor A general purpose interrupt n is not pending. (default)
0001 - Processor A general purpose interrupt n is pending.
27-24 RFn
RFn For n = {0, 1, 2, 3} Processor A Receive Register n Full. (Read-only)
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Messaging Unit (MU)
Field Description
• The RFn bit is set to "1" when the BTRn register is written on the Processor B-side.
• After the RFn bit is set to "1", the RFn bit signals the Processor A-side that new data is ready to be
read by the Processor A in the ARRn register, and a Receive n interrupt is issued on the Processor
A-side (if the RIEn bit in the ACR register has been set to "1").
• RFn bit is cleared when the ARRn register is read, and when the MU is reset.
0000 - ARRn register is not full (default).
0001 - ARRn register has received data from BTRn register and is ready to be read by the Processor A.
23-20 TEn
TEn For n = {0, 1, 2, 3} Processor A Transmit Register n Empty. (Read-only)
• The TEn bit is set to "1" after the BRRn register is read on the Processor B-side.
• After the TEn bit is set to "1", the TEn bit signals the Processor A-side that the ATRn register is
ready to be written on the Processor A-side, and a Transmit n interrupt is issued on the Processor
A-side (if the TEn bit in the ACR register is set to "1").
• TEn bit is cleared after the ATRn register is written on the Processor A-side.
• TEn bit is set to "1" when the MU is reset.
0000 - ATRn register is not empty.
0001 - ATRn register is empty (default).
19-10 -
— Reserved
9 BRDIP
BRDIP Processor B Reset De-asserted Interrupt Pending. (Read-Write)
• BRDIP bit signals the Processor A-side that the Processor B-side has come out of reset.
• BRDIP bit is set to "1" after the MU Processor B-side comes out of reset, after synchronization. The
interrupt generated by a Processor B-side reset de-assertion is ORed with the Processor A general
purpose interrupt 3. The Processor A general purpose interrupt 3 is issued when the Processor B-
side comes out of reset (if the interrupt is enabled).
• To clear the BRDIP bit, write "1", which also clears general purpose interrupt 3.
• When Processor A-side of MU comes out of reset BRDIP bit has value "0"(default).Then Processor
A sees the status of Processor B-side and if Processor B-side has come out of reset then BRDIP
bit goes high. This takes 5-6 clock cycles. If the BRDIP bit is read now it shows as high although its
reset value was "0".
0 - The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is
cleared (default).
1 - The Processor B-side is out of reset.
8 FUP
FUP Processor A Flags Update Pending. (Read-only)
• FUP bit is set to "1" when the Processor A-side sends a Flags Update request to the Processor B-
side.
• A Flags Update request is generated when the ABF[2:0] bits of the ACR register change. No flag
update changes are allowed while the FUP bit is set to "1". Any write to the ABF[2:0] bits, while the
FUP bit is set to "1", will not generate a Flags Update event, and the ABF[2:0] bits will stay
unchanged.
• FUP bit is cleared when this Flags Update request is internally acknowledged (that the flag is
updated) from the MU Processor B-side, and during MU reset.
0 - No flags updated, initiated by the Processor A, in progress (default)
1 - Processor A initiated flags update, processing
7 BRS
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Field Description
BRS Processor B-side Reset State. (Read-only)
• BRS bit indicates if the Processor B-side of the MU is in a reset state or not.
• If the BRS bit is set to "1", then the Processor B-side of the MU is still in the reset state.
• If the BRS bit is cleared, then the Processor B-side of the MU are out of reset.
• The BRS bit is set to "1" during: a Processor B system reset, or an MU reset (caused by setting the
MUR bit at the ACR register).
• The BRS bit is cleared when the reset sequence on the Processor B-side of the MU ends. After
issuing any of the reset events mentioned previously, verify that the BRS bit is cleared before
starting any accesses.
• When Processor A side of MU comes out of reset BRS bit has value "1"(default).Then Processor A
sees the status of Processor B-side and if Processor B-side has come out of reset then BRS bit
goes low. This takes 5-6 clock cycles. If the BRS bit is read now it shows as low although its reset
value was "1" .
0 - The Processor B-side of the MU is not in reset.
1 - The Processor B-side of the MU is in reset.
6-5 -
— Reserved
4 EP
EP Processor A-Side Event Pending. (Read-only)
• EP bit is set to "1" when the Processor A-side mechanism sends an event update request to the
Processor B-side.
• EP bit is cleared when the event update acknowledge is received. An "event" is any hardware
message that is reflected in the BSR register on the Processor B-side (for example, "transmit
register 0 written"). During normal operations, users do not have to deal with the state of the EP bit
because the event update mechanism works automatically.
• To ensure events have been posted to Processor B before entering STOP mode, verify that the EP
bit is cleared. If EP bit is set to "1", wait and continue to poll it (EP bit) before entering STOP mode.
• Reading the ASR register (to check the EP bit) should be the last access to the MU that should be
performed before entering STOP or WAIT modes; otherwise, the EP bit may be set by subsequent
additional actions.
• The EP bit is cleared when the MU resets.
0 - The Processor A-side event is not pending (default).
1 - The Processor A-side event is pending.
3 -
— Reserved
2-0 Fn
Fn For n = {0, 1, 2} Processor A-Side Flag n. (Read-only)
• Fn bit is the Processor A-side flag that reflects the values written to the BAFn bit in the Processor B
control register.
• Every time that the BAFn bit is written, the BAFn bit write event updates the Fn bit after the event
update latency, which is measured in terms of the number of clocks of the Processor B and the
Processor A.
000 - BAFn bit in BCR register is written 0 (default).
001 - BAFn bit in BCR register is written 1.
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4.3.6.1.11 Processor A Control Register (ACR)
Use the Processor A Control Register (ACR, 32-bit, read-write) to enable the MU
interrupts on the Processor A-side, and trigger events and interrupts on the Processor B-
side (general purpose interrupt, flag update).
For the fields GIEn, RIEn, TIEn and GIRn, n=0 corresponds to the high order bit and n=3
corresponds to the low order bit.
4.3.6.1.11.1 Offset
Register Offset
ACR 24h
4.3.6.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GIEn RIEn TIEn GIRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
BRDIE
ABFn
MUR
BHR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.6.1.11.3 Fields
Field Description
31-28 GIEn
GIEn For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Enable n. (Read-Write) When GIEn=0
corresponds to the high order bit and GIE3 corresponds to the low order bit.
• GIEn bit enables Processor A General Interrupt n.
• If GIEn bit is set to "1" (enabled), then a General Interrupt n request is issued when the GIPn bit in
the ASR register is set to "1".
• If GIEn is cleared (disabled), then the value of the GIPn bit is ignored and no General Interrupt n
request will be issued.
• GIEn bit is cleared when the MU resets.
0000 - Disables Processor A General Interrupt n. (default)
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Field Description
0001 - Enables Processor A General Interrupt n.
27-24 RIEn
RIEn For n = {0, 1, 2, 3} Processor A Receive Interrupt Enable n. (Read-Write)
• RIEn bit enables Processor A Receive Interrupt n.
• If RIEn bit is set to "1" (enabled), then an Processor A Receive Interrupt n request is issued when
the RFn bit in the ASR register is set to "1".
• If RIEn bit is cleared (disabled), then the value of the RFn bit is ignored and no Processor A
Receive Interrupt n request will be issued.
• RIEn bit is cleared when the MU resets.
0000 - Disables Processor A Receive Interrupt n. (default)
0001 - Enables Processor A Receive Interrupt n.
23-20 TIEn
TIEn For n = {0, 1, 2, 3} Processor A Transmit Interrupt Enable n. (Read-Write)
• TIEn bit enables Processor A Transmit Interrupt n.
• If TIEn bit is set to "1" (enabled), then an Processor A Transmit Interrupt n request is issued when
the TEn bit in the ASR register is set to "1".
• If TIEn bit is cleared (disabled), then the value of the TEn bit is ignored and no Processor A
Transmit Interrupt n request will be issued.
• TIEn bit is cleared when the MU resets.
0000 - Disables Processor A Transmit Interrupt n. (default)
0001 - Enables Processor A Transmit Interrupt n.
19-16 GIRn
GIRn For n = {0, 1, 2, 3} Processor A General Purpose Interrupt Request n. (Read-Write)
• Writing "1" to the GIRn bit sets the GIPn bit in the BSR register on the Processor B-side. If the GIEn
bit in the BCR register is set to "1" on the Processor B-side, a General Purpose Interrupt n request
is triggered.
• The GIRn bit is cleared if the GIPn bit (in the BSR register on the Processor B-side) is cleared by
writing it (GIPn bit) as "1", thereby signalling the Processor A that the interrupt was accepted
(cleared by the software). The GIPn bit cannot be written as "0" on the Processor A-side.
• To ensure proper operations, verify that the GIRn bit is cleared (meaning that there is no pending
interrupt) before setting it (GIRn bit).
• GIRn bit is cleared when the MU resets.
0000 - Processor A General Interrupt n is not requested to the Processor B (default).
0001 - Processor A General Interrupt n is requested to the Processor B.
15-7 -
— Reserved
6 BRDIE
BRDIE Processor B Reset De-assertion Interrupt Enable. (Read-Write)
• BRDIE bit enables Processor A General Interrupt 3.
• If BRDIE bit is set to "1", then General Interrupt 3 request is issued to the Processor A when the
BRDIP bit in the ASR register is set to "1".
• If BRDIE is cleared, then the value of the BRDIP bit is ignored and no General Interrupt 3 request
will be issued.
• The BRDIE bit is cleared when the MU resets.
0 - Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-
assertion to the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B
side to come out of reset thus setting BRDIP bit to "1".
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Field Description
1 - Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion
to the Processor A.
5 MUR
MUR Processor A MU Reset.
• Setting MUR bit to "1" resets both the Processor B and the Processor A sides of the MU module,
forcing all control and status registers to return to their default values (except the BHR bit in the
ACR register and BHRM bit in BCR register), and all internal states to be cleared.
• Before setting the MUR bit to "1", it is advisable to interrupt the Processor B, because setting the
MUR bit may affect the ongoing Processor B program.
• After setting the MUR bit, monitor the value of the BRS bit in the ASR register to know when the
reset sequence on the Processor B-side has ended.
• MUR bit can only be written as "1".
• MUR bit is always read as "0".
• MUR bit is cleared during the MU reset sequence.
0 - N/A. Self clearing bit (default).
1 - Asserts the Processor A MU reset.
4 BHR
BHR Processor B Hardware Reset. (Read-Write)
• BHR bit asserts and de-asserts the hardware reset of the Processor B.
• Set BHR bit to "1" to start a hardware reset of the Processor B.
• Clear the BHR bit to de-assert the Processor B hardware reset input.
• Assert the BHR bit for a minimum of 3 clock cycles of network clock (sampling clock in SRC) clock.
The BRS bit in MU_ASR register (b[7]) indicates the state of the Processor B. As soon as the
Processor B goes into Reset (BRS bit is set to "1"), the BHR bit can be de-asserted.
• Strobe-setting the BHR bit will not cause an internal MU reset but will be routed outside MU to
Processor B domain reset logic
• After clearing the BHR bit, monitor the value of the BRS bit at the ASR to know when the Processor
B reset sequence has ended.
• The BHR reset issued by the Processor A to the Processor B is maskable by the Processor B
(according to the settings of the BHRM bit in the BCR register). If the BHRM bit (in the BCR
register) is set to "1", then the BHR reset is masked; if the BHRM bit (in the BCR register) is cleared
(default), then the BHR reset is enabled.
• The BHR bit does not return to the reset value during the software (MUR) reset.
0 - De-assert Hardware reset to the Processor B. (default)
1 - Assert Hardware reset to the Processor B.
3 -
— Reserved
2-0 ABFn
ABFn For n = {0, 1, 2} Processor A to Processor B Flag n. (Read-Write)
• ABFn bit is a read-write flag that is reflected in Fn bit in the BSR register on the Processor B-side.
• ABFn bit is cleared when the MU resets.
000 - N/A. Self clearing bit (default).
001 - Asserts the Processor A MU reset.
4.3.7 MU Processor B-side Memory Map/Register Definition
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4.3.7.1 MUB register descriptions
This section contains the detailed register descriptions for the Processor B-side MU
registers.
4.3.7.1.1 MUB memory map
MUB base address: 30AB_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Processor B Transmit Register 0 (BTR0) 32 RW 0000_0000
4 Processor B Transmit Register 1 (BTR1) 32 RW 0000_0000
8 Processor B Transmit Register 2 (BTR2) 32 RW 0000_0000
C Processor B Transmit Register 3 (BTR3) 32 RW 0000_0000
10 Processor B Receive Register 0 (BRR0) 32 RO 0000_0000
14 Processor B Receive Register 1 (BRR1) 32 RO 0000_0000
18 Processor B Receive Register 2 (BRR2) 32 RO 0000_0000
1C Processor B Receive Register 3 (BRR3) 32 RO 0000_0000
20 Processor B Status Register (BSR) 32 RW 00F0_0080
24 Processor B Control Register (BCR) 32 RW 0000_0000
4.3.7.1.2 Processor B Transmit Register 0 (BTR0)
Use Processor B Transmit Register 0 (BTR0, 32-bit, write-only) to transmit a message or
data to the Processor A.
• The BTR0 register can only be written when the TE0 bit in BSR register is set to "1".
• Reading the BTR0 register returns all zeros.
4.3.7.1.2.1 Offset
Register Offset
BTR0 0h
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4.3.7.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BTR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BTR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.2.3 Fields
Field Description
31-0 BTR0
BTR0 Processor B Transmit Register 0. (Write-only)
• Data written to the BTR0 register is reflected on the Processor A-side in the Processor A Receive
Register 0 (ARR0). The BTR0 and ARR0 registers are not double-buffered—a write to the BTR0
register overrides the data readable at the ARR0 register.
• A write to the transmit register clears a "transmitter empty" bit (TE0) in the Processor B Status
Register (BSR) on the transmitter side, and sets a "receiver full" bit (RF0) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 0 on the Processor A-side).
• Any write to the BTR0 register will update all status information.
4.3.7.1.3 Processor B Transmit Register 1 (BTR1)
Use Processor B Transmit Register 1 (BTR1, 32-bit, write-only) to transmit a message or
data to the Processor A.
• The BTR1 register can only be written when the TE1 bit in BSR register is set to "1".
• Reading the BTR1 register returns all zeros.
4.3.7.1.3.1 Offset
Register Offset
BTR1 4h
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4.3.7.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BTR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BTR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.3.3 Fields
Field Description
31-0 BTR1
BTR1 Processor B Transmit Register 1. (Write-only)
• Data written to the BTR1 register is reflected on the Processor A-side in the Processor A Receive
Register 1 (ARR1). The BTR1 and ARR1 registers are not double-buffered—a write to the BTR1
register overrides the data readable at the ARR1 register.
• A write to the transmit register clears a "transmitter empty" bit (TE1) in the Processor B Status
Register (BSR) on the transmitter side, and sets a "receiver full" bit (RF1) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 1 on the Processor A-side).
• Any write to the BTR1 register will update all status information.
4.3.7.1.4 Processor B Transmit Register 2 (BTR2)
Use Processor B Transmit Register 2 (BTR2, 32-bit, write-only) to transmit a message or
data to the Processor A.
• The BTR2 register can only be written when the TE2 bit in BSR register is set to "1".
• Reading the BTR2 register returns all zeros.
4.3.7.1.4.1 Offset
Register Offset
BTR2 8h
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4.3.7.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BTR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BTR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.4.3 Fields
Field Description
31-0 BTR2
BTR2 Processor B Transmit Register 2. (Write-only)
• Data written to the BTR2 register is reflected on the Processor A-side in the Processor A Receive
Register 2 (ARR2). The BTR2 and ARR2 registers are not double-buffered—a write to the BTR2
register overrides the data readable at the ARR2 register.
• A write to the transmit register clears a "transmitter empty" bit (TE2) in the Processor B Status
Register (BSR) on the transmitter side, and sets a "receiver full" bit (RF2) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 2 on the Processor A-side).
• Any write to the BTR2 register will update all status information.
4.3.7.1.5 Processor B Transmit Register 3 (BTR3)
Use Processor B Transmit Register 3 (BTR3, 32-bit, write-only) to transmit a message or
data to the Processor A.
• The BTR3 register can only be written when the TE3 bit in BSR register is set to "1".
• Reading the BTR3 register returns all zeros.
4.3.7.1.5.1 Offset
Register Offset
BTR3 Ch
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4.3.7.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BTR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BTR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.5.3 Fields
Field Description
31-0 BTR3
BTR3 Processor B Transmit Register 3. (Write-only)
• Data written to the BTR3 register is reflected on the Processor A-side in the Processor A Receive
Register 3 (ARR3). The BTR3 and ARR3 registers are not double-buffered—a write to the BTR3
register overrides the data readable at the ARR3 register.
• A write to the transmit register clears a "transmitter empty" bit (TE3) in the Processor B Status
Register (BSR) on the transmitter side, and sets a "receiver full" bit (RF3) in the Processor A Status
Register (ASR) on the receiver side (optionally triggering an interrupt 3 on the Processor A-side).
• Any write to the BTR3 register will update all status information.
4.3.7.1.6 Processor B Receive Register 0 (BRR0)
Use Processor B Receive Register 0 (BRR0, 32-bit, read-only) to receive a message or
data from the Processor A.
• Data written to the ATR0 register is immediately reflected in the BRR0 register.
• The BRR0 register can only be read when the RF0 bit in the BSR register is set to
"1".
• Writing to the BRR0 register generates an error response to the Processor B.
4.3.7.1.6.1 Offset
Register Offset
BRR0 10h
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4.3.7.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BRR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BRR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.6.3 Fields
Field Description
31-0 BRR0
BRR0 Processor B Receive Register 0. (Read-only)
• Reflects the data written to Processor A Transmit Register 0 (ATR0).
• Reading the BRR0 register clears the "receiver full" bit (RF0) in the Processor B Status Register
(BSR) on the receiver side, and sets the "transmitter empty" bit (TE0) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 0 on the Processor A-
side).
• Any read of the BRR0 register will update all status information.
4.3.7.1.7 Processor B Receive Register 1 (BRR1)
Use Processor B Receive Register 1 (BRR1, 32-bit, read-only) to receive a message or
data from the Processor A.
• Data written to the ATR1 register is immediately reflected in the BRR1 register.
• The BRR1 register can only be read when the RF1 bit in the BSR register is set to
"1".
• Writing to the BRR1 register generates an error response to the Processor B.
4.3.7.1.7.1 Offset
Register Offset
BRR1 14h
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4.3.7.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BRR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BRR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.7.3 Fields
Field Description
31-0 BRR1
BRR1 Processor B Receive Register 1. (Read-only)
• Reflects the data written to Processor A Transmit Register 1 (ATR1).
• Reading the BRR1 register clears the "receiver full" bit (RF1) in the Processor B Status Register
(BSR) on the receiver side, and sets the "transmitter empty" bit (TE1) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 1 on the Processor A-
side).
• Any read of the BRR1 register will update all status information.
4.3.7.1.8 Processor B Receive Register 2 (BRR2)
Use Processor B Receive Register 2 (BRR2, 32-bit, read-only) to receive a message or
data from the Processor A.
• Data written to the ATR2 register is immediately reflected in the BRR2 register.
• The BRR2 register can only be read when the RF2 bit in the BSR register is set to
"1".
• Writing to the BRR2 register generates an error response to the Processor B.
4.3.7.1.8.1 Offset
Register Offset
BRR2 18h
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4.3.7.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BRR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BRR2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.8.3 Fields
Field Description
31-0 BRR2
BRR2 Processor B Receive Register 2. (Read-only)
• Reflects the data written to Processor A Transmit Register 1 (ATR2).
• Reading the BRR2 register clears the "receiver full" bit (RF2) in the Processor B Status Register
(BSR) on the receiver side, and sets the "transmitter empty" bit (TE2) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 2 on the Processor A-
side).
• Any read of the BRR2 register will update all status information.
4.3.7.1.9 Processor B Receive Register 3 (BRR3)
Use Processor B Receive Register 3 (BRR3, 32-bit, read-only) to receive a message or
data from the Processor A.
• Data written to the ATR3 register is immediately reflected in the BRR3 register.
• The BRR3 register can only be read when the RF3 bit in the BSR register is set to
"1".
• Writing to the BRR3 register generates an error response to the Processor B.
4.3.7.1.9.1 Offset
Register Offset
BRR3 1Ch
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4.3.7.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R BRR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BRR3
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.9.3 Fields
Field Description
31-0 BRR3
BRR3 Processor B Receive Register 3. (Read-only)
• Reflects the data written to Processor A Transmit Register 3 (ATR3).
• Reading the BRR3 register clears the "receiver full" bit (RF3) in the Processor B Status Register
(BSR) on the receiver side, and sets the "transmitter empty" bit (TE3) in the Processor A Status
Register on the transmitter side (optionally triggering a transmit interrupt 3 on the Processor A-
side).
• Any read of the BRR3 register will update all status information.
4.3.7.1.10 Processor B Status Register (BSR)
Use the Processor B Status Register (BSR, 32-bit, read-write) to show interrupt status
from the Processor B, general purpose flags, the Processor A power mode, and to set dual
function control-status bits.
• Dual-purpose bits are set by the Processor B-side programmer, and cleared by the
MU logic.
4.3.7.1.10.1 Offset
Register Offset
BSR 20h
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4.3.7.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GIPn RFn TEn Reserved
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APM
R
Reserved
Reserved
ARS
FUP
EP
Fn
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
4.3.7.1.10.3 Fields
Field Description
31-28 GIPn
GIPn For n = {0, 1, 2, 3} Processor B General Interrupt Request n Pending. (Read-Write)
• GIPn bit signals the Processor B that the GIRn bit in the ACR register on the Processor A-side was
set from "0" to "1". If the GIEn bit in the BCR register is set to "1", a General Interrupt n request is
issued.
• The GIPn bit is cleared by writing it back as "1". Writing "0", or writing "1" when the GIPn bit is
cleared is ignored. Use this feature in the interrupt routine, where the GIPn bit is cleared in order to
de-assert the interrupt request source at the interrupt controller.
• GIPn bit is cleared when the MU is reset.
0000 - Processor B general purpose interrupt n is not pending. (default)
0001 - Processor B general purpose interrupt n is pending.
27-24 RFn
RFn For n = {0, 1, 2, 3} Processor B Receive Register n Full. (Read-only)
• RFn bit signals to the Processor B-side that new data was written by the Processor A to the ATRn
register, and is ready to be read by the Processor B in the BRRn register.
• The RFn bit is set to "1" when the ATRn register is written on the Processor A-side.
• After the RFn bit is set to "1", the RFn bit signals the Processor B-side that new data is ready to be
read by the Processor B in the BRRn register, and a Receive n interrupt is issued on the Processor
A-side (if the RIEn bit in the BCR register has been set to "1").
• RFn bit is cleared when the BRRn register is read, and when the MU is reset.
0000 - BRRn register is not full (default).
0001 - BRRn register has received data from ATRn register and is ready to be read by the Processor B.
23-20 TEn
TEn For n = {0, 1, 2, 3} Processor B Transmit Register n Empty. (Read-only)
• When TEn = "1", it signals to the Processor B-side that the BTRn register is ready to be written on
the Processor B-side.
• The TEn bit is set to "1" after the ARRn register is read on the Processor A-side.
• Setting TEn bit will issue a transmit n interrupt on the Processor B-side (if the TIEn bit in the BCR
register is set to "1".
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Field Description
• TEn bit is cleared after the BTRn register is written on the Processor B-side.
• TEn bit is set to "1" when the MU is reset.
0000 - BTRn register is not empty.
0001 - BTRn register is empty (default).
19-9 Reserved
—
8 FUP
FUP Processor B Flags Update Pending. (Read-only)
• FUP bit is set to "1" when the Processor B-side sends a Flags Update request to the Processor A-
side.
• A Flags Update request is generated when the BAF[2:0] bits of the BCR register change. No flag
update changes are allowed while the FUP bit is set to "1". Any write to the BAF[2:0] bits, while the
FUP bit is set to "1", will not generate a Flags Update event, and the BAF[2:0] bits will stay
unchanged.
• FUP bit is cleared when this Flags Update request is internally acknowledged (that the flag is
updated) from the MU Processor A-side, and during MU reset.
0 - No flags updated, initiated by the Processor B, in progress (default)
1 - Processor B initiated flags update, processing
7 ARS
ARS Processor A Reset State. (Read-only)
• ARS bit indicates if the Processor A-side of the MU is in a reset state or not.
• If the ARS bit is set to "1", then the Processor A-side of the MU is still in the reset state.
• If the ARS bit is cleared, then both the Processor A and the Processor A-side of the MU are out of
reset.
• The ARS bit is set to "1" during: a Processor A system reset, or an MU reset (caused by setting the
MUR bit at the BCR register).
• The ARS bit is cleared when the reset sequence on the Processor A-side of the MU ends. After
issuing any of the three reset events mentioned previously, it should be verified that the ARS bit is
cleared before starting any accesses.
• When Processor B side of MU comes out of reset ARS bit has value "1"(default).Then Processor B
sees the status of Processor A side and if Processor A has come out of reset then ARS bit goes
low. This takes 5-6 clock cycles. If the ARS bit is read now it is low although its reset value was
"1" .
0 - The Processor A or the Processor A-side of the MU is not in reset.
1 - The Processor A or the Processor A-side of the MU is in reset.
6-5 APM
APM Processor A Power Mode. (Read-only)
• APM[1:0] bits indicate the Processor A power mode.
00 - The System is in Run Mode.
01 - The System is in WAIT Mode.
10 - Reserved.
11 - The System is in STOP Mode.
4 EP
EP Processor B-Side Event Pending. (Read-only)
• EP bit is set to "1" when the Processor B-side mechanism sends an event update request to the
Processor A-side.
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Messaging Unit (MU)
Field Description
• EP bit is cleared when the event update acknowledge is received. An "event" is any hardware
message that is reflected in the ASR register on the Processor A-side (for example, "transmit
register 0 written"). During normal operations, the state of the EP bit does not have to be manually
updated because the event update mechanism works automatically.
• To ensure events have been posted to Processor A before entering STOP mode, it should be
verified that the EP bit is cleared. If EP bit is set to "1", continue to poll it (EP bit) before entering
STOP mode.
• Reading the BSR register (to check the EP bit) should be the last access to the MU that should be
performed before entering STOP mode; otherwise, the EP bit may be set by subsequent additional
actions.
• Due to Processor B pipeline effects, three NOP operations (or their timing equivalent) should be
given after an instruction that sets an event before the EP bit can reflect this event.
• The EP bit is cleared when the MU resets.
0 - The Processor B-side event is not pending (default).
1 - The Processor B-side event is pending.
3 Reserved
—
2-0 Fn
Fn For n = {0, 1, 2} Processor B-Side Flag n. (Read-only)
• Fn bit is the Processor B-side flag that reflects the values written to the ABFn bit in the Processor A
control register.
• Every time that the ABFn bit is written, the ABFn bit write event updates the Fn bit after the event
update latency, which is measured in terms of the number of clocks of the Processor A and the
Processor B.
000 - ABFn bit in ACR register is written 0 (default).
001 - ABFn bit in ACR register is written 1.
4.3.7.1.11 Processor B Control Register (BCR)
Use the Processor B Control Register (BCR, 32-bit, read-write) to enable the MU
interrupts on the Processor B-side, and trigger events and interrupts on the Processor A-
side (wake from STOP, hardware reset, flag update).
For the fields GIEn, RIEn, TIEn and GIRn, n=0 corresponds to the high order bit and n=3
corresponds to the low order bit.
4.3.7.1.11.1 Offset
Register Offset
BCR 24h
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4.3.7.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GIEn RIEn TIEn GIRn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
BAFn
HRM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.3.7.1.11.3 Fields
Field Description
31-28 GIEn
GIEn For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Enable n. (Read-Write)
• GIEn bit enables Processor B General Interrupt n.
• If GIEn bit is set to "1" (enabled), then a General Interrupt n request is issued when the GIPn bit in
the BSR register is set to "1".
• If GIEn is cleared (disabled), then the value of the GIPn bit is ignored and no General Interrupt n
request will be issued.
• GIEn bit is cleared when the MU resets.
0000 - Disables Processor B General Interrupt n. (default)
0001 - Enables Processor B General Interrupt n.
27-24 RIEn
RIEn For n = {0, 1, 2, 3} Processor B Receive Interrupt Enable n. (Read-Write)
• RIEn bit enables Processor B Receive Interrupt n.
• If RIEn bit is set to "1" (enabled), then an Processor B Receive Interrupt n request is issued when
the RFn bit in the BSR register is set to "1".
• If RIEn bit is cleared (disabled), then the value of the RFn bit is ignored and no Processor B
Receive Interrupt n request will be issued.
• RIEn bit is cleared when the MU resets.
0000 - Disables Processor B Receive Interrupt n. (default)
0001 - Enables Processor B Receive Interrupt n.
23-20 TIEn
TIEn For n = {0, 1, 2, 3} Processor B Transmit Interrupt Enable n. (Read-Write)
• TIEn bit enables Processor B Transmit Interrupt n.
• If TIEn bit is set to "1" (enabled), then an Processor B Transmit Interrupt n request is issued when
the TEn bit in the BSR register is set to "1".
• If TIEn bit is cleared (disabled), then the value of the TEn bit is ignored and no Processor B
Transmit Interrupt n request will be issued.
• TIEn bit is cleared when the MU resets.
0000 - Disables Processor B Transmit Interrupt n. (default)
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Semaphore (SEMA4)
Field Description
0001 - Enables Processor B Transmit Interrupt n.
19-16 GIRn
GIRn For n = {0, 1, 2, 3} Processor B General Purpose Interrupt Request n. (Read-Write)
• Writing "1" to the GIRn bit sets the GIPn bit in the ASR register on the Processor A-side. If the GIEn
bit in the ACR register is set to "1" on the Processor A-side, a General Purpose Interrupt n request
is triggered.
• The GIRn bit is cleared if the GIPn bit (in the ASR register on the Processor A-side) is cleared by
writing it (GIPn bit) as "1", thereby signalling the Processor B that the interrupt was accepted
(cleared by the software). The GIPn bit cannot be written as "0" on the Processor B-side.
• To ensure proper operations, it must be verified that the GIRn bit is cleared (meaning that there is
no pending interrupt) before setting it (GIRn bit).
• GIRn bit is cleared when the MU resets.
0000 - Processor B General Interrupt n is not requested to the Processor A (default).
0001 - Processor B General Interrupt n is requested to the Processor A.
15-5 Reserved
—
4 HRM
HRM Processor B Hardware Reset Mask. (Read-Write)
• The Processor A can give a hardware reset to the Processor B by setting the BHR bit in the ACR
Register to "1".
• When the HRM bit is set to "1" by the Processor B, the BHR reset issued by the Processor A is
masked (disabled by the Processor B).
• When the HRM bit is cleared, the BHR reset issued by the Processor A to the Processor B is not
masked (enabled by the Processor B).
0 - BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware
reset).
1 - BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
3 Reserved
—
2-0 BAFn
BAFn For n = {0, 1, 2} Processor B to Processor A Flag n. (Read-Write)
• BAFn bit is a read-write flag that is reflected in Fn bit in the ASR register on the Processor A-side.
• BAFn bit is cleared when the MU resets.
000 - Clears the Fn bit in the ASR register.
001 - Sets the Fn bit in the ASR register.
4.4 Semaphore (SEMA4)
4.4.1 Overview
The Semaphores (SEMA4) module provides a platform IPS slave device which
implements 16 hardware-enforced gates.
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4.4.1.1 Block Diagram
A simplified block diagram of the Semaphores module is shown in Figure 4-7. This is a
dual-processor configuration, where cp0 is core processor 0 and cp1 is core processor 1.
In the diagram, the register blocks named gate0, gate1,…, gate 15 include the finite state
machines (FSM) implementing the semaphore gates plus the interrupt notification logic.
ips_semaphores
0 aips_master
2
= =
master_eq_cp{0,1} 0 ips_wdata
31
= = =
wdata_eq_{unlock, cp[0-1]_lock}
ips_addr
decode
gate0 gate1 gate2 gate3
control
gate12 gate13 gate14 gate15
mux
0 ips_rdata
cp0_semaphore_int cp1_semaphore_int 31
IPS Bus
Figure 4-7. Semaphores Block Diagram
4.4.1.2 Features
The Semaphores module implements hardware-enforced semaphores as an IPS-mapped
slave peripheral device. The feature set includes:
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Semaphore (SEMA4)
• Support for 16 hardware-enforced gates in a dual-processor configuration
• Each hardware gate appears as a 3-state, 2-bit state machine, with all 16 gates
mapped as a byte-size array
• Processors lock gates by writing "processor_number+1" to the appropriate
gate and must read back the gate value to verify the lock operation was
successful.
3-state implementation:
if gate = 0b00, then state = unlocked
if gate = 0b01, then state = locked by processor 0
if gate = 0b10, then state = locked by processor 1
• Uses the bus master number/ID as a reference attribute plus the specified
data patterns to validate all write operations
• Once locked, the gate can (and must) be unlocked by a write of zeroes from
the locking processor
• Optional interrupt notification after a failed lock write provides a mechanism to
indicate when the gate is unlocked
• Secure reset mechanisms are supported to clear the contents of individual gates
or notification logic, as well as a clear_all capability
• Memory-mapped IPS slave peripheral platform module
• Interface to the IPS bus for programming-model accesses
• Two outputs (one per processor) for interrupt notification of failed lock writes
4.4.2 Functional Description
In this section, the functional operation of the Semaphores module, specifically the state
machines of the SEMA4_GATEn and SEMA4_CPnNTF registers are detailed.
4.4.2.1 Modes of Operation
The Semaphores module does not support any special modes of operation. As a slave
peripheral memory-mapped device located on the platform's IPS slave bus, it responds
based strictly on the memory addresses of the connected bus. The IPS bus is used to
access the Semaphores' programming model.
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4.4.2.2 SEMA4_GATEn Operation
Recall each of the SEMA4_GATEn registers implements a 2-bit, 3-state machine. The
state transitions for each gate are shown in the following figure.
reset
1
idle
00
~((master == cp0) & (wdata == cp0_lock))
&~((master == cp1) & (wdata == cp1_lock))
2
master == cp0 master == cp1
& (wdata == cp0_lock) & (wdata == cp1_lock)
3 4
cp0_lock cp1_lock
01 10
5 7
master != cp0 master != cp1
6 | (wdata != unlock) | (wdata != unlock) 8
master == cp0 master == cp1
& (wdata == unlock) & (wdata == unlock)
Figure 4-8. SEMA4_GATEn State Machine
The bus master number/ID is used to identify core processor 0 (cp0) or core processor 1
(cp1).
The state transitions for SEMA4_GATEn are defined in the following table.
Table 4-12. SEMA4_GATEn State Transitions
Transitio
Current State Next State Description
n
idle 1 Any reset, whether a system reset or an individual gate reset,
–
unconditionally forces the gate into the idle state.
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Table 4-12. SEMA4_GATEn State Transitions (continued)
Transitio
Current State Next State Description
n
idle 2 Unless a write of the appropriate lock value from the
idle corresponding processor occurs, the gate remains in the idle
state.
cp0_lock 3 When a write of the "cp0_lock" data value is initiated by
idle
processor 0, the gate transitions into the cp0_lock state.
cp1_lock 4 When a write of the "cp1_lock" value is initiated by processor
idle
1, the gate transitions into the cp1_lock state.
cp0_lock 5 Once in this state, the gate remains here if any attempted
cp0_lock
write is not from cp0 with the unlock data value.
idle 6 The gate returns to the idle (unlocked) state once a write from
cp0_lock
cp0 with the unlock data value occurs.
cp1_lock 7 Once in this state, the gate remains here if any attempted
cp1_lock
write is not from cp1 with the unlock data value.
idle 8 The gate returns to the idle (unlocked) state once a write from
cp1_lock
cp1 with the unlock data value occurs.
4.4.2.3 SEMA4_CPnNTF Operation
The failed lock write notification interrupt request is implemented in a 3-bit, 5-state
machine which records failed lock attempts and transitions based on gate locking and
unlocking. Two specific states are encoded and program-visible as
SEMA4_CP0NTF[GNn] and SEMA4_CP1NTF[GNn]. See the following figure.
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any_reset
idle
000 ~transition_condition_3
& ~transition_condition_4
2
master == cp0 master == cp1
& (wdata == cp0_lock) & (wdata == cp1_lock)
& (gate == cp1_lock) & (gate == cp0_lock)
3 4
wait4_cp1_unlock wait4_cp0_unlock
010 001
gate != unlock
gate != unlock
5 7
10 6 8 13
gate ==cp1_lock gate == unlock gate == unlock gate == cp0_lock
wait4_cp0_lock wait4_cp1_lock
110 101
gate = !cp0_lock
& !cp1_lock
9 12
gate = !cp0_lock
11 & !cp1_lock 14
gate == cp0_lock gate == cp1_lock
Figure 4-9. IRQ Notification State Machine
The state transitions of the IRQ notification function are defined in the following table.
Specific states of this machine are program-visible as the SEMA4_CPnNTF registers. In
particular, two states are program-visible:
if state = wait4_cp0_lock (0b110) // generate cp0_semaphore_int if properly enabled
then SEMA4_CP0NTF[GNn] = 1;
else SEMA4_CP0NTF[GNn] = 0
if state = wait4_cp1_lock (0b101) // generate cp1_semaphore_int if properly enabled
then SEMA4_CP1NTF[GNn] = 1;
else SEMA4_CP1NTF[GNn] = 0
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Table 4-13. IRQ Notification State Transitions
Transitio
Current State Next State Description
n
idle 1 Any reset, including a system reset or an individual
– notification or secure gate reset, unconditionally forces the
machine into the idle state.
idle 2 Unless a write of the appropriate lock value from the
idle corresponding processor to an already-locked gate occurs,
the machine remains in the idle state.
wait4_cp1_unlock 3 When a write of the "cp0_lock" data value is initiated by
processor 0 but the gate is already locked by cp1, the
idle
machine transitions into this state, where it waits for cp1 to
unlock the gate.
wait4_cp0_unlock 4 When a write of the "cp1_lock" data value is initiated by
processor 1but the gate is already locked by cp0, the machine
idle
transitions into this state, where it waits for cp0 to unlock the
gate
wait4_cp1_unlock wait4_cp1_unlock 5 Once in this state, the machine remains here until the gate is
unlocked.
wait4_cp1_unlock wait4_cp0_lock 6 From this state, the machine transitions into the next state,
waiting for cp0 to lock the gate, once it has been unlocked.
wait4_cp0_unlock wait4_cp0_unlock 7 Once in this state, the machine remains here until the gate is
unlocked.
wait4_cp0_unlock wait4_cp1_lock 8 From this state, the machine transitions into the next state,
waiting for cp1 to lock the gate, once it has been unlocked.
wait4_cp0_lock 9 In this state, the machine generates the notification interrupt
wait4_cp0_lock (if properly-enabled) and remains here until the gate is locked
by processor 0 or the gate is again locked by processor 1.
wait4_cp1_unlock 10 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is again locked
wait4_cp0_lock
by processor 1. With this transition, the notification interrupt
request is negated.
idle 11 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is finally locked
wait4_cp0_lock
by processor 0. With this transition, the notification interrupt
request is negated.
wait4_cp1_lock 12 In this state, the machine generates the notification interrupt
wait4_cp1_lock (if properly-enabled) and remains here until the gate is locked
by processor 1or the gate is again locked by processor 0.
wait4_cp0_unlock 13 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is again locked
wait4_cp1_lock
by processor 0. With this transition, the notification interrupt
request is negated.
idle 14 In this state, the machine generates the notification interrupt
(if properly-enabled) and transitions if the gate is finally locked
wait4_cp1_lock
by processor 1. With this transition, the notification interrupt
request is negated.
The Semaphores module generates two interrupt request output signals, one per
processor, combining the SEMA4_CPnINE and SEMA4_CPnNTF registers, where the
boolean equations are:
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cp0_semaphore_int
= SEMA4_CP0INE[INE0] & SEMA4_CP0NTF[GN0]
| SEMA4_CP0INE[INE1] & SEMA4_CP0NTF[GN1]
| SEMA4_CP0INE[INE2] & SEMA4_CP0NTF[GN2]
...
| SEMA4_CP0INE[INE15] & SEMA4_CP0NTF[GN15]
cp1_semaphore_int
= SEMA4_CP1INE[INE0] & SEMA4_CP1NTF[GN0]
| SEMA4_CP1INE[INE1] & SEMA4_CP1NTF[GN1]
| SEMA4_CP1INE[INE2] & SEMA4_CP1NTF[GN2]
...
| SEMA4_CP1INE[INE15] & SEMA4_CP1NTF[GN15]
4.4.3 External Signal Description
The Semaphores module does not include any external interfaces.
4.4.4 Initialization Information
The reset state of the Semaphores module allows it to begin operation without the need
for any further initialization. All the internal state machines are cleared by any reset
event, allowing the module to immediately begin operation.
4.4.5 Application Information
In an operational multi-core system, most interactions involving the Semaphores module
involves reads and writes to the SEMA4_GATEn registers for implementation of the
hardware-enforced software gate functions. Typical code segments for gate functions
perform the following operations:
• To lock (close) a gate
• The processor performs a byte write of "logical_processor_number + 1" to
gate[i]
• The processor reads back gate[i] and checks for a value of
"logical_processor_number + 1"
If the compare indicates the expected value, then the gate is locked; proceed with the
protected code segment. If the compare does not indicate the expected value, the lock
operation failed; repeat the process beginning with byte write to gate[i] in spin-wait loop,
or proceed with another execution path and wait for failed lock interrupt notification.
A simple C-language example of a gateLock function is shown in the following figure.
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#define UNLOCK 0
#define CP0_LOCK 1
#define CP1_LOCK 2
void gateLock (n)
int n; /* gate number to lock */
{
int i;
int current_value;
int locked_value;
i = processor_number(); /* obtain logical CPU number */
if (i == 0)
locked_value = CP0_LOCK;
else
locked_value = CP1_LOCK;
/* read the current value of the gate and wait until the state == UNLOCK */
do {
current_value = gate[n];
} while (current_value != UNLOCK);
/* the current value of the gate == UNLOCK. attempt to lock the gate for this
processor. spin-wait in this loop until gate ownership is obtained */
do {
gate[n] = locked_value; /* write gate with processor_number + 1 */
current_value = gate[n]; /* read gate to verify ownership was obtained */
} while (current_value != locked_value);
Figure 4-10. Sample gateLock Function
• To unlock (open) a gate
• After completing the protected code segment, the locking processor performs a
byte write of zeroes to gate[i], opening (unlocking) the gate
A few comments on the logical CPU number are appropriate. In this example, a reference
to processor_number() is used to retrieve this hardware configuration value. Typically, the
logical processor numbers are defined by a hardwired input vector to the individual cores.
The exact method for accessing the logical processor number varies by architecture.
If the optional failed lock IRQ notification mechanisms are used, then accesses to the
related registers (SEMA4_CPnINE, SEMA4_ CPnNTF) are required. Note that there is
no required negation of the failed lock write notification interrupt, as the request is
automatically cleared by the Semaphores module once the gate has been successfully
locked by the "failing" processor.
Finally, in the event a system state requires a software-controlled reset of a gate or IRQ
notification register(s), accesses to the secure reset control registers (SEMA4_RSTGT,
SEMA4_RSTNTF) are required. For these situations, it is recommended that the
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appropriate IRQ notification enable (SEMA4_CPnINE) bits should be disabled before
initiating the secure reset 2-write sequence (write RSTGT and write RSTNTF), to avoid
any race conditions involving spurious notification interrupt requests.
4.4.6 Memory map and register definition
The Semaphores module provides an IPS programming model mapped to an on-platform
16 KB space. The description here specifies a dual-core configuration with 16 semaphore
gates. All the register names are prefixed with "SEMA4" as an abbreviation for the full
module name.
The programming model is referenced using 8-, 16- and 32-bit accesses. Reads can use
any reference size, while writes are generally restricted to the size of the register.
Exceptions to the write size restrictions are detailed in the individual register
descriptions. Attempted references using inappropriate access sizes, to undefined
(reserved) addresses, or with a non-supported access type (for example, a write to a read-
only register) generate an IPS error termination.
The 16 KB Semaphores programming model map is shown in the following table.
SEMA4 memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30AC_0000 Semaphores Gate n Register (SEMA4_Gate0) 8 R/W 00h 4.4.6.1/154
30AC_0001 Semaphores Gate n Register (SEMA4_Gate1) 8 R/W 00h 4.4.6.1/154
30AC_0002 Semaphores Gate n Register (SEMA4_Gate2) 8 R/W 00h 4.4.6.1/154
30AC_0003 Semaphores Gate n Register (SEMA4_Gate3) 8 R/W 00h 4.4.6.1/154
30AC_0004 Semaphores Gate n Register (SEMA4_Gate4) 8 R/W 00h 4.4.6.1/154
30AC_0005 Semaphores Gate n Register (SEMA4_Gate5) 8 R/W 00h 4.4.6.1/154
30AC_0006 Semaphores Gate n Register (SEMA4_Gate6) 8 R/W 00h 4.4.6.1/154
30AC_0007 Semaphores Gate n Register (SEMA4_Gate7) 8 R/W 00h 4.4.6.1/154
30AC_0008 Semaphores Gate n Register (SEMA4_Gate8) 8 R/W 00h 4.4.6.1/154
30AC_0009 Semaphores Gate n Register (SEMA4_Gate9) 8 R/W 00h 4.4.6.1/154
30AC_000A Semaphores Gate n Register (SEMA4_Gate10) 8 R/W 00h 4.4.6.1/154
30AC_000B Semaphores Gate n Register (SEMA4_Gate11) 8 R/W 00h 4.4.6.1/154
30AC_000C Semaphores Gate n Register (SEMA4_Gate12) 8 R/W 00h 4.4.6.1/154
30AC_000D Semaphores Gate n Register (SEMA4_Gate13) 8 R/W 00h 4.4.6.1/154
30AC_000E Semaphores Gate n Register (SEMA4_Gate14) 8 R/W 00h 4.4.6.1/154
30AC_000F Semaphores Gate n Register (SEMA4_Gate15) 8 R/W 00h 4.4.6.1/154
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SEMA4 memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Semaphores Processor n IRQ Notification Enable
30AC_0040 16 R/W 0000h 4.4.6.2/155
(SEMA4_CP0INE)
Semaphores Processor n IRQ Notification Enable
30AC_0048 16 R/W 0000h 4.4.6.2/155
(SEMA4_CP1INE)
Semaphores Processor n IRQ Notification
30AC_0080 16 R 0000h 4.4.6.3/157
(SEMA4_CP0NTF)
Semaphores Processor n IRQ Notification
30AC_0088 16 R 0000h 4.4.6.3/157
(SEMA4_CP1NTF)
30AC_0100 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT) 16 R/W 0000h 4.4.6.4/159
Semaphores (Secure) Reset IRQ Notification
30AC_0104 16 R/W 0000h 4.4.6.5/161
(SEMA4_RSTNTF)
4.4.6.1 Semaphores Gate n Register (SEMA4_Gaten)
Each semaphore gate is implemented in a 2-bit finite state machine (FSM), right-justified
in a byte data structure. The hardware uses the bus master number in conjunction with the
data patterns to validate all attempted write operations. Only processor bus masters can
modify the gate registers. Once locked, a gate can (and must) be opened (unlocked) by
the locking processor core.
Multiple gate values can be read in a single access, but only a single gate can be updated
via a write operation at a time. 16- and 32-bit writes to multiple gates are allowed, but the
write data operand must only update the state of a single gate. A byte write data value of
0x03 is defined as "no operation" and does not affect the state of the corresponding gate
register. Attempts to write multiple gates in a single aligned access with a size larger than
an 8-bit (byte) reference generate an error termination and do not allow any gate state
changes
Address: 30AC_0000h base + 0h offset + (1d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read 0 GTFSM
Write
Reset 0 0 0 0 0 0 0 0
SEMA4_Gaten field descriptions
Field Description
7–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
GTFSM Gate Finite State Machine.
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SEMA4_Gaten field descriptions (continued)
Field Description
Gate Finite State Machine. The hardware gate is maintained in a 3-state implementation-unlocked, locked
by processor 0 or locked by processor 1. For more details, see SEMA4_GATEn Operation .
NOTE: The state of the gate reflects the last processor that locked it, which can be useful during system
debug.
00 The gate is unlocked (free).
01 The gate has been locked by processor 0.
10 The gate has been locked by processor 1.
11 This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as
"no operation" and do not affect the gate state machine.
4.4.6.2 Semaphores Processor n IRQ Notification Enable
(SEMA4_CPnINE)
The application of a hardware semaphore module provides an opportunity for
implementation of helpful system-level features. An example is an optional mechanism to
generate a processor interrupt after a failed lock attempt. Recall traditional software gate
functions execute a spin-wait loop in an effort to obtain and lock the referenced gate.
With this module, the processor that fails in the lock attempt could continue with other
tasks and allow a properly-enabled notification interrupt to return its execution to the
original lock function.
The optional notification interrupt function consists of two registers for each processor:
an interrupt notification enable register (SEMA4_CPnINE) and the interrupt request
register (SEMA4_CPnNTF). To support implementations with more than 16 gates, these
registers can be referenced with aligned 16- or 32-bit accesses. For the SEMA4_CPnINE
registers, unimplemented bits read as zeroes, and writes are ignored.
Address: 30AC_0000h base + 40h offset + (8d × i), where i=0d to 1d
Bit 15 14 13 12 11 10 9 8
Read INE8 INE9 INE10 INE11 INE12 INE13 INE14 INE15
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read INE0 INE1 INE2 INE3 INE4 INE5 INE6 INE7
Write
Reset 0 0 0 0 0 0 0 0
SEMA4_CPnINE field descriptions
Field Description
15 Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt
INE8 notification from a failed attempt to lock gate 8.
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SEMA4_CPnINE field descriptions (continued)
Field Description
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
14 Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt
INE9 notification from a failed attempt to lock gate 9.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
13 Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt
INE10 notification from a failed attempt to lock gate 10.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
12 Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt
INE11 notification from a failed attempt to lock gate 11.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
11 Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt
INE12 notification from a failed attempt to lock gate 12.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
10 Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt
INE13 notification from a failed attempt to lock gate 13.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
9 Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt
INE14 notification from a failed attempt to lock gate 14.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
8 Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt
INE15 notification from a failed attempt to lock gate 15.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
7 Interrupt Request Notification Enable 0. This field is a bitmap to enable the generation of an interrupt
INE0 notification from a failed attempt to lock gate 0.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
6 Interrupt Request Notification Enable 1. This field is a bitmap to enable the generation of an interrupt
INE1 notification from a failed attempt to lock gate 1.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
5 Interrupt Request Notification Enable 2. This field is a bitmap to enable the generation of an interrupt
INE2 notification from a failed attempt to lock gate 2.
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SEMA4_CPnINE field descriptions (continued)
Field Description
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
4 Interrupt Request Notification Enable 3. This field is a bitmap to enable the generation of an interrupt
INE3 notification from a failed attempt to lock gate 3.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
3 Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt
INE4 notification from a failed attempt to lock gate 4.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
2 Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt
INE5 notification from a failed attempt to lock gate 5.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
1 Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt
INE6 notification from a failed attempt to lock gate 6.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
0 Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt
INE7 notification from a failed attempt to lock gate 7.
0 The generation of the notification interrupt is disabled.
1 The generation of the notification interrupt is enabled.
4.4.6.3 Semaphores Processor n IRQ Notification (SEMA4_CPnNTF)
The Semaphores module optionally allows the processor that fails in the lock attempt to
continue with other tasks and allow a properly-enabled notification interrupt to return its
execution to the original lock function rather than simply execute in a spin-wait loop.
The optional notification interrupt mechanism consists of two registers for each
processor: an interrupt notification enable register (SEMA4_CPnINE) and the read-only
notification interrupt request register (SEMA4_CPnNTF). To support implementations
with more than 16 gates, these registers can be referenced with aligned 16- or 32-bit
accesses. For the SEMA4_CPnNTF registers, unimplemented bits read as zeroes.
The notification interrupt is generated via a unique finite state machine (FSM), one per
hardware gate. This machine operates in the following manner:
1. When an attempted lock fails, the FSM enters a first state where it waits until the
gate is unlocked.
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2. Once unlocked, the FSM enters a second state where it generates an interrupt request
to the “failed lock” processor.
3. When the “failed lock” processor succeeds in locking the gate, the IRQ is
automatically cleared and the FSM returns to the idle state. However, if the other
processor again locks the gate, the FSM returns to the first state, clears the interrupt
request, and then waits for the gate to be unlocked (again).
The notification interrupt request is implemented in a 3-bit, 5-state machine, where two
specific states are encoded and program-visible as SEMA4_CP0NTF[GNn] and
SEMA4_CP1NTF[GNn].
Address: 30AC_0000h base + 80h offset + (8d × i), where i=0d to 1d
Bit 15 14 13 12 11 10 9 8
Read GN8 GN9 GN10 GN11 GN12 GN13 GN14 GN15
Write
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Read GN0 GN1 GN2 GN3 GN4 GN5 GN6 GN7
Write
Reset 0 0 0 0 0 0 0 0
SEMA4_CPnNTF field descriptions
Field Description
15 Gate 8 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN8 attempt to lock gate 8. For more details, see SEMA4_CPnNTF Operation .
14 Gate 9 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN9 attempt to lock gate 9. For more details, see SEMA4_CPnNTF Operation .
13 Gate 10 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN10 attempt to lock gate 10. For more details, see SEMA4_CPnNTF Operation .
12 Gate 11 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN11 attempt to lock gate 11. For more details, see SEMA4_CPnNTF Operation .
11 Gate 12 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN12 attempt to lock gate 12. For more details, see SEMA4_CPnNTF Operation .
10 Gate 13 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN13 attempt to lock gate 13. For more details, see SEMA4_CPnNTF Operation .
9 Gate 14 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN14 attempt to lock gate 14. For more details, see SEMA4_CPnNTF Operation .
8 Gate 15 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN15 attempt to lock gate 15. For more details, see SEMA4_CPnNTF Operation .
7 Gate 0 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN0 attempt to lock gate 0. For more details, see SEMA4_CPnNTF Operation .
6 Gate 1 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN1 attempt to lock gate 1. For more details, see SEMA4_CPnNTF Operation .
5 Gate 2 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN2 attempt to lock gate 2. For more details, see SEMA4_CPnNTF Operation .
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SEMA4_CPnNTF field descriptions (continued)
Field Description
4 Gate 3 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN3 attempt to lock gate 3. For more details, see SEMA4_CPnNTF Operation .
3 Gate 4 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN4 attempt to lock gate 4. For more details, see SEMA4_CPnNTF Operation .
2 Gate 5 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN5 attempt to lock gate 5. For more details, see SEMA4_CPnNTF Operation .
1 Gate 6 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN6 attempt to lock gate 6. For more details, see SEMA4_CPnNTF Operation .
0 Gate 7 Notification. This read-only field is a bitmap of the interrupt request notification from a failed
GN7 attempt to lock gate 7. For more details, see SEMA4_CPnNTF Operation .
4.4.6.4 Semaphores (Secure) Reset Gate n (SEMA4_RSTGT)
Although the intent of the hardware gate implementation specifies a protocol where the
locking processor must unlock the gate, it is recognized that system operation may
require a reset function to re-initialize the state of any gate(s) without requiring a system-
level reset.
To support this special gate reset requirement, the Semaphores module implements a
"secure" reset mechanism which allows a hardware gate (or all the gates) to be initialized
by following a specific dual-write access pattern. Using a technique similar to that
required for the servicing of a software watchdog timer, the secure gate reset requires two
consecutive writes with predefined data patterns from the same processor to force the
clearing of the specified gate(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTGT memory location. The
least significant byte (SEMA4_RSTGT[RSTGDP]) must be 0xe2; the most
significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTGT
location. For this write, the lower byte (SEMA4_RSTGT[RSTGDP]) is the logical
complement of the first data pattern (0x1d) and the upper byte
(SEMA4_RSTGT[RSTGTN]) specifies the gate(s) to be reset. This gate field can
specify a single gate be cleared, or that all gates are cleared.
3. Reads of the SEMA4_RSTGT location return information on the 2-bit state machine
(SEMA4_RSTGT[RSTGSM]) which implements this function, the bus master
performing the reset (SEMA4_RSTGT[RSTGMS]) and the gate number(s) last
cleared (SEMA4_RSTGT[RSTGTN]). Reads of the SEMA4_RSTGT register do not
affect the secure reset finite state machine in any manner.
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Address: 30AC_0000h base + 100h offset = 30AC_0100h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read RSTGTN RSTGSM_RSTGMS_RSTGDP
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SEMA4_RSTGT field descriptions
Field Description
15–8 Reset Gate Number. This 8-bit field specifies the specific hardware gate to be reset. This field is updated
RSTGTN by the second write.
This field contains the hexidecimal value of the gate number. If RSTGTN < 64, then reset the single gate
defined by RSTGTN, else reset all the gates. The corresponding secure IRQ notification state machine(s)
are also reset.
RSTGSM_
RSTGMS_ NOTE: This field contains sub-fields that vary depending on whether it is being read or written. Sub-fields
RSTGDP indicated as having read access are valid only for read operations. Sub-fields indicated as having
write access are valid only for write operations. Bit numbering in the descriptions begins with the
most significant bit numbered 0. See the following table for details.
Access Sub-Field Description
Read-Only 7-6 Reserved. Always reads 0.
Reserved
5-4 Reset Gate Finite State Machine. Reads of the SEMA4_RSTGT
register return the encoded state machine value. The reset state
RSTGSM
machine is maintained in a 2-bit, 3-state implementation, defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified gate
reset(s). After the reset is performed, this machine returns to the
idle (waiting for first data pattern write) state. Note that the
RSTGSM = 0b10 state is valid for only a single machine cycle, so
it is impossible for a read to return this value
11 This state encoding is never used and therefore reserved.
3 Reserved. Always reads 0.
Reserved
2-0 Reset Gate Bus Master. This 3-bit read-only field records the logical
number of the bus master performing the gate reset function. The reset
RSTGMS
function requires that the two consecutive writes to this register be
initiated by the same bus master to succeed. This field is updated each
time a write to this register occurs. The association between system
bus master port numbers, the associated bus master device and the
logical processor number is SoC-specific. See the chip-specific
information section.
Write-Only 7-0 Reset Gate Data Pattern. This write-only field is accessed with the
specified data patterns on the two consecutive writes to enable the gate
RSTGDP
reset mechanism. For the first write, RSTGDP = 0xe2 while the second
write requires RSTGDP = 0x1d.
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4.4.6.5 Semaphores (Secure) Reset IRQ Notification
(SEMA4_RSTNTF)
As with the case of the secure reset function of the hardware gates, it is recognized that
system operation may require a reset function to re-initialize the state of the IRQ
notification logic without requiring a system-level reset.
To support this special notification reset requirement, the Semaphores module
implements a "secure" reset mechanism which allows an IRQ notification (or all the
notifications) to be initialized by following a specific dual-write access pattern. When
successful, the specified IRQ notification state machine(s) are reset. Using a technique
similar to that required for the servicing of a software watchdog timer, the secure reset
mechanism requires two consecutive writes with predefined data patterns from the same
processor to force the clearing of the IRQ notification(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTNTF memory location. The
least significant byte (SEMA4_RSTNTF[RSTNDP]) must be 0x47; the most
significant byte is a "don't_care" for this reference.
2. The same processor then performs a second 16-bit write to the SEMA4_RSTNTF
location. For this write, the lower byte (SEMA4_RSTNTF[RSTNDP]) is the logical
complement of the first data pattern (0xb8) and the upper byte
(SEMA4_RSTNTF[RSTNTN]) specifies the notification(s) to be reset. This field can
specify a single notification be cleared, or that all notifications are cleared.
3. Reads of the SEMA4_RSTNTF location return information on the 2-bit state
machine (SEMA4_RSTNTF[RSTNSM]) which implements this function, the bus
master performing the reset (SEMA4_RSTNTF[RSTNMS]) and the notification
number(s) last cleared (SEMA4_RSTNTF[RSTNTN]). Reads of the
SEMA4_RSTNTF register do not affect the secure reset finite state machine in any
manner.
Address: 30AC_0000h base + 104h offset = 30AC_0104h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read RSTNTN RSTNSM_RSTNMS_RSTNDP
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SEMA4_RSTNTF field descriptions
Field Description
15–8 Reset Notification Number. This 8-bit field specifies the specific IRQ notification state machine to be reset.
RSTNTN This field is updated by the second write.
This field contains the hexidecimal value of the gate number. If RSTNTN < 64, then reset the single IRQ
notification machine defined by RSTNTN, else reset all the notifications.
Table continues on the next page...
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On-Chip RAM Memory Controller (OCRAM)
SEMA4_RSTNTF field descriptions (continued)
Field Description
RSTNSM_
RSTNMS_ NOTE: This field contains sub-fields that vary depending on whether it is being read or written. Sub-fields
RSTNDP indicated as having read access are valid only for read operations. Sub-fields indicated as having
write access are valid only for write operations. Bit numbering in the descriptions begins with the
most significant bit numbered 0. See the following table for details.
Access Sub-Field Description
Read-Only 7-6 Reserved. Always reads 0.
Reserved
5-4 Reset Notification Finite State Machine. Reads of the SEMA4_RSTNTF
register return the encoded state machine value. The reset state
RSTNSM
machine is maintained in a 2-bit, 3-state implementation, defined as:
00 Idle, waiting for the first data pattern write.
01 Waiting for the second data pattern write.
10 The 2-write sequence has completed. Generate the specified
notification reset(s). After the reset is performed, this machine
returns to the idle (waiting for first data pattern write) state. Note
the RSTNSM = 10 state is valid for only a single machine cycle,
so it is impossible for a read to return this value.
11 This state encoding is never used and therefore reserved..
3 Reserved. Always reads 0.
Reserved
2-0 Reset Notification Bus Master. This 3-bit read-only field records the
logical number of the bus master performing the notification reset
RSTNMS
function. The reset function requires that the two consecutive writes to
this register be initiated by the same bus master to succeed. This field
is updated each time a write to this register occurs. The association
between system bus master port numbers, the associated bus master
device and the logical processor number is SoC-specific. See the chip-
specific information section.
Write-Only 7-0 Reset Notification Data Pattern. This write-only field is accessed with
the specified data patterns on the two consecutive writes to enable the
RSTNDP
notification reset mechanism. For the first write, RSTNDP = 0x47 while
the second write requires RSTNDP = 0xb8.
4.5 On-Chip RAM Memory Controller (OCRAM)
4.5.1 Overview
The OCRAM block is implemented as an slave module on the 64-bit system AXI bus.
Designed as a simple on-chip memory controller, it supports only one AXI port with
memory banks. For the AXI port, the read and write transactions are handled by two
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independent modules. As it is possible to have simultaneous read and write request from
the AXI bus, each memory bank has an arbiter with round-robin scheme. After
arbitration, the granted read or write access command can then be issued to the memory
cell through a read/write MUX.
The memory banks are organized with the lower 2 bits of the address which is the AXI
bus address and is 64 bits aligned interleaved. This allows a read access and a write
access to be processed at the same time if they are targeted to different memory banks.
Various options are provided for adding a pipeline in a read/write access, in order to
ensure flexible timing control at both high and low frequencies.
4.5.1.1 Block diagram
The OCRAM block diagram is shown in the figure below.
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On-Chip RAM Memory Controller (OCRAM)
OCRAM CONTROLLER
RDATA 0[63:0]
RDATA 1[63:0]
MUX RDATA 2[63:0]
RDATA 3[63:0]
AXI RADDR
Read Read Control
Control
Module
AXI RDATA MEM_SEL[3..0]
RAM
MUX
RAM MEM_WE[3..0]
RAM
MUX
RAM
MUX
Write Control MUX
AXI WADDR
MEM_ADDR[3..0]
WDATA [63:0]
AXI WDATA Write
Control
Module MEM_WDATA [3..0]
AXI WRESP
RD
REQ
DEC
Arbiter
Arbiter
Arbiter
Timing Arbiter
WR
Configuration
REQ
DEC
Figure 4-11. OCRAM Block Diagram
4.5.2 Functional Description
4.5.2.1 Read/Write Arbitration
The detailed rules used in arbitration are as follows:
• If there is no granted read or write in the last cycle, and there is only a read request or
a write request, the request will be granted.
• If there is no granted read or write in the last cycle, and there are both read or write
requests coming in at the same time, the read request will be granted first.
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• If a granted read/write transaction has just finished, the write/read request will have
the higher priority in the next cycle.
• If the first read/write access request in a transaction is granted, all the data transfer in
this burst will be finished before the next arbitration begins, that is, the round-robin
arbitration mechanism is based on AXI transaction, not data access.
4.5.3 Programmable Registers
There are no programmable registers in this block. However, OCRAM configurable bits
can be found in the IOMUX Controller (IOMUXC) general purpose registers as below.
• TrustZone bits: IOMUXC_GPR_GPR10 and IOMUXC_GPR_GPR11
4.6 Network Interconnect Bus System (NIC)
4.6.1 Overview
This section provides an overview of the NIC-301 (Network Inter-Connect) AXI arbiter
IP.on chip Network Interconnection Bus System. The Bus System is composed of two
kinds of IP
The NIC-301 (by Arm Ltd.) is a configurable AXI arbiter between several masters and
slaves. The NIC-301 IP is designed so that many configuration options are selected at the
hardware design stage, determined by SoC characteristics and needs, while several other
configuration options are software-controlled.
• NIC-301 (Network Inter-Connect) AXI arbiter IP
The NIC-301 (by Arm Ltd.) is a configurable AXI arbiter between several masters
and slaves. The NIC-301 IP is designed so that many configuration options are
selected at the hardware design stage, determined by SoC characteristics and needs,
while several other configuration options are software-controlled.
• NoC (Network on Chip) fabric IP
The NoC (by Arteris Ltd.) is a configurable high efficiency and performance fabric IP.
Similar to the NIC-301 IP the majority design options are configured during hardware
design stage. Mean while those application specific configurations are required
to be configured by software.
NOTE
The NIC-301 and NoC default settings are configured by NXP's
board support package (BSP), and in most cases should not be
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AHB to IP Bridge (AIPSTZ)
modified by the customer. The default settings have gone
through exhaustive testing during the validation of the part, and
have proven to work well for the part's intended target
applications. Changes to the default settings may result in a
degradation in system performance.
4.7 AHB to IP Bridge (AIPSTZ)
4.7.1 Overview
This section provides an overview of the AHB to IP Bridge (AIPSTZ). This particular
peripheral is designed as the bridge between AHB bus and peripherals with the lower
bandwidth IP Slave (IPS) buses.
4.7.1.1 Features
The following list summarizes the key features of the bridge:
• The bridge supports the IPS slave bus signals.
• The bridge supports 8-, 16-, and 32-bit IPS peripherals. (Accesses larger than the size
of a peripheral are not supported, except to 32-bit memory.)
• The bridge supports a pair of IPS accesses for 64-bit and certain misaligned AHB
transfers to 32-bit memory in 64-bit platforms.
• The bridge directly supports up to 32 64-Kbyte external IPS peripherals, and 2 global
external IPS peripheral spaces. The bridge occupies 1 MBytes of total address space.
• The bridge provides configurable per-block and per-master access protections.
Access permissions are based on bus master (e.g. DMA or core) privilege levels and
resource domain. More details on the protection features and configuration can be
found in the Security Reference Manual
• Peripheral read transactions require a minimum of 2 hclk clocks, and unbuffered
write transactions require a minimum of 3 hclk clocks.
• The bridge uses one single asynchronous reset and one global clock.
4.7.2 Clocks
The following table describes the clock sources for AIPSTZ. Please see Clock Controller
Module (CCM) for clock setting, configuration and gating information.
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Table 4-14. AIPSTZ Clocks
Clock name Clock Root Description
hclk ahb_clk_root Module clock
4.7.3 Functional Description
The AIPS bridge serves as a protocol translator between the AHB system bus and the IP
bus.
Support is provided for generating a pair of 32-bit IP bus accesses when targeted by a 64-
bit system bus access, or a misaligned access which crosses a 32-bit boundary. No other
bus-sizing access support is provided.
The AHB to IP bridge is the interface between the AHB and on-chip IPS peripherals,
which are sub-blocks containing readable/writable control and status registers.
The AHB master reads and writes these registers through the AIPSTZ. The bridge
generates block enables, the block address, transfer attributes, byte enables and write data
as inputs to the IPS peripherals. The bridge captures read data from the IPS interface and
drives it on the AHB.
Each bridge that connects to the IPS (or peripherals) are referred as AIPS. The chip has
several separate AIPS modules, and peripherals are grouped and assigned under each
AIPS block. The list of peripherals are indicated as n-1, ... and n-x for AIPS-1, ... and
AIPS-x respectively.
AIPS occupies a 1-Mbyte portion of the address space. The register maps of the IPS
peripherals are located on 64-Kbyte boundaries. Each IPS peripheral is allocated one 64-
Kbyte block of the memory map, and is activated by one of the block enables from the
bridge. Up to thirty-two 64-Kbyte external IPS peripherals may be implemented,
occupying contiguous blocks of 64-Kbytes. Two global external IPS block enables are
available for the remaining address space to allow for customization and expansion of
addressed peripheral devices. In addition, a single "non-global" block enable is also
asserted whenever any of the thirty-two non-global block enables is asserted.
The bridge is responsible for indicating to IPS peripherals if an access is in supervisor or
user mode. It may block user mode accesses to certain IPS peripherals or it may allow the
individual IPS peripherals to determine if user mode accesses are allowed. In addition,
peripherals may be designated as write-protected.
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The bridge supports the notion of "trusted" masters for security purposes. Masters may be
individually designated as trusted for reads, trusted for writes, or trusted for both reads
and writes, as well as being forced to look as though all accesses from a master are in
user-mode privilege level. Refer to AIPSTZ Memory Map/Register Definition for more
information.
The AIPSTZ prevents access to a peripheral if the transaction originated from a source
from a resource domain that has been explicitly omitted. Resource domains are assigned
in the RDC submodule. Please refer to the RDC chapter for programming details.
All peripheral devices are expected to only require aligned accesses equal to or smaller in
size than the peripheral size. An exception to this rule is supported for 32-bit peripherals
to allow memory to be placed on the IPS.
4.7.4 Access Protections
The AIPSTZ bridge provides programmable access protections for both masters and
peripherals. It allows the privilege level of a master to be overridden, forcing it to user-
mode privilege, and allows masters to be designated as trusted or untrusted.
Peripherals may require supervisor privilege level for access, may restrict access to a
trusted master only, and may be write-protected. IP bus peripherals are subject to access
control policies set in both CSU registers and AIPSTZ registers. An access is blocked if it
is denied by either policy.
Masters and peripherals are assigned to one or more resource domains in the RDC
submodule (see the RDC chapter for details). Depending on RDC programming, masters
transactions through the AIPSTZ may or may not be allowed access to peripherals in
different resource domains.
4.7.5 Access Support
Aligned 64-bit accesses, aligned and misaligned word and half word accesses, as well as
byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to
allow memory to be placed on the IPS.
Peripheral registers must not be misaligned, although no explicit checking is performed
by the AIPS bridge. The bridge will perform two IPS transfers for 64-bit accesses, word
accesses with byte offsets of 1, 2, or 3, and for half word accesses with a byte offset of 3.
All other accesses will be performed with a single IPS transfer.
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Only aligned half word and byte accesses are supported for 16-bit peripherals. All other
accesses types are unsupported, and results of such accesses are undefined. They are not
terminated with an error response.
Only byte accesses are supported for 8-bit peripherals. All other accesses types are
unsupported, and results of such accesses are undefined. They are not terminated with an
error response.
4.7.6 Initialization Information
The AIPS bridge should be programmed before use.
The following registers should be initialized: The Master Privilege Registers
(AIPSTZ_MPRs), the Peripheral Access Control registers (AIPSTZ_PACRs), and the
Off-platform Peripheral Access Control registers (AIPSTZ_OPACRs) described in
AIPSTZ Memory Map/Register Definition.
4.7.6.1 Security Block
The AIPSTZ contains a security block that is connected to each off-platform peripheral.
This block filters accesses based on write/read, non-secure, and supervisor signals.
Each peripheral can be individually configured to allow or deny each of the following
transactions as described in the table below:
Table 4-15. Peripheral Access Configuration options
Config Bit Write Non-Secure Supervisor Meaning
0 0 0 0 Secure User Read
1 0 0 1 Secure Supervisor Read
2 0 1 0 Non-Secure User Read
3 0 1 1 Non-Secure Supervisor Read
4 1 0 0 Secure User Write
5 1 0 1 Secure Supervisor Write
6 1 1 0 Non-Secure User Write
7 1 1 1 Non-Secure Supervisor Write
Each peripheral has a security configuration (sec_config_X) input for determining
whether to allow or deny a given access type. These are 8-bit vectors, with each bit
corresponding to one of the transactions above as listed in the Config Bit column of
Table 4-15. If the bit is asserted (1'b1), the transaction is allowed. If the bit is negated
(1'b0), the transaction is not allowed.
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For example, if peripheral 0 is configured as follows:
sec_config_0 [7:0] = 8'b0011_0011
This peripheral can only be accessed by secure transactions. Bits 0, 1, 4, and 5 are
asserted and these bits refer to the four types of secure transactions. If an insecure
transaction is attempted to this peripheral, it will result in an error.
Eight bits per peripheral across an entire system can result in a large number of
configuration bits that must be assigned and controlled, most likely in a series of registers
in another block. To reduce the number of register bits required predefined sets of
security profiles can be defined and encapsulated in an external security translation block.
The table below describes one set of security profiles that has been proposed for use with
the AIPSTZ.
Table 4-16. Security Levels
CSU_SEC_LEVEL Non-Secure User Non-Secure Secure User Secure Supervisor
Supervisor
0 RD+WR RD+WR RD+WR RD+WR
1 NOT ALLOWED RD+WR RD+WR RD+WR
2 Read Only Read Only RD+WR RD+WR
3 NOT ALLOWED Read Only RD+WR RD+WR
4 NOT ALLOWED NOT ALLOWED RD+WR RD+WR
5 NOT ALLOWED NOT ALLOWED NOT ALLOWED RD+WR
6 NOT ALLOWED NOT ALLOWED Read Only Read Only
7 NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED
Information regarding CSU is provided in the Security Reference Manual. Contact your
NXP representative for information about obtaining this document.
A 3-bit input, 8-bit output translation block can be used such that only three register bits
are required to set the security profile and the translation block will drive the correct 8-bit
configuration vector. Each peripheral connected to the AIPSTZ would require this
translation block. The top level AIPSTZ has this three bit input line `csu_sec_level[2:0]'
corresponding to each peripheral X.
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4.7.7 Off-Platform Peripherals Index
The off-platform peripherals index allocation is shown in the following table.
Table 4-17. External IPS Peripherals
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4 AIPSTZ5
OPAC31 Reserved QoSC ENET2_TSN Reserved Reserved
OPAC30 CSU Reserved ENET1 NOC BLK_CTL Reserved
OPAC29 RDC PERFMON2 SDMA HDMI_TX Reserved
OPAC28 SEMAPHORE2 PERFMON1 Reserved Reserved
OPAC27 SEMAPHORE1 Reserved QSPI Reserved Reserved
OPAC26 GPC Reserved Reserved Reserved Reserved
OPAC25 SRC Reserved Reserved Reserved Reserved
OPAC24 CCM Reserved Reserved TZASC Reserved
OPAC23 SNVS_HP Reserved Reserved Reserved Reserved
OPAC22 ANA_PLL Reserved uSDHC3 Reserved Reserved
OPAC21 OCOTP_CTRL Reserved uSDHC2 Reserved Reserved
OPAC20 IOMUXC_GPR Reserved uSDHC1 Reserved Reserved
OPAC19 IOMUXC Reserved Reserved Reserved Reserved
OPAC18 Reserved Reserved Reserved Reserved Reserved
OPAC17 Reserved Reserved Reserved HSIOMIX Reserved
BLK_CTL
OPAC16 Reserved GPT4 Reserved PCIE_PHY1 Reserved
OPAC15 GPT3 GPT5 Reserved Reserved Reserved
OPAC14 GPT2 GPT6 I2C6 Reserved Reserved
OPAC13 GPT1 Reserved I2C5 Reserved Reserved
OPAC12 OCRAM_S System SEMAPHORE_HS MEDIAMIX Reserved
Counter_CTRL BLK_CTL
OPAC11 OCRAM System MU_1_B (A53, M7) LVDS2 Reserved
Counter_CMP
OPAC10 WDOG3 System MU_1_A (A53,M7) LVDS1 Reserved
Counter_RD
OPAC9 WDOG2 PWM4 Reserved LCDIF2 MU_3_B (M7,
Audio Processor)
OPAC8 WDOG1 PWM3 IRQ_STEER LCDIF1 MU_3_A (M7,
(Audio Processor) Audio Processor)
OPAC7 ANA_OSC PWM2 Reserved Reserved MU_2_B (A53,
Audio Processor
OPAC6 ANA_TSENSOR PWM1 UART4 MIPI_DSI1 MU_2_A (A53,
Audio Processor)
OPAC5 Reserved Reserved I2C4 MIPI_CSI2 eDMA
Channels[31:16] at
4KB/ch
Table continues on the next page...
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Table 4-17. External IPS Peripherals (continued)
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4 AIPSTZ5
OPAC4 GPIO5 Reserved I2C3 MIPI_CSI1 eDMA
Channels[15:0] at
4KB/ch
OPAC3 GPIO4 Reserved I2C2 IPS Dewarp eDMA
Management Page
OPAC2 GPIO3 Reserved I2C1 ISP2 AUDIO BLK_CTRL
OPAC1 GPIO2 Reserved Reserved ISP1 SDMA2
OPAC0 GPIO1 Reserved Reserved ISI SDMA3
Global external IPS peripheral
OPAC ID AIPSTZ1 AIPSTZ2 AIPSTZ3 AIPSTZ4 AIPSTZ5
OPAC33 Reserved Reserved CAAM Reserved Reserved
OPAC32 Reserved Reserved SPBA1: CAN_FD2, Reserved SPBA2: AUDIO
CAN_FD1, UART2, XCVR RX (eARC),
UART3, UART1, HDMI TX AUDLNK
eCSPI3, eCSPI2, MSTR, PDM
eCSPI1. (MICFIL), ASRC,
SAI7, SAI6, SAI5,
SAI3, SAI2, SAI1.
4.7.8 AIPSTZ Memory Map/Register Definition
The memory map for the AIPS SW-visible registers is shown in the table below.
The MPROT and OPACR fields are 4 bits in width. Some bits may be reserved
depending on device.
AIPSTZ memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3000_0000 Master Priviledge Registers (AIPSTZ1_MPR) 32 R/W 7700_0000h 4.7.8.1/174
Off-Platform Peripheral Access Control Registers
3000_0040 32 R/W 4444_4444h 4.7.8.2/176
(AIPSTZ1_OPACR)
Off-Platform Peripheral Access Control Registers
3000_0044 32 R/W 4444_4444h 4.7.8.3/179
(AIPSTZ1_OPACR1)
Off-Platform Peripheral Access Control Registers
3000_0048 32 R/W 4444_4444h 4.7.8.4/182
(AIPSTZ1_OPACR2)
Off-Platform Peripheral Access Control Registers
3000_004C 32 R/W 4444_4444h 4.7.8.5/185
(AIPSTZ1_OPACR3)
Off-Platform Peripheral Access Control Registers
3000_0050 32 R/W 4444_4444h 4.7.8.6/188
(AIPSTZ1_OPACR4)
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AIPSTZ memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3040_0000 Master Priviledge Registers (AIPSTZ2_MPR) 32 R/W 7700_0000h 4.7.8.1/174
Off-Platform Peripheral Access Control Registers
3040_0040 32 R/W 4444_4444h 4.7.8.2/176
(AIPSTZ2_OPACR)
Off-Platform Peripheral Access Control Registers
3040_0044 32 R/W 4444_4444h 4.7.8.3/179
(AIPSTZ2_OPACR1)
Off-Platform Peripheral Access Control Registers
3040_0048 32 R/W 4444_4444h 4.7.8.4/182
(AIPSTZ2_OPACR2)
Off-Platform Peripheral Access Control Registers
3040_004C 32 R/W 4444_4444h 4.7.8.5/185
(AIPSTZ2_OPACR3)
Off-Platform Peripheral Access Control Registers
3040_0050 32 R/W 4444_4444h 4.7.8.6/188
(AIPSTZ2_OPACR4)
3080_0000 Master Priviledge Registers (AIPSTZ3_MPR) 32 R/W 7700_0000h 4.7.8.1/174
Off-Platform Peripheral Access Control Registers
3080_0040 32 R/W 4444_4444h 4.7.8.2/176
(AIPSTZ3_OPACR)
Off-Platform Peripheral Access Control Registers
3080_0044 32 R/W 4444_4444h 4.7.8.3/179
(AIPSTZ3_OPACR1)
Off-Platform Peripheral Access Control Registers
3080_0048 32 R/W 4444_4444h 4.7.8.4/182
(AIPSTZ3_OPACR2)
Off-Platform Peripheral Access Control Registers
3080_004C 32 R/W 4444_4444h 4.7.8.5/185
(AIPSTZ3_OPACR3)
Off-Platform Peripheral Access Control Registers
3080_0050 32 R/W 4444_4444h 4.7.8.6/188
(AIPSTZ3_OPACR4)
30C0_0000 Master Priviledge Registers (AIPSTZ5_MPR) 32 R/W 7700_0000h 4.7.8.1/174
Off-Platform Peripheral Access Control Registers
30C0_0040 32 R/W 4444_4444h 4.7.8.2/176
(AIPSTZ5_OPACR)
Off-Platform Peripheral Access Control Registers
30C0_0044 32 R/W 4444_4444h 4.7.8.3/179
(AIPSTZ5_OPACR1)
Off-Platform Peripheral Access Control Registers
30C0_0048 32 R/W 4444_4444h 4.7.8.4/182
(AIPSTZ5_OPACR2)
Off-Platform Peripheral Access Control Registers
30C0_004C 32 R/W 4444_4444h 4.7.8.5/185
(AIPSTZ5_OPACR3)
Off-Platform Peripheral Access Control Registers
30C0_0050 32 R/W 4444_4444h 4.7.8.6/188
(AIPSTZ5_OPACR4)
32C0_0000 Master Priviledge Registers (AIPSTZ4_MPR) 32 R/W 7700_0000h 4.7.8.1/174
Off-Platform Peripheral Access Control Registers
32C0_0040 32 R/W 4444_4444h 4.7.8.2/176
(AIPSTZ4_OPACR)
Off-Platform Peripheral Access Control Registers
32C0_0044 32 R/W 4444_4444h 4.7.8.3/179
(AIPSTZ4_OPACR1)
Off-Platform Peripheral Access Control Registers
32C0_0048 32 R/W 4444_4444h 4.7.8.4/182
(AIPSTZ4_OPACR2)
Off-Platform Peripheral Access Control Registers
32C0_004C 32 R/W 4444_4444h 4.7.8.5/185
(AIPSTZ4_OPACR3)
Off-Platform Peripheral Access Control Registers
32C0_0050 32 R/W 4444_4444h 4.7.8.6/188
(AIPSTZ4_OPACR4)
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AHB to IP Bridge (AIPSTZ)
4.7.8.1 Master Priviledge Registers (AIPSTZx_MPR)
Each AIPSTZ_MPR specifies 16 4-bit fields defining the access privilege level
associated with a bus master in the platform, as well as specifying whether write accesses
from this master are bufferable shown in Table 4-18
The registers provide one field per bus master, where field 15 corresponds to master 15,
field 14 to master 14,... field 0 to master 0 (typically the processor core). The master
index allocation is shown in the table below.
Table 4-18. MPROT Field
Bit Field Description
3 MBW Master Buffer Writes - This bit determines whether the AIPSTZ is enabled to buffer writes
from this master.
2 MTR Master Trusted for Reads - This bit determines whether the master is trusted for read
accesses.
1 MTW Master Trusted for Writes - This bit determines whether the master is trusted for write
accesses.
0 MPL Master Privilege Level - This bit determines how the privilege level of the master is
determined.
NOTE
The reset value is set to 0000_0000_7700_0000, which makes
master 0 and master 1 (Arm CORE) the trusted masters.
Trusted software can change the settings after reset.
Table 4-19. Master Index Allocation
Master Index Master Name Comments
Master 0 All masters excluding Arm core Share the same number allocation.
Master 1 Arm A53 core
Master 3 SDMA
Master 5 Arm M7 core
Master 6 HIFI4 Audio Processor
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MPROT0 MPROT1 MPROT2 MPROT3 Reserved MPROT5 Reserved Reserved
Reset 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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AIPSTZx_MPR field descriptions
Field Description
31–28 Master 0 Priviledge, Buffer, Read, Write Control
MPROT0
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
27–24 Master 1 Priviledge, Buffer, Read, Write Control
MPROT1
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
23–20 Master 2 Priviledge, Buffer, Read, Write Control
MPROT2
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
19–16 Master 3 Priviledge, Buffer, Read, Write Control.
MPROT3
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
Table continues on the next page...
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AHB to IP Bridge (AIPSTZ)
AIPSTZx_MPR field descriptions (continued)
Field Description
15–12 This field is reserved.
- Reserved
11–8 Master 5 Priviledge, Buffer, Read, Write Control.
MPROT5
xxx0 MPL0 — Accesses from this master are forced to user-mode (ips_supervisor_access is forced to
zero) regardless of the hprot[1] access attribute.
xxx1 MPL1 — Accesses from this master are not forced to user-mode. The hprot[1] access attribute is
used directly to determine ips_supervisor_access.
xx0x MTW0 — This master is not trusted for write accesses.
xx1x MTW1 — This master is trusted for write accesses.
x0xx MTR0 — This master is not trusted for read accesses.
x1xx MTR1 — This master is trusted for read accesses.
0xxx MBW0 — Write accesses from this master are not bufferable
1xxx MBW1 — Write accesses from this master are allowed to be buffered
7–4 This field is reserved.
- Reserved
- This field is reserved.
Reserved
4.7.8.2 Off-Platform Peripheral Access Control Registers
(AIPSTZx_OPACR)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-20
Table 4-20. OPAC Field
Bit Field Description
3 BW Buffer Writes - This bit determines whether write accesses to this peripheral are allowed to
be buffered.1
2 SP Supervisor Protect - This bit determines whether the peripheral requires supervisor privilege
level for access.
1 WP Write Protect - This bit determines whether the peripheral allows write accesses.
0 TP Trusted Protect - This bit determines whether the peripheral allows accesses from an
untrusted master.
1. Buffered writes are not available for AIPSTZ. This bit should be set to '0'.
Address: Base address + 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC0 OPAC1 OPAC2 OPAC3 OPAC4 OPAC5 OPAC6 OPAC7
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
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AIPSTZx_OPACR field descriptions
Field Description
31–28 Off-platform Peripheral Access Control 0
OPAC0
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 1
OPAC1
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 2
OPAC2
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 3
OPAC3
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AHB to IP Bridge (AIPSTZ)
AIPSTZx_OPACR field descriptions (continued)
Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 4
OPAC4
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 5
OPAC5
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 6
OPAC6
xxx0 TP0 — Accesses from an untrusted master are allowed.
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AIPSTZx_OPACR field descriptions (continued)
Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC7 Off-platform Peripheral Access Control 7
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
4.7.8.3 Off-Platform Peripheral Access Control Registers
(AIPSTZx_OPACR1)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-20
Address: Base address + 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC8 OPAC9 OPAC10 OPAC11 OPAC12 OPAC13 OPAC14 OPAC15
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
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AIPSTZx_OPACR1 field descriptions
Field Description
31–28 Off-platform Peripheral Access Control 8
OPAC8
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 9
OPAC9
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 10
OPAC10
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 11
OPAC11
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AIPSTZx_OPACR1 field descriptions (continued)
Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 12
OPAC12
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 13
OPAC13
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 14
OPAC14
xxx0 TP0 — Accesses from an untrusted master are allowed.
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AHB to IP Bridge (AIPSTZ)
AIPSTZx_OPACR1 field descriptions (continued)
Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC15 Off-platform Peripheral Access Control 15
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
4.7.8.4 Off-Platform Peripheral Access Control Registers
(AIPSTZx_OPACR2)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-20
Address: Base address + 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC16 OPAC17 OPAC18 OPAC19 OPAC20 OPAC21 OPAC22 OPAC23
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
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AIPSTZx_OPACR2 field descriptions
Field Description
31–28 Off-platform Peripheral Access Control 16
OPAC16
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 17
OPAC17
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 18
OPAC18
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 19
OPAC19
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AHB to IP Bridge (AIPSTZ)
AIPSTZx_OPACR2 field descriptions (continued)
Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 20
OPAC20
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 21
OPAC21
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 22
OPAC22
xxx0 TP0 — Accesses from an untrusted master are allowed.
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AIPSTZx_OPACR2 field descriptions (continued)
Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC23 Off-platform Peripheral Access Control 23
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
4.7.8.5 Off-Platform Peripheral Access Control Registers
(AIPSTZx_OPACR3)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-20
Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC24 OPAC25 OPAC26 OPAC27 OPAC28 OPAC29 OPAC30 OPAC31
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
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AIPSTZx_OPACR3 field descriptions
Field Description
31–28 Off-platform Peripheral Access Control 24
OPAC24
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 25
OPAC25
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
23–20 Off-platform Peripheral Access Control 26
OPAC26
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
19–16 Off-platform Peripheral Access Control 27
OPAC27
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AIPSTZx_OPACR3 field descriptions (continued)
Field Description
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
15–12 Off-platform Peripheral Access Control 28
OPAC28
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
11–8 Off-platform Peripheral Access Control 29
OPAC29
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
7–4 Off-platform Peripheral Access Control 30
OPAC30
xxx0 TP0 — Accesses from an untrusted master are allowed.
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AIPSTZx_OPACR3 field descriptions (continued)
Field Description
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
OPAC31 Off-platform Peripheral Access Control 31
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
4.7.8.6 Off-Platform Peripheral Access Control Registers
(AIPSTZx_OPACR4)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control
Register (AIPSTZ_OPACR) which defines the access levels supported by the given
block.
Each AIPSTZ_OPACR has the following format shown in Table 4-20
Address: Base address + 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
OPAC32 OPAC33 Reserved
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
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AIPSTZx_OPACR4 field descriptions
Field Description
31–28 Off-platform Peripheral Access Control 32
OPAC32
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
27–24 Off-platform Peripheral Access Control 33
OPAC33
xxx0 TP0 — Accesses from an untrusted master are allowed.
xxx1 TP1 — Accesses from an untrusted master are not allowed. If an access is attempted by an
untrusted master, the access is terminated with an error response and no peripheral access is
initiated on the IPS bus.
xx0x WP0 — This peripheral allows write accesses.
xx1x WP1 — This peripheral is write protected. If a write access is attempted, the access is terminated
with an error response and no peripheral access is initiated on the IPS bus.
x0xx SP0 — This peripheral does not require supervisor privilege level for accesses.
x1xx SP1 — This peripheral requires supervisor privilege level for accesses. The master privilege level
must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the
master must be set. If not, the access is terminated with an error response and no peripheral
access is initiated on the IPS bus.
0xxx BW0 — Write accesses to this peripheral are not bufferable by the AIPSTZ.
1xxx BW1 — Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
- This field is reserved.
Reserved
4.8 Shared Peripheral Bus Arbiter (SPBA)
4.8.1 Overview
The Shared Peripheral Bus Arbiter (SPBA) is a three-to-one IP Bus interface arbiter.
Three masters arbitrate for shared peripheral access through the SPBA.
The SPBA has three primary functions:
• The IP Bus Line switches a master to one peripheral
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Shared Peripheral Bus Arbiter (SPBA)
• The Masters arbiter arbitrates between the three masters to solve concurrent access or
restricted access to peripherals
• The Control Registers and Ownership Control includes a set of registers which are
reachable through software and permit the access scheme to be defined for each
peripheral (Resource Ownership and Access Control). It generates signals for the
external steering logic of interrupts and DMA signals.
4.8.1.1 Block Diagram
The figure below shows the SPBA block diagram
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MASTER A MASTER B MASTER C
mb_dead_owner
ma_dead_owner
mc_dead_owner
Control
Registers
obsc0 Masters
+
IOSRTR Arbitration
obsc31 Ownership
module
Control
SPBA
IP-bus interface
IPMUX
Per0 Per30
Out-of-band signals
Figure 4-12. SPBA Block Diagram
4.8.1.2 Features
The SPBA includes the following features:
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Shared Peripheral Bus Arbiter (SPBA)
• Three IP Bus masters arbitration: Master A, B and C
• Support for DMA masters
• 32-bit data
• Supports up to 32 shared peripherals, each consuming 64 kilobytes of address space
• SPBA can be considered the 33rd peripheral, used for resource ownership and access
control of the 31 peripherals
• Provides 31 sets of out of band steering control (OBSC) signals to the off-block
steering logic
• Operating frequency up to 67 MHz
• Clocks: ipg_clk, ipg_clk_s
4.8.2 Functional description
4.8.2.1 Modes of operation
SPBA behavior is transparent when accessing a peripheral, though it has these distinct
modes of operation.
Reset/Abort
The SPBA has a hardware reset which initializes all registers, arbitration and
peripherals rights registers (PRRs).
An abort signal input is provided allowing each master to abort its current access and
release ownership (in case of master reset sequence).
Functional
Once a master request is granted, its IP Bus signals are steered to the requested
peripheral.
Standby
No clock needed. The SPBA needs clocks only during access to the PRRs, arbitration,
and abort phases. It generates two clock enable signals indicating when the clocks
must be provided.
Configuration
During this phase, a master accesses the SPBA PRRs. The SPBA memory-mapped
registers are seen as a shared peripheral.
4.8.2.2 Masters arbitration
The arbitration mechanism determines which port will control the master port, based on a
simple round-robin arbitration scheme.
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There are several use cases to consider.
• Only one master request per access. The master is switched to the shared peripheral
bus, without arbitration. Figure 4-13 shows the MB request on the global module
enable signal, served without wait state.
• If two masters simultaneously access SPBA, the last granted master is held off using
the <master>_ips_xfr_wait output signal (default value is high). When the master is
granted sips_xfr_wait, shared IP Bus peripheral is connected to
<master>_ips_xfr_wait outputs.
• If three masters simultaneously access SPBA, then the last two granted masters are
held off using <master>_ips_xfr_wait. Figure 4-14 shows a case in which the last
two accesses granted are MA and MB. The requests are used even if they are in the
same cycle.
• If after reset, at the first multiple access, no master has been granted, the priority is
static: Master A (MA), Master B (MB) and last Master C (MC) port.
• No master request. No master switch to shared peripherals.
ipg_clk
mb_ips_module_en
mb_ips_addr[24:0] 0x0000000
mb_ips_xfr_wait
mb_ips_rdata[31:0] valid data
sips_module_en[0]
sips_ips_xfr_wait
sips_rdata[31:0] valid data
Figure 4-13. Example of one master request, no SPBA arbitration
The following figure assumes MA and MB have been the last two masters granted in the
previous transfers (MA then MB).
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Shared Peripheral Bus Arbiter (SPBA)
clk
mb_ips_module_en
mb_ips_addr[24:0] 0x0000000
mb_ips_xfer_wait
mb_ips_rdata[31:0] valid data
ma_ips_module_en
ma_ips_addr[24:0] 0x004000
ma_ips_xfer_wait
ma_ips_rdata[31:0] valid data
mc_ips_module_en
mc_ips_addr[24:0] 0x0008000
mc_ips_xfer_wait
mc_ips_rdata[31:0] valid data
sips_module_en[0]
sips_module_en[1]
sips_module_en[2]
MASTER_GRANTED MC MA MB
Figure 4-14. Example of three master requests: Masters already granted are "waited";
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4.8.2.3 Resource ownership control
The resource ownership control regulates access to the shared peripherals and determines
the steering of out-of-band signals.
4.8.2.3.1 Access control
4.8.2.3.1.1 Peripheral access
The peripheral access (resource access) of the requesting master is given by the
corresponding RAR bit of the Peripheral Right Register. It determines if the master has
access privilege to the resource.
Any attempt at access made by a requesting master whose access privilege bit is not set
(in the PRR) is terminated with a bus error (<master>_ips_xfr_err is asserted by SPBA
logic). The master that owns the resource can lock the peripheral for itself and/or grant
other masters access to the peripheral by setting the appropriate bit(s) in the RAR field.
ipg_clk_s
mb_ips_module_en
mb_ips_addr[24:0] 0x3C008
mb_ips_wdata[31:0] 31'd2
mb_ips_rwb
mb_ips_xfr_wait
obsc2[4:0] 5'b10010
Master B is taking ownership of peripheral 2 by writing 3'b010 in the SPBA peripheral 2 right register (rarfield)
This ownership can be checked on obsc2 output as roi2[1:0] = 2'b10 and rar2[2:0] = 3'b010
(obsc[4:0] = {roi2[1], roi2[0], rar2[2], rar2[1], rar2[0]})
Figure 4-15. Example of one master B gaining ownership of peripheral 2
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Shared Peripheral Bus Arbiter (SPBA)
4.8.2.3.1.2 Peripheral Right Register access
The ROI bits of the Peripheral Right Register (PRR) determine which master is allowed
to make write access to PRR. The identification of the requesting master is compared to
the ROI bits of the PRR to determine if the master has ownership of the corresponding
register.
Any attempted write access to a PRR already owned by another master will be ignored.
4.8.2.3.2 Owner election
When the peripheral is not owned by any master (ROI="00", after coming out of reset for
instance), the first master to perform successfully a write to the RAR bits of the PRR is
granted ownership of the peripheral and its associated PRR.
After writing to the PRR (RAR bit(s)), the master must read it back to make sure that it
was granted ownership. If the RMO field is 2'b11, then the ownership claim is successful.
If RMO is 2'b10, another master claimed ownership before this master was able to
complete its write. This resolves the case in which two or more masters attempt to write
the PRR at the same time; only the first master will be granted ownership. However all
masters must read the PRR to determine if this case occurred, and if so, whether they
were the first master which was granted ownership.
NOTE
A master that has been granted ownership of the PRR does not
automatically have the right access to the peripheral; it must
still set its own RAR bits in the PRR to access the peripheral.
4.8.2.3.3 Ending ownership
Ownership may be voluntarily ended by the owning master, or automatically upon
assertion of a master-specific dead_owner signal.
The former is appropriate for software-controlled yielding of ownership. The latter is
appropriate for automatic yielding of ownership when the owner has gone into reset.
When a master is reset, it clears the ROI bits of the PRRs owned by the corresponding
master. When the owner is dead (in reset), all peripherals previously owned by that
master must be changed to the un-owned state.
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NOTE
It is the programmer's responsibility to make sure the
peripherals are placed in an appropriate state before ending
ownership.
4.8.2.3.3.1 Software Controlled Ownership Ending
The ROI bits will be automatically cleared when the master that owns the PRR access
right clears (write) the RAR bits (Table 2).
It will then end the ownership of the PRR.
4.8.2.3.4 The Un-owned State
During the time when the peripheral is un-owned (i.e the ROI field contains all 0's), all
masters have full access to it (RAR bits can then be modified by a master if ROI[1:0] =
2'b0).
In such cases it is necessary for software to ensure any necessary coherency in the
resource, there is no hardware protection.
4.8.2.4 Clocks
The table found here describes the clock sources for SPBA.
Please see Clock Controller Module (CCM) for clock setting, configuration and gating
information.
Table 4-21. SPBA Clocks
Clock name Clock Root Description
ipg_clk ipg_clk_root Peripheral clock
ipg_clk_s ipg_clk_root Peripheral access clock
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Shared Peripheral Bus Arbiter (SPBA)
4.8.3 SPBA Memory Map/Register Definition
The SPBA control registers (Peripheral Right Registers) are mapped as a virtual shared
peripheral.
SPBA can support up to 32 shared peripherals. Each of them has its own Peripheral Right
Register (PRR) accessible within the SPBA memory-mapped registers, and consists of
the Requesting Master Owner, the Resource Owner ID and the Resource Access Right
fields.
SPBA memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
308F_0000 Peripheral Rights Register (SPBA1_PRR0) 32 R/W 0000_0007h 4.8.3.1/200
308F_0004 Peripheral Rights Register (SPBA1_PRR1) 32 R/W 0000_0007h 4.8.3.1/200
308F_0008 Peripheral Rights Register (SPBA1_PRR2) 32 R/W 0000_0007h 4.8.3.1/200
308F_000C Peripheral Rights Register (SPBA1_PRR3) 32 R/W 0000_0007h 4.8.3.1/200
308F_0010 Peripheral Rights Register (SPBA1_PRR4) 32 R/W 0000_0007h 4.8.3.1/200
308F_0014 Peripheral Rights Register (SPBA1_PRR5) 32 R/W 0000_0007h 4.8.3.1/200
308F_0018 Peripheral Rights Register (SPBA1_PRR6) 32 R/W 0000_0007h 4.8.3.1/200
308F_001C Peripheral Rights Register (SPBA1_PRR7) 32 R/W 0000_0007h 4.8.3.1/200
308F_0020 Peripheral Rights Register (SPBA1_PRR8) 32 R/W 0000_0007h 4.8.3.1/200
308F_0024 Peripheral Rights Register (SPBA1_PRR9) 32 R/W 0000_0007h 4.8.3.1/200
308F_0028 Peripheral Rights Register (SPBA1_PRR10) 32 R/W 0000_0007h 4.8.3.1/200
308F_002C Peripheral Rights Register (SPBA1_PRR11) 32 R/W 0000_0007h 4.8.3.1/200
308F_0030 Peripheral Rights Register (SPBA1_PRR12) 32 R/W 0000_0007h 4.8.3.1/200
308F_0034 Peripheral Rights Register (SPBA1_PRR13) 32 R/W 0000_0007h 4.8.3.1/200
308F_0038 Peripheral Rights Register (SPBA1_PRR14) 32 R/W 0000_0007h 4.8.3.1/200
308F_003C Peripheral Rights Register (SPBA1_PRR15) 32 R/W 0000_0007h 4.8.3.1/200
308F_0040 Peripheral Rights Register (SPBA1_PRR16) 32 R/W 0000_0007h 4.8.3.1/200
308F_0044 Peripheral Rights Register (SPBA1_PRR17) 32 R/W 0000_0007h 4.8.3.1/200
308F_0048 Peripheral Rights Register (SPBA1_PRR18) 32 R/W 0000_0007h 4.8.3.1/200
308F_004C Peripheral Rights Register (SPBA1_PRR19) 32 R/W 0000_0007h 4.8.3.1/200
308F_0050 Peripheral Rights Register (SPBA1_PRR20) 32 R/W 0000_0007h 4.8.3.1/200
308F_0054 Peripheral Rights Register (SPBA1_PRR21) 32 R/W 0000_0007h 4.8.3.1/200
308F_0058 Peripheral Rights Register (SPBA1_PRR22) 32 R/W 0000_0007h 4.8.3.1/200
308F_005C Peripheral Rights Register (SPBA1_PRR23) 32 R/W 0000_0007h 4.8.3.1/200
308F_0060 Peripheral Rights Register (SPBA1_PRR24) 32 R/W 0000_0007h 4.8.3.1/200
Table continues on the next page...
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SPBA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
308F_0064 Peripheral Rights Register (SPBA1_PRR25) 32 R/W 0000_0007h 4.8.3.1/200
308F_0068 Peripheral Rights Register (SPBA1_PRR26) 32 R/W 0000_0007h 4.8.3.1/200
308F_006C Peripheral Rights Register (SPBA1_PRR27) 32 R/W 0000_0007h 4.8.3.1/200
308F_0070 Peripheral Rights Register (SPBA1_PRR28) 32 R/W 0000_0007h 4.8.3.1/200
308F_0074 Peripheral Rights Register (SPBA1_PRR29) 32 R/W 0000_0007h 4.8.3.1/200
308F_0078 Peripheral Rights Register (SPBA1_PRR30) 32 R/W 0000_0007h 4.8.3.1/200
308F_007C Peripheral Rights Register (SPBA1_PRR31) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0000 Peripheral Rights Register (SPBA2_PRR0) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0004 Peripheral Rights Register (SPBA2_PRR1) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0008 Peripheral Rights Register (SPBA2_PRR2) 32 R/W 0000_0007h 4.8.3.1/200
30CF_000C Peripheral Rights Register (SPBA2_PRR3) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0010 Peripheral Rights Register (SPBA2_PRR4) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0014 Peripheral Rights Register (SPBA2_PRR5) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0018 Peripheral Rights Register (SPBA2_PRR6) 32 R/W 0000_0007h 4.8.3.1/200
30CF_001C Peripheral Rights Register (SPBA2_PRR7) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0020 Peripheral Rights Register (SPBA2_PRR8) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0024 Peripheral Rights Register (SPBA2_PRR9) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0028 Peripheral Rights Register (SPBA2_PRR10) 32 R/W 0000_0007h 4.8.3.1/200
30CF_002C Peripheral Rights Register (SPBA2_PRR11) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0030 Peripheral Rights Register (SPBA2_PRR12) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0034 Peripheral Rights Register (SPBA2_PRR13) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0038 Peripheral Rights Register (SPBA2_PRR14) 32 R/W 0000_0007h 4.8.3.1/200
30CF_003C Peripheral Rights Register (SPBA2_PRR15) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0040 Peripheral Rights Register (SPBA2_PRR16) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0044 Peripheral Rights Register (SPBA2_PRR17) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0048 Peripheral Rights Register (SPBA2_PRR18) 32 R/W 0000_0007h 4.8.3.1/200
30CF_004C Peripheral Rights Register (SPBA2_PRR19) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0050 Peripheral Rights Register (SPBA2_PRR20) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0054 Peripheral Rights Register (SPBA2_PRR21) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0058 Peripheral Rights Register (SPBA2_PRR22) 32 R/W 0000_0007h 4.8.3.1/200
30CF_005C Peripheral Rights Register (SPBA2_PRR23) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0060 Peripheral Rights Register (SPBA2_PRR24) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0064 Peripheral Rights Register (SPBA2_PRR25) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0068 Peripheral Rights Register (SPBA2_PRR26) 32 R/W 0000_0007h 4.8.3.1/200
30CF_006C Peripheral Rights Register (SPBA2_PRR27) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0070 Peripheral Rights Register (SPBA2_PRR28) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0074 Peripheral Rights Register (SPBA2_PRR29) 32 R/W 0000_0007h 4.8.3.1/200
30CF_0078 Peripheral Rights Register (SPBA2_PRR30) 32 R/W 0000_0007h 4.8.3.1/200
Table continues on the next page...
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Shared Peripheral Bus Arbiter (SPBA)
SPBA memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30CF_007C Peripheral Rights Register (SPBA2_PRR31) 32 R/W 0000_0007h 4.8.3.1/200
4.8.3.1 Peripheral Rights Register (SPBAx_PRRn)
This register controls master ownership and access for a peripheral.
Address: Base address + 0h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RMO ROI
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RARC
RARB
RARA
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
SPBAx_PRRn field descriptions
Field Description
31–30 Requesting Master Owner. This 2-bit register field indicates if the corresponding resource is owned by the
RMO requesting master or not. This register is reset to 2'b0 if ROI = 2'b0.
00 UNOWNED — The resource is unowned.
01 Reserved.
10 ANOTHER_MASTER — The resource is owned by another master.
11 REQUESTING_MASTER — The resource is owned by the requesting master.
29–18 This field is reserved.
- Reserved
Table continues on the next page...
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SPBAx_PRRn field descriptions (continued)
Field Description
17–16 Resource Owner ID. This field indicates which master (one at a time) can access to the PRR for rights
ROI modification. This is a read-only register.
After reset, ROI bits are cleared ("00" -> un-owned resource).
A master performing a write access to the an un-owned PRR will get its ID automatically written into ROI,
while modifying RARx bits. It can then read back the RMO, RAR, ROI bits to make sure RMO returns the
right value, ROI bits contain its ID and RARx bits are correctly asserted. Then no other master (whom ID is
different from the one stored in ROI) will be able to modify RAR fields.
Owner master of a peripheral can assert its dead_owner signal, or write 1'b0 in the RARx to release the
ownership (ROI[1:0] reset to 2'b0).
00 UNOWNED — Unowned resource.
01 MASTER_A — The resource is owned by master A port.
10 MASTER_B — The resource is owned by master B port.
11 MASTER_C — The resource is owned by master C port.
15–3 This field is reserved.
- Reserved
2 Resource Access Right. Control and Status bit for master C.
RARC
This field indicates whether master C can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).
0 PROHIBITED — Access to peripheral is not allowed.
1 ALLOWED — Access to peripheral is granted.
1 Resource Access Right. Control and Status bit for master B.
RARB
This field indicates whether master B can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).
0 PROHIBITED — Access to peripheral is not allowed.
1 ALLOWED — Access to peripheral is granted.
0 Resource Access Right. Control and Status bit for master A.
RARA
This field indicates whether master A can access the peripheral. From 0 up to 3 masters can have
permission to access a resource (all the master can be granted on a peripheral, but only one access at a
time will be granted by SPBA).
0 PROHIBITED — Access to peripheral is not allowed.
1 ALLOWED — Access to peripheral is granted.
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TrustZone Address Space Controller (TZASC)
4.9 TrustZone Address Space Controller (TZASC)
4.9.1 Overview
The TrustZone Address Space Controller (TZASC) protects security-sensitive SW and
data in a trusted execution environment against potentially compromised SW running on
the platform.
4.9.1.1 Block Diagram
The TZASC block diagram is shown in figure below.
APB Slave TZASC Interrupt signal
Interface
AXI Bus
AXI bus Slave Address Master (to DDR Controller)
Interface Region Control Interface
Security lock signal
Clock and reset
Figure 4-16. TZASC Block Diagram
4.9.1.2 Features
By default, the TZASC module is bypassed. The TZASC_ENABLE fuse should be
blown in order for the TZASC to be taken out of bypass mode, and start to perform
security checks on AXI accesses to DRAM memory. If this fuse is not blown, it is not
possible to create protected regions in DDR.
Enabling the TZASC may have an impact on memory performance. The exact value
cannot be stated since it can vary depending on the specific application software.
The TZASC is an IP by Arm ("CoreLink™ TrustZone Address Space Controller
TZC-380"), designed to provide configurable protection over program (SW) memory
space.
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The main features of TZASC are:
• Supports 16 independent address regions
• Access controls are independently programmable for each address region
• Sensitive registers may be locked
• Host interrupt may be programmed to signal attempted access control violations
• AXI master/slave interfaces for transactions
• APB slave interface for configuration and status reporting
NOTE
In this device it is necessary to set
TZASC_ID_SWAP_BYPASS in IOMUXC_GPR10[1] as ID
SWAP function can't work as expected.
4.9.2 Functional Description
4.9.2.1 Address Mapping in various memory mapping modes
The TZASC region base address starts at the beginning of DDR memory space
(0x40000000) instead of the beginning of memory map (0x00000000). In this case the
addresses configured in TZASC controller will be 1GB (0x40000000) offset and does not
match the local addresses.
For example, setting region_setup_low_x=0xBE000000 maps
DDR_ADDR=0xFE000000, the same behavior is observed with fail_address_x registers.
Memory "aliasing" implications on TZASC settings - in systems which does not utilize
the maximal supported DDR space the controller is designed for, the whole DDR
memory map becomes "aliased" (replicated) by the size of the physical memory used. In
such cases, the TZASC must be configured to protect all aliased regions as well (i.e.
effectively reducing the number of available TZASC regions, since all aliased regions
must be handled, for each "real" space needing protection).
For complete details on TZASC functionality and the programming model, see the Arm
document, “CoreLink™ TrustZone Address Space Controller TZC-380 Technical
Reference Manual, (Rev r0p1 or newer)”, available at http://infocenter.arm.com.
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System Debug
4.9.2.2 Clocks
The table found here describes the clock sources for TZASC.
Table 4-22. TZASC Clocks
Clock name Clock Root Description
aclk ccm_clk_root Module clock
4.10 System Debug
4.10.1 Debug
4.10.1.1 Debug Architecture
The chapter describes the debug architecture of the chip.
4.10.1.2 Debug System Features
The chip debug is based on Arm’s CoreSight platform, with support for Quad-core A53
platform and Cortex-M7 core. The key features of the debug system include:
• Support 5-pins(JTAG) interface.
• Support both non-intrusive and halt-mode trace/debug options.
• MDM-AP registers for debugger to control mutli-core halt/resume cores.
• Trace Memory Controller (TMC) is used to enable capturing trace.
• 4KB in SOC trace block.
• ETR is used to allow routing trace data to system memory.
• Support ARM real time trace interface (TPIU) 16-bit @133MHz.
• Support cross trigger between Quad Cortex-A53 and Cortex-M7.
• 4 JTAG security levels, via SJC security functions together with e-Fuse (challenge
response, field return, intrusive detection)
4.10.1.3 System level debug architecture
The debug architecture is shown in the following figure:
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JTAG/SW
DEBUG
DP
Cortex-A53 MPCore Domain APB
AP
Cortex-A53 Integration Layer
DAP
Cortex-A53 MPCore Debug APB
IC Cortex-M7 Integration Layer
1
ETM 1 AHB AP
ATB
CPU 0 ETM 0 FUNNEL
ETM
ATB
CTI 1 FUNNEL
CTM ITM
CTI 0
ATB FUNNEL CM7 Core
AUDIOMIX Funnel
Audio DSP
ETF
ETR
TRACE AXI
SRAM
Figure 4-17. Debug Architecture Diagram
4.10.1.4 Functional description
This section gives a brief overview of the modules that are implemented within the
Cortex-M/Cortex-A Core Platform. The debug blocks are part of the overall CoreSight
platform debug system, which include the ETR, CTM, CTI, ATB replicator, APB address
decode, TPIU and DAP. The CoreSight™ compatible Embedded Trace Macrocell (ETM)
enables traces of program flow to be collected, compressed, and fed into the trace
infrastructure. The Cross Trigger Interface (CTI) is included to provide a common
programming model for use by the debug tools, control the trigger sources, and interface
to the Cross Trigger Matrix (CTM). The debug is controlled via an ARM Debug Access
Port (DAP).
4.10.1.4.1 Embedded Trace Router (ETR)
The Embedded Trace Router (ETR) is a CoreSight trace component which buffers trace
data before dumping that data into DRAM through the AXI bus (via AXI master port).
The output of the funnel is the ETR, and has the ability to buffer a certain amount before
writing the data to DRAM.
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Debug
4.10.1.4.2 Embedded Trace Macrocell (ETM)
The Embedded Trace Macrocell (ETM) is a CoreSight component. The ETM trace unit is
a module that performs real-time instruction flow tracing based on the Embedded Trace
Macrocell (ETM) architecture ETMv4.
4.10.1.4.3 Cross Trigger Matrix (CTM)
The CoreSight CTI channel signals from all the cores are combined using a Cross Trigger
Matrix (CTM) block so that a single cross trigger channel interface is presented in the
Cortex processor. This module can combine four internal channel interfaces
corresponding to each core along with one external channel interface.
In the Cortex processor CTM, the external channel output is driven by the OR output of
all internal channel outputs. Each internal channel input is driven by the OR output of
internal channel outputs of all other CTIs in addition to the external channel input.
4.10.1.4.4 Cross Trigger Interface (CTI)
The Cortex processor has a single external cross trigger channel interface. This external
interface is connected to the CoreSight Cross Trigger Interface (CTI) interface
corresponding to each core through a Cross Trigger Matrix (CTM). A number of
Embedded Cross Trigger (ECT) trigger inputs and trigger outputs are connected between
debug components in the Cortex-A processor and CoreSight CTI blocks.
The CTI enables the debug logic, ETM trace unit, and performance monitoring, to
interact with each other and with other CoreSight components. This is called cross
triggering. For example, you configure the CTI to generate an interrupt when the ETM
trace unit trigger event occurs.
4.10.1.4.5 AMBA Trace Bus Interface (ATB)
The AMBA Trace Bus (ATB) CoreSight debug components are part of the Trace stream
block. The ATB components consist of the ATB Funnel and ATB Replicator. The ATB
Funnel is used to merge several streams together to produce a single output to the ATB
Replicator. The ATB Replicator enables two trace sinks to be wired together and receive
ATB trace data from the same trace source.
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4.10.1.4.6 Advanced Peripheral Bus Interface (APB)
The APB asynchronous interface / bridge connects several debug components. Each
component has a single separate APB interface from the APB-IC (w/ ROM), which
hooks up to a separate APB asynchronous component. The APB interface connects the
core debug functions to the DAP.
4.10.1.4.7 Instrumentation Trace Macrocell (ITM)
The Instrumentation Trace Macrocell (ITM) is a application-driven trace source that
supports printf style debugging to trace operating system and application events. The
ITM generates diagnostic system information as packets. Multiple sources can generate
packets. If multiple sources generate packets at the same time, the ITM arbitrates the
order in which packets are output. These sources in decreasing order of priority are:
• Software trace. Software can write directly to ITM stimulus registers to generate
packets.
• Hardware trace. The DWT generates these packets, and the ITM outputs them.
• Time stamping. Timestamps are generated relative to packets. The ITM contains a
21-bit counter to generate the timestamp. The Cortex-M processor clock or the
bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter.
4.10.1.4.8 Data Watchpoint and Trace (DWT)
The Data Watchpoint and Trace (DWT) debug unit provides watchpoints, data tracing,
and system profiling for the processor.
4.10.1.4.9 Debug Access Port (DAP)
The Debug Access Port (DAP) is a physical port that connects to external debug tools.
The DAP is part of the standardized ARM Debug Interface, and provides a bridge
between a JTAG pin interface and on-chip memory mapped peripherals via the DAP bus.
Transactions generated by the DAP are referred to as External Debugger Accesses.
4.10.1.5 JTAG topology
There is only one JTAG on the chip, and two JTAG modes are supported. Select via the
JTAG_MOD pin.
• Debug mode: JTAG_MOD == 0, DAP is the only TAP controller in the daisy chain.
SJC will be attached to JTAG-AP of DAP.
• Test mode: JTAG_MOD == 1, SJC is the only TAP controller in the daisy chain.
1149.1-compliant, and support 1149.6 AC coupled test.
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System Counter (SYS_CTR)
When the JTAG interface is in Debug Mode, it can be operating in standard 5-pin JTAG
interface. cJTAG/SWD interface is not supported by this chip.
4.11 System Counter (SYS_CTR)
4.11.1 Overview
The System Counter (SYS_CTR) is a programmable system counter, which provides a
shared time base to multiple processors. It is intended for applications where the counter
is always powered on, and supports multiple unrelated clocks.
4.11.1.1 Block diagram
The block diagram of the System Counter is shown below.
Processor
System Platform 0
Bus
Counter 56-bit, Gray
24 MHz base_clk
32 kHz slow_clk
Processor
Platform 1
Figure 4-18. Block diagram
4.11.1.2 Features
• Two counter clock frequencies
• Base clock for normal operation
• Alternate clock for low power operation
• 56-bit counter width
• Gray coded counter output for distribution to the processor timers
• 2 Compare Frames
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• Each compare frame contains a 64-bit compare value
• Each compare frame contains programmable interrupt generation
4.11.2 Functional description
The System Counter inputs two counter clock sources and outputs a gray coded counter
value and interrupt signals (one per compare frame) to the platform’s interrupt controller.
4.11.2.1 Operation
After reset, the System Counter is disabled with count value reset to zero and base
frequency selected. Once the counter is enabled, it will increment the appropriate value
on each rising edge of the selected clock. Because the System Counter is handling a 56-
bit count value across multiple clock domains, synchronization is necessary. The System
Counter provides synchronization mechanisms between the various clock domains.
When the system switches the counter’s clock source, there is a short pause while the
clock multiplexer is handling the clock transition. In order to maintain an accurate count
value, the clock control logic employs two offset counters; one for the base-to-slow
transtion and one for the slow-to-base transition. These offset counters only operate
during the clock transition time to compensate for the idled source clock. Both counters
run off of the base clock. The transition offset values are added to the system count value
at the appropriate time when the counter’s clock is restored.
NOTE
Both base clock and alternate clock must be running when
changing frequencies.
4.11.2.2 Clocks
The System Counter clocks are shown in the table below.
Table 4-23. Clocks
Clock Description
ipg_clk Peripheral Clock
ipg_clk_s Gated peripheral clock for register transactions
base_clk Base Clock. This clock is used during normal operation. It is internally divided by 3
before use.
slow_clk Slow Clock. This clock is used during low power mode. It is internally divided by 64
before use.
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System Counter (SYS_CTR)
Table 4-23. Clocks (continued)
Clock Description
ctr_clk Counter Clock. The ctr_clk is generated by selecting either the base_clk or slow_clk.
Because the compare frame must generate an interrupt when either clock is selected,
most of the compare frame logic resides in this clock domain.
4.11.3 Programming model
The System Counter module contians three programmer’s model sections. Each sections
has an indepentent module enable to allow individual secure access control.
Table 4-24. Programming model
Programming model Description
CNTControlBase This model controls the counter frequency, enable, debug, and count value. This model
also contains the frequency modes table which supplies control and status for the
frequency of the System Counter.
CNTReadBase This model allows the user to read the count value.
CNTCompareBase This model controls the compare value frequency, enable, interrupt mask, and interrupt
status for each compare frame.
4.11.4 Memory map/register definition
This section describes the registers and data structures in the SYS_CTR module.
4.11.4.1 SYS_CTR_CONTROL register descriptions
SYS_CTR_CONTROL Hardware Register Format Summary
4.11.4.1.1 SYS_CTR_CONTROL memory map
SYS_CTR_CONTROL base address: 0h
Offset Register Width Access Reset value
(In bits)
0h Counter Control Register (CNTCR) 32 RW 0000_0000h
4h Counter Status Register (CNTSR) 32 RO 0000_0100h
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Offset Register Width Access Reset value
(In bits)
8h Counter Count Value Low Register (CNTCV0) 32 RW 0000_0000h
Ch Counter Count Value High Register (CNTCV1) 32 RW 0000_0000h
20h Frequency Modes Table 0 Register (CNTFID0) 32 RO 007A_1200h
24h Frequency Modes Table 1 Register (CNTFID1) 32 RO 0000_0200h
28h Frequency Modes Table 2 Register (CNTFID2) 32 RO 0000_0000h
FD0h Counter ID Register (CNTID0) 32 RO 0000_0000h
4.11.4.1.2 Counter Control Register (CNTCR)
4.11.4.1.2.1 Offset
Register Offset
CNTCR 0h
4.11.4.1.2.2 Function
The 32-bit Counter Control Register defines the basic operating configuration of the
System Counter.
The System Counter operates using a fixed base frequency. However, the counter can
increment at a lower, alternate frequency than the base frequency, using a
correspondingly larger increment. For example, it can increment by 15625 and run at a
frequency of 1/15625 of the base frequency. The two frequencies available are
indentified in the frequency modes table. These two frequencies are the base frequency
(table entry 0) and the lower, alternate frequency (table entry 1). Setting the FCR1 bit
selects the alternate frequency. Setting the FCR0 bit selects the base frequency. Setting or
clearing both FCR0 and FCR1 will have no effect; the freqeuncy will not change.
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4.11.4.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
HDBG
FCR1
FCR0
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.1.2.4 Fields
Field Function
31-10 -
— Reserved
9 FCR1
FCR1 Frequency Change Request, ID 1
0b - No change.
1b - Select frequency modes table entry 1, the base frequency.
8 FCR0
FCR0 Frequency Change Request, ID 0
0b - No change.
1b - Select frequency modes table entry 0, the base frequency.
7-2 -
— Reserved
1 HDBG
HDBG Enable Debug
0b - The assertion of the debug input is ignored.
1b - The assertion of the debug input causes the System Counter to halt.
0 EN
EN Enable Counting
0b - Counter disabled
1b - Counter enabled
4.11.4.1.3 Counter Status Register (CNTSR)
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4.11.4.1.3.1 Offset
Register Offset
CNTSR 4h
4.11.4.1.3.2 Function
The system counter status register provides information concerning the clock frequency
and debug state.
4.11.4.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBGH
FCA1
FCA0
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
4.11.4.1.3.4 Fields
Field Function
31-10 -
— Reserved
9 FCA1
FCA1 Frequency Change Acknowledge, ID 1
0b - Base frequency is not selected.
1b - Base frequency is selected.
8 FCA0
FCA0 Frequency Change Acknowledge, ID 0
0b - Base frequency is not selected.
1b - Base frequency is selected.
7-1 -
— Reserved
0 DBGH
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Field Function
DBGH Debug Halt
0b - Counter is not halted by debug.
1b - Counter is halted by debug.
4.11.4.1.4 Counter Count Value Low Register (CNTCV0)
4.11.4.1.4.1 Offset
Register Offset
CNTCV0 8h
4.11.4.1.4.2 Function
The Counter Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
4.11.4.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CNTCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CNTCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.1.4.4 Fields
Field Function
31-0 CNTCV0
CNTCV0 Counter Count Value bits [31:0]
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4.11.4.1.5 Counter Count Value High Register (CNTCV1)
4.11.4.1.5.1 Offset
Register Offset
CNTCV1 Ch
4.11.4.1.5.2 Function
The Counter Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CNTCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
4.11.4.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved CNTCV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CNTCV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.1.5.4 Fields
Field Function
31-25 -
— Reserved
24-0 CNTCV1
CNTCV1 Counter Count Value bits [55:32]
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4.11.4.1.6 Frequency Modes Table 0 Register (CNTFID0)
4.11.4.1.6.1 Offset
Register Offset
CNTFID0 20h
4.11.4.1.6.2 Function
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
4.11.4.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTFID0
W
Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTFID0
W
Reset 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0
4.11.4.1.6.4 Fields
Field Function
31-0 CNTFID0
CNTFID0 Base Frequency (24 MHz /3 = 8 MHz)
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4.11.4.1.7 Frequency Modes Table 1 Register (CNTFID1)
4.11.4.1.7.1 Offset
Register Offset
CNTFID1 24h
4.11.4.1.7.2 Function
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
4.11.4.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTFID1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTFID1
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
4.11.4.1.7.4 Fields
Field Function
31-0 CNTFID1
CNTFID1 Alternate Frequency (32 kHz /64 = 512 Hz)
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4.11.4.1.8 Frequency Modes Table 2 Register (CNTFID2)
4.11.4.1.8.1 Offset
Register Offset
CNTFID2 28h
4.11.4.1.8.2 Function
The Counter Frequency ID registers is the frequency modes table starting at offset 0x020.
Table entries are 32-bits, and each entry specifies a system counter update frequency, in
Hz. The first entry in the table specifies the base frequency of the system counter. To
ensure overall counter accuracy is maintained, any subsequent entries in the table are
exact divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the
increment applied at each counter update is given by: increment = (base_frequency) /
(selected_frequency) A 32-bit word of zero value marks the end of the table. That is, the
word of memory immediately after the last entry in the table is zero.
4.11.4.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTFID2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTFID2
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.1.8.4 Fields
Field Function
31-0 CNTFID2
CNTFID2 End Marker
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4.11.4.1.9 Counter ID Register (CNTID0)
4.11.4.1.9.1 Offset
Register Offset
CNTID0 FD0h
4.11.4.1.9.2 Function
The Counter ID register indicates the architecture version 0.
4.11.4.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.1.9.4 Fields
Field Function
31-0 CNTID
CNTID Counter Identification. Counter ID 0.
4.11.4.2 SYS_CTR_READ register descriptions
The read frame registers are all read-only. These registers read the same values as the
control frame registers for the count value and counter ID. They are processed via a
separate mechanism from the control frame to allow nonsecure, user mode access.
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System Counter (SYS_CTR)
4.11.4.2.1 SYS_CTR_READ memory map
SYS_CTR_READ base address: 0h
Offset Register Width Access Reset value
(In bits)
0h Counter Count Value Low Register (CNTCV0) 32 RO 0000_0000h
4h Counter Count Value High Register (CNTCV1) 32 RO 0000_0000h
FD0h Counter ID Register (CNTID0) 32 RO 0000_0000h
4.11.4.2.2 Counter Count Value Low Register (CNTCV0)
4.11.4.2.2.1 Offset
Register Offset
CNTCV0 0h
4.11.4.2.2.2 Function
The Counter Count Value Low register indicates the current count value bits 31-0.
4.11.4.2.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.2.2.4 Fields
Field Function
31-0 CNTCV0
CNTCV0 Counter Count Value bits [31:0]
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4.11.4.2.3 Counter Count Value High Register (CNTCV1)
4.11.4.2.3.1 Offset
Register Offset
CNTCV1 4h
4.11.4.2.3.2 Function
The Counter Count Value High register indicates the current count value bits 63-32.
4.11.4.2.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTCV1
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTCV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.2.3.4 Fields
Field Function
31-25 -
— Reserved
24-0 CNTCV1
CNTCV1 Counter Count Value bits [55:32]. Bits[63:56] are always zero.
4.11.4.2.4 Counter ID Register (CNTID0)
4.11.4.2.4.1 Offset
Register Offset
CNTID0 FD0h
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4.11.4.2.4.2 Function
The Counter ID register indicates the architecture version 0.
4.11.4.2.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.2.4.4 Fields
Field Function
31-0 CNTID
CNTID Counter Identification. Counter ID 0.
4.11.4.3 SYS_CTR_COMPARE register descriptions
Each compare frame consists of a 256 byte region. Each compare frame has its own
compare value and control register. Each compare frame is capable of generating one
maskable interrupt.
4.11.4.3.1 SYS_CTR_COMPARE memory map
SYS_CTR_COMPARE base address: 0h
Offset Register Width Access Reset value
(In bits)
20h Compare Count Value Low Register (CMPCVL0) 32 RO 0000_0000h
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Offset Register Width Access Reset value
(In bits)
24h Compare Count Value High Register (CMPCVH0) 32 RO 0000_0000h
2Ch Compare Control Register (CMPCR0) 32 RW 0000_0000h
120h Compare Count Value Low Register (CMPCVL1) 32 RO 0000_0000h
124h Compare Count Value High Register (CMPCVH1) 32 RO 0000_0000h
12Ch Compare Control Register (CMPCR1) 32 RW 0000_0000h
FD0h Counter ID Register (CNTID0) 32 RO 0000_0000h
4.11.4.3.2 Compare Count Value Low Register (CMPCVL0 - CMPCVL1)
4.11.4.3.2.1 Offset
Register Offset
CMPCVL0 20h
CMPCVL1 120h
4.11.4.3.2.2 Function
The Compare Count Value Low register indicates the current count value bits 31-0.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
4.11.4.3.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CMPCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMPCV0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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4.11.4.3.2.4 Fields
Field Function
31-0 CMPCV0
CMPCV0 Compare Count Value bits [31:0]
4.11.4.3.3 Compare Count Value High Register (CMPCVH0 - CMPCVH1)
4.11.4.3.3.1 Offset
Register Offset
CMPCVH0 24h
CMPCVH1 124h
4.11.4.3.3.2 Function
The Compare Count Value High register indicates the current count value bits 63-32.
NOTE
Writes to the CMPCV registers must be performed while
operating on the base frequency only. Writes to these registers
while running on the alternate frequency may have
unpredictable results.
4.11.4.3.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CMPCV1
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CMPCV1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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4.11.4.3.3.4 Fields
Field Function
31-25 -
— Reserved
24-0 CMPCV1
CMPCV1 Compare Count Value bits [55:32]. Bits[63:56] are always zero.
4.11.4.3.4 Compare Control Register (CMPCR0 - CMPCR1)
4.11.4.3.4.1 Offset
Register Offset
CMPCR0 2Ch
CMPCR1 12Ch
4.11.4.3.4.2 Function
The compare control register provides control and status of the compare function. When
enabled, the ISTAT bit indicates whether the counter value is greater than or equal to the
value in the compare value register (CMPCV). The ISTAT equation is:
ISTAT = (CNTCV >= CMPCV)
ISTAT takes no account of the value of the IMASK bit. If ISTAT is set to 1 and IMASK
is 0, then the interrupt request is asserted. Clearing the enable bit (EN=0) will clear the
status bit (ISTAT=0) and will negate the interrupt output signal.
4.11.4.3.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ISTAT
Reserved
R
IMASK
EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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4.11.4.3.4.4 Fields
Field Function
31-3 -
— Reserved
2 ISTAT
ISTAT Compare (interrupt) status
0b - Counter value is less than the compare value or compare is disabled.
1b - Counter value is greater than or equal to the compare value and compare is enabled.
1 IMASK
IMASK Interrupt request mask
0b - Interrupt output signal is not masked.
1b - Interrupt output signal is masked.
0 EN
EN Enable the compare function
0b - Compare disabled
1b - Compare enabled
4.11.4.3.5 Counter ID Register (CNTID0)
4.11.4.3.5.1 Offset
Register Offset
CNTID0 FD0h
4.11.4.3.5.2 Function
The Counter ID register indicates the architecture version 0.
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4.11.4.3.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.11.4.3.5.4 Fields
Field Function
31-0 CNTID
CNTID Counter Identification. Counter ID 0.
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Chapter 5
Clocks and Power Management
5.1 Clock Control Module (CCM)
5.1.1 Overview
Clock Control Module (CCM) manages the on-chip module clocks. CCM receives clocks
from PLLs and oscillators and creates clocks for on-chip peripherals through a set of
multiplexers, dividers and gates. When entering or exiting a low power mode, CCM
automatically turns on and off PLLs and peripheral clocks.
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Clock Control Module (CCM)
CCM Low Power Clock Gating
(LPCG)
Clock Root Generation
CCM_EXT_CLK[4:1] LPCG
Blocks
clock slices Module Clocks
Clock Roots
cg
mux
: cg div
cg
PLL cg
Clock Source from cg
PLL/Divider cg
24 MHz PLLs cg
cg
mux
: cg div
cg
32 kHz
to on-chip
peripherals
Pre-Dividers PLL Enable
PLL
Control
PLL Lock
Clock Gating Control
DSM WAIT / STOP Clock Enable
(CCGR)
Clock Gate
GPC SRC
CCM_CLKO[2:1]
Figure 5-1. CCM Block Diagram
5.1.2 Clock Root Selects
The table below details the clock root slices and clock source selection inputs for each
clock slice.
NOTE
The value of all clock root slice registers
(CCM_TARGET_ROOTn) are zero after Power On Reset
(POR) with the exception of DRAM_CLK_ROOT_SEL. Please
see the System Boot chapter for ROM reset values and default
frequency settings for the clock root slices.
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Table 5-1. Clock Root Table
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
0 (Core) ARM_A53_CLK_ROOT 0x8000 1000 000 - 24M_REF_CLK
001 - ARM_PLL_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL1_DIV2
011 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV2
111 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
1 (Core) ARM_M7_CLK_ROOT 0x8080 800 000 - 24M_REF_CLK
011 - VPU_PLL_CLK
100 - SYSTEM_PLL1_CLK
010 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
111 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
2 (Core) ML_CLK_ROOT 0x8100 1000 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
3 (Core) GPU3D_CORE_CLK_ROOT 0x8180 1000 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
4 (Core) GPU3D_SHADER_CLK_RO 0x8200 1000 000 - 24M_REF_CLK
OT
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
5 (Core) GPU2D_CLK_ROOT 0x8280 1000 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
6 (Core) AUDIO_AXI_CLK_ROOT 0x8300 800 000 - 24M_REF_CLK
001 - GPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
7 (Core) HSIO_AXI_CLK_ROOT 0x8380 500 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
8 (Core) MEDIA_ISP_CLK_ROOT 0x8400 500 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_CLK
111 - SYSTEM_PLL2_DIV2
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
16 (Bus) MAIN_AXI_CLK_ROOT 0x8800 400 000 - 24M_REF_CLK
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
010 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV8
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
011 - SYSTEM_PLL2_DIV4
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
17 (Bus) ENET_AXI_CLK_ROOT 0x8880 266 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
011 - SYSTEM_PLL2_DIV4
100 - SYSTEM_PLL2_DIV5
111 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
18 (Bus) NAND_USDHC_BUS_CLK_R 0x8900 266 000 - 24M_REF_CLK
OOT
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL1_DIV6
110 - SYSTEM_PLL2_DIV4
011 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
19 (Bus) VPU_BUS_CLK_ROOT 0x8980 800 000 - 24M_REF_CLK
010 - VPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV8
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL2_CLK
20 (Bus) MEDIA_AXI_CLK_ROOT 0x8A00 500 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_CLK
111 - SYSTEM_PLL2_DIV2
011 - SYSTEM_PLL3_CLK
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
21 (Bus) MEDIA_APB_CLK_ROOT 0x8A80 200 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
22 (Bus) HDMI_APB_CLK_ROOT 0x8B00 200 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
23 (Bus) HDMI_AXI_CLK_ROOT 0x8B80 500 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_CLK
111 - SYSTEM_PLL2_DIV2
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL2_CLK
110 - EXT_CLK_1
24 (Bus) GPU_AXI_CLK_ROOT 0x8C00 800 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
25 (Bus) GPU_AHB_CLK_ROOT 0x8C80 400 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
26 (Bus) NOC_CLK_ROOT 0x8D00 1000 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
100 - SYSTEM_PLL2_DIV2
010 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
27 (Bus) NOC_IO_CLK_ROOT 0x8D80 800 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
100 - SYSTEM_PLL2_DIV2
010 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
28 (Bus) ML_AXI_CLK_ROOT 0x8E00 800 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
29 (Bus) ML_AHB_CLK_ROOT 0x8E80 400 000 - 24M_REF_CLK
010 - GPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
32 (Bus) AHB_CLK_ROOT 0x9000 133 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
33 (Bus) IPG_CLK_ROOT 0x9080 133 xxx - AHB_CLK_ROOT
34 (Bus) AUDIO_AHB_CLK_ROOT 0x9100 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV6
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
38 (Bus) MEDIA_DISP2_CLK_ROOT 0x9300 160 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
001 - VIDEO_PLL_CLK
111 - EXT_CLK_4
48 DRAM_CLK_ROOT_SEL 0x9800 800 000 - DRAM_PLL_CLK
001 - DRAM_ALT_CLK_ROOT
49 ARM_A53_CLK_ROOT_SEL 0x9880 1200 000 - ARM_PLL_CLK
100 - ARM_A53_CLK_ROOT
64 (Peripheral) DRAM_ALT_CLK_ROOT 0xA000 800 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_CLK
111 - SYSTEM_PLL1_DIV3
010 - SYSTEM_PLL1_DIV8
100 - SYSTEM_PLL2_CLK
011 - SYSTEM_PLL2_DIV2
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
65 (Peripheral) DRAM_APB_CLK_ROOT 0xA080 200 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
66 (Peripheral) VPU_G1_CLK_ROOT 0xA100 800 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_CLK
101 - SYSTEM_PLL2_DIV8
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
67 (Peripheral) VPU_G2_CLK_ROOT 0xA180 700 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_CLK
101 - SYSTEM_PLL2_DIV8
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
68 (Peripheral) CAN1_CLK_ROOT 0xA200 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
69 (Peripheral) CAN2_CLK_ROOT 0xA280 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
70 (Peripheral) MEMREPAIR_CLK_ROOT 0xA300 50 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
71 (Peripheral) PCIE_PHY_CLK_ROOT 0xA380 250 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV2
010 - SYSTEM_PLL2_DIV2
001 - SYSTEM_PLL2_DIV10
011 - EXT_CLK_1
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
72 (Peripheral) PCIE_AUX_CLK_ROOT 0xA400 10 000 - 24M_REF_CLK
111 - SYSTEM_PLL1_DIV4
110 - SYSTEM_PLL1_DIV5
101 - SYSTEM_PLL1_DIV10
001 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
73 (Peripheral) I2C5_CLK_ROOT 0xA480 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
74 (Peripheral) I2C6_CLK_ROOT 0xA500 66 000 - 24M_REF_CLK
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
75 (Peripheral) SAI1_CLK_ROOT 0xA580 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_1
111 - EXT_CLK_2
101 - Reserved
76 (Peripheral) SAI2_CLK_ROOT 0xA600 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_2
111 - EXT_CLK_3
101 - Reserved
77 (Peripheral) SAI3_CLK_ROOT 0xA680 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_3
111 - EXT_CLK_4
101 - Reserved
79 (Peripheral) SAI5_CLK_ROOT 0xA780 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_2
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
111 - EXT_CLK_3
101 - Reserved
80 (Peripheral) SAI6_CLK_ROOT 0xA800 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_3
111 - EXT_CLK_4
101 - Reserved
81 (Peripheral) ENET_QOS_CLK_ROOT 0xA880 125 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - EXT_CLK_4
82 (Peripheral) ENET_QOS_TIMER_CLK_R 0xA900 200 000 - 24M_REF_CLK
OOT
001 - SYSTEM_PLL2_DIV10
010 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
011 - EXT_CLK_1
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
83 (Peripheral) ENET_REF_CLK_ROOT 0xA980 125 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - EXT_CLK_4
84 (Peripheral) ENET_TIMER_CLK_ROOT 0xAA00 125 000 - 24M_REF_CLK
001 - SYSTEM_PLL2_DIV10
010 - AUDIO_PLL1_CLK
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
111 - VIDEO_PLL_CLK
011 - EXT_CLK_1
100 - EXT_CLK_2
101 - EXT_CLK_3
110 - EXT_CLK_4
85 (Peripheral) ENET_PHY_REF_CLK_ROO 0xAA80 125 000 - 24M_REF_CLK
T
100 - SYSTEM_PLL2_DIV2
011 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL2_DIV8
001 - SYSTEM_PLL2_DIV20
101 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - VIDEO_PLL_CLK
86 (Peripheral) NAND_CLK_ROOT 0xAB00 500 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL2_DIV2
110 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
010 - AUDIO_PLL1_CLK
100 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
87 (Peripheral) QSPI_CLK_ROOT 0xAB80 400 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
010 - SYSTEM_PLL2_DIV3
110 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL2_CLK
88 (Peripheral) USDHC1_CLK_ROOT 0xAC00 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
89 (Peripheral) USDHC2_CLK_ROOT 0xAC80 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
90 (Peripheral) I2C1_CLK_ROOT 0xAD00 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
91 (Peripheral) I2C2_CLK_ROOT 0xAD80 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
92 (Peripheral) I2C3_CLK_ROOT 0xAE00 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
93 (Peripheral) I2C4_CLK_ROOT 0xAE80 66 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV5
111 - SYSTEM_PLL1_DIV6
010 - SYSTEM_PLL2_DIV20
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
011 - SYSTEM_PLL3_CLK
100 - AUDIO_PLL1_CLK
110 - AUDIO_PLL2_CLK
101 - VIDEO_PLL_CLK
94 (Peripheral) UART1_CLK_ROOT 0xAF00 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
95 (Peripheral) UART2_CLK_ROOT 0xAF80 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
96 (Peripheral) UART3_CLK_ROOT 0xB000 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_4
97 (Peripheral) UART4_CLK_ROOT 0xB080 80 000 - 24M_REF_CLK
001 - SYSTEM_PLL1_DIV10
010 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
101 - EXT_CLK_2
110 - EXT_CLK_3
100 (Peripheral) GIC_CLK_ROOT 0xB200 500 000 - 24M_REF_CLK
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
100 - SYSTEM_PLL1_CLK
010 - SYSTEM_PLL1_DIV20
101 - SYSTEM_PLL2_DIV2
001 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV10
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_4
101 (Peripheral) ECSPI1_CLK_ROOT 0xB280 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
102 (Peripheral) ECSPI2_CLK_ROOT 0xB300 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
103 (Peripheral) PWM1_CLK_ROOT 0xB380 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_1
104 (Peripheral) PWM2_CLK_ROOT 0xB400 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
111 - VIDEO_PLL_CLK
101 - EXT_CLK_1
105 (Peripheral) PWM3_CLK_ROOT 0xB480 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
106 (Peripheral) PWM4_CLK_ROOT 0xB500 66 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV5
110 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
100 - SYSTEM_PLL3_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
107 (Peripheral) GPT1_CLK_ROOT 0xB580 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_1
108 (Peripheral) GPT2_CLK_ROOT 0xB600 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_2
109 (Peripheral) GPT3_CLK_ROOT 0xB680 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_3
110 (Peripheral) GPT4_CLK_ROOT 0xB700 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_1
111 (Peripheral) GPT5_CLK_ROOT 0xB780 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_2
112 (Peripheral) GPT6_CLK_ROOT 0xB800 100 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV10
011 - SYSTEM_PLL1_DIV20
001 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL1_CLK
100 - VIDEO_PLL_CLK
111 - EXT_CLK_3
113 (Peripheral) TRACE_CLK_ROOT 0xB880 133 000 - 24M_REF_CLK
011 - VPU_PLL_CLK
010 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL1_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK
110 - EXT_CLK_1
111 - EXT_CLK_3
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
114 (Peripheral) WDOG_CLK_ROOT 0xB900 66 000 - 24M_REF_CLK
011 - VPU_PLL_CLK
010 - SYSTEM_PLL1_DIV5
001 - SYSTEM_PLL1_DIV6
110 - SYSTEM_PLL1_DIV10
111 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL2_DIV8
101 - SYSTEM_PLL3_CLK
115 (Peripheral) WRCLK_CLK_ROOT 0xB980 40 000 - 24M_REF_CLK
010 - VPU_PLL_CLK
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
001 - SYSTEM_PLL1_DIV20
110 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL3_CLK
116 (Peripheral) IPP_DO_CLKO1 0xBA00 266 000 - 24M_REF_CLK
110 - VPU_PLL_CLK
001 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV4
010 - SYSTEM_PLL1_DIV6
111 - SYSTEM_PLL1_DIV10
101 - SYSTEM_PLL2_DIV2
100 - AUDIO_PLL2_CLK
117 (Peripheral) IPP_DO_CLKO2 0xBA80 266 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_DIV2
001 - SYSTEM_PLL2_DIV5
011 - SYSTEM_PLL2_DIV6
100 - SYSTEM_PLL3_CLK
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - 32K_REF_CLK
118 (Peripheral) HDMI_FDCC_TST_CLK_RO 0xBB00 600 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
Table continues on the next page...
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NXP Semiconductors 245
Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
120 (Peripheral) HDMI_REF_266M_CLK_RO 0xBC00 266 000 - 24M_REF_CLK
OT
001 - SYSTEM_PLL1_DIV2
100 - SYSTEM_PLL1_DIV3
011 - SYSTEM_PLL2_DIV3
101 - SYSTEM_PLL2_DIV5
010 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL1_CLK
111 - VIDEO_PLL_CLK
121 (Peripheral) USDHC3_CLK_ROOT 0xBC80 400 000 - 24M_REF_CLK
010 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV2
101 - SYSTEM_PLL1_DIV3
111 - SYSTEM_PLL1_DIV8
011 - SYSTEM_PLL2_DIV2
100 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
122 (Peripheral) MEDIA_CAM1_PIX_CLK_RO 0xBD00 500 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
123 (Peripheral) MEDIA_MIPI_PHY1_REF_CL 0xBD80 125 000 - 24M_REF_CLK
K_ROOT
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
010 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
Table continues on the next page...
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246 NXP Semiconductors
Chapter 5 Clocks and Power Management
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
124 (Peripheral) MEDIA_DISP1_PIX_CLK_RO 0xBE00 250 000 - 24M_REF_CLK
OT
100 - SYSTEM_PLL1_CLK
101 - SYSTEM_PLL2_CLK
110 - SYSTEM_PLL3_CLK
011 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
001 - VIDEO_PLL_CLK
111 - EXT_CLK_4
125 (Peripheral) MEDIA_CAM2_PIX_CLK_RO 0xBE80 266 000 - 24M_REF_CLK
OT
011 - SYSTEM_PLL1_CLK
001 - SYSTEM_PLL1_DIV3
100 - SYSTEM_PLL2_CLK
010 - SYSTEM_PLL2_DIV4
101 - SYSTEM_PLL3_CLK
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
126 (Peripheral) MEDIA_LDB_CLK_ROOT 0xBF00 560 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV3
010 - SYSTEM_PLL2_DIV10
110 - AUDIO_PLL2_CLK
111 - VIDEO_PLL_CLK
101 - EXT_CLK_2
130 (Peripheral) MEDIA_MIPI_TEST_BYTE_C 0xC100 200 000 - 24M_REF_CLK
LK
111 - SYSTEM_PLL1_DIV4
110 - SYSTEM_PLL1_DIV5
101 - SYSTEM_PLL1_DIV10
001 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV10
010 - SYSTEM_PLL2_DIV20
011 - SYSTEM_PLL3_CLK
131 (Peripheral) ECSPI3_CLK_ROOT 0xC180 80 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL1_DIV5
010 - SYSTEM_PLL1_DIV20
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 247
Clock Control Module (CCM)
Table 5-1. Clock Root Table (continued)
Slice Index n Clock Root Offset Max Freq Source Select
(MHz)
(CCM_TARGET_ROOTn[MUX])
110 - SYSTEM_PLL2_DIV4
001 - SYSTEM_PLL2_DIV5
101 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL2_CLK
132 (Peripheral) PDM_CLK_ROOT 0xC200 200 000 - 24M_REF_CLK
011 - SYSTEM_PLL1_CLK
100 - SYSTEM_PLL2_CLK
001 - SYSTEM_PLL2_DIV10
101 - SYSTEM_PLL3_CLK
010 - AUDIO_PLL1_CLK
111 - AUDIO_PLL2_CLK
110 - EXT_CLK_3
133 (Peripheral) VPU_VC8000E_CLK_ROOT 0xC280 800 000 - 24M_REF_CLK
001 - VPU_PLL_CLK
010 - SYSTEM_PLL1_CLK
011 - SYSTEM_PLL2_CLK
101 - SYSTEM_PLL2_DIV8
110 - SYSTEM_PLL3_CLK
111 - AUDIO_PLL1_CLK
100 - AUDIO_PLL2_CLK
134 (Peripheral) SAI7_CLK_ROOT 0xC300 66 000 - 24M_REF_CLK
100 - SYSTEM_PLL1_DIV6
001 - AUDIO_PLL1_CLK
010 - AUDIO_PLL2_CLK
011 - VIDEO_PLL_CLK
110 - EXT_CLK_3
111 - EXT_CLK_4
101 - Reserved
5.1.3 Clock Tree
The figure below illustrates the clock sources from the PLLs.
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248 NXP Semiconductors
Chapter 5 Clocks and Power Management
NOTE
Some clock gates illustrated below are symbolic of distributed
clock gates (multiple) and not a sole clock gate. These clock
slices typically source multiple IP (e.g. bus clocks).
EXT_CLK_4
EXT_CLK_3
EXT_CLK_2
EXT_CLK_1
OSC_32K
VIDEO
DIV
PLL
Audio
DIV
PLL2
Audio
DIV
PLL1
System
PLL3
System
/20
PLL2
/10
/8
/6
/5
/4
/3
/2
System
/20
PLL1
/10
/8
/6
/5
/4
/3
/2
GPU PLL DIV
VPU PLL DIV
DRAM DIV
PLL1
ARM PLL DIV
OSC_24M
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
DRAM_PLL1_CLK
VIDEO_PLL_CLK
GPU_PLL_CLK
VPU_PLL_CLK
ARM_PLL_CLK
24M_REF_CLK
32K_REF_CLK
EXT_CLK_1
EXT_CLK_2
EXT_CLK_3
EXT_CLK_4
Figure 5-2. CCM input clock sources
The figure below illustrates the clock slices of CCM and clock root generation.
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NXP Semiconductors 249
Clock Control Module (CCM)
LPCG
PRE[MUX_A]
POST[MUX_A]
POST[SELECT]
cg
ARM_A53_CLK_ROOT
RRE[MUX_B]
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
PRE[MUX_A]
POST[SELECT]
cg
ARM_M7_CLK_ROOT
RRE[MUX_B]
POST[MUX_B]
cg POST[POST_PODF]
POST[MUX_A]
PRE[MUX_A]
POST[SELECT]
cg CCGR91
ML_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
PRE[MUX_A]
POST[SELECT]
cg CCGR70
GPU3D_CORE_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR70
GPU3D_SHADER_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_A]
PRE[MUX_A]
POST[SELECT]
cg CCGR69
GPU2D_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A]
POST[SELECT]
cg CCGR101
AUDIO_AXI_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
PRE[MUX_A] CCGR37 ||
POST[SELECT] CCGR77
cg
HSIO_AXI_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
PRE[MUX_A]
POST[SELECT]
cg CCGR93
MEDIA_ISP_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
POST[MUX_A]
PRE[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
MAIN_AXI_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
RRE[MUX_B] ENET_AXI_CLK_ROOT
cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg NAND_USDHC_BUS_CLK_ROOT
RRE[MUX_B] cg
cg POST[POST_PODF]
POST[MUX_B]
PRE[PRE_PODF_B]
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR99
VPU_BUS_CLK_ROOT
RRE[MUX_B] cg
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
cg POST[POST_PODF]
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
PRE[PRE_PODF_B]
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
POST[MUX_B]
VIDEO_PLL_CLK
DRAM_PLL1_CLK
32K_REF_CLK
GPU_PLL_CLK
ARM_PLL_CLK
24M_REF_CLK
VPU_PLL_CLK
EXT_CLK_2
EXT_CLK_1
EXT_CLK_4
EXT_CLK_3
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250 NXP Semiconductors
Chapter 5 Clocks and Power Management
POST[MUX_A] LPCG
PRE[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR93
MEDIA_AXI_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_A]
PRE[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR93
MEDIA_APB_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR95
HDMI_APB_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR95
HDMI_AXI_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
CCGR60 ||
POST[MUX_A]
PRE[MUX_A] PRE[PRE_PODF_A] CCGR70 ||
POST[SELECT] CCGR87
cg
GPU_AXI_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B] CCGR60 ||
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] CCGR70 ||
POST[SELECT] CCGR87
cg
GPU_AHB_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_A]
PRE[MUX_A] PRE[PRE_PODF_A]
POST[SELECT] CCGR88
cg
` PRE[MUX_B]
NOC_CLK_ROOT
cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR88
` PRE[MUX_B]
NOC_IO_CLK_ROOT
cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg
ML_AXI_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A]
POST[SELECT]
cg CCGR91
ML_AHB_CLK_ROOT
PRE[MUX_B] cg
cg POST[POST_PODF]
PRE[PRE_PODF_B]
POST[MUX_B] AHB_CLK_ROOT
cg
PRE[MUX_A]
POST[MUX_A]
POST[SELECT]
cg IPG[POST_PODF]
IPG_CLK_ROOT
PRE[MUX_B] cg
cg AHB[POST_PODF] CCGR101
CKIL_SYNC
SYNC
POST[MUX_B] AUDIO_AHB_CLK_ROOT
PRE[MUX_A]
POST[MUX_A]
cg
POST[SELECT]
cg IPG[POST_PODF]
PRE[MUX_B]
cg AHB[POST_PODF] CCGR93
POST[MUX_B] MEDIA_DISP2_CLK_ROOT
POST[MUX_B] PRE[MUX_A]
POST[MUX_A]
cg
POST[SELECT]
cg IPG[POST_PODF]
PRE[MUX_B]
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
POST[MUX_B]
cg AHB[POST_PODF]
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
VIDEO_PLL_CLK
DRAM_PLL1_CLK
32K_REF_CLK
GPU_PLL_CLK
ARM_PLL_CLK
24M_REF_CLK
VPU_PLL_CLK
POST[MUX_B]
EXT_CLK_2
EXT_CLK_1
EXT_CLK_4
EXT_CLK_3
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NXP Semiconductors 251
Clock Control Module (CCM)
POST[MUX_B] LPCG
POST[MUX_B]
PRE[MUX_A]
POST[MUX_A] CCGR5
PRE[PRE_PODF_A] POST[POST_PODF]
DRAM_ALT_CLK_ROOT
cg cg
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR5
DRAM_APB_CLK_ROOT
cg cg
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR86
VPU_G1_CLK_ROOT
cg cg
POST[MUX_A]
PRE[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF] CCGR90
VPU_G2_CLK_ROOT
cg cg
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR53
CAN1_CLK_ROOT
cg cg
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR54
CAN2_CLK_ROOT
cg cg
PRE[MUX_A]
POST[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR37
PCIE_AUX_CLK_ROOT
cg cg
PRE[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
SAI2_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
SAI3_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
SAI5_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
SAI6_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
SAI7_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR59
ENET_QOS_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR59
ENET_QOS_TIMER_CLK_ROOT
cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR10
ENET_REF_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR10
ENET_TIMER_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF]
ENET_PHY_REF_CLK_ROOT
cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR48
NAND_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR47
QSPI_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR81
USDHC1_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR82
USDHC2_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR94
USDHC3_CLK_ROOT
cg cg
PRE[MUX_A] CCGR23
PRE[PRE_PODF_A] POST[POST_PODF] I2C1_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
VIDEO_PLL_CLK
DRAM_PLL1_CLK
32K_REF_CLK
GPU_PLL_CLK
ARM_PLL_CLK
24M_REF_CLK
VPU_PLL_CLK
EXT_CLK_2
EXT_CLK_1
EXT_CLK_4
EXT_CLK_3
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252 NXP Semiconductors
Chapter 5 Clocks and Power Management
LPCG
PRE[MUX_A] CCGR25
PRE[PRE_PODF_A] POST[POST_PODF] I2C2_CLK_ROOT
cg cg
PRE[MUX_A] CCGR25
PRE[PRE_PODF_A] POST[POST_PODF] I2C3_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR26
I2C4_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR51
I2C5_CLK_ROOT
cg cg
CCGR52
PRE[PRE_PODF_A] POST[POST_PODF] I2C6_CLK_ROOT
cg cg
CCGR73
PRE[PRE_PODF_A] POST[POST_PODF] UART1_CLK_ROOT
cg cg
PRE[PRE_PODF_A] POST[POST_PODF] CCGR74
UART2_CLK_ROOT
cg cg
PRE[PRE_PODF_A] POST[POST_PODF] CCGR75
UART3_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR76
UART4_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR88
GIC_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR7
ECSPI1_CLK_ROOT
cg cg
PRE[PRE_PODF_A] POST[POST_PODF] CCGR8
PRE[MUX_A] ECSPI2_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR9
ECSPI3_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR40
PWM1_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR41
PWM2_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR42
PWM3_CLK_ROOT
cg cg
PRE[MUX_A] CCGR43
PRE[PRE_PODF_A] POST[POST_PODF] PWM4_CLK_ROOT
cg cg
PRE[MUX_A] CCGR16
PRE[PRE_PODF_A] POST[POST_PODF] GPT1_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR17
GPT2_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR18
GPT3_CLK_ROOT
cg cg
PRE[MUX_A] CCGR19
PRE[PRE_PODF_A] POST[POST_PODF]
GPT4_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR20
GPT5_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR21
GPT6_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR72
TRACE_CLK_ROOT
cg cg
PRE[MUX_A]
PRE[PRE_PODF_A] POST[POST_PODF]
WDOG_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
VIDEO_PLL_CLK
DRAM_PLL1_CLK
32K_REF_CLK
GPU_PLL_CLK
ARM_PLL_CLK
24M_REF_CLK
VPU_PLL_CLK
EXT_CLK_4
EXT_CLK_2
EXT_CLK_1
EXT_CLK_3
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NXP Semiconductors 253
Clock Control Module (CCM)
LPCG
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
MEDIA_CAM1_PIX_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
MEDIA_CAM2_PIX_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
MEDIA_MIPI_PHY1_REF_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
MEDIA_DISP1_PIX_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR93
MEDIA_LDB_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR89
VPU_VC8000E_CLK_ROOT
cg cg
PRE[MUX_A] PRE[PRE_PODF_A] POST[POST_PODF] CCGR101
PDM_CLK_ROOT
cg cg
SYSTEM_PLL1_DIV20
SYSTEM_PLL2_DIV20
SYSTEM_PLL1_DIV10
SYSTEM_PLL2_DIV10
SYSTEM_PLL1_DIV2
SYSTEM_PLL1_DIV3
SYSTEM_PLL1_DIV4
SYSTEM_PLL1_DIV5
SYSTEM_PLL1_DIV6
SYSTEM_PLL1_DIV8
SYSTEM_PLL2_DIV2
SYSTEM_PLL2_DIV3
SYSTEM_PLL2_DIV4
SYSTEM_PLL2_DIV5
SYSTEM_PLL2_DIV6
SYSTEM_PLL2_DIV8
SYSTEM_PLL1_CLK
SYSTEM_PLL2_CLK
SYSTEM_PLL3_CLK
AUDIO_PLL1_CLK
AUDIO_PLL2_CLK
VIDEO_PLL_CLK
DRAM_PLL1_CLK
32K_REF_CLK
GPU_PLL_CLK
ARM_PLL_CLK
25M_REF_CLK
VPU_PLL_CLK
EXT_CLK_2
EXT_CLK_1
EXT_CLK_4
EXT_CLK_3
Figure 5-3. CCM Clock Tree Root Slices
5.1.4 System Clocks
The table below shows the CCM output module clock connectivity and gating.
Table 5-2. System Clocks
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
AIPSTZ aips_tz1.hclk AHB_CLK_ROOT ccm_clk_enable_ipmux1
(CCGR28)
aips_tz2.hclk AHB_CLK_ROOT ccm_clk_enable_ipmux2
(CCGR29)
aips_tz3.hclk AHB_CLK_ROOT ccm_clk_enable_ipmux3
(CCGR30)
APBH rawnand.u_bch_input_apb_clk NAND_USDHC_BUS_CLK_R ccm_clk_enable_rawnand
(RAWNAND) OOT (CCGR48)
rawnand.u_gpmi_input_apb_clk NAND_USDHC_BUS_CLK_R ccm_clk_enable_rawnand
OOT (CCGR48)
APBHDMA apbhdma.hclk NAND_USDHC_BUS_CLK_R ccm_clk_enable_rawnand
OOT (CCGR48)
apbhdma_sec.mst_hclk NAND_USDHC_BUS_CLK_R ccm_clk_enable_rawnand
OOT (CCGR48)
ARM Platform coresight.DBGCLK MAIN_AXI_CLK_ROOT ccm_clk_enable_trace
(CCGR72)
coresight.traceclkin TRACE_CLK_ROOT ccm_clk_enable_trace
(CCGR72)
Table continues on the next page...
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254 NXP Semiconductors
Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
dap.dapclk_2_2 AHB_CLK_ROOT ccm_clk_enable_debug
(CCGR4)
m7.CLKIN ARM_M7_CLK_ROOT ccm_clk_enable_m7
m7.FCLK ARM_M7_CLK_ROOT ccm_clk_enable_m7
m7.ATCLK ARM_M7_CLK_ROOT ccm_clk_enable_debug
(CCGR4)
m7.DAPCLK AHB_CLK_ROOT ccm_clk_enable_debug
(CCGR4)
m7_sec.mst_hclk ARM_M7_CLK_ROOT ccm_clk_enable_m7
ASRC asrc_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
asrc_ipg_gatedclk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
BCH rawnand.u_gpmi_bch_input_bch_clk NAND_USDHC_BUS_CLK_R ccm_clk_enable_rawnand
(RAWNAND) OOT (CCGR48)
CAAM caam.aclk AHB_CLK_ROOT -
caam.ipg_clk IPG_CLK_ROOT -
caam.ipg_clk_s IPG_CLK_ROOT -
CCM ccmsrcgpcmix.ipg_clk IPG_CLK_ROOT ccm_clk_enable_mrpr
(CCMSRCGPCM (CCGR100)
IX)
DDR (DDRMIX) ddrmix.dram_alt_clk_root DRAM_ALT_CLK_ROOT ccm_clk_enable_dram1
(CCGR5)
ddrmix.dram_apb_clk_root DRAM_APB_CLK_ROOT ccm_clk_enable_dram1
(CCGR5)
eARC earc_ipg_earc_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
earc_phy_ai_clk SYS_OSC_CLK ccm_clk_enable_audio
(CCGR101)
earc_phy_audio_ss_clk SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
ECSPI ecspi1.ipg_clk_per ECSPI1_CLK_ROOT ccm_clk_enable_ecspi1
(CCGR7)
ecspi1.ipg_clk IPG_CLK_ROOT ccm_clk_enable_ecspi1
(CCGR7)
ecspi1.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_ecspi1
(CCGR7)
ecspi2.ipg_clk_per ECSPI2_CLK_ROOT ccm_clk_enable_ecspi2
(CCGR8)
ecspi2.ipg_clk IPG_CLK_ROOT ccm_clk_enable_ecspi2
(CCGR8)
ecspi2.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_ecspi2
(CCGR8)
Table continues on the next page...
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NXP Semiconductors 255
Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
ecspi3.ipg_clk_per ECSPI3_CLK_ROOT ccm_clk_enable_ecspi3
(CCGR9)
ecspi3.ipg_clk IPG_CLK_ROOT ccm_clk_enable_ecspi3
(CCGR9)
ecspi3.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_ecspi3
(CCGR9)
eDMA edma_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
asrc_ipg_gatedclk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
ENET_QOS enet_qos.aclk_i ENET_AXI_CLK_ROOT ccm_clk_enable_enet_qos
(CCGR59)
enet_qos.clk_csr_i ENET_AXI_CLK_ROOT ccm_clk_enable_enet_qos
(CCGR59)
enet_qos.clk_ptp_ref_i ENET_QOS_TIMER_CLK_R ccm_clk_enable_enet_qos
OOT (CCGR59)
enet_qos_mem.mem_clk ENET_AXI_CLK_ROOT ccm_clk_enable_enet_qos
(CCGR59)
enet_qos_mem.clk_ptp_ref_i ENET_QOS_TIMER_CLK_R ccm_clk_enable_enet_qos
OOT (CCGR59)
ENETn enet1.ipg_clk ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1.ipg_clk_mac0 ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1.ipg_clk_mac0_s ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1.ipg_clk_s ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1.ipp_ind_mac0_txclk ENET_REF_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1.ipg_clk_time ENET_TIMER_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1_mem.mac0_rxmem_clk ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
enet1_mem.mac0_txmem_clk ENET_AXI_CLK_ROOT ccm_clk_enable_enet1
(CCGR10)
FlexCAN can1.ipg_clk IPG_CLK_ROOT ccm_clk_enable_can1
(CCGR53)
can1.ipg_clk_chi IPG_CLK_ROOT ccm_clk_enable_can1
(CCGR53)
can1.ipg_clk_pe CAN1_PECLK_MUXED ccm_clk_enable_can1
(CCGR53)
can1.ipg_clk_pe_nogate CAN1_PECLK_MUXED ccm_clk_enable_can1
(CCGR53)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
can1.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_can1
(CCGR53)
can1.ipt_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_can1
(CCGR53)
can1.osc_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_can1
(CCGR53)
can1_mem.can_hclk IPG_CLK_ROOT ccm_clk_enable_can1
(CCGR53)
can2.ipg_clk IPG_CLK_ROOT ccm_clk_enable_can2
(CCGR54)
can2.ipg_clk_chi IPG_CLK_ROOT ccm_clk_enable_can2
(CCGR54)
can2.ipg_clk_pe CAN2_PECLK_MUXED ccm_clk_enable_can2
(CCGR54)
can2.ipg_clk_pe_nogate CAN2_PECLK_MUXED ccm_clk_enable_can2
(CCGR54)
can2.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_can2
(CCGR54)
can2.ipt_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_can2
(CCGR54)
can2.osc_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_can2
(CCGR54)
can2_mem.can_hclk IPG_CLK_ROOT ccm_clk_enable_can2
(CCGR54)
FlexSPI flexspi.hclk AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi.ipg_clk IPG_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi.ipg_clk_sfck QSPI_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.AHBRX_CLKA AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.AHBRX_CLKB AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.IPTX_CLKA AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.IPTX_CLKB AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.IPRX_CLKA AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.IPRX_CLKB AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
flexspi_mem.LUT_CLKA AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_mem.LUT_CLKB AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_sec.mst_hclk AHB_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
flexspi_sec.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_flexspi
(CCGR47)
GPC ccmsrcgpcmix.ipg_clk IPG_CLK_ROOT ccm_clk_enable_mrpr
(CCMSRCGPCM (CCGR100)
IX) ccmsrcgpcmix.ckil_clk CKIL_SYNC_CLK_ROOT ccm_clk_enable_mrpr
(CCGR100)
GPIO gpio1.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_gpio1
(CCGR11)
gpio2.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_gpio2
(CCGR12)
gpio3.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_gpio3
(CCGR13)
gpio4.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_gpio4
(CCGR14)
gpio5.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_gpio5
(CCGR15)
GPMI rawnand.u_gpmi_bch_input_gpmi_io_clk NAND_CLK_ROOT ccm_clk_enable_rawnand
(RAWNAND) (CCGR48)
GPT gpt1.ipg_clk GPT1_CLK_ROOT ccm_clk_enable_gpt1
(CCGR16)
gpt1.ipg_clk_highfreq GPT1_CLK_ROOT ccm_clk_enable_gpt1
(CCGR16)
gpt1.ipg_clk_s GPT1_CLK_ROOT ccm_clk_enable_gpt1
(CCGR16)
gpt1.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt1
(CCGR16)
gpt2.ipg_clk GPT2_CLK_ROOT ccm_clk_enable_gpt2
(CCGR17)
gpt2.ipg_clk_highfreq GPT2_CLK_ROOT ccm_clk_enable_gpt2
(CCGR17)
gpt2.ipg_clk_s GPT2_CLK_ROOT ccm_clk_enable_gpt2
(CCGR17)
gpt2.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt2
(CCGR17)
gpt3.ipg_clk GPT3_CLK_ROOT ccm_clk_enable_gpt3
(CCGR18)
gpt3.ipg_clk_highfreq GPT3_CLK_ROOT ccm_clk_enable_gpt3
(CCGR18)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
gpt3.ipg_clk_s GPT3_CLK_ROOT ccm_clk_enable_gpt3
(CCGR18)
gpt3.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt3
(CCGR18)
gpt4.ipg_clk GPT4_CLK_ROOT ccm_clk_enable_gpt4
(CCGR19)
gpt4.ipg_clk_highfreq GPT4_CLK_ROOT ccm_clk_enable_gpt4
(CCGR19)
gpt4.ipg_clk_s GPT4_CLK_ROOT ccm_clk_enable_gpt4
(CCGR19)
gpt4.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt4
(CCGR19)
gpt5.ipg_clk GPT5_CLK_ROOT ccm_clk_enable_gpt5
(CCGR20)
gpt5.ipg_clk_highfreq GPT5_CLK_ROOT ccm_clk_enable_gpt5
(CCGR20)
gpt5.ipg_clk_s GPT5_CLK_ROOT ccm_clk_enable_gpt5
(CCGR20)
gpt5.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt5
(CCGR20)
gpt6.ipg_clk GPT6_CLK_ROOT ccm_clk_enable_gpt6
(CCGR21)
gpt6.ipg_clk_highfreq GPT6_CLK_ROOT ccm_clk_enable_gpt6
(CCGR21)
gpt6.ipg_clk_s GPT6_CLK_ROOT ccm_clk_enable_gpt6
(CCGR21)
gpt6.ipg_clk_24m ANAMIX_OSC_24M_CLK ccm_clk_enable_gpt6
(CCGR21)
GPU 520L gpumix.ccm_gpu_ahb_clk_root GPU_AHB_CLK_ROOT ccm_clk_enable_gpu_all
(GPUMIX)
ccm_clk_enable_gpu2d
(CCGR69)
ccm_clk_enable_gpu
(CCGR87)
gpumix.ccm_gpu_axi_clk_root GPU_AXI_CLK_ROOT ccm_clk_enable_gpu_all
ccm_clk_enable_gpu2d
(CCGR69)
ccm_clk_enable_gpu
(CCGR87)
gpumix.ccm_gpu_g2d2x_clk_root GPU2D_CLK_ROOT ccm_clk_enable_gpu2d
(CCGR69)
GPU 7000UL gpumix.ccm_gpu_ahb_clk_root GPU_AHB_CLK_ROOT ccm_clk_enable_gpu_all
(GPUMIX)
ccm_clk_enable_gpu3d
(CCGR70)
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
ccm_clk_enable_gpu
(CCGR87)
gpumix.ccm_gpu_axi_clk_root GPU_AXI_CLK_ROOT ccm_clk_enable_gpu_all
ccm_clk_enable_gpu3d
(CCGR70)
ccm_clk_enable_gpu
(CCGR87)
gpumix.ccm_gpu_g3d2x_clk_root GPU3D_CORE_CLK_ROOT ccm_clk_enable_gpu3d
(CCGR70)
gpumix.ccm_gpu_g3dsh_clk_root GPU3D_SHADER_CLK_RO ccm_clk_enable_gpu3d
OT (CCGR70)
HDMI TRNG clk HDMI_APB_CLK ccm_clk_enable_hdmi
Controller (CCGR95)
(HDMIMIX)
HDMI TX iapb_hpi_clk HDMI_APB_CLK ccm_clk_enable_hdmi
Controller (CCGR95)
(HDMIMIX) iapbclk HDMI_APB_CLK ccm_clk_enable_hdmi
(CCGR95)
iesmclk HDMI_HTX_REF266M_CLK ccm_clk_enable_hdmi
(CCGR95)
HDMI TX BLK apb_clk HDMI_APB_CLK ccm_clk_enable_hdmi
CTRL (HDMIMIX) (CCGR95)
apb_clkg HDMI_APB_CLK ccm_clk_enable_hdmi
(CCGR95)
HIFI 4 DSP hifi4cluster_hifi_core__CLK AUDIO_HIFI4_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
hifi4cluster_hifi_dbg_apbs__pclkm AUDIO_HIFI4_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
HTX PAI apb_clk HDMI_APB_CLK ccm_clk_enable_hdmi
(HDMIMIX) (CCGR95)
apb_gatedclk HDMI_APB_CLK ccm_clk_enable_hdmi
(CCGR95)
HTX PVI apb_clk HDMI_APB_CLK ccm_clk_enable_hdmi
(HDMIMIX) (CCGR95)
apb_clkg HDMI_APB_CLK ccm_clk_enable_hdmi
(CCGR95)
I2Cn i2c1.ipg_clk_patref I2C1_CLK_ROOT ccm_clk_enable_i2c1
(CCGR23)
i2c1.ipg_clk_s I2C1_CLK_ROOT ccm_clk_enable_i2c1
(CCGR23)
i2c2.ipg_clk_patref I2C2_CLK_ROOT ccm_clk_enable_i2c2
(CCGR24)
i2c2.ipg_clk_s I2C2_CLK_ROOT ccm_clk_enable_i2c2
(CCGR24)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
i2c3.ipg_clk_patref I2C3_CLK_ROOT ccm_clk_enable_i2c3
(CCGR25)
i2c3.ipg_clk_s I2C3_CLK_ROOT ccm_clk_enable_i2c3
(CCGR25)
i2c4.ipg_clk_patref I2C4_CLK_ROOT ccm_clk_enable_i2c4
(CCGR26)
i2c4.ipg_clk_s I2C4_CLK_ROOT ccm_clk_enable_i2c4
(CCGR26)
i2c5.ipg_clk_patref I2C5_CLK_ROOT ccm_clk_enable_i2c5
(CCGR51)
i2c5.ipg_clk_s I2C5_CLK_ROOT ccm_clk_enable_i2c5
(CCGR51)
i2c6.ipg_clk_patref I2C6_CLK_ROOT ccm_clk_enable_i2c6
(CCGR52)
i2c6.ipg_clk_s I2C6_CLK_ROOT ccm_clk_enable_i2c6
(CCGR52)
IOMUXC iomuxc.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_iomux
(CCGR27)
iomuxc_gpr.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_iomux
(CCGR27)
IRQ_STEER irq_steer.ipg_clk IPG_CLK_ROOT ccm_clk_enable_irq_steer
(CCGR63)
IRQ_STEER ipg_clk HDMI_APB_CLK ccm_clk_enable_hdmi
(HDMIMIX) (CCGR95)
ISI (MEDIAMIX) apb_clk MEDIA_APB_CLK_ROOT ccm_clk_enable_media
(CCGR93)
ipg_proc_clk[0] MEDIA_AXI_CLK_ROOT ccm_clk_enable_media
(CCGR93)
ipg_proc_clk[1] MEDIA_AXI_CLK_ROOT ccm_clk_enable_media
(CCGR93)
ipg_proc_ungated_clk MEDIA_AXI_CLK_ROOT ccm_clk_enable_media
(CCGR93)
axi_clk MEDIA_AXI_CLK_ROOT ccm_clk_enable_media
(CCGR93)
ISP (MEDIAMIX) mediamix.ccm_media_mix_isp_cor_clk_ro MEDIA_ISP_CLK_ROOT ccm_clk_enable_media
ot (CCGR93)
LCDIF apb_clk MEDIA_AXI_CLK_ROOT ccm_clk_enable_media
(MEDIAMIX) (CCGR93)
pixel_clk MEDIA_DISP1_PIX_CLK_RO ccm_clk_enable_media
OT (CCGR93)
pixel_clk MEDIA_DISP2_PIX_CLK_RO ccm_clk_enable_media
OT (CCGR93)
LCDIF apb_clk HDMI_APB_CLK ccm_clk_enable_hdmi
(HDMIMIX) (CCGR95)
Table continues on the next page...
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Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
b_clk HDMI_B_CLK ccm_clk_enable_hdmi
(CCGR95)
LDB (MEDIAMIX) mediamix.ccm_media_ldb_serial_clk MEDIA_LDB_CLK_ROOT ccm_clk_enable_media
(CCGR93)
MICFIL pdm_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
pdm_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_app_nonstop AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_app AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_inp AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dc AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_hb AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fir AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_app_fifo AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad_dec[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad_dec16[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad_ndec[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad_zcd[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_vad_noise[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[0] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[1] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[1] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
Table continues on the next page...
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262 NXP Semiconductors
Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
pdm_ipg_clk_fifo[1] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[2] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[2] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[2] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[3] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[3] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[3] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[4] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[4] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[4] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[5] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[5] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[5] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[6] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[6] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[6] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec[7] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_dec16[7] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_fifo[7] AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_decfil AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
pdm_ipg_clk_decfil_free AUDIO_PDM_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
MIPI_DSI mipi_dsi_CLKREF MEDIA_MIPI_DSI_REF_CLK ccm_clk_enable_media
(MEDIAMIX) _ROOT (CCGR93)
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NXP Semiconductors 263
Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
mipi_dsi_I_PCLK MEDIA_APB_CLK_ROOT ccm_clk_enable_media
(CCGR93)
MU mu1.ipg_clk_dsp IPG_CLK_ROOT ccm_clk_enable_mu
(CCGR33)
mu1.ipg_clk_mcu IPG_CLK_ROOT ccm_clk_enable_mu
(CCGR33)
mu1.ipg_clk_s_dsp IPG_CLK_ROOT ccm_clk_enable_mu
(CCGR33)
mu1.ipg_clk_s_mcu IPG_CLK_ROOT ccm_clk_enable_mu
(CCGR33)
MU (AUDIOMIX) mu2_ipg_clk_dsp AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu2_ipg_clk_s_dsp AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu2_ipg_clk_mcu AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu2_ipg_clk_s_mcu AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu3_ipg_clk_dsp AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu3_ipg_clk_s_dsp AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu3_ipg_clk_mcu AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
mu3_ipg_clk_s_mcu AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
NPU mlmix.ccm_npu_ahb_clk_root ML_AHB_CLK_ROOT ccm_clk_enable_npu
(CCGR91)
mlmix.ccm_npu_axi_clk_root ML_AXI_CLK_ROOT ccm_clk_enable_npu
(CCGR91)
mlmix.ccm_npu_npu2x_clk_root ML_CLK_ROOT ccm_clk_enable_npu
(CCGR91)
OCOTP_CTRL ocotp.ipg_clk IPG_CLK_ROOT ccm_clk_enable_ocotp
(CCGR34)
ocotp.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_ocotp
(CCGR34)
OCRAM ocram_mem.clk MAIN_AXI_CLK_ROOT ccm_clk_enable_ocram
(CCGR35)
ocram_s_mem.clk AHB_CLK_ROOT ccm_clk_enable_ocram_s
(CCGR36)
OCRAM ocram_a_clk AUDIO_HIFI4_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
PCIe (HSIOMIX) module_clk HSIOMIX_BUS_CLK_ROOT ccm_clk_enable_hsio
(CCGR92)
Table continues on the next page...
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264 NXP Semiconductors
Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
ipg_clk IPG_CLK_ROOT ccm_clk_enable_hsio
(CCGR92)
aux_clk PCIE_AUX_CLK_ROOT ccm_clk_enable_pcie
(CCGR37)
PWM pwm1.ipg_clk PWM1_CLK_ROOT ccm_clk_enable_pwm1
(CCGR40)
pwm1.ipg_clk_highfreq PWM1_CLK_ROOT ccm_clk_enable_pwm1
(CCGR40)
pwm1.ipg_clk_s PWM1_CLK_ROOT ccm_clk_enable_pwm1
(CCGR40)
pwm2.ipg_clk PWM2_CLK_ROOT ccm_clk_enable_pwm2
(CCGR41)
pwm2.ipg_clk_highfreq PWM2_CLK_ROOT ccm_clk_enable_pwm2
(CCGR41)
pwm2.ipg_clk_s PWM2_CLK_ROOT ccm_clk_enable_pwm2
(CCGR41)
pwm3.ipg_clk PWM3_CLK_ROOT ccm_clk_enable_pwm3
(CCGR42)
pwm3.ipg_clk_highfreq PWM3_CLK_ROOT ccm_clk_enable_pwm3
(CCGR42)
pwm3.ipg_clk_s PWM3_CLK_ROOT ccm_clk_enable_pwm3
(CCGR42)
pwm4.ipg_clk PWM4_CLK_ROOT ccm_clk_enable_pwm4
(CCGR43)
pwm4.ipg_clk_highfreq PWM4_CLK_ROOT ccm_clk_enable_pwm4
(CCGR43)
pwm4.ipg_clk_s PWM4_CLK_ROOT ccm_clk_enable_pwm4
(CCGR43)
RDC rdc.ipg_clk IPG_CLK_ROOT ccm_clk_enable_rdc
(CCGR49)
rdc.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_rdc
(CCGR49)
SAIn sai1_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
sai1_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai1_sai_mclk_1 SAI__MCLK_MUX.SAI1_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai1_sai_mclk_2 SAI__MCLK_MUX.SAI1_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
sai1_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai1_ipt_clk_sai_bclk CCM_SAI1_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
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NXP Semiconductors 265
Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
sai2_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai2_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai2_sai_mclk_1 SAI__MCLK_MUX.SAI2_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai2_sai_mclk_2 SAI__MCLK_MUX.SAI2_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
sai2_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai2_ipt_clk_sai_bclk CCM_SAI2_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai3_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai3_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai3_sai_mclk_1 SAI__MCLK_MUX.SAI3_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai3_sai_mclk_2 SAI__MCLK_MUX.SAI3_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
sai3_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai3_ipt_clk_sai_bclk CCM_SAI3_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai5_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai5_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai5_sai_mclk_1 SAI__MCLK_MUX.SAI5_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai5_sai_mclk_2 SAI__MCLK_MUX.SAI5_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
sai5_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai5_ipt_clk_sai_bclk CCM_SAI5_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai6_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai6_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai6_sai_mclk_1 SAI__MCLK_MUX.SAI6_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai6_sai_mclk_2 SAI__MCLK_MUX.SAI6_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
sai6_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai7_ipt_clk_sai_bclk CCM_SAI6_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai7_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai7_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
sai7_sai_mclk_1 SAI__MCLK_MUX.SAI7_MCL ccm_clk_enable_audio
K_1_ROOT (CCGR101)
sai7_sai_mclk_2 SAI__MCLK_MUX.SAI7_MCL ccm_clk_enable_audio
K_2_ROOT (CCGR101)
sai7_sai_mclk_3 SAI_PLL_DIV2.CLK_OUT ccm_clk_enable_audio
(CCGR101)
sai7_ipt_clk_sai_bclk CCM_SAI7_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
SDMA sdma1.ips_hostctrl_clk IPG_CLK_ROOT ccm_clk_enable_sdma1
(CCGR58)
sdma1.sdma_core_clk IPG_CLK_ROOT ccm_clk_enable_sdma1
(CCGR58)
sdma1.sdma_ap_ahb_clk AHB_CLK_ROOT ccm_clk_enable_sdma1
(CCGR58)
SDMA spba2_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
sdma2_sdma_core_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
SEMA4 sema1.clk IPG_CLK_ROOT ccm_clk_enable_sema1
(CCGR61)
sema2.clk IPG_CLK_ROOT ccm_clk_enable_sema2
(CCGR62)
SJC sjc.tck
SNVS snvs_hp_wrapper.ipg_clk IPG_CLK_ROOT ccm_clk_enable_snvs
(CCGR71)
snvs_hp_wrapper.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_snvs
(CCGR71)
SPBA spba1.ipg_clk IPG_CLK_ROOT ccm_clk_enable_ipmux3
(CCGR30)
SPBA spba2_ipg_clk_s AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(AUDIOMIX) (CCGR101)
spba2_ipg_clk AUDIO_AHB_CLK_ROOT ccm_clk_enable_audio
(CCGR101)
SRC ccmsrcgpcmix.ipg_clk IPG_CLK_ROOT ccm_clk_enable_mrpr
(CCMSRCGPCM (CCGR100)
IX)
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Clock Control Module (CCM)
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
SYS_CTR sctr.ipg_clk IPG_CLK_ROOT ccm_clk_enable_sctr
(CCGR57)
sctr.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_sctr
(CCGR57)
sctr.scan_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_sctr
(CCGR57)
sctr.sys_ctr_base_clk ANAMIX_OSC_24M_CLK ccm_clk_enable_sctr
(CCGR57)
UART uart1.ipg_clk IPG_CLK_ROOT ccm_clk_enable_uart1
(CCGR73)
uart1.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_uart1
(CCGR73)
uart1.ipg_perclk UART1_CLK_ROOT ccm_clk_enable_uart1
(CCGR73)
uart2.ipg_clk IPG_CLK_ROOT ccm_clk_enable_uart2
(CCGR74)
uart2.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_uart2
(CCGR74)
uart2.ipg_perclk UART2_CLK_ROOT ccm_clk_enable_uart2
(CCGR74)
uart3.ipg_clk IPG_CLK_ROOT ccm_clk_enable_uart3
(CCGR75)
uart3.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_uart3
(CCGR75)
uart3.ipg_perclk UART3_CLK_ROOT ccm_clk_enable_uart3
(CCGR75)
uart4.ipg_clk IPG_CLK_ROOT ccm_clk_enable_uart4
(CCGR76)
uart4.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_uart4
(CCGR76)
uart4.ipg_perclk UART4_CLK_ROOT ccm_clk_enable_uart4
(CCGR76)
USB (HSIOMIX) module_clk HSIOMIX_BUS_CLK_ROOT ccm_clk_enable_hsio
(CCGR92)
ipg_clk IPG_CLK_ROOT ccm_clk_enable_hsio
(CCGR92)
ckil_sync CKIL_SYNC_CLK_ROOT ccm_clk_enable_usb
(CCGR77)
USDHC usdhc1.hclk NAND_USDHC_BUS_CLK_R ccm_clk_enable_usdhc1
OOT (CCGR81)
usdhc1.ipg_clk IPG_CLK_ROOT ccm_clk_enable_usdhc1
(CCGR81)
usdhc1.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_usdhc1
(CCGR81)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-2. System Clocks (continued)
Module Module Clock (instance.clock) Clock Root Module Clock Gating
Enable
usdhc1.ipg_clk_perclk USDHC1_CLK_ROOT ccm_clk_enable_usdhc1
(CCGR81)
usdhc2.hclk NAND_USDHC_BUS_CLK_R ccm_clk_enable_usdhc2
OOT (CCGR82)
usdhc2.ipg_clk IPG_CLK_ROOT ccm_clk_enable_usdhc2
(CCGR82)
usdhc2.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_usdhc2
(CCGR82)
usdhc2.ipg_clk_perclk USDHC2_CLK_ROOT ccm_clk_enable_usdhc2
(CCGR82)
usdhc3.hclk NAND_USDHC_BUS_CLK_R ccm_clk_enable_usdhc3
OOT (CCGR94)
usdhc3.ipg_clk IPG_CLK_ROOT ccm_clk_enable_usdhc3
(CCGR94)
usdhc3.ipg_clk_s IPG_CLK_ROOT ccm_clk_enable_usdhc3
(CCGR94)
usdhc3.ipg_clk_perclk USDHC3_CLK_ROOT ccm_clk_enable_usdhc3
(CCGR94)
VPU G1 vpumix.g1_core_clk VPU_G1_CLK_ROOT ccm_clk_enable_vpu_g1
(VPUMIX) (CCGR86)
VPU G2 vpumix.g2_core_clk VPU_G2_CLK_ROOT ccm_clk_enable_vpu_g2
(VPUMIX) (CCGR90)
VPU VC8000E vpumix.main_clk VPU_BUS_CLK_ROOT ccm_clk_enable_vpu
(VPUMIX) (CCGR99)
vpumix.vc8000e_core_clk VPU_VC8000E_CLK_ROOT ccm_clk_enable_vpu_vc8ke
(CCGR89)
WDOG wdog1.ipg_clk WDOG_CLK_ROOT ccm_clk_enable_wdog1
(CCGR83)
wdog1.ipg_clk_s WDOG_CLK_ROOT ccm_clk_enable_wdog1
(CCGR83)
wdog2.ipg_clk WDOG_CLK_ROOT ccm_clk_enable_wdog2
(CCGR84)
wdog2.ipg_clk_s WDOG_CLK_ROOT ccm_clk_enable_wdog2
(CCGR84)
wdog3.ipg_clk WDOG_CLK_ROOT ccm_clk_enable_wdog3
(CCGR85)
wdog3.ipg_clk_s WDOG_CLK_ROOT ccm_clk_enable_wdog3
(CCGR85)
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Clock Control Module (CCM)
5.1.5 Functional Description
CCM receives clocks from PLLs and oscillators. Then the clock root generation logic
inside CCM will generate various clock roots required for core, bus, and peripheral
blocks. These clock roots will be delivered to each module through LPCG, which
contains the clock gating logic for each clock.
The following sections further describe the functional details of CCM.
5.1.5.1 Input Clocks
The table below describes the input clock sources that supply the 8: 1 selector muxes to
the clock slices in the clock root generator.
Control Register Input Clock Frequency (MHz) Description
(CCM_PLL_CTRLn)
12 ARM_PLL_CLK 1000 Arm PLL
13 GPU_PLL_CLK 1000 GPU PLL clock output
14 VPU_PLL_CLK 800 VPU PLL clock output
15 DRAM_PLL1_CLK 1067 DDR PLL
16 SYSTEM_PLL1_CLK 800 System PLL1 output clock
17 SYSTEM_PLL1_DIV2 400 System PLL1 divided 2 clock output
18 SYSTEM_PLL1_DIV3 266 System PLL1 divided 3 clock output
19 SYSTEM_PLL1_DIV4 200 System PLL1 divided 4 clock output
20 SYSTEM_PLL1_DIV5 160 System PLL1 divided 5 clock output
21 SYSTEM_PLL1_DIV6 133 System PLL1 divided 6 clock output
22 SYSTEM_PLL1_DIV8 100 System PLL1 divided 8 clock output
23 SYSTEM_PLL1_DIV10 80 System PLL1 divided 10 clock output
24 SYSTEM_PLL1_DIV20 40 System PLL1 divided 20 clock output
25 SYSTEM_PLL2_CLK 1000 System PLL2 output clock
26 SYSTEM_PLL2_DIV2 500 System PLL2 divided 2 clock output
27 SYSTEM_PLL2_DIV3 333 System PLL2 divided 3 clock output
28 SYSTEM_PLL2_DIV4 250 System PLL2 divided 4 clock output
29 SYSTEM_PLL2_DIV5 200 System PLL2 divided 5 clock output
30 SYSTEM_PLL2_DIV6 166 System PLL2 divided 6 clock output
31 SYSTEM_PLL2_DIV8 125 System PLL2 divided 8 clock output
32 SYSTEM_PLL2_DIV10 100 System PLL2 divided 10 clock output
33 SYSTEM_PLL2_DIV20 50 System PLL2 divided 20 clock output
34 SYSTEM_PLL3_CLK 1000 System PLL3 output clock
35 AUDIO_PLL1_CLK 650 Audio PLL1 clock output
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Control Register Input Clock Frequency (MHz) Description
(CCM_PLL_CTRLn)
36 AUDIO_PLL2_CLK 650 Audio PLL2 clock output
37 VIDEO_PLL_CLK 1190 Video PLL clock output
external source 32K_REF_CLK 0.032 32K oscillator clock output
external source 24M_REF_CLK 24 24M oscillator clock output
external source EXT_CLK_1 133 Clock input from external IO
external source EXT_CLK_2 133 Clock input from external IO
external source EXT_CLK_3 133 Clock input from external IO
external source EXT_CLK_4 133 Clock input from external IO
5.1.5.2 CKIL Synchronizer
CCM provides a synchronized version of the 32K clock called CKIL Synchronizer
(CKIL_SYNC). The CKIL_SYNC clock is generated and synchronized by the
IPG_CLK_ROOT when IPG_CLK_ROOT is active.
When the system enters low-power mode that requires the shutdown of
IPG_CLK_ROOT, the CKIL Synchonrizer will be bypassed and fed directly from the
XTALOSC 32K source.
NOTE
CKIL_SYNC needs to be configured the same as the PLL for
ipg_clk
5.1.5.3 Clock Components
The details of the CCM clock components are detailed below.
5.1.5.3.1 Clock Divider
The synchronized clock dividers (PRE_PODF and POST_PODF) can be used to perform
integer division on the source clock frequency. The divider guarantees a clean clock
signal on its output during the change of the divide factor. Dividers perform a 1/(N+1)
divide. A glitch can cause a sync-divider to go into an unrecoverable state, therefore a
clean clock signal must be provided to a sync-divider.
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NXP Semiconductors 271
Clock Control Module (CCM)
5.1.5.3.2 Clock Switching Multiplexer
The 2-to-1 clock switching multiplexers can guarantee a clean clock signal when
switching between 2 clock sources. Both clock inputs must be active when switching. If
there is any glitch in the selected clock source, then it may be transferred to the output
clock while the de-selected source is blocked. Glitches may cause an unpredictable state,
and will recover in 2~3 cycles.
The clock switching multiplexers shutdown the current active clock source before
switching. After receiving an acknowledgement that the current clock source has
shutdown, the multiplexer turns on the selected clock source. As the acknowledgement of
turning on the new clock source is received, the clock source switch finishes.
5.1.5.3.3 Clock Gate
A clock gate cell is used to gate clocks. When gated, the clock will stop at 0. A clock gate
cell can accept glitches on its clock inputs. If the gate cell is off, it will block or absorb
glitches. If the gate cell is on, it may pass glitches to its output. A gate cell needs 2~3
clock cycles to change states. The state during this period is either on or off and will
recover in 2~3 cycles, but cannot be predicted which state it is in during this period.
5.1.5.3.4 8 to 1 Multiplexer
The 8-to-1 multiplexer is a combinational multiplexer that can switch anytime. The
multiplexer output does not guarantee a clean clock signal. The output clock path from
the multiplexer must be clock gated before changing the multiplexer selection. This will
insure a clean clock source change.
5.1.5.4 Clock Slices
There are several types of clock generation slices in CCM. The slices are categorized as
Core, Bus, Peripheral (IP), and DRAM.
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Chapter 5 Clocks and Power Management
Clock Source from Clock Root 0
PLL/PFD/Divider Clock Slice 0
Clock Root 1
Clock Slice 1
...
Clock Root N
Clock Slice N
Figure 5-4. Clock Slices
The following figure illustrates the CCM clock components that a clock slice can
comprise of, and the associated register controls. Not all clock slice types will comprise
of all the components provided in the figure below. Please refer to the following sections
to identify the components included in particular clock slice type. The slice shown below
is comprised of a post divider and a clock switching multiplexer with 2 input sources.
Each input source has a pre-divider, a clock gate and a clock multiplexer inside.
CCM_PREn[MUX_A]
clk 0
clk 1
MUX_A
CCM_PREn[EN_A]
clk 2
clk 3 CG
clk 4
clk 5 CCM_PREn[PRE_PODF_A]
CCM_POSTn[SELECT]
clk 6
clk 7 PRE_PODF_A
MUX
POST_PODF
PRE_PODF_B
CCM_POSTn[POST_PODF]
MUX_B
CCM_PREn[PRE_PODF_B]
CG
CCM_PREn[EN_B]
CCM_PREn[MUX_B]
Figure 5-5. Clock Slice Components
5.1.5.4.1 Core clock slice
Core clock slices are designed for high speed, non-stop clock generation, typically for an
Arm core. A core clock slice is comprised of a post divider and a 2-to-1 clock switching
multiplexer with 2 input sources. Each input source has a clock gate and a 8-to-1 clock
multiplexer. To run at high frequency, the post divider is only 3 bits, which is half the bit
width of other slices. The two 8-to-1 multiplexers are not glitch-less, so switching them
should only be done when they are clock gated to prevent propagation glitches.
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Clock Control Module (CCM)
clk 0
clk 1
MUX_A
clk 2
clk 3
CG
clk 4
clk 5
clk 6
clk 7
MUX
POST_PODF
MUX_B
CG
Figure 5-6. Core clock slice
5.1.5.4.2 Bus clock slice
Bus clock slices are comprised of a post divider and a clock switching multiplexer with 2
input sources. Each input source has a pre-divider, a clock gate and a clock multiplexer
inside. The pre-divider is three bits and provides a maximum division factor of 8. The
post-divider is six bits. The two 8-to-1 multiplexers are not glitch-less, so switching
should only be done when they are clock gated to prevent propagation glitches. The eight
clock selections are the same for MUX_A and MUX_B.
clk 0
clk 1
MUX_A
clk 2
clk 3 CG
clk 4
clk 5
clk 6
clk 7 PRE_PODF_A
MUX
POST_PODF
PRE_PODF_B
MUX_B
CG
Figure 5-7. Bus clock slice
5.1.5.4.3 Peripheral clock slice
The peripheral (IP) clock slices are comprised of a clock multiplexer, clock gate, pre-
divider and post-divider. The pre-divider is three bit and can divide down by a factor of 8.
The post-divider is six bit . The 8-to-1 multiplexer is not glitch-less, so switching should
only be done when they are clock gated to prevent propagation glitches.
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Peripheral clock slices must be stopped to change the clock source.
clk 0
clk 1
clk 2
MUX_A
clk 3
clk 4 CG PRE_PODF_A POST_PODF
clk 5
clk 6
clk 7
Figure 5-8. Peripheral clock slice
5.1.5.4.4 SSCG and Fractional PLLs
The Spread Spectrum Clock Generator (SSCG) and Fractional-N PLLs are detailed
below.
The fractional PLL consists of a phase-frequency detector (PFD), charge pump, voltage
controller oscillator (VCO), a 6-bit pre divider, 10-bit main divider, a 3-bit scaler, a delta-
sigma modulator (DSM) and an automatic frequency control (AFC).
The figure below shows the Fractional PLL block diagram.
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Clock Control Module (CCM)
AFC_ENB
EXTAFC[4:0]
MUX
ICP[2:0] AFC_CODE[4:0]
5
FREF
Phase UP Voltage
Charge VCOOUT FOUT
Pre-Divider Frequency Controlled Scaler
FIN FEED Pump
Detector DN Oscillator
P[5:0] S[2:0] BYPASS
Main /2Divider
K[15:0] Divider
SEL_PF[1:0]
20 10
Modulation
SSCG_EN DSM
Control
FSEL
MFR[7:0] MRR[5:0] M[9:0]
FREF
FEED _OUT
MUX
FEED
FREF
AFC_ENB
FEED AFC
AFC_CODE[4:0]
FEED_EN
FIN/p Phase Voltage FVCO Post-Scaler
Pre- Divider
FIN Frequency Controlled (s) FOUT
(p)
Detector Ocsillator
Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_PRE_DIV]
Pre-Divider Main Divider
FVCO/m
(m)
Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_MAIN_DIV]
Main Divider
Programmable CCM_ANALOG_xx_FDIV_CTL0[PLL_POST_DIV]
Post-Divider
Figure 5-9. Fractional PLL Block Diagram
Formula for Fraction PLLOUT:
• FOUT=((m + k/65536) × FIN) / (p × 2s)
• Where, 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6, -32768 ≤ k ≤ 32767
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• p, m, and s are unsigned integers. k is a two's complement integer.
• Where, FOUT is the output frequency, FIN is the input frequency, and p,m,s and k
are division values for pre-divider, main divider, scaler and DSM respectively
When SSCG_EN = 1, the spread spectrum mode is enabled. The associated formulas and
values are provided below:
• Modulation frequency (MF) = FFIN / p / mfr / (25) [Hz]
• Modulation rate (MR) = mfr × mrr / m / (26) × 100 [%]
• Where, 0 ≤ mfr ≤ 255, 1 ≤ mrr ≤ 63, 0 ≤ mrr × mfr ≤ 512
The ARM PLL, GPU PLL, VPU PLL, DRAM PLL, Audio PLL1/2, and Video PLL1 are
fractional PLLs. The frequency on these can be tuned to be very accurate to meet audio
and video interface requirements.
5.1.5.5 Clock gate control
CCM can perform automatic clock shutdown of on-chip peripherals according to system
low power mode. Each logic domain can respectively declare its dependency level on
each clock. If a clock is detected that is not dependant on any domain, it will be shutdown
to save power.
Clock generation inside the CCM creates a clock root for on-chip peripherals. Before the
clock root goes into peripherals via low power clock gating cells. By controlling these
LPCGs, CCM can manage on-chip peripheral clocks.
Clock gate controls use active clock gating in LPCG, which means an active clock root is
required. The clock generation module only performs multiplexing, gating and dividing
on clock sources. Therefore, the clock root from the generation module will stop when
the corresponding clock source stops.
The ENABLE bit must be set for the clock root that LPCG is actively gating.
5.1.5.6 Clock source control
The CCM can perform automatic PLL shutdown of CCM_ANALOG according to
system low power mode. Each logic domain can respectively declare its dependency
level on each clock. If a PLL is not dependent on any domain, it will be shutdown to save
power.
PLLs in CCM_ANALOG can also be controlled by the CCM via setting the override bits
in the respective PLL's control register.
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For PLLs, there are controls on every PLL. PLLs are the source for the PFDs and
dividers. For any clock that is enabled, its source must be left on, otherwise, the behavior
is undefined. For a shutdown clock source, if it is set as dependent by writing to the clock
source control registers (CCM_PLL_CTRLn[SETTING0/1/2/3]), the controlling logic
will turn on the source immediately, while the setting goes into a shadow register. After
the clock source is ready, the setting will be accepted by the source control logic, and
copied from the shadow register to the setting register. Handshake with the PLL happens
if the change of the setting causes a PLL to start up or shutdown. The time cost is
determined by the PLL that is under control. Software can poll the setting field for a new
setting value.
5.1.5.7 Access control
CCM can implement its own access control based on domain to provide more precise
control on shared resources. Access controls are implemented on clock root generation,
clock gate control, and clock source control. Access control logic does not impact read
access, but blocks unauthentic write access.
Access controls on clock root generation are independent between every clock root. A
sticky authentic fail flag is set when a domain writes to a register and authentication fails.
The access control logic contains a whitelist and a semaphore. By default, each clock
root's access control logic is disabled after power-on reset. Software can enable access
control anytime after reset.
NOTE
Once access logic is enabled, it cannot be disabled until the
next power-on reset.
Table 5-3. Whitelist
Enabled Write access will be authenticated before being performed.
Disabled every access on protected item will be performed.
NOTE
Only domains that are on the whitelist can perform write access
to this clock root when access control is enabled.
Table 5-4. Semaphore
Enabled A domain must obtain the semaphore’s ownership before its write access can be
authenticated. Only a domain on the whitelist can obtain the ownership and the
ownership will last until the domain explicitly releases the ownership. Semaphore
obtain will fail if it is already fetched by some other domain.
Disabled Authentic check will check only on whitelist.
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NOTE
Semaphore is intended to help software keep the clock root
from unexpectedly changing.
Access control of clock gate and clock source control is performed in a simple operation.
Every domain can only write on the bits for it's own setting. Any write to irrespective
domain will be ignored.
5.1.5.8 System level considerations
Clock shutdown strategy
Any clock shutdown should first shutdown the LPCG, then the PLL. If the LPCG is
configured not to shutdown, the clock root for the LPCG should not stop either. Violating
this rule leads the system into an unpredictable state.
Core clock root frequency
If the core clock is set lower than one third of the IPG clock, SRC needs to generate a
longer reset signal to match the requirement from the Arm core. This typically happens
when the Arm core runs at some divided value of the XTAL 24M while IPG clock is
supplied by the PLL.
DRAM clock
The DRAM PHYM clock needs a clock frequency faster than 400MHz.
USB CLOCK
The USB clock may not be a reliable clock source in some applications. This clock may
stop when USB cable is disconnected.
5.1.6 Programming Guide
5.1.6.1 Set, Clear, and Toggle register features
Every register of the CCM has set, clear, and toggle features.
The set feature for a given register is located at:
Base Address of the register + 0x04
The clear feature for a given register is located at:
Base Address of the regsister + 0x08
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The toggle feature is located at:
Base Address of the register + 0x0c
Read from all 4 locations to get the current register value. Writing to the base register bits
sets the register to the write value. Writing 1 to the set register bits sets them to 1, while
writing 0 has no effect. Writing 1 to the clear register bits clears them to 0, while writing
0 has no effect. Writing 1 to the toggle register bits sets them to invert the value, while
writing 0 has no effect.
5.1.6.2 PLL Interface
CCM can control PLLs inside CCM_ANALOG when entering or leaving low-power
mode. Software must set the PLL override inside CCM_ANALOG before entering low-
power mode after power-on reset (POR).
There are four levels of low-power modes in a logic domain:
• Not needed
• Needed in RUN
• Needed in RUN and WAIT
• Needed in RUN, WAIT, and STOP
CCM only takes action while domain status are switching between STOP (DEEP SLEEP
mode is considered the same as STOP). There are 4 domains that can be assigned. Any
CPU platform can be assigned to any domain by RDC. If a domain is empty, the domain
is considered as STOP.
Each domain can declare its dependency to CCM. The use of any clock, without
declaring it in its own domain, is not permitted. A domain declares its dependency on a
clock by writing the dependency level. Settings against behavior in low-power mode are
as follows:
Table 5-5. Domain Dependency
Domain Level Run Wait Stop / Deep sleep
0
1 Required
2 Required Required
3 Required Required Required
Table 5-6. CCGR Program Interface
CC Domain3 Domain2 Domain1 Domain0
GR
Table continues on the next page...
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Table 5-6. CCGR Program Interface (continued)
31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Level1 Level0 Level1 Level0 Level1 Level0 Level1 Level0
Each domain can change only bits assigned to control access. Any irrelevant write to it
will be ignored. For example, Domain 0 can only write to bits [1:0]. Any bits written to,
other than bits [1:0], will be ignored. Other domains can read all of the other domain
settings. The default value for domain 0 is 2, and will enter STOP mode after shutting
down. When the default value of the other domain setting is 0, it will not be required.
When setting clock source, the settings will not take effect immediately. The setting will
enter the shadow register first. If a PLL shutdown or new setting enters the shadow
register to declare dependency on the PLL, the PLL will turn on immediately. When the
PLL is ready, the setting in shadow register will be updated to the new setting. During
this period, the pending bit will be set and cleared. Then CCM will send the PLL control
signal as a shadow register and inform GPC the PLL status according to the setting
register. In other cases, the setting will be updated from the shadow register immediately.
Clock sources have dependency on each other.
NOTE
Do not shutdown the parent clock when the required child clock
is active. Attempting to do so will lead to unpredicable and
unrecoverable behavior. It is recommended to shutdown the
parent clock and child clock together.
5.1.6.3 CCGR Interface
Before a clock root goes to on–chip peripherals, the clock root is distributed through low
power clock gates (LPCG). These LPCG are implemented to automatically perform clock
shutdown when a domain enters and leaves a low-power state.
There are four levels of low-power modes in a logic domain:
• Not needed
• Needed in RUN
• Needed in RUN and WAIT
• Needed in RUN, WAIT, and STOP
CCM only takes action while domain status are switching between STOP (DEEP SLEEP
mode is considered the same as STOP). There are 4 domains that can be assigned. Any
CPU platform can be assigned to any domain by RDC. If a domain is empty, the domain
is considered as STOP.
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Clock Control Module (CCM)
Each domain can declare its dependency to CCM. The use of any clock, without
declaring it in its own domain, is not permitted. A domain declares its dependency on a
clock by writing the dependency level. Settings against behavior in low-power mode are
as follows:
Table 5-7. Domain Dependency
Domain Level RUN WAIT STOP/ DEEP SLEEP
0
1 Required
2 Required Required
3 Required Required Required
Table 5-8. CCGR Program Interface
CC Domain3 Domain2 Domain1 Domain0
GR
31-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Level1 Level0 Level1 Level0 Level1 Level0 Level1 Level0
Each domain can change only bits assigned to control access. Any irrelevant write to it
will be ignored. For example, Domain 0 can only write to bits [1:0]. Any bits written to,
other than bits [1:0], will be ignored. Other domains can read all of the other domain
settings. The default value for domain 0 is 2, and will enter STOP mode after shutting
down. When the default value of the other domain setting is 0, it will not be required.
The table below lists the CCM Clock Gating Register (CCGR) and associated offset for
each LPCG enable.
NOTE
Not all CCGRs are mapped.
NOTE
Sec_debug clock gating (CCGR60) must be active in low
power mode. DO NOT gate this clock in low power mode to
guarantee the low power mode functions such as stop WDOG
counting.
Table 5-9. CCGR Mapping Table
Gating Register LPCG Enable Offset
CCM_CCGR0 DVFS 0x4000
CCM_CCGR1 Anamix 0x4010
CCM_CCGR2 CPU 0x4020
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Table 5-9. CCGR Mapping Table (continued)
Gating Register LPCG Enable Offset
CCM_CCGR3 CSU 0x4030
CCM_CCGR4 Debug 0x4040
CCM_CCGR5 DRAM1 0x4050
CCM_CCGR6 Reserved 0x4060
CCM_CCGR7 ECSPI1 0x4070
CCM_CCGR8 ECSPI2 0x4080
CCM_CCGR9 ECSPI3 0x4090
CCM_CCGR10 ENET1 0x40A0
CCM_CCGR11 GPIO1 0x40B0
CCM_CCGR12 GPIO2 0x40C0
CCM_CCGR13 GPIO3 0x40D0
CCM_CCGR14 GPIO4 0x40E0
CCM_CCGR15 GPIO5 0x40F0
CCM_CCGR16 GPT1 0x4100
CCM_CCGR17 GPT2 0x4110
CCM_CCGR18 GPT3 0x4120
CCM_CCGR19 GPT4 0x4130
CCM_CCGR20 GPT5 0x4140
CCM_CCGR21 GPT6 0x4150
CCM_CCGR22 HS 0x4160
CCM_CCGR23 I2C1 0x4170
CCM_CCGR24 I2C2 0x4180
CCM_CCGR25 I2C3 0x4190
CCM_CCGR26 I2C4 0x41A0
CCM_CCGR27 IOMUX 0x41B0
CCM_CCGR28 IPMUX1 0x41C0
CCM_CCGR29 IPMUX2 0x41D0
CCM_CCGR30 IPMUX3 0x41E0
CCM_CCGR31 Reserved 0x41F0
CCM_CCGR32 Reserved 0x4200
CCM_CCGR33 MU 0x4210
CCM_CCGR34 OCOTP 0x4220
CCM_CCGR35 OCRAM 0x4230
CCM_CCGR36 OCRAM_s 0x4240
CCM_CCGR37 PCIE 0x4250
CCM_CCGR38 PERFMON1 0x4260
CCM_CCGR39 PERFMON2 0x4270
CCM_CCGR40 PWM1 0x4280
CCM_CCGR41 PWM2 0x4290
Table continues on the next page...
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Table 5-9. CCGR Mapping Table (continued)
Gating Register LPCG Enable Offset
CCM_CCGR42 PWM3 0x42A0
CCM_CCGR43 PWM4 0x42B0
CCM_CCGR44 QoS 0x42C0
CCM_CCGR45 Reserved 0x42D0
CCM_CCGR46 QoS_ENET 0x42E0
CCM_CCGR47 FLEXSPI 0x42F0
CCM_CCGR48 RAWNAND 0x4300
CCM_CCGR49 RDC 0x4310
CCM_CCGR50 ROM 0x4320
CCM_CCGR51 I2C5 0x4330
CCM_CCGR52 I2C6 0x4340
CCM_CCGR53 CAN1 0x4350
CCM_CCGR54 CAN2 0x4360
CCM_CCGR55 Reserved 0x4370
CCM_CCGR56 Reserved 0x4380
CCM_CCGR57 SCTR 0x4390
CCM_CCGR58 SDMA1 0x43A0
CCM_CCGR59 ENET_QoS 0x43B0
CCM_CCGR60 SEC_DEBUG 0x43C0
CCM_CCGR61 SEMA1 0x43D0
CCM_CCGR62 SEMA2 0x43E0
CCM_CCGR63 IRQ_STEER 0x43F0
CCM_CCGR64 SIM_ENET 0x4400
CCM_CCGR65 SIM_m 0x4410
CCM_CCGR66 SIM_main 0x4420
CCM_CCGR67 SIM_s 0x4430
CCM_CCGR68 SIM_wakeup 0x4440
CCM_CCGR69 GPU2D 0x4450
CCM_CCGR70 GPU3D 0x4460
CCM_CCGR71 SNVS 0x4470
CCM_CCGR72 TRACE 0x4480
CCM_CCGR73 UART1 0x4490
CCM_CCGR74 UART2 0x44A0
CCM_CCGR75 UART3 0x44B0
CCM_CCGR76 UART4 0x44C0
CCM_CCGR77 USB 0x44D0
CCM_CCGR78 Reserved 0x44E0
CCM_CCGR79 USB_PHY 0x44F0
CCM_CCGR80 Reserved 0x4500
Table continues on the next page...
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Table 5-9. CCGR Mapping Table (continued)
Gating Register LPCG Enable Offset
CCM_CCGR81 USDHC1 0x4510
CCM_CCGR82 USDHC2 0x4520
CCM_CCGR83 WDOG1 0x4530
CCM_CCGR84 WDOG2 0x4540
CCM_CCGR85 WDOG3 0x4550
CCM_CCGR86 VPU_G1 0x4560
CCM_CCGR87 GPU 0x4570
CCM_CCGR88 NOC_WRAPPER 0x4580
CCM_CCGR89 VPU_VC8KE 0x4590
CCM_CCGR90 VPU_G2 0x45A0
CCM_CCGR91 NPU 0x45B0
CCM_CCGR92 HSIO 0x45C0
CCM_CCGR93 MEDIA 0x45D0
CCM_CCGR94 USDHC3 0x45E0
CCM_CCGR95 HDMI 0x45F0
CCM_CCGR96 XTAL 0x4600
CCM_CCGR97 PLL 0x4610
CCM_CCGR98 TSENSOR 0x4620
CCM_CCGR99 VPU 0x4630
CCM_CCGR100 MRPR 0x4640
CCM_CCGR101 AUDIO 0x4650
CCM_CCGR102 Reserved 0x4660
5.1.6.4 Target Interface
The Target Interface is optimized to simplify software operation. Using this interface, all
clock roots are in the same program model with the same register bit field mapping. The
software does not handle the details of the clock slice and clock slice types. Software
writes the desired settings to the register, and the internal hardware logic generates a
required sequence to achieve the desired settings.
The Target Interface requires the software to provide whether a clock is active, the clock
source number to be selected, pre-divide value, and post-divide value. If a clock slice
does not support a setting, that setting is simply ignored, and will not effect the supported
fields.
Freq = (clock source freq)/(pre_div+1)/(post_div+1)
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The internal logic sequence of the Target Interface guarantees a clean clock on output
without frequency overshoot. A requirement of the Target Interface's software is that the
target clock source is active.
The Target Interface sequence begins by opening all clocks, applying highest divider
value, switching to the new clock source, then decreasing divider value to the target
frequency. If Shutdown is requested, it will be performed last.
The clock output is always active when using the Target Interface. For intermediate
frequency requests, the Target Interface choses the lowest frequency source to avoid
frequency overshoot on the Peripheral clock slices. For Core and Bus clock slices, the
clock switching multiplexer is used to guarantee smooth clock switching.
A write operation on a target interface completes once the output clock is running at the
desired setting. Software polling is not necessary to determine clock stability.
STEP STATE OPERATION
0 SMART_IDLE Idle state, no write operation is pending
1 SMART_WAIT_READY State occurs when a write access is received, wait for every
field to be ready
2 SMART_APPLY_GATE1 Open all branches, all gates inside clock slices
3 SMART_WAIT_GATE1 Wait for gate applied
4 SMART_APPLY_PODF1 apply post divider and post divider for if new value generate
slower clock
5 SMART_WAIT_PODF1 Wait for divider accept new value
6 SMART_APPLY_GATE2 shutdown spare branch if exist, else shutdown working
branch
7 SMART_WAIT_GATE2 Wait for shutdown operation complete
8 SMART_APPLY_MUX Change multiplexer to new source on spare branch if exist,
else switch working one
9 SMART_APPLY_GATE3 open gates on all branches
10 SMART_WAIT_GATE3 Wait for gates opened
11 SMART_APPLY_SWITCH Switch clock switching multiplexer if there is one
12 SMART_WAIT_SWITCH Wait for clock switching multiplexer switch
13 SMART_APPLY_PODF2 apply post divider and post divider for if new value generate
faster clock
14 SMART_WAIT_PODF2 Wait for divider accept new value
15 SMART_APPLY_GATE4 apply clock gate setting, shutdown spare one if there is
16 SMART_WAIT_GATE4 Wait for gate applied
17 SMART_APPLY_AUTO apply auto and auto divider
18 SMART_DONE Finish, wait for bus operation complete
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5.1.6.5 Normal Interface
Normal interface is more controllable than target interface. And also provides protections
against dangerous operations.
Normal interface provides safe sequences to handle each clock component, divider, gate,
and multiplexer. But it is software that needs to guarantee the order and relationship
between updating components.
Writing to this interface will complete immediately, and internal logic will continue to
apply written values to clock components. A busy flag will be asserted during
application.
Field access rules:
1. Only one field can be modified at a time
2. No field can be modified when any field is pending
3. Do not violate change condition in following table
FIELD CHANGE CONDITION FINISH CONDITION
Auto immediate
Auto-divider immediate
Bypass Gatea active and gateb active Bypass switch complete
Post-divider New divider value applied
Gate B Bypass disable New gate value active
Pre-divider B Bypass disable and gateb not gated New divider value applied
MUX B Bypass disable and gateb gating immediate
Gate A Bypass New gate value active
Pre-divider A Bypass and gatea not gated New divider value applied
MUX A Bypass and gatea gating immediate
• Error will be reported if access rules violated.
• Unsafe or ambiguous access will be ignored.
If a write access iss blocked by normal interface, the write operation will be ignored. And
a sticky bit “violate” will be set. The bit will last until software clears it explicitly. The
violate bit is 4 bits inside CCM, each for a logic domain. Each domain can read and clear
the bit for itself, the bits for other domain is neither visible nor clearable.
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5.1.7 CCM Memory Map/Register Definition
The Memory Map below represents the full array for CCM.
NOTE
Not all mapped Clock Slices and CCGRs are tied to functional
components.
Please see the following for the functional mapping tables and information:
• CCM_PLL_CTRL - Input Clocks
• CCM_TARGET_ROOT - Clock Root Selects
• CCM_CCGR - CCGR Interface
CCM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0000 General Purpose Register (CCM_GPR0) 32 R/W 0000_0000h 5.1.7.1/444
3038_0004 General Purpose Register (CCM_GPR0_SET) 32 R/W 0000_0000h 5.1.7.1/444
3038_0008 General Purpose Register (CCM_GPR0_CLR) 32 R/W 0000_0000h 5.1.7.1/444
3038_000C General Purpose Register (CCM_GPR0_TOG) 32 R/W 0000_0000h 5.1.7.1/444
3038_0800 CCM PLL Control Register (CCM_PLL_CTRL0) 32 R/W 0000_0002h 5.1.7.2/445
3038_0804 CCM PLL Control Register (CCM_PLL_CTRL0_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0808 CCM PLL Control Register (CCM_PLL_CTRL0_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_080C CCM PLL Control Register (CCM_PLL_CTRL0_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0810 CCM PLL Control Register (CCM_PLL_CTRL1) 32 R/W 0000_0002h 5.1.7.2/445
3038_0814 CCM PLL Control Register (CCM_PLL_CTRL1_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0818 CCM PLL Control Register (CCM_PLL_CTRL1_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_081C CCM PLL Control Register (CCM_PLL_CTRL1_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0820 CCM PLL Control Register (CCM_PLL_CTRL2) 32 R/W 0000_0002h 5.1.7.2/445
3038_0824 CCM PLL Control Register (CCM_PLL_CTRL2_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0828 CCM PLL Control Register (CCM_PLL_CTRL2_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_082C CCM PLL Control Register (CCM_PLL_CTRL2_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0830 CCM PLL Control Register (CCM_PLL_CTRL3) 32 R/W 0000_0002h 5.1.7.2/445
3038_0834 CCM PLL Control Register (CCM_PLL_CTRL3_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0838 CCM PLL Control Register (CCM_PLL_CTRL3_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_083C CCM PLL Control Register (CCM_PLL_CTRL3_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0840 CCM PLL Control Register (CCM_PLL_CTRL4) 32 R/W 0000_0002h 5.1.7.2/445
3038_0844 CCM PLL Control Register (CCM_PLL_CTRL4_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0848 CCM PLL Control Register (CCM_PLL_CTRL4_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_084C CCM PLL Control Register (CCM_PLL_CTRL4_TOG) 32 R/W 0000_0002h 5.1.7.5/451
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
288 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0850 CCM PLL Control Register (CCM_PLL_CTRL5) 32 R/W 0000_0002h 5.1.7.2/445
3038_0854 CCM PLL Control Register (CCM_PLL_CTRL5_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0858 CCM PLL Control Register (CCM_PLL_CTRL5_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_085C CCM PLL Control Register (CCM_PLL_CTRL5_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0860 CCM PLL Control Register (CCM_PLL_CTRL6) 32 R/W 0000_0002h 5.1.7.2/445
3038_0864 CCM PLL Control Register (CCM_PLL_CTRL6_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0868 CCM PLL Control Register (CCM_PLL_CTRL6_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_086C CCM PLL Control Register (CCM_PLL_CTRL6_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0870 CCM PLL Control Register (CCM_PLL_CTRL7) 32 R/W 0000_0002h 5.1.7.2/445
3038_0874 CCM PLL Control Register (CCM_PLL_CTRL7_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0878 CCM PLL Control Register (CCM_PLL_CTRL7_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_087C CCM PLL Control Register (CCM_PLL_CTRL7_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0880 CCM PLL Control Register (CCM_PLL_CTRL8) 32 R/W 0000_0002h 5.1.7.2/445
3038_0884 CCM PLL Control Register (CCM_PLL_CTRL8_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0888 CCM PLL Control Register (CCM_PLL_CTRL8_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_088C CCM PLL Control Register (CCM_PLL_CTRL8_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0890 CCM PLL Control Register (CCM_PLL_CTRL9) 32 R/W 0000_0002h 5.1.7.2/445
3038_0894 CCM PLL Control Register (CCM_PLL_CTRL9_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0898 CCM PLL Control Register (CCM_PLL_CTRL9_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_089C CCM PLL Control Register (CCM_PLL_CTRL9_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08A0 CCM PLL Control Register (CCM_PLL_CTRL10) 32 R/W 0000_0002h 5.1.7.2/445
3038_08A4 CCM PLL Control Register (CCM_PLL_CTRL10_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_08A8 CCM PLL Control Register (CCM_PLL_CTRL10_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08AC CCM PLL Control Register (CCM_PLL_CTRL10_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08B0 CCM PLL Control Register (CCM_PLL_CTRL11) 32 R/W 0000_0002h 5.1.7.2/445
3038_08B4 CCM PLL Control Register (CCM_PLL_CTRL11_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_08B8 CCM PLL Control Register (CCM_PLL_CTRL11_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08BC CCM PLL Control Register (CCM_PLL_CTRL11_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08C0 CCM PLL Control Register (CCM_PLL_CTRL12) 32 R/W 0000_0002h 5.1.7.2/445
3038_08C4 CCM PLL Control Register (CCM_PLL_CTRL12_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_08C8 CCM PLL Control Register (CCM_PLL_CTRL12_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08CC CCM PLL Control Register (CCM_PLL_CTRL12_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08D0 CCM PLL Control Register (CCM_PLL_CTRL13) 32 R/W 0000_0002h 5.1.7.2/445
3038_08D4 CCM PLL Control Register (CCM_PLL_CTRL13_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_08D8 CCM PLL Control Register (CCM_PLL_CTRL13_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08DC CCM PLL Control Register (CCM_PLL_CTRL13_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08E0 CCM PLL Control Register (CCM_PLL_CTRL14) 32 R/W 0000_0002h 5.1.7.2/445
3038_08E4 CCM PLL Control Register (CCM_PLL_CTRL14_SET) 32 R/W 0000_0002h 5.1.7.3/447
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 289
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_08E8 CCM PLL Control Register (CCM_PLL_CTRL14_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08EC CCM PLL Control Register (CCM_PLL_CTRL14_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_08F0 CCM PLL Control Register (CCM_PLL_CTRL15) 32 R/W 0000_0002h 5.1.7.2/445
3038_08F4 CCM PLL Control Register (CCM_PLL_CTRL15_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_08F8 CCM PLL Control Register (CCM_PLL_CTRL15_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_08FC CCM PLL Control Register (CCM_PLL_CTRL15_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0900 CCM PLL Control Register (CCM_PLL_CTRL16) 32 R/W 0000_0002h 5.1.7.2/445
3038_0904 CCM PLL Control Register (CCM_PLL_CTRL16_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0908 CCM PLL Control Register (CCM_PLL_CTRL16_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_090C CCM PLL Control Register (CCM_PLL_CTRL16_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0910 CCM PLL Control Register (CCM_PLL_CTRL17) 32 R/W 0000_0002h 5.1.7.2/445
3038_0914 CCM PLL Control Register (CCM_PLL_CTRL17_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0918 CCM PLL Control Register (CCM_PLL_CTRL17_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_091C CCM PLL Control Register (CCM_PLL_CTRL17_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0920 CCM PLL Control Register (CCM_PLL_CTRL18) 32 R/W 0000_0002h 5.1.7.2/445
3038_0924 CCM PLL Control Register (CCM_PLL_CTRL18_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0928 CCM PLL Control Register (CCM_PLL_CTRL18_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_092C CCM PLL Control Register (CCM_PLL_CTRL18_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0930 CCM PLL Control Register (CCM_PLL_CTRL19) 32 R/W 0000_0002h 5.1.7.2/445
3038_0934 CCM PLL Control Register (CCM_PLL_CTRL19_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0938 CCM PLL Control Register (CCM_PLL_CTRL19_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_093C CCM PLL Control Register (CCM_PLL_CTRL19_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0940 CCM PLL Control Register (CCM_PLL_CTRL20) 32 R/W 0000_0002h 5.1.7.2/445
3038_0944 CCM PLL Control Register (CCM_PLL_CTRL20_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0948 CCM PLL Control Register (CCM_PLL_CTRL20_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_094C CCM PLL Control Register (CCM_PLL_CTRL20_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0950 CCM PLL Control Register (CCM_PLL_CTRL21) 32 R/W 0000_0002h 5.1.7.2/445
3038_0954 CCM PLL Control Register (CCM_PLL_CTRL21_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0958 CCM PLL Control Register (CCM_PLL_CTRL21_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_095C CCM PLL Control Register (CCM_PLL_CTRL21_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0960 CCM PLL Control Register (CCM_PLL_CTRL22) 32 R/W 0000_0002h 5.1.7.2/445
3038_0964 CCM PLL Control Register (CCM_PLL_CTRL22_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0968 CCM PLL Control Register (CCM_PLL_CTRL22_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_096C CCM PLL Control Register (CCM_PLL_CTRL22_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0970 CCM PLL Control Register (CCM_PLL_CTRL23) 32 R/W 0000_0002h 5.1.7.2/445
3038_0974 CCM PLL Control Register (CCM_PLL_CTRL23_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0978 CCM PLL Control Register (CCM_PLL_CTRL23_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_097C CCM PLL Control Register (CCM_PLL_CTRL23_TOG) 32 R/W 0000_0002h 5.1.7.5/451
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
290 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0980 CCM PLL Control Register (CCM_PLL_CTRL24) 32 R/W 0000_0002h 5.1.7.2/445
3038_0984 CCM PLL Control Register (CCM_PLL_CTRL24_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0988 CCM PLL Control Register (CCM_PLL_CTRL24_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_098C CCM PLL Control Register (CCM_PLL_CTRL24_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0990 CCM PLL Control Register (CCM_PLL_CTRL25) 32 R/W 0000_0002h 5.1.7.2/445
3038_0994 CCM PLL Control Register (CCM_PLL_CTRL25_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0998 CCM PLL Control Register (CCM_PLL_CTRL25_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_099C CCM PLL Control Register (CCM_PLL_CTRL25_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09A0 CCM PLL Control Register (CCM_PLL_CTRL26) 32 R/W 0000_0002h 5.1.7.2/445
3038_09A4 CCM PLL Control Register (CCM_PLL_CTRL26_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09A8 CCM PLL Control Register (CCM_PLL_CTRL26_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09AC CCM PLL Control Register (CCM_PLL_CTRL26_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09B0 CCM PLL Control Register (CCM_PLL_CTRL27) 32 R/W 0000_0002h 5.1.7.2/445
3038_09B4 CCM PLL Control Register (CCM_PLL_CTRL27_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09B8 CCM PLL Control Register (CCM_PLL_CTRL27_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09BC CCM PLL Control Register (CCM_PLL_CTRL27_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09C0 CCM PLL Control Register (CCM_PLL_CTRL28) 32 R/W 0000_0002h 5.1.7.2/445
3038_09C4 CCM PLL Control Register (CCM_PLL_CTRL28_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09C8 CCM PLL Control Register (CCM_PLL_CTRL28_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09CC CCM PLL Control Register (CCM_PLL_CTRL28_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09D0 CCM PLL Control Register (CCM_PLL_CTRL29) 32 R/W 0000_0002h 5.1.7.2/445
3038_09D4 CCM PLL Control Register (CCM_PLL_CTRL29_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09D8 CCM PLL Control Register (CCM_PLL_CTRL29_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09DC CCM PLL Control Register (CCM_PLL_CTRL29_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09E0 CCM PLL Control Register (CCM_PLL_CTRL30) 32 R/W 0000_0002h 5.1.7.2/445
3038_09E4 CCM PLL Control Register (CCM_PLL_CTRL30_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09E8 CCM PLL Control Register (CCM_PLL_CTRL30_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09EC CCM PLL Control Register (CCM_PLL_CTRL30_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_09F0 CCM PLL Control Register (CCM_PLL_CTRL31) 32 R/W 0000_0002h 5.1.7.2/445
3038_09F4 CCM PLL Control Register (CCM_PLL_CTRL31_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_09F8 CCM PLL Control Register (CCM_PLL_CTRL31_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_09FC CCM PLL Control Register (CCM_PLL_CTRL31_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A00 CCM PLL Control Register (CCM_PLL_CTRL32) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A04 CCM PLL Control Register (CCM_PLL_CTRL32_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A08 CCM PLL Control Register (CCM_PLL_CTRL32_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A0C CCM PLL Control Register (CCM_PLL_CTRL32_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A10 CCM PLL Control Register (CCM_PLL_CTRL33) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A14 CCM PLL Control Register (CCM_PLL_CTRL33_SET) 32 R/W 0000_0002h 5.1.7.3/447
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 291
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_0A18 CCM PLL Control Register (CCM_PLL_CTRL33_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A1C CCM PLL Control Register (CCM_PLL_CTRL33_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A20 CCM PLL Control Register (CCM_PLL_CTRL34) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A24 CCM PLL Control Register (CCM_PLL_CTRL34_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A28 CCM PLL Control Register (CCM_PLL_CTRL34_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A2C CCM PLL Control Register (CCM_PLL_CTRL34_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A30 CCM PLL Control Register (CCM_PLL_CTRL35) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A34 CCM PLL Control Register (CCM_PLL_CTRL35_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A38 CCM PLL Control Register (CCM_PLL_CTRL35_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A3C CCM PLL Control Register (CCM_PLL_CTRL35_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A40 CCM PLL Control Register (CCM_PLL_CTRL36) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A44 CCM PLL Control Register (CCM_PLL_CTRL36_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A48 CCM PLL Control Register (CCM_PLL_CTRL36_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A4C CCM PLL Control Register (CCM_PLL_CTRL36_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A50 CCM PLL Control Register (CCM_PLL_CTRL37) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A54 CCM PLL Control Register (CCM_PLL_CTRL37_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A58 CCM PLL Control Register (CCM_PLL_CTRL37_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A5C CCM PLL Control Register (CCM_PLL_CTRL37_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_0A60 CCM PLL Control Register (CCM_PLL_CTRL38) 32 R/W 0000_0002h 5.1.7.2/445
3038_0A64 CCM PLL Control Register (CCM_PLL_CTRL38_SET) 32 R/W 0000_0002h 5.1.7.3/447
3038_0A68 CCM PLL Control Register (CCM_PLL_CTRL38_CLR) 32 R/W 0000_0002h 5.1.7.4/449
3038_0A6C CCM PLL Control Register (CCM_PLL_CTRL38_TOG) 32 R/W 0000_0002h 5.1.7.5/451
3038_4000 CCM Clock Gating Register (CCM_CCGR0) 32 R/W 0000_0002h 5.1.7.6/452
3038_4004 CCM Clock Gating Register (CCM_CCGR0_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4008 CCM Clock Gating Register (CCM_CCGR0_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_400C CCM Clock Gating Register (CCM_CCGR0_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4010 CCM Clock Gating Register (CCM_CCGR1) 32 R/W 0000_0002h 5.1.7.6/452
3038_4014 CCM Clock Gating Register (CCM_CCGR1_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4018 CCM Clock Gating Register (CCM_CCGR1_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_401C CCM Clock Gating Register (CCM_CCGR1_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4020 CCM Clock Gating Register (CCM_CCGR2) 32 R/W 0000_0002h 5.1.7.6/452
3038_4024 CCM Clock Gating Register (CCM_CCGR2_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4028 CCM Clock Gating Register (CCM_CCGR2_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_402C CCM Clock Gating Register (CCM_CCGR2_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4030 CCM Clock Gating Register (CCM_CCGR3) 32 R/W 0000_0002h 5.1.7.6/452
3038_4034 CCM Clock Gating Register (CCM_CCGR3_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4038 CCM Clock Gating Register (CCM_CCGR3_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_403C CCM Clock Gating Register (CCM_CCGR3_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
292 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4040 CCM Clock Gating Register (CCM_CCGR4) 32 R/W 0000_0002h 5.1.7.6/452
3038_4044 CCM Clock Gating Register (CCM_CCGR4_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4048 CCM Clock Gating Register (CCM_CCGR4_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_404C CCM Clock Gating Register (CCM_CCGR4_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4050 CCM Clock Gating Register (CCM_CCGR5) 32 R/W 0000_0002h 5.1.7.6/452
3038_4054 CCM Clock Gating Register (CCM_CCGR5_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4058 CCM Clock Gating Register (CCM_CCGR5_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_405C CCM Clock Gating Register (CCM_CCGR5_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4060 CCM Clock Gating Register (CCM_CCGR6) 32 R/W 0000_0002h 5.1.7.6/452
3038_4064 CCM Clock Gating Register (CCM_CCGR6_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4068 CCM Clock Gating Register (CCM_CCGR6_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_406C CCM Clock Gating Register (CCM_CCGR6_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4070 CCM Clock Gating Register (CCM_CCGR7) 32 R/W 0000_0002h 5.1.7.6/452
3038_4074 CCM Clock Gating Register (CCM_CCGR7_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4078 CCM Clock Gating Register (CCM_CCGR7_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_407C CCM Clock Gating Register (CCM_CCGR7_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4080 CCM Clock Gating Register (CCM_CCGR8) 32 R/W 0000_0002h 5.1.7.6/452
3038_4084 CCM Clock Gating Register (CCM_CCGR8_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4088 CCM Clock Gating Register (CCM_CCGR8_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_408C CCM Clock Gating Register (CCM_CCGR8_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4090 CCM Clock Gating Register (CCM_CCGR9) 32 R/W 0000_0002h 5.1.7.6/452
3038_4094 CCM Clock Gating Register (CCM_CCGR9_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4098 CCM Clock Gating Register (CCM_CCGR9_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_409C CCM Clock Gating Register (CCM_CCGR9_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40A0 CCM Clock Gating Register (CCM_CCGR10) 32 R/W 0000_0002h 5.1.7.6/452
3038_40A4 CCM Clock Gating Register (CCM_CCGR10_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_40A8 CCM Clock Gating Register (CCM_CCGR10_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40AC CCM Clock Gating Register (CCM_CCGR10_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40B0 CCM Clock Gating Register (CCM_CCGR11) 32 R/W 0000_0002h 5.1.7.6/452
3038_40B4 CCM Clock Gating Register (CCM_CCGR11_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_40B8 CCM Clock Gating Register (CCM_CCGR11_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40BC CCM Clock Gating Register (CCM_CCGR11_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40C0 CCM Clock Gating Register (CCM_CCGR12) 32 R/W 0000_0002h 5.1.7.6/452
3038_40C4 CCM Clock Gating Register (CCM_CCGR12_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_40C8 CCM Clock Gating Register (CCM_CCGR12_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40CC CCM Clock Gating Register (CCM_CCGR12_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40D0 CCM Clock Gating Register (CCM_CCGR13) 32 R/W 0000_0002h 5.1.7.6/452
3038_40D4 CCM Clock Gating Register (CCM_CCGR13_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 293
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_40D8 CCM Clock Gating Register (CCM_CCGR13_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40DC CCM Clock Gating Register (CCM_CCGR13_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40E0 CCM Clock Gating Register (CCM_CCGR14) 32 R/W 0000_0002h 5.1.7.6/452
3038_40E4 CCM Clock Gating Register (CCM_CCGR14_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_40E8 CCM Clock Gating Register (CCM_CCGR14_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40EC CCM Clock Gating Register (CCM_CCGR14_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_40F0 CCM Clock Gating Register (CCM_CCGR15) 32 R/W 0000_0002h 5.1.7.6/452
3038_40F4 CCM Clock Gating Register (CCM_CCGR15_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_40F8 CCM Clock Gating Register (CCM_CCGR15_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_40FC CCM Clock Gating Register (CCM_CCGR15_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4100 CCM Clock Gating Register (CCM_CCGR16) 32 R/W 0000_0002h 5.1.7.6/452
3038_4104 CCM Clock Gating Register (CCM_CCGR16_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4108 CCM Clock Gating Register (CCM_CCGR16_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_410C CCM Clock Gating Register (CCM_CCGR16_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4110 CCM Clock Gating Register (CCM_CCGR17) 32 R/W 0000_0002h 5.1.7.6/452
3038_4114 CCM Clock Gating Register (CCM_CCGR17_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4118 CCM Clock Gating Register (CCM_CCGR17_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_411C CCM Clock Gating Register (CCM_CCGR17_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4120 CCM Clock Gating Register (CCM_CCGR18) 32 R/W 0000_0002h 5.1.7.6/452
3038_4124 CCM Clock Gating Register (CCM_CCGR18_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4128 CCM Clock Gating Register (CCM_CCGR18_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_412C CCM Clock Gating Register (CCM_CCGR18_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4130 CCM Clock Gating Register (CCM_CCGR19) 32 R/W 0000_0002h 5.1.7.6/452
3038_4134 CCM Clock Gating Register (CCM_CCGR19_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4138 CCM Clock Gating Register (CCM_CCGR19_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_413C CCM Clock Gating Register (CCM_CCGR19_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4140 CCM Clock Gating Register (CCM_CCGR20) 32 R/W 0000_0002h 5.1.7.6/452
3038_4144 CCM Clock Gating Register (CCM_CCGR20_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4148 CCM Clock Gating Register (CCM_CCGR20_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_414C CCM Clock Gating Register (CCM_CCGR20_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4150 CCM Clock Gating Register (CCM_CCGR21) 32 R/W 0000_0002h 5.1.7.6/452
3038_4154 CCM Clock Gating Register (CCM_CCGR21_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4158 CCM Clock Gating Register (CCM_CCGR21_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_415C CCM Clock Gating Register (CCM_CCGR21_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4160 CCM Clock Gating Register (CCM_CCGR22) 32 R/W 0000_0002h 5.1.7.6/452
3038_4164 CCM Clock Gating Register (CCM_CCGR22_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4168 CCM Clock Gating Register (CCM_CCGR22_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_416C CCM Clock Gating Register (CCM_CCGR22_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
294 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4170 CCM Clock Gating Register (CCM_CCGR23) 32 R/W 0000_0002h 5.1.7.6/452
3038_4174 CCM Clock Gating Register (CCM_CCGR23_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4178 CCM Clock Gating Register (CCM_CCGR23_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_417C CCM Clock Gating Register (CCM_CCGR23_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4180 CCM Clock Gating Register (CCM_CCGR24) 32 R/W 0000_0002h 5.1.7.6/452
3038_4184 CCM Clock Gating Register (CCM_CCGR24_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4188 CCM Clock Gating Register (CCM_CCGR24_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_418C CCM Clock Gating Register (CCM_CCGR24_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4190 CCM Clock Gating Register (CCM_CCGR25) 32 R/W 0000_0002h 5.1.7.6/452
3038_4194 CCM Clock Gating Register (CCM_CCGR25_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4198 CCM Clock Gating Register (CCM_CCGR25_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_419C CCM Clock Gating Register (CCM_CCGR25_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41A0 CCM Clock Gating Register (CCM_CCGR26) 32 R/W 0000_0002h 5.1.7.6/452
3038_41A4 CCM Clock Gating Register (CCM_CCGR26_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41A8 CCM Clock Gating Register (CCM_CCGR26_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41AC CCM Clock Gating Register (CCM_CCGR26_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41B0 CCM Clock Gating Register (CCM_CCGR27) 32 R/W 0000_0002h 5.1.7.6/452
3038_41B4 CCM Clock Gating Register (CCM_CCGR27_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41B8 CCM Clock Gating Register (CCM_CCGR27_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41BC CCM Clock Gating Register (CCM_CCGR27_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41C0 CCM Clock Gating Register (CCM_CCGR28) 32 R/W 0000_0002h 5.1.7.6/452
3038_41C4 CCM Clock Gating Register (CCM_CCGR28_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41C8 CCM Clock Gating Register (CCM_CCGR28_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41CC CCM Clock Gating Register (CCM_CCGR28_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41D0 CCM Clock Gating Register (CCM_CCGR29) 32 R/W 0000_0002h 5.1.7.6/452
3038_41D4 CCM Clock Gating Register (CCM_CCGR29_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41D8 CCM Clock Gating Register (CCM_CCGR29_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41DC CCM Clock Gating Register (CCM_CCGR29_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41E0 CCM Clock Gating Register (CCM_CCGR30) 32 R/W 0000_0002h 5.1.7.6/452
3038_41E4 CCM Clock Gating Register (CCM_CCGR30_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41E8 CCM Clock Gating Register (CCM_CCGR30_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41EC CCM Clock Gating Register (CCM_CCGR30_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_41F0 CCM Clock Gating Register (CCM_CCGR31) 32 R/W 0000_0002h 5.1.7.6/452
3038_41F4 CCM Clock Gating Register (CCM_CCGR31_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_41F8 CCM Clock Gating Register (CCM_CCGR31_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_41FC CCM Clock Gating Register (CCM_CCGR31_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4200 CCM Clock Gating Register (CCM_CCGR32) 32 R/W 0000_0002h 5.1.7.6/452
3038_4204 CCM Clock Gating Register (CCM_CCGR32_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 295
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4208 CCM Clock Gating Register (CCM_CCGR32_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_420C CCM Clock Gating Register (CCM_CCGR32_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4210 CCM Clock Gating Register (CCM_CCGR33) 32 R/W 0000_0002h 5.1.7.6/452
3038_4214 CCM Clock Gating Register (CCM_CCGR33_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4218 CCM Clock Gating Register (CCM_CCGR33_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_421C CCM Clock Gating Register (CCM_CCGR33_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4220 CCM Clock Gating Register (CCM_CCGR34) 32 R/W 0000_0002h 5.1.7.6/452
3038_4224 CCM Clock Gating Register (CCM_CCGR34_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4228 CCM Clock Gating Register (CCM_CCGR34_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_422C CCM Clock Gating Register (CCM_CCGR34_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4230 CCM Clock Gating Register (CCM_CCGR35) 32 R/W 0000_0002h 5.1.7.6/452
3038_4234 CCM Clock Gating Register (CCM_CCGR35_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4238 CCM Clock Gating Register (CCM_CCGR35_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_423C CCM Clock Gating Register (CCM_CCGR35_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4240 CCM Clock Gating Register (CCM_CCGR36) 32 R/W 0000_0002h 5.1.7.6/452
3038_4244 CCM Clock Gating Register (CCM_CCGR36_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4248 CCM Clock Gating Register (CCM_CCGR36_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_424C CCM Clock Gating Register (CCM_CCGR36_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4250 CCM Clock Gating Register (CCM_CCGR37) 32 R/W 0000_0002h 5.1.7.6/452
3038_4254 CCM Clock Gating Register (CCM_CCGR37_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4258 CCM Clock Gating Register (CCM_CCGR37_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_425C CCM Clock Gating Register (CCM_CCGR37_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4260 CCM Clock Gating Register (CCM_CCGR38) 32 R/W 0000_0002h 5.1.7.6/452
3038_4264 CCM Clock Gating Register (CCM_CCGR38_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4268 CCM Clock Gating Register (CCM_CCGR38_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_426C CCM Clock Gating Register (CCM_CCGR38_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4270 CCM Clock Gating Register (CCM_CCGR39) 32 R/W 0000_0002h 5.1.7.6/452
3038_4274 CCM Clock Gating Register (CCM_CCGR39_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4278 CCM Clock Gating Register (CCM_CCGR39_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_427C CCM Clock Gating Register (CCM_CCGR39_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4280 CCM Clock Gating Register (CCM_CCGR40) 32 R/W 0000_0002h 5.1.7.6/452
3038_4284 CCM Clock Gating Register (CCM_CCGR40_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4288 CCM Clock Gating Register (CCM_CCGR40_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_428C CCM Clock Gating Register (CCM_CCGR40_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4290 CCM Clock Gating Register (CCM_CCGR41) 32 R/W 0000_0002h 5.1.7.6/452
3038_4294 CCM Clock Gating Register (CCM_CCGR41_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4298 CCM Clock Gating Register (CCM_CCGR41_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_429C CCM Clock Gating Register (CCM_CCGR41_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
296 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_42A0 CCM Clock Gating Register (CCM_CCGR42) 32 R/W 0000_0002h 5.1.7.6/452
3038_42A4 CCM Clock Gating Register (CCM_CCGR42_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42A8 CCM Clock Gating Register (CCM_CCGR42_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42AC CCM Clock Gating Register (CCM_CCGR42_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_42B0 CCM Clock Gating Register (CCM_CCGR43) 32 R/W 0000_0002h 5.1.7.6/452
3038_42B4 CCM Clock Gating Register (CCM_CCGR43_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42B8 CCM Clock Gating Register (CCM_CCGR43_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42BC CCM Clock Gating Register (CCM_CCGR43_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_42C0 CCM Clock Gating Register (CCM_CCGR44) 32 R/W 0000_0002h 5.1.7.6/452
3038_42C4 CCM Clock Gating Register (CCM_CCGR44_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42C8 CCM Clock Gating Register (CCM_CCGR44_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42CC CCM Clock Gating Register (CCM_CCGR44_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_42D0 CCM Clock Gating Register (CCM_CCGR45) 32 R/W 0000_0002h 5.1.7.6/452
3038_42D4 CCM Clock Gating Register (CCM_CCGR45_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42D8 CCM Clock Gating Register (CCM_CCGR45_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42DC CCM Clock Gating Register (CCM_CCGR45_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_42E0 CCM Clock Gating Register (CCM_CCGR46) 32 R/W 0000_0002h 5.1.7.6/452
3038_42E4 CCM Clock Gating Register (CCM_CCGR46_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42E8 CCM Clock Gating Register (CCM_CCGR46_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42EC CCM Clock Gating Register (CCM_CCGR46_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_42F0 CCM Clock Gating Register (CCM_CCGR47) 32 R/W 0000_0002h 5.1.7.6/452
3038_42F4 CCM Clock Gating Register (CCM_CCGR47_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_42F8 CCM Clock Gating Register (CCM_CCGR47_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_42FC CCM Clock Gating Register (CCM_CCGR47_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4300 CCM Clock Gating Register (CCM_CCGR48) 32 R/W 0000_0002h 5.1.7.6/452
3038_4304 CCM Clock Gating Register (CCM_CCGR48_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4308 CCM Clock Gating Register (CCM_CCGR48_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_430C CCM Clock Gating Register (CCM_CCGR48_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4310 CCM Clock Gating Register (CCM_CCGR49) 32 R/W 0000_0002h 5.1.7.6/452
3038_4314 CCM Clock Gating Register (CCM_CCGR49_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4318 CCM Clock Gating Register (CCM_CCGR49_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_431C CCM Clock Gating Register (CCM_CCGR49_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4320 CCM Clock Gating Register (CCM_CCGR50) 32 R/W 0000_0002h 5.1.7.6/452
3038_4324 CCM Clock Gating Register (CCM_CCGR50_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4328 CCM Clock Gating Register (CCM_CCGR50_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_432C CCM Clock Gating Register (CCM_CCGR50_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4330 CCM Clock Gating Register (CCM_CCGR51) 32 R/W 0000_0002h 5.1.7.6/452
3038_4334 CCM Clock Gating Register (CCM_CCGR51_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 297
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4338 CCM Clock Gating Register (CCM_CCGR51_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_433C CCM Clock Gating Register (CCM_CCGR51_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4340 CCM Clock Gating Register (CCM_CCGR52) 32 R/W 0000_0002h 5.1.7.6/452
3038_4344 CCM Clock Gating Register (CCM_CCGR52_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4348 CCM Clock Gating Register (CCM_CCGR52_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_434C CCM Clock Gating Register (CCM_CCGR52_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4350 CCM Clock Gating Register (CCM_CCGR53) 32 R/W 0000_0002h 5.1.7.6/452
3038_4354 CCM Clock Gating Register (CCM_CCGR53_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4358 CCM Clock Gating Register (CCM_CCGR53_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_435C CCM Clock Gating Register (CCM_CCGR53_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4360 CCM Clock Gating Register (CCM_CCGR54) 32 R/W 0000_0002h 5.1.7.6/452
3038_4364 CCM Clock Gating Register (CCM_CCGR54_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4368 CCM Clock Gating Register (CCM_CCGR54_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_436C CCM Clock Gating Register (CCM_CCGR54_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4370 CCM Clock Gating Register (CCM_CCGR55) 32 R/W 0000_0002h 5.1.7.6/452
3038_4374 CCM Clock Gating Register (CCM_CCGR55_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4378 CCM Clock Gating Register (CCM_CCGR55_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_437C CCM Clock Gating Register (CCM_CCGR55_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4380 CCM Clock Gating Register (CCM_CCGR56) 32 R/W 0000_0002h 5.1.7.6/452
3038_4384 CCM Clock Gating Register (CCM_CCGR56_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4388 CCM Clock Gating Register (CCM_CCGR56_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_438C CCM Clock Gating Register (CCM_CCGR56_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4390 CCM Clock Gating Register (CCM_CCGR57) 32 R/W 0000_0002h 5.1.7.6/452
3038_4394 CCM Clock Gating Register (CCM_CCGR57_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4398 CCM Clock Gating Register (CCM_CCGR57_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_439C CCM Clock Gating Register (CCM_CCGR57_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_43A0 CCM Clock Gating Register (CCM_CCGR58) 32 R/W 0000_0002h 5.1.7.6/452
3038_43A4 CCM Clock Gating Register (CCM_CCGR58_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43A8 CCM Clock Gating Register (CCM_CCGR58_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43AC CCM Clock Gating Register (CCM_CCGR58_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_43B0 CCM Clock Gating Register (CCM_CCGR59) 32 R/W 0000_0002h 5.1.7.6/452
3038_43B4 CCM Clock Gating Register (CCM_CCGR59_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43B8 CCM Clock Gating Register (CCM_CCGR59_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43BC CCM Clock Gating Register (CCM_CCGR59_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_43C0 CCM Clock Gating Register (CCM_CCGR60) 32 R/W 0000_0002h 5.1.7.6/452
3038_43C4 CCM Clock Gating Register (CCM_CCGR60_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43C8 CCM Clock Gating Register (CCM_CCGR60_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43CC CCM Clock Gating Register (CCM_CCGR60_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
298 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_43D0 CCM Clock Gating Register (CCM_CCGR61) 32 R/W 0000_0002h 5.1.7.6/452
3038_43D4 CCM Clock Gating Register (CCM_CCGR61_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43D8 CCM Clock Gating Register (CCM_CCGR61_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43DC CCM Clock Gating Register (CCM_CCGR61_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_43E0 CCM Clock Gating Register (CCM_CCGR62) 32 R/W 0000_0002h 5.1.7.6/452
3038_43E4 CCM Clock Gating Register (CCM_CCGR62_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43E8 CCM Clock Gating Register (CCM_CCGR62_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43EC CCM Clock Gating Register (CCM_CCGR62_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_43F0 CCM Clock Gating Register (CCM_CCGR63) 32 R/W 0000_0002h 5.1.7.6/452
3038_43F4 CCM Clock Gating Register (CCM_CCGR63_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_43F8 CCM Clock Gating Register (CCM_CCGR63_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_43FC CCM Clock Gating Register (CCM_CCGR63_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4400 CCM Clock Gating Register (CCM_CCGR64) 32 R/W 0000_0002h 5.1.7.6/452
3038_4404 CCM Clock Gating Register (CCM_CCGR64_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4408 CCM Clock Gating Register (CCM_CCGR64_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_440C CCM Clock Gating Register (CCM_CCGR64_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4410 CCM Clock Gating Register (CCM_CCGR65) 32 R/W 0000_0002h 5.1.7.6/452
3038_4414 CCM Clock Gating Register (CCM_CCGR65_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4418 CCM Clock Gating Register (CCM_CCGR65_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_441C CCM Clock Gating Register (CCM_CCGR65_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4420 CCM Clock Gating Register (CCM_CCGR66) 32 R/W 0000_0002h 5.1.7.6/452
3038_4424 CCM Clock Gating Register (CCM_CCGR66_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4428 CCM Clock Gating Register (CCM_CCGR66_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_442C CCM Clock Gating Register (CCM_CCGR66_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4430 CCM Clock Gating Register (CCM_CCGR67) 32 R/W 0000_0002h 5.1.7.6/452
3038_4434 CCM Clock Gating Register (CCM_CCGR67_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4438 CCM Clock Gating Register (CCM_CCGR67_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_443C CCM Clock Gating Register (CCM_CCGR67_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4440 CCM Clock Gating Register (CCM_CCGR68) 32 R/W 0000_0002h 5.1.7.6/452
3038_4444 CCM Clock Gating Register (CCM_CCGR68_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4448 CCM Clock Gating Register (CCM_CCGR68_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_444C CCM Clock Gating Register (CCM_CCGR68_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4450 CCM Clock Gating Register (CCM_CCGR69) 32 R/W 0000_0002h 5.1.7.6/452
3038_4454 CCM Clock Gating Register (CCM_CCGR69_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4458 CCM Clock Gating Register (CCM_CCGR69_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_445C CCM Clock Gating Register (CCM_CCGR69_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4460 CCM Clock Gating Register (CCM_CCGR70) 32 R/W 0000_0002h 5.1.7.6/452
3038_4464 CCM Clock Gating Register (CCM_CCGR70_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 299
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4468 CCM Clock Gating Register (CCM_CCGR70_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_446C CCM Clock Gating Register (CCM_CCGR70_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4470 CCM Clock Gating Register (CCM_CCGR71) 32 R/W 0000_0002h 5.1.7.6/452
3038_4474 CCM Clock Gating Register (CCM_CCGR71_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4478 CCM Clock Gating Register (CCM_CCGR71_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_447C CCM Clock Gating Register (CCM_CCGR71_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4480 CCM Clock Gating Register (CCM_CCGR72) 32 R/W 0000_0002h 5.1.7.6/452
3038_4484 CCM Clock Gating Register (CCM_CCGR72_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4488 CCM Clock Gating Register (CCM_CCGR72_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_448C CCM Clock Gating Register (CCM_CCGR72_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4490 CCM Clock Gating Register (CCM_CCGR73) 32 R/W 0000_0002h 5.1.7.6/452
3038_4494 CCM Clock Gating Register (CCM_CCGR73_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4498 CCM Clock Gating Register (CCM_CCGR73_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_449C CCM Clock Gating Register (CCM_CCGR73_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44A0 CCM Clock Gating Register (CCM_CCGR74) 32 R/W 0000_0002h 5.1.7.6/452
3038_44A4 CCM Clock Gating Register (CCM_CCGR74_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44A8 CCM Clock Gating Register (CCM_CCGR74_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44AC CCM Clock Gating Register (CCM_CCGR74_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44B0 CCM Clock Gating Register (CCM_CCGR75) 32 R/W 0000_0002h 5.1.7.6/452
3038_44B4 CCM Clock Gating Register (CCM_CCGR75_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44B8 CCM Clock Gating Register (CCM_CCGR75_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44BC CCM Clock Gating Register (CCM_CCGR75_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44C0 CCM Clock Gating Register (CCM_CCGR76) 32 R/W 0000_0002h 5.1.7.6/452
3038_44C4 CCM Clock Gating Register (CCM_CCGR76_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44C8 CCM Clock Gating Register (CCM_CCGR76_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44CC CCM Clock Gating Register (CCM_CCGR76_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44D0 CCM Clock Gating Register (CCM_CCGR77) 32 R/W 0000_0002h 5.1.7.6/452
3038_44D4 CCM Clock Gating Register (CCM_CCGR77_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44D8 CCM Clock Gating Register (CCM_CCGR77_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44DC CCM Clock Gating Register (CCM_CCGR77_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44E0 CCM Clock Gating Register (CCM_CCGR78) 32 R/W 0000_0002h 5.1.7.6/452
3038_44E4 CCM Clock Gating Register (CCM_CCGR78_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44E8 CCM Clock Gating Register (CCM_CCGR78_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44EC CCM Clock Gating Register (CCM_CCGR78_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_44F0 CCM Clock Gating Register (CCM_CCGR79) 32 R/W 0000_0002h 5.1.7.6/452
3038_44F4 CCM Clock Gating Register (CCM_CCGR79_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_44F8 CCM Clock Gating Register (CCM_CCGR79_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_44FC CCM Clock Gating Register (CCM_CCGR79_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
300 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4500 CCM Clock Gating Register (CCM_CCGR80) 32 R/W 0000_0002h 5.1.7.6/452
3038_4504 CCM Clock Gating Register (CCM_CCGR80_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4508 CCM Clock Gating Register (CCM_CCGR80_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_450C CCM Clock Gating Register (CCM_CCGR80_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4510 CCM Clock Gating Register (CCM_CCGR81) 32 R/W 0000_0002h 5.1.7.6/452
3038_4514 CCM Clock Gating Register (CCM_CCGR81_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4518 CCM Clock Gating Register (CCM_CCGR81_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_451C CCM Clock Gating Register (CCM_CCGR81_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4520 CCM Clock Gating Register (CCM_CCGR82) 32 R/W 0000_0002h 5.1.7.6/452
3038_4524 CCM Clock Gating Register (CCM_CCGR82_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4528 CCM Clock Gating Register (CCM_CCGR82_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_452C CCM Clock Gating Register (CCM_CCGR82_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4530 CCM Clock Gating Register (CCM_CCGR83) 32 R/W 0000_0002h 5.1.7.6/452
3038_4534 CCM Clock Gating Register (CCM_CCGR83_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4538 CCM Clock Gating Register (CCM_CCGR83_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_453C CCM Clock Gating Register (CCM_CCGR83_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4540 CCM Clock Gating Register (CCM_CCGR84) 32 R/W 0000_0002h 5.1.7.6/452
3038_4544 CCM Clock Gating Register (CCM_CCGR84_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4548 CCM Clock Gating Register (CCM_CCGR84_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_454C CCM Clock Gating Register (CCM_CCGR84_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4550 CCM Clock Gating Register (CCM_CCGR85) 32 R/W 0000_0002h 5.1.7.6/452
3038_4554 CCM Clock Gating Register (CCM_CCGR85_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4558 CCM Clock Gating Register (CCM_CCGR85_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_455C CCM Clock Gating Register (CCM_CCGR85_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4560 CCM Clock Gating Register (CCM_CCGR86) 32 R/W 0000_0002h 5.1.7.6/452
3038_4564 CCM Clock Gating Register (CCM_CCGR86_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4568 CCM Clock Gating Register (CCM_CCGR86_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_456C CCM Clock Gating Register (CCM_CCGR86_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4570 CCM Clock Gating Register (CCM_CCGR87) 32 R/W 0000_0002h 5.1.7.6/452
3038_4574 CCM Clock Gating Register (CCM_CCGR87_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4578 CCM Clock Gating Register (CCM_CCGR87_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_457C CCM Clock Gating Register (CCM_CCGR87_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4580 CCM Clock Gating Register (CCM_CCGR88) 32 R/W 0000_0002h 5.1.7.6/452
3038_4584 CCM Clock Gating Register (CCM_CCGR88_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4588 CCM Clock Gating Register (CCM_CCGR88_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_458C CCM Clock Gating Register (CCM_CCGR88_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4590 CCM Clock Gating Register (CCM_CCGR89) 32 R/W 0000_0002h 5.1.7.6/452
3038_4594 CCM Clock Gating Register (CCM_CCGR89_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 301
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4598 CCM Clock Gating Register (CCM_CCGR89_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_459C CCM Clock Gating Register (CCM_CCGR89_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45A0 CCM Clock Gating Register (CCM_CCGR90) 32 R/W 0000_0002h 5.1.7.6/452
3038_45A4 CCM Clock Gating Register (CCM_CCGR90_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45A8 CCM Clock Gating Register (CCM_CCGR90_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45AC CCM Clock Gating Register (CCM_CCGR90_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45B0 CCM Clock Gating Register (CCM_CCGR91) 32 R/W 0000_0002h 5.1.7.6/452
3038_45B4 CCM Clock Gating Register (CCM_CCGR91_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45B8 CCM Clock Gating Register (CCM_CCGR91_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45BC CCM Clock Gating Register (CCM_CCGR91_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45C0 CCM Clock Gating Register (CCM_CCGR92) 32 R/W 0000_0002h 5.1.7.6/452
3038_45C4 CCM Clock Gating Register (CCM_CCGR92_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45C8 CCM Clock Gating Register (CCM_CCGR92_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45CC CCM Clock Gating Register (CCM_CCGR92_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45D0 CCM Clock Gating Register (CCM_CCGR93) 32 R/W 0000_0002h 5.1.7.6/452
3038_45D4 CCM Clock Gating Register (CCM_CCGR93_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45D8 CCM Clock Gating Register (CCM_CCGR93_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45DC CCM Clock Gating Register (CCM_CCGR93_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45E0 CCM Clock Gating Register (CCM_CCGR94) 32 R/W 0000_0002h 5.1.7.6/452
3038_45E4 CCM Clock Gating Register (CCM_CCGR94_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45E8 CCM Clock Gating Register (CCM_CCGR94_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45EC CCM Clock Gating Register (CCM_CCGR94_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_45F0 CCM Clock Gating Register (CCM_CCGR95) 32 R/W 0000_0002h 5.1.7.6/452
3038_45F4 CCM Clock Gating Register (CCM_CCGR95_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_45F8 CCM Clock Gating Register (CCM_CCGR95_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_45FC CCM Clock Gating Register (CCM_CCGR95_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4600 CCM Clock Gating Register (CCM_CCGR96) 32 R/W 0000_0002h 5.1.7.6/452
3038_4604 CCM Clock Gating Register (CCM_CCGR96_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4608 CCM Clock Gating Register (CCM_CCGR96_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_460C CCM Clock Gating Register (CCM_CCGR96_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4610 CCM Clock Gating Register (CCM_CCGR97) 32 R/W 0000_0002h 5.1.7.6/452
3038_4614 CCM Clock Gating Register (CCM_CCGR97_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4618 CCM Clock Gating Register (CCM_CCGR97_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_461C CCM Clock Gating Register (CCM_CCGR97_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4620 CCM Clock Gating Register (CCM_CCGR98) 32 R/W 0000_0002h 5.1.7.6/452
3038_4624 CCM Clock Gating Register (CCM_CCGR98_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4628 CCM Clock Gating Register (CCM_CCGR98_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_462C CCM Clock Gating Register (CCM_CCGR98_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
302 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4630 CCM Clock Gating Register (CCM_CCGR99) 32 R/W 0000_0002h 5.1.7.6/452
3038_4634 CCM Clock Gating Register (CCM_CCGR99_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4638 CCM Clock Gating Register (CCM_CCGR99_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_463C CCM Clock Gating Register (CCM_CCGR99_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4640 CCM Clock Gating Register (CCM_CCGR100) 32 R/W 0000_0002h 5.1.7.6/452
3038_4644 CCM Clock Gating Register (CCM_CCGR100_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4648 CCM Clock Gating Register (CCM_CCGR100_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_464C CCM Clock Gating Register (CCM_CCGR100_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4650 CCM Clock Gating Register (CCM_CCGR101) 32 R/W 0000_0002h 5.1.7.6/452
3038_4654 CCM Clock Gating Register (CCM_CCGR101_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4658 CCM Clock Gating Register (CCM_CCGR101_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_465C CCM Clock Gating Register (CCM_CCGR101_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4660 CCM Clock Gating Register (CCM_CCGR102) 32 R/W 0000_0002h 5.1.7.6/452
3038_4664 CCM Clock Gating Register (CCM_CCGR102_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4668 CCM Clock Gating Register (CCM_CCGR102_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_466C CCM Clock Gating Register (CCM_CCGR102_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4670 CCM Clock Gating Register (CCM_CCGR103) 32 R/W 0000_0002h 5.1.7.6/452
3038_4674 CCM Clock Gating Register (CCM_CCGR103_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4678 CCM Clock Gating Register (CCM_CCGR103_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_467C CCM Clock Gating Register (CCM_CCGR103_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4680 CCM Clock Gating Register (CCM_CCGR104) 32 R/W 0000_0002h 5.1.7.6/452
3038_4684 CCM Clock Gating Register (CCM_CCGR104_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4688 CCM Clock Gating Register (CCM_CCGR104_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_468C CCM Clock Gating Register (CCM_CCGR104_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4690 CCM Clock Gating Register (CCM_CCGR105) 32 R/W 0000_0002h 5.1.7.6/452
3038_4694 CCM Clock Gating Register (CCM_CCGR105_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4698 CCM Clock Gating Register (CCM_CCGR105_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_469C CCM Clock Gating Register (CCM_CCGR105_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46A0 CCM Clock Gating Register (CCM_CCGR106) 32 R/W 0000_0002h 5.1.7.6/452
3038_46A4 CCM Clock Gating Register (CCM_CCGR106_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_46A8 CCM Clock Gating Register (CCM_CCGR106_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46AC CCM Clock Gating Register (CCM_CCGR106_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46B0 CCM Clock Gating Register (CCM_CCGR107) 32 R/W 0000_0002h 5.1.7.6/452
3038_46B4 CCM Clock Gating Register (CCM_CCGR107_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_46B8 CCM Clock Gating Register (CCM_CCGR107_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46BC CCM Clock Gating Register (CCM_CCGR107_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46C0 CCM Clock Gating Register (CCM_CCGR108) 32 R/W 0000_0002h 5.1.7.6/452
3038_46C4 CCM Clock Gating Register (CCM_CCGR108_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 303
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_46C8 CCM Clock Gating Register (CCM_CCGR108_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46CC CCM Clock Gating Register (CCM_CCGR108_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46D0 CCM Clock Gating Register (CCM_CCGR109) 32 R/W 0000_0002h 5.1.7.6/452
3038_46D4 CCM Clock Gating Register (CCM_CCGR109_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_46D8 CCM Clock Gating Register (CCM_CCGR109_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46DC CCM Clock Gating Register (CCM_CCGR109_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46E0 CCM Clock Gating Register (CCM_CCGR110) 32 R/W 0000_0002h 5.1.7.6/452
3038_46E4 CCM Clock Gating Register (CCM_CCGR110_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_46E8 CCM Clock Gating Register (CCM_CCGR110_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46EC CCM Clock Gating Register (CCM_CCGR110_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_46F0 CCM Clock Gating Register (CCM_CCGR111) 32 R/W 0000_0002h 5.1.7.6/452
3038_46F4 CCM Clock Gating Register (CCM_CCGR111_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_46F8 CCM Clock Gating Register (CCM_CCGR111_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_46FC CCM Clock Gating Register (CCM_CCGR111_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4700 CCM Clock Gating Register (CCM_CCGR112) 32 R/W 0000_0002h 5.1.7.6/452
3038_4704 CCM Clock Gating Register (CCM_CCGR112_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4708 CCM Clock Gating Register (CCM_CCGR112_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_470C CCM Clock Gating Register (CCM_CCGR112_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4710 CCM Clock Gating Register (CCM_CCGR113) 32 R/W 0000_0002h 5.1.7.6/452
3038_4714 CCM Clock Gating Register (CCM_CCGR113_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4718 CCM Clock Gating Register (CCM_CCGR113_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_471C CCM Clock Gating Register (CCM_CCGR113_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4720 CCM Clock Gating Register (CCM_CCGR114) 32 R/W 0000_0002h 5.1.7.6/452
3038_4724 CCM Clock Gating Register (CCM_CCGR114_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4728 CCM Clock Gating Register (CCM_CCGR114_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_472C CCM Clock Gating Register (CCM_CCGR114_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4730 CCM Clock Gating Register (CCM_CCGR115) 32 R/W 0000_0002h 5.1.7.6/452
3038_4734 CCM Clock Gating Register (CCM_CCGR115_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4738 CCM Clock Gating Register (CCM_CCGR115_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_473C CCM Clock Gating Register (CCM_CCGR115_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4740 CCM Clock Gating Register (CCM_CCGR116) 32 R/W 0000_0002h 5.1.7.6/452
3038_4744 CCM Clock Gating Register (CCM_CCGR116_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4748 CCM Clock Gating Register (CCM_CCGR116_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_474C CCM Clock Gating Register (CCM_CCGR116_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4750 CCM Clock Gating Register (CCM_CCGR117) 32 R/W 0000_0002h 5.1.7.6/452
3038_4754 CCM Clock Gating Register (CCM_CCGR117_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4758 CCM Clock Gating Register (CCM_CCGR117_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_475C CCM Clock Gating Register (CCM_CCGR117_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
304 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4760 CCM Clock Gating Register (CCM_CCGR118) 32 R/W 0000_0002h 5.1.7.6/452
3038_4764 CCM Clock Gating Register (CCM_CCGR118_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4768 CCM Clock Gating Register (CCM_CCGR118_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_476C CCM Clock Gating Register (CCM_CCGR118_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4770 CCM Clock Gating Register (CCM_CCGR119) 32 R/W 0000_0002h 5.1.7.6/452
3038_4774 CCM Clock Gating Register (CCM_CCGR119_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4778 CCM Clock Gating Register (CCM_CCGR119_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_477C CCM Clock Gating Register (CCM_CCGR119_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4780 CCM Clock Gating Register (CCM_CCGR120) 32 R/W 0000_0002h 5.1.7.6/452
3038_4784 CCM Clock Gating Register (CCM_CCGR120_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4788 CCM Clock Gating Register (CCM_CCGR120_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_478C CCM Clock Gating Register (CCM_CCGR120_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4790 CCM Clock Gating Register (CCM_CCGR121) 32 R/W 0000_0002h 5.1.7.6/452
3038_4794 CCM Clock Gating Register (CCM_CCGR121_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4798 CCM Clock Gating Register (CCM_CCGR121_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_479C CCM Clock Gating Register (CCM_CCGR121_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47A0 CCM Clock Gating Register (CCM_CCGR122) 32 R/W 0000_0002h 5.1.7.6/452
3038_47A4 CCM Clock Gating Register (CCM_CCGR122_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_47A8 CCM Clock Gating Register (CCM_CCGR122_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47AC CCM Clock Gating Register (CCM_CCGR122_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47B0 CCM Clock Gating Register (CCM_CCGR123) 32 R/W 0000_0002h 5.1.7.6/452
3038_47B4 CCM Clock Gating Register (CCM_CCGR123_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_47B8 CCM Clock Gating Register (CCM_CCGR123_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47BC CCM Clock Gating Register (CCM_CCGR123_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47C0 CCM Clock Gating Register (CCM_CCGR124) 32 R/W 0000_0002h 5.1.7.6/452
3038_47C4 CCM Clock Gating Register (CCM_CCGR124_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_47C8 CCM Clock Gating Register (CCM_CCGR124_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47CC CCM Clock Gating Register (CCM_CCGR124_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47D0 CCM Clock Gating Register (CCM_CCGR125) 32 R/W 0000_0002h 5.1.7.6/452
3038_47D4 CCM Clock Gating Register (CCM_CCGR125_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_47D8 CCM Clock Gating Register (CCM_CCGR125_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47DC CCM Clock Gating Register (CCM_CCGR125_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47E0 CCM Clock Gating Register (CCM_CCGR126) 32 R/W 0000_0002h 5.1.7.6/452
3038_47E4 CCM Clock Gating Register (CCM_CCGR126_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_47E8 CCM Clock Gating Register (CCM_CCGR126_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47EC CCM Clock Gating Register (CCM_CCGR126_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_47F0 CCM Clock Gating Register (CCM_CCGR127) 32 R/W 0000_0002h 5.1.7.6/452
3038_47F4 CCM Clock Gating Register (CCM_CCGR127_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 305
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_47F8 CCM Clock Gating Register (CCM_CCGR127_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_47FC CCM Clock Gating Register (CCM_CCGR127_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4800 CCM Clock Gating Register (CCM_CCGR128) 32 R/W 0000_0002h 5.1.7.6/452
3038_4804 CCM Clock Gating Register (CCM_CCGR128_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4808 CCM Clock Gating Register (CCM_CCGR128_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_480C CCM Clock Gating Register (CCM_CCGR128_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4810 CCM Clock Gating Register (CCM_CCGR129) 32 R/W 0000_0002h 5.1.7.6/452
3038_4814 CCM Clock Gating Register (CCM_CCGR129_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4818 CCM Clock Gating Register (CCM_CCGR129_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_481C CCM Clock Gating Register (CCM_CCGR129_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4820 CCM Clock Gating Register (CCM_CCGR130) 32 R/W 0000_0002h 5.1.7.6/452
3038_4824 CCM Clock Gating Register (CCM_CCGR130_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4828 CCM Clock Gating Register (CCM_CCGR130_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_482C CCM Clock Gating Register (CCM_CCGR130_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4830 CCM Clock Gating Register (CCM_CCGR131) 32 R/W 0000_0002h 5.1.7.6/452
3038_4834 CCM Clock Gating Register (CCM_CCGR131_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4838 CCM Clock Gating Register (CCM_CCGR131_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_483C CCM Clock Gating Register (CCM_CCGR131_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4840 CCM Clock Gating Register (CCM_CCGR132) 32 R/W 0000_0002h 5.1.7.6/452
3038_4844 CCM Clock Gating Register (CCM_CCGR132_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4848 CCM Clock Gating Register (CCM_CCGR132_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_484C CCM Clock Gating Register (CCM_CCGR132_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4850 CCM Clock Gating Register (CCM_CCGR133) 32 R/W 0000_0002h 5.1.7.6/452
3038_4854 CCM Clock Gating Register (CCM_CCGR133_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4858 CCM Clock Gating Register (CCM_CCGR133_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_485C CCM Clock Gating Register (CCM_CCGR133_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4860 CCM Clock Gating Register (CCM_CCGR134) 32 R/W 0000_0002h 5.1.7.6/452
3038_4864 CCM Clock Gating Register (CCM_CCGR134_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4868 CCM Clock Gating Register (CCM_CCGR134_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_486C CCM Clock Gating Register (CCM_CCGR134_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4870 CCM Clock Gating Register (CCM_CCGR135) 32 R/W 0000_0002h 5.1.7.6/452
3038_4874 CCM Clock Gating Register (CCM_CCGR135_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4878 CCM Clock Gating Register (CCM_CCGR135_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_487C CCM Clock Gating Register (CCM_CCGR135_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4880 CCM Clock Gating Register (CCM_CCGR136) 32 R/W 0000_0002h 5.1.7.6/452
3038_4884 CCM Clock Gating Register (CCM_CCGR136_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4888 CCM Clock Gating Register (CCM_CCGR136_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_488C CCM Clock Gating Register (CCM_CCGR136_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
306 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4890 CCM Clock Gating Register (CCM_CCGR137) 32 R/W 0000_0002h 5.1.7.6/452
3038_4894 CCM Clock Gating Register (CCM_CCGR137_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4898 CCM Clock Gating Register (CCM_CCGR137_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_489C CCM Clock Gating Register (CCM_CCGR137_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48A0 CCM Clock Gating Register (CCM_CCGR138) 32 R/W 0000_0002h 5.1.7.6/452
3038_48A4 CCM Clock Gating Register (CCM_CCGR138_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48A8 CCM Clock Gating Register (CCM_CCGR138_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48AC CCM Clock Gating Register (CCM_CCGR138_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48B0 CCM Clock Gating Register (CCM_CCGR139) 32 R/W 0000_0002h 5.1.7.6/452
3038_48B4 CCM Clock Gating Register (CCM_CCGR139_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48B8 CCM Clock Gating Register (CCM_CCGR139_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48BC CCM Clock Gating Register (CCM_CCGR139_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48C0 CCM Clock Gating Register (CCM_CCGR140) 32 R/W 0000_0002h 5.1.7.6/452
3038_48C4 CCM Clock Gating Register (CCM_CCGR140_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48C8 CCM Clock Gating Register (CCM_CCGR140_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48CC CCM Clock Gating Register (CCM_CCGR140_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48D0 CCM Clock Gating Register (CCM_CCGR141) 32 R/W 0000_0002h 5.1.7.6/452
3038_48D4 CCM Clock Gating Register (CCM_CCGR141_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48D8 CCM Clock Gating Register (CCM_CCGR141_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48DC CCM Clock Gating Register (CCM_CCGR141_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48E0 CCM Clock Gating Register (CCM_CCGR142) 32 R/W 0000_0002h 5.1.7.6/452
3038_48E4 CCM Clock Gating Register (CCM_CCGR142_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48E8 CCM Clock Gating Register (CCM_CCGR142_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48EC CCM Clock Gating Register (CCM_CCGR142_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_48F0 CCM Clock Gating Register (CCM_CCGR143) 32 R/W 0000_0002h 5.1.7.6/452
3038_48F4 CCM Clock Gating Register (CCM_CCGR143_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_48F8 CCM Clock Gating Register (CCM_CCGR143_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_48FC CCM Clock Gating Register (CCM_CCGR143_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4900 CCM Clock Gating Register (CCM_CCGR144) 32 R/W 0000_0002h 5.1.7.6/452
3038_4904 CCM Clock Gating Register (CCM_CCGR144_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4908 CCM Clock Gating Register (CCM_CCGR144_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_490C CCM Clock Gating Register (CCM_CCGR144_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4910 CCM Clock Gating Register (CCM_CCGR145) 32 R/W 0000_0002h 5.1.7.6/452
3038_4914 CCM Clock Gating Register (CCM_CCGR145_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4918 CCM Clock Gating Register (CCM_CCGR145_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_491C CCM Clock Gating Register (CCM_CCGR145_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4920 CCM Clock Gating Register (CCM_CCGR146) 32 R/W 0000_0002h 5.1.7.6/452
3038_4924 CCM Clock Gating Register (CCM_CCGR146_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 307
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4928 CCM Clock Gating Register (CCM_CCGR146_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_492C CCM Clock Gating Register (CCM_CCGR146_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4930 CCM Clock Gating Register (CCM_CCGR147) 32 R/W 0000_0002h 5.1.7.6/452
3038_4934 CCM Clock Gating Register (CCM_CCGR147_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4938 CCM Clock Gating Register (CCM_CCGR147_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_493C CCM Clock Gating Register (CCM_CCGR147_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4940 CCM Clock Gating Register (CCM_CCGR148) 32 R/W 0000_0002h 5.1.7.6/452
3038_4944 CCM Clock Gating Register (CCM_CCGR148_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4948 CCM Clock Gating Register (CCM_CCGR148_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_494C CCM Clock Gating Register (CCM_CCGR148_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4950 CCM Clock Gating Register (CCM_CCGR149) 32 R/W 0000_0002h 5.1.7.6/452
3038_4954 CCM Clock Gating Register (CCM_CCGR149_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4958 CCM Clock Gating Register (CCM_CCGR149_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_495C CCM Clock Gating Register (CCM_CCGR149_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4960 CCM Clock Gating Register (CCM_CCGR150) 32 R/W 0000_0002h 5.1.7.6/452
3038_4964 CCM Clock Gating Register (CCM_CCGR150_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4968 CCM Clock Gating Register (CCM_CCGR150_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_496C CCM Clock Gating Register (CCM_CCGR150_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4970 CCM Clock Gating Register (CCM_CCGR151) 32 R/W 0000_0002h 5.1.7.6/452
3038_4974 CCM Clock Gating Register (CCM_CCGR151_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4978 CCM Clock Gating Register (CCM_CCGR151_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_497C CCM Clock Gating Register (CCM_CCGR151_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4980 CCM Clock Gating Register (CCM_CCGR152) 32 R/W 0000_0002h 5.1.7.6/452
3038_4984 CCM Clock Gating Register (CCM_CCGR152_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4988 CCM Clock Gating Register (CCM_CCGR152_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_498C CCM Clock Gating Register (CCM_CCGR152_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4990 CCM Clock Gating Register (CCM_CCGR153) 32 R/W 0000_0002h 5.1.7.6/452
3038_4994 CCM Clock Gating Register (CCM_CCGR153_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4998 CCM Clock Gating Register (CCM_CCGR153_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_499C CCM Clock Gating Register (CCM_CCGR153_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_49A0 CCM Clock Gating Register (CCM_CCGR154) 32 R/W 0000_0002h 5.1.7.6/452
3038_49A4 CCM Clock Gating Register (CCM_CCGR154_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49A8 CCM Clock Gating Register (CCM_CCGR154_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49AC CCM Clock Gating Register (CCM_CCGR154_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_49B0 CCM Clock Gating Register (CCM_CCGR155) 32 R/W 0000_0002h 5.1.7.6/452
3038_49B4 CCM Clock Gating Register (CCM_CCGR155_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49B8 CCM Clock Gating Register (CCM_CCGR155_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49BC CCM Clock Gating Register (CCM_CCGR155_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
308 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_49C0 CCM Clock Gating Register (CCM_CCGR156) 32 R/W 0000_0002h 5.1.7.6/452
3038_49C4 CCM Clock Gating Register (CCM_CCGR156_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49C8 CCM Clock Gating Register (CCM_CCGR156_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49CC CCM Clock Gating Register (CCM_CCGR156_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_49D0 CCM Clock Gating Register (CCM_CCGR157) 32 R/W 0000_0002h 5.1.7.6/452
3038_49D4 CCM Clock Gating Register (CCM_CCGR157_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49D8 CCM Clock Gating Register (CCM_CCGR157_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49DC CCM Clock Gating Register (CCM_CCGR157_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_49E0 CCM Clock Gating Register (CCM_CCGR158) 32 R/W 0000_0002h 5.1.7.6/452
3038_49E4 CCM Clock Gating Register (CCM_CCGR158_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49E8 CCM Clock Gating Register (CCM_CCGR158_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49EC CCM Clock Gating Register (CCM_CCGR158_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_49F0 CCM Clock Gating Register (CCM_CCGR159) 32 R/W 0000_0002h 5.1.7.6/452
3038_49F4 CCM Clock Gating Register (CCM_CCGR159_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_49F8 CCM Clock Gating Register (CCM_CCGR159_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_49FC CCM Clock Gating Register (CCM_CCGR159_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A00 CCM Clock Gating Register (CCM_CCGR160) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A04 CCM Clock Gating Register (CCM_CCGR160_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A08 CCM Clock Gating Register (CCM_CCGR160_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A0C CCM Clock Gating Register (CCM_CCGR160_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A10 CCM Clock Gating Register (CCM_CCGR161) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A14 CCM Clock Gating Register (CCM_CCGR161_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A18 CCM Clock Gating Register (CCM_CCGR161_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A1C CCM Clock Gating Register (CCM_CCGR161_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A20 CCM Clock Gating Register (CCM_CCGR162) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A24 CCM Clock Gating Register (CCM_CCGR162_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A28 CCM Clock Gating Register (CCM_CCGR162_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A2C CCM Clock Gating Register (CCM_CCGR162_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A30 CCM Clock Gating Register (CCM_CCGR163) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A34 CCM Clock Gating Register (CCM_CCGR163_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A38 CCM Clock Gating Register (CCM_CCGR163_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A3C CCM Clock Gating Register (CCM_CCGR163_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A40 CCM Clock Gating Register (CCM_CCGR164) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A44 CCM Clock Gating Register (CCM_CCGR164_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A48 CCM Clock Gating Register (CCM_CCGR164_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A4C CCM Clock Gating Register (CCM_CCGR164_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A50 CCM Clock Gating Register (CCM_CCGR165) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A54 CCM Clock Gating Register (CCM_CCGR165_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 309
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4A58 CCM Clock Gating Register (CCM_CCGR165_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A5C CCM Clock Gating Register (CCM_CCGR165_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A60 CCM Clock Gating Register (CCM_CCGR166) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A64 CCM Clock Gating Register (CCM_CCGR166_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A68 CCM Clock Gating Register (CCM_CCGR166_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A6C CCM Clock Gating Register (CCM_CCGR166_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A70 CCM Clock Gating Register (CCM_CCGR167) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A74 CCM Clock Gating Register (CCM_CCGR167_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A78 CCM Clock Gating Register (CCM_CCGR167_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A7C CCM Clock Gating Register (CCM_CCGR167_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A80 CCM Clock Gating Register (CCM_CCGR168) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A84 CCM Clock Gating Register (CCM_CCGR168_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A88 CCM Clock Gating Register (CCM_CCGR168_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A8C CCM Clock Gating Register (CCM_CCGR168_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4A90 CCM Clock Gating Register (CCM_CCGR169) 32 R/W 0000_0002h 5.1.7.6/452
3038_4A94 CCM Clock Gating Register (CCM_CCGR169_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4A98 CCM Clock Gating Register (CCM_CCGR169_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4A9C CCM Clock Gating Register (CCM_CCGR169_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4AA0 CCM Clock Gating Register (CCM_CCGR170) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AA4 CCM Clock Gating Register (CCM_CCGR170_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AA8 CCM Clock Gating Register (CCM_CCGR170_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4AAC CCM Clock Gating Register (CCM_CCGR170_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4AB0 CCM Clock Gating Register (CCM_CCGR171) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AB4 CCM Clock Gating Register (CCM_CCGR171_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AB8 CCM Clock Gating Register (CCM_CCGR171_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4ABC CCM Clock Gating Register (CCM_CCGR171_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4AC0 CCM Clock Gating Register (CCM_CCGR172) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AC4 CCM Clock Gating Register (CCM_CCGR172_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AC8 CCM Clock Gating Register (CCM_CCGR172_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4ACC CCM Clock Gating Register (CCM_CCGR172_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4AD0 CCM Clock Gating Register (CCM_CCGR173) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AD4 CCM Clock Gating Register (CCM_CCGR173_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AD8 CCM Clock Gating Register (CCM_CCGR173_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4ADC CCM Clock Gating Register (CCM_CCGR173_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4AE0 CCM Clock Gating Register (CCM_CCGR174) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AE4 CCM Clock Gating Register (CCM_CCGR174_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AE8 CCM Clock Gating Register (CCM_CCGR174_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4AEC CCM Clock Gating Register (CCM_CCGR174_TOG) 32 R/W 0000_0002h 5.1.7.9/459
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
310 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4AF0 CCM Clock Gating Register (CCM_CCGR175) 32 R/W 0000_0002h 5.1.7.6/452
3038_4AF4 CCM Clock Gating Register (CCM_CCGR175_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4AF8 CCM Clock Gating Register (CCM_CCGR175_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4AFC CCM Clock Gating Register (CCM_CCGR175_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B00 CCM Clock Gating Register (CCM_CCGR176) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B04 CCM Clock Gating Register (CCM_CCGR176_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B08 CCM Clock Gating Register (CCM_CCGR176_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B0C CCM Clock Gating Register (CCM_CCGR176_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B10 CCM Clock Gating Register (CCM_CCGR177) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B14 CCM Clock Gating Register (CCM_CCGR177_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B18 CCM Clock Gating Register (CCM_CCGR177_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B1C CCM Clock Gating Register (CCM_CCGR177_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B20 CCM Clock Gating Register (CCM_CCGR178) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B24 CCM Clock Gating Register (CCM_CCGR178_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B28 CCM Clock Gating Register (CCM_CCGR178_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B2C CCM Clock Gating Register (CCM_CCGR178_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B30 CCM Clock Gating Register (CCM_CCGR179) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B34 CCM Clock Gating Register (CCM_CCGR179_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B38 CCM Clock Gating Register (CCM_CCGR179_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B3C CCM Clock Gating Register (CCM_CCGR179_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B40 CCM Clock Gating Register (CCM_CCGR180) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B44 CCM Clock Gating Register (CCM_CCGR180_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B48 CCM Clock Gating Register (CCM_CCGR180_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B4C CCM Clock Gating Register (CCM_CCGR180_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B50 CCM Clock Gating Register (CCM_CCGR181) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B54 CCM Clock Gating Register (CCM_CCGR181_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B58 CCM Clock Gating Register (CCM_CCGR181_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B5C CCM Clock Gating Register (CCM_CCGR181_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B60 CCM Clock Gating Register (CCM_CCGR182) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B64 CCM Clock Gating Register (CCM_CCGR182_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B68 CCM Clock Gating Register (CCM_CCGR182_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B6C CCM Clock Gating Register (CCM_CCGR182_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B70 CCM Clock Gating Register (CCM_CCGR183) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B74 CCM Clock Gating Register (CCM_CCGR183_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B78 CCM Clock Gating Register (CCM_CCGR183_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B7C CCM Clock Gating Register (CCM_CCGR183_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B80 CCM Clock Gating Register (CCM_CCGR184) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B84 CCM Clock Gating Register (CCM_CCGR184_SET) 32 R/W 0000_0002h 5.1.7.7/455
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 311
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_4B88 CCM Clock Gating Register (CCM_CCGR184_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B8C CCM Clock Gating Register (CCM_CCGR184_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4B90 CCM Clock Gating Register (CCM_CCGR185) 32 R/W 0000_0002h 5.1.7.6/452
3038_4B94 CCM Clock Gating Register (CCM_CCGR185_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4B98 CCM Clock Gating Register (CCM_CCGR185_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4B9C CCM Clock Gating Register (CCM_CCGR185_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BA0 CCM Clock Gating Register (CCM_CCGR186) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BA4 CCM Clock Gating Register (CCM_CCGR186_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BA8 CCM Clock Gating Register (CCM_CCGR186_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BAC CCM Clock Gating Register (CCM_CCGR186_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BB0 CCM Clock Gating Register (CCM_CCGR187) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BB4 CCM Clock Gating Register (CCM_CCGR187_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BB8 CCM Clock Gating Register (CCM_CCGR187_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BBC CCM Clock Gating Register (CCM_CCGR187_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BC0 CCM Clock Gating Register (CCM_CCGR188) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BC4 CCM Clock Gating Register (CCM_CCGR188_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BC8 CCM Clock Gating Register (CCM_CCGR188_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BCC CCM Clock Gating Register (CCM_CCGR188_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BD0 CCM Clock Gating Register (CCM_CCGR189) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BD4 CCM Clock Gating Register (CCM_CCGR189_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BD8 CCM Clock Gating Register (CCM_CCGR189_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BDC CCM Clock Gating Register (CCM_CCGR189_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BE0 CCM Clock Gating Register (CCM_CCGR190) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BE4 CCM Clock Gating Register (CCM_CCGR190_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BE8 CCM Clock Gating Register (CCM_CCGR190_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BEC CCM Clock Gating Register (CCM_CCGR190_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_4BF0 CCM Clock Gating Register (CCM_CCGR191) 32 R/W 0000_0002h 5.1.7.6/452
3038_4BF4 CCM Clock Gating Register (CCM_CCGR191_SET) 32 R/W 0000_0002h 5.1.7.7/455
3038_4BF8 CCM Clock Gating Register (CCM_CCGR191_CLR) 32 R/W 0000_0002h 5.1.7.8/457
3038_4BFC CCM Clock Gating Register (CCM_CCGR191_TOG) 32 R/W 0000_0002h 5.1.7.9/459
3038_8000 Target Register (CCM_TARGET_ROOT0) 32 R/W 1000_0000h 5.1.7.10/461
3038_8004 Target Register (CCM_TARGET_ROOT0_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8008 Target Register (CCM_TARGET_ROOT0_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_800C Target Register (CCM_TARGET_ROOT0_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8010 Miscellaneous Register (CCM_MISC0) 32 R/W 0000_0000h 5.1.7.14/469
3038_8014 Miscellaneous Register (CCM_MISC_ROOT0_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8018 Miscellaneous Register (CCM_MISC_ROOT0_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_801C Miscellaneous Register (CCM_MISC_ROOT0_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
312 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8020 Post Divider Register (CCM_POST0) 32 R/W 0000_0000h 5.1.7.18/473
3038_8024 Post Divider Register (CCM_POST_ROOT0_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8028 Post Divider Register (CCM_POST_ROOT0_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_802C Post Divider Register (CCM_POST_ROOT0_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8030 Pre Divider Register (CCM_PRE0) 32 R/W 1000_0000h 5.1.7.22/485
3038_8034 Pre Divider Register (CCM_PRE_ROOT0_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8038 Pre Divider Register (CCM_PRE_ROOT0_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_803C Pre Divider Register (CCM_PRE_ROOT0_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8070 Access Control Register (CCM_ACCESS_CTRL0) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8074 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT0_SET)
Access Control Register
3038_8078 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT0_CLR)
Access Control Register
3038_807C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT0_TOG)
3038_8080 Target Register (CCM_TARGET_ROOT1) 32 R/W 1000_0000h 5.1.7.10/461
3038_8084 Target Register (CCM_TARGET_ROOT1_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8088 Target Register (CCM_TARGET_ROOT1_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_808C Target Register (CCM_TARGET_ROOT1_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8090 Miscellaneous Register (CCM_MISC1) 32 R/W 0000_0000h 5.1.7.14/469
3038_8094 Miscellaneous Register (CCM_MISC_ROOT1_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8098 Miscellaneous Register (CCM_MISC_ROOT1_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_809C Miscellaneous Register (CCM_MISC_ROOT1_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_80A0 Post Divider Register (CCM_POST1) 32 R/W 0000_0000h 5.1.7.18/473
3038_80A4 Post Divider Register (CCM_POST_ROOT1_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_80A8 Post Divider Register (CCM_POST_ROOT1_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_80AC Post Divider Register (CCM_POST_ROOT1_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_80B0 Pre Divider Register (CCM_PRE1) 32 R/W 1000_0000h 5.1.7.22/485
3038_80B4 Pre Divider Register (CCM_PRE_ROOT1_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_80B8 Pre Divider Register (CCM_PRE_ROOT1_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_80BC Pre Divider Register (CCM_PRE_ROOT1_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_80F0 Access Control Register (CCM_ACCESS_CTRL1) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_80F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT1_SET)
Access Control Register
3038_80F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT1_CLR)
Access Control Register
3038_80FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT1_TOG)
3038_8100 Target Register (CCM_TARGET_ROOT2) 32 R/W 1000_0000h 5.1.7.10/461
3038_8104 Target Register (CCM_TARGET_ROOT2_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 313
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8108 Target Register (CCM_TARGET_ROOT2_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_810C Target Register (CCM_TARGET_ROOT2_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8110 Miscellaneous Register (CCM_MISC2) 32 R/W 0000_0000h 5.1.7.14/469
3038_8114 Miscellaneous Register (CCM_MISC_ROOT2_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8118 Miscellaneous Register (CCM_MISC_ROOT2_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_811C Miscellaneous Register (CCM_MISC_ROOT2_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8120 Post Divider Register (CCM_POST2) 32 R/W 0000_0000h 5.1.7.18/473
3038_8124 Post Divider Register (CCM_POST_ROOT2_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8128 Post Divider Register (CCM_POST_ROOT2_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_812C Post Divider Register (CCM_POST_ROOT2_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8130 Pre Divider Register (CCM_PRE2) 32 R/W 1000_0000h 5.1.7.22/485
3038_8134 Pre Divider Register (CCM_PRE_ROOT2_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8138 Pre Divider Register (CCM_PRE_ROOT2_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_813C Pre Divider Register (CCM_PRE_ROOT2_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8170 Access Control Register (CCM_ACCESS_CTRL2) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8174 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT2_SET)
Access Control Register
3038_8178 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT2_CLR)
Access Control Register
3038_817C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT2_TOG)
3038_8180 Target Register (CCM_TARGET_ROOT3) 32 R/W 1000_0000h 5.1.7.10/461
3038_8184 Target Register (CCM_TARGET_ROOT3_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8188 Target Register (CCM_TARGET_ROOT3_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_818C Target Register (CCM_TARGET_ROOT3_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8190 Miscellaneous Register (CCM_MISC3) 32 R/W 0000_0000h 5.1.7.14/469
3038_8194 Miscellaneous Register (CCM_MISC_ROOT3_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8198 Miscellaneous Register (CCM_MISC_ROOT3_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_819C Miscellaneous Register (CCM_MISC_ROOT3_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_81A0 Post Divider Register (CCM_POST3) 32 R/W 0000_0000h 5.1.7.18/473
3038_81A4 Post Divider Register (CCM_POST_ROOT3_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_81A8 Post Divider Register (CCM_POST_ROOT3_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_81AC Post Divider Register (CCM_POST_ROOT3_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_81B0 Pre Divider Register (CCM_PRE3) 32 R/W 1000_0000h 5.1.7.22/485
3038_81B4 Pre Divider Register (CCM_PRE_ROOT3_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_81B8 Pre Divider Register (CCM_PRE_ROOT3_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_81BC Pre Divider Register (CCM_PRE_ROOT3_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_81F0 Access Control Register (CCM_ACCESS_CTRL3) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
314 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_81F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT3_SET)
Access Control Register
3038_81F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT3_CLR)
Access Control Register
3038_81FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT3_TOG)
3038_8200 Target Register (CCM_TARGET_ROOT4) 32 R/W 1000_0000h 5.1.7.10/461
3038_8204 Target Register (CCM_TARGET_ROOT4_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8208 Target Register (CCM_TARGET_ROOT4_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_820C Target Register (CCM_TARGET_ROOT4_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8210 Miscellaneous Register (CCM_MISC4) 32 R/W 0000_0000h 5.1.7.14/469
3038_8214 Miscellaneous Register (CCM_MISC_ROOT4_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8218 Miscellaneous Register (CCM_MISC_ROOT4_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_821C Miscellaneous Register (CCM_MISC_ROOT4_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8220 Post Divider Register (CCM_POST4) 32 R/W 0000_0000h 5.1.7.18/473
3038_8224 Post Divider Register (CCM_POST_ROOT4_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8228 Post Divider Register (CCM_POST_ROOT4_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_822C Post Divider Register (CCM_POST_ROOT4_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8230 Pre Divider Register (CCM_PRE4) 32 R/W 1000_0000h 5.1.7.22/485
3038_8234 Pre Divider Register (CCM_PRE_ROOT4_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8238 Pre Divider Register (CCM_PRE_ROOT4_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_823C Pre Divider Register (CCM_PRE_ROOT4_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8270 Access Control Register (CCM_ACCESS_CTRL4) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8274 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT4_SET)
Access Control Register
3038_8278 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT4_CLR)
Access Control Register
3038_827C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT4_TOG)
3038_8280 Target Register (CCM_TARGET_ROOT5) 32 R/W 1000_0000h 5.1.7.10/461
3038_8284 Target Register (CCM_TARGET_ROOT5_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8288 Target Register (CCM_TARGET_ROOT5_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_828C Target Register (CCM_TARGET_ROOT5_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8290 Miscellaneous Register (CCM_MISC5) 32 R/W 0000_0000h 5.1.7.14/469
3038_8294 Miscellaneous Register (CCM_MISC_ROOT5_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8298 Miscellaneous Register (CCM_MISC_ROOT5_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_829C Miscellaneous Register (CCM_MISC_ROOT5_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_82A0 Post Divider Register (CCM_POST5) 32 R/W 0000_0000h 5.1.7.18/473
3038_82A4 Post Divider Register (CCM_POST_ROOT5_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_82A8 Post Divider Register (CCM_POST_ROOT5_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 315
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_82AC Post Divider Register (CCM_POST_ROOT5_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_82B0 Pre Divider Register (CCM_PRE5) 32 R/W 1000_0000h 5.1.7.22/485
3038_82B4 Pre Divider Register (CCM_PRE_ROOT5_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_82B8 Pre Divider Register (CCM_PRE_ROOT5_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_82BC Pre Divider Register (CCM_PRE_ROOT5_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_82F0 Access Control Register (CCM_ACCESS_CTRL5) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_82F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT5_SET)
Access Control Register
3038_82F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT5_CLR)
Access Control Register
3038_82FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT5_TOG)
3038_8300 Target Register (CCM_TARGET_ROOT6) 32 R/W 1000_0000h 5.1.7.10/461
3038_8304 Target Register (CCM_TARGET_ROOT6_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8308 Target Register (CCM_TARGET_ROOT6_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_830C Target Register (CCM_TARGET_ROOT6_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8310 Miscellaneous Register (CCM_MISC6) 32 R/W 0000_0000h 5.1.7.14/469
3038_8314 Miscellaneous Register (CCM_MISC_ROOT6_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8318 Miscellaneous Register (CCM_MISC_ROOT6_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_831C Miscellaneous Register (CCM_MISC_ROOT6_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8320 Post Divider Register (CCM_POST6) 32 R/W 0000_0000h 5.1.7.18/473
3038_8324 Post Divider Register (CCM_POST_ROOT6_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8328 Post Divider Register (CCM_POST_ROOT6_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_832C Post Divider Register (CCM_POST_ROOT6_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8330 Pre Divider Register (CCM_PRE6) 32 R/W 1000_0000h 5.1.7.22/485
3038_8334 Pre Divider Register (CCM_PRE_ROOT6_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8338 Pre Divider Register (CCM_PRE_ROOT6_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_833C Pre Divider Register (CCM_PRE_ROOT6_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8370 Access Control Register (CCM_ACCESS_CTRL6) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8374 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT6_SET)
Access Control Register
3038_8378 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT6_CLR)
Access Control Register
3038_837C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT6_TOG)
3038_8380 Target Register (CCM_TARGET_ROOT7) 32 R/W 1000_0000h 5.1.7.10/461
3038_8384 Target Register (CCM_TARGET_ROOT7_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8388 Target Register (CCM_TARGET_ROOT7_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_838C Target Register (CCM_TARGET_ROOT7_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8390 Miscellaneous Register (CCM_MISC7) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
316 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8394 Miscellaneous Register (CCM_MISC_ROOT7_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8398 Miscellaneous Register (CCM_MISC_ROOT7_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_839C Miscellaneous Register (CCM_MISC_ROOT7_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_83A0 Post Divider Register (CCM_POST7) 32 R/W 0000_0000h 5.1.7.18/473
3038_83A4 Post Divider Register (CCM_POST_ROOT7_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_83A8 Post Divider Register (CCM_POST_ROOT7_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_83AC Post Divider Register (CCM_POST_ROOT7_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_83B0 Pre Divider Register (CCM_PRE7) 32 R/W 1000_0000h 5.1.7.22/485
3038_83B4 Pre Divider Register (CCM_PRE_ROOT7_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_83B8 Pre Divider Register (CCM_PRE_ROOT7_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_83BC Pre Divider Register (CCM_PRE_ROOT7_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_83F0 Access Control Register (CCM_ACCESS_CTRL7) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_83F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT7_SET)
Access Control Register
3038_83F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT7_CLR)
Access Control Register
3038_83FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT7_TOG)
3038_8400 Target Register (CCM_TARGET_ROOT8) 32 R/W 1000_0000h 5.1.7.10/461
3038_8404 Target Register (CCM_TARGET_ROOT8_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8408 Target Register (CCM_TARGET_ROOT8_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_840C Target Register (CCM_TARGET_ROOT8_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8410 Miscellaneous Register (CCM_MISC8) 32 R/W 0000_0000h 5.1.7.14/469
3038_8414 Miscellaneous Register (CCM_MISC_ROOT8_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8418 Miscellaneous Register (CCM_MISC_ROOT8_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_841C Miscellaneous Register (CCM_MISC_ROOT8_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8420 Post Divider Register (CCM_POST8) 32 R/W 0000_0000h 5.1.7.18/473
3038_8424 Post Divider Register (CCM_POST_ROOT8_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8428 Post Divider Register (CCM_POST_ROOT8_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_842C Post Divider Register (CCM_POST_ROOT8_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8430 Pre Divider Register (CCM_PRE8) 32 R/W 1000_0000h 5.1.7.22/485
3038_8434 Pre Divider Register (CCM_PRE_ROOT8_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8438 Pre Divider Register (CCM_PRE_ROOT8_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_843C Pre Divider Register (CCM_PRE_ROOT8_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8470 Access Control Register (CCM_ACCESS_CTRL8) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8474 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT8_SET)
Access Control Register
3038_8478 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT8_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 317
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_847C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT8_TOG)
3038_8480 Target Register (CCM_TARGET_ROOT9) 32 R/W 1000_0000h 5.1.7.10/461
3038_8484 Target Register (CCM_TARGET_ROOT9_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8488 Target Register (CCM_TARGET_ROOT9_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_848C Target Register (CCM_TARGET_ROOT9_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8490 Miscellaneous Register (CCM_MISC9) 32 R/W 0000_0000h 5.1.7.14/469
3038_8494 Miscellaneous Register (CCM_MISC_ROOT9_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8498 Miscellaneous Register (CCM_MISC_ROOT9_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_849C Miscellaneous Register (CCM_MISC_ROOT9_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_84A0 Post Divider Register (CCM_POST9) 32 R/W 0000_0000h 5.1.7.18/473
3038_84A4 Post Divider Register (CCM_POST_ROOT9_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_84A8 Post Divider Register (CCM_POST_ROOT9_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_84AC Post Divider Register (CCM_POST_ROOT9_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_84B0 Pre Divider Register (CCM_PRE9) 32 R/W 1000_0000h 5.1.7.22/485
3038_84B4 Pre Divider Register (CCM_PRE_ROOT9_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_84B8 Pre Divider Register (CCM_PRE_ROOT9_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_84BC Pre Divider Register (CCM_PRE_ROOT9_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_84F0 Access Control Register (CCM_ACCESS_CTRL9) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_84F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT9_SET)
Access Control Register
3038_84F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT9_CLR)
Access Control Register
3038_84FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT9_TOG)
3038_8500 Target Register (CCM_TARGET_ROOT10) 32 R/W 1000_0000h 5.1.7.10/461
3038_8504 Target Register (CCM_TARGET_ROOT10_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8508 Target Register (CCM_TARGET_ROOT10_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_850C Target Register (CCM_TARGET_ROOT10_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8510 Miscellaneous Register (CCM_MISC10) 32 R/W 0000_0000h 5.1.7.14/469
3038_8514 Miscellaneous Register (CCM_MISC_ROOT10_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8518 Miscellaneous Register (CCM_MISC_ROOT10_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_851C Miscellaneous Register (CCM_MISC_ROOT10_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8520 Post Divider Register (CCM_POST10) 32 R/W 0000_0000h 5.1.7.18/473
3038_8524 Post Divider Register (CCM_POST_ROOT10_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8528 Post Divider Register (CCM_POST_ROOT10_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_852C Post Divider Register (CCM_POST_ROOT10_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8530 Pre Divider Register (CCM_PRE10) 32 R/W 1000_0000h 5.1.7.22/485
3038_8534 Pre Divider Register (CCM_PRE_ROOT10_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
318 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8538 Pre Divider Register (CCM_PRE_ROOT10_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_853C Pre Divider Register (CCM_PRE_ROOT10_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8570 Access Control Register (CCM_ACCESS_CTRL10) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8574 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT10_SET)
Access Control Register
3038_8578 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT10_CLR)
Access Control Register
3038_857C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT10_TOG)
3038_8580 Target Register (CCM_TARGET_ROOT11) 32 R/W 1000_0000h 5.1.7.10/461
3038_8584 Target Register (CCM_TARGET_ROOT11_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8588 Target Register (CCM_TARGET_ROOT11_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_858C Target Register (CCM_TARGET_ROOT11_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8590 Miscellaneous Register (CCM_MISC11) 32 R/W 0000_0000h 5.1.7.14/469
3038_8594 Miscellaneous Register (CCM_MISC_ROOT11_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8598 Miscellaneous Register (CCM_MISC_ROOT11_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_859C Miscellaneous Register (CCM_MISC_ROOT11_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_85A0 Post Divider Register (CCM_POST11) 32 R/W 0000_0000h 5.1.7.18/473
3038_85A4 Post Divider Register (CCM_POST_ROOT11_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_85A8 Post Divider Register (CCM_POST_ROOT11_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_85AC Post Divider Register (CCM_POST_ROOT11_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_85B0 Pre Divider Register (CCM_PRE11) 32 R/W 1000_0000h 5.1.7.22/485
3038_85B4 Pre Divider Register (CCM_PRE_ROOT11_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_85B8 Pre Divider Register (CCM_PRE_ROOT11_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_85BC Pre Divider Register (CCM_PRE_ROOT11_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_85F0 Access Control Register (CCM_ACCESS_CTRL11) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_85F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT11_SET)
Access Control Register
3038_85F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT11_CLR)
Access Control Register
3038_85FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT11_TOG)
3038_8600 Target Register (CCM_TARGET_ROOT12) 32 R/W 1000_0000h 5.1.7.10/461
3038_8604 Target Register (CCM_TARGET_ROOT12_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8608 Target Register (CCM_TARGET_ROOT12_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_860C Target Register (CCM_TARGET_ROOT12_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8610 Miscellaneous Register (CCM_MISC12) 32 R/W 0000_0000h 5.1.7.14/469
3038_8614 Miscellaneous Register (CCM_MISC_ROOT12_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8618 Miscellaneous Register (CCM_MISC_ROOT12_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_861C Miscellaneous Register (CCM_MISC_ROOT12_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 319
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8620 Post Divider Register (CCM_POST12) 32 R/W 0000_0000h 5.1.7.18/473
3038_8624 Post Divider Register (CCM_POST_ROOT12_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8628 Post Divider Register (CCM_POST_ROOT12_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_862C Post Divider Register (CCM_POST_ROOT12_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8630 Pre Divider Register (CCM_PRE12) 32 R/W 1000_0000h 5.1.7.22/485
3038_8634 Pre Divider Register (CCM_PRE_ROOT12_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8638 Pre Divider Register (CCM_PRE_ROOT12_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_863C Pre Divider Register (CCM_PRE_ROOT12_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8670 Access Control Register (CCM_ACCESS_CTRL12) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8674 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT12_SET)
Access Control Register
3038_8678 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT12_CLR)
Access Control Register
3038_867C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT12_TOG)
3038_8680 Target Register (CCM_TARGET_ROOT13) 32 R/W 1000_0000h 5.1.7.10/461
3038_8684 Target Register (CCM_TARGET_ROOT13_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8688 Target Register (CCM_TARGET_ROOT13_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_868C Target Register (CCM_TARGET_ROOT13_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8690 Miscellaneous Register (CCM_MISC13) 32 R/W 0000_0000h 5.1.7.14/469
3038_8694 Miscellaneous Register (CCM_MISC_ROOT13_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8698 Miscellaneous Register (CCM_MISC_ROOT13_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_869C Miscellaneous Register (CCM_MISC_ROOT13_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_86A0 Post Divider Register (CCM_POST13) 32 R/W 0000_0000h 5.1.7.18/473
3038_86A4 Post Divider Register (CCM_POST_ROOT13_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_86A8 Post Divider Register (CCM_POST_ROOT13_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_86AC Post Divider Register (CCM_POST_ROOT13_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_86B0 Pre Divider Register (CCM_PRE13) 32 R/W 1000_0000h 5.1.7.22/485
3038_86B4 Pre Divider Register (CCM_PRE_ROOT13_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_86B8 Pre Divider Register (CCM_PRE_ROOT13_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_86BC Pre Divider Register (CCM_PRE_ROOT13_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_86F0 Access Control Register (CCM_ACCESS_CTRL13) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_86F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT13_SET)
Access Control Register
3038_86F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT13_CLR)
Access Control Register
3038_86FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT13_TOG)
3038_8700 Target Register (CCM_TARGET_ROOT14) 32 R/W 1000_0000h 5.1.7.10/461
3038_8704 Target Register (CCM_TARGET_ROOT14_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
320 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8708 Target Register (CCM_TARGET_ROOT14_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_870C Target Register (CCM_TARGET_ROOT14_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8710 Miscellaneous Register (CCM_MISC14) 32 R/W 0000_0000h 5.1.7.14/469
3038_8714 Miscellaneous Register (CCM_MISC_ROOT14_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8718 Miscellaneous Register (CCM_MISC_ROOT14_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_871C Miscellaneous Register (CCM_MISC_ROOT14_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8720 Post Divider Register (CCM_POST14) 32 R/W 0000_0000h 5.1.7.18/473
3038_8724 Post Divider Register (CCM_POST_ROOT14_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8728 Post Divider Register (CCM_POST_ROOT14_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_872C Post Divider Register (CCM_POST_ROOT14_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8730 Pre Divider Register (CCM_PRE14) 32 R/W 1000_0000h 5.1.7.22/485
3038_8734 Pre Divider Register (CCM_PRE_ROOT14_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8738 Pre Divider Register (CCM_PRE_ROOT14_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_873C Pre Divider Register (CCM_PRE_ROOT14_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8770 Access Control Register (CCM_ACCESS_CTRL14) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8774 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT14_SET)
Access Control Register
3038_8778 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT14_CLR)
Access Control Register
3038_877C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT14_TOG)
3038_8780 Target Register (CCM_TARGET_ROOT15) 32 R/W 1000_0000h 5.1.7.10/461
3038_8784 Target Register (CCM_TARGET_ROOT15_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8788 Target Register (CCM_TARGET_ROOT15_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_878C Target Register (CCM_TARGET_ROOT15_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8790 Miscellaneous Register (CCM_MISC15) 32 R/W 0000_0000h 5.1.7.14/469
3038_8794 Miscellaneous Register (CCM_MISC_ROOT15_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8798 Miscellaneous Register (CCM_MISC_ROOT15_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_879C Miscellaneous Register (CCM_MISC_ROOT15_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_87A0 Post Divider Register (CCM_POST15) 32 R/W 0000_0000h 5.1.7.18/473
3038_87A4 Post Divider Register (CCM_POST_ROOT15_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_87A8 Post Divider Register (CCM_POST_ROOT15_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_87AC Post Divider Register (CCM_POST_ROOT15_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_87B0 Pre Divider Register (CCM_PRE15) 32 R/W 1000_0000h 5.1.7.22/485
3038_87B4 Pre Divider Register (CCM_PRE_ROOT15_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_87B8 Pre Divider Register (CCM_PRE_ROOT15_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_87BC Pre Divider Register (CCM_PRE_ROOT15_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_87F0 Access Control Register (CCM_ACCESS_CTRL15) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 321
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_87F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT15_SET)
Access Control Register
3038_87F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT15_CLR)
Access Control Register
3038_87FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT15_TOG)
3038_8800 Target Register (CCM_TARGET_ROOT16) 32 R/W 1000_0000h 5.1.7.10/461
3038_8804 Target Register (CCM_TARGET_ROOT16_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8808 Target Register (CCM_TARGET_ROOT16_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_880C Target Register (CCM_TARGET_ROOT16_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8810 Miscellaneous Register (CCM_MISC16) 32 R/W 0000_0000h 5.1.7.14/469
3038_8814 Miscellaneous Register (CCM_MISC_ROOT16_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8818 Miscellaneous Register (CCM_MISC_ROOT16_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_881C Miscellaneous Register (CCM_MISC_ROOT16_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8820 Post Divider Register (CCM_POST16) 32 R/W 0000_0000h 5.1.7.18/473
3038_8824 Post Divider Register (CCM_POST_ROOT16_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8828 Post Divider Register (CCM_POST_ROOT16_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_882C Post Divider Register (CCM_POST_ROOT16_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8830 Pre Divider Register (CCM_PRE16) 32 R/W 1000_0000h 5.1.7.22/485
3038_8834 Pre Divider Register (CCM_PRE_ROOT16_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8838 Pre Divider Register (CCM_PRE_ROOT16_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_883C Pre Divider Register (CCM_PRE_ROOT16_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8870 Access Control Register (CCM_ACCESS_CTRL16) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8874 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT16_SET)
Access Control Register
3038_8878 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT16_CLR)
Access Control Register
3038_887C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT16_TOG)
3038_8880 Target Register (CCM_TARGET_ROOT17) 32 R/W 1000_0000h 5.1.7.10/461
3038_8884 Target Register (CCM_TARGET_ROOT17_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8888 Target Register (CCM_TARGET_ROOT17_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_888C Target Register (CCM_TARGET_ROOT17_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8890 Miscellaneous Register (CCM_MISC17) 32 R/W 0000_0000h 5.1.7.14/469
3038_8894 Miscellaneous Register (CCM_MISC_ROOT17_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8898 Miscellaneous Register (CCM_MISC_ROOT17_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_889C Miscellaneous Register (CCM_MISC_ROOT17_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_88A0 Post Divider Register (CCM_POST17) 32 R/W 0000_0000h 5.1.7.18/473
3038_88A4 Post Divider Register (CCM_POST_ROOT17_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_88A8 Post Divider Register (CCM_POST_ROOT17_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
322 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_88AC Post Divider Register (CCM_POST_ROOT17_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_88B0 Pre Divider Register (CCM_PRE17) 32 R/W 1000_0000h 5.1.7.22/485
3038_88B4 Pre Divider Register (CCM_PRE_ROOT17_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_88B8 Pre Divider Register (CCM_PRE_ROOT17_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_88BC Pre Divider Register (CCM_PRE_ROOT17_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_88F0 Access Control Register (CCM_ACCESS_CTRL17) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_88F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT17_SET)
Access Control Register
3038_88F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT17_CLR)
Access Control Register
3038_88FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT17_TOG)
3038_8900 Target Register (CCM_TARGET_ROOT18) 32 R/W 1000_0000h 5.1.7.10/461
3038_8904 Target Register (CCM_TARGET_ROOT18_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8908 Target Register (CCM_TARGET_ROOT18_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_890C Target Register (CCM_TARGET_ROOT18_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8910 Miscellaneous Register (CCM_MISC18) 32 R/W 0000_0000h 5.1.7.14/469
3038_8914 Miscellaneous Register (CCM_MISC_ROOT18_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8918 Miscellaneous Register (CCM_MISC_ROOT18_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_891C Miscellaneous Register (CCM_MISC_ROOT18_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8920 Post Divider Register (CCM_POST18) 32 R/W 0000_0000h 5.1.7.18/473
3038_8924 Post Divider Register (CCM_POST_ROOT18_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8928 Post Divider Register (CCM_POST_ROOT18_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_892C Post Divider Register (CCM_POST_ROOT18_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8930 Pre Divider Register (CCM_PRE18) 32 R/W 1000_0000h 5.1.7.22/485
3038_8934 Pre Divider Register (CCM_PRE_ROOT18_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8938 Pre Divider Register (CCM_PRE_ROOT18_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_893C Pre Divider Register (CCM_PRE_ROOT18_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8970 Access Control Register (CCM_ACCESS_CTRL18) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8974 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT18_SET)
Access Control Register
3038_8978 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT18_CLR)
Access Control Register
3038_897C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT18_TOG)
3038_8980 Target Register (CCM_TARGET_ROOT19) 32 R/W 1000_0000h 5.1.7.10/461
3038_8984 Target Register (CCM_TARGET_ROOT19_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8988 Target Register (CCM_TARGET_ROOT19_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_898C Target Register (CCM_TARGET_ROOT19_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8990 Miscellaneous Register (CCM_MISC19) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 323
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8994 Miscellaneous Register (CCM_MISC_ROOT19_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8998 Miscellaneous Register (CCM_MISC_ROOT19_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_899C Miscellaneous Register (CCM_MISC_ROOT19_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_89A0 Post Divider Register (CCM_POST19) 32 R/W 0000_0000h 5.1.7.18/473
3038_89A4 Post Divider Register (CCM_POST_ROOT19_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_89A8 Post Divider Register (CCM_POST_ROOT19_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_89AC Post Divider Register (CCM_POST_ROOT19_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_89B0 Pre Divider Register (CCM_PRE19) 32 R/W 1000_0000h 5.1.7.22/485
3038_89B4 Pre Divider Register (CCM_PRE_ROOT19_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_89B8 Pre Divider Register (CCM_PRE_ROOT19_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_89BC Pre Divider Register (CCM_PRE_ROOT19_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_89F0 Access Control Register (CCM_ACCESS_CTRL19) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_89F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT19_SET)
Access Control Register
3038_89F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT19_CLR)
Access Control Register
3038_89FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT19_TOG)
3038_8A00 Target Register (CCM_TARGET_ROOT20) 32 R/W 1000_0000h 5.1.7.10/461
3038_8A04 Target Register (CCM_TARGET_ROOT20_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8A08 Target Register (CCM_TARGET_ROOT20_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8A0C Target Register (CCM_TARGET_ROOT20_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8A10 Miscellaneous Register (CCM_MISC20) 32 R/W 0000_0000h 5.1.7.14/469
3038_8A14 Miscellaneous Register (CCM_MISC_ROOT20_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8A18 Miscellaneous Register (CCM_MISC_ROOT20_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8A1C Miscellaneous Register (CCM_MISC_ROOT20_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8A20 Post Divider Register (CCM_POST20) 32 R/W 0000_0000h 5.1.7.18/473
3038_8A24 Post Divider Register (CCM_POST_ROOT20_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8A28 Post Divider Register (CCM_POST_ROOT20_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8A2C Post Divider Register (CCM_POST_ROOT20_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8A30 Pre Divider Register (CCM_PRE20) 32 R/W 1000_0000h 5.1.7.22/485
3038_8A34 Pre Divider Register (CCM_PRE_ROOT20_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8A38 Pre Divider Register (CCM_PRE_ROOT20_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8A3C Pre Divider Register (CCM_PRE_ROOT20_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8A70 Access Control Register (CCM_ACCESS_CTRL20) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8A74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT20_SET)
Access Control Register
3038_8A78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT20_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
324 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_8A7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT20_TOG)
3038_8A80 Target Register (CCM_TARGET_ROOT21) 32 R/W 1000_0000h 5.1.7.10/461
3038_8A84 Target Register (CCM_TARGET_ROOT21_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8A88 Target Register (CCM_TARGET_ROOT21_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8A8C Target Register (CCM_TARGET_ROOT21_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8A90 Miscellaneous Register (CCM_MISC21) 32 R/W 0000_0000h 5.1.7.14/469
3038_8A94 Miscellaneous Register (CCM_MISC_ROOT21_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8A98 Miscellaneous Register (CCM_MISC_ROOT21_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8A9C Miscellaneous Register (CCM_MISC_ROOT21_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8AA0 Post Divider Register (CCM_POST21) 32 R/W 0000_0000h 5.1.7.18/473
3038_8AA4 Post Divider Register (CCM_POST_ROOT21_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8AA8 Post Divider Register (CCM_POST_ROOT21_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8AAC Post Divider Register (CCM_POST_ROOT21_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8AB0 Pre Divider Register (CCM_PRE21) 32 R/W 1000_0000h 5.1.7.22/485
3038_8AB4 Pre Divider Register (CCM_PRE_ROOT21_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8AB8 Pre Divider Register (CCM_PRE_ROOT21_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8ABC Pre Divider Register (CCM_PRE_ROOT21_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8AF0 Access Control Register (CCM_ACCESS_CTRL21) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8AF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT21_SET)
Access Control Register
3038_8AF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT21_CLR)
Access Control Register
3038_8AFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT21_TOG)
3038_8B00 Target Register (CCM_TARGET_ROOT22) 32 R/W 1000_0000h 5.1.7.10/461
3038_8B04 Target Register (CCM_TARGET_ROOT22_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8B08 Target Register (CCM_TARGET_ROOT22_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8B0C Target Register (CCM_TARGET_ROOT22_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8B10 Miscellaneous Register (CCM_MISC22) 32 R/W 0000_0000h 5.1.7.14/469
3038_8B14 Miscellaneous Register (CCM_MISC_ROOT22_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8B18 Miscellaneous Register (CCM_MISC_ROOT22_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8B1C Miscellaneous Register (CCM_MISC_ROOT22_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8B20 Post Divider Register (CCM_POST22) 32 R/W 0000_0000h 5.1.7.18/473
3038_8B24 Post Divider Register (CCM_POST_ROOT22_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8B28 Post Divider Register (CCM_POST_ROOT22_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8B2C Post Divider Register (CCM_POST_ROOT22_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8B30 Pre Divider Register (CCM_PRE22) 32 R/W 1000_0000h 5.1.7.22/485
3038_8B34 Pre Divider Register (CCM_PRE_ROOT22_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 325
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8B38 Pre Divider Register (CCM_PRE_ROOT22_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8B3C Pre Divider Register (CCM_PRE_ROOT22_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8B70 Access Control Register (CCM_ACCESS_CTRL22) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8B74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT22_SET)
Access Control Register
3038_8B78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT22_CLR)
Access Control Register
3038_8B7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT22_TOG)
3038_8B80 Target Register (CCM_TARGET_ROOT23) 32 R/W 1000_0000h 5.1.7.10/461
3038_8B84 Target Register (CCM_TARGET_ROOT23_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8B88 Target Register (CCM_TARGET_ROOT23_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8B8C Target Register (CCM_TARGET_ROOT23_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8B90 Miscellaneous Register (CCM_MISC23) 32 R/W 0000_0000h 5.1.7.14/469
3038_8B94 Miscellaneous Register (CCM_MISC_ROOT23_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8B98 Miscellaneous Register (CCM_MISC_ROOT23_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8B9C Miscellaneous Register (CCM_MISC_ROOT23_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8BA0 Post Divider Register (CCM_POST23) 32 R/W 0000_0000h 5.1.7.18/473
3038_8BA4 Post Divider Register (CCM_POST_ROOT23_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8BA8 Post Divider Register (CCM_POST_ROOT23_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8BAC Post Divider Register (CCM_POST_ROOT23_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8BB0 Pre Divider Register (CCM_PRE23) 32 R/W 1000_0000h 5.1.7.22/485
3038_8BB4 Pre Divider Register (CCM_PRE_ROOT23_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8BB8 Pre Divider Register (CCM_PRE_ROOT23_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8BBC Pre Divider Register (CCM_PRE_ROOT23_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8BF0 Access Control Register (CCM_ACCESS_CTRL23) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8BF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT23_SET)
Access Control Register
3038_8BF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT23_CLR)
Access Control Register
3038_8BFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT23_TOG)
3038_8C00 Target Register (CCM_TARGET_ROOT24) 32 R/W 1000_0000h 5.1.7.10/461
3038_8C04 Target Register (CCM_TARGET_ROOT24_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8C08 Target Register (CCM_TARGET_ROOT24_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8C0C Target Register (CCM_TARGET_ROOT24_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8C10 Miscellaneous Register (CCM_MISC24) 32 R/W 0000_0000h 5.1.7.14/469
3038_8C14 Miscellaneous Register (CCM_MISC_ROOT24_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8C18 Miscellaneous Register (CCM_MISC_ROOT24_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8C1C Miscellaneous Register (CCM_MISC_ROOT24_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
326 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8C20 Post Divider Register (CCM_POST24) 32 R/W 0000_0000h 5.1.7.18/473
3038_8C24 Post Divider Register (CCM_POST_ROOT24_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8C28 Post Divider Register (CCM_POST_ROOT24_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8C2C Post Divider Register (CCM_POST_ROOT24_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8C30 Pre Divider Register (CCM_PRE24) 32 R/W 1000_0000h 5.1.7.22/485
3038_8C34 Pre Divider Register (CCM_PRE_ROOT24_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8C38 Pre Divider Register (CCM_PRE_ROOT24_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8C3C Pre Divider Register (CCM_PRE_ROOT24_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8C70 Access Control Register (CCM_ACCESS_CTRL24) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8C74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT24_SET)
Access Control Register
3038_8C78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT24_CLR)
Access Control Register
3038_8C7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT24_TOG)
3038_8C80 Target Register (CCM_TARGET_ROOT25) 32 R/W 1000_0000h 5.1.7.10/461
3038_8C84 Target Register (CCM_TARGET_ROOT25_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8C88 Target Register (CCM_TARGET_ROOT25_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8C8C Target Register (CCM_TARGET_ROOT25_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8C90 Miscellaneous Register (CCM_MISC25) 32 R/W 0000_0000h 5.1.7.14/469
3038_8C94 Miscellaneous Register (CCM_MISC_ROOT25_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8C98 Miscellaneous Register (CCM_MISC_ROOT25_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8C9C Miscellaneous Register (CCM_MISC_ROOT25_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8CA0 Post Divider Register (CCM_POST25) 32 R/W 0000_0000h 5.1.7.18/473
3038_8CA4 Post Divider Register (CCM_POST_ROOT25_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8CA8 Post Divider Register (CCM_POST_ROOT25_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8CAC Post Divider Register (CCM_POST_ROOT25_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8CB0 Pre Divider Register (CCM_PRE25) 32 R/W 1000_0000h 5.1.7.22/485
3038_8CB4 Pre Divider Register (CCM_PRE_ROOT25_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8CB8 Pre Divider Register (CCM_PRE_ROOT25_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8CBC Pre Divider Register (CCM_PRE_ROOT25_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8CF0 Access Control Register (CCM_ACCESS_CTRL25) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8CF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT25_SET)
Access Control Register
3038_8CF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT25_CLR)
Access Control Register
3038_8CFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT25_TOG)
3038_8D00 Target Register (CCM_TARGET_ROOT26) 32 R/W 1000_0000h 5.1.7.10/461
3038_8D04 Target Register (CCM_TARGET_ROOT26_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 327
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8D08 Target Register (CCM_TARGET_ROOT26_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8D0C Target Register (CCM_TARGET_ROOT26_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8D10 Miscellaneous Register (CCM_MISC26) 32 R/W 0000_0000h 5.1.7.14/469
3038_8D14 Miscellaneous Register (CCM_MISC_ROOT26_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8D18 Miscellaneous Register (CCM_MISC_ROOT26_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8D1C Miscellaneous Register (CCM_MISC_ROOT26_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8D20 Post Divider Register (CCM_POST26) 32 R/W 0000_0000h 5.1.7.18/473
3038_8D24 Post Divider Register (CCM_POST_ROOT26_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8D28 Post Divider Register (CCM_POST_ROOT26_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8D2C Post Divider Register (CCM_POST_ROOT26_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8D30 Pre Divider Register (CCM_PRE26) 32 R/W 1000_0000h 5.1.7.22/485
3038_8D34 Pre Divider Register (CCM_PRE_ROOT26_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8D38 Pre Divider Register (CCM_PRE_ROOT26_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8D3C Pre Divider Register (CCM_PRE_ROOT26_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8D70 Access Control Register (CCM_ACCESS_CTRL26) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8D74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT26_SET)
Access Control Register
3038_8D78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT26_CLR)
Access Control Register
3038_8D7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT26_TOG)
3038_8D80 Target Register (CCM_TARGET_ROOT27) 32 R/W 1000_0000h 5.1.7.10/461
3038_8D84 Target Register (CCM_TARGET_ROOT27_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8D88 Target Register (CCM_TARGET_ROOT27_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8D8C Target Register (CCM_TARGET_ROOT27_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8D90 Miscellaneous Register (CCM_MISC27) 32 R/W 0000_0000h 5.1.7.14/469
3038_8D94 Miscellaneous Register (CCM_MISC_ROOT27_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8D98 Miscellaneous Register (CCM_MISC_ROOT27_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8D9C Miscellaneous Register (CCM_MISC_ROOT27_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8DA0 Post Divider Register (CCM_POST27) 32 R/W 0000_0000h 5.1.7.18/473
3038_8DA4 Post Divider Register (CCM_POST_ROOT27_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8DA8 Post Divider Register (CCM_POST_ROOT27_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8DAC Post Divider Register (CCM_POST_ROOT27_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8DB0 Pre Divider Register (CCM_PRE27) 32 R/W 1000_0000h 5.1.7.22/485
3038_8DB4 Pre Divider Register (CCM_PRE_ROOT27_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8DB8 Pre Divider Register (CCM_PRE_ROOT27_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8DBC Pre Divider Register (CCM_PRE_ROOT27_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8DF0 Access Control Register (CCM_ACCESS_CTRL27) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
328 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_8DF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT27_SET)
Access Control Register
3038_8DF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT27_CLR)
Access Control Register
3038_8DFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT27_TOG)
3038_8E00 Target Register (CCM_TARGET_ROOT28) 32 R/W 1000_0000h 5.1.7.10/461
3038_8E04 Target Register (CCM_TARGET_ROOT28_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8E08 Target Register (CCM_TARGET_ROOT28_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8E0C Target Register (CCM_TARGET_ROOT28_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8E10 Miscellaneous Register (CCM_MISC28) 32 R/W 0000_0000h 5.1.7.14/469
3038_8E14 Miscellaneous Register (CCM_MISC_ROOT28_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8E18 Miscellaneous Register (CCM_MISC_ROOT28_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8E1C Miscellaneous Register (CCM_MISC_ROOT28_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8E20 Post Divider Register (CCM_POST28) 32 R/W 0000_0000h 5.1.7.18/473
3038_8E24 Post Divider Register (CCM_POST_ROOT28_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8E28 Post Divider Register (CCM_POST_ROOT28_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8E2C Post Divider Register (CCM_POST_ROOT28_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8E30 Pre Divider Register (CCM_PRE28) 32 R/W 1000_0000h 5.1.7.22/485
3038_8E34 Pre Divider Register (CCM_PRE_ROOT28_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8E38 Pre Divider Register (CCM_PRE_ROOT28_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8E3C Pre Divider Register (CCM_PRE_ROOT28_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8E70 Access Control Register (CCM_ACCESS_CTRL28) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8E74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT28_SET)
Access Control Register
3038_8E78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT28_CLR)
Access Control Register
3038_8E7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT28_TOG)
3038_8E80 Target Register (CCM_TARGET_ROOT29) 32 R/W 1000_0000h 5.1.7.10/461
3038_8E84 Target Register (CCM_TARGET_ROOT29_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8E88 Target Register (CCM_TARGET_ROOT29_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8E8C Target Register (CCM_TARGET_ROOT29_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8E90 Miscellaneous Register (CCM_MISC29) 32 R/W 0000_0000h 5.1.7.14/469
3038_8E94 Miscellaneous Register (CCM_MISC_ROOT29_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8E98 Miscellaneous Register (CCM_MISC_ROOT29_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8E9C Miscellaneous Register (CCM_MISC_ROOT29_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8EA0 Post Divider Register (CCM_POST29) 32 R/W 0000_0000h 5.1.7.18/473
3038_8EA4 Post Divider Register (CCM_POST_ROOT29_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8EA8 Post Divider Register (CCM_POST_ROOT29_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 329
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8EAC Post Divider Register (CCM_POST_ROOT29_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8EB0 Pre Divider Register (CCM_PRE29) 32 R/W 1000_0000h 5.1.7.22/485
3038_8EB4 Pre Divider Register (CCM_PRE_ROOT29_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8EB8 Pre Divider Register (CCM_PRE_ROOT29_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8EBC Pre Divider Register (CCM_PRE_ROOT29_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8EF0 Access Control Register (CCM_ACCESS_CTRL29) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8EF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT29_SET)
Access Control Register
3038_8EF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT29_CLR)
Access Control Register
3038_8EFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT29_TOG)
3038_8F00 Target Register (CCM_TARGET_ROOT30) 32 R/W 1000_0000h 5.1.7.10/461
3038_8F04 Target Register (CCM_TARGET_ROOT30_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8F08 Target Register (CCM_TARGET_ROOT30_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8F0C Target Register (CCM_TARGET_ROOT30_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8F10 Miscellaneous Register (CCM_MISC30) 32 R/W 0000_0000h 5.1.7.14/469
3038_8F14 Miscellaneous Register (CCM_MISC_ROOT30_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8F18 Miscellaneous Register (CCM_MISC_ROOT30_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8F1C Miscellaneous Register (CCM_MISC_ROOT30_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8F20 Post Divider Register (CCM_POST30) 32 R/W 0000_0000h 5.1.7.18/473
3038_8F24 Post Divider Register (CCM_POST_ROOT30_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8F28 Post Divider Register (CCM_POST_ROOT30_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8F2C Post Divider Register (CCM_POST_ROOT30_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8F30 Pre Divider Register (CCM_PRE30) 32 R/W 1000_0000h 5.1.7.22/485
3038_8F34 Pre Divider Register (CCM_PRE_ROOT30_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8F38 Pre Divider Register (CCM_PRE_ROOT30_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8F3C Pre Divider Register (CCM_PRE_ROOT30_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8F70 Access Control Register (CCM_ACCESS_CTRL30) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8F74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT30_SET)
Access Control Register
3038_8F78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT30_CLR)
Access Control Register
3038_8F7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT30_TOG)
3038_8F80 Target Register (CCM_TARGET_ROOT31) 32 R/W 1000_0000h 5.1.7.10/461
3038_8F84 Target Register (CCM_TARGET_ROOT31_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_8F88 Target Register (CCM_TARGET_ROOT31_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_8F8C Target Register (CCM_TARGET_ROOT31_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_8F90 Miscellaneous Register (CCM_MISC31) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
330 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_8F94 Miscellaneous Register (CCM_MISC_ROOT31_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_8F98 Miscellaneous Register (CCM_MISC_ROOT31_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_8F9C Miscellaneous Register (CCM_MISC_ROOT31_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_8FA0 Post Divider Register (CCM_POST31) 32 R/W 0000_0000h 5.1.7.18/473
3038_8FA4 Post Divider Register (CCM_POST_ROOT31_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_8FA8 Post Divider Register (CCM_POST_ROOT31_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_8FAC Post Divider Register (CCM_POST_ROOT31_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_8FB0 Pre Divider Register (CCM_PRE31) 32 R/W 1000_0000h 5.1.7.22/485
3038_8FB4 Pre Divider Register (CCM_PRE_ROOT31_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_8FB8 Pre Divider Register (CCM_PRE_ROOT31_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_8FBC Pre Divider Register (CCM_PRE_ROOT31_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_8FF0 Access Control Register (CCM_ACCESS_CTRL31) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_8FF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT31_SET)
Access Control Register
3038_8FF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT31_CLR)
Access Control Register
3038_8FFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT31_TOG)
3038_9000 Target Register (CCM_TARGET_ROOT32) 32 R/W 1000_0000h 5.1.7.10/461
3038_9004 Target Register (CCM_TARGET_ROOT32_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9008 Target Register (CCM_TARGET_ROOT32_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_900C Target Register (CCM_TARGET_ROOT32_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9010 Miscellaneous Register (CCM_MISC32) 32 R/W 0000_0000h 5.1.7.14/469
3038_9014 Miscellaneous Register (CCM_MISC_ROOT32_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9018 Miscellaneous Register (CCM_MISC_ROOT32_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_901C Miscellaneous Register (CCM_MISC_ROOT32_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9020 Post Divider Register (CCM_POST32) 32 R/W 0000_0000h 5.1.7.18/473
3038_9024 Post Divider Register (CCM_POST_ROOT32_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9028 Post Divider Register (CCM_POST_ROOT32_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_902C Post Divider Register (CCM_POST_ROOT32_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9030 Pre Divider Register (CCM_PRE32) 32 R/W 1000_0000h 5.1.7.22/485
3038_9034 Pre Divider Register (CCM_PRE_ROOT32_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9038 Pre Divider Register (CCM_PRE_ROOT32_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_903C Pre Divider Register (CCM_PRE_ROOT32_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9070 Access Control Register (CCM_ACCESS_CTRL32) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9074 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT32_SET)
Access Control Register
3038_9078 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT32_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 331
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_907C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT32_TOG)
3038_9080 Target Register (CCM_TARGET_ROOT33) 32 R/W 1000_0000h 5.1.7.10/461
3038_9084 Target Register (CCM_TARGET_ROOT33_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9088 Target Register (CCM_TARGET_ROOT33_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_908C Target Register (CCM_TARGET_ROOT33_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9090 Miscellaneous Register (CCM_MISC33) 32 R/W 0000_0000h 5.1.7.14/469
3038_9094 Miscellaneous Register (CCM_MISC_ROOT33_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9098 Miscellaneous Register (CCM_MISC_ROOT33_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_909C Miscellaneous Register (CCM_MISC_ROOT33_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_90A0 Post Divider Register (CCM_POST33) 32 R/W 0000_0000h 5.1.7.18/473
3038_90A4 Post Divider Register (CCM_POST_ROOT33_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_90A8 Post Divider Register (CCM_POST_ROOT33_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_90AC Post Divider Register (CCM_POST_ROOT33_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_90B0 Pre Divider Register (CCM_PRE33) 32 R/W 1000_0000h 5.1.7.22/485
3038_90B4 Pre Divider Register (CCM_PRE_ROOT33_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_90B8 Pre Divider Register (CCM_PRE_ROOT33_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_90BC Pre Divider Register (CCM_PRE_ROOT33_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_90F0 Access Control Register (CCM_ACCESS_CTRL33) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_90F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT33_SET)
Access Control Register
3038_90F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT33_CLR)
Access Control Register
3038_90FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT33_TOG)
3038_9100 Target Register (CCM_TARGET_ROOT34) 32 R/W 1000_0000h 5.1.7.10/461
3038_9104 Target Register (CCM_TARGET_ROOT34_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9108 Target Register (CCM_TARGET_ROOT34_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_910C Target Register (CCM_TARGET_ROOT34_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9110 Miscellaneous Register (CCM_MISC34) 32 R/W 0000_0000h 5.1.7.14/469
3038_9114 Miscellaneous Register (CCM_MISC_ROOT34_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9118 Miscellaneous Register (CCM_MISC_ROOT34_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_911C Miscellaneous Register (CCM_MISC_ROOT34_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9120 Post Divider Register (CCM_POST34) 32 R/W 0000_0000h 5.1.7.18/473
3038_9124 Post Divider Register (CCM_POST_ROOT34_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9128 Post Divider Register (CCM_POST_ROOT34_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_912C Post Divider Register (CCM_POST_ROOT34_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9130 Pre Divider Register (CCM_PRE34) 32 R/W 1000_0000h 5.1.7.22/485
3038_9134 Pre Divider Register (CCM_PRE_ROOT34_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
332 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9138 Pre Divider Register (CCM_PRE_ROOT34_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_913C Pre Divider Register (CCM_PRE_ROOT34_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9170 Access Control Register (CCM_ACCESS_CTRL34) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9174 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT34_SET)
Access Control Register
3038_9178 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT34_CLR)
Access Control Register
3038_917C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT34_TOG)
3038_9180 Target Register (CCM_TARGET_ROOT35) 32 R/W 1000_0000h 5.1.7.10/461
3038_9184 Target Register (CCM_TARGET_ROOT35_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9188 Target Register (CCM_TARGET_ROOT35_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_918C Target Register (CCM_TARGET_ROOT35_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9190 Miscellaneous Register (CCM_MISC35) 32 R/W 0000_0000h 5.1.7.14/469
3038_9194 Miscellaneous Register (CCM_MISC_ROOT35_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9198 Miscellaneous Register (CCM_MISC_ROOT35_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_919C Miscellaneous Register (CCM_MISC_ROOT35_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_91A0 Post Divider Register (CCM_POST35) 32 R/W 0000_0000h 5.1.7.18/473
3038_91A4 Post Divider Register (CCM_POST_ROOT35_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_91A8 Post Divider Register (CCM_POST_ROOT35_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_91AC Post Divider Register (CCM_POST_ROOT35_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_91B0 Pre Divider Register (CCM_PRE35) 32 R/W 1000_0000h 5.1.7.22/485
3038_91B4 Pre Divider Register (CCM_PRE_ROOT35_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_91B8 Pre Divider Register (CCM_PRE_ROOT35_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_91BC Pre Divider Register (CCM_PRE_ROOT35_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_91F0 Access Control Register (CCM_ACCESS_CTRL35) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_91F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT35_SET)
Access Control Register
3038_91F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT35_CLR)
Access Control Register
3038_91FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT35_TOG)
3038_9200 Target Register (CCM_TARGET_ROOT36) 32 R/W 1000_0000h 5.1.7.10/461
3038_9204 Target Register (CCM_TARGET_ROOT36_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9208 Target Register (CCM_TARGET_ROOT36_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_920C Target Register (CCM_TARGET_ROOT36_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9210 Miscellaneous Register (CCM_MISC36) 32 R/W 0000_0000h 5.1.7.14/469
3038_9214 Miscellaneous Register (CCM_MISC_ROOT36_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9218 Miscellaneous Register (CCM_MISC_ROOT36_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_921C Miscellaneous Register (CCM_MISC_ROOT36_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 333
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9220 Post Divider Register (CCM_POST36) 32 R/W 0000_0000h 5.1.7.18/473
3038_9224 Post Divider Register (CCM_POST_ROOT36_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9228 Post Divider Register (CCM_POST_ROOT36_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_922C Post Divider Register (CCM_POST_ROOT36_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9230 Pre Divider Register (CCM_PRE36) 32 R/W 1000_0000h 5.1.7.22/485
3038_9234 Pre Divider Register (CCM_PRE_ROOT36_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9238 Pre Divider Register (CCM_PRE_ROOT36_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_923C Pre Divider Register (CCM_PRE_ROOT36_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9270 Access Control Register (CCM_ACCESS_CTRL36) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9274 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT36_SET)
Access Control Register
3038_9278 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT36_CLR)
Access Control Register
3038_927C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT36_TOG)
3038_9280 Target Register (CCM_TARGET_ROOT37) 32 R/W 1000_0000h 5.1.7.10/461
3038_9284 Target Register (CCM_TARGET_ROOT37_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9288 Target Register (CCM_TARGET_ROOT37_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_928C Target Register (CCM_TARGET_ROOT37_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9290 Miscellaneous Register (CCM_MISC37) 32 R/W 0000_0000h 5.1.7.14/469
3038_9294 Miscellaneous Register (CCM_MISC_ROOT37_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9298 Miscellaneous Register (CCM_MISC_ROOT37_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_929C Miscellaneous Register (CCM_MISC_ROOT37_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_92A0 Post Divider Register (CCM_POST37) 32 R/W 0000_0000h 5.1.7.18/473
3038_92A4 Post Divider Register (CCM_POST_ROOT37_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_92A8 Post Divider Register (CCM_POST_ROOT37_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_92AC Post Divider Register (CCM_POST_ROOT37_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_92B0 Pre Divider Register (CCM_PRE37) 32 R/W 1000_0000h 5.1.7.22/485
3038_92B4 Pre Divider Register (CCM_PRE_ROOT37_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_92B8 Pre Divider Register (CCM_PRE_ROOT37_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_92BC Pre Divider Register (CCM_PRE_ROOT37_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_92F0 Access Control Register (CCM_ACCESS_CTRL37) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_92F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT37_SET)
Access Control Register
3038_92F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT37_CLR)
Access Control Register
3038_92FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT37_TOG)
3038_9300 Target Register (CCM_TARGET_ROOT38) 32 R/W 1000_0000h 5.1.7.10/461
3038_9304 Target Register (CCM_TARGET_ROOT38_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
334 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9308 Target Register (CCM_TARGET_ROOT38_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_930C Target Register (CCM_TARGET_ROOT38_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9310 Miscellaneous Register (CCM_MISC38) 32 R/W 0000_0000h 5.1.7.14/469
3038_9314 Miscellaneous Register (CCM_MISC_ROOT38_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9318 Miscellaneous Register (CCM_MISC_ROOT38_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_931C Miscellaneous Register (CCM_MISC_ROOT38_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9320 Post Divider Register (CCM_POST38) 32 R/W 0000_0000h 5.1.7.18/473
3038_9324 Post Divider Register (CCM_POST_ROOT38_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9328 Post Divider Register (CCM_POST_ROOT38_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_932C Post Divider Register (CCM_POST_ROOT38_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9330 Pre Divider Register (CCM_PRE38) 32 R/W 1000_0000h 5.1.7.22/485
3038_9334 Pre Divider Register (CCM_PRE_ROOT38_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9338 Pre Divider Register (CCM_PRE_ROOT38_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_933C Pre Divider Register (CCM_PRE_ROOT38_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9370 Access Control Register (CCM_ACCESS_CTRL38) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9374 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT38_SET)
Access Control Register
3038_9378 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT38_CLR)
Access Control Register
3038_937C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT38_TOG)
3038_9380 Target Register (CCM_TARGET_ROOT39) 32 R/W 1000_0000h 5.1.7.10/461
3038_9384 Target Register (CCM_TARGET_ROOT39_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9388 Target Register (CCM_TARGET_ROOT39_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_938C Target Register (CCM_TARGET_ROOT39_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9390 Miscellaneous Register (CCM_MISC39) 32 R/W 0000_0000h 5.1.7.14/469
3038_9394 Miscellaneous Register (CCM_MISC_ROOT39_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9398 Miscellaneous Register (CCM_MISC_ROOT39_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_939C Miscellaneous Register (CCM_MISC_ROOT39_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_93A0 Post Divider Register (CCM_POST39) 32 R/W 0000_0000h 5.1.7.18/473
3038_93A4 Post Divider Register (CCM_POST_ROOT39_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_93A8 Post Divider Register (CCM_POST_ROOT39_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_93AC Post Divider Register (CCM_POST_ROOT39_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_93B0 Pre Divider Register (CCM_PRE39) 32 R/W 1000_0000h 5.1.7.22/485
3038_93B4 Pre Divider Register (CCM_PRE_ROOT39_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_93B8 Pre Divider Register (CCM_PRE_ROOT39_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_93BC Pre Divider Register (CCM_PRE_ROOT39_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_93F0 Access Control Register (CCM_ACCESS_CTRL39) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 335
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_93F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT39_SET)
Access Control Register
3038_93F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT39_CLR)
Access Control Register
3038_93FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT39_TOG)
3038_9400 Target Register (CCM_TARGET_ROOT40) 32 R/W 1000_0000h 5.1.7.10/461
3038_9404 Target Register (CCM_TARGET_ROOT40_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9408 Target Register (CCM_TARGET_ROOT40_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_940C Target Register (CCM_TARGET_ROOT40_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9410 Miscellaneous Register (CCM_MISC40) 32 R/W 0000_0000h 5.1.7.14/469
3038_9414 Miscellaneous Register (CCM_MISC_ROOT40_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9418 Miscellaneous Register (CCM_MISC_ROOT40_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_941C Miscellaneous Register (CCM_MISC_ROOT40_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9420 Post Divider Register (CCM_POST40) 32 R/W 0000_0000h 5.1.7.18/473
3038_9424 Post Divider Register (CCM_POST_ROOT40_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9428 Post Divider Register (CCM_POST_ROOT40_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_942C Post Divider Register (CCM_POST_ROOT40_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9430 Pre Divider Register (CCM_PRE40) 32 R/W 1000_0000h 5.1.7.22/485
3038_9434 Pre Divider Register (CCM_PRE_ROOT40_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9438 Pre Divider Register (CCM_PRE_ROOT40_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_943C Pre Divider Register (CCM_PRE_ROOT40_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9470 Access Control Register (CCM_ACCESS_CTRL40) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9474 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT40_SET)
Access Control Register
3038_9478 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT40_CLR)
Access Control Register
3038_947C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT40_TOG)
3038_9480 Target Register (CCM_TARGET_ROOT41) 32 R/W 1000_0000h 5.1.7.10/461
3038_9484 Target Register (CCM_TARGET_ROOT41_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9488 Target Register (CCM_TARGET_ROOT41_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_948C Target Register (CCM_TARGET_ROOT41_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9490 Miscellaneous Register (CCM_MISC41) 32 R/W 0000_0000h 5.1.7.14/469
3038_9494 Miscellaneous Register (CCM_MISC_ROOT41_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9498 Miscellaneous Register (CCM_MISC_ROOT41_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_949C Miscellaneous Register (CCM_MISC_ROOT41_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_94A0 Post Divider Register (CCM_POST41) 32 R/W 0000_0000h 5.1.7.18/473
3038_94A4 Post Divider Register (CCM_POST_ROOT41_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_94A8 Post Divider Register (CCM_POST_ROOT41_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
336 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_94AC Post Divider Register (CCM_POST_ROOT41_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_94B0 Pre Divider Register (CCM_PRE41) 32 R/W 1000_0000h 5.1.7.22/485
3038_94B4 Pre Divider Register (CCM_PRE_ROOT41_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_94B8 Pre Divider Register (CCM_PRE_ROOT41_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_94BC Pre Divider Register (CCM_PRE_ROOT41_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_94F0 Access Control Register (CCM_ACCESS_CTRL41) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_94F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT41_SET)
Access Control Register
3038_94F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT41_CLR)
Access Control Register
3038_94FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT41_TOG)
3038_9500 Target Register (CCM_TARGET_ROOT42) 32 R/W 1000_0000h 5.1.7.10/461
3038_9504 Target Register (CCM_TARGET_ROOT42_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9508 Target Register (CCM_TARGET_ROOT42_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_950C Target Register (CCM_TARGET_ROOT42_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9510 Miscellaneous Register (CCM_MISC42) 32 R/W 0000_0000h 5.1.7.14/469
3038_9514 Miscellaneous Register (CCM_MISC_ROOT42_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9518 Miscellaneous Register (CCM_MISC_ROOT42_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_951C Miscellaneous Register (CCM_MISC_ROOT42_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9520 Post Divider Register (CCM_POST42) 32 R/W 0000_0000h 5.1.7.18/473
3038_9524 Post Divider Register (CCM_POST_ROOT42_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9528 Post Divider Register (CCM_POST_ROOT42_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_952C Post Divider Register (CCM_POST_ROOT42_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9530 Pre Divider Register (CCM_PRE42) 32 R/W 1000_0000h 5.1.7.22/485
3038_9534 Pre Divider Register (CCM_PRE_ROOT42_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9538 Pre Divider Register (CCM_PRE_ROOT42_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_953C Pre Divider Register (CCM_PRE_ROOT42_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9570 Access Control Register (CCM_ACCESS_CTRL42) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9574 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT42_SET)
Access Control Register
3038_9578 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT42_CLR)
Access Control Register
3038_957C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT42_TOG)
3038_9580 Target Register (CCM_TARGET_ROOT43) 32 R/W 1000_0000h 5.1.7.10/461
3038_9584 Target Register (CCM_TARGET_ROOT43_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9588 Target Register (CCM_TARGET_ROOT43_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_958C Target Register (CCM_TARGET_ROOT43_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9590 Miscellaneous Register (CCM_MISC43) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 337
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9594 Miscellaneous Register (CCM_MISC_ROOT43_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9598 Miscellaneous Register (CCM_MISC_ROOT43_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_959C Miscellaneous Register (CCM_MISC_ROOT43_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_95A0 Post Divider Register (CCM_POST43) 32 R/W 0000_0000h 5.1.7.18/473
3038_95A4 Post Divider Register (CCM_POST_ROOT43_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_95A8 Post Divider Register (CCM_POST_ROOT43_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_95AC Post Divider Register (CCM_POST_ROOT43_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_95B0 Pre Divider Register (CCM_PRE43) 32 R/W 1000_0000h 5.1.7.22/485
3038_95B4 Pre Divider Register (CCM_PRE_ROOT43_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_95B8 Pre Divider Register (CCM_PRE_ROOT43_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_95BC Pre Divider Register (CCM_PRE_ROOT43_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_95F0 Access Control Register (CCM_ACCESS_CTRL43) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_95F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT43_SET)
Access Control Register
3038_95F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT43_CLR)
Access Control Register
3038_95FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT43_TOG)
3038_9600 Target Register (CCM_TARGET_ROOT44) 32 R/W 1000_0000h 5.1.7.10/461
3038_9604 Target Register (CCM_TARGET_ROOT44_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9608 Target Register (CCM_TARGET_ROOT44_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_960C Target Register (CCM_TARGET_ROOT44_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9610 Miscellaneous Register (CCM_MISC44) 32 R/W 0000_0000h 5.1.7.14/469
3038_9614 Miscellaneous Register (CCM_MISC_ROOT44_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9618 Miscellaneous Register (CCM_MISC_ROOT44_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_961C Miscellaneous Register (CCM_MISC_ROOT44_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9620 Post Divider Register (CCM_POST44) 32 R/W 0000_0000h 5.1.7.18/473
3038_9624 Post Divider Register (CCM_POST_ROOT44_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9628 Post Divider Register (CCM_POST_ROOT44_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_962C Post Divider Register (CCM_POST_ROOT44_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9630 Pre Divider Register (CCM_PRE44) 32 R/W 1000_0000h 5.1.7.22/485
3038_9634 Pre Divider Register (CCM_PRE_ROOT44_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9638 Pre Divider Register (CCM_PRE_ROOT44_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_963C Pre Divider Register (CCM_PRE_ROOT44_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9670 Access Control Register (CCM_ACCESS_CTRL44) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9674 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT44_SET)
Access Control Register
3038_9678 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT44_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
338 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_967C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT44_TOG)
3038_9680 Target Register (CCM_TARGET_ROOT45) 32 R/W 1000_0000h 5.1.7.10/461
3038_9684 Target Register (CCM_TARGET_ROOT45_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9688 Target Register (CCM_TARGET_ROOT45_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_968C Target Register (CCM_TARGET_ROOT45_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9690 Miscellaneous Register (CCM_MISC45) 32 R/W 0000_0000h 5.1.7.14/469
3038_9694 Miscellaneous Register (CCM_MISC_ROOT45_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9698 Miscellaneous Register (CCM_MISC_ROOT45_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_969C Miscellaneous Register (CCM_MISC_ROOT45_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_96A0 Post Divider Register (CCM_POST45) 32 R/W 0000_0000h 5.1.7.18/473
3038_96A4 Post Divider Register (CCM_POST_ROOT45_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_96A8 Post Divider Register (CCM_POST_ROOT45_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_96AC Post Divider Register (CCM_POST_ROOT45_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_96B0 Pre Divider Register (CCM_PRE45) 32 R/W 1000_0000h 5.1.7.22/485
3038_96B4 Pre Divider Register (CCM_PRE_ROOT45_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_96B8 Pre Divider Register (CCM_PRE_ROOT45_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_96BC Pre Divider Register (CCM_PRE_ROOT45_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_96F0 Access Control Register (CCM_ACCESS_CTRL45) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_96F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT45_SET)
Access Control Register
3038_96F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT45_CLR)
Access Control Register
3038_96FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT45_TOG)
3038_9700 Target Register (CCM_TARGET_ROOT46) 32 R/W 1000_0000h 5.1.7.10/461
3038_9704 Target Register (CCM_TARGET_ROOT46_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9708 Target Register (CCM_TARGET_ROOT46_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_970C Target Register (CCM_TARGET_ROOT46_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9710 Miscellaneous Register (CCM_MISC46) 32 R/W 0000_0000h 5.1.7.14/469
3038_9714 Miscellaneous Register (CCM_MISC_ROOT46_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9718 Miscellaneous Register (CCM_MISC_ROOT46_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_971C Miscellaneous Register (CCM_MISC_ROOT46_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9720 Post Divider Register (CCM_POST46) 32 R/W 0000_0000h 5.1.7.18/473
3038_9724 Post Divider Register (CCM_POST_ROOT46_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9728 Post Divider Register (CCM_POST_ROOT46_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_972C Post Divider Register (CCM_POST_ROOT46_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9730 Pre Divider Register (CCM_PRE46) 32 R/W 1000_0000h 5.1.7.22/485
3038_9734 Pre Divider Register (CCM_PRE_ROOT46_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 339
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9738 Pre Divider Register (CCM_PRE_ROOT46_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_973C Pre Divider Register (CCM_PRE_ROOT46_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9770 Access Control Register (CCM_ACCESS_CTRL46) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9774 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT46_SET)
Access Control Register
3038_9778 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT46_CLR)
Access Control Register
3038_977C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT46_TOG)
3038_9780 Target Register (CCM_TARGET_ROOT47) 32 R/W 1000_0000h 5.1.7.10/461
3038_9784 Target Register (CCM_TARGET_ROOT47_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9788 Target Register (CCM_TARGET_ROOT47_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_978C Target Register (CCM_TARGET_ROOT47_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9790 Miscellaneous Register (CCM_MISC47) 32 R/W 0000_0000h 5.1.7.14/469
3038_9794 Miscellaneous Register (CCM_MISC_ROOT47_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9798 Miscellaneous Register (CCM_MISC_ROOT47_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_979C Miscellaneous Register (CCM_MISC_ROOT47_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_97A0 Post Divider Register (CCM_POST47) 32 R/W 0000_0000h 5.1.7.18/473
3038_97A4 Post Divider Register (CCM_POST_ROOT47_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_97A8 Post Divider Register (CCM_POST_ROOT47_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_97AC Post Divider Register (CCM_POST_ROOT47_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_97B0 Pre Divider Register (CCM_PRE47) 32 R/W 1000_0000h 5.1.7.22/485
3038_97B4 Pre Divider Register (CCM_PRE_ROOT47_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_97B8 Pre Divider Register (CCM_PRE_ROOT47_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_97BC Pre Divider Register (CCM_PRE_ROOT47_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_97F0 Access Control Register (CCM_ACCESS_CTRL47) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_97F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT47_SET)
Access Control Register
3038_97F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT47_CLR)
Access Control Register
3038_97FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT47_TOG)
3038_9800 Target Register (CCM_TARGET_ROOT48) 32 R/W 1000_0000h 5.1.7.10/461
3038_9804 Target Register (CCM_TARGET_ROOT48_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9808 Target Register (CCM_TARGET_ROOT48_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_980C Target Register (CCM_TARGET_ROOT48_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9810 Miscellaneous Register (CCM_MISC48) 32 R/W 0000_0000h 5.1.7.14/469
3038_9814 Miscellaneous Register (CCM_MISC_ROOT48_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9818 Miscellaneous Register (CCM_MISC_ROOT48_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_981C Miscellaneous Register (CCM_MISC_ROOT48_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
340 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9820 Post Divider Register (CCM_POST48) 32 R/W 0000_0000h 5.1.7.18/473
3038_9824 Post Divider Register (CCM_POST_ROOT48_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9828 Post Divider Register (CCM_POST_ROOT48_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_982C Post Divider Register (CCM_POST_ROOT48_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9830 Pre Divider Register (CCM_PRE48) 32 R/W 1000_0000h 5.1.7.22/485
3038_9834 Pre Divider Register (CCM_PRE_ROOT48_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9838 Pre Divider Register (CCM_PRE_ROOT48_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_983C Pre Divider Register (CCM_PRE_ROOT48_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9870 Access Control Register (CCM_ACCESS_CTRL48) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9874 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT48_SET)
Access Control Register
3038_9878 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT48_CLR)
Access Control Register
3038_987C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT48_TOG)
3038_9880 Target Register (CCM_TARGET_ROOT49) 32 R/W 1000_0000h 5.1.7.10/461
3038_9884 Target Register (CCM_TARGET_ROOT49_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9888 Target Register (CCM_TARGET_ROOT49_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_988C Target Register (CCM_TARGET_ROOT49_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9890 Miscellaneous Register (CCM_MISC49) 32 R/W 0000_0000h 5.1.7.14/469
3038_9894 Miscellaneous Register (CCM_MISC_ROOT49_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9898 Miscellaneous Register (CCM_MISC_ROOT49_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_989C Miscellaneous Register (CCM_MISC_ROOT49_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_98A0 Post Divider Register (CCM_POST49) 32 R/W 0000_0000h 5.1.7.18/473
3038_98A4 Post Divider Register (CCM_POST_ROOT49_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_98A8 Post Divider Register (CCM_POST_ROOT49_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_98AC Post Divider Register (CCM_POST_ROOT49_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_98B0 Pre Divider Register (CCM_PRE49) 32 R/W 1000_0000h 5.1.7.22/485
3038_98B4 Pre Divider Register (CCM_PRE_ROOT49_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_98B8 Pre Divider Register (CCM_PRE_ROOT49_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_98BC Pre Divider Register (CCM_PRE_ROOT49_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_98F0 Access Control Register (CCM_ACCESS_CTRL49) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_98F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT49_SET)
Access Control Register
3038_98F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT49_CLR)
Access Control Register
3038_98FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT49_TOG)
3038_9900 Target Register (CCM_TARGET_ROOT50) 32 R/W 1000_0000h 5.1.7.10/461
3038_9904 Target Register (CCM_TARGET_ROOT50_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 341
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9908 Target Register (CCM_TARGET_ROOT50_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_990C Target Register (CCM_TARGET_ROOT50_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9910 Miscellaneous Register (CCM_MISC50) 32 R/W 0000_0000h 5.1.7.14/469
3038_9914 Miscellaneous Register (CCM_MISC_ROOT50_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9918 Miscellaneous Register (CCM_MISC_ROOT50_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_991C Miscellaneous Register (CCM_MISC_ROOT50_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9920 Post Divider Register (CCM_POST50) 32 R/W 0000_0000h 5.1.7.18/473
3038_9924 Post Divider Register (CCM_POST_ROOT50_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9928 Post Divider Register (CCM_POST_ROOT50_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_992C Post Divider Register (CCM_POST_ROOT50_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9930 Pre Divider Register (CCM_PRE50) 32 R/W 1000_0000h 5.1.7.22/485
3038_9934 Pre Divider Register (CCM_PRE_ROOT50_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9938 Pre Divider Register (CCM_PRE_ROOT50_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_993C Pre Divider Register (CCM_PRE_ROOT50_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9970 Access Control Register (CCM_ACCESS_CTRL50) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9974 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT50_SET)
Access Control Register
3038_9978 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT50_CLR)
Access Control Register
3038_997C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT50_TOG)
3038_9980 Target Register (CCM_TARGET_ROOT51) 32 R/W 1000_0000h 5.1.7.10/461
3038_9984 Target Register (CCM_TARGET_ROOT51_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9988 Target Register (CCM_TARGET_ROOT51_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_998C Target Register (CCM_TARGET_ROOT51_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9990 Miscellaneous Register (CCM_MISC51) 32 R/W 0000_0000h 5.1.7.14/469
3038_9994 Miscellaneous Register (CCM_MISC_ROOT51_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9998 Miscellaneous Register (CCM_MISC_ROOT51_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_999C Miscellaneous Register (CCM_MISC_ROOT51_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_99A0 Post Divider Register (CCM_POST51) 32 R/W 0000_0000h 5.1.7.18/473
3038_99A4 Post Divider Register (CCM_POST_ROOT51_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_99A8 Post Divider Register (CCM_POST_ROOT51_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_99AC Post Divider Register (CCM_POST_ROOT51_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_99B0 Pre Divider Register (CCM_PRE51) 32 R/W 1000_0000h 5.1.7.22/485
3038_99B4 Pre Divider Register (CCM_PRE_ROOT51_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_99B8 Pre Divider Register (CCM_PRE_ROOT51_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_99BC Pre Divider Register (CCM_PRE_ROOT51_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_99F0 Access Control Register (CCM_ACCESS_CTRL51) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
342 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_99F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT51_SET)
Access Control Register
3038_99F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT51_CLR)
Access Control Register
3038_99FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT51_TOG)
3038_9A00 Target Register (CCM_TARGET_ROOT52) 32 R/W 1000_0000h 5.1.7.10/461
3038_9A04 Target Register (CCM_TARGET_ROOT52_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9A08 Target Register (CCM_TARGET_ROOT52_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9A0C Target Register (CCM_TARGET_ROOT52_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9A10 Miscellaneous Register (CCM_MISC52) 32 R/W 0000_0000h 5.1.7.14/469
3038_9A14 Miscellaneous Register (CCM_MISC_ROOT52_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9A18 Miscellaneous Register (CCM_MISC_ROOT52_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9A1C Miscellaneous Register (CCM_MISC_ROOT52_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9A20 Post Divider Register (CCM_POST52) 32 R/W 0000_0000h 5.1.7.18/473
3038_9A24 Post Divider Register (CCM_POST_ROOT52_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9A28 Post Divider Register (CCM_POST_ROOT52_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9A2C Post Divider Register (CCM_POST_ROOT52_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9A30 Pre Divider Register (CCM_PRE52) 32 R/W 1000_0000h 5.1.7.22/485
3038_9A34 Pre Divider Register (CCM_PRE_ROOT52_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9A38 Pre Divider Register (CCM_PRE_ROOT52_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9A3C Pre Divider Register (CCM_PRE_ROOT52_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9A70 Access Control Register (CCM_ACCESS_CTRL52) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9A74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT52_SET)
Access Control Register
3038_9A78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT52_CLR)
Access Control Register
3038_9A7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT52_TOG)
3038_9A80 Target Register (CCM_TARGET_ROOT53) 32 R/W 1000_0000h 5.1.7.10/461
3038_9A84 Target Register (CCM_TARGET_ROOT53_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9A88 Target Register (CCM_TARGET_ROOT53_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9A8C Target Register (CCM_TARGET_ROOT53_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9A90 Miscellaneous Register (CCM_MISC53) 32 R/W 0000_0000h 5.1.7.14/469
3038_9A94 Miscellaneous Register (CCM_MISC_ROOT53_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9A98 Miscellaneous Register (CCM_MISC_ROOT53_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9A9C Miscellaneous Register (CCM_MISC_ROOT53_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9AA0 Post Divider Register (CCM_POST53) 32 R/W 0000_0000h 5.1.7.18/473
3038_9AA4 Post Divider Register (CCM_POST_ROOT53_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9AA8 Post Divider Register (CCM_POST_ROOT53_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 343
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9AAC Post Divider Register (CCM_POST_ROOT53_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9AB0 Pre Divider Register (CCM_PRE53) 32 R/W 1000_0000h 5.1.7.22/485
3038_9AB4 Pre Divider Register (CCM_PRE_ROOT53_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9AB8 Pre Divider Register (CCM_PRE_ROOT53_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9ABC Pre Divider Register (CCM_PRE_ROOT53_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9AF0 Access Control Register (CCM_ACCESS_CTRL53) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9AF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT53_SET)
Access Control Register
3038_9AF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT53_CLR)
Access Control Register
3038_9AFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT53_TOG)
3038_9B00 Target Register (CCM_TARGET_ROOT54) 32 R/W 1000_0000h 5.1.7.10/461
3038_9B04 Target Register (CCM_TARGET_ROOT54_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9B08 Target Register (CCM_TARGET_ROOT54_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9B0C Target Register (CCM_TARGET_ROOT54_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9B10 Miscellaneous Register (CCM_MISC54) 32 R/W 0000_0000h 5.1.7.14/469
3038_9B14 Miscellaneous Register (CCM_MISC_ROOT54_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9B18 Miscellaneous Register (CCM_MISC_ROOT54_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9B1C Miscellaneous Register (CCM_MISC_ROOT54_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9B20 Post Divider Register (CCM_POST54) 32 R/W 0000_0000h 5.1.7.18/473
3038_9B24 Post Divider Register (CCM_POST_ROOT54_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9B28 Post Divider Register (CCM_POST_ROOT54_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9B2C Post Divider Register (CCM_POST_ROOT54_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9B30 Pre Divider Register (CCM_PRE54) 32 R/W 1000_0000h 5.1.7.22/485
3038_9B34 Pre Divider Register (CCM_PRE_ROOT54_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9B38 Pre Divider Register (CCM_PRE_ROOT54_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9B3C Pre Divider Register (CCM_PRE_ROOT54_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9B70 Access Control Register (CCM_ACCESS_CTRL54) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9B74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT54_SET)
Access Control Register
3038_9B78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT54_CLR)
Access Control Register
3038_9B7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT54_TOG)
3038_9B80 Target Register (CCM_TARGET_ROOT55) 32 R/W 1000_0000h 5.1.7.10/461
3038_9B84 Target Register (CCM_TARGET_ROOT55_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9B88 Target Register (CCM_TARGET_ROOT55_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9B8C Target Register (CCM_TARGET_ROOT55_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9B90 Miscellaneous Register (CCM_MISC55) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
344 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9B94 Miscellaneous Register (CCM_MISC_ROOT55_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9B98 Miscellaneous Register (CCM_MISC_ROOT55_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9B9C Miscellaneous Register (CCM_MISC_ROOT55_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9BA0 Post Divider Register (CCM_POST55) 32 R/W 0000_0000h 5.1.7.18/473
3038_9BA4 Post Divider Register (CCM_POST_ROOT55_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9BA8 Post Divider Register (CCM_POST_ROOT55_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9BAC Post Divider Register (CCM_POST_ROOT55_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9BB0 Pre Divider Register (CCM_PRE55) 32 R/W 1000_0000h 5.1.7.22/485
3038_9BB4 Pre Divider Register (CCM_PRE_ROOT55_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9BB8 Pre Divider Register (CCM_PRE_ROOT55_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9BBC Pre Divider Register (CCM_PRE_ROOT55_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9BF0 Access Control Register (CCM_ACCESS_CTRL55) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9BF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT55_SET)
Access Control Register
3038_9BF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT55_CLR)
Access Control Register
3038_9BFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT55_TOG)
3038_9C00 Target Register (CCM_TARGET_ROOT56) 32 R/W 1000_0000h 5.1.7.10/461
3038_9C04 Target Register (CCM_TARGET_ROOT56_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9C08 Target Register (CCM_TARGET_ROOT56_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9C0C Target Register (CCM_TARGET_ROOT56_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9C10 Miscellaneous Register (CCM_MISC56) 32 R/W 0000_0000h 5.1.7.14/469
3038_9C14 Miscellaneous Register (CCM_MISC_ROOT56_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9C18 Miscellaneous Register (CCM_MISC_ROOT56_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9C1C Miscellaneous Register (CCM_MISC_ROOT56_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9C20 Post Divider Register (CCM_POST56) 32 R/W 0000_0000h 5.1.7.18/473
3038_9C24 Post Divider Register (CCM_POST_ROOT56_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9C28 Post Divider Register (CCM_POST_ROOT56_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9C2C Post Divider Register (CCM_POST_ROOT56_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9C30 Pre Divider Register (CCM_PRE56) 32 R/W 1000_0000h 5.1.7.22/485
3038_9C34 Pre Divider Register (CCM_PRE_ROOT56_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9C38 Pre Divider Register (CCM_PRE_ROOT56_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9C3C Pre Divider Register (CCM_PRE_ROOT56_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9C70 Access Control Register (CCM_ACCESS_CTRL56) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9C74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT56_SET)
Access Control Register
3038_9C78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT56_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 345
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_9C7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT56_TOG)
3038_9C80 Target Register (CCM_TARGET_ROOT57) 32 R/W 1000_0000h 5.1.7.10/461
3038_9C84 Target Register (CCM_TARGET_ROOT57_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9C88 Target Register (CCM_TARGET_ROOT57_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9C8C Target Register (CCM_TARGET_ROOT57_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9C90 Miscellaneous Register (CCM_MISC57) 32 R/W 0000_0000h 5.1.7.14/469
3038_9C94 Miscellaneous Register (CCM_MISC_ROOT57_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9C98 Miscellaneous Register (CCM_MISC_ROOT57_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9C9C Miscellaneous Register (CCM_MISC_ROOT57_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9CA0 Post Divider Register (CCM_POST57) 32 R/W 0000_0000h 5.1.7.18/473
3038_9CA4 Post Divider Register (CCM_POST_ROOT57_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9CA8 Post Divider Register (CCM_POST_ROOT57_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9CAC Post Divider Register (CCM_POST_ROOT57_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9CB0 Pre Divider Register (CCM_PRE57) 32 R/W 1000_0000h 5.1.7.22/485
3038_9CB4 Pre Divider Register (CCM_PRE_ROOT57_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9CB8 Pre Divider Register (CCM_PRE_ROOT57_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9CBC Pre Divider Register (CCM_PRE_ROOT57_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9CF0 Access Control Register (CCM_ACCESS_CTRL57) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9CF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT57_SET)
Access Control Register
3038_9CF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT57_CLR)
Access Control Register
3038_9CFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT57_TOG)
3038_9D00 Target Register (CCM_TARGET_ROOT58) 32 R/W 1000_0000h 5.1.7.10/461
3038_9D04 Target Register (CCM_TARGET_ROOT58_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9D08 Target Register (CCM_TARGET_ROOT58_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9D0C Target Register (CCM_TARGET_ROOT58_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9D10 Miscellaneous Register (CCM_MISC58) 32 R/W 0000_0000h 5.1.7.14/469
3038_9D14 Miscellaneous Register (CCM_MISC_ROOT58_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9D18 Miscellaneous Register (CCM_MISC_ROOT58_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9D1C Miscellaneous Register (CCM_MISC_ROOT58_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9D20 Post Divider Register (CCM_POST58) 32 R/W 0000_0000h 5.1.7.18/473
3038_9D24 Post Divider Register (CCM_POST_ROOT58_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9D28 Post Divider Register (CCM_POST_ROOT58_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9D2C Post Divider Register (CCM_POST_ROOT58_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9D30 Pre Divider Register (CCM_PRE58) 32 R/W 1000_0000h 5.1.7.22/485
3038_9D34 Pre Divider Register (CCM_PRE_ROOT58_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
346 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9D38 Pre Divider Register (CCM_PRE_ROOT58_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9D3C Pre Divider Register (CCM_PRE_ROOT58_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9D70 Access Control Register (CCM_ACCESS_CTRL58) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9D74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT58_SET)
Access Control Register
3038_9D78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT58_CLR)
Access Control Register
3038_9D7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT58_TOG)
3038_9D80 Target Register (CCM_TARGET_ROOT59) 32 R/W 1000_0000h 5.1.7.10/461
3038_9D84 Target Register (CCM_TARGET_ROOT59_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9D88 Target Register (CCM_TARGET_ROOT59_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9D8C Target Register (CCM_TARGET_ROOT59_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9D90 Miscellaneous Register (CCM_MISC59) 32 R/W 0000_0000h 5.1.7.14/469
3038_9D94 Miscellaneous Register (CCM_MISC_ROOT59_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9D98 Miscellaneous Register (CCM_MISC_ROOT59_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9D9C Miscellaneous Register (CCM_MISC_ROOT59_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9DA0 Post Divider Register (CCM_POST59) 32 R/W 0000_0000h 5.1.7.18/473
3038_9DA4 Post Divider Register (CCM_POST_ROOT59_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9DA8 Post Divider Register (CCM_POST_ROOT59_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9DAC Post Divider Register (CCM_POST_ROOT59_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9DB0 Pre Divider Register (CCM_PRE59) 32 R/W 1000_0000h 5.1.7.22/485
3038_9DB4 Pre Divider Register (CCM_PRE_ROOT59_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9DB8 Pre Divider Register (CCM_PRE_ROOT59_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9DBC Pre Divider Register (CCM_PRE_ROOT59_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9DF0 Access Control Register (CCM_ACCESS_CTRL59) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9DF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT59_SET)
Access Control Register
3038_9DF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT59_CLR)
Access Control Register
3038_9DFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT59_TOG)
3038_9E00 Target Register (CCM_TARGET_ROOT60) 32 R/W 1000_0000h 5.1.7.10/461
3038_9E04 Target Register (CCM_TARGET_ROOT60_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9E08 Target Register (CCM_TARGET_ROOT60_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9E0C Target Register (CCM_TARGET_ROOT60_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9E10 Miscellaneous Register (CCM_MISC60) 32 R/W 0000_0000h 5.1.7.14/469
3038_9E14 Miscellaneous Register (CCM_MISC_ROOT60_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9E18 Miscellaneous Register (CCM_MISC_ROOT60_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9E1C Miscellaneous Register (CCM_MISC_ROOT60_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 347
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9E20 Post Divider Register (CCM_POST60) 32 R/W 0000_0000h 5.1.7.18/473
3038_9E24 Post Divider Register (CCM_POST_ROOT60_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9E28 Post Divider Register (CCM_POST_ROOT60_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9E2C Post Divider Register (CCM_POST_ROOT60_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9E30 Pre Divider Register (CCM_PRE60) 32 R/W 1000_0000h 5.1.7.22/485
3038_9E34 Pre Divider Register (CCM_PRE_ROOT60_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9E38 Pre Divider Register (CCM_PRE_ROOT60_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9E3C Pre Divider Register (CCM_PRE_ROOT60_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9E70 Access Control Register (CCM_ACCESS_CTRL60) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9E74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT60_SET)
Access Control Register
3038_9E78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT60_CLR)
Access Control Register
3038_9E7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT60_TOG)
3038_9E80 Target Register (CCM_TARGET_ROOT61) 32 R/W 1000_0000h 5.1.7.10/461
3038_9E84 Target Register (CCM_TARGET_ROOT61_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9E88 Target Register (CCM_TARGET_ROOT61_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9E8C Target Register (CCM_TARGET_ROOT61_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9E90 Miscellaneous Register (CCM_MISC61) 32 R/W 0000_0000h 5.1.7.14/469
3038_9E94 Miscellaneous Register (CCM_MISC_ROOT61_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9E98 Miscellaneous Register (CCM_MISC_ROOT61_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9E9C Miscellaneous Register (CCM_MISC_ROOT61_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9EA0 Post Divider Register (CCM_POST61) 32 R/W 0000_0000h 5.1.7.18/473
3038_9EA4 Post Divider Register (CCM_POST_ROOT61_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9EA8 Post Divider Register (CCM_POST_ROOT61_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9EAC Post Divider Register (CCM_POST_ROOT61_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9EB0 Pre Divider Register (CCM_PRE61) 32 R/W 1000_0000h 5.1.7.22/485
3038_9EB4 Pre Divider Register (CCM_PRE_ROOT61_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9EB8 Pre Divider Register (CCM_PRE_ROOT61_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9EBC Pre Divider Register (CCM_PRE_ROOT61_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9EF0 Access Control Register (CCM_ACCESS_CTRL61) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9EF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT61_SET)
Access Control Register
3038_9EF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT61_CLR)
Access Control Register
3038_9EFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT61_TOG)
3038_9F00 Target Register (CCM_TARGET_ROOT62) 32 R/W 1000_0000h 5.1.7.10/461
3038_9F04 Target Register (CCM_TARGET_ROOT62_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
348 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_9F08 Target Register (CCM_TARGET_ROOT62_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9F0C Target Register (CCM_TARGET_ROOT62_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9F10 Miscellaneous Register (CCM_MISC62) 32 R/W 0000_0000h 5.1.7.14/469
3038_9F14 Miscellaneous Register (CCM_MISC_ROOT62_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9F18 Miscellaneous Register (CCM_MISC_ROOT62_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9F1C Miscellaneous Register (CCM_MISC_ROOT62_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9F20 Post Divider Register (CCM_POST62) 32 R/W 0000_0000h 5.1.7.18/473
3038_9F24 Post Divider Register (CCM_POST_ROOT62_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9F28 Post Divider Register (CCM_POST_ROOT62_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9F2C Post Divider Register (CCM_POST_ROOT62_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9F30 Pre Divider Register (CCM_PRE62) 32 R/W 1000_0000h 5.1.7.22/485
3038_9F34 Pre Divider Register (CCM_PRE_ROOT62_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9F38 Pre Divider Register (CCM_PRE_ROOT62_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9F3C Pre Divider Register (CCM_PRE_ROOT62_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9F70 Access Control Register (CCM_ACCESS_CTRL62) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_9F74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT62_SET)
Access Control Register
3038_9F78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT62_CLR)
Access Control Register
3038_9F7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT62_TOG)
3038_9F80 Target Register (CCM_TARGET_ROOT63) 32 R/W 1000_0000h 5.1.7.10/461
3038_9F84 Target Register (CCM_TARGET_ROOT63_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_9F88 Target Register (CCM_TARGET_ROOT63_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_9F8C Target Register (CCM_TARGET_ROOT63_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_9F90 Miscellaneous Register (CCM_MISC63) 32 R/W 0000_0000h 5.1.7.14/469
3038_9F94 Miscellaneous Register (CCM_MISC_ROOT63_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_9F98 Miscellaneous Register (CCM_MISC_ROOT63_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_9F9C Miscellaneous Register (CCM_MISC_ROOT63_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_9FA0 Post Divider Register (CCM_POST63) 32 R/W 0000_0000h 5.1.7.18/473
3038_9FA4 Post Divider Register (CCM_POST_ROOT63_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_9FA8 Post Divider Register (CCM_POST_ROOT63_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_9FAC Post Divider Register (CCM_POST_ROOT63_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_9FB0 Pre Divider Register (CCM_PRE63) 32 R/W 1000_0000h 5.1.7.22/485
3038_9FB4 Pre Divider Register (CCM_PRE_ROOT63_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_9FB8 Pre Divider Register (CCM_PRE_ROOT63_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_9FBC Pre Divider Register (CCM_PRE_ROOT63_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_9FF0 Access Control Register (CCM_ACCESS_CTRL63) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 349
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_9FF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT63_SET)
Access Control Register
3038_9FF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT63_CLR)
Access Control Register
3038_9FFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT63_TOG)
3038_A000 Target Register (CCM_TARGET_ROOT64) 32 R/W 1000_0000h 5.1.7.10/461
3038_A004 Target Register (CCM_TARGET_ROOT64_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A008 Target Register (CCM_TARGET_ROOT64_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A00C Target Register (CCM_TARGET_ROOT64_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A010 Miscellaneous Register (CCM_MISC64) 32 R/W 0000_0000h 5.1.7.14/469
3038_A014 Miscellaneous Register (CCM_MISC_ROOT64_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A018 Miscellaneous Register (CCM_MISC_ROOT64_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A01C Miscellaneous Register (CCM_MISC_ROOT64_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A020 Post Divider Register (CCM_POST64) 32 R/W 0000_0000h 5.1.7.18/473
3038_A024 Post Divider Register (CCM_POST_ROOT64_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A028 Post Divider Register (CCM_POST_ROOT64_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A02C Post Divider Register (CCM_POST_ROOT64_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A030 Pre Divider Register (CCM_PRE64) 32 R/W 1000_0000h 5.1.7.22/485
3038_A034 Pre Divider Register (CCM_PRE_ROOT64_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A038 Pre Divider Register (CCM_PRE_ROOT64_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A03C Pre Divider Register (CCM_PRE_ROOT64_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A070 Access Control Register (CCM_ACCESS_CTRL64) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A074 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT64_SET)
Access Control Register
3038_A078 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT64_CLR)
Access Control Register
3038_A07C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT64_TOG)
3038_A080 Target Register (CCM_TARGET_ROOT65) 32 R/W 1000_0000h 5.1.7.10/461
3038_A084 Target Register (CCM_TARGET_ROOT65_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A088 Target Register (CCM_TARGET_ROOT65_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A08C Target Register (CCM_TARGET_ROOT65_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A090 Miscellaneous Register (CCM_MISC65) 32 R/W 0000_0000h 5.1.7.14/469
3038_A094 Miscellaneous Register (CCM_MISC_ROOT65_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A098 Miscellaneous Register (CCM_MISC_ROOT65_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A09C Miscellaneous Register (CCM_MISC_ROOT65_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A0A0 Post Divider Register (CCM_POST65) 32 R/W 0000_0000h 5.1.7.18/473
3038_A0A4 Post Divider Register (CCM_POST_ROOT65_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A0A8 Post Divider Register (CCM_POST_ROOT65_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
350 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A0AC Post Divider Register (CCM_POST_ROOT65_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A0B0 Pre Divider Register (CCM_PRE65) 32 R/W 1000_0000h 5.1.7.22/485
3038_A0B4 Pre Divider Register (CCM_PRE_ROOT65_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A0B8 Pre Divider Register (CCM_PRE_ROOT65_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A0BC Pre Divider Register (CCM_PRE_ROOT65_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A0F0 Access Control Register (CCM_ACCESS_CTRL65) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A0F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT65_SET)
Access Control Register
3038_A0F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT65_CLR)
Access Control Register
3038_A0FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT65_TOG)
3038_A100 Target Register (CCM_TARGET_ROOT66) 32 R/W 1000_0000h 5.1.7.10/461
3038_A104 Target Register (CCM_TARGET_ROOT66_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A108 Target Register (CCM_TARGET_ROOT66_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A10C Target Register (CCM_TARGET_ROOT66_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A110 Miscellaneous Register (CCM_MISC66) 32 R/W 0000_0000h 5.1.7.14/469
3038_A114 Miscellaneous Register (CCM_MISC_ROOT66_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A118 Miscellaneous Register (CCM_MISC_ROOT66_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A11C Miscellaneous Register (CCM_MISC_ROOT66_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A120 Post Divider Register (CCM_POST66) 32 R/W 0000_0000h 5.1.7.18/473
3038_A124 Post Divider Register (CCM_POST_ROOT66_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A128 Post Divider Register (CCM_POST_ROOT66_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A12C Post Divider Register (CCM_POST_ROOT66_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A130 Pre Divider Register (CCM_PRE66) 32 R/W 1000_0000h 5.1.7.22/485
3038_A134 Pre Divider Register (CCM_PRE_ROOT66_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A138 Pre Divider Register (CCM_PRE_ROOT66_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A13C Pre Divider Register (CCM_PRE_ROOT66_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A170 Access Control Register (CCM_ACCESS_CTRL66) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A174 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT66_SET)
Access Control Register
3038_A178 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT66_CLR)
Access Control Register
3038_A17C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT66_TOG)
3038_A180 Target Register (CCM_TARGET_ROOT67) 32 R/W 1000_0000h 5.1.7.10/461
3038_A184 Target Register (CCM_TARGET_ROOT67_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A188 Target Register (CCM_TARGET_ROOT67_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A18C Target Register (CCM_TARGET_ROOT67_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A190 Miscellaneous Register (CCM_MISC67) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 351
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A194 Miscellaneous Register (CCM_MISC_ROOT67_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A198 Miscellaneous Register (CCM_MISC_ROOT67_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A19C Miscellaneous Register (CCM_MISC_ROOT67_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A1A0 Post Divider Register (CCM_POST67) 32 R/W 0000_0000h 5.1.7.18/473
3038_A1A4 Post Divider Register (CCM_POST_ROOT67_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A1A8 Post Divider Register (CCM_POST_ROOT67_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A1AC Post Divider Register (CCM_POST_ROOT67_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A1B0 Pre Divider Register (CCM_PRE67) 32 R/W 1000_0000h 5.1.7.22/485
3038_A1B4 Pre Divider Register (CCM_PRE_ROOT67_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A1B8 Pre Divider Register (CCM_PRE_ROOT67_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A1BC Pre Divider Register (CCM_PRE_ROOT67_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A1F0 Access Control Register (CCM_ACCESS_CTRL67) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A1F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT67_SET)
Access Control Register
3038_A1F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT67_CLR)
Access Control Register
3038_A1FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT67_TOG)
3038_A200 Target Register (CCM_TARGET_ROOT68) 32 R/W 1000_0000h 5.1.7.10/461
3038_A204 Target Register (CCM_TARGET_ROOT68_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A208 Target Register (CCM_TARGET_ROOT68_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A20C Target Register (CCM_TARGET_ROOT68_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A210 Miscellaneous Register (CCM_MISC68) 32 R/W 0000_0000h 5.1.7.14/469
3038_A214 Miscellaneous Register (CCM_MISC_ROOT68_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A218 Miscellaneous Register (CCM_MISC_ROOT68_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A21C Miscellaneous Register (CCM_MISC_ROOT68_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A220 Post Divider Register (CCM_POST68) 32 R/W 0000_0000h 5.1.7.18/473
3038_A224 Post Divider Register (CCM_POST_ROOT68_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A228 Post Divider Register (CCM_POST_ROOT68_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A22C Post Divider Register (CCM_POST_ROOT68_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A230 Pre Divider Register (CCM_PRE68) 32 R/W 1000_0000h 5.1.7.22/485
3038_A234 Pre Divider Register (CCM_PRE_ROOT68_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A238 Pre Divider Register (CCM_PRE_ROOT68_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A23C Pre Divider Register (CCM_PRE_ROOT68_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A270 Access Control Register (CCM_ACCESS_CTRL68) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A274 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT68_SET)
Access Control Register
3038_A278 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT68_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
352 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_A27C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT68_TOG)
3038_A280 Target Register (CCM_TARGET_ROOT69) 32 R/W 1000_0000h 5.1.7.10/461
3038_A284 Target Register (CCM_TARGET_ROOT69_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A288 Target Register (CCM_TARGET_ROOT69_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A28C Target Register (CCM_TARGET_ROOT69_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A290 Miscellaneous Register (CCM_MISC69) 32 R/W 0000_0000h 5.1.7.14/469
3038_A294 Miscellaneous Register (CCM_MISC_ROOT69_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A298 Miscellaneous Register (CCM_MISC_ROOT69_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A29C Miscellaneous Register (CCM_MISC_ROOT69_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A2A0 Post Divider Register (CCM_POST69) 32 R/W 0000_0000h 5.1.7.18/473
3038_A2A4 Post Divider Register (CCM_POST_ROOT69_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A2A8 Post Divider Register (CCM_POST_ROOT69_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A2AC Post Divider Register (CCM_POST_ROOT69_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A2B0 Pre Divider Register (CCM_PRE69) 32 R/W 1000_0000h 5.1.7.22/485
3038_A2B4 Pre Divider Register (CCM_PRE_ROOT69_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A2B8 Pre Divider Register (CCM_PRE_ROOT69_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A2BC Pre Divider Register (CCM_PRE_ROOT69_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A2F0 Access Control Register (CCM_ACCESS_CTRL69) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A2F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT69_SET)
Access Control Register
3038_A2F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT69_CLR)
Access Control Register
3038_A2FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT69_TOG)
3038_A300 Target Register (CCM_TARGET_ROOT70) 32 R/W 1000_0000h 5.1.7.10/461
3038_A304 Target Register (CCM_TARGET_ROOT70_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A308 Target Register (CCM_TARGET_ROOT70_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A30C Target Register (CCM_TARGET_ROOT70_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A310 Miscellaneous Register (CCM_MISC70) 32 R/W 0000_0000h 5.1.7.14/469
3038_A314 Miscellaneous Register (CCM_MISC_ROOT70_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A318 Miscellaneous Register (CCM_MISC_ROOT70_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A31C Miscellaneous Register (CCM_MISC_ROOT70_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A320 Post Divider Register (CCM_POST70) 32 R/W 0000_0000h 5.1.7.18/473
3038_A324 Post Divider Register (CCM_POST_ROOT70_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A328 Post Divider Register (CCM_POST_ROOT70_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A32C Post Divider Register (CCM_POST_ROOT70_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A330 Pre Divider Register (CCM_PRE70) 32 R/W 1000_0000h 5.1.7.22/485
3038_A334 Pre Divider Register (CCM_PRE_ROOT70_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 353
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A338 Pre Divider Register (CCM_PRE_ROOT70_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A33C Pre Divider Register (CCM_PRE_ROOT70_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A370 Access Control Register (CCM_ACCESS_CTRL70) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A374 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT70_SET)
Access Control Register
3038_A378 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT70_CLR)
Access Control Register
3038_A37C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT70_TOG)
3038_A380 Target Register (CCM_TARGET_ROOT71) 32 R/W 1000_0000h 5.1.7.10/461
3038_A384 Target Register (CCM_TARGET_ROOT71_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A388 Target Register (CCM_TARGET_ROOT71_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A38C Target Register (CCM_TARGET_ROOT71_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A390 Miscellaneous Register (CCM_MISC71) 32 R/W 0000_0000h 5.1.7.14/469
3038_A394 Miscellaneous Register (CCM_MISC_ROOT71_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A398 Miscellaneous Register (CCM_MISC_ROOT71_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A39C Miscellaneous Register (CCM_MISC_ROOT71_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A3A0 Post Divider Register (CCM_POST71) 32 R/W 0000_0000h 5.1.7.18/473
3038_A3A4 Post Divider Register (CCM_POST_ROOT71_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A3A8 Post Divider Register (CCM_POST_ROOT71_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A3AC Post Divider Register (CCM_POST_ROOT71_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A3B0 Pre Divider Register (CCM_PRE71) 32 R/W 1000_0000h 5.1.7.22/485
3038_A3B4 Pre Divider Register (CCM_PRE_ROOT71_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A3B8 Pre Divider Register (CCM_PRE_ROOT71_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A3BC Pre Divider Register (CCM_PRE_ROOT71_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A3F0 Access Control Register (CCM_ACCESS_CTRL71) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A3F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT71_SET)
Access Control Register
3038_A3F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT71_CLR)
Access Control Register
3038_A3FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT71_TOG)
3038_A400 Target Register (CCM_TARGET_ROOT72) 32 R/W 1000_0000h 5.1.7.10/461
3038_A404 Target Register (CCM_TARGET_ROOT72_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A408 Target Register (CCM_TARGET_ROOT72_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A40C Target Register (CCM_TARGET_ROOT72_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A410 Miscellaneous Register (CCM_MISC72) 32 R/W 0000_0000h 5.1.7.14/469
3038_A414 Miscellaneous Register (CCM_MISC_ROOT72_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A418 Miscellaneous Register (CCM_MISC_ROOT72_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A41C Miscellaneous Register (CCM_MISC_ROOT72_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
354 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A420 Post Divider Register (CCM_POST72) 32 R/W 0000_0000h 5.1.7.18/473
3038_A424 Post Divider Register (CCM_POST_ROOT72_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A428 Post Divider Register (CCM_POST_ROOT72_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A42C Post Divider Register (CCM_POST_ROOT72_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A430 Pre Divider Register (CCM_PRE72) 32 R/W 1000_0000h 5.1.7.22/485
3038_A434 Pre Divider Register (CCM_PRE_ROOT72_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A438 Pre Divider Register (CCM_PRE_ROOT72_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A43C Pre Divider Register (CCM_PRE_ROOT72_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A470 Access Control Register (CCM_ACCESS_CTRL72) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A474 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT72_SET)
Access Control Register
3038_A478 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT72_CLR)
Access Control Register
3038_A47C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT72_TOG)
3038_A480 Target Register (CCM_TARGET_ROOT73) 32 R/W 1000_0000h 5.1.7.10/461
3038_A484 Target Register (CCM_TARGET_ROOT73_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A488 Target Register (CCM_TARGET_ROOT73_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A48C Target Register (CCM_TARGET_ROOT73_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A490 Miscellaneous Register (CCM_MISC73) 32 R/W 0000_0000h 5.1.7.14/469
3038_A494 Miscellaneous Register (CCM_MISC_ROOT73_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A498 Miscellaneous Register (CCM_MISC_ROOT73_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A49C Miscellaneous Register (CCM_MISC_ROOT73_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A4A0 Post Divider Register (CCM_POST73) 32 R/W 0000_0000h 5.1.7.18/473
3038_A4A4 Post Divider Register (CCM_POST_ROOT73_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A4A8 Post Divider Register (CCM_POST_ROOT73_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A4AC Post Divider Register (CCM_POST_ROOT73_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A4B0 Pre Divider Register (CCM_PRE73) 32 R/W 1000_0000h 5.1.7.22/485
3038_A4B4 Pre Divider Register (CCM_PRE_ROOT73_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A4B8 Pre Divider Register (CCM_PRE_ROOT73_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A4BC Pre Divider Register (CCM_PRE_ROOT73_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A4F0 Access Control Register (CCM_ACCESS_CTRL73) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A4F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT73_SET)
Access Control Register
3038_A4F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT73_CLR)
Access Control Register
3038_A4FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT73_TOG)
3038_A500 Target Register (CCM_TARGET_ROOT74) 32 R/W 1000_0000h 5.1.7.10/461
3038_A504 Target Register (CCM_TARGET_ROOT74_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 355
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A508 Target Register (CCM_TARGET_ROOT74_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A50C Target Register (CCM_TARGET_ROOT74_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A510 Miscellaneous Register (CCM_MISC74) 32 R/W 0000_0000h 5.1.7.14/469
3038_A514 Miscellaneous Register (CCM_MISC_ROOT74_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A518 Miscellaneous Register (CCM_MISC_ROOT74_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A51C Miscellaneous Register (CCM_MISC_ROOT74_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A520 Post Divider Register (CCM_POST74) 32 R/W 0000_0000h 5.1.7.18/473
3038_A524 Post Divider Register (CCM_POST_ROOT74_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A528 Post Divider Register (CCM_POST_ROOT74_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A52C Post Divider Register (CCM_POST_ROOT74_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A530 Pre Divider Register (CCM_PRE74) 32 R/W 1000_0000h 5.1.7.22/485
3038_A534 Pre Divider Register (CCM_PRE_ROOT74_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A538 Pre Divider Register (CCM_PRE_ROOT74_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A53C Pre Divider Register (CCM_PRE_ROOT74_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A570 Access Control Register (CCM_ACCESS_CTRL74) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A574 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT74_SET)
Access Control Register
3038_A578 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT74_CLR)
Access Control Register
3038_A57C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT74_TOG)
3038_A580 Target Register (CCM_TARGET_ROOT75) 32 R/W 1000_0000h 5.1.7.10/461
3038_A584 Target Register (CCM_TARGET_ROOT75_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A588 Target Register (CCM_TARGET_ROOT75_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A58C Target Register (CCM_TARGET_ROOT75_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A590 Miscellaneous Register (CCM_MISC75) 32 R/W 0000_0000h 5.1.7.14/469
3038_A594 Miscellaneous Register (CCM_MISC_ROOT75_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A598 Miscellaneous Register (CCM_MISC_ROOT75_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A59C Miscellaneous Register (CCM_MISC_ROOT75_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A5A0 Post Divider Register (CCM_POST75) 32 R/W 0000_0000h 5.1.7.18/473
3038_A5A4 Post Divider Register (CCM_POST_ROOT75_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A5A8 Post Divider Register (CCM_POST_ROOT75_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A5AC Post Divider Register (CCM_POST_ROOT75_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A5B0 Pre Divider Register (CCM_PRE75) 32 R/W 1000_0000h 5.1.7.22/485
3038_A5B4 Pre Divider Register (CCM_PRE_ROOT75_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A5B8 Pre Divider Register (CCM_PRE_ROOT75_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A5BC Pre Divider Register (CCM_PRE_ROOT75_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A5F0 Access Control Register (CCM_ACCESS_CTRL75) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
356 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_A5F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT75_SET)
Access Control Register
3038_A5F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT75_CLR)
Access Control Register
3038_A5FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT75_TOG)
3038_A600 Target Register (CCM_TARGET_ROOT76) 32 R/W 1000_0000h 5.1.7.10/461
3038_A604 Target Register (CCM_TARGET_ROOT76_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A608 Target Register (CCM_TARGET_ROOT76_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A60C Target Register (CCM_TARGET_ROOT76_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A610 Miscellaneous Register (CCM_MISC76) 32 R/W 0000_0000h 5.1.7.14/469
3038_A614 Miscellaneous Register (CCM_MISC_ROOT76_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A618 Miscellaneous Register (CCM_MISC_ROOT76_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A61C Miscellaneous Register (CCM_MISC_ROOT76_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A620 Post Divider Register (CCM_POST76) 32 R/W 0000_0000h 5.1.7.18/473
3038_A624 Post Divider Register (CCM_POST_ROOT76_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A628 Post Divider Register (CCM_POST_ROOT76_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A62C Post Divider Register (CCM_POST_ROOT76_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A630 Pre Divider Register (CCM_PRE76) 32 R/W 1000_0000h 5.1.7.22/485
3038_A634 Pre Divider Register (CCM_PRE_ROOT76_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A638 Pre Divider Register (CCM_PRE_ROOT76_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A63C Pre Divider Register (CCM_PRE_ROOT76_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A670 Access Control Register (CCM_ACCESS_CTRL76) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A674 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT76_SET)
Access Control Register
3038_A678 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT76_CLR)
Access Control Register
3038_A67C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT76_TOG)
3038_A680 Target Register (CCM_TARGET_ROOT77) 32 R/W 1000_0000h 5.1.7.10/461
3038_A684 Target Register (CCM_TARGET_ROOT77_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A688 Target Register (CCM_TARGET_ROOT77_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A68C Target Register (CCM_TARGET_ROOT77_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A690 Miscellaneous Register (CCM_MISC77) 32 R/W 0000_0000h 5.1.7.14/469
3038_A694 Miscellaneous Register (CCM_MISC_ROOT77_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A698 Miscellaneous Register (CCM_MISC_ROOT77_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A69C Miscellaneous Register (CCM_MISC_ROOT77_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A6A0 Post Divider Register (CCM_POST77) 32 R/W 0000_0000h 5.1.7.18/473
3038_A6A4 Post Divider Register (CCM_POST_ROOT77_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A6A8 Post Divider Register (CCM_POST_ROOT77_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 357
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A6AC Post Divider Register (CCM_POST_ROOT77_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A6B0 Pre Divider Register (CCM_PRE77) 32 R/W 1000_0000h 5.1.7.22/485
3038_A6B4 Pre Divider Register (CCM_PRE_ROOT77_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A6B8 Pre Divider Register (CCM_PRE_ROOT77_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A6BC Pre Divider Register (CCM_PRE_ROOT77_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A6F0 Access Control Register (CCM_ACCESS_CTRL77) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A6F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT77_SET)
Access Control Register
3038_A6F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT77_CLR)
Access Control Register
3038_A6FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT77_TOG)
3038_A700 Target Register (CCM_TARGET_ROOT78) 32 R/W 1000_0000h 5.1.7.10/461
3038_A704 Target Register (CCM_TARGET_ROOT78_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A708 Target Register (CCM_TARGET_ROOT78_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A70C Target Register (CCM_TARGET_ROOT78_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A710 Miscellaneous Register (CCM_MISC78) 32 R/W 0000_0000h 5.1.7.14/469
3038_A714 Miscellaneous Register (CCM_MISC_ROOT78_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A718 Miscellaneous Register (CCM_MISC_ROOT78_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A71C Miscellaneous Register (CCM_MISC_ROOT78_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A720 Post Divider Register (CCM_POST78) 32 R/W 0000_0000h 5.1.7.18/473
3038_A724 Post Divider Register (CCM_POST_ROOT78_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A728 Post Divider Register (CCM_POST_ROOT78_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A72C Post Divider Register (CCM_POST_ROOT78_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A730 Pre Divider Register (CCM_PRE78) 32 R/W 1000_0000h 5.1.7.22/485
3038_A734 Pre Divider Register (CCM_PRE_ROOT78_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A738 Pre Divider Register (CCM_PRE_ROOT78_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A73C Pre Divider Register (CCM_PRE_ROOT78_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A770 Access Control Register (CCM_ACCESS_CTRL78) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A774 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT78_SET)
Access Control Register
3038_A778 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT78_CLR)
Access Control Register
3038_A77C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT78_TOG)
3038_A780 Target Register (CCM_TARGET_ROOT79) 32 R/W 1000_0000h 5.1.7.10/461
3038_A784 Target Register (CCM_TARGET_ROOT79_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A788 Target Register (CCM_TARGET_ROOT79_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A78C Target Register (CCM_TARGET_ROOT79_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A790 Miscellaneous Register (CCM_MISC79) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
358 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A794 Miscellaneous Register (CCM_MISC_ROOT79_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A798 Miscellaneous Register (CCM_MISC_ROOT79_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A79C Miscellaneous Register (CCM_MISC_ROOT79_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A7A0 Post Divider Register (CCM_POST79) 32 R/W 0000_0000h 5.1.7.18/473
3038_A7A4 Post Divider Register (CCM_POST_ROOT79_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A7A8 Post Divider Register (CCM_POST_ROOT79_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A7AC Post Divider Register (CCM_POST_ROOT79_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A7B0 Pre Divider Register (CCM_PRE79) 32 R/W 1000_0000h 5.1.7.22/485
3038_A7B4 Pre Divider Register (CCM_PRE_ROOT79_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A7B8 Pre Divider Register (CCM_PRE_ROOT79_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A7BC Pre Divider Register (CCM_PRE_ROOT79_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A7F0 Access Control Register (CCM_ACCESS_CTRL79) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A7F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT79_SET)
Access Control Register
3038_A7F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT79_CLR)
Access Control Register
3038_A7FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT79_TOG)
3038_A800 Target Register (CCM_TARGET_ROOT80) 32 R/W 1000_0000h 5.1.7.10/461
3038_A804 Target Register (CCM_TARGET_ROOT80_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A808 Target Register (CCM_TARGET_ROOT80_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A80C Target Register (CCM_TARGET_ROOT80_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A810 Miscellaneous Register (CCM_MISC80) 32 R/W 0000_0000h 5.1.7.14/469
3038_A814 Miscellaneous Register (CCM_MISC_ROOT80_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A818 Miscellaneous Register (CCM_MISC_ROOT80_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A81C Miscellaneous Register (CCM_MISC_ROOT80_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A820 Post Divider Register (CCM_POST80) 32 R/W 0000_0000h 5.1.7.18/473
3038_A824 Post Divider Register (CCM_POST_ROOT80_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A828 Post Divider Register (CCM_POST_ROOT80_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A82C Post Divider Register (CCM_POST_ROOT80_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A830 Pre Divider Register (CCM_PRE80) 32 R/W 1000_0000h 5.1.7.22/485
3038_A834 Pre Divider Register (CCM_PRE_ROOT80_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A838 Pre Divider Register (CCM_PRE_ROOT80_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A83C Pre Divider Register (CCM_PRE_ROOT80_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A870 Access Control Register (CCM_ACCESS_CTRL80) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A874 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT80_SET)
Access Control Register
3038_A878 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT80_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 359
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_A87C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT80_TOG)
3038_A880 Target Register (CCM_TARGET_ROOT81) 32 R/W 1000_0000h 5.1.7.10/461
3038_A884 Target Register (CCM_TARGET_ROOT81_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A888 Target Register (CCM_TARGET_ROOT81_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A88C Target Register (CCM_TARGET_ROOT81_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A890 Miscellaneous Register (CCM_MISC81) 32 R/W 0000_0000h 5.1.7.14/469
3038_A894 Miscellaneous Register (CCM_MISC_ROOT81_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A898 Miscellaneous Register (CCM_MISC_ROOT81_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A89C Miscellaneous Register (CCM_MISC_ROOT81_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A8A0 Post Divider Register (CCM_POST81) 32 R/W 0000_0000h 5.1.7.18/473
3038_A8A4 Post Divider Register (CCM_POST_ROOT81_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A8A8 Post Divider Register (CCM_POST_ROOT81_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A8AC Post Divider Register (CCM_POST_ROOT81_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A8B0 Pre Divider Register (CCM_PRE81) 32 R/W 1000_0000h 5.1.7.22/485
3038_A8B4 Pre Divider Register (CCM_PRE_ROOT81_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A8B8 Pre Divider Register (CCM_PRE_ROOT81_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A8BC Pre Divider Register (CCM_PRE_ROOT81_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A8F0 Access Control Register (CCM_ACCESS_CTRL81) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A8F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT81_SET)
Access Control Register
3038_A8F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT81_CLR)
Access Control Register
3038_A8FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT81_TOG)
3038_A900 Target Register (CCM_TARGET_ROOT82) 32 R/W 1000_0000h 5.1.7.10/461
3038_A904 Target Register (CCM_TARGET_ROOT82_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A908 Target Register (CCM_TARGET_ROOT82_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A90C Target Register (CCM_TARGET_ROOT82_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A910 Miscellaneous Register (CCM_MISC82) 32 R/W 0000_0000h 5.1.7.14/469
3038_A914 Miscellaneous Register (CCM_MISC_ROOT82_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A918 Miscellaneous Register (CCM_MISC_ROOT82_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A91C Miscellaneous Register (CCM_MISC_ROOT82_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A920 Post Divider Register (CCM_POST82) 32 R/W 0000_0000h 5.1.7.18/473
3038_A924 Post Divider Register (CCM_POST_ROOT82_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A928 Post Divider Register (CCM_POST_ROOT82_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A92C Post Divider Register (CCM_POST_ROOT82_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A930 Pre Divider Register (CCM_PRE82) 32 R/W 1000_0000h 5.1.7.22/485
3038_A934 Pre Divider Register (CCM_PRE_ROOT82_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
360 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_A938 Pre Divider Register (CCM_PRE_ROOT82_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A93C Pre Divider Register (CCM_PRE_ROOT82_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A970 Access Control Register (CCM_ACCESS_CTRL82) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A974 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT82_SET)
Access Control Register
3038_A978 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT82_CLR)
Access Control Register
3038_A97C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT82_TOG)
3038_A980 Target Register (CCM_TARGET_ROOT83) 32 R/W 1000_0000h 5.1.7.10/461
3038_A984 Target Register (CCM_TARGET_ROOT83_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_A988 Target Register (CCM_TARGET_ROOT83_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_A98C Target Register (CCM_TARGET_ROOT83_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_A990 Miscellaneous Register (CCM_MISC83) 32 R/W 0000_0000h 5.1.7.14/469
3038_A994 Miscellaneous Register (CCM_MISC_ROOT83_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_A998 Miscellaneous Register (CCM_MISC_ROOT83_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_A99C Miscellaneous Register (CCM_MISC_ROOT83_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_A9A0 Post Divider Register (CCM_POST83) 32 R/W 0000_0000h 5.1.7.18/473
3038_A9A4 Post Divider Register (CCM_POST_ROOT83_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_A9A8 Post Divider Register (CCM_POST_ROOT83_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_A9AC Post Divider Register (CCM_POST_ROOT83_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_A9B0 Pre Divider Register (CCM_PRE83) 32 R/W 1000_0000h 5.1.7.22/485
3038_A9B4 Pre Divider Register (CCM_PRE_ROOT83_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_A9B8 Pre Divider Register (CCM_PRE_ROOT83_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_A9BC Pre Divider Register (CCM_PRE_ROOT83_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_A9F0 Access Control Register (CCM_ACCESS_CTRL83) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_A9F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT83_SET)
Access Control Register
3038_A9F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT83_CLR)
Access Control Register
3038_A9FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT83_TOG)
3038_AA00 Target Register (CCM_TARGET_ROOT84) 32 R/W 1000_0000h 5.1.7.10/461
3038_AA04 Target Register (CCM_TARGET_ROOT84_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AA08 Target Register (CCM_TARGET_ROOT84_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AA0C Target Register (CCM_TARGET_ROOT84_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AA10 Miscellaneous Register (CCM_MISC84) 32 R/W 0000_0000h 5.1.7.14/469
3038_AA14 Miscellaneous Register (CCM_MISC_ROOT84_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AA18 Miscellaneous Register (CCM_MISC_ROOT84_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AA1C Miscellaneous Register (CCM_MISC_ROOT84_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 361
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_AA20 Post Divider Register (CCM_POST84) 32 R/W 0000_0000h 5.1.7.18/473
3038_AA24 Post Divider Register (CCM_POST_ROOT84_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AA28 Post Divider Register (CCM_POST_ROOT84_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AA2C Post Divider Register (CCM_POST_ROOT84_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AA30 Pre Divider Register (CCM_PRE84) 32 R/W 1000_0000h 5.1.7.22/485
3038_AA34 Pre Divider Register (CCM_PRE_ROOT84_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AA38 Pre Divider Register (CCM_PRE_ROOT84_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AA3C Pre Divider Register (CCM_PRE_ROOT84_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AA70 Access Control Register (CCM_ACCESS_CTRL84) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AA74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT84_SET)
Access Control Register
3038_AA78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT84_CLR)
Access Control Register
3038_AA7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT84_TOG)
3038_AA80 Target Register (CCM_TARGET_ROOT85) 32 R/W 1000_0000h 5.1.7.10/461
3038_AA84 Target Register (CCM_TARGET_ROOT85_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AA88 Target Register (CCM_TARGET_ROOT85_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AA8C Target Register (CCM_TARGET_ROOT85_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AA90 Miscellaneous Register (CCM_MISC85) 32 R/W 0000_0000h 5.1.7.14/469
3038_AA94 Miscellaneous Register (CCM_MISC_ROOT85_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AA98 Miscellaneous Register (CCM_MISC_ROOT85_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AA9C Miscellaneous Register (CCM_MISC_ROOT85_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AAA0 Post Divider Register (CCM_POST85) 32 R/W 0000_0000h 5.1.7.18/473
3038_AAA4 Post Divider Register (CCM_POST_ROOT85_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AAA8 Post Divider Register (CCM_POST_ROOT85_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AAAC Post Divider Register (CCM_POST_ROOT85_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AAB0 Pre Divider Register (CCM_PRE85) 32 R/W 1000_0000h 5.1.7.22/485
3038_AAB4 Pre Divider Register (CCM_PRE_ROOT85_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AAB8 Pre Divider Register (CCM_PRE_ROOT85_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AABC Pre Divider Register (CCM_PRE_ROOT85_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AAF0 Access Control Register (CCM_ACCESS_CTRL85) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AAF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT85_SET)
Access Control Register
3038_AAF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT85_CLR)
Access Control Register
3038_AAFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT85_TOG)
3038_AB00 Target Register (CCM_TARGET_ROOT86) 32 R/W 1000_0000h 5.1.7.10/461
3038_AB04 Target Register (CCM_TARGET_ROOT86_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
362 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_AB08 Target Register (CCM_TARGET_ROOT86_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AB0C Target Register (CCM_TARGET_ROOT86_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AB10 Miscellaneous Register (CCM_MISC86) 32 R/W 0000_0000h 5.1.7.14/469
3038_AB14 Miscellaneous Register (CCM_MISC_ROOT86_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AB18 Miscellaneous Register (CCM_MISC_ROOT86_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AB1C Miscellaneous Register (CCM_MISC_ROOT86_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AB20 Post Divider Register (CCM_POST86) 32 R/W 0000_0000h 5.1.7.18/473
3038_AB24 Post Divider Register (CCM_POST_ROOT86_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AB28 Post Divider Register (CCM_POST_ROOT86_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AB2C Post Divider Register (CCM_POST_ROOT86_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AB30 Pre Divider Register (CCM_PRE86) 32 R/W 1000_0000h 5.1.7.22/485
3038_AB34 Pre Divider Register (CCM_PRE_ROOT86_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AB38 Pre Divider Register (CCM_PRE_ROOT86_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AB3C Pre Divider Register (CCM_PRE_ROOT86_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AB70 Access Control Register (CCM_ACCESS_CTRL86) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AB74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT86_SET)
Access Control Register
3038_AB78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT86_CLR)
Access Control Register
3038_AB7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT86_TOG)
3038_AB80 Target Register (CCM_TARGET_ROOT87) 32 R/W 1000_0000h 5.1.7.10/461
3038_AB84 Target Register (CCM_TARGET_ROOT87_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AB88 Target Register (CCM_TARGET_ROOT87_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AB8C Target Register (CCM_TARGET_ROOT87_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AB90 Miscellaneous Register (CCM_MISC87) 32 R/W 0000_0000h 5.1.7.14/469
3038_AB94 Miscellaneous Register (CCM_MISC_ROOT87_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AB98 Miscellaneous Register (CCM_MISC_ROOT87_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AB9C Miscellaneous Register (CCM_MISC_ROOT87_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_ABA0 Post Divider Register (CCM_POST87) 32 R/W 0000_0000h 5.1.7.18/473
3038_ABA4 Post Divider Register (CCM_POST_ROOT87_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_ABA8 Post Divider Register (CCM_POST_ROOT87_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_ABAC Post Divider Register (CCM_POST_ROOT87_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_ABB0 Pre Divider Register (CCM_PRE87) 32 R/W 1000_0000h 5.1.7.22/485
3038_ABB4 Pre Divider Register (CCM_PRE_ROOT87_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_ABB8 Pre Divider Register (CCM_PRE_ROOT87_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_ABBC Pre Divider Register (CCM_PRE_ROOT87_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_ABF0 Access Control Register (CCM_ACCESS_CTRL87) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 363
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_ABF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT87_SET)
Access Control Register
3038_ABF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT87_CLR)
Access Control Register
3038_ABFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT87_TOG)
3038_AC00 Target Register (CCM_TARGET_ROOT88) 32 R/W 1000_0000h 5.1.7.10/461
3038_AC04 Target Register (CCM_TARGET_ROOT88_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AC08 Target Register (CCM_TARGET_ROOT88_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AC0C Target Register (CCM_TARGET_ROOT88_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AC10 Miscellaneous Register (CCM_MISC88) 32 R/W 0000_0000h 5.1.7.14/469
3038_AC14 Miscellaneous Register (CCM_MISC_ROOT88_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AC18 Miscellaneous Register (CCM_MISC_ROOT88_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AC1C Miscellaneous Register (CCM_MISC_ROOT88_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AC20 Post Divider Register (CCM_POST88) 32 R/W 0000_0000h 5.1.7.18/473
3038_AC24 Post Divider Register (CCM_POST_ROOT88_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AC28 Post Divider Register (CCM_POST_ROOT88_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AC2C Post Divider Register (CCM_POST_ROOT88_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AC30 Pre Divider Register (CCM_PRE88) 32 R/W 1000_0000h 5.1.7.22/485
3038_AC34 Pre Divider Register (CCM_PRE_ROOT88_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AC38 Pre Divider Register (CCM_PRE_ROOT88_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AC3C Pre Divider Register (CCM_PRE_ROOT88_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AC70 Access Control Register (CCM_ACCESS_CTRL88) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AC74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT88_SET)
Access Control Register
3038_AC78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT88_CLR)
Access Control Register
3038_AC7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT88_TOG)
3038_AC80 Target Register (CCM_TARGET_ROOT89) 32 R/W 1000_0000h 5.1.7.10/461
3038_AC84 Target Register (CCM_TARGET_ROOT89_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AC88 Target Register (CCM_TARGET_ROOT89_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AC8C Target Register (CCM_TARGET_ROOT89_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AC90 Miscellaneous Register (CCM_MISC89) 32 R/W 0000_0000h 5.1.7.14/469
3038_AC94 Miscellaneous Register (CCM_MISC_ROOT89_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AC98 Miscellaneous Register (CCM_MISC_ROOT89_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AC9C Miscellaneous Register (CCM_MISC_ROOT89_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_ACA0 Post Divider Register (CCM_POST89) 32 R/W 0000_0000h 5.1.7.18/473
3038_ACA4 Post Divider Register (CCM_POST_ROOT89_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_ACA8 Post Divider Register (CCM_POST_ROOT89_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
364 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_ACAC Post Divider Register (CCM_POST_ROOT89_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_ACB0 Pre Divider Register (CCM_PRE89) 32 R/W 1000_0000h 5.1.7.22/485
3038_ACB4 Pre Divider Register (CCM_PRE_ROOT89_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_ACB8 Pre Divider Register (CCM_PRE_ROOT89_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_ACBC Pre Divider Register (CCM_PRE_ROOT89_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_ACF0 Access Control Register (CCM_ACCESS_CTRL89) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_ACF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT89_SET)
Access Control Register
3038_ACF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT89_CLR)
Access Control Register
3038_ACFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT89_TOG)
3038_AD00 Target Register (CCM_TARGET_ROOT90) 32 R/W 1000_0000h 5.1.7.10/461
3038_AD04 Target Register (CCM_TARGET_ROOT90_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AD08 Target Register (CCM_TARGET_ROOT90_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AD0C Target Register (CCM_TARGET_ROOT90_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AD10 Miscellaneous Register (CCM_MISC90) 32 R/W 0000_0000h 5.1.7.14/469
3038_AD14 Miscellaneous Register (CCM_MISC_ROOT90_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AD18 Miscellaneous Register (CCM_MISC_ROOT90_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AD1C Miscellaneous Register (CCM_MISC_ROOT90_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AD20 Post Divider Register (CCM_POST90) 32 R/W 0000_0000h 5.1.7.18/473
3038_AD24 Post Divider Register (CCM_POST_ROOT90_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AD28 Post Divider Register (CCM_POST_ROOT90_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AD2C Post Divider Register (CCM_POST_ROOT90_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AD30 Pre Divider Register (CCM_PRE90) 32 R/W 1000_0000h 5.1.7.22/485
3038_AD34 Pre Divider Register (CCM_PRE_ROOT90_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AD38 Pre Divider Register (CCM_PRE_ROOT90_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AD3C Pre Divider Register (CCM_PRE_ROOT90_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AD70 Access Control Register (CCM_ACCESS_CTRL90) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AD74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT90_SET)
Access Control Register
3038_AD78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT90_CLR)
Access Control Register
3038_AD7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT90_TOG)
3038_AD80 Target Register (CCM_TARGET_ROOT91) 32 R/W 1000_0000h 5.1.7.10/461
3038_AD84 Target Register (CCM_TARGET_ROOT91_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AD88 Target Register (CCM_TARGET_ROOT91_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AD8C Target Register (CCM_TARGET_ROOT91_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AD90 Miscellaneous Register (CCM_MISC91) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 365
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_AD94 Miscellaneous Register (CCM_MISC_ROOT91_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AD98 Miscellaneous Register (CCM_MISC_ROOT91_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AD9C Miscellaneous Register (CCM_MISC_ROOT91_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_ADA0 Post Divider Register (CCM_POST91) 32 R/W 0000_0000h 5.1.7.18/473
3038_ADA4 Post Divider Register (CCM_POST_ROOT91_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_ADA8 Post Divider Register (CCM_POST_ROOT91_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_ADAC Post Divider Register (CCM_POST_ROOT91_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_ADB0 Pre Divider Register (CCM_PRE91) 32 R/W 1000_0000h 5.1.7.22/485
3038_ADB4 Pre Divider Register (CCM_PRE_ROOT91_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_ADB8 Pre Divider Register (CCM_PRE_ROOT91_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_ADBC Pre Divider Register (CCM_PRE_ROOT91_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_ADF0 Access Control Register (CCM_ACCESS_CTRL91) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_ADF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT91_SET)
Access Control Register
3038_ADF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT91_CLR)
Access Control Register
3038_ADFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT91_TOG)
3038_AE00 Target Register (CCM_TARGET_ROOT92) 32 R/W 1000_0000h 5.1.7.10/461
3038_AE04 Target Register (CCM_TARGET_ROOT92_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AE08 Target Register (CCM_TARGET_ROOT92_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AE0C Target Register (CCM_TARGET_ROOT92_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AE10 Miscellaneous Register (CCM_MISC92) 32 R/W 0000_0000h 5.1.7.14/469
3038_AE14 Miscellaneous Register (CCM_MISC_ROOT92_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AE18 Miscellaneous Register (CCM_MISC_ROOT92_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AE1C Miscellaneous Register (CCM_MISC_ROOT92_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AE20 Post Divider Register (CCM_POST92) 32 R/W 0000_0000h 5.1.7.18/473
3038_AE24 Post Divider Register (CCM_POST_ROOT92_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AE28 Post Divider Register (CCM_POST_ROOT92_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AE2C Post Divider Register (CCM_POST_ROOT92_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AE30 Pre Divider Register (CCM_PRE92) 32 R/W 1000_0000h 5.1.7.22/485
3038_AE34 Pre Divider Register (CCM_PRE_ROOT92_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AE38 Pre Divider Register (CCM_PRE_ROOT92_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AE3C Pre Divider Register (CCM_PRE_ROOT92_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AE70 Access Control Register (CCM_ACCESS_CTRL92) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AE74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT92_SET)
Access Control Register
3038_AE78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT92_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
366 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_AE7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT92_TOG)
3038_AE80 Target Register (CCM_TARGET_ROOT93) 32 R/W 1000_0000h 5.1.7.10/461
3038_AE84 Target Register (CCM_TARGET_ROOT93_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AE88 Target Register (CCM_TARGET_ROOT93_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AE8C Target Register (CCM_TARGET_ROOT93_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AE90 Miscellaneous Register (CCM_MISC93) 32 R/W 0000_0000h 5.1.7.14/469
3038_AE94 Miscellaneous Register (CCM_MISC_ROOT93_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AE98 Miscellaneous Register (CCM_MISC_ROOT93_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AE9C Miscellaneous Register (CCM_MISC_ROOT93_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AEA0 Post Divider Register (CCM_POST93) 32 R/W 0000_0000h 5.1.7.18/473
3038_AEA4 Post Divider Register (CCM_POST_ROOT93_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AEA8 Post Divider Register (CCM_POST_ROOT93_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AEAC Post Divider Register (CCM_POST_ROOT93_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AEB0 Pre Divider Register (CCM_PRE93) 32 R/W 1000_0000h 5.1.7.22/485
3038_AEB4 Pre Divider Register (CCM_PRE_ROOT93_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AEB8 Pre Divider Register (CCM_PRE_ROOT93_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AEBC Pre Divider Register (CCM_PRE_ROOT93_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AEF0 Access Control Register (CCM_ACCESS_CTRL93) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AEF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT93_SET)
Access Control Register
3038_AEF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT93_CLR)
Access Control Register
3038_AEFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT93_TOG)
3038_AF00 Target Register (CCM_TARGET_ROOT94) 32 R/W 1000_0000h 5.1.7.10/461
3038_AF04 Target Register (CCM_TARGET_ROOT94_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AF08 Target Register (CCM_TARGET_ROOT94_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AF0C Target Register (CCM_TARGET_ROOT94_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AF10 Miscellaneous Register (CCM_MISC94) 32 R/W 0000_0000h 5.1.7.14/469
3038_AF14 Miscellaneous Register (CCM_MISC_ROOT94_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AF18 Miscellaneous Register (CCM_MISC_ROOT94_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AF1C Miscellaneous Register (CCM_MISC_ROOT94_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AF20 Post Divider Register (CCM_POST94) 32 R/W 0000_0000h 5.1.7.18/473
3038_AF24 Post Divider Register (CCM_POST_ROOT94_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AF28 Post Divider Register (CCM_POST_ROOT94_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AF2C Post Divider Register (CCM_POST_ROOT94_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AF30 Pre Divider Register (CCM_PRE94) 32 R/W 1000_0000h 5.1.7.22/485
3038_AF34 Pre Divider Register (CCM_PRE_ROOT94_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 367
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_AF38 Pre Divider Register (CCM_PRE_ROOT94_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AF3C Pre Divider Register (CCM_PRE_ROOT94_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AF70 Access Control Register (CCM_ACCESS_CTRL94) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AF74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT94_SET)
Access Control Register
3038_AF78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT94_CLR)
Access Control Register
3038_AF7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT94_TOG)
3038_AF80 Target Register (CCM_TARGET_ROOT95) 32 R/W 1000_0000h 5.1.7.10/461
3038_AF84 Target Register (CCM_TARGET_ROOT95_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_AF88 Target Register (CCM_TARGET_ROOT95_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_AF8C Target Register (CCM_TARGET_ROOT95_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_AF90 Miscellaneous Register (CCM_MISC95) 32 R/W 0000_0000h 5.1.7.14/469
3038_AF94 Miscellaneous Register (CCM_MISC_ROOT95_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_AF98 Miscellaneous Register (CCM_MISC_ROOT95_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_AF9C Miscellaneous Register (CCM_MISC_ROOT95_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_AFA0 Post Divider Register (CCM_POST95) 32 R/W 0000_0000h 5.1.7.18/473
3038_AFA4 Post Divider Register (CCM_POST_ROOT95_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_AFA8 Post Divider Register (CCM_POST_ROOT95_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_AFAC Post Divider Register (CCM_POST_ROOT95_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_AFB0 Pre Divider Register (CCM_PRE95) 32 R/W 1000_0000h 5.1.7.22/485
3038_AFB4 Pre Divider Register (CCM_PRE_ROOT95_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_AFB8 Pre Divider Register (CCM_PRE_ROOT95_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_AFBC Pre Divider Register (CCM_PRE_ROOT95_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_AFF0 Access Control Register (CCM_ACCESS_CTRL95) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_AFF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT95_SET)
Access Control Register
3038_AFF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT95_CLR)
Access Control Register
3038_AFFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT95_TOG)
3038_B000 Target Register (CCM_TARGET_ROOT96) 32 R/W 1000_0000h 5.1.7.10/461
3038_B004 Target Register (CCM_TARGET_ROOT96_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B008 Target Register (CCM_TARGET_ROOT96_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B00C Target Register (CCM_TARGET_ROOT96_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B010 Miscellaneous Register (CCM_MISC96) 32 R/W 0000_0000h 5.1.7.14/469
3038_B014 Miscellaneous Register (CCM_MISC_ROOT96_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B018 Miscellaneous Register (CCM_MISC_ROOT96_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B01C Miscellaneous Register (CCM_MISC_ROOT96_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
368 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B020 Post Divider Register (CCM_POST96) 32 R/W 0000_0000h 5.1.7.18/473
3038_B024 Post Divider Register (CCM_POST_ROOT96_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B028 Post Divider Register (CCM_POST_ROOT96_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B02C Post Divider Register (CCM_POST_ROOT96_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B030 Pre Divider Register (CCM_PRE96) 32 R/W 1000_0000h 5.1.7.22/485
3038_B034 Pre Divider Register (CCM_PRE_ROOT96_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B038 Pre Divider Register (CCM_PRE_ROOT96_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B03C Pre Divider Register (CCM_PRE_ROOT96_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B070 Access Control Register (CCM_ACCESS_CTRL96) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B074 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT96_SET)
Access Control Register
3038_B078 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT96_CLR)
Access Control Register
3038_B07C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT96_TOG)
3038_B080 Target Register (CCM_TARGET_ROOT97) 32 R/W 1000_0000h 5.1.7.10/461
3038_B084 Target Register (CCM_TARGET_ROOT97_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B088 Target Register (CCM_TARGET_ROOT97_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B08C Target Register (CCM_TARGET_ROOT97_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B090 Miscellaneous Register (CCM_MISC97) 32 R/W 0000_0000h 5.1.7.14/469
3038_B094 Miscellaneous Register (CCM_MISC_ROOT97_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B098 Miscellaneous Register (CCM_MISC_ROOT97_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B09C Miscellaneous Register (CCM_MISC_ROOT97_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B0A0 Post Divider Register (CCM_POST97) 32 R/W 0000_0000h 5.1.7.18/473
3038_B0A4 Post Divider Register (CCM_POST_ROOT97_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B0A8 Post Divider Register (CCM_POST_ROOT97_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B0AC Post Divider Register (CCM_POST_ROOT97_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B0B0 Pre Divider Register (CCM_PRE97) 32 R/W 1000_0000h 5.1.7.22/485
3038_B0B4 Pre Divider Register (CCM_PRE_ROOT97_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B0B8 Pre Divider Register (CCM_PRE_ROOT97_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B0BC Pre Divider Register (CCM_PRE_ROOT97_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B0F0 Access Control Register (CCM_ACCESS_CTRL97) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B0F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT97_SET)
Access Control Register
3038_B0F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT97_CLR)
Access Control Register
3038_B0FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT97_TOG)
3038_B100 Target Register (CCM_TARGET_ROOT98) 32 R/W 1000_0000h 5.1.7.10/461
3038_B104 Target Register (CCM_TARGET_ROOT98_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 369
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B108 Target Register (CCM_TARGET_ROOT98_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B10C Target Register (CCM_TARGET_ROOT98_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B110 Miscellaneous Register (CCM_MISC98) 32 R/W 0000_0000h 5.1.7.14/469
3038_B114 Miscellaneous Register (CCM_MISC_ROOT98_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B118 Miscellaneous Register (CCM_MISC_ROOT98_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B11C Miscellaneous Register (CCM_MISC_ROOT98_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B120 Post Divider Register (CCM_POST98) 32 R/W 0000_0000h 5.1.7.18/473
3038_B124 Post Divider Register (CCM_POST_ROOT98_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B128 Post Divider Register (CCM_POST_ROOT98_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B12C Post Divider Register (CCM_POST_ROOT98_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B130 Pre Divider Register (CCM_PRE98) 32 R/W 1000_0000h 5.1.7.22/485
3038_B134 Pre Divider Register (CCM_PRE_ROOT98_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B138 Pre Divider Register (CCM_PRE_ROOT98_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B13C Pre Divider Register (CCM_PRE_ROOT98_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B170 Access Control Register (CCM_ACCESS_CTRL98) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B174 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT98_SET)
Access Control Register
3038_B178 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT98_CLR)
Access Control Register
3038_B17C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT98_TOG)
3038_B180 Target Register (CCM_TARGET_ROOT99) 32 R/W 1000_0000h 5.1.7.10/461
3038_B184 Target Register (CCM_TARGET_ROOT99_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B188 Target Register (CCM_TARGET_ROOT99_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B18C Target Register (CCM_TARGET_ROOT99_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B190 Miscellaneous Register (CCM_MISC99) 32 R/W 0000_0000h 5.1.7.14/469
3038_B194 Miscellaneous Register (CCM_MISC_ROOT99_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B198 Miscellaneous Register (CCM_MISC_ROOT99_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B19C Miscellaneous Register (CCM_MISC_ROOT99_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B1A0 Post Divider Register (CCM_POST99) 32 R/W 0000_0000h 5.1.7.18/473
3038_B1A4 Post Divider Register (CCM_POST_ROOT99_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B1A8 Post Divider Register (CCM_POST_ROOT99_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B1AC Post Divider Register (CCM_POST_ROOT99_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B1B0 Pre Divider Register (CCM_PRE99) 32 R/W 1000_0000h 5.1.7.22/485
3038_B1B4 Pre Divider Register (CCM_PRE_ROOT99_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B1B8 Pre Divider Register (CCM_PRE_ROOT99_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B1BC Pre Divider Register (CCM_PRE_ROOT99_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B1F0 Access Control Register (CCM_ACCESS_CTRL99) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
370 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_B1F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT99_SET)
Access Control Register
3038_B1F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT99_CLR)
Access Control Register
3038_B1FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT99_TOG)
3038_B200 Target Register (CCM_TARGET_ROOT100) 32 R/W 1000_0000h 5.1.7.10/461
3038_B204 Target Register (CCM_TARGET_ROOT100_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B208 Target Register (CCM_TARGET_ROOT100_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B20C Target Register (CCM_TARGET_ROOT100_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B210 Miscellaneous Register (CCM_MISC100) 32 R/W 0000_0000h 5.1.7.14/469
3038_B214 Miscellaneous Register (CCM_MISC_ROOT100_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B218 Miscellaneous Register (CCM_MISC_ROOT100_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B21C Miscellaneous Register (CCM_MISC_ROOT100_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B220 Post Divider Register (CCM_POST100) 32 R/W 0000_0000h 5.1.7.18/473
3038_B224 Post Divider Register (CCM_POST_ROOT100_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B228 Post Divider Register (CCM_POST_ROOT100_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B22C Post Divider Register (CCM_POST_ROOT100_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B230 Pre Divider Register (CCM_PRE100) 32 R/W 1000_0000h 5.1.7.22/485
3038_B234 Pre Divider Register (CCM_PRE_ROOT100_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B238 Pre Divider Register (CCM_PRE_ROOT100_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B23C Pre Divider Register (CCM_PRE_ROOT100_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B270 Access Control Register (CCM_ACCESS_CTRL100) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B274 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT100_SET)
Access Control Register
3038_B278 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT100_CLR)
Access Control Register
3038_B27C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT100_TOG)
3038_B280 Target Register (CCM_TARGET_ROOT101) 32 R/W 1000_0000h 5.1.7.10/461
3038_B284 Target Register (CCM_TARGET_ROOT101_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B288 Target Register (CCM_TARGET_ROOT101_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B28C Target Register (CCM_TARGET_ROOT101_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B290 Miscellaneous Register (CCM_MISC101) 32 R/W 0000_0000h 5.1.7.14/469
3038_B294 Miscellaneous Register (CCM_MISC_ROOT101_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B298 Miscellaneous Register (CCM_MISC_ROOT101_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B29C Miscellaneous Register (CCM_MISC_ROOT101_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B2A0 Post Divider Register (CCM_POST101) 32 R/W 0000_0000h 5.1.7.18/473
3038_B2A4 Post Divider Register (CCM_POST_ROOT101_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B2A8 Post Divider Register (CCM_POST_ROOT101_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 371
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B2AC Post Divider Register (CCM_POST_ROOT101_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B2B0 Pre Divider Register (CCM_PRE101) 32 R/W 1000_0000h 5.1.7.22/485
3038_B2B4 Pre Divider Register (CCM_PRE_ROOT101_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B2B8 Pre Divider Register (CCM_PRE_ROOT101_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B2BC Pre Divider Register (CCM_PRE_ROOT101_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B2F0 Access Control Register (CCM_ACCESS_CTRL101) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B2F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT101_SET)
Access Control Register
3038_B2F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT101_CLR)
Access Control Register
3038_B2FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT101_TOG)
3038_B300 Target Register (CCM_TARGET_ROOT102) 32 R/W 1000_0000h 5.1.7.10/461
3038_B304 Target Register (CCM_TARGET_ROOT102_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B308 Target Register (CCM_TARGET_ROOT102_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B30C Target Register (CCM_TARGET_ROOT102_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B310 Miscellaneous Register (CCM_MISC102) 32 R/W 0000_0000h 5.1.7.14/469
3038_B314 Miscellaneous Register (CCM_MISC_ROOT102_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B318 Miscellaneous Register (CCM_MISC_ROOT102_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B31C Miscellaneous Register (CCM_MISC_ROOT102_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B320 Post Divider Register (CCM_POST102) 32 R/W 0000_0000h 5.1.7.18/473
3038_B324 Post Divider Register (CCM_POST_ROOT102_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B328 Post Divider Register (CCM_POST_ROOT102_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B32C Post Divider Register (CCM_POST_ROOT102_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B330 Pre Divider Register (CCM_PRE102) 32 R/W 1000_0000h 5.1.7.22/485
3038_B334 Pre Divider Register (CCM_PRE_ROOT102_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B338 Pre Divider Register (CCM_PRE_ROOT102_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B33C Pre Divider Register (CCM_PRE_ROOT102_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B370 Access Control Register (CCM_ACCESS_CTRL102) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B374 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT102_SET)
Access Control Register
3038_B378 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT102_CLR)
Access Control Register
3038_B37C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT102_TOG)
3038_B380 Target Register (CCM_TARGET_ROOT103) 32 R/W 1000_0000h 5.1.7.10/461
3038_B384 Target Register (CCM_TARGET_ROOT103_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B388 Target Register (CCM_TARGET_ROOT103_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B38C Target Register (CCM_TARGET_ROOT103_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B390 Miscellaneous Register (CCM_MISC103) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
372 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B394 Miscellaneous Register (CCM_MISC_ROOT103_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B398 Miscellaneous Register (CCM_MISC_ROOT103_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B39C Miscellaneous Register (CCM_MISC_ROOT103_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B3A0 Post Divider Register (CCM_POST103) 32 R/W 0000_0000h 5.1.7.18/473
3038_B3A4 Post Divider Register (CCM_POST_ROOT103_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B3A8 Post Divider Register (CCM_POST_ROOT103_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B3AC Post Divider Register (CCM_POST_ROOT103_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B3B0 Pre Divider Register (CCM_PRE103) 32 R/W 1000_0000h 5.1.7.22/485
3038_B3B4 Pre Divider Register (CCM_PRE_ROOT103_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B3B8 Pre Divider Register (CCM_PRE_ROOT103_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B3BC Pre Divider Register (CCM_PRE_ROOT103_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B3F0 Access Control Register (CCM_ACCESS_CTRL103) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B3F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT103_SET)
Access Control Register
3038_B3F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT103_CLR)
Access Control Register
3038_B3FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT103_TOG)
3038_B400 Target Register (CCM_TARGET_ROOT104) 32 R/W 1000_0000h 5.1.7.10/461
3038_B404 Target Register (CCM_TARGET_ROOT104_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B408 Target Register (CCM_TARGET_ROOT104_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B40C Target Register (CCM_TARGET_ROOT104_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B410 Miscellaneous Register (CCM_MISC104) 32 R/W 0000_0000h 5.1.7.14/469
3038_B414 Miscellaneous Register (CCM_MISC_ROOT104_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B418 Miscellaneous Register (CCM_MISC_ROOT104_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B41C Miscellaneous Register (CCM_MISC_ROOT104_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B420 Post Divider Register (CCM_POST104) 32 R/W 0000_0000h 5.1.7.18/473
3038_B424 Post Divider Register (CCM_POST_ROOT104_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B428 Post Divider Register (CCM_POST_ROOT104_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B42C Post Divider Register (CCM_POST_ROOT104_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B430 Pre Divider Register (CCM_PRE104) 32 R/W 1000_0000h 5.1.7.22/485
3038_B434 Pre Divider Register (CCM_PRE_ROOT104_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B438 Pre Divider Register (CCM_PRE_ROOT104_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B43C Pre Divider Register (CCM_PRE_ROOT104_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B470 Access Control Register (CCM_ACCESS_CTRL104) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B474 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT104_SET)
Access Control Register
3038_B478 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT104_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 373
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_B47C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT104_TOG)
3038_B480 Target Register (CCM_TARGET_ROOT105) 32 R/W 1000_0000h 5.1.7.10/461
3038_B484 Target Register (CCM_TARGET_ROOT105_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B488 Target Register (CCM_TARGET_ROOT105_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B48C Target Register (CCM_TARGET_ROOT105_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B490 Miscellaneous Register (CCM_MISC105) 32 R/W 0000_0000h 5.1.7.14/469
3038_B494 Miscellaneous Register (CCM_MISC_ROOT105_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B498 Miscellaneous Register (CCM_MISC_ROOT105_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B49C Miscellaneous Register (CCM_MISC_ROOT105_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B4A0 Post Divider Register (CCM_POST105) 32 R/W 0000_0000h 5.1.7.18/473
3038_B4A4 Post Divider Register (CCM_POST_ROOT105_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B4A8 Post Divider Register (CCM_POST_ROOT105_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B4AC Post Divider Register (CCM_POST_ROOT105_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B4B0 Pre Divider Register (CCM_PRE105) 32 R/W 1000_0000h 5.1.7.22/485
3038_B4B4 Pre Divider Register (CCM_PRE_ROOT105_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B4B8 Pre Divider Register (CCM_PRE_ROOT105_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B4BC Pre Divider Register (CCM_PRE_ROOT105_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B4F0 Access Control Register (CCM_ACCESS_CTRL105) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B4F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT105_SET)
Access Control Register
3038_B4F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT105_CLR)
Access Control Register
3038_B4FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT105_TOG)
3038_B500 Target Register (CCM_TARGET_ROOT106) 32 R/W 1000_0000h 5.1.7.10/461
3038_B504 Target Register (CCM_TARGET_ROOT106_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B508 Target Register (CCM_TARGET_ROOT106_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B50C Target Register (CCM_TARGET_ROOT106_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B510 Miscellaneous Register (CCM_MISC106) 32 R/W 0000_0000h 5.1.7.14/469
3038_B514 Miscellaneous Register (CCM_MISC_ROOT106_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B518 Miscellaneous Register (CCM_MISC_ROOT106_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B51C Miscellaneous Register (CCM_MISC_ROOT106_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B520 Post Divider Register (CCM_POST106) 32 R/W 0000_0000h 5.1.7.18/473
3038_B524 Post Divider Register (CCM_POST_ROOT106_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B528 Post Divider Register (CCM_POST_ROOT106_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B52C Post Divider Register (CCM_POST_ROOT106_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B530 Pre Divider Register (CCM_PRE106) 32 R/W 1000_0000h 5.1.7.22/485
3038_B534 Pre Divider Register (CCM_PRE_ROOT106_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
374 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B538 Pre Divider Register (CCM_PRE_ROOT106_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B53C Pre Divider Register (CCM_PRE_ROOT106_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B570 Access Control Register (CCM_ACCESS_CTRL106) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B574 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT106_SET)
Access Control Register
3038_B578 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT106_CLR)
Access Control Register
3038_B57C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT106_TOG)
3038_B580 Target Register (CCM_TARGET_ROOT107) 32 R/W 1000_0000h 5.1.7.10/461
3038_B584 Target Register (CCM_TARGET_ROOT107_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B588 Target Register (CCM_TARGET_ROOT107_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B58C Target Register (CCM_TARGET_ROOT107_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B590 Miscellaneous Register (CCM_MISC107) 32 R/W 0000_0000h 5.1.7.14/469
3038_B594 Miscellaneous Register (CCM_MISC_ROOT107_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B598 Miscellaneous Register (CCM_MISC_ROOT107_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B59C Miscellaneous Register (CCM_MISC_ROOT107_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B5A0 Post Divider Register (CCM_POST107) 32 R/W 0000_0000h 5.1.7.18/473
3038_B5A4 Post Divider Register (CCM_POST_ROOT107_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B5A8 Post Divider Register (CCM_POST_ROOT107_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B5AC Post Divider Register (CCM_POST_ROOT107_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B5B0 Pre Divider Register (CCM_PRE107) 32 R/W 1000_0000h 5.1.7.22/485
3038_B5B4 Pre Divider Register (CCM_PRE_ROOT107_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B5B8 Pre Divider Register (CCM_PRE_ROOT107_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B5BC Pre Divider Register (CCM_PRE_ROOT107_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B5F0 Access Control Register (CCM_ACCESS_CTRL107) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B5F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT107_SET)
Access Control Register
3038_B5F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT107_CLR)
Access Control Register
3038_B5FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT107_TOG)
3038_B600 Target Register (CCM_TARGET_ROOT108) 32 R/W 1000_0000h 5.1.7.10/461
3038_B604 Target Register (CCM_TARGET_ROOT108_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B608 Target Register (CCM_TARGET_ROOT108_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B60C Target Register (CCM_TARGET_ROOT108_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B610 Miscellaneous Register (CCM_MISC108) 32 R/W 0000_0000h 5.1.7.14/469
3038_B614 Miscellaneous Register (CCM_MISC_ROOT108_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B618 Miscellaneous Register (CCM_MISC_ROOT108_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B61C Miscellaneous Register (CCM_MISC_ROOT108_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 375
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B620 Post Divider Register (CCM_POST108) 32 R/W 0000_0000h 5.1.7.18/473
3038_B624 Post Divider Register (CCM_POST_ROOT108_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B628 Post Divider Register (CCM_POST_ROOT108_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B62C Post Divider Register (CCM_POST_ROOT108_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B630 Pre Divider Register (CCM_PRE108) 32 R/W 1000_0000h 5.1.7.22/485
3038_B634 Pre Divider Register (CCM_PRE_ROOT108_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B638 Pre Divider Register (CCM_PRE_ROOT108_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B63C Pre Divider Register (CCM_PRE_ROOT108_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B670 Access Control Register (CCM_ACCESS_CTRL108) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B674 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT108_SET)
Access Control Register
3038_B678 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT108_CLR)
Access Control Register
3038_B67C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT108_TOG)
3038_B680 Target Register (CCM_TARGET_ROOT109) 32 R/W 1000_0000h 5.1.7.10/461
3038_B684 Target Register (CCM_TARGET_ROOT109_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B688 Target Register (CCM_TARGET_ROOT109_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B68C Target Register (CCM_TARGET_ROOT109_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B690 Miscellaneous Register (CCM_MISC109) 32 R/W 0000_0000h 5.1.7.14/469
3038_B694 Miscellaneous Register (CCM_MISC_ROOT109_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B698 Miscellaneous Register (CCM_MISC_ROOT109_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B69C Miscellaneous Register (CCM_MISC_ROOT109_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B6A0 Post Divider Register (CCM_POST109) 32 R/W 0000_0000h 5.1.7.18/473
3038_B6A4 Post Divider Register (CCM_POST_ROOT109_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B6A8 Post Divider Register (CCM_POST_ROOT109_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B6AC Post Divider Register (CCM_POST_ROOT109_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B6B0 Pre Divider Register (CCM_PRE109) 32 R/W 1000_0000h 5.1.7.22/485
3038_B6B4 Pre Divider Register (CCM_PRE_ROOT109_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B6B8 Pre Divider Register (CCM_PRE_ROOT109_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B6BC Pre Divider Register (CCM_PRE_ROOT109_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B6F0 Access Control Register (CCM_ACCESS_CTRL109) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B6F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT109_SET)
Access Control Register
3038_B6F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT109_CLR)
Access Control Register
3038_B6FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT109_TOG)
3038_B700 Target Register (CCM_TARGET_ROOT110) 32 R/W 1000_0000h 5.1.7.10/461
3038_B704 Target Register (CCM_TARGET_ROOT110_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
376 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B708 Target Register (CCM_TARGET_ROOT110_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B70C Target Register (CCM_TARGET_ROOT110_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B710 Miscellaneous Register (CCM_MISC110) 32 R/W 0000_0000h 5.1.7.14/469
3038_B714 Miscellaneous Register (CCM_MISC_ROOT110_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B718 Miscellaneous Register (CCM_MISC_ROOT110_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B71C Miscellaneous Register (CCM_MISC_ROOT110_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B720 Post Divider Register (CCM_POST110) 32 R/W 0000_0000h 5.1.7.18/473
3038_B724 Post Divider Register (CCM_POST_ROOT110_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B728 Post Divider Register (CCM_POST_ROOT110_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B72C Post Divider Register (CCM_POST_ROOT110_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B730 Pre Divider Register (CCM_PRE110) 32 R/W 1000_0000h 5.1.7.22/485
3038_B734 Pre Divider Register (CCM_PRE_ROOT110_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B738 Pre Divider Register (CCM_PRE_ROOT110_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B73C Pre Divider Register (CCM_PRE_ROOT110_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B770 Access Control Register (CCM_ACCESS_CTRL110) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B774 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT110_SET)
Access Control Register
3038_B778 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT110_CLR)
Access Control Register
3038_B77C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT110_TOG)
3038_B780 Target Register (CCM_TARGET_ROOT111) 32 R/W 1000_0000h 5.1.7.10/461
3038_B784 Target Register (CCM_TARGET_ROOT111_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B788 Target Register (CCM_TARGET_ROOT111_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B78C Target Register (CCM_TARGET_ROOT111_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B790 Miscellaneous Register (CCM_MISC111) 32 R/W 0000_0000h 5.1.7.14/469
3038_B794 Miscellaneous Register (CCM_MISC_ROOT111_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B798 Miscellaneous Register (CCM_MISC_ROOT111_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B79C Miscellaneous Register (CCM_MISC_ROOT111_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B7A0 Post Divider Register (CCM_POST111) 32 R/W 0000_0000h 5.1.7.18/473
3038_B7A4 Post Divider Register (CCM_POST_ROOT111_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B7A8 Post Divider Register (CCM_POST_ROOT111_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B7AC Post Divider Register (CCM_POST_ROOT111_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B7B0 Pre Divider Register (CCM_PRE111) 32 R/W 1000_0000h 5.1.7.22/485
3038_B7B4 Pre Divider Register (CCM_PRE_ROOT111_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B7B8 Pre Divider Register (CCM_PRE_ROOT111_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B7BC Pre Divider Register (CCM_PRE_ROOT111_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B7F0 Access Control Register (CCM_ACCESS_CTRL111) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 377
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_B7F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT111_SET)
Access Control Register
3038_B7F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT111_CLR)
Access Control Register
3038_B7FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT111_TOG)
3038_B800 Target Register (CCM_TARGET_ROOT112) 32 R/W 1000_0000h 5.1.7.10/461
3038_B804 Target Register (CCM_TARGET_ROOT112_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B808 Target Register (CCM_TARGET_ROOT112_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B80C Target Register (CCM_TARGET_ROOT112_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B810 Miscellaneous Register (CCM_MISC112) 32 R/W 0000_0000h 5.1.7.14/469
3038_B814 Miscellaneous Register (CCM_MISC_ROOT112_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B818 Miscellaneous Register (CCM_MISC_ROOT112_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B81C Miscellaneous Register (CCM_MISC_ROOT112_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B820 Post Divider Register (CCM_POST112) 32 R/W 0000_0000h 5.1.7.18/473
3038_B824 Post Divider Register (CCM_POST_ROOT112_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B828 Post Divider Register (CCM_POST_ROOT112_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B82C Post Divider Register (CCM_POST_ROOT112_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B830 Pre Divider Register (CCM_PRE112) 32 R/W 1000_0000h 5.1.7.22/485
3038_B834 Pre Divider Register (CCM_PRE_ROOT112_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B838 Pre Divider Register (CCM_PRE_ROOT112_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B83C Pre Divider Register (CCM_PRE_ROOT112_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B870 Access Control Register (CCM_ACCESS_CTRL112) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B874 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT112_SET)
Access Control Register
3038_B878 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT112_CLR)
Access Control Register
3038_B87C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT112_TOG)
3038_B880 Target Register (CCM_TARGET_ROOT113) 32 R/W 1000_0000h 5.1.7.10/461
3038_B884 Target Register (CCM_TARGET_ROOT113_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B888 Target Register (CCM_TARGET_ROOT113_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B88C Target Register (CCM_TARGET_ROOT113_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B890 Miscellaneous Register (CCM_MISC113) 32 R/W 0000_0000h 5.1.7.14/469
3038_B894 Miscellaneous Register (CCM_MISC_ROOT113_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B898 Miscellaneous Register (CCM_MISC_ROOT113_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B89C Miscellaneous Register (CCM_MISC_ROOT113_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B8A0 Post Divider Register (CCM_POST113) 32 R/W 0000_0000h 5.1.7.18/473
3038_B8A4 Post Divider Register (CCM_POST_ROOT113_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B8A8 Post Divider Register (CCM_POST_ROOT113_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
378 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B8AC Post Divider Register (CCM_POST_ROOT113_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B8B0 Pre Divider Register (CCM_PRE113) 32 R/W 1000_0000h 5.1.7.22/485
3038_B8B4 Pre Divider Register (CCM_PRE_ROOT113_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B8B8 Pre Divider Register (CCM_PRE_ROOT113_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B8BC Pre Divider Register (CCM_PRE_ROOT113_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B8F0 Access Control Register (CCM_ACCESS_CTRL113) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B8F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT113_SET)
Access Control Register
3038_B8F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT113_CLR)
Access Control Register
3038_B8FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT113_TOG)
3038_B900 Target Register (CCM_TARGET_ROOT114) 32 R/W 1000_0000h 5.1.7.10/461
3038_B904 Target Register (CCM_TARGET_ROOT114_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B908 Target Register (CCM_TARGET_ROOT114_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B90C Target Register (CCM_TARGET_ROOT114_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B910 Miscellaneous Register (CCM_MISC114) 32 R/W 0000_0000h 5.1.7.14/469
3038_B914 Miscellaneous Register (CCM_MISC_ROOT114_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B918 Miscellaneous Register (CCM_MISC_ROOT114_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B91C Miscellaneous Register (CCM_MISC_ROOT114_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B920 Post Divider Register (CCM_POST114) 32 R/W 0000_0000h 5.1.7.18/473
3038_B924 Post Divider Register (CCM_POST_ROOT114_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B928 Post Divider Register (CCM_POST_ROOT114_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B92C Post Divider Register (CCM_POST_ROOT114_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B930 Pre Divider Register (CCM_PRE114) 32 R/W 1000_0000h 5.1.7.22/485
3038_B934 Pre Divider Register (CCM_PRE_ROOT114_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B938 Pre Divider Register (CCM_PRE_ROOT114_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B93C Pre Divider Register (CCM_PRE_ROOT114_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B970 Access Control Register (CCM_ACCESS_CTRL114) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B974 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT114_SET)
Access Control Register
3038_B978 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT114_CLR)
Access Control Register
3038_B97C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT114_TOG)
3038_B980 Target Register (CCM_TARGET_ROOT115) 32 R/W 1000_0000h 5.1.7.10/461
3038_B984 Target Register (CCM_TARGET_ROOT115_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_B988 Target Register (CCM_TARGET_ROOT115_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_B98C Target Register (CCM_TARGET_ROOT115_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_B990 Miscellaneous Register (CCM_MISC115) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 379
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_B994 Miscellaneous Register (CCM_MISC_ROOT115_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_B998 Miscellaneous Register (CCM_MISC_ROOT115_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_B99C Miscellaneous Register (CCM_MISC_ROOT115_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_B9A0 Post Divider Register (CCM_POST115) 32 R/W 0000_0000h 5.1.7.18/473
3038_B9A4 Post Divider Register (CCM_POST_ROOT115_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_B9A8 Post Divider Register (CCM_POST_ROOT115_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_B9AC Post Divider Register (CCM_POST_ROOT115_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_B9B0 Pre Divider Register (CCM_PRE115) 32 R/W 1000_0000h 5.1.7.22/485
3038_B9B4 Pre Divider Register (CCM_PRE_ROOT115_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_B9B8 Pre Divider Register (CCM_PRE_ROOT115_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_B9BC Pre Divider Register (CCM_PRE_ROOT115_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_B9F0 Access Control Register (CCM_ACCESS_CTRL115) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_B9F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT115_SET)
Access Control Register
3038_B9F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT115_CLR)
Access Control Register
3038_B9FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT115_TOG)
3038_BA00 Target Register (CCM_TARGET_ROOT116) 32 R/W 1000_0000h 5.1.7.10/461
3038_BA04 Target Register (CCM_TARGET_ROOT116_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BA08 Target Register (CCM_TARGET_ROOT116_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BA0C Target Register (CCM_TARGET_ROOT116_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BA10 Miscellaneous Register (CCM_MISC116) 32 R/W 0000_0000h 5.1.7.14/469
3038_BA14 Miscellaneous Register (CCM_MISC_ROOT116_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BA18 Miscellaneous Register (CCM_MISC_ROOT116_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BA1C Miscellaneous Register (CCM_MISC_ROOT116_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BA20 Post Divider Register (CCM_POST116) 32 R/W 0000_0000h 5.1.7.18/473
3038_BA24 Post Divider Register (CCM_POST_ROOT116_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BA28 Post Divider Register (CCM_POST_ROOT116_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BA2C Post Divider Register (CCM_POST_ROOT116_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BA30 Pre Divider Register (CCM_PRE116) 32 R/W 1000_0000h 5.1.7.22/485
3038_BA34 Pre Divider Register (CCM_PRE_ROOT116_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BA38 Pre Divider Register (CCM_PRE_ROOT116_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BA3C Pre Divider Register (CCM_PRE_ROOT116_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BA70 Access Control Register (CCM_ACCESS_CTRL116) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BA74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT116_SET)
Access Control Register
3038_BA78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT116_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
380 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_BA7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT116_TOG)
3038_BA80 Target Register (CCM_TARGET_ROOT117) 32 R/W 1000_0000h 5.1.7.10/461
3038_BA84 Target Register (CCM_TARGET_ROOT117_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BA88 Target Register (CCM_TARGET_ROOT117_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BA8C Target Register (CCM_TARGET_ROOT117_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BA90 Miscellaneous Register (CCM_MISC117) 32 R/W 0000_0000h 5.1.7.14/469
3038_BA94 Miscellaneous Register (CCM_MISC_ROOT117_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BA98 Miscellaneous Register (CCM_MISC_ROOT117_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BA9C Miscellaneous Register (CCM_MISC_ROOT117_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BAA0 Post Divider Register (CCM_POST117) 32 R/W 0000_0000h 5.1.7.18/473
3038_BAA4 Post Divider Register (CCM_POST_ROOT117_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BAA8 Post Divider Register (CCM_POST_ROOT117_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BAAC Post Divider Register (CCM_POST_ROOT117_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BAB0 Pre Divider Register (CCM_PRE117) 32 R/W 1000_0000h 5.1.7.22/485
3038_BAB4 Pre Divider Register (CCM_PRE_ROOT117_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BAB8 Pre Divider Register (CCM_PRE_ROOT117_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BABC Pre Divider Register (CCM_PRE_ROOT117_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BAF0 Access Control Register (CCM_ACCESS_CTRL117) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BAF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT117_SET)
Access Control Register
3038_BAF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT117_CLR)
Access Control Register
3038_BAFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT117_TOG)
3038_BB00 Target Register (CCM_TARGET_ROOT118) 32 R/W 1000_0000h 5.1.7.10/461
3038_BB04 Target Register (CCM_TARGET_ROOT118_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BB08 Target Register (CCM_TARGET_ROOT118_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BB0C Target Register (CCM_TARGET_ROOT118_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BB10 Miscellaneous Register (CCM_MISC118) 32 R/W 0000_0000h 5.1.7.14/469
3038_BB14 Miscellaneous Register (CCM_MISC_ROOT118_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BB18 Miscellaneous Register (CCM_MISC_ROOT118_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BB1C Miscellaneous Register (CCM_MISC_ROOT118_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BB20 Post Divider Register (CCM_POST118) 32 R/W 0000_0000h 5.1.7.18/473
3038_BB24 Post Divider Register (CCM_POST_ROOT118_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BB28 Post Divider Register (CCM_POST_ROOT118_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BB2C Post Divider Register (CCM_POST_ROOT118_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BB30 Pre Divider Register (CCM_PRE118) 32 R/W 1000_0000h 5.1.7.22/485
3038_BB34 Pre Divider Register (CCM_PRE_ROOT118_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 381
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_BB38 Pre Divider Register (CCM_PRE_ROOT118_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BB3C Pre Divider Register (CCM_PRE_ROOT118_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BB70 Access Control Register (CCM_ACCESS_CTRL118) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BB74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT118_SET)
Access Control Register
3038_BB78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT118_CLR)
Access Control Register
3038_BB7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT118_TOG)
3038_BB80 Target Register (CCM_TARGET_ROOT119) 32 R/W 1000_0000h 5.1.7.10/461
3038_BB84 Target Register (CCM_TARGET_ROOT119_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BB88 Target Register (CCM_TARGET_ROOT119_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BB8C Target Register (CCM_TARGET_ROOT119_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BB90 Miscellaneous Register (CCM_MISC119) 32 R/W 0000_0000h 5.1.7.14/469
3038_BB94 Miscellaneous Register (CCM_MISC_ROOT119_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BB98 Miscellaneous Register (CCM_MISC_ROOT119_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BB9C Miscellaneous Register (CCM_MISC_ROOT119_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BBA0 Post Divider Register (CCM_POST119) 32 R/W 0000_0000h 5.1.7.18/473
3038_BBA4 Post Divider Register (CCM_POST_ROOT119_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BBA8 Post Divider Register (CCM_POST_ROOT119_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BBAC Post Divider Register (CCM_POST_ROOT119_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BBB0 Pre Divider Register (CCM_PRE119) 32 R/W 1000_0000h 5.1.7.22/485
3038_BBB4 Pre Divider Register (CCM_PRE_ROOT119_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BBB8 Pre Divider Register (CCM_PRE_ROOT119_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BBBC Pre Divider Register (CCM_PRE_ROOT119_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BBF0 Access Control Register (CCM_ACCESS_CTRL119) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BBF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT119_SET)
Access Control Register
3038_BBF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT119_CLR)
Access Control Register
3038_BBFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT119_TOG)
3038_BC00 Target Register (CCM_TARGET_ROOT120) 32 R/W 1000_0000h 5.1.7.10/461
3038_BC04 Target Register (CCM_TARGET_ROOT120_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BC08 Target Register (CCM_TARGET_ROOT120_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BC0C Target Register (CCM_TARGET_ROOT120_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BC10 Miscellaneous Register (CCM_MISC120) 32 R/W 0000_0000h 5.1.7.14/469
3038_BC14 Miscellaneous Register (CCM_MISC_ROOT120_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BC18 Miscellaneous Register (CCM_MISC_ROOT120_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BC1C Miscellaneous Register (CCM_MISC_ROOT120_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
382 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_BC20 Post Divider Register (CCM_POST120) 32 R/W 0000_0000h 5.1.7.18/473
3038_BC24 Post Divider Register (CCM_POST_ROOT120_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BC28 Post Divider Register (CCM_POST_ROOT120_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BC2C Post Divider Register (CCM_POST_ROOT120_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BC30 Pre Divider Register (CCM_PRE120) 32 R/W 1000_0000h 5.1.7.22/485
3038_BC34 Pre Divider Register (CCM_PRE_ROOT120_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BC38 Pre Divider Register (CCM_PRE_ROOT120_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BC3C Pre Divider Register (CCM_PRE_ROOT120_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BC70 Access Control Register (CCM_ACCESS_CTRL120) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BC74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT120_SET)
Access Control Register
3038_BC78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT120_CLR)
Access Control Register
3038_BC7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT120_TOG)
3038_BC80 Target Register (CCM_TARGET_ROOT121) 32 R/W 1000_0000h 5.1.7.10/461
3038_BC84 Target Register (CCM_TARGET_ROOT121_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BC88 Target Register (CCM_TARGET_ROOT121_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BC8C Target Register (CCM_TARGET_ROOT121_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BC90 Miscellaneous Register (CCM_MISC121) 32 R/W 0000_0000h 5.1.7.14/469
3038_BC94 Miscellaneous Register (CCM_MISC_ROOT121_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BC98 Miscellaneous Register (CCM_MISC_ROOT121_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BC9C Miscellaneous Register (CCM_MISC_ROOT121_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BCA0 Post Divider Register (CCM_POST121) 32 R/W 0000_0000h 5.1.7.18/473
3038_BCA4 Post Divider Register (CCM_POST_ROOT121_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BCA8 Post Divider Register (CCM_POST_ROOT121_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BCAC Post Divider Register (CCM_POST_ROOT121_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BCB0 Pre Divider Register (CCM_PRE121) 32 R/W 1000_0000h 5.1.7.22/485
3038_BCB4 Pre Divider Register (CCM_PRE_ROOT121_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BCB8 Pre Divider Register (CCM_PRE_ROOT121_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BCBC Pre Divider Register (CCM_PRE_ROOT121_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BCF0 Access Control Register (CCM_ACCESS_CTRL121) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BCF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT121_SET)
Access Control Register
3038_BCF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT121_CLR)
Access Control Register
3038_BCFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT121_TOG)
3038_BD00 Target Register (CCM_TARGET_ROOT122) 32 R/W 1000_0000h 5.1.7.10/461
3038_BD04 Target Register (CCM_TARGET_ROOT122_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 383
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_BD08 Target Register (CCM_TARGET_ROOT122_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BD0C Target Register (CCM_TARGET_ROOT122_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BD10 Miscellaneous Register (CCM_MISC122) 32 R/W 0000_0000h 5.1.7.14/469
3038_BD14 Miscellaneous Register (CCM_MISC_ROOT122_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BD18 Miscellaneous Register (CCM_MISC_ROOT122_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BD1C Miscellaneous Register (CCM_MISC_ROOT122_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BD20 Post Divider Register (CCM_POST122) 32 R/W 0000_0000h 5.1.7.18/473
3038_BD24 Post Divider Register (CCM_POST_ROOT122_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BD28 Post Divider Register (CCM_POST_ROOT122_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BD2C Post Divider Register (CCM_POST_ROOT122_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BD30 Pre Divider Register (CCM_PRE122) 32 R/W 1000_0000h 5.1.7.22/485
3038_BD34 Pre Divider Register (CCM_PRE_ROOT122_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BD38 Pre Divider Register (CCM_PRE_ROOT122_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BD3C Pre Divider Register (CCM_PRE_ROOT122_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BD70 Access Control Register (CCM_ACCESS_CTRL122) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BD74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT122_SET)
Access Control Register
3038_BD78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT122_CLR)
Access Control Register
3038_BD7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT122_TOG)
3038_BD80 Target Register (CCM_TARGET_ROOT123) 32 R/W 1000_0000h 5.1.7.10/461
3038_BD84 Target Register (CCM_TARGET_ROOT123_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BD88 Target Register (CCM_TARGET_ROOT123_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BD8C Target Register (CCM_TARGET_ROOT123_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BD90 Miscellaneous Register (CCM_MISC123) 32 R/W 0000_0000h 5.1.7.14/469
3038_BD94 Miscellaneous Register (CCM_MISC_ROOT123_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BD98 Miscellaneous Register (CCM_MISC_ROOT123_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BD9C Miscellaneous Register (CCM_MISC_ROOT123_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BDA0 Post Divider Register (CCM_POST123) 32 R/W 0000_0000h 5.1.7.18/473
3038_BDA4 Post Divider Register (CCM_POST_ROOT123_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BDA8 Post Divider Register (CCM_POST_ROOT123_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BDAC Post Divider Register (CCM_POST_ROOT123_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BDB0 Pre Divider Register (CCM_PRE123) 32 R/W 1000_0000h 5.1.7.22/485
3038_BDB4 Pre Divider Register (CCM_PRE_ROOT123_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BDB8 Pre Divider Register (CCM_PRE_ROOT123_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BDBC Pre Divider Register (CCM_PRE_ROOT123_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BDF0 Access Control Register (CCM_ACCESS_CTRL123) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
384 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_BDF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT123_SET)
Access Control Register
3038_BDF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT123_CLR)
Access Control Register
3038_BDFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT123_TOG)
3038_BE00 Target Register (CCM_TARGET_ROOT124) 32 R/W 1000_0000h 5.1.7.10/461
3038_BE04 Target Register (CCM_TARGET_ROOT124_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BE08 Target Register (CCM_TARGET_ROOT124_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BE0C Target Register (CCM_TARGET_ROOT124_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BE10 Miscellaneous Register (CCM_MISC124) 32 R/W 0000_0000h 5.1.7.14/469
3038_BE14 Miscellaneous Register (CCM_MISC_ROOT124_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BE18 Miscellaneous Register (CCM_MISC_ROOT124_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BE1C Miscellaneous Register (CCM_MISC_ROOT124_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BE20 Post Divider Register (CCM_POST124) 32 R/W 0000_0000h 5.1.7.18/473
3038_BE24 Post Divider Register (CCM_POST_ROOT124_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BE28 Post Divider Register (CCM_POST_ROOT124_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BE2C Post Divider Register (CCM_POST_ROOT124_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BE30 Pre Divider Register (CCM_PRE124) 32 R/W 1000_0000h 5.1.7.22/485
3038_BE34 Pre Divider Register (CCM_PRE_ROOT124_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BE38 Pre Divider Register (CCM_PRE_ROOT124_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BE3C Pre Divider Register (CCM_PRE_ROOT124_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BE70 Access Control Register (CCM_ACCESS_CTRL124) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BE74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT124_SET)
Access Control Register
3038_BE78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT124_CLR)
Access Control Register
3038_BE7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT124_TOG)
3038_BE80 Target Register (CCM_TARGET_ROOT125) 32 R/W 1000_0000h 5.1.7.10/461
3038_BE84 Target Register (CCM_TARGET_ROOT125_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BE88 Target Register (CCM_TARGET_ROOT125_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BE8C Target Register (CCM_TARGET_ROOT125_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BE90 Miscellaneous Register (CCM_MISC125) 32 R/W 0000_0000h 5.1.7.14/469
3038_BE94 Miscellaneous Register (CCM_MISC_ROOT125_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BE98 Miscellaneous Register (CCM_MISC_ROOT125_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BE9C Miscellaneous Register (CCM_MISC_ROOT125_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BEA0 Post Divider Register (CCM_POST125) 32 R/W 0000_0000h 5.1.7.18/473
3038_BEA4 Post Divider Register (CCM_POST_ROOT125_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BEA8 Post Divider Register (CCM_POST_ROOT125_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 385
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_BEAC Post Divider Register (CCM_POST_ROOT125_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BEB0 Pre Divider Register (CCM_PRE125) 32 R/W 1000_0000h 5.1.7.22/485
3038_BEB4 Pre Divider Register (CCM_PRE_ROOT125_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BEB8 Pre Divider Register (CCM_PRE_ROOT125_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BEBC Pre Divider Register (CCM_PRE_ROOT125_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BEF0 Access Control Register (CCM_ACCESS_CTRL125) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BEF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT125_SET)
Access Control Register
3038_BEF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT125_CLR)
Access Control Register
3038_BEFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT125_TOG)
3038_BF00 Target Register (CCM_TARGET_ROOT126) 32 R/W 1000_0000h 5.1.7.10/461
3038_BF04 Target Register (CCM_TARGET_ROOT126_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BF08 Target Register (CCM_TARGET_ROOT126_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BF0C Target Register (CCM_TARGET_ROOT126_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BF10 Miscellaneous Register (CCM_MISC126) 32 R/W 0000_0000h 5.1.7.14/469
3038_BF14 Miscellaneous Register (CCM_MISC_ROOT126_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BF18 Miscellaneous Register (CCM_MISC_ROOT126_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BF1C Miscellaneous Register (CCM_MISC_ROOT126_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BF20 Post Divider Register (CCM_POST126) 32 R/W 0000_0000h 5.1.7.18/473
3038_BF24 Post Divider Register (CCM_POST_ROOT126_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BF28 Post Divider Register (CCM_POST_ROOT126_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BF2C Post Divider Register (CCM_POST_ROOT126_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BF30 Pre Divider Register (CCM_PRE126) 32 R/W 1000_0000h 5.1.7.22/485
3038_BF34 Pre Divider Register (CCM_PRE_ROOT126_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BF38 Pre Divider Register (CCM_PRE_ROOT126_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BF3C Pre Divider Register (CCM_PRE_ROOT126_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BF70 Access Control Register (CCM_ACCESS_CTRL126) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BF74 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT126_SET)
Access Control Register
3038_BF78 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT126_CLR)
Access Control Register
3038_BF7C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT126_TOG)
3038_BF80 Target Register (CCM_TARGET_ROOT127) 32 R/W 1000_0000h 5.1.7.10/461
3038_BF84 Target Register (CCM_TARGET_ROOT127_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_BF88 Target Register (CCM_TARGET_ROOT127_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_BF8C Target Register (CCM_TARGET_ROOT127_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_BF90 Miscellaneous Register (CCM_MISC127) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
386 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_BF94 Miscellaneous Register (CCM_MISC_ROOT127_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_BF98 Miscellaneous Register (CCM_MISC_ROOT127_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_BF9C Miscellaneous Register (CCM_MISC_ROOT127_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_BFA0 Post Divider Register (CCM_POST127) 32 R/W 0000_0000h 5.1.7.18/473
3038_BFA4 Post Divider Register (CCM_POST_ROOT127_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_BFA8 Post Divider Register (CCM_POST_ROOT127_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_BFAC Post Divider Register (CCM_POST_ROOT127_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_BFB0 Pre Divider Register (CCM_PRE127) 32 R/W 1000_0000h 5.1.7.22/485
3038_BFB4 Pre Divider Register (CCM_PRE_ROOT127_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_BFB8 Pre Divider Register (CCM_PRE_ROOT127_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_BFBC Pre Divider Register (CCM_PRE_ROOT127_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_BFF0 Access Control Register (CCM_ACCESS_CTRL127) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_BFF4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT127_SET)
Access Control Register
3038_BFF8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT127_CLR)
Access Control Register
3038_BFFC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT127_TOG)
3038_C000 Target Register (CCM_TARGET_ROOT128) 32 R/W 1000_0000h 5.1.7.10/461
3038_C004 Target Register (CCM_TARGET_ROOT128_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C008 Target Register (CCM_TARGET_ROOT128_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C00C Target Register (CCM_TARGET_ROOT128_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C010 Miscellaneous Register (CCM_MISC128) 32 R/W 0000_0000h 5.1.7.14/469
3038_C014 Miscellaneous Register (CCM_MISC_ROOT128_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C018 Miscellaneous Register (CCM_MISC_ROOT128_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C01C Miscellaneous Register (CCM_MISC_ROOT128_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C020 Post Divider Register (CCM_POST128) 32 R/W 0000_0000h 5.1.7.18/473
3038_C024 Post Divider Register (CCM_POST_ROOT128_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C028 Post Divider Register (CCM_POST_ROOT128_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C02C Post Divider Register (CCM_POST_ROOT128_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C030 Pre Divider Register (CCM_PRE128) 32 R/W 1000_0000h 5.1.7.22/485
3038_C034 Pre Divider Register (CCM_PRE_ROOT128_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C038 Pre Divider Register (CCM_PRE_ROOT128_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C03C Pre Divider Register (CCM_PRE_ROOT128_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C070 Access Control Register (CCM_ACCESS_CTRL128) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C074 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT128_SET)
Access Control Register
3038_C078 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT128_CLR)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 387
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_C07C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT128_TOG)
3038_C080 Target Register (CCM_TARGET_ROOT129) 32 R/W 1000_0000h 5.1.7.10/461
3038_C084 Target Register (CCM_TARGET_ROOT129_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C088 Target Register (CCM_TARGET_ROOT129_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C08C Target Register (CCM_TARGET_ROOT129_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C090 Miscellaneous Register (CCM_MISC129) 32 R/W 0000_0000h 5.1.7.14/469
3038_C094 Miscellaneous Register (CCM_MISC_ROOT129_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C098 Miscellaneous Register (CCM_MISC_ROOT129_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C09C Miscellaneous Register (CCM_MISC_ROOT129_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C0A0 Post Divider Register (CCM_POST129) 32 R/W 0000_0000h 5.1.7.18/473
3038_C0A4 Post Divider Register (CCM_POST_ROOT129_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C0A8 Post Divider Register (CCM_POST_ROOT129_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C0AC Post Divider Register (CCM_POST_ROOT129_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C0B0 Pre Divider Register (CCM_PRE129) 32 R/W 1000_0000h 5.1.7.22/485
3038_C0B4 Pre Divider Register (CCM_PRE_ROOT129_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C0B8 Pre Divider Register (CCM_PRE_ROOT129_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C0BC Pre Divider Register (CCM_PRE_ROOT129_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C0F0 Access Control Register (CCM_ACCESS_CTRL129) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C0F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT129_SET)
Access Control Register
3038_C0F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT129_CLR)
Access Control Register
3038_C0FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT129_TOG)
3038_C100 Target Register (CCM_TARGET_ROOT130) 32 R/W 1000_0000h 5.1.7.10/461
3038_C104 Target Register (CCM_TARGET_ROOT130_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C108 Target Register (CCM_TARGET_ROOT130_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C10C Target Register (CCM_TARGET_ROOT130_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C110 Miscellaneous Register (CCM_MISC130) 32 R/W 0000_0000h 5.1.7.14/469
3038_C114 Miscellaneous Register (CCM_MISC_ROOT130_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C118 Miscellaneous Register (CCM_MISC_ROOT130_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C11C Miscellaneous Register (CCM_MISC_ROOT130_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C120 Post Divider Register (CCM_POST130) 32 R/W 0000_0000h 5.1.7.18/473
3038_C124 Post Divider Register (CCM_POST_ROOT130_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C128 Post Divider Register (CCM_POST_ROOT130_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C12C Post Divider Register (CCM_POST_ROOT130_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C130 Pre Divider Register (CCM_PRE130) 32 R/W 1000_0000h 5.1.7.22/485
3038_C134 Pre Divider Register (CCM_PRE_ROOT130_SET) 32 R/W 0000_0000h 5.1.7.23/488
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
388 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_C138 Pre Divider Register (CCM_PRE_ROOT130_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C13C Pre Divider Register (CCM_PRE_ROOT130_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C170 Access Control Register (CCM_ACCESS_CTRL130) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C174 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT130_SET)
Access Control Register
3038_C178 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT130_CLR)
Access Control Register
3038_C17C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT130_TOG)
3038_C180 Target Register (CCM_TARGET_ROOT131) 32 R/W 1000_0000h 5.1.7.10/461
3038_C184 Target Register (CCM_TARGET_ROOT131_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C188 Target Register (CCM_TARGET_ROOT131_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C18C Target Register (CCM_TARGET_ROOT131_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C190 Miscellaneous Register (CCM_MISC131) 32 R/W 0000_0000h 5.1.7.14/469
3038_C194 Miscellaneous Register (CCM_MISC_ROOT131_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C198 Miscellaneous Register (CCM_MISC_ROOT131_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C19C Miscellaneous Register (CCM_MISC_ROOT131_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C1A0 Post Divider Register (CCM_POST131) 32 R/W 0000_0000h 5.1.7.18/473
3038_C1A4 Post Divider Register (CCM_POST_ROOT131_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C1A8 Post Divider Register (CCM_POST_ROOT131_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C1AC Post Divider Register (CCM_POST_ROOT131_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C1B0 Pre Divider Register (CCM_PRE131) 32 R/W 1000_0000h 5.1.7.22/485
3038_C1B4 Pre Divider Register (CCM_PRE_ROOT131_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C1B8 Pre Divider Register (CCM_PRE_ROOT131_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C1BC Pre Divider Register (CCM_PRE_ROOT131_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C1F0 Access Control Register (CCM_ACCESS_CTRL131) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C1F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT131_SET)
Access Control Register
3038_C1F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT131_CLR)
Access Control Register
3038_C1FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT131_TOG)
3038_C200 Target Register (CCM_TARGET_ROOT132) 32 R/W 1000_0000h 5.1.7.10/461
3038_C204 Target Register (CCM_TARGET_ROOT132_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C208 Target Register (CCM_TARGET_ROOT132_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C20C Target Register (CCM_TARGET_ROOT132_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C210 Miscellaneous Register (CCM_MISC132) 32 R/W 0000_0000h 5.1.7.14/469
3038_C214 Miscellaneous Register (CCM_MISC_ROOT132_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C218 Miscellaneous Register (CCM_MISC_ROOT132_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C21C Miscellaneous Register (CCM_MISC_ROOT132_TOG) 32 R/W 0000_0000h 5.1.7.17/472
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 389
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_C220 Post Divider Register (CCM_POST132) 32 R/W 0000_0000h 5.1.7.18/473
3038_C224 Post Divider Register (CCM_POST_ROOT132_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C228 Post Divider Register (CCM_POST_ROOT132_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C22C Post Divider Register (CCM_POST_ROOT132_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C230 Pre Divider Register (CCM_PRE132) 32 R/W 1000_0000h 5.1.7.22/485
3038_C234 Pre Divider Register (CCM_PRE_ROOT132_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C238 Pre Divider Register (CCM_PRE_ROOT132_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C23C Pre Divider Register (CCM_PRE_ROOT132_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C270 Access Control Register (CCM_ACCESS_CTRL132) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C274 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT132_SET)
Access Control Register
3038_C278 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT132_CLR)
Access Control Register
3038_C27C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT132_TOG)
3038_C280 Target Register (CCM_TARGET_ROOT133) 32 R/W 1000_0000h 5.1.7.10/461
3038_C284 Target Register (CCM_TARGET_ROOT133_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C288 Target Register (CCM_TARGET_ROOT133_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C28C Target Register (CCM_TARGET_ROOT133_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C290 Miscellaneous Register (CCM_MISC133) 32 R/W 0000_0000h 5.1.7.14/469
3038_C294 Miscellaneous Register (CCM_MISC_ROOT133_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C298 Miscellaneous Register (CCM_MISC_ROOT133_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C29C Miscellaneous Register (CCM_MISC_ROOT133_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C2A0 Post Divider Register (CCM_POST133) 32 R/W 0000_0000h 5.1.7.18/473
3038_C2A4 Post Divider Register (CCM_POST_ROOT133_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C2A8 Post Divider Register (CCM_POST_ROOT133_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C2AC Post Divider Register (CCM_POST_ROOT133_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C2B0 Pre Divider Register (CCM_PRE133) 32 R/W 1000_0000h 5.1.7.22/485
3038_C2B4 Pre Divider Register (CCM_PRE_ROOT133_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C2B8 Pre Divider Register (CCM_PRE_ROOT133_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C2BC Pre Divider Register (CCM_PRE_ROOT133_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C2F0 Access Control Register (CCM_ACCESS_CTRL133) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C2F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT133_SET)
Access Control Register
3038_C2F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT133_CLR)
Access Control Register
3038_C2FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT133_TOG)
3038_C300 Target Register (CCM_TARGET_ROOT134) 32 R/W 1000_0000h 5.1.7.10/461
3038_C304 Target Register (CCM_TARGET_ROOT134_SET) 32 R/W 0000_0000h 5.1.7.11/463
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
390 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_C308 Target Register (CCM_TARGET_ROOT134_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C30C Target Register (CCM_TARGET_ROOT134_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C310 Miscellaneous Register (CCM_MISC134) 32 R/W 0000_0000h 5.1.7.14/469
3038_C314 Miscellaneous Register (CCM_MISC_ROOT134_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C318 Miscellaneous Register (CCM_MISC_ROOT134_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C31C Miscellaneous Register (CCM_MISC_ROOT134_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C320 Post Divider Register (CCM_POST134) 32 R/W 0000_0000h 5.1.7.18/473
3038_C324 Post Divider Register (CCM_POST_ROOT134_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C328 Post Divider Register (CCM_POST_ROOT134_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C32C Post Divider Register (CCM_POST_ROOT134_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C330 Pre Divider Register (CCM_PRE134) 32 R/W 1000_0000h 5.1.7.22/485
3038_C334 Pre Divider Register (CCM_PRE_ROOT134_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C338 Pre Divider Register (CCM_PRE_ROOT134_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C33C Pre Divider Register (CCM_PRE_ROOT134_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C370 Access Control Register (CCM_ACCESS_CTRL134) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C374 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT134_SET)
Access Control Register
3038_C378 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT134_CLR)
Access Control Register
3038_C37C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT134_TOG)
3038_C380 Target Register (CCM_TARGET_ROOT135) 32 R/W 1000_0000h 5.1.7.10/461
3038_C384 Target Register (CCM_TARGET_ROOT135_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C388 Target Register (CCM_TARGET_ROOT135_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C38C Target Register (CCM_TARGET_ROOT135_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C390 Miscellaneous Register (CCM_MISC135) 32 R/W 0000_0000h 5.1.7.14/469
3038_C394 Miscellaneous Register (CCM_MISC_ROOT135_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C398 Miscellaneous Register (CCM_MISC_ROOT135_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C39C Miscellaneous Register (CCM_MISC_ROOT135_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C3A0 Post Divider Register (CCM_POST135) 32 R/W 0000_0000h 5.1.7.18/473
3038_C3A4 Post Divider Register (CCM_POST_ROOT135_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C3A8 Post Divider Register (CCM_POST_ROOT135_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C3AC Post Divider Register (CCM_POST_ROOT135_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C3B0 Pre Divider Register (CCM_PRE135) 32 R/W 1000_0000h 5.1.7.22/485
3038_C3B4 Pre Divider Register (CCM_PRE_ROOT135_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C3B8 Pre Divider Register (CCM_PRE_ROOT135_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C3BC Pre Divider Register (CCM_PRE_ROOT135_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C3F0 Access Control Register (CCM_ACCESS_CTRL135) 32 R/W 0000_0000h 5.1.7.26/497
Table continues on the next page...
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NXP Semiconductors 391
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_C3F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT135_SET)
Access Control Register
3038_C3F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT135_CLR)
Access Control Register
3038_C3FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT135_TOG)
3038_C400 Target Register (CCM_TARGET_ROOT136) 32 R/W 1000_0000h 5.1.7.10/461
3038_C404 Target Register (CCM_TARGET_ROOT136_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C408 Target Register (CCM_TARGET_ROOT136_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C40C Target Register (CCM_TARGET_ROOT136_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C410 Miscellaneous Register (CCM_MISC136) 32 R/W 0000_0000h 5.1.7.14/469
3038_C414 Miscellaneous Register (CCM_MISC_ROOT136_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C418 Miscellaneous Register (CCM_MISC_ROOT136_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C41C Miscellaneous Register (CCM_MISC_ROOT136_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C420 Post Divider Register (CCM_POST136) 32 R/W 0000_0000h 5.1.7.18/473
3038_C424 Post Divider Register (CCM_POST_ROOT136_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C428 Post Divider Register (CCM_POST_ROOT136_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C42C Post Divider Register (CCM_POST_ROOT136_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C430 Pre Divider Register (CCM_PRE136) 32 R/W 1000_0000h 5.1.7.22/485
3038_C434 Pre Divider Register (CCM_PRE_ROOT136_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C438 Pre Divider Register (CCM_PRE_ROOT136_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C43C Pre Divider Register (CCM_PRE_ROOT136_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C470 Access Control Register (CCM_ACCESS_CTRL136) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C474 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT136_SET)
Access Control Register
3038_C478 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT136_CLR)
Access Control Register
3038_C47C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT136_TOG)
3038_C480 Target Register (CCM_TARGET_ROOT137) 32 R/W 1000_0000h 5.1.7.10/461
3038_C484 Target Register (CCM_TARGET_ROOT137_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C488 Target Register (CCM_TARGET_ROOT137_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C48C Target Register (CCM_TARGET_ROOT137_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C490 Miscellaneous Register (CCM_MISC137) 32 R/W 0000_0000h 5.1.7.14/469
3038_C494 Miscellaneous Register (CCM_MISC_ROOT137_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C498 Miscellaneous Register (CCM_MISC_ROOT137_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C49C Miscellaneous Register (CCM_MISC_ROOT137_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C4A0 Post Divider Register (CCM_POST137) 32 R/W 0000_0000h 5.1.7.18/473
3038_C4A4 Post Divider Register (CCM_POST_ROOT137_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C4A8 Post Divider Register (CCM_POST_ROOT137_CLR) 32 R/W 0000_0000h 5.1.7.20/479
Table continues on the next page...
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Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_C4AC Post Divider Register (CCM_POST_ROOT137_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C4B0 Pre Divider Register (CCM_PRE137) 32 R/W 1000_0000h 5.1.7.22/485
3038_C4B4 Pre Divider Register (CCM_PRE_ROOT137_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C4B8 Pre Divider Register (CCM_PRE_ROOT137_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C4BC Pre Divider Register (CCM_PRE_ROOT137_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C4F0 Access Control Register (CCM_ACCESS_CTRL137) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C4F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT137_SET)
Access Control Register
3038_C4F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT137_CLR)
Access Control Register
3038_C4FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT137_TOG)
3038_C500 Target Register (CCM_TARGET_ROOT138) 32 R/W 1000_0000h 5.1.7.10/461
3038_C504 Target Register (CCM_TARGET_ROOT138_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C508 Target Register (CCM_TARGET_ROOT138_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C50C Target Register (CCM_TARGET_ROOT138_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C510 Miscellaneous Register (CCM_MISC138) 32 R/W 0000_0000h 5.1.7.14/469
3038_C514 Miscellaneous Register (CCM_MISC_ROOT138_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C518 Miscellaneous Register (CCM_MISC_ROOT138_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C51C Miscellaneous Register (CCM_MISC_ROOT138_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C520 Post Divider Register (CCM_POST138) 32 R/W 0000_0000h 5.1.7.18/473
3038_C524 Post Divider Register (CCM_POST_ROOT138_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C528 Post Divider Register (CCM_POST_ROOT138_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C52C Post Divider Register (CCM_POST_ROOT138_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C530 Pre Divider Register (CCM_PRE138) 32 R/W 1000_0000h 5.1.7.22/485
3038_C534 Pre Divider Register (CCM_PRE_ROOT138_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C538 Pre Divider Register (CCM_PRE_ROOT138_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C53C Pre Divider Register (CCM_PRE_ROOT138_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C570 Access Control Register (CCM_ACCESS_CTRL138) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C574 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT138_SET)
Access Control Register
3038_C578 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT138_CLR)
Access Control Register
3038_C57C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT138_TOG)
3038_C580 Target Register (CCM_TARGET_ROOT139) 32 R/W 1000_0000h 5.1.7.10/461
3038_C584 Target Register (CCM_TARGET_ROOT139_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C588 Target Register (CCM_TARGET_ROOT139_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C58C Target Register (CCM_TARGET_ROOT139_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C590 Miscellaneous Register (CCM_MISC139) 32 R/W 0000_0000h 5.1.7.14/469
Table continues on the next page...
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NXP Semiconductors 393
Clock Control Module (CCM)
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3038_C594 Miscellaneous Register (CCM_MISC_ROOT139_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C598 Miscellaneous Register (CCM_MISC_ROOT139_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C59C Miscellaneous Register (CCM_MISC_ROOT139_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C5A0 Post Divider Register (CCM_POST139) 32 R/W 0000_0000h 5.1.7.18/473
3038_C5A4 Post Divider Register (CCM_POST_ROOT139_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C5A8 Post Divider Register (CCM_POST_ROOT139_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C5AC Post Divider Register (CCM_POST_ROOT139_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C5B0 Pre Divider Register (CCM_PRE139) 32 R/W 1000_0000h 5.1.7.22/485
3038_C5B4 Pre Divider Register (CCM_PRE_ROOT139_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C5B8 Pre Divider Register (CCM_PRE_ROOT139_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C5BC Pre Divider Register (CCM_PRE_ROOT139_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C5F0 Access Control Register (CCM_ACCESS_CTRL139) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C5F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT139_SET)
Access Control Register
3038_C5F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT139_CLR)
Access Control Register
3038_C5FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT139_TOG)
3038_C600 Target Register (CCM_TARGET_ROOT140) 32 R/W 1000_0000h 5.1.7.10/461
3038_C604 Target Register (CCM_TARGET_ROOT140_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C608 Target Register (CCM_TARGET_ROOT140_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C60C Target Register (CCM_TARGET_ROOT140_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C610 Miscellaneous Register (CCM_MISC140) 32 R/W 0000_0000h 5.1.7.14/469
3038_C614 Miscellaneous Register (CCM_MISC_ROOT140_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C618 Miscellaneous Register (CCM_MISC_ROOT140_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C61C Miscellaneous Register (CCM_MISC_ROOT140_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C620 Post Divider Register (CCM_POST140) 32 R/W 0000_0000h 5.1.7.18/473
3038_C624 Post Divider Register (CCM_POST_ROOT140_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C628 Post Divider Register (CCM_POST_ROOT140_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C62C Post Divider Register (CCM_POST_ROOT140_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C630 Pre Divider Register (CCM_PRE140) 32 R/W 1000_0000h 5.1.7.22/485
3038_C634 Pre Divider Register (CCM_PRE_ROOT140_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C638 Pre Divider Register (CCM_PRE_ROOT140_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C63C Pre Divider Register (CCM_PRE_ROOT140_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C670 Access Control Register (CCM_ACCESS_CTRL140) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C674 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT140_SET)
Access Control Register
3038_C678 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT140_CLR)
Table continues on the next page...
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394 NXP Semiconductors
Chapter 5 Clocks and Power Management
CCM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Access Control Register
3038_C67C 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT140_TOG)
3038_C680 Target Register (CCM_TARGET_ROOT141) 32 R/W 1000_0000h 5.1.7.10/461
3038_C684 Target Register (CCM_TARGET_ROOT141_SET) 32 R/W 0000_0000h 5.1.7.11/463
3038_C688 Target Register (CCM_TARGET_ROOT141_CLR) 32 R/W 0000_0000h 5.1.7.12/465
3038_C68C Target Register (CCM_TARGET_ROOT141_TOG) 32 R/W 0000_0000h 5.1.7.13/467
3038_C690 Miscellaneous Register (CCM_MISC141) 32 R/W 0000_0000h 5.1.7.14/469
3038_C694 Miscellaneous Register (CCM_MISC_ROOT141_SET) 32 R/W 0000_0000h 5.1.7.15/470
3038_C698 Miscellaneous Register (CCM_MISC_ROOT141_CLR) 32 R/W 0000_0000h 5.1.7.16/471
3038_C69C Miscellaneous Register (CCM_MISC_ROOT141_TOG) 32 R/W 0000_0000h 5.1.7.17/472
3038_C6A0 Post Divider Register (CCM_POST141) 32 R/W 0000_0000h 5.1.7.18/473
3038_C6A4 Post Divider Register (CCM_POST_ROOT141_SET) 32 R/W 0000_0000h 5.1.7.19/476
3038_C6A8 Post Divider Register (CCM_POST_ROOT141_CLR) 32 R/W 0000_0000h 5.1.7.20/479
3038_C6AC Post Divider Register (CCM_POST_ROOT141_TOG) 32 R/W 0000_0000h 5.1.7.21/482
3038_C6B0 Pre Divider Register (CCM_PRE141) 32 R/W 1000_0000h 5.1.7.22/485
3038_C6B4 Pre Divider Register (CCM_PRE_ROOT141_SET) 32 R/W 0000_0000h 5.1.7.23/488
3038_C6B8 Pre Divider Register (CCM_PRE_ROOT141_CLR) 32 R/W 0000_0000h 5.1.7.24/491
3038_C6BC Pre Divider Register (CCM_PRE_ROOT141_TOG) 32 R/W 0000_0000h 5.1.7.25/494
3038_C6F0 Access Control Register (CCM_ACCESS_CTRL141) 32 R/W 0000_0000h 5.1.7.26/497
Access Control Register
3038_C6F4 32 R/W 0000_0000h 5.1.7.27/499
(CCM_ACCESS_CTRL_ROOT141_SET)
Access Control Register
3038_C6F8 32 R/W 0000_0000h 5.1.7.28/502
(CCM_ACCESS_CTRL_ROOT141_CLR)
Access Control Register
3038_C6FC 32 R/W 0000_0000h 5.1.7.29/505
(CCM_ACCESS_CTRL_ROOT141_TOG)
5.1.7.1 General Purpose Register (CCM_GPR0n)
GPR0
Address: 3038_0000h base + 0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GP0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_GPR0n field descriptions
Field Description
GP0 Timeout cycle count of ipg_clk, when perform read and write.
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Clock Control Module (CCM)
5.1.7.2 CCM PLL Control Register (CCM_PLL_CTRLn)
See Input Clocks for PLL control mapping.
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 800h offset + (16d × i), where i=0d to 38d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_PLL_CTRLn field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
Table continues on the next page...
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Chapter 5 Clocks and Power Management
CCM_PLL_CTRLn field descriptions (continued)
Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.3 CCM PLL Control Register (CCM_PLL_CTRLn_SET)
See Input Clocks for PLL control mapping.
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 804h offset + (16d × i), where i=0d to 38d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_PLL_CTRLn_SET field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
Table continues on the next page...
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Chapter 5 Clocks and Power Management
CCM_PLL_CTRLn_SET field descriptions (continued)
Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.4 CCM PLL Control Register (CCM_PLL_CTRLn_CLR)
See Input Clocks for PLL control mapping.
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 808h offset + (16d × i), where i=0d to 38d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_PLL_CTRLn_CLR field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
Table continues on the next page...
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Chapter 5 Clocks and Power Management
CCM_PLL_CTRLn_CLR field descriptions (continued)
Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.5 CCM PLL Control Register (CCM_PLL_CTRLn_TOG)
See Input Clocks for PLL control mapping.
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
Address: 3038_0000h base + 80Ch offset + (16d × i), where i=0d to 38d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_PLL_CTRLn_TOG field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
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Chapter 5 Clocks and Power Management
CCM_PLL_CTRLn_TOG field descriptions (continued)
Field Description
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
5.1.7.6 CCM Clock Gating Register (CCM_CCGRn)
NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
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Clock Control Module (CCM)
NOTE
Sec_debug clock gating (CCGR60) must be active in low
power mode. DO NOT gate this clock in low power mode to
guarantee the low power mode functions such as stop WDOG
counting.
Address: 3038_0000h base + 4000h offset + (16d × i), where i=0d to 191d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_CCGRn field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
11 This field is reserved.
- Reserved
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Chapter 5 Clocks and Power Management
CCM_CCGRn field descriptions (continued)
Field Description
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.7 CCM Clock Gating Register (CCM_CCGRn_SET)
NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 4004h offset + (16d × i), where i=0d to 191d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_CCGRn_SET field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Chapter 5 Clocks and Power Management
CCM_CCGRn_SET field descriptions (continued)
Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.8 CCM Clock Gating Register (CCM_CCGRn_CLR)
NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 4008h offset + (16d × i), where i=0d to 191d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_CCGRn_CLR field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Chapter 5 Clocks and Power Management
CCM_CCGRn_CLR field descriptions (continued)
Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.9 CCM Clock Gating Register (CCM_CCGRn_TOG)
NOTE
Not all CCGRs are mapped. See CCGR Interface for CCGR
mapping and clock gating information.
Address: 3038_0000h base + 400Ch offset + (16d × i), where i=0d to 191d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SETTING3 SETTING2 SETTING1 SETTING0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
CCM_CCGRn_TOG field descriptions
Field Description
31–16 This field is reserved.
- Reserved
15 This field is reserved.
- Reserved
14 This field is reserved.
- Reserved
13–12 Clock gate control setting for domain 3.
SETTING3
This field can only be written by domain 3
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Chapter 5 Clocks and Power Management
CCM_CCGRn_TOG field descriptions (continued)
Field Description
11 This field is reserved.
- Reserved
10 This field is reserved.
- Reserved
9–8 Clock gate control setting for domain 2.
SETTING2
This field can only be written by domain 2
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
7 This field is reserved.
- Reserved
6 This field is reserved.
- Reserved
5–4 Clock gate control setting for domain 1.
SETTING1
This field can only be written by domain 1.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
3 This field is reserved.
- Reserved
2 This field is reserved.
- Reserved
SETTING0 Clock gate control setting for domain 0.
This field can only be written by domain 0.
00 Domain clocks not needed
01 Domain clocks needed when in RUN
10 Domain clocks needed when in RUN and WAIT
11 Domain clocks needed all the time
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Clock Control Module (CCM)
5.1.7.10 Target Register (CCM_TARGET_ROOTn)
See Target Interface for more information.
NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8000h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
ENABLE
Reserved MUX Reserved PRE_PODF
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_TARGET_ROOTn field descriptions
Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE
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CCM_TARGET_ROOTn field descriptions (continued)
Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.11 Target Register (CCM_TARGET_ROOTn_SET)
See Target Interface for more information.
NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8004h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
ENABLE
Reserved MUX Reserved PRE_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_TARGET_ROOTn_SET field descriptions
Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE
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Chapter 5 Clocks and Power Management
CCM_TARGET_ROOTn_SET field descriptions (continued)
Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.12 Target Register (CCM_TARGET_ROOTn_CLR)
See Target Interface for more information.
NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 8008h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
ENABLE
Reserved MUX Reserved PRE_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_TARGET_ROOTn_CLR field descriptions
Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE
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Chapter 5 Clocks and Power Management
CCM_TARGET_ROOTn_CLR field descriptions (continued)
Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divider divide the number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.13 Target Register (CCM_TARGET_ROOTn_TOG)
See Target Interface for more information.
NOTE
See Clock Root Selects for clock root offsets and muxing
information.
Address: 3038_0000h base + 800Ch offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
ENABLE
Reserved MUX Reserved PRE_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_TARGET_ROOTn_TOG field descriptions
Field Description
31–29 This field is reserved.
- Reserved
28 Enable this clock
ENABLE
0 clock root is OFF
1 clock root is ON
27 This field is reserved.
- Reserved
26–24 Selection of clock sources
MUX
Please see Clock Root Selects for clock root offsets and muxing information.
This field is 1 bit long for DRAM and CORE
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CCM_TARGET_ROOTn_TOG field descriptions (continued)
Field Description
23–19 This field is reserved.
- Reserved
18–16 Pre divide divide number
PRE_PODF
Divider value is n+1
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15–6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1.
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 1 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.14 Miscellaneous Register (CCM_MISCn)
MISC
Address: 3038_0000h base + 8010h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTHEN_FAIL
R
TIMEOUT
VIOLATE
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_MISCn field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1
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5.1.7.15 Miscellaneous Register (CCM_MISC_ROOTn_SET)
Misc
Address: 3038_0000h base + 8014h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTHEN_FAIL
R
TIMEOUT
VIOLATE
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_MISC_ROOTn_SET field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1
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Clock Control Module (CCM)
5.1.7.16 Miscellaneous Register (CCM_MISC_ROOTn_CLR)
MISC
Address: 3038_0000h base + 8018h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTHEN_FAIL
R
TIMEOUT
VIOLATE
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_MISC_ROOTn_CLR field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1
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5.1.7.17 Miscellaneous Register (CCM_MISC_ROOTn_TOG)
MISC
Address: 3038_0000h base + 801Ch offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUTHEN_FAIL
R
TIMEOUT
VIOLATE
Reserved Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_MISC_ROOTn_TOG field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 This sticky bit reflects access violation in normal interface of this clock.
VIOLATE
This bit has internal 4 bits, one for each domain.
Violation from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
7–5 This field is reserved.
- Reserved
4 This sticky bit reflects time out happened during accessing this clock.
TIMEOUT
This bit has internal 4 bits, one for each domain.
Timeout from other domain is not visible or clearable.
This file is cleared to 0 while write 1.
3–1 This field is reserved.
- Reserved
0 This sticky bit reflects access restricted by access control of this clock.
AUTHEN_FAIL
This bit has internal 4 bits, one for each domain.
Authentic fail from other domain is not visible or clearable.
This file is cleared to 0 while write 1
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Clock Control Module (CCM)
5.1.7.18 Post Divider Register (CCM_POSTn)
Post Register
Address: 3038_0000h base + 8020h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2
R
SELECT
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
R
Reserved
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_POSTn field descriptions
Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice
0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1
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Clock Control Module (CCM)
CCM_POSTn field descriptions (continued)
Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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5.1.7.19 Post Divider Register (CCM_POST_ROOTn_SET)
Post Divider Register
Address: 3038_0000h base + 8024h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2
R
SELECT
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
R
Reserved
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_POST_ROOTn_SET field descriptions
Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice
0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1
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CCM_POST_ROOTn_SET field descriptions (continued)
Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.20 Post Divider Register (CCM_POST_ROOTn_CLR)
Post Root Register
Address: 3038_0000h base + 8028h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2
R
SELECT
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
R
Reserved
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_POST_ROOTn_CLR field descriptions
Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice
0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide the number
Divider value is n + 1
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Clock Control Module (CCM)
CCM_POST_ROOTn_CLR field descriptions (continued)
Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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5.1.7.21 Post Divider Register (CCM_POST_ROOTn_TOG)
Post Root Register
Address: 3038_0000h base + 802Ch offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY2
R
SELECT
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
R
Reserved
Reserved POST_PODF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_POST_ROOTn_TOG field descriptions
Field Description
31 Clock switching multiplexer is applying new setting
BUSY2
30–29 This field is reserved.
- Reserved
28 Selection of post clock branches
SELECT
This field is not applicable to Peripheral (IP) Clock Slice, see Peripheral clock slice Peripheral clock slice
0 select branch A
1 select branch B
27–8 This field is reserved.
- Reserved
7 Post divider is applying new set value
BUSY1
6 This field is reserved.
- Reserved
POST_PODF Post divider divide number
Divider value is n + 1
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CCM_POST_ROOTn_TOG field descriptions (continued)
Field Description
For CORE, this field is 3 bit long.
For Peripheral (IP), this field is 2 bit long.
This field does not apply to DRAM_PHYM
000000 Divide by 1
000001 Divide by 2
000010 Divide by 3
000011 Divide by 4
000100 Divide by 5
000101 Divide by 6
:
111111 Divide by 64
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Clock Control Module (CCM)
5.1.7.22 Pre Divider Register (CCM_PREn)
Pre Register
Address: 3038_0000h base + 8030h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4
BUSY3
R
Reserved
EN_A
Reserved MUX_A Reserved PRE_PODF_A
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
BUSY0
R
Reserved
EN_B
Reserved MUX_B Reserved PRE_PODF_B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_PREn field descriptions
Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM
0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM
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Clock Control Module (CCM)
CCM_PREn field descriptions (continued)
Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch a is applying
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
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5.1.7.23 Pre Divider Register (CCM_PRE_ROOTn_SET)
Pre Divider Register
Address: 3038_0000h base + 8034h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4
BUSY3
R
Reserved
EN_A
Reserved MUX_A Reserved PRE_PODF_A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
BUSY0
R
Reserved
EN_B
Reserved MUX_B Reserved PRE_PODF_B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_PRE_ROOTn_SET field descriptions
Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM
0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM
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CCM_PRE_ROOTn_SET field descriptions (continued)
Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch A is applying
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
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Clock Control Module (CCM)
5.1.7.24 Pre Divider Register (CCM_PRE_ROOTn_CLR)
Pree Root Register
Address: 3038_0000h base + 8038h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4
BUSY3
R
Reserved
EN_A
Reserved MUX_A Reserved PRE_PODF_A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
BUSY0
R
Reserved
EN_B
Reserved MUX_B Reserved PRE_PODF_B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_PRE_ROOTn_CLR field descriptions
Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM
0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM
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Clock Control Module (CCM)
CCM_PRE_ROOTn_CLR field descriptions (continued)
Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch A is applied
BUSY0
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
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5.1.7.25 Pre Divider Register (CCM_PRE_ROOTn_TOG)
Pre Root Register
Address: 3038_0000h base + 803Ch offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BUSY4
BUSY3
R
Reserved
EN_A
Reserved MUX_A Reserved PRE_PODF_A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY1
BUSY0
R
Reserved
EN_B
Reserved MUX_B Reserved PRE_PODF_B
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_PRE_ROOTn_TOG field descriptions
Field Description
31 EN_A field is applied to field
BUSY4
This field applies to DRAM and DRAM_PHYM
30–29 This field is reserved.
- Reserved
28 Branch A clock gate control
EN_A
This field applies to DRAM and DRAM_PHYM
0 Clock shutdown
1 clock ON
27 This field is reserved.
- Reserved
26–24 Selection control of multiplexer of branch A
MUX_A
This field applies to DRAM and DRAM_PHYM
23–20 This field is reserved.
- Reserved
19 Pre divider value for branch A is applied
BUSY3
This field applies to DRAM and DRAM_PHYM
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CCM_PRE_ROOTn_TOG field descriptions (continued)
Field Description
18–16 Pre divider divide number for branch A
PRE_PODF_A
Divider value is n + 1.
This field does not apply for CORE, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
15 EN_B is applied to field
BUSY1
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
14–13 This field is reserved.
- Reserved
12 Branch B clock gate control
EN_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
0 Clock shutdown
1 Clock ON
11 This field is reserved.
- Reserved
10–8 Selection control of multiplexer of branch B
MUX_B
This field does not apply for CORE, IP,DRAM, DRAM_PHYM
7–4 This field is reserved.
- Reserved
3 Pre divider value for branch a is applied
BUSY0
field does not apply for CORE, IP,DRAM, DRAM_PHYM
PRE_PODF_B Pre divider divide number for branch B
Divider value is n + 1.
This field does not apply for CORE, IP, DRAM, DRAM_PHYM
000 Divide by 1
001 Divide by 2
010 Divide by 3
011 Divide by 4
100 Divide by 5
101 Divide by 6
110 Divide by 7
111 Divide by 8
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Clock Control Module (CCM)
5.1.7.26 Access Control Register (CCM_ACCESS_CTRLn)
Access Control Register
Address: 3038_0000h base + 8070h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OWNER_ID
DOMAIN3_WHITELIST
DOMAIN2_WHITELIST
DOMAIN1_WHITELIST
DOMAIN0_WHITELIST
SEMA_EN
MUTEX
LOCK
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ACCESS_CTRLn field descriptions
Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.
0 Access control inactive
1 Access control active
30–29 This field is reserved.
- Reserved
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CCM_ACCESS_CTRLn field descriptions (continued)
Field Description
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1
0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0
0 domaino
1 domain1
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
Table continues on the next page...
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Clock Control Module (CCM)
CCM_ACCESS_CTRLn field descriptions (continued)
Field Description
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0
5.1.7.27 Access Control Register
(CCM_ACCESS_CTRL_ROOTn_SET)
Access Control Register
Address: 3038_0000h base + 8074h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OWNER_ID
DOMAIN3_WHITELIST
DOMAIN2_WHITELIST
DOMAIN1_WHITELIST
DOMAIN0_WHITELIST
SEMA_EN
MUTEX
LOCK
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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CCM_ACCESS_CTRL_ROOTn_SET field descriptions
Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.
0 Access control inactive
1 Access control active
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1
0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0
0 domaino
1 domain1
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Clock Control Module (CCM)
CCM_ACCESS_CTRL_ROOTn_SET field descriptions (continued)
Field Description
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0
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5.1.7.28 Access Control Register
(CCM_ACCESS_CTRL_ROOTn_CLR)
Access Control Register
Address: 3038_0000h base + 8078h offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OWNER_ID
DOMAIN3_WHITELIST
DOMAIN2_WHITELIST
DOMAIN1_WHITELIST
DOMAIN0_WHITELIST
SEMA_EN
MUTEX
LOCK
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ACCESS_CTRL_ROOTn_CLR field descriptions
Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.
0 Access control inactive
1 Access control active
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Clock Control Module (CCM)
CCM_ACCESS_CTRL_ROOTn_CLR field descriptions (continued)
Field Description
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1
0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0
0 domaino
1 domain1
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
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CCM_ACCESS_CTRL_ROOTn_CLR field descriptions (continued)
Field Description
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0
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5.1.7.29 Access Control Register
(CCM_ACCESS_CTRL_ROOTn_TOG)
Access Control Register
Address: 3038_0000h base + 807Ch offset + (128d × i), where i=0d to 141d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R OWNER_ID
DOMAIN3_WHITELIST
DOMAIN2_WHITELIST
DOMAIN1_WHITELIST
DOMAIN0_WHITELIST
SEMA_EN
MUTEX
LOCK
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOMAIN3_INFO DOMAIN2_INFO DOMAIN1_INFO DOMAIN0_INFO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ACCESS_CTRL_ROOTn_TOG field descriptions
Field Description
31 Lock this clock root to use access control
LOCK
This bit can be set to 1 by software, and can be cleared only by system reset.
0 Access control inactive
1 Access control active
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Chapter 5 Clocks and Power Management
CCM_ACCESS_CTRL_ROOTn_TOG field descriptions (continued)
Field Description
30–29 This field is reserved.
- Reserved
28 Enable internal semaphore
SEMA_EN
This field cannot be changed when lock bit is 1
0 Disable
1 Enable
27 White list of domains that can change setting of this clock root.
DOMAIN3_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
26 White list of domains that can change setting of this clock root.
DOMAIN2_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
25 White list of domains that can change setting of this clock root.
DOMAIN1_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
24 White list of domains that can change setting of this clock root.
DOMAIN0_
Each domain has a corresponding bit.
WHITELIST
0 Domain cannot change the setting
1 Domain can change the setting
23–21 This field is reserved.
- Reserved
20 Semaphore to control access
MUTEX
0 Semaphore is free to take
1 Semaphore is taken
Write 0 Release semaphore
Write 1 Acquire semaphore
19–18 This field is reserved.
- Reserved
17–16 Current domain that owns semaphore
OWNER_ID
This field is meaningless when MUTEX is 0
0 domaino
1 domain1
2 domain2
3 domain3
15–12 Information from domain 3 to pass to others
DOMAIN3_INFO
This field can only be changed by domain 3
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Clock Control Module (CCM)
CCM_ACCESS_CTRL_ROOTn_TOG field descriptions (continued)
Field Description
11–8 Information from domain 2 to pass to others
DOMAIN2_INFO
This field can only be changed by domain 2
7–4 Information from domain 1 to pass to others
DOMAIN1_INFO
This field can only be changed by domain 1
DOMAIN0_INFO Information from domain 0 to pass to others
This field can only be changed by domain 0
5.1.8 CCM Analog Memory Map/Register Definition
CCM_ANALOG memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
AUDIO PLL1 General Function Control Register
3036_0000 32 R/W 0000_2010h 5.1.8.1/510
(CCM_ANALOG_AUDIO_PLL1_GEN_CTRL)
AUDIO PLL1 Divide and Fraction Data Control 0 Register
3036_0004 32 R/W 0014_5032h 5.1.8.2/512
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0)
AUDIO PLL1 Divide and Fraction Data Control 1 Register
3036_0008 32 R/W 0000_0000h 5.1.8.3/513
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1)
AUDIO PLL1 PLL SSCG Control Register
3036_000C 32 R/W 0000_0000h 5.1.8.4/513
(CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL)
AUDIO PLL1 PLL Monitoring Control Register
3036_0010 32 R/W 0010_0103h 5.1.8.5/515
(CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL)
AUDIO PLL2 General Function Control Register
3036_0014 32 R/W 0000_2010h 5.1.8.6/517
(CCM_ANALOG_AUDIO_PLL2_GEN_CTRL)
AUDIO PLL2 Divide and Fraction Data Control 0 Register
3036_0018 32 R/W 0014_5032h 5.1.8.7/519
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0)
AUDIO PLL2 Divide and Fraction Data Control 1 Register
3036_001C 32 R/W 0000_0000h 5.1.8.8/520
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1)
AUDIO PLL2 PLL SSCG Control Register
3036_0020 32 R/W 0000_0000h 5.1.8.9/520
(CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL)
AUDIO PLL2 PLL Monitoring Control Register
3036_0024 32 R/W 0010_0103h 5.1.8.10/522
(CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL)
VIDEO PLL1 General Function Control Register
3036_0028 32 R/W 0000_2010h 5.1.8.11/524
(CCM_ANALOG_VIDEO_PLL1_GEN_CTRL)
VIDEO PLL1 Divide and Fraction Data Control 0 Register
3036_002C 32 R/W 0014_5032h 5.1.8.12/526
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0)
VIDEO PLL1 Divide and Fraction Data Control 1 Register
3036_0030 32 R/W 0000_0000h 5.1.8.13/527
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1)
VIDEO PLL1 PLL SSCG Control Register
3036_0034 32 R/W 0000_0000h 5.1.8.14/527
(CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL)
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CCM_ANALOG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
VIDEO PLL1 PLL Monitoring Control Register
3036_0038 32 R/W 0010_0103h 5.1.8.15/529
(CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL)
DRAM PLL General Function Control Register
3036_0050 32 R/W 0000_2010h 5.1.8.16/531
(CCM_ANALOG_DRAM_PLL_GEN_CTRL)
DRAM PLL Divide and Fraction Data Control 0 Register
3036_0054 32 R/W 0012_C032h 5.1.8.17/533
(CCM_ANALOG_DRAM_PLL_FDIV_CTL0)
DRAM PLL Divide and Fraction Data Control 1 Register
3036_0058 32 R/W 0000_0000h 5.1.8.18/534
(CCM_ANALOG_DRAM_PLL_FDIV_CTL1)
DRAM PLL PLL SSCG Control Register
3036_005C 32 R/W 0000_0000h 5.1.8.19/534
(CCM_ANALOG_DRAM_PLL_SSCG_CTRL)
DRAM PLL PLL Monitoring Control Register
3036_0060 32 R/W 0010_0103h 5.1.8.20/536
(CCM_ANALOG_DRAM_PLL_MNIT_CTRL)
GPU PLL General Function Control Register
3036_0064 32 R/W 0000_0810h 5.1.8.21/538
(CCM_ANALOG_GPU_PLL_GEN_CTRL)
GPU PLL Divide and Fraction Data Control 0 Register
3036_0068 32 R/W 000C_8031h 5.1.8.22/540
(CCM_ANALOG_GPU_PLL_FDIV_CTL0)
PLL Lock Detector Control Register
3036_006C 32 R/W 0010_003Fh 5.1.8.23/541
(CCM_ANALOG_GPU_PLL_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0070 32 R/W 0028_0081h 5.1.8.24/542
(CCM_ANALOG_GPU_PLL_MNIT_CTRL)
VPU PLL General Function Control Register
3036_0074 32 R/W 0000_0810h 5.1.8.25/544
(CCM_ANALOG_VPU_PLL_GEN_CTRL)
VPU PLL Divide and Fraction Data Control 0 Register
3036_0078 32 R/W 0012_C032h 5.1.8.26/546
(CCM_ANALOG_VPU_PLL_FDIV_CTL0)
PLL Lock Detector Control Register
3036_007C 32 R/W 0010_003Fh 5.1.8.23/541
(CCM_ANALOG_VPU_PLL_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0080 32 R/W 0028_0081h 5.1.8.24/542
(CCM_ANALOG_VPU_PLL_MNIT_CTRL)
ARM PLL General Function Control Register
3036_0084 32 R/W 0000_0810h 5.1.8.27/548
(CCM_ANALOG_ARM_PLL_GEN_CTRL)
ARM PLL Divide and Fraction Data Control 0 Register
3036_0088 32 R/W 000F_A031h 5.1.8.28/550
(CCM_ANALOG_ARM_PLL_FDIV_CTL0)
PLL Lock Detector Control Register
3036_008C 32 R/W 0010_003Fh 5.1.8.23/541
(CCM_ANALOG_ARM_PLL_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0090 32 R/W 0028_0081h 5.1.8.24/542
(CCM_ANALOG_ARM_PLL_MNIT_CTRL)
SYS PLL1 General Function Control Register
3036_0094 32 R/W 0AAA_A810h 5.1.8.29/552
(CCM_ANALOG_SYS_PLL1_GEN_CTRL)
SYS PLL1 Divide and Fraction Data Control 0 Register
3036_0098 32 R/W 0019_0032h 5.1.8.30/555
(CCM_ANALOG_SYS_PLL1_FDIV_CTL0)
PLL Lock Detector Control Register
3036_009C 32 R/W 0010_003Fh 5.1.8.23/541
(CCM_ANALOG_SYS_PLL1_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0100 32 R/W 0028_0081h 5.1.8.31/556
(CCM_ANALOG_SYS_PLL1_MNIT_CTRL)
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Clock Control Module (CCM)
CCM_ANALOG memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SYS PLL2 General Function Control Register
3036_0104 32 R/W 0AAA_A810h 5.1.8.32/558
(CCM_ANALOG_SYS_PLL2_GEN_CTRL)
SYS PLL2 Divide and Fraction Data Control 0 Register
3036_0108 32 R/W 000F_A031h 5.1.8.33/561
(CCM_ANALOG_SYS_PLL2_FDIV_CTL0)
PLL Lock Detector Control Register
3036_010C 32 R/W 0010_003Fh 5.1.8.34/562
(CCM_ANALOG_SYS_PLL2_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0110 32 R/W 0028_0081h 5.1.8.31/556
(CCM_ANALOG_SYS_PLL2_MNIT_CTRL)
SYS PLL3 General Function Control Register
3036_0114 32 R/W 0000_0810h 5.1.8.35/564
(CCM_ANALOG_SYS_PLL3_GEN_CTRL)
SYS PLL3 Divide and Fraction Data Control 0 Register
3036_0118 32 R/W 000F_A031h 5.1.8.36/566
(CCM_ANALOG_SYS_PLL3_FDIV_CTL0)
PLL Lock Detector Control Register
3036_011C 32 R/W 0010_003Fh 5.1.8.34/562
(CCM_ANALOG_SYS_PLL3_LOCKD_CTRL)
PLL Monitoring Control Register
3036_0120 32 R/W 0028_0081h 5.1.8.31/556
(CCM_ANALOG_SYS_PLL3_MNIT_CTRL)
Osc Misc Configuration Register
3036_0124 32 R/W 0000_0000h 5.1.8.37/567
(CCM_ANALOG_OSC_MISC_CFG)
PLL Clock Output for Test Enable and Select Register
3036_0128 32 R/W 0000_0000h 5.1.8.38/568
(CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)
3036_0800 DIGPROG Register (CCM_ANALOG_DIGPROG) 32 R 0082_4010h 5.1.8.39/570
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5.1.8.1 AUDIO PLL1 General Function Control Register
(CCM_ANALOG_AUDIO_PLL1_GEN_CTRL)
AUDIO PLL1 General Function Control Register
Address: 3036_0000h base + 0h offset = 3036_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_EXT_BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
R
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
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CCM_ANALOG_AUDIO_PLL1_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
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5.1.8.2 AUDIO PLL1 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0)
AUDIO PLL1 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 4h offset = 3036_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0
CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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Clock Control Module (CCM)
5.1.8.3 AUDIO PLL1 Divide and Fraction Data Control 1 Register
(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1)
AUDIO PLL1 Divide and Fraction Data Control 1 Register
Address: 3036_0000h base + 8h offset = 3036_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM
5.1.8.4 AUDIO PLL1 PLL SSCG Control Register
(CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL)
AUDIO PLL1 PLL SSCG Control Register
Address: 3036_0000h base + Ch offset = 3036_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN
Reserved PLL_MFREQ_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL field descriptions
Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control
00 Down spread
01 Up spread
1x Center spread
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Clock Control Module (CCM)
5.1.8.5 AUDIO PLL1 PLL Monitoring Control Register
(CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL)
AUDIO PLL1 PLL Monitoring Control Register
Address: 3036_0000h base + 10h offset = 3036_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
PBIAS_CTRL
AFC_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL field descriptions
Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
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CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL field descriptions (continued)
Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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Clock Control Module (CCM)
5.1.8.6 AUDIO PLL2 General Function Control Register
(CCM_ANALOG_AUDIO_PLL2_GEN_CTRL)
AUDIO PLL2 General Function Control Register
Address: 3036_0000h base + 14h offset = 3036_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_EXT_BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
R
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
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CCM_ANALOG_AUDIO_PLL2_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
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5.1.8.7 AUDIO PLL2 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0)
AUDIO PLL2 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 18h offset = 3036_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0
CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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5.1.8.8 AUDIO PLL2 Divide and Fraction Data Control 1 Register
(CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1)
AUDIO PLL2 Divide and Fraction Data Control 1 Register
Address: 3036_0000h base + 1Ch offset = 3036_001Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM
5.1.8.9 AUDIO PLL2 PLL SSCG Control Register
(CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL)
AUDIO PLL2 PLL SSCG Control Register
Address: 3036_0000h base + 20h offset = 3036_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN
Reserved PLL_MFREQ_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL field descriptions
Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control
00 Down spread
01 Up spread
1x Center spread
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5.1.8.10 AUDIO PLL2 PLL Monitoring Control Register
(CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL)
AUDIO PLL2 PLL Monitoring Control Register
Address: 3036_0000h base + 24h offset = 3036_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
PBIAS_CTRL
AFC_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL field descriptions
Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...
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Clock Control Module (CCM)
CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL field descriptions (continued)
Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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5.1.8.11 VIDEO PLL1 General Function Control Register
(CCM_ANALOG_VIDEO_PLL1_GEN_CTRL)
VIDEO PLL1 General Function Control Register
Address: 3036_0000h base + 28h offset = 3036_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_EXT_BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
R
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
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Clock Control Module (CCM)
CCM_ANALOG_VIDEO_PLL1_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
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5.1.8.12 VIDEO PLL1 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0)
VIDEO PLL1 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 2Ch offset = 3036_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0
CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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Clock Control Module (CCM)
5.1.8.13 VIDEO PLL1 Divide and Fraction Data Control 1 Register
(CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1)
VIDEO PLL1 Divide and Fraction Data Control 1 Register
Address: 3036_0000h base + 30h offset = 3036_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM
5.1.8.14 VIDEO PLL1 PLL SSCG Control Register
(CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL)
VIDEO PLL1 PLL SSCG Control Register
Address: 3036_0000h base + 34h offset = 3036_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN
Reserved PLL_MFREQ_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL field descriptions
Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(2^5) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr x mrr /m /(2^6) x 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control
00 Down spread
01 Up spread
1x Center spread
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Clock Control Module (CCM)
5.1.8.15 VIDEO PLL1 PLL Monitoring Control Register
(CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL)
VIDEO PLL1 PLL Monitoring Control Register
Address: 3036_0000h base + 38h offset = 3036_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
PBIAS_CTRL
AFC_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL field descriptions
Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50*VDD
1 0.67*VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...
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CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL field descriptions (continued)
Field Description
0 nominal delay
1 nominal delay * 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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Clock Control Module (CCM)
5.1.8.16 DRAM PLL General Function Control Register
(CCM_ANALOG_DRAM_PLL_GEN_CTRL)
DRAM PLL General Function Control Register
Address: 3036_0000h base + 50h offset = 3036_0050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_EXT_BYPASS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
R
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0
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CCM_ANALOG_DRAM_PLL_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30–17 This field is reserved.
- Reserved
16 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
15–14 This field is reserved.
- Reserved
13 PLL output clock clock gating enable
PLL_CLKE
12 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
11–10 This field is reserved.
- Reserved
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
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5.1.8.17 DRAM PLL Divide and Fraction Data Control 0 Register
(CCM_ANALOG_DRAM_PLL_FDIV_CTL0)
DRAM PLL Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 54h offset = 3036_0054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0
CCM_ANALOG_DRAM_PLL_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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5.1.8.18 DRAM PLL Divide and Fraction Data Control 1 Register
(CCM_ANALOG_DRAM_PLL_FDIV_CTL1)
DRAM PLL Divide and Fraction Data Control 1 Register
Address: 3036_0000h base + 58h offset = 3036_0058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved PLL_DSM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_DRAM_PLL_FDIV_CTL1 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
PLL_DSM Value of the DSM
5.1.8.19 DRAM PLL PLL SSCG Control Register
(CCM_ANALOG_DRAM_PLL_SSCG_CTRL)
DRAM PLL PLL SSCG Control Register
Address: 3036_0000h base + 5Ch offset = 3036_005Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSCG_EN
Reserved PLL_MFREQ_CTL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_MFREQ_CTL Reserved PLL_MRAT_CTL Reserved SEL_PF
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
CCM_ANALOG_DRAM_PLL_SSCG_CTRL field descriptions
Field Description
31 SSCG Enable
SSCG_EN
1 Enable Spread Spectrum Mode
0 Disable Spread Spectrum Mode
30–20 This field is reserved.
- Reserved
19–12 Value of modulation frequency control
PLL_MFREQ_
Modulation Frequency, MF is determined by the following equation:
CTL
MF = FFIN/p/mfr/(25) Hz
FFIN is the PLL input clock frequency, mfr is the decimal value for PLL_MFREQ_CTL[7:0], and p is the
decimal value for PLL_PRE_DIV.
11–10 This field is reserved.
- Reserved
9–4 Value of modulation rate control
PLL_MRAT_CTL
Modulation rate (pk-pk), MR, is determined by the following equation:
MR = mfr × mrr / m / f(26) × 100 [%]
mfr is the decimal value of PLL_MFREQ_CTL, mrr is the decimal value for PLL_MRAT_CTL[5:0], and m is
the decimal of PLL_MAIN_DIV.
3–2 This field is reserved.
- Reserved
SEL_PF Value of modulation method control
00 Down spread
01 Up spread
1x Center spread
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5.1.8.20 DRAM PLL PLL Monitoring Control Register
(CCM_ANALOG_DRAM_PLL_MNIT_CTRL)
DRAM PLL PLL Monitoring Control Register
Address: 3036_0000h base + 60h offset = 3036_0060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
PBIAS_CTRL
AFC_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
CCM_ANALOG_DRAM_PLL_MNIT_CTRL field descriptions
Field Description
31–21 This field is reserved.
- Reserved
20 AFC Mode select
AFC_SEL
19 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50 × VDD
1 0.67 × VDD
18 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
17 AFC initial delay select pin
AFCINIT_SEL
Table continues on the next page...
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Clock Control Module (CCM)
CCM_ANALOG_DRAM_PLL_MNIT_CTRL field descriptions (continued)
Field Description
0 nominal delay
1 nominal delay × 2
16 This field is reserved.
- Reserved
15 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
14 FEED_OUT enable pin
FEED_EN
13–9 This field is reserved.
- Reserved
8–4 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
3 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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5.1.8.21 GPU PLL General Function Control Register
(CCM_ANALOG_GPU_PLL_GEN_CTRL)
GPU PLL General Function Control Register
Address: 3036_0000h base + 64h offset = 3036_0064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_GPU_PLL_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
Table continues on the next page...
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CCM_ANALOG_GPU_PLL_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.22 GPU PLL Divide and Fraction Data Control 0 Register
(CCM_ANALOG_GPU_PLL_FDIV_CTL0)
GPU PLL Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 68h offset = 3036_0068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1
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CCM_ANALOG_GPU_PLL_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
5.1.8.23 PLL Lock Detector Control Register
(CCM_ANALOG_nLOCKD_CTRL)
PLL Lock Detector Control Register
Address: 3036_0000h base + 6Ch offset + (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CON_
R
LOCK_CON_ LOCK_CON_
Reserved IN
DLY OUT
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
CCM_ANALOG_nLOCKD_CTRL field descriptions
Field Description
31–6 This field is reserved.
- Reserved
5–4 Lock detector setting of the detection resolution
LOCK_CON_
DLY
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CCM_ANALOG_nLOCKD_CTRL field descriptions (continued)
Field Description
3–2 Lock detector setting of the output margin
LOCK_CON_
OUT
LOCK_CON_IN Lock detector setting of the input margin
5.1.8.24 PLL Monitoring Control Register
(CCM_ANALOG_nMNIT_CTRL)
PLL Monitoring Control Register
Address: 3036_0000h base + 70h offset + (16d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
FOUT_MASK
PBIAS_CTRL
AFC_SEL
LRD_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
Reserved
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
CCM_ANALOG_nMNIT_CTRL field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21 Monitoring pin. AFC operation mode select pin
LRD_EN
20 Scaler's re-initialization time control pin[3]
FOUT_MASK
Table continues on the next page...
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CCM_ANALOG_nMNIT_CTRL field descriptions (continued)
Field Description
19 AFC Mode select
AFC_SEL
18 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50 × VDD
1 0.67 × VDD
17 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
16 AFC initial delay select pin
AFCINIT_SEL
0 nominal delay
1 nominal delay × 2
15 This field is reserved.
- Reserved
14 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
13 FEED_OUT enable pin
FEED_EN
12–8 This field is reserved.
- Reserved
7–3 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
2 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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5.1.8.25 VPU PLL General Function Control Register
(CCM_ANALOG_VPU_PLL_GEN_CTRL)
VPU PLL General Function Control Register
Address: 3036_0000h base + 74h offset = 3036_0074h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_VPU_PLL_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
Table continues on the next page...
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CCM_ANALOG_VPU_PLL_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.26 VPU PLL Divide and Fraction Data Control 0 Register
(CCM_ANALOG_VPU_PLL_FDIV_CTL0)
VPU PLL Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 78h offset = 3036_0078h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0
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Clock Control Module (CCM)
CCM_ANALOG_VPU_PLL_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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5.1.8.27 ARM PLL General Function Control Register
(CCM_ANALOG_ARM_PLL_GEN_CTRL)
ARM PLL General Function Control Register
Address: 3036_0000h base + 84h offset = 3036_0084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Clock Control Module (CCM)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_ARM_PLL_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
Table continues on the next page...
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CCM_ANALOG_ARM_PLL_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.28 ARM PLL Divide and Fraction Data Control 0 Register
(CCM_ANALOG_ARM_PLL_FDIV_CTL0)
ARM PLL Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 88h offset = 3036_0088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1
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Clock Control Module (CCM)
CCM_ANALOG_ARM_PLL_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
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5.1.8.29 SYS PLL1 General Function Control Register
(CCM_ANALOG_SYS_PLL1_GEN_CTRL)
SYS PLL1 General Function Control Register
Address: 3036_0000h base + 94h offset = 3036_0094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_DIV20_CLKE_OVERRIDE
PLL_DIV10_CLKE_OVERRIDE
PLL_DIV8_CLKE_OVERRIDE
PLL_DIV6_CLKE_OVERRIDE
PLL_DIV5_CLKE_OVERRIDE
PLL_DIV4_CLKE_OVERRIDE
R
PLL_EXT_BYPASS
PLL_DIV20_CLKE
PLL_DIV10_CLKE
PLL_DIV8_CLKE
PLL_DIV6_CLKE
PLL_DIV5_CLKE
PLL_DIV4_CLKE
PLL_LOCK_SEL
Reserved
Reset 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PLL_DIV3_CLKE_OVERRIDE
PLL_DIV2_CLKE_OVERRIDE
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_DIV3_CLKE
PLL_DIV2_CLKE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved
RST SEL CLK_SEL
Reset 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27 PLL clock divided by 20 output gating enable
PLL_DIV20_
CLKE
26 PLL clock divided by 20 output gating enable overrided by CCM
PLL_DIV20_
CLKE_
OVERRIDE
25 PLL clock divided by 10 output gating enable
PLL_DIV10_
CLKE
24 PLL clock divided by 10 output gating enable overrided by CCM
PLL_DIV10_
CLKE_
OVERRIDE
23 PLL clock divided by 8 output gating enable
PLL_DIV8_CLKE
Table continues on the next page...
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CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions (continued)
Field Description
22 PLL clock divided by 8 output gating enable overrided by CCM
PLL_DIV8_
CLKE_
OVERRIDE
21 PLL clock divided by 6 output gating enable
PLL_DIV6_CLKE
20 PLL clock divided by 6 output gating enable overrided by CCM
PLL_DIV6_
CLKE_
OVERRIDE
19 PLL clock divided by 5 output gating enable
PLL_DIV5_CLKE
18 PLL clock divided by 5 output gating enable overrided by CCM
PLL_DIV5_
CLKE_
OVERRIDE
17 PLL clock divided by 4 output gating enable
PLL_DIV4_CLKE
16 PLL clock divided by 4 output gating enable overrided by CCM
PLL_DIV4_
CLKE_
OVERRIDE
15 PLL clock divided by 3 output gating enable
PLL_DIV3_CLKE
14 PLL clock divided by 3 output gating enable overrided by CCM
PLL_DIV3_
CLKE_
OVERRIDE
13 PLL clock divided by 2 output gating enable
PLL_DIV2_CLKE
12 PLL clock divided by 2 output gating enable overrided by CCM
PLL_DIV2_
CLKE_
OVERRIDE
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
Table continues on the next page...
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Clock Control Module (CCM)
CCM_ANALOG_SYS_PLL1_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.30 SYS PLL1 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_SYS_PLL1_FDIV_CTL0)
SYS PLL1 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 98h offset = 3036_0098h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
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CCM_ANALOG_SYS_PLL1_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
5.1.8.31 PLL Monitoring Control Register
(CCM_ANALOG_nMNIT_CTRL)
PLL Monitoring Control Register
Address: 3036_0000h base + 100h offset + (16d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PBIAS_CTRL_EN
R
AFCINIT_SEL
FOUT_MASK
PBIAS_CTRL
AFC_SEL
LRD_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FEED_EN
Reserved
AFC_EN
FSEL Reserved EXTAFC ICP
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1
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CCM_ANALOG_nMNIT_CTRL field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21 Monitoring pin. AFC operation mode select pin
LRD_EN
20 Scaler's re-initialization time control pin[3]
FOUT_MASK
19 AFC Mode select
AFC_SEL
18 PBIAS pull-down initial voltage control pin
PBIAS_CTRL
0 0.50 × VDD
1 0.67 × VDD
17 PBIAS voltage pull-down enable pin
PBIAS_CTRL_
EN
16 AFC initial delay select pin
AFCINIT_SEL
0 nominal delay
1 nominal delay × 2
15 This field is reserved.
- Reserved
14 Monitoring frequency select pin
FSEL
0 FEED_OUT = FREF
1 FEED_OUT = FEED
13 FEED_OUT enable pin
FEED_EN
12–8 This field is reserved.
- Reserved
7–3 Monitoring pin. If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the
EXTAFC test of VCO range
2 If AFC_ENB=0, AFC is enabled and VCO is calibrated automatically.(AFC_ENB=0 and EXTAFC=0 are
AFC_EN mandatory) If AFC_ENB=1, AFC is disabled and VCO is calibrated manually by EXTAFC[4:0] for the test
of VCO range
ICP Controls the charge-pump current
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5.1.8.32 SYS PLL2 General Function Control Register
(CCM_ANALOG_SYS_PLL2_GEN_CTRL)
SYS PLL2 General Function Control Register
Address: 3036_0000h base + 104h offset = 3036_0104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
PLL_DIV20_CLKE_OVERRIDE
PLL_DIV10_CLKE_OVERRIDE
PLL_DIV8_CLKE_OVERRIDE
PLL_DIV6_CLKE_OVERRIDE
PLL_DIV5_CLKE_OVERRIDE
PLL_DIV4_CLKE_OVERRIDE
R
PLL_EXT_BYPASS
PLL_DIV20_CLKE
PLL_DIV10_CLKE
PLL_DIV8_CLKE
PLL_DIV6_CLKE
PLL_DIV5_CLKE
PLL_DIV4_CLKE
PLL_LOCK_SEL
Reserved
Reset 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PLL_DIV3_CLKE_OVERRIDE
PLL_DIV2_CLKE_OVERRIDE
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_DIV3_CLKE
PLL_DIV2_CLKE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved
RST SEL CLK_SEL
Reset 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27 PLL clock divided by 20 output gating enable
PLL_DIV20_
CLKE
26 PLL clock divided by 20 output gating enable overrided by CCM
PLL_DIV20_
CLKE_
OVERRIDE
25 PLL clock divided by 10 output gating enable
PLL_DIV10_
CLKE
24 PLL clock divided by 10 output gating enable overrided by CCM
PLL_DIV10_
CLKE_
OVERRIDE
23 PLL clock divided by 8 output gating enable
PLL_DIV8_CLKE
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CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions (continued)
Field Description
22 PLL clock divided by 8 output gating enable overrided by CCM
PLL_DIV8_
CLKE_
OVERRIDE
21 PLL clock divided by 6 output gating enable
PLL_DIV6_CLKE
20 PLL clock divided by 6 output gating enable overrided by CCM
PLL_DIV6_
CLKE_
OVERRIDE
19 PLL clock divided by 5 output gating enable
PLL_DIV5_CLKE
18 PLL clock divided by 5 output gating enable overrided by CCM
PLL_DIV5_
CLKE_
OVERRIDE
17 PLL clock divided by 4 output gating enable
PLL_DIV4_CLKE
16 PLL clock divided by 4 output gating enable overrided by CCM
PLL_DIV4_
CLKE_
OVERRIDE
15 PLL clock divided by 3 output gating enable
PLL_DIV3_CLKE
14 PLL clock divided by 3 output gating enable overrided by CCM
PLL_DIV3_
CLKE_
OVERRIDE
13 PLL clock divided by 2 output gating enable
PLL_DIV2_CLKE
12 PLL clock divided by 2 output gating enable overrided by CCM
PLL_DIV2_
CLKE_
OVERRIDE
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
Table continues on the next page...
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CCM_ANALOG_SYS_PLL2_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.33 SYS PLL2 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_SYS_PLL2_FDIV_CTL0)
SYS PLL2 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 108h offset = 3036_0108h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1
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CCM_ANALOG_SYS_PLL2_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
5.1.8.34 PLL Lock Detector Control Register
(CCM_ANALOG_nLOCKD_CTRL)
PLL Lock Detector Control Register
Address: 3036_0000h base + 10Ch offset + (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK_CON_
R
LOCK_CON_ LOCK_CON_
Reserved IN
DLY OUT
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
CCM_ANALOG_nLOCKD_CTRL field descriptions
Field Description
31–6 This field is reserved.
- Reserved
5–4 Lock detector setting of the detection resolution
LOCK_CON_
DLY
Table continues on the next page...
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CCM_ANALOG_nLOCKD_CTRL field descriptions (continued)
Field Description
3–2 Lock detector setting of the output margin
LOCK_CON_
OUT
LOCK_CON_IN Lock detector setting of the input margin
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5.1.8.35 SYS PLL3 General Function Control Register
(CCM_ANALOG_SYS_PLL3_GEN_CTRL)
SYS PLL3 General Function Control Register
Address: 3036_0000h base + 114h offset = 3036_0114h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL_LOCK
R
PLL_EXT_BYPASS
PLL_LOCK_SEL
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLL_CLKE_OVERRIDE
PLL_RST_OVERRIDE
PLL_BYPASS
PLL_CLKE
PLL_ PAD_CLK_ PLL_REF_
Reserved Reserved
RST SEL CLK_SEL
Reset 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_SYS_PLL3_GEN_CTRL field descriptions
Field Description
31 PLL lock signal
PLL_LOCK
30 This field is reserved.
- Reserved
29 PLL lock select
PLL_LOCK_SEL
0 Using PLL maximum lock time
1 Using PLL output lock
28 PLL analog block bypass, clock output traces to PLL source
PLL_EXT_
BYPASS
27–12 This field is reserved.
- Reserved
11 PLL output clock clock gating enable
PLL_CLKE
10 Override the PLL_CLKE, clock gating enable signal from CCM
PLL_CLKE_
OVERRIDE
9 PLL reset (active low)
PLL_RST
8 PLL reset overrided by CCM
PLL_RST_
OVERRIDE
7–5 This field is reserved.
- Reserved
4 PLL output clock bypass
PLL_BYPASS
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CCM_ANALOG_SYS_PLL3_GEN_CTRL field descriptions (continued)
Field Description
3–2 PAD clock select
PAD_CLK_SEL
PAD_CLK is an alternate input reference clock for the PLL. The clock source selection for PAD_CLK is
defined below.
00 CLKIN1 XOR CLKIN2
01 CLKIN2
10 CLKIN1
11 Reserved
PLL_REF_CLK_ PLL reference clock select
SEL
00 24M_REF_CLK
01 PAD_CLK
10 Reserved
11 Reserved
5.1.8.36 SYS PLL3 Divide and Fraction Data Control 0 Register
(CCM_ANALOG_SYS_PLL3_FDIV_CTL0)
SYS PLL3 Divide and Fraction Data Control 0 Register
Address: 3036_0000h base + 118h offset = 3036_0118h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PLL_MAIN_DIV
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
PLL_MAIN_DIV Reserved PLL_PRE_DIV PLL_POST_DIV
Reset 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1
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CCM_ANALOG_SYS_PLL3_FDIV_CTL0 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21–12 Value of the main-divider
PLL_MAIN_DIV
11–10 This field is reserved.
- Reserved
9–4 Value of the pre-divider
PLL_PRE_DIV
3 This field is reserved.
- Reserved
PLL_POST_DIV Value of the post-divider
5.1.8.37 Osc Misc Configuration Register
(CCM_ANALOG_OSC_MISC_CFG)
Osc Misc Register
Address: 3036_0000h base + 124h offset = 3036_0124h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSC_32K_SEL
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_OSC_MISC_CFG field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0 32KHz OSC input select
OSC_32K_SEL
0 Divided by 24M clock
1 32K Oscillator
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5.1.8.38 PLL Clock Output for Test Enable and Select Register
(CCM_ANALOG_ANAMIX_PLL_MNIT_CTL)
PLL Clock Output for Test Enable and Select Register
Address: 3036_0000h base + 128h offset = 3036_0128h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OUTPUT_CKE
R
CLKOUT2_
CLKOUT2_OUTPUT_DIV_
Reserved CLKOUT2_OUTPUT_SEL
VAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OUTPUT_CKE
R
CLKOUT1_
CLKOUT1_OUTPUT_DIV_
Reserved CLKOUT1_OUTPUT_SEL
VAL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCM_ANALOG_ANAMIX_PLL_MNIT_CTL field descriptions
Field Description
31–25 This field is reserved.
- Reserved
24 CLKOUT2 Monitor output enable
CLKOUT2_
OUTPUT_CKE
23–20 CLKOUT2 Monitor output clock select
CLKOUT2_
4'b0000 : audio_pll1_clk
OUTPUT_SEL
4'b0001 : audio_pll2_clk
4'b0010 : video_pll1_clk
4'b0011 : hsio_pll_clk
4'b0100 : misc_mnit_clk
4'b0101 : gpu_pll_clk
4'b0110 : vpu_pll_clk
4'b0111 : arm_pll_clk
4'b1000 : system_pll1_clk
Table continues on the next page...
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CCM_ANALOG_ANAMIX_PLL_MNIT_CTL field descriptions (continued)
Field Description
4'b1001 : system_pll2_clk
4'b1010 : system_pll3_clk
4'b1011 : CLKIN1
4'b1100 : CLKIN2
4'b1101 : sysosc_24m_clk
4'b1110 : sai_pll_clk
4'b1111 : osc_32k_clk
19–16 CLKOUT2 output divide value
CLKOUT2_
OUTPUT_DIV_
VAL
15–9 This field is reserved.
- Reserved
8 CLKOUT1 Monitor output enable
CLKOUT1_
OUTPUT_CKE
7–4 CLKOUT1 Monitor output clock select
CLKOUT1_
4'b0000 : audio_pll1_clk
OUTPUT_SEL
4'b0001 : audio_pll2_clk
4'b0010 : video_pll1_clk
4'b0011 : hsio_pll_clk
4'b0100 : misc_mnit_clk
4'b0101 : gpu_pll_clk
4'b0110 : vpu_pll_clk
4'b0111 : arm_pll_clk
4'b1000 : system_pll1_clk
4'b1001 : system_pll2_clk
4'b1010 : system_pll3_clk
4'b1011 : CLKIN1
4'b1100 : CLKIN2
4'b1101 : sysosc_24m_clk
4'b1110 : sai_pll_clk
4'b1111 : osc_32k_clk
CLKOUT1_ CLKOUT1 output divide value
OUTPUT_DIV_
VAL
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5.1.8.39 DIGPROG Register (CCM_ANALOG_DIGPROG)
DIGPROG Register
Address: 3036_0000h base + 800h offset = 3036_0800h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DIGPROG_MAJOR_UPPER DIGPROG_MAJOR_LOWER DIGPROG_MINOR
Reserved
W
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0
CCM_ANALOG_DIGPROG field descriptions
Field Description
31–24 This field is reserved.
- Reserved
23–16 Bit[7:4] is 0x8, stands for “i.MX8” Bit[3:0] is 0x2, stands for ”M”
DIGPROG_
MAJOR_UPPER
15–8 Bit[7:4] is 0x4, stands for “Quad” Bit[3:0] is 0x3, stands for “Plus”
DIGPROG_
MAJOR_LOWER
DIGPROG_ Bit[7:4] is the base layer revision, Bit[3:0] is the metal layer revision 0x10 stands for Tapeout 1.0
MINOR
5.2 General Power Controller (GPC)
5.2.1 Overview
The General Power Controller (GPC) module controls the following functions:
• Provide low power mode control for A53 and M7 platform
• Provide Power domain management all Arm and SOC power domain
• Provide domain control mechanism based on A53 and M7 CPU domain
• Provide handshake with CCM for clock management in low power mode
• Provide handshake with SRC for power down and power up sequence
• Provide handshake with Analog for Deep Sleep Mode control
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5.2.2 Features
The General Power Controller (GPC) module controls the following functions:
• Support programmable feature for WAIT/STOP/DSM low power mode
• Support time slot based power domain control
• Support flexible sleep and wakeup condition
• Support domain control for multi CPU platforms system
• All register accessed by IP bus
• Interface for the following IPs:
• CCM – clock controller module
• SRC – system reset controller
• ANALOG – miscellaneous analog control
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5.2.3 Block Diagram
Handshake
analog and with
PMIC
interrupt
LPM Quad A53 LPM M7
wfi
DSM Control
SMC
Power state Clock handshake Power handshake
Power state
Clock handshake Domain
Control
Logic
PGC_1
Handshake with SRC
Timeslot PGC_2
...
Control
PGC_PDN
PGTSC
Power signal
Figure 5-10. GPC Block Diagram
The GPC module contains two sub-modules: System Mode Controller (SMC) and Power
Gating Time Slot Control (PGTSC):
• GPC Top: the top level GPC. It also includes the top memory map and registers,
domain control information, and memory low power control.
• System Mode Controller (SMC):
• The SMC supports two low power modes (LPM), WAIT and STOP. Each LPM
corresponds to one mode for A53 platform and one mode for M7 platform.
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• SMC controls the power sequence in Deep Sleep Mode (DSM)
• SMC support the power up and power down of A53 core0/core1/core2/core3 by
IRQ/WFI signals without LPM triggered
• SMC can translate the LPM request for A53 and M7 platform to power up and
power down request to PGTSC.
• Power Gating Time Slot Control (PGTSC):
• The Power Gating Controller (PGC) is a power management component that
controls the power-down and power-up sequencing of individual
subsystems. For subsystems to be completely powered down in low power
modes, a specific sequence of power control signals must be followed. The
sequence timing is programmable using the PGC control registers.
• There are 27 PGCs in the chip, all of them can be power down/up with a
software trigger and all of them can be mapped to 27 timing slots and
power-up and power down by request from SMC.
5.2.4 Functional Description
5.2.4.1 RUN mode
This is the normal/functional operating mode. In this mode, the CPU runs in its normal
operational mode.
5.2.4.2 Low power mode
There are two CPU platforms (each of them represents a CPU domain): Quad core Cortex
A53 platform and Cortex M7 platform. Each platform supports two low power modes:
WAIT mode and STOP mode.
5.2.4.2.1 WAIT mode
In this low power mode:
• LPCG can be defined to be shut off or not in wait mode for each CPU domain
• PLL can be defined to be shut off or not in wait mode for each CPU domain
NOTE
The PLLs will only been closed in non-fast wake-up mode,
relevant bit are
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GPC_SLPCR[EN_A53_FASTWUP_WAIT_MODE] and
GPC_SLPCR[EN_M7_FASTWUP_WAIT_MODE]
• CPU clock can be defined been shut off or not in wait for each CPU platform.
(GPC_LPCR_A53_BSC[CPU_CLK_ON_LPM] and
GPC_LPCR_M7[CPU_CLK_ON_LPM])
• Power of different power domain can be defined be shut off or not in wait mode for
each platform domain
• Some peripherals may go to wait mode along with A53 or M7 platform.
5.2.4.2.2 STOP mode
In this low power mode:
• LPCG can be defined been shut off or not in stop mode for each CPU domain
• PLL can be defined been shut off or not in stop mode for each CPU domain
NOTE
The PLLs will only been closed in non-fast wake-up mode,
relevant bit are
GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] and
GPC_SLPCR[EN_M7_FASTWUP_STOP_MODE]
• CPU clock can be defined been shut off or not in stop for each CPU
(GPC_LPCR_A53_BSC[CPU_CLK_ON_LPM] and
GPC_LPCR_M7[CPU_CLK_ON_LPM])
• Power of different power domain can be defined be shut off or not in stop mode for
each platform domain
• Some peripherals may go to stop mode along with A53 or M7 platform.
5.2.4.3 Deep Sleep Mode
The Deep Sleep Mode (DSM) is a system low power mode.
In this mode:
• On-chip OSC can be defined to be shut off or not in DSM (GPC_SLPCR[SBYOS])
• PMIC can be defined to be stand-by mode or not in DSM (GPC_SLPCR[VSTBY])
• Regulator can be defined to be BYPASS mode or not in DSM
(GPC_SLPCR[RBC_EN])
• Memory can be defined to go to retention mode or not in
DSM(GPC_MLPCR[MEMLP_CTL_DIS])
• A53 platform power (VDD_ARM) can be defined to be shut off or not in DSM.
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NOTE
CCM configuration must make sure close all PLLs before
system goes to DSM
NOTE
For the SoC to correctly power up after entering DSM,
CCM_PLL_CTRLx must not be set to 0x0 or 0x3 for any
domain in use.
5.2.4.4 LPM Sleep Process
CPU platform will go to WAIT/STOP under the following conditions:
• LPM registers (GPC_LPCR_A53_BSC[LPM0], GPC_LPCR_A53_BSC[LPM1],
GPC_LPCR_A53_BSC2[LPM2], GPC_LPCR_A53_BSC2[LPM3],
GPC_LPCR_M7[LPM]) are set to WAIT or STOP.
NOTE
Since A53 platform has four cores, the so each core has its
own LPM register: GPC_LPCR_A53_BSC[LPM0] and
GPC_LPCR_A53_BSC[LPM1],
GPC_LPCR_A53_BSC2[LPM2] and
GPC_LPCR_A53_BSC2[LPM3]. The unified LPM of A53
will be generated with the lower LPM of the cores.
• Asserting the WFI signal will trigger CPU sleep process. There are five WFIs that
come from A53 platform: WFI_core0, WFI_core1, WFI_core2, WFI_core3, and
WFI_scu. The A53 platform will go to LPM when all WFIs are asserted. If the
GPC_LPCR_A53_AD[EN_C0_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C1_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C2_WFI_PDN] or
GPC_LPCR_A53_AD[EN_C3_WFI_PDN] bit is set, the LPM trigger condition will
be a little different. See Power control for A53 Platform for more information. Only
one WFI comes from M7 platform. The M7 platform will go to LPM when WFI_M7
asserted.
NOTE
WFI condition can be masked by register bits
GPC_LPCR_A53_BSC[MASK_n_WFI] and
GPC_LPCR_M7[MASK_M7_WFI]
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RUN
LPM = 10
AND ~dsm_request
dsm_request LPM = 01 OR
AND AND dsm_wakeup
~dsm_wakeup ~dsm_request dsm_request
OR AND
dsm_wakeup ~dsm_wakeup
STOP WAIT
dsm_request dsm_request
AND gpc_pup_ack AND gpc_pup_ack
~dsm_wakeup ~dsm_wakeup
STOP_PGC WAIT_PGC
Figure 5-11. LPM transition inside CPU platform
System will go to DSM under the following conditions:
• Both A53 and M7 are STOP mode.
• Both GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] and
GPC_SLPCR[EN_M7_FASTWUP_STOP_MODE] are not set.
• GPC_SLPCR[EN_DSM] is set.
NOTE
If GPC_LPCR_M7[MASK_DSM_TRIGGER] is set, the
system will go to DSM when A53 goes STOP mode and
GPC_SLPCR[EN_A53_FASTWUP_STOP_MODE] is not
set. If GPC_LPCR_A53_BSC[MASK_DSM_TRIGGER]
is set, the system will go to DSM when M7 goes to STOP
mode and
GPC_SLPCR[EN_M7_FASTWUP_STOP_MODE] not
set. GPC_LPCR_M7[MASK_DSM_TRIGGER] and
GPC_LPCR_A53_BSC[MASK_DSM_TRIGGER] cannot
be set at the same time.
5.2.4.5 LPM Wake Up Process
DSM, STOP, WAIT mode will be woken up by interrupts:
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• The CPU platforms share the same IRQ sources in this chip. Software can use
GPC_IMRn_CORE0_A53, GPC_IMRn_CORE1_A53, GPC_IMRn_CORE2_A53,
GPC_IMRn_CORE3_A53, and GPC_IMRn_M7 to separate the 128 bits IRQ
sources to A53 core0, core1, core2, and core3, and M7 platform.
• The A53 core0, core1, core2, and core3 IRQ can also be from GIC source (defined
by GPC_LPCR_A53_BSC[IRQ_SRC_C3], GPC_LPCR_A53_BSC[IRQ_SRC_C2],
GPC_LPCR_A53_BSC[IRQ_SRC_C1], and
GPC_LPCR_A53_BSC[IRQ_SRC_C0]) and if it is chosen from GIC source the
GPC_IMRn_x_A53 will lose its function. See Power control for A53 Platform for
more information.
• Interrupts for both A53 and M7 will cause the system wake up from DSM, A53
interrupt will wake up A53 from LPM, M7 interrupt will wake up M7 from LPM.
5.2.5 Power Gating Controller (PGC) Overview
The Power Gating Controller (PGC) is a power management component that controls the
power-down and power-up sequencing of individual subsystems. For subsystems to be
completely powered down in low power modes, a specific sequence of power control
signals must be followed. The sequence timing is programmable using the PGC control
registers.
Power-Management and Clock-Control Subsystem
PGC
Higher-level pdn_req isolation
Componenet Target
pup_req
Subsystem
pdn_ack switch_b
pup_ack
module_clk pwrgate_rst_b
enable_clk
Figure 5-12. Power Gating Controller (PGC)
5.2.5.1 PGC power domains
The following table lists the PGCs in the chip and the corresponding power domain.
There are three types of PGC - CPU, MIX, and PU. The power for the PUs (Power Units)
can be controlled by the GPC.
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PGC type Power domain
PGC_C0 core0 of ca53
PGC_C1 core1 of ca53
PGC_C2 core0 of ca53
PGC_C3 core0 of ca53
PGC_SCU SCU/L2 cache RAM of A53
PGC_SUPERMIX supermix
PGC_SS_NOC_WRAPPER ss_noc_wrapper
PGC_MIPI_PHY1 mipi_phy1
PGC_PCIE_PHY pcie_phy
PGC_USB1_PHY usb1_phy
PGC_USB2_PHY usb2_phy
PGC_MLMIX mlmix
PGC_AUDIOMIX audiomix switchable
PGC_GPU_2D gpu_2d
PGC_GPU_SHARE_LOGIC gpu_share_logic
PGC_VPUMIX_SHARE_LOGIC vpumix_share_logic
PGC_GPU3D gpu3d
PGC_MEDIMIX medimix default switchable
PGC_VPU_G1 vpu_g1
PGC_VPU_G2 vpu_g2
PGC_VPU_VC8K VPU_VC8K
PGC_HDMIMIX hdmimix
PGC_HDMI_PHY hdmi_phy
PGC_MIPI_PHY2 mipi_phy2
PGC_HSIOMIX hsiomix switchable
PGC_MEDIA_ISP_DWP media_isp_dwp
PGC_DDRMIX ddrmix
5.2.5.2 Trigger to PGC: Hardware and Software Requests
All PGCs can be power up/down by hardware or software request.
The LPM controller for each platform can generate hardware power down or power up
request. All hardware requests will be mapped to “timeslot controller” before they goes to
relevant PGC (see “Time slot control for PGCs” for more information).
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The CPU can also generate software power up or power down request to relevant PGCs.
The software trigger will not be mapped to timeslot control. If there are PGCs in software
PDN/PUP sequence the request from LPM will be masked. The software trigger will also
be failed if the timeslot control is in “busy” state.
All power up/down request to PGCs will be mapped to domain control module (see
“Domain control for PGCs ”).
PGC_C0, PGC_C1, PGC_C2, and PGC_C3 can be triggered by its own “WFI/IRQ”
without LPM trigger and time slot. See Power control for A53 Platform for more
information.
5.2.5.3 Time slot control mechanism for PGCs
GPC uses a time slot controller to control the PGC sub-systems, such as the PGC in
CPU0, CPU1,CPU2, CPU3, MIX, PCIE PHY, etc. We use it for below reasons when
system wakes from low power mode.
1. Support flexible power down/up sequence for different sub-system
2. Sub-system can be power up in different slot to avoid large ramping up current in
case they start ramping up at the same time
There are a total of 27 time slots used in the chip, one or more PGCs are used for power
up or power down in each of these slots. The time slot controller will sample power up/
down requests at slot0. If there are power up/down requests from SMC, it will scan from
slot0 to slot26. When the scan process comes to one slot which has a defined power up or
power down for one or more PGCs (defined by “SLTn_CFG”), the power up/down
sequence of relevant PGCs will happen in that slot. Otherwise, the relevant slot will be
skipped.
The next slot will not begin until the all PGCs finish their power up or power down
process in current time slot. When all the 27 slots are finished, slot controller will jump to
IDLE state and monitor new request from SMC.
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IDLE
sample hw_*_req, total 27 requests
any No
hw_*_req asserted
Yes
slot0 check slt0_cfg, power-up/down PGC if request asserted, ACK to hw_*_req
if slt0_cfg is 18'h0, stay in slot0 one cycle, then jumps to slot1
slot1 check slt1_cfg, power-up/down PGC if request asserted, ACK to hw_*_req
if slt1_cfg is 18'h0, stay in slot1 one cycle, then jumps to slot2
.....
slot25 check slt25_cfg, power-up/down PGC if request asserted, ACK to hw_*_req
if slt25_cfg is 18'h0, stay in slot26 one cycle, then jumps to IDLE
Figure 5-13. Slot controller processing flow
NOTE
PGC_SCU should be “always-on” to PGC_C0 PGC_C1,
PGC_C2, and PGC_C3. This means PGC_SCU should be
power up earlier than PGC_C0/PGC_C1/PGC_C2/PGC_C3
and should be power down later than PGC_C0/PGC_C1/
PGC_C2/PGC_C3 (see example code 1 and 2). If we arrange
A53 Cx/A53 SCU power down/up in same slot, special setting
is required (see example code 2).
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NOTE
When the system enters/exists ALL_OFF or L2_RETENTION
mode, PGC_MF should be power up earlier than PGC_C0/
PGC_C1/PGC_C2/PGC_C3/PGC_SCU. We can arrange MIX
PGC power up in earlier slot than A53 Cx/SCU power up slot
(See example code 1 and 2).
NOTE
SCU power down should not be enabled in wait mode.
5.2.5.4 Handshake between LPM controller and time slot controller
The figure below shows an example of A53 “into” LPM sequence. We want to power up
A53 SCU and A53 core0 in time slot0 /slot1/slot2 respectively. Request from low power
mode controller will be mapped to relevant PGCs according to the rules listed above. We
choose acknowledge from PGC_core0 as the acknowledge for A53 LPM power down
request (relevant register bits are defined in “PGC_ACK_SEL_A53”). The A53 LPM
will regard the three PGCs as a virtual big PGC and it will cancel all power up request
when it receive the acknowledge signals from PGC_core0.
slot0 slot1 slot2
pup_req
PGC_mf
time
Low power mode pup_req pup_req
logic PGC_plat
controller for
A53 platform
pup_req
PGC_c0
pup_ack Virtual PGC for A53 Platform
Figure 5-14. A53 into LPM sequence
NOTE
If a PGC is mapped to two CPU domain (refer to “Domain
control for PGCs ”for more information), it cannot be selected
as the power down acknowledge for both of the CPU platform.
“PGC_ACK_SEL_A53”, "PGC_ACK_SEL_A53_PU", and
“PGC_ACK_SEL_M7” are should be chosen for the last PGC
in power up or power down sequence in the time slot. If there is
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no PGC be power up/power down with LPM sequence, the
“dummy” acknowledge should be selected. Only one PGC
should be selected for power down or power up acknowledge
for one CPU platform.
5.2.6 Power control for A53 Platform
5.2.6.1 A53 Platform power domains and power modes
There are six power domains inside SEC dual core Cortex A53 platform: Core0, Core1,
Core2, Core3, SCU, and L2 RAM. There are seven power states in A53 platform:
Power State PDCPU0 PDCPU1 PDCPU2 PDCPU3 PDPLAT PDL2 VDD_ARM
ALL_ON ON ON ON ON ON ON ON
THREE_CPU 3 CPUs are ON, 1 CPU is OFF ON ON ON
_ON
TWO_CPU_O 2 CPUs are ON, 2 CPUs are OFF ON ON ON
N
ONE_CPU_O 1 CPU is ON, 3 CPUs are OFF ON ON ON
N
ALL_CPU_OF OFF OFF OFF OFF ON ON ON
F
L2_RETENTI OFF OFF OFF OFF OFF RET ON
ON
VDD_ARM_O OFF OFF OFF OFF OFF OFF ON
FF
NOTE
In all seven power states, “ALL_ON”, “THREE_CPU_ON",
"TWO_CPU_ON", and "ONE_CPU_ON" can exist in all RUN,
WAIT or STOP mode of A53 platform.
"ALL_CPU_OFF","L2_RETENTION" and
"VDD_ARM_OFF" can only exist in WAIT or STOP mode of
A53 platform.
5.2.6.2 Power down process for the A53 Platform
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5.2.6.2.1 Power down of Core0, Core1, Core2, and Core3 in the A53
Platform
The power of core0, core1, core2, and core3 can be shut off along with the LPM process,
as show in the following figure:
SCU WFI
Core0 WFI Core1 WFI
&
Core2 WFI Core3 WFI
WAIT/STOP
Core0 Core3
Power-down Power-down
Core1 Core2
Power-down Power-down
WAIT_PGC
STOP_PGC
Figure 5-15. Power down of Core0, Core1, Core2, and Core3
WFIs from A53 platform will trigger the A53 platform LPM and the power of core0,
core1, core2, or core3 will be shut off when “lpcr_a53_ad.en_c0_pdn”,
“lpcr_a53_ad.en_c1_pdn”, “lpcr_a53_ad.en_c2_pdn”, or “lpcr_a53_ad.en_c3_pdn”
enabled in this process. This mode should be used when core0 is used as the leading core
of A53 platform.
The power of core0, core1, core2, and core3 can also be shut off in RUN mode: in this
mode “LPCR_A53_AD.en_c0_wfi_pdn”, “LPCR_A53_AD.en_c1_wfi_pdn”,
“LPCR_A53_AD.en_c2_wfi_pdn”, and “LPCR_A53_AD.en_c3_wfi_pdn” should be set
and the condition to trigger A53 LPM will be some different:
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Core0 Core1
Power-down Power-down
ACK ACK
Core2 SCU WFI Core3
Power-down Power-down
ACK ACK
Core0 Core1
Power-down Power-down
Core2 Core3
Power-down Power-down
&
WAIT/STOP
WAIT_PGC
STOP_PGC
Figure 5-16. Power down of Core0, Core1, Core2, and Core3 in RUN mode
In this mode, core0/core1/core2/core3 power down process should not be disturbed by
IRQs.
5.2.6.2.2 Power down of SCU and L2 Cache RAM
Power domain SCU and L2 cache RAM is controlled by one PGC – “PGC_PLAT” and
they can only be power down in LPM process (when “LPCR_A53_AD.en_plat_pdn” is
set). There is another bit “LPCR_A53_AD.l2pge” which will decide if L2 cache RAM
need to be in retention mode when SCU domain is power down.
5.2.6.3 Power up process for the A53 Platform
• The core0, core1, core2, and core3 can be powered up with the exit of A53 LPM.
The relevant bits are “LPCR_A53_AD.en_c0_pup”, “LPCR_A53_AD.en_c1_pup”,
“LPCR_A53_AD.en_c2_pup”, and “LPCR_A53_AD.en_c3_pup”.
• The core0, core1, core2, and core3 can also be powered up by interrupt signal in
RUN mode.
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• The relevant bit are “LPCR_A53_AD.en_c0_irq_pup”,
“LPCR_A53_AD.en_c1_irq_pup”, “LPCR_A53_AD.en_c2_irq_pup”, and
“LPCR_A53_AD.en_c3_irq_pup”.
• The interrupt signal can be chosen from GIC or directly from IRQ with mask in
GPCv2.
• The relevant select bits are “LPCR_A53_BSC.irq_src_c0”,
“LPCR_A53_BSC.irq_src_c1”, “LPCR_A53_BSC.irq_src_c2”,
“LPCR_A53_BSC.irq_src_c3”, and “LPCR_A53_BSC.irq_src_a53_wup”.
(LPCR_A53_BSC[30],LPCR_A53_BSC[23:22],LPCR_A53_BSC.)
{LPCR_A53_BSC[30],LPCR_A53_BS Usage Restriction
C[23:22],LPCR_A53_BSC[29:28]}
5'b00000 Use IRQ trigger A53 LPM and use IRQ None
to power up core0 to core3
5'b01111 Use GIC trigger A53 LPM and GIC to SCU cannot power down in LPM, CPU
power up core0 to core3 clock cannot stop in LPM
5'b11111 Use IRQ trigger A53 LPM and GIC to SCU cannot power down in LPM
power up core0 to core3
As show in the table above, core0/core1/core2/core3 can only be power up by its own
interrupt in RUN mode of A53 platform.
There are three combination of
{LPCR_A53_BSC[30],LPCR_A53_BSC[23:22],LPCR_A53_BSC[29:28]}:
1. In the first case, “IMRn_CORE0_A53, IMRn_CORE1_A53, IMRn_CORE2_A53,
IMRn_CORE3_A53“ are used to separate the 128 bits interrupts for core0, core1,
core2, and core3 of A53 platform and also used as the interrupt mask for A53 LPM.
2. In the second case, “IMRn_CORE0_A53, IMRn_CORE1_A53,
IMRn_CORE2_A53, IMRn_CORE3_A53” are not used, GIC setting are used to
separate interrupts for core0, core1, core2, and core3 of A53 platform and also used
as the interrupt mask for A53 LPM.
3. In the third case, “IMRn_CORE0_A53, IMRn_CORE1_A53, IMRn_CORE2_A53,
IMRn_CORE3_A53” is used as the mask for interrupt for A53 LPM, GIC setting are
used to separate interrupts for core0, core1, core2, and core3.
5.2.7 Power control for the M7 Platform
M7 LPM is same as A53 LPM. The M7 platform does not have its own power domain.
There is a virtual PGC reserved for the M7. The virtual PGC will do nothing else except
generating an acknowledge signal and this signal can be chosen as the acknowledge
signal for the M7 platform.
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5.2.8 Domain control for PGCs
The following rules are used for PGC power up/down with domain mapping control:
1. For PGCs inside CPU platform (since M7 doesn’t have its own power domain, only
PGCs in A53 platform are referred): for hardware trigger (including both power up
and power down) only the LPM request from its own platform will take effect; for
software trigger (including both power up and power down) (the relevant register bit
are “CPU_PGC_SW_PUP_REQ” and “CPU_PGC_SW_PDN_REQ”), only the
software running in its own platform will take effect.
2. For PGCs outside CPU platform(MIX and PU PGCs), register bits
“PGC_CPU_MAPPING” will map MIX and PU PGCs to A53 or M7 CPU domain:
• One PGC can be mapped to one or both of A53 and M7 domain;
• For hardware power up request, if a PGC is mapped to any CPU domain, the
PGC will be powered up when the corresponding CPU platform sends out its
power up request.
• For software power up, if a PGC is mapped any CPU platform, the PGC can be
powered up by software running in corresponding CPU.(the relevant register bits
are “MIX_PGC_SW_PUP_REQ” and “PU_PGC_SW_PUP_REQ”)
• For hardware power down, if a power domain is mapped to only one CPU
domain, the relevant PGC can be powered down when the corresponding CPU
platform sends out its power down request; If a power domain is mapped to both
two CPU domain, when one CPU platform sends out its hardware power down
request, the relevant PGC will power down with any of the following condition
satisfied: the other CPU already in LPM; the other CPU want to power down
relevant PGC (the relevant register are “A53_MIX_PDN_FLG,
M7_MIX_PDN_FLG, A53_PU_PDN_FLG, M7_PU_PDN_FLG”)
• For software power down, if a power domain is mapped to only one CPU
domain, the PGC can be powered down by software running in corresponding
CPU. (the relevant register bits are “MIX_PGC_SW_PUP_REQ” and
“PU_PGC_SW_PUP_REQ”). If a power domain is mapped to both two CPU
domain, when one CPU platform sends out its software power down request, the
relevant PGC will power down with any of the following condition satisfied: the
other CPU already in LPM; the other CPU want to power down relevant PGC
(the relevant register are “A53_MIX_PDN_FLG, M7_MIX_PDN_FLG,
A53_PU_PDN_FLG, M7_PU_PDN_FLG”)
• The access of “PGC_CPU_MAPPING” is controlled by domain information
from RDC
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5.2.9 Example Code
Below are code examples for entering specific power scenarios
5.2.9.1 Example Code 1
//Arm enters into ALL_OFF(STOP) mode and enable DSM :
//after "wfi", MIX/C0/C1/C2/C3 power down in SLOT0, SCU power down in SLOT1 when
//after "GPT1_INT" arrived, MIX power up in SLOT2, SCU power up in SLOT3, C0 power up in
SLOT4
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF); //[23] : GPT1 used as wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_CO/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x80000000) ;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//SLT_CFG0
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reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000055) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0000001) ;
//[0] : power down in SLOT0
//SLT_CFG1
reg32_write(GPC_IPS_BASE_ADDR + 0xB4,0x00000100) ;
//[8] : A53_SCU power down in SLOT1
//SLT_CFG2_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x208,0x00000002) ;
//[1] : power up in SLOT2
//SLT_CFG3
reg32_write(GPC_IPS_BASE_ADDR + 0xBC,0x00000200) ;
//[9] : A53_SCU power up in SLOT3
//SLT_CFG4
reg32_write(GPC_IPS_BASE_ADDR + 0xC0,0x00000002) ;
//[1] : A53_C0 power up in SLOT4, A53_C1/ A53_C2/A53_C3 not power up
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00000001) ;
//[0] : MIX PGC mapping to A53 LPM
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x8C0, reg32_read(GPC_IPS_BASE_ADDR +0x8C0) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt:lt: 10) | 0x5B | (0x51 lt:lt: 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down
5.2.9.2 Example Code 2
//Arm enters into L2_RETENTION(STOP) mode and enable DSM :
//after "wfi", MIX/C0/C1/C2/C3/SCU power down in SLOT0
//after "GPT1_INT" arrived, MIX power up in SLOT1, SCU/C0 power up in SLOT2
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF);
//[23] : GPT1 used as wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);
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//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_C0/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x80000000) ;
//[31] : DSM ingore to check M4 low power state
//[1:0] : M4 LPM run mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//SLT_CFG0
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000155) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//[8] : A53_SCU power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0000001) ;
//[0] : power down in SLOT0
//A53_Cx/SCU are power down in same slot. Special setting is required( see below PGC setting
#A )
//SLT_CFG1_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x204,0x00000002) ;
//[1] : power up in SLOT1
//SLT_CFG2
reg32_write(GPC_IPS_BASE_ADDR + 0xB8,0x00000202) ;
//[9] : A53_SCU power up in SLOT1
//[1] : A53_C0 power up in SLOT1, A53_C1/ A53_C2/ A53_C3 not power up
//A53_Cx/SCU are power up in same slot. Special setting is required( see below PGC setting
#B )
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00000001) ;
//[0] : MIX PGC mapping to A53 LPM
//Special PGC setting #A for C0/C1/C2/C3/SCU power down in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x808, (reg32_read(GPC_IPS_BASE_ADDR +0x808) & 0xFFFFC0C0) |
0x0801 ) ;
// set C0.ISO2SW = 8 ; C0.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C1.ISO2SW = 8 ; C1.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x888, (reg32_read(GPC_IPS_BASE_ADDR +0x888) & 0xFFFFC0C0) |
0x0801 ) ;
// set C2.ISO2SW = 8 ; C2.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x8C8, (reg32_read(GPC_IPS_BASE_ADDR +0x8C8) & 0xFFFFC0C0) |
0x0801 ) ;
// set C3.ISO2SW = 8 ; C3.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x908, (reg32_read(GPC_IPS_BASE_ADDR +0x908) & 0xFFFFC0C0) |
0x1001 ) ;
// set SCU.ISO2SW = 16 ; SCU.ISO = 1;
//Special PGC setting #B for A53_Cx/SCU power up in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
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reg32_write(GPC_IPS_BASE_ADDR +0x804, (reg32_read(GPC_IPS_BASE_ADDR +0x804) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C0.SW = 0x11 ; C0.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C1.SW = 0x11 ; C1.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x884, (reg32_read(GPC_IPS_BASE_ADDR +0x884) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C2.SW = 0x11 ; C2.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x8C4, (reg32_read(GPC_IPS_BASE_ADDR +0x8C4) & 0xFF800040) |
0x11 | (0x20 lt;lt; 7) ) ;
// set C3.SW = 0x11 ; C3.SW2ISO = 0x20 ;
reg32_write(GPC_IPS_BASE_ADDR +0x904, (reg32_read(GPC_IPS_BASE_ADDR +0x904) & 0xFF800040) |
0x1 | (0x0f lt;lt; 7) ) ;
// set SCU.SW = 0x1 ; SCU.SW2ISO = 0x0f ;
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x8C0, reg32_read(GPC_IPS_BASE_ADDR +0x8C0) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt;lt; 10) | 0x5B | (0x51 lt;lt; 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down
5.2.9.3 Example Code 3
//A53/M4 both enters into low power mode. A53/M4 are in different master domain.
//MIX are mapping to both A53 and M4
//after A53/M4 enters into low power mode, MIX will be also power down.A53/M4 enters into
low power mode any time
//either A53 or M4 exists from low power mode, MIX will be also power up
//IMRx_CORE0_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x30, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x34, 0xFF7FFFFF);
//[23] : GPT1 used as Arm wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x38, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x3C, 0xFFFFFFFF);
//IMRx_CORE1_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x40, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x44, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x48, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x4C, 0xFFFFFFFF);
//IMRx_CORE2_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1C0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1C8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1CC, 0xFFFFFFFF);
//IMRx_CORE3_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x1D0, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D4, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1D8, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x1DC, 0xFFFFFFFF);
//IMRx_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x50, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x54, 0xFFBFFFFF);
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//[22] : GPT2 used as M4 wakeup source
reg32_write(GPC_IPS_BASE_ADDR + 0x58, 0xFFFFFFFF);
reg32_write(GPC_IPS_BASE_ADDR + 0x5C, 0xFFFFFFFF);
//LPCR_A53_BSC
reg32_write(GPC_IPS_BASE_ADDR, 0x0000000A) ;
//[30],[23:22],[29:28] : A53_C0/A53_C1/A53_C2/A53_C3/LPM wakeup from external INT
//[14] : CLOCK OFF during STOP mode
//[3:0] : STOP mode
//LPCR_A53_BSC2
reg32_write(GPC_IPS_BASE_ADDR + 0x108, 0x0000000A) ;
//[3:0] : STOP mode
//LPCR_A53_AD
reg32_write(GPC_IPS_BASE_ADDR + 0x4, 0x0A0A0A1A) ;
//[16] : 1(ALL_OFF mode); 0(L2 retention mode)
//[27]/[25]/[11]/[9]: A53_C0/A53_C1/A53_C2/A53_C3 power up with A53 LPM PUP REQ
//[4] : A53_SCU power down with A53 LPM PDN REQ
//[19]/[17]/[3]/[1] : A53_C0/A53_C1/A53_C2/A53_C3 powr down with A53 LPM PDN REQ
//LPCR_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x8, 0x00003FFE) ;
//[31] : 0(check M4 low power state to enter into DSM)
//[14] : 0(M4 clock OFF during low power mode)
//[3:2] : enable M4 virtual PGC power up/down with M4 LPM
//[1:0] : M4 LPM STOP mode
//SLPCR
reg32_write(GPC_IPS_BASE_ADDR + 0x14,0xe000ffA7) ;
//[31] : enable DSM
//[30] : eneable regulator bypass
//[5:3] : wait 64 ckil clock cycles
//[2] : enable PMIC standby
//[1] : enable OSC power down
//[0] : bypass PMIC ready handshake
//PGC_ACK_SEL_A53
reg32_write(GPC_IPS_BASE_ADDR + 0x24,0x00010004) ;
//[2] : A53_SCU PGC as LPM power down ack
//[16] : A53_C0 PGC as LPM power up ack
//PGC_ACK_SEL_M4
reg32_write(GPC_IPS_BASE_ADDR + 0x28,0x00010001) ;
//[0] : M4 virtual PGC as M4 LPM power down ack
//[16] : M4 virtual PGC as M4 LPM power up ack
//GPC_MISC
reg32_write(GPC_IPS_BASE_ADDR + 0x2C,reg32_read(GPC_IPS_BASE_ADDR + 0x2C) | 0x100) ;
//[8] : not mask M4 power down request to M4 virtual PGC
//SLT_CFG0
reg32_write(GPC_IPS_BASE_ADDR + 0xB0,0x00000155) ;
//[6]/[4]/[2]/[0] : A53_C0/A53_C1/ A53_C2/A53_C3 power down in SLOT0
//[8] : A53_SCU power down in SLOT0
//SLT_CFG0_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x200,0x0001001) ;
//[0] : power down in SLOT0
//[12] : M4 virtual PGC power down in SLOT0
//A53_Cx/SCU are power down in same slot. Special setting is required( see below PGC setting
#A )
//SLT_CFG1_PU
reg32_write(GPC_IPS_BASE_ADDR + 0x204,0x00002002) ;
//[2] : power up in SLOT1
//[13] : M4 virtual PGC power up in SLOT1
//SLT_CFG2
reg32_write(GPC_IPS_BASE_ADDR + 0xB8,0x00000202) ;
//[9] : A53_SCU power up in SLOT1
//[1] : A53_C0 power up in SLOT1, A53_C1/ A53_C2/ A53_C3 not power up
//A53_Cx/SCU are power up in same slot. Special setting is required( see below PGC setting
#B )
//PGC_CPU_MAPPING
reg32_write(GPC_IPS_BASE_ADDR + 0xEC,0x00010001) ;
//[0] : MIX PGC mapping to A53 LPM
//[16] : MIX PGC mapping to M4 LPM
//Special PGC setting #A for C0/C1/SCU power down in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x808, (reg32_read(GPC_IPS_BASE_ADDR +0x808) & 0xFFFFC0C0) |
0x0801 ) ;
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// set C0.ISO2SW = 8 ; C0.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C1.ISO2SW = 8 ; C1.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x848, (reg32_read(GPC_IPS_BASE_ADDR +0x848) & 0xFFFFC0C0) |
0x0801 ) ;
// set C2.ISO2SW = 8 ; C2.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x888, (reg32_read(GPC_IPS_BASE_ADDR +0x888) & 0xFFFFC0C0) |
0x0801 ) ;
// set C3.ISO2SW = 8 ; C3.ISO = 1;
reg32_write(GPC_IPS_BASE_ADDR +0x908, (reg32_read(GPC_IPS_BASE_ADDR +0x908) & 0xFFFFC0C0) |
0x1001 ) ;
// set SCU.ISO2SW = 16 ; SCU.ISO = 1;
//Special PGC setting #B for A53_Cx/SCU power up in same slot(SCU should be always ON
comparing to C0/C1/C2/C3)
reg32_write(GPC_IPS_BASE_ADDR +0x804, (reg32_read(GPC_IPS_BASE_ADDR +0x804) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C0.SW = 0x10 ; C0.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C1.SW = 0x10 ; C1.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x844, (reg32_read(GPC_IPS_BASE_ADDR +0x844) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C2.SW = 0x10 ; C2.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x884, (reg32_read(GPC_IPS_BASE_ADDR +0x884) & 0xFF800040) |
0x10 | (0x1f lt:lt: 7) ) ;
// set C3.SW = 0x10 ; C3.SW2ISO = 0x1f ;
reg32_write(GPC_IPS_BASE_ADDR +0x904, (reg32_read(GPC_IPS_BASE_ADDR +0x904) & 0xFF800040) |
0x1 | (0x0f lt:lt: 7) ) ;
// set SCU.SW = 0x1 ; SCU.SW2ISO = 0x0f ;
//A53 PGC
reg32_write(GPC_IPS_BASE_ADDR +0x800, reg32_read(GPC_IPS_BASE_ADDR +0x800) | 0x00000001) ;
// enable A53_C0 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C1 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x840, reg32_read(GPC_IPS_BASE_ADDR +0x840) | 0x00000001) ;
// enable A53_C2 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x880, reg32_read(GPC_IPS_BASE_ADDR +0x880) | 0x00000001) ;
// enable A53_C3 PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x900, reg32_read(GPC_IPS_BASE_ADDR +0x900) | 0x00000001) ;
// enable A53_SCU PGC power down
reg32_write(GPC_IPS_BASE_ADDR +0x910, (0x59 lt:lt: 10) | 0x5B | (0x51 lt:lt: 20) ) ;
// change nL2retn/mempwr/dftram to meet SCU power up timing
// PGC
reg32_write(GPC_IPS_BASE_ADDR +0xA00, reg32_read(GPC_IPS_BASE_ADDR +0xA00) | 0x00000001) ;
// enable MIX PGC power down
5.2.9.4 Example Code 4
// software power up/down PCIE PHY
//power up PCIE PHY
reg32_write ( GPC_IPS_BASE_ADDR + 0xEC, reg32_read(GPC_IPS_BASE_ADDR + 0x0EC) | 0x8 );
//map PCIE PGC to A53
reg32_write ( GPC_IPS_BASE_ADDR + 0xF8 , reg32_read(GPC_IPS_BASE_ADDR + 0xF8) | 0x2 );
//trigger sw Power up Request
while( read(GPC_IPS_BASE_ADDR + 0xF8) & 0x2 );
//wait software power up request self clear
//power down PCIE PHY
reg32_write ( GPC_IPS_BASE_ADDR + 0xEC, reg32_read(GPC_IPS_BASE_ADDR + 0x0EC) | 0x8 );
//map PCIE PGC to A53
reg32_write ( GPC_IPS_BASE_ADDR + 0xC40, reg32_read(GPC_IPS_BASE_ADDR + 0xC40) | 0x1 );
// enable PCIE PGC power down
reg32_write ( GPC_IPS_BASE_ADDR + 0x104 , reg32_read(GPC_IPS_BASE_ADDR + 0x104) | 0x2 );
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General Power Controller (GPC)
//trigger sw Power Down Request
while( read(GPC_IPS_BASE_ADDR + 0x104) & 0x2 );
//wait software power down request self clear
5.2.10 GPC Memory Map/Register Definition
Detailed descriptions of each register can be found below.
The total GPC memory map is 4KB
Table 5-10. Memory Regions
Address Range(offset) Region
0x000 - 0x3FF GPC configuration register
0x400 - 0x7FF Reserved
0x800 - 0x9FF CPU and SCU type PGC register base address
0xA000 - 0xAFF MIX type PGC register base address
0xB00 - 0xFFF PU type PGC register base address
Each PGC (CPU type, MIX type, PU type) will occupy 64 Bytes address space, the
specific base address of each PGC are listed as below.
• 0x800 ~ 0x83F : PGC for A53 core0
• 0x840 ~ 0x87F: PGC for A53 core1
• 0x880 ~ 0x8BF: PGC for A53 core2
• 0x8C0 ~ 0x8FF: PGC for A53 core3
• 0x900 ~ 0x93F: PGC for A53 SCU
• 0xA00 ~ 0xA3F: Reserved
• 0xA40 ~ 0xA7F: PGC for NOC mix
• 0xB00 ~ 0xB3F: PGC for MIPI PHY1
• 0xB40 ~ 0xB7F: PGC for PCIE PHY
• 0xB80 ~ 0xBBF: PGC for USB1 PHY
• 0xBC0 ~ 0xBFF: PGC for USB2 PHY
• 0xC00 ~ 0xC3F: PGC for MLMIX
• 0xC40 ~ 0xC7F: PGC for AUDIOMIX
• 0xC80 ~ 0xCBF: PGC for GPU2D
• 0xCC0 ~ 0xCFF: PGC for GPU Share Logic
• 0xD00 ~ 0xD3F: PGC for VPUMIX Share Logic
• 0xD40 ~ 0xD7F: PGC for GPU3D
• 0xD80 ~ 0xDBF: PGC for MEDIMIX
• 0xDC0 ~ 0xDFF: PGC for VPU G1
• 0xE00 ~ 0xE3F: PGC for VPU G2
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• 0xE40 ~ 0xE7F: PGC for VPU VC8000E
• 0xE80 ~ 0xEBF: PGC for HDMIMIX
• 0xEC0 ~ 0xEFF: PGC for HDMI PHY
• 0xF00 ~ 0xF3F: PGC for MIPI PHY2
• 0xF40 ~ 0xF7F: PGC for HSIOMIX
• 0xF80 ~ 0xFBF: PGC for Media ISP DWP
• 0xFC0 ~ 0xFFF: PGC for DDRMIX
For more specific information about PGC register definition, please see the register
definition for each PGC.
GPC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Basic Low power control register of A53 platform
303A_0000 32 R/W 0000_3FF0h 5.2.10.1/602
(GPC_LPCR_A53_BSC)
Advanced Low power control register of A53 platform
303A_0004 32 R/W 0000_0020h 5.2.10.2/605
(GPC_LPCR_A53_AD)
303A_0008 Low power control register of CPU1 (GPC_LPCR_M7) 32 R/W 0000_3FF0h 5.2.10.3/607
303A_0014 System low power control register (GPC_SLPCR) 32 R/W E000_FF82h 5.2.10.4/609
303A_0018 MASTER LPM Handshake (GPC_MST_CPU_MAPPING) 32 R/W 0000_00FFh 5.2.10.5/612
303A_0020 Memory low power control register (GPC_MLPCR) 32 R/W 0101_0100h 5.2.10.6/613
PGC acknowledge signal selection of A53 platform
303A_0024 32 R/W 8000_8000h 5.2.10.7/614
(GPC_PGC_ACK_SEL_A53)
PGC acknowledge signal selection of M7 platform
303A_0028 32 R/W 8000_8000h 5.2.10.8/616
(GPC_PGC_ACK_SEL_M7)
303A_002C GPC Miscellaneous register (GPC_MISC) 32 R/W 0000_0021h 5.2.10.9/617
IRQ masking register 1 of A53 core0 5.2.10.10/
303A_0030 32 R/W 0000_0000h
(GPC_IMR1_CORE0_A53) 619
IRQ masking register 2 of A53 core0 5.2.10.11/
303A_0034 32 R/W 0000_0000h
(GPC_IMR2_CORE0_A53) 619
IRQ masking register 3 of A53 core0 5.2.10.12/
303A_0038 32 R/W 0000_0000h
(GPC_IMR3_CORE0_A53) 619
IRQ masking register 4 of A53 core0 5.2.10.13/
303A_003C 32 R/W 0000_0000h
(GPC_IMR4_CORE0_A53) 620
IRQ masking register 5 of A53 core0 5.2.10.14/
303A_0040 32 R/W 0000_0000h
(GPC_IMR5_CORE0_A53) 620
IRQ masking register 1 of A53 core1 5.2.10.15/
303A_0044 32 R/W 0000_0000h
(GPC_IMR1_CORE1_A53) 621
IRQ masking register 2 of A53 core1 5.2.10.16/
303A_0048 32 R/W 0000_0000h
(GPC_IMR2_CORE1_A53) 621
IRQ masking register 3 of A53 core1 5.2.10.17/
303A_004C 32 R/W 0000_0000h
(GPC_IMR3_CORE1_A53) 622
IRQ masking register 4 of A53 core1 5.2.10.18/
303A_0050 32 R/W 0000_0000h
(GPC_IMR4_CORE1_A53) 622
Table continues on the next page...
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General Power Controller (GPC)
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
IRQ masking register 5 of A53 core1 5.2.10.19/
303A_0054 32 R/W 0000_0000h
(GPC_IMR5_CORE1_A53) 622
5.2.10.20/
303A_0058 IRQ masking register 1 of M7 (GPC_IMR1_M7) 32 R/W 0000_0000h
623
5.2.10.21/
303A_005C IRQ masking register 2 of M7 (GPC_IMR2_M7) 32 R/W 0000_0000h
623
5.2.10.22/
303A_0060 IRQ masking register 3 of M7 (GPC_IMR3_M7) 32 R/W 0000_0000h
624
5.2.10.23/
303A_0064 IRQ masking register 4 of M7 (GPC_IMR4_M7) 32 R/W 0000_0000h
624
5.2.10.24/
303A_0068 IRQ masking register 5 of M7 (GPC_IMR5_M7) 32 R/W 0000_0000h
624
5.2.10.25/
303A_0080 IRQ status register 1 of A53 (GPC_ISR1_A53) 32 R 0000_0000h
625
5.2.10.26/
303A_0084 IRQ status register 2 of A53 (GPC_ISR2_A53) 32 R 0000_0000h
625
5.2.10.27/
303A_0088 IRQ status register 3 of A53 (GPC_ISR3_A53) 32 R 0000_0000h
626
5.2.10.28/
303A_008C IRQ status register 4 of A53 (GPC_ISR4_A53) 32 R 0000_0000h
626
5.2.10.29/
303A_0090 IRQ status register 5 of A53 (GPC_ISR5_A53) 32 R 0000_0000h
626
5.2.10.30/
303A_0094 IRQ status register 1 of M7 (GPC_ISR1_M7) 32 R 0000_0000h
627
5.2.10.31/
303A_0098 IRQ status register 2 of M7 (GPC_ISR2_M7) 32 R 0000_0000h
627
5.2.10.32/
303A_009C IRQ status register 3 of M7 (GPC_ISR3_M7) 32 R 0000_0000h
627
5.2.10.33/
303A_00A0 IRQ status register 4 of M7 (GPC_ISR4_M7) 32 R 0000_0000h
628
5.2.10.34/
303A_00A4 IRQ status register 5 of M7 (GPC_ISR5_M7) 32 R 0000_0000h
628
CPU PGC software power up trigger 5.2.10.35/
303A_00D0 32 R/W 0000_0000h
(GPC_CPU_PGC_SW_PUP_REQ) 629
MIX PGC software power up trigger 5.2.10.36/
303A_00D4 32 R/W 0000_0000h
(GPC_MIX_PGC_SW_PUP_REQ) 630
PU PGC software up trigger 5.2.10.37/
303A_00D8 32 R/W 0000_0000h
(GPC_PU_PGC_SW_PUP_REQ) 630
CPU PGC software down trigger 5.2.10.38/
303A_00DC 32 R/W 0000_0000h
(GPC_CPU_PGC_SW_PDN_REQ) 632
MIX PGC software power down trigger 5.2.10.39/
303A_00E0 32 R/W 0000_0000h
(GPC_MIX_PGC_SW_PDN_REQ) 633
PU PGC software down trigger 5.2.10.40/
303A_00E4 32 R/W 0000_0000h
(GPC_PU_PGC_SW_PDN_REQ) 634
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Advanced Low power control register of CM4 platform 5.2.10.41/
303A_00EC 32 R 0000_0000h
(GPC_GPC_LPCR_CM4_AD) 637
CPU PGC software up trigger status1 5.2.10.42/
303A_0108 32 R 0000_0000h
(GPC_CPU_PGC_PUP_STATUS1) 638
A53 MIX software up trigger status register 5.2.10.43/
303A_010C 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS0) 640
A53 MIX software up trigger status register 5.2.10.43/
303A_0110 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS1) 640
A53 MIX software up trigger status register 5.2.10.43/
303A_0114 32 R 0000_0000h
(GPC_A53_MIX_PGC_PUP_STATUS2) 640
M7 MIX PGC software up trigger status register 5.2.10.44/
303A_0118 32 R 0000_0000h
(GPC_M7_MIX_PGC_PUP_STATUS0) 641
M7 MIX PGC software up trigger status register 5.2.10.44/
303A_011C 32 R 0000_0000h
(GPC_M7_MIX_PGC_PUP_STATUS1) 641
M7 MIX PGC software up trigger status register 5.2.10.44/
303A_0120 32 R 0000_0000h
(GPC_M7_MIX_PGC_PUP_STATUS2) 641
A53 PU software up trigger status register 5.2.10.45/
303A_0124 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS0) 643
A53 PU software up trigger status register 5.2.10.45/
303A_0128 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS1) 643
A53 PU software up trigger status register 5.2.10.45/
303A_012C 32 R 0000_0000h
(GPC_A53_PU_PGC_PUP_STATUS2) 643
M7 PU PGC software up trigger status register 5.2.10.46/
303A_0130 32 R 0000_0000h
(GPC_M7_PU_PGC_PUP_STATUS0) 647
M7 PU PGC software up trigger status register 5.2.10.46/
303A_0134 32 R 0000_0000h
(GPC_M7_PU_PGC_PUP_STATUS1) 647
M7 PU PGC software up trigger status register 5.2.10.46/
303A_0138 32 R 0000_0000h
(GPC_M7_PU_PGC_PUP_STATUS2) 647
CPU PGC software dn trigger status1 5.2.10.47/
303A_013C 32 R 0000_0000h
(GPC_CPU_PGC_PDN_STATUS1) 651
A53 MIX software down trigger status register 5.2.10.48/
303A_0140 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS0) 653
A53 MIX software down trigger status register 5.2.10.48/
303A_0144 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS1) 653
A53 MIX software down trigger status register 5.2.10.48/
303A_0148 32 R 0000_0000h
(GPC_A53_MIX_PGC_PDN_STATUS2) 653
M7 MIX PGC software power down trigger status register 5.2.10.49/
303A_014C 32 R 0000_0000h
(GPC_M7_MIX_PGC_PDN_STATUS0) 654
M7 MIX PGC software power down trigger status register 5.2.10.49/
303A_0150 32 R 0000_0000h
(GPC_M7_MIX_PGC_PDN_STATUS1) 654
M7 MIX PGC software power down trigger status register 5.2.10.49/
303A_0154 32 R 0000_0000h
(GPC_M7_MIX_PGC_PDN_STATUS2) 654
A53 PU PGC software down trigger status 5.2.10.50/
303A_0158 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS0) 656
Table continues on the next page...
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General Power Controller (GPC)
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
A53 PU PGC software down trigger status 5.2.10.50/
303A_015C 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS1) 656
A53 PU PGC software down trigger status 5.2.10.50/
303A_0160 32 R 0000_0000h
(GPC_A53_PU_PGC_PDN_STATUS2) 656
M7 PU PGC software down trigger status 5.2.10.51/
303A_0164 32 R 0000_0000h
(GPC_M7_PU_PGC_PDN_STATUS0) 660
M7 PU PGC software down trigger status 5.2.10.51/
303A_0168 32 R 0000_0000h
(GPC_M7_PU_PGC_PDN_STATUS1) 660
M7 PU PGC software down trigger status 5.2.10.51/
303A_016C 32 R 0000_0000h
(GPC_M7_PU_PGC_PDN_STATUS2) 660
5.2.10.52/
303A_0170 A53 MIX PDN FLG (GPC_A53_MIX_PDN_FLG) 32 R/W 0000_0000h
664
5.2.10.53/
303A_0174 A53 PU PDN FLG (GPC_A53_PU_PDN_FLG) 32 R/W 0000_0000h
665
5.2.10.54/
303A_0178 M7 MIX PDN FLG (GPC_M7_MIX_PDN_FLG) 32 R/W 0000_0000h
666
5.2.10.55/
303A_017C M7 PU PDN FLG (GPC_M7_PU_PDN_FLG) 32 R/W 0000_0000h
667
Basic Low power control register of A53 platform 5.2.10.56/
303A_0180 32 R/W 0000_0000h
(GPC_LPCR_A53_BSC2) 667
5.2.10.57/
303A_0190 Power handshake register (GPC_PU_PWRHSK) 32 R/W 0000_FFFFh
669
IRQ masking register 1 of A53 core2 5.2.10.58/
303A_0194 32 R/W 0000_0000h
(GPC_IMR1_CORE2_A53) 673
IRQ masking register 2 of A53 core2 5.2.10.59/
303A_0198 32 R/W 0000_0000h
(GPC_IMR2_CORE2_A53) 673
IRQ masking register 3 of A53 core2 5.2.10.60/
303A_019C 32 R/W 0000_0000h
(GPC_IMR3_CORE2_A53) 674
IRQ masking register 4 of A53 core2 5.2.10.61/
303A_01A0 32 R/W 0000_0000h
(GPC_IMR4_CORE2_A53) 674
IRQ masking register 5 of A53 core2 5.2.10.62/
303A_01A4 32 R/W 0000_0000h
(GPC_IMR5_CORE2_A53) 675
IRQ masking register 1 of A53 core3 5.2.10.63/
303A_01A8 32 R/W 0000_0000h
(GPC_IMR1_CORE3_A53) 675
IRQ masking register 2 of A53 core3 5.2.10.64/
303A_01AC 32 R/W 0000_0000h
(GPC_IMR2_CORE3_A53) 676
IRQ masking register 3 of A53 core3 5.2.10.65/
303A_01B0 32 R/W 0000_0000h
(GPC_IMR3_CORE3_A53) 676
IRQ masking register 4 of A53 core3 5.2.10.66/
303A_01B4 32 R/W 0000_0000h
(GPC_IMR4_CORE3_A53) 677
IRQ masking register 5 of A53 core3 5.2.10.67/
303A_01B8 32 R/W 0000_0000h
(GPC_IMR5_CORE3_A53) 677
PGC acknowledge signal selection of A53 platform for PUs 5.2.10.68/
303A_01BC 32 R/W 0000_0000h
(GPC_ACK_SEL_A53_PU) 678
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
PGC acknowledge signal selection of A53 platform for PUs 5.2.10.69/
303A_01C0 32 R/W 0000_0000h
(GPC_ACK_SEL_A53_PU1) 681
PGC acknowledge signal selection of M7 platform for PUs 5.2.10.70/
303A_01C4 32 R/W 0000_0000h
(GPC_ACK_SEL_M7_PU) 682
PGC acknowledge signal selection of M7 platform for PUs 5.2.10.71/
303A_01C8 32 R/W 0000_0000h
(GPC_ACK_SEL_M7_PU1) 685
5.2.10.72/
303A_01CC PGC CPU A53 mapping (GPC_PGC_CPU_A53_MAPPING) 32 R/W 0000_0000h
687
5.2.10.73/
303A_01D0 PGC CPU M7 mapping (GPC_PGC_CPU_M7_MAPPING) 32 R/W 0000_0000h
689
5.2.10.74/
303A_0200 Slot configure register for CPUs (GPC_SLT0_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0204 Slot configure register for CPUs (GPC_SLT1_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0208 Slot configure register for CPUs (GPC_SLT2_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_020C Slot configure register for CPUs (GPC_SLT3_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0210 Slot configure register for CPUs (GPC_SLT4_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0214 Slot configure register for CPUs (GPC_SLT5_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0218 Slot configure register for CPUs (GPC_SLT6_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_021C Slot configure register for CPUs (GPC_SLT7_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0220 Slot configure register for CPUs (GPC_SLT8_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0224 Slot configure register for CPUs (GPC_SLT9_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0228 Slot configure register for CPUs (GPC_SLT10_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_022C Slot configure register for CPUs (GPC_SLT11_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0230 Slot configure register for CPUs (GPC_SLT12_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0234 Slot configure register for CPUs (GPC_SLT13_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0238 Slot configure register for CPUs (GPC_SLT14_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_023C Slot configure register for CPUs (GPC_SLT15_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0240 Slot configure register for CPUs (GPC_SLT16_CFG) 32 R/W 0000_0000h
692
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 549
General Power Controller (GPC)
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.10.74/
303A_0244 Slot configure register for CPUs (GPC_SLT17_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0248 Slot configure register for CPUs (GPC_SLT18_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_024C Slot configure register for CPUs (GPC_SLT19_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0250 Slot configure register for CPUs (GPC_SLT20_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0254 Slot configure register for CPUs (GPC_SLT21_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0258 Slot configure register for CPUs (GPC_SLT22_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_025C Slot configure register for CPUs (GPC_SLT23_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0260 Slot configure register for CPUs (GPC_SLT24_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0264 Slot configure register for CPUs (GPC_SLT25_CFG) 32 R/W 0000_0000h
692
5.2.10.74/
303A_0268 Slot configure register for CPUs (GPC_SLT26_CFG) 32 R/W 0000_0000h
692
5.2.10.75/
303A_0280 Slot configure register for PGC PUs (GPC_SLT0_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0284 32 R/W 0000_0000h
(GPC_SLT0_CFG_PU1) 698
5.2.10.75/
303A_0288 Slot configure register for PGC PUs (GPC_SLT1_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_028C 32 R/W 0000_0000h
(GPC_SLT1_CFG_PU1) 698
5.2.10.75/
303A_0290 Slot configure register for PGC PUs (GPC_SLT2_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0294 32 R/W 0000_0000h
(GPC_SLT2_CFG_PU1) 698
5.2.10.75/
303A_0298 Slot configure register for PGC PUs (GPC_SLT3_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_029C 32 R/W 0000_0000h
(GPC_SLT3_CFG_PU1) 698
5.2.10.75/
303A_02A0 Slot configure register for PGC PUs (GPC_SLT4_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02A4 32 R/W 0000_0000h
(GPC_SLT4_CFG_PU1) 698
5.2.10.75/
303A_02A8 Slot configure register for PGC PUs (GPC_SLT5_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02AC 32 R/W 0000_0000h
(GPC_SLT5_CFG_PU1) 698
Table continues on the next page...
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550 NXP Semiconductors
Chapter 5 Clocks and Power Management
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.10.75/
303A_02B0 Slot configure register for PGC PUs (GPC_SLT6_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02B4 32 R/W 0000_0000h
(GPC_SLT6_CFG_PU1) 698
5.2.10.75/
303A_02B8 Slot configure register for PGC PUs (GPC_SLT7_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02BC 32 R/W 0000_0000h
(GPC_SLT7_CFG_PU1) 698
5.2.10.75/
303A_02C0 Slot configure register for PGC PUs (GPC_SLT8_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02C4 32 R/W 0000_0000h
(GPC_SLT8_CFG_PU1) 698
5.2.10.75/
303A_02C8 Slot configure register for PGC PUs (GPC_SLT9_CFG_PU) 32 R/W 0000_0000h
694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02CC 32 R/W 0000_0000h
(GPC_SLT9_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02D0 32 R/W 0000_0000h
(GPC_SLT10_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02D4 32 R/W 0000_0000h
(GPC_SLT10_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02D8 32 R/W 0000_0000h
(GPC_SLT11_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02DC 32 R/W 0000_0000h
(GPC_SLT11_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02E0 32 R/W 0000_0000h
(GPC_SLT12_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02E4 32 R/W 0000_0000h
(GPC_SLT12_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02E8 32 R/W 0000_0000h
(GPC_SLT13_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02EC 32 R/W 0000_0000h
(GPC_SLT13_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02F0 32 R/W 0000_0000h
(GPC_SLT14_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02F4 32 R/W 0000_0000h
(GPC_SLT14_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_02F8 32 R/W 0000_0000h
(GPC_SLT15_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_02FC 32 R/W 0000_0000h
(GPC_SLT15_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0300 32 R/W 0000_0000h
(GPC_SLT16_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0304 32 R/W 0000_0000h
(GPC_SLT16_CFG_PU1) 698
Table continues on the next page...
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NXP Semiconductors 551
General Power Controller (GPC)
GPC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Slot configure register for PGC PUs 5.2.10.75/
303A_0308 32 R/W 0000_0000h
(GPC_SLT17_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_030C 32 R/W 0000_0000h
(GPC_SLT17_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0310 32 R/W 0000_0000h
(GPC_SLT18_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0314 32 R/W 0000_0000h
(GPC_SLT18_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0318 32 R/W 0000_0000h
(GPC_SLT19_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_031C 32 R/W 0000_0000h
(GPC_SLT19_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0320 32 R/W 0000_0000h
(GPC_SLT20_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0324 32 R/W 0000_0000h
(GPC_SLT20_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0328 32 R/W 0000_0000h
(GPC_SLT21_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_032C 32 R/W 0000_0000h
(GPC_SLT21_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0330 32 R/W 0000_0000h
(GPC_SLT22_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0334 32 R/W 0000_0000h
(GPC_SLT22_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0338 32 R/W 0000_0000h
(GPC_SLT23_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_033C 32 R/W 0000_0000h
(GPC_SLT23_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0340 32 R/W 0000_0000h
(GPC_SLT24_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0344 32 R/W 0000_0000h
(GPC_SLT24_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0348 32 R/W 0000_0000h
(GPC_SLT25_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_034C 32 R/W 0000_0000h
(GPC_SLT25_CFG_PU1) 698
Slot configure register for PGC PUs 5.2.10.75/
303A_0350 32 R/W 0000_0000h
(GPC_SLT26_CFG_PU) 694
Extended slot configure register for PGC PUs 5.2.10.76/
303A_0354 32 R/W 0000_0000h
(GPC_SLT26_CFG_PU1) 698
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552 NXP Semiconductors
Chapter 5 Clocks and Power Management
5.2.10.1 Basic Low power control register of A53 platform
(GPC_LPCR_A53_BSC)
NOTE
LPCR_A53_BSC[CPU_CLK_ON_LPM] should be set 1’b1
when using A53 low power debug feature
NOTE
Always set LPM1/LPM0 with same value
Address: 303A_0000h base + 0h offset = 303A_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK_DSM_TRIGGER
IRQ_SRC_A53_WUP
MASK_CORE3_WFI
MASK_CORE2_WFI
MASK_CORE1_WFI
MASK_CORE0_WFI
MASK_L2CC_WFI
R MASK_SCU_WFI
IRQ_SRC_C1
IRQ_SRC_C0
IRQ_SRC_C3
IRQ_SRC_C2
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST2_LPM_HSK_MASK
MST1_LPM_HSK_MASK
MST0_LPM_HSK_MASK
CPU_CLK_ON_LPM
R
Reserved
Reserved Reserved LPM1 LPM0
Reset 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
GPC_LPCR_A53_BSC field descriptions
Field Description
31 DSM Trigger Mask
MASK_DSM_
TRIGGER 0 DSM trigger of A53 platform will not be masked
1 DSM trigger of A53 platform will be masked
30 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_A53_ LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
WUP the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.
Table continues on the next page...
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NXP Semiconductors 553
General Power Controller (GPC)
GPC_LPCR_A53_BSC field descriptions (continued)
Field Description
0 LPM wakeup source be “OR” result of LPCR_A53_BSC[IRQ_SRC_C0]/
LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3]
setting
1 LPM wakeup source from external INT[127:0], masked by IMR0
29 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C1 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.
0 core1 wakeup source from external INT[127:0], masked by IMR1 refer to “Power up process for A53
platform” for more specific information
1 core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during low power
mode when this bit is set to 1’b1
28 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C0 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power. See “Power up process for A53
platform” for more specific information.
0 core0 wakeup source from external INT[127:0], masked by IMR0 refer to “Power up process for A53
platform” for more specific information
1 core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during low power
mode when this bit is set to 1’b1
27 This field is reserved.
- Reserved
26 L2 cache controller Wait For Interrupt Mask Register
MASK_L2CC_
WFI 0 WFI for L2 cache controller is not masked
1 WFI for L2 cache controller is masked
25 This field is reserved.
- Reserved
24 SCU Wait For Interrupt Mask Register
MASK_SCU_WFI
0 WFI for SCU is not masked
1 WFI for SCU is masked
23 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C3 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power.
0 core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53
Platform for more specific information.
1 core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during
low power mode when this bit is set to 1'b1.
22 LPCR_A53_BSC[IRQ_SRC_C0], LPCR_A53_BSC[IRQ_SRC_C1], LPCR_A53_BSC[IRQ_SRC_C2],
IRQ_SRC_C2 LPCR_A53_BSC[IRQ_SRC_C3], and LPCR_A53_BSC[IRQ_SRC_A53_WUP] work together to decide
the wake up source for A53 LPM and core0/core1/core2/core3 power.
0 core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53
Platform for more specific information.
1 core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down during
low power mode when this bit is set to 1'b1.
Table continues on the next page...
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554 NXP Semiconductors
Chapter 5 Clocks and Power Management
GPC_LPCR_A53_BSC field descriptions (continued)
Field Description
21–20 This field is reserved.
-
19 CORE3 Wait For Interrupt Mask
MASK_CORE3_
WFI 0 WFI for CORE3 is not masked
1 WFI for CORE3 is masked
18 CORE2 Wait For Interrupt Mask
MASK_CORE2_
WFI 0 WFI for CORE2 is not masked
1 WFI for CORE2 is masked
17 CORE1 Wait For Interrupt Mask
MASK_CORE1_
WFI 0 WFI for CORE1 is not masked
1 WFI for CORE1 is masked
16 CORE0 Wait For Interrupt Mask
MASK_CORE0_
WFI 0 WFI for CORE0 is not masked
1 WFI for CORE0 is masked
15 This field is reserved.
- Reserved
14 Define if A53 clocks will be disabled on wait/stop mode.
CPU_CLK_ON_
LPM 0 A53 clock disabled on wait/stop mode
1 A53 clock enabled on wait/stop mode
13–9 This field is reserved.
- Reserved
8 MASTER2 LPM handshake mask
MST2_LPM_
HSK_MASK MASTER2(supermix2noc ADB) will handshake with GPC in LPM, follow this when you want this master
power off. This bit should use together with MST_CPU_MAPPING[2]
If you want power of supermix2noc ADB, use this setting: LPCR_A53_BSC[8]=0;
MST_CPU_MAPPING[2]=1
Otherwise use: LPCR_A53_BSC[8]=1; MST_CPU_MAPPING[2]=0
0 enable MASTER2 LPM handshake, wait ACK from MASTER2
1 disable MASTER2 LPM handshake, mask ACK from MASTER2
7 MASTER1 LPM handshake mask
MST1_LPM_
HSK_MASK MASTER1(supermix2noc ADB) will handshake with GPC in LPM, follow this when you want this master
power off. This bit should use together with MST_CPU_MAPPING[1]
If you want power of supermix2noc ADB, use this setting: LPCR_A53_BSC[7]=0;
MST_CPU_MAPPING[1]=1
Otherwise use: LPCR_A53_BSC[7]=1; MST_CPU_MAPPING[1]=0
0 enable MASTER1 LPM handshake, wait ACK from MASTER1
1 disable MASTER1 LPM handshake, mask ACK from MASTER1
6 MASTER0 LPM handshake mask
MST0_LPM_
HSK_MASK
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 555
General Power Controller (GPC)
GPC_LPCR_A53_BSC field descriptions (continued)
Field Description
MASTER0(SCU) will handshake with GPC in LPM, follow this when you want this master power off. This
bit should be used together with MST_CPU_MAPPING[0].
If you want power of SCU, use this setting: LPCR_A53_BSC[6]=0; MST_CPU_MAPPING[0]=1
Otherwise use: LPCR_A53_BSC[6]=1; MST_CPU_MAPPING[0]=0
0 enable MASTER0 LPM handshake, wait ACK from MASTER0
1 disable MASTER0 LPM handshake, mask ACK from MASTER0
5–4 This field is reserved.
- Reserved
3–2 CORE1 Setting the low power mode that system will enter on next assertion of dsm_request signal.
LPM1
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
LPM0 CORE0 Setting the low power mode that system will enter on next assertion of dsm_request signal.
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
5.2.10.2 Advanced Low power control register of A53 platform
(GPC_LPCR_A53_AD)
Address: 303A_0000h base + 4h offset = 303A_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_C3_WFI_
EN_C2_WFI_
EN_C3_IRQ_
EN_C2_IRQ_
R
EN_ EN_ EN_ EN_
L2PGE
PDN
PDN
PUP
PUP
Reserved C3_ C2_ Reserved C3_ C2_
PUP PUP PDN PDN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN_PLAT_PDN
EN_C1_WFI_
EN_C0_WFI_
EN_C1_IRQ_
EN_C0_IRQ_
EN_L2_WFI_
R
EN_ EN_ EN_ EN_
PDN
PDN
PDN
PUP
PUP
Reserved C1_ C0_ Reserved C1_ C0_
PUP PUP PDN PDN
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
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Chapter 5 Clocks and Power Management
GPC_LPCR_A53_AD field descriptions
Field Description
31 0 L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
L2PGE 1 L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF
mode)
30–28 This field is reserved.
- Reserved
27 0 CORE3 will not power up with lower power mode request
EN_C3_PUP 1 CORE3 will power up with low power mode request (only used wake up from CPU_OFF)
26 0 CORE3 will not power up with IRQ request
EN_C3_IRQ_ 1 CORE3 will power up with IRQ request
PUP
25 0 CORE2 will not power up with lower power mode request
EN_C2_PUP 1 CORE2 will power up with low power mode request (only used wake up from CPU_OFF)
24 0 CORE2 will not power up with IRQ request
EN_C2_IRQ_ 1 CORE2 will power up with IRQ request
PUP
23–20 This field is reserved.
- Reserved
19 0 CORE3 will not be power down with low power mode request
EN_C3_PDN 1 CORE3 will be power down with low power mode request
18 0 CORE3 will not be power down with WFI request
EN_C3_WFI_ 1 CORE3 will be power down with WFI request
PDN
17 0 CORE2 will not be power down with low power mode request
EN_C2_PDN 1 CORE2 will be power down with low power mode request
16 0 CORE2 will not be power down with WFI request
EN_C2_WFI_ 1 CORE2 will be power down with WFI request
PDN
15–12 This field is reserved.
- Reserved
11 0 CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
EN_C1_PUP 1 CORE1 will power up with low power mode request
10 0 CORE1 will not power up with IRQ request
EN_C1_IRQ_ 1 CORE1 will power up with IRQ request
PUP
9 (only used wake up from CPU01_OFF mode)
EN_C0_PUP
0 CORE0 will not power up with low power mode request
1 CORE0 will power up with low power mode request
8 0 CORE0 will not power up with IRQ request
EN_C0_IRQ_ 1 CORE0 will power up with IRQ request
PUP
7–6 This field is reserved.
- Reserved
5
EN_L2_WFI_ NOTE: Before reset, L2 WFI is 1 and make GPC generate an error DSM request. This bit is used to
PDN mask the L2 WFI before reset. After reset, L2 WFI change to 0, and functions are OK, SW must
clear this bit at the beginning of code.
Table continues on the next page...
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NXP Semiconductors 557
General Power Controller (GPC)
GPC_LPCR_A53_AD field descriptions (continued)
Field Description
0 SCU and L2 will be power down with WFI request
1 SCU and L2 will not be power down with WFI request (default)
4 0 SCU and L2 cache RAM will not be power down with low power mode request
EN_PLAT_PDN 1 SCU and L2 cache RAM will be power down with low power mode request
3 0 CORE1 will not be power down with low power mode request
EN_C1_PDN 1 CORE1 will be power down with low power mode request
2 0 CORE1 will not be power down with WFI request
EN_C1_WFI_ 1 CORE1 will be power down with WFI request
PDN
1 0 CORE0 will not be power down with low power mode request
EN_C0_PDN 1 CORE0 will be power down with low power mode request
0 0 CORE0 will not be power down with WFI request
EN_C0_WFI_ 1 CORE0 will be power down with WFI request
PDN
5.2.10.3 Low power control register of CPU1 (GPC_LPCR_M7)
Address: 303A_0000h base + 8h offset = 303A_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK_DSM_TRIGGER
MASK_M7_WFI
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_CLK_ON_LPM
R
Reserved
EN_ EN_
Reserved M7_ M7_ LPM0
PUP PDN
W
Reset 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0
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GPC_LPCR_M7 field descriptions
Field Description
31 M7 WFI Mask
MASK_DSM_
TRIGGER 0 DSM trigger of M7 platform will not be masked
1 DSM trigger of M7 platform will be masked
30–17 This field is reserved.
- Reserved
16 M7 WFI Mask
MASK_M7_WFI
0 WFI for M7 is not masked
1 WFI for M7 is masked
15 This field is reserved.
- Reserved
14 Define if M7 clocks will be disabled on wait/stop mode.
CPU_CLK_ON_
LPM 0 M7 clock disabled on wait/stop mode.
1 M7 clock enabled on wait/stop mode.
13–4 This field is reserved.
- Reserved
3 Enable M7 virtual PGC power up with LPM enter
EN_M7_PUP
2 Enable M7 virtual PGC power down with LPM enter
EN_M7_PDN
LPM0 Setting the low power mode that system will enter on next assertion of dsm_request signal.
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
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General Power Controller (GPC)
5.2.10.4 System low power control register (GPC_SLPCR)
NOTE
SLPCR[VSTBY] must be set to 1’b1 if SLPCR[RBC_EN] is
set to 1’b1; SLPCR[SBYOS] must be set to 1’b1 if
SLPCR[VSTBY] is set to 1’b1.
Address: 303A_0000h base + 14h offset = 303A_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN_M7_FASTWUP_WA
DISABLE_A53_IS_DSM
EN_A53_FASTWUP_W
EN_M7_FASTWUP_ST
EN_A53_FASTWUP_S
R
TOP_MODE
AIT_MODE
OP_MODE
IT_MODE
EN_DSM
RBC_EN
REG_BYPASS_COUNT Reserved
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6
COSC_PWRDOWN 5 4 3 2 1 0
BYPASS_PMIC_
R
COSC_EN
SBYOS
READY
VSTBY
OSCCNT STBY_COUNT
Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0
GPC_SLPCR field descriptions
Field Description
31 DSM enable
EN_DSM
0 DSM disabled
1 DSM enabled
30 Enable for REG_BYPASS_COUNTER. If enabled, REG_BYPASS signal will be asserted after
RBC_EN REG_BYPASS_COUNT clocks of CKIL, after standby voltage is requested. If standby voltage is not
requested REG_BYPASS won’t be asserted, even if counter is enabled.
0 REG_BYPASS_COUNTER disabled
1 REG_BYPASS_COUNTER enabled
29–24 Counter for REG_BYPASS signal assertion after standby voltage request by PMIC_STBY_REQ.
REG_BYPASS_
COUNT 000000 no delay
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GPC_SLPCR field descriptions (continued)
Field Description
000001 1 CKIL clock period delay
111111 63 CKIL clock period delay
23 0 Enable A53 isolation signal in DSM
DISABLE_A53_I 1 Disable A53 isolation signal in DSM
S_DSM
22–20 This field is reserved.
- Reserved
19 Enable M7 fast wake up stop mode, relevant PLLs will not be closed in this mode.
EN_M7_FASTW
UP_STOP_MOD
E
18 Enable M7 fast wake up wait mode, relevant PLLs will not be closed in this mode.
EN_M7_FASTW
UP_WAIT_MOD
E
17 Enable A53 fast wake up stop mode, relevant PLLs will not be closed in this mode.
EN_A53_FASTW
UP_STOP_MOD
E
16 Enable A53 fast wake up wait mode, relevant PLLs will not be closed in this mode.
EN_A53_FASTW
UP_WAIT_MOD
E
15–8 Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for
OSCCNT oscillator lock time. This is used for oscillator lock time. Current estimation is ~5ms. This counter will be
used in sequence out of DSM and if sbyos bit was defined. GPC will wait the “OSCCNT” number of cycles
before it notify CCM to open the relevant PLLs.
00000000 count 1 ckil
11111111 count 256 ckils
7 On-chip oscillator enable bit - this bit value is reflected on the output cosc_en. The system will start with
COSC_EN on-chip oscillator enabled to supply source for the PLLs. Software can change this bit if a transition to the
bypass PLL clocks was performed for all the PLLs. In cases that this bit is changed from ‘0’ to ‘1’ then
GPC will enable the on-chip oscillator and after counting oscnt ckil clock cycles before it notify CCM to
open the relevant PLLs . The cosc_en bit should be changed only when on-chip oscillator is not chosen as
the clock source.
0 Disable on-chip oscillator
1 Enable on-chip oscillator
6 In run mode, software can manually control powering down of on chip oscillator, i.e. generating ‘1’ on
COSC_ cosc_pwrdown signal. If software manually powered down the on chip oscillator, then sbyos functionality
PWRDOWN for on-chip oscillator will be bypassed.
The manual closing of on-chip oscillator should be performed only in case the reference oscillator is not
the source of all the clocks generation.
0 On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
1 On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
5–3 Standby counter definition. These two bits define, in the case of stop exit (if VSTBY bit was set), the
STBY_COUNT amount of time GPC will wait between PMIC_STBY_REQ negation and the check of assertion of
PMIC_READY.
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General Power Controller (GPC)
GPC_SLPCR field descriptions (continued)
Field Description
000 GPC will wait 4 ckil clock cycles
001 GPC will wait 8 ckil clock cycles
010 GPC will wait 16 ckil clock cycles
011 GPC will wait 32 ckil clock cycles
100 GPC will wait 64 ckil clock cycles
101 GPC will wait 128 ckil clock cycles
110 GPC will wait 256 ckil clock cycles
111 GPC will wait 512 ckil clock cycles
2 Voltage standby request bit. This bit defines if PMIC_STBY_REQ pin, which notifies external power
VSTBY management IC to move from functional voltage to standby voltage, will be asserted in stop mode.
0 Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ
will remain negated - ‘0’)
1 Voltage will be changed to standby voltage after next entrance to stop mode.
1 Standby clock oscillator bit. This bit defines if cosc_pwrdown, which power down the on chip oscillator, will
SBYOS be asserted in DSM.
0 On chip oscillator will not be powered down, after next entrance to DSM.
1 On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM,
external oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after
oscnt count GPC will continue with the exit from DSM process.
0 By asserting this bit GPC will bypass waiting for PMIC_READY signal when coming out of DSM. This
BYPASS_PMIC_ should be used for PMIC’s that don’t support the PMIC_READY signal.
READY
0 Don’t bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode
if standby voltage was enabled
1 Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power mode if
standby voltage was enabled
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5.2.10.5 MASTER LPM Handshake (GPC_MST_CPU_MAPPING)
Address: 303A_0000h base + 18h offset = 303A_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MST2_CPU_
MST1_CPU_
MST0_CPU_
R
MAPPING
MAPPING
MAPPING
Reserved
W
Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GPC_MST_CPU_MAPPING field descriptions
Field Description
31–3 This field is reserved.
- Reserved
2 MASTER2 CPU Mapping
MST2_CPU_
MAPPING noc2supermix ADB LPM handshake mask. This bit should be used together with LPCR_A53_BSC[8].
If you want power of SCU, use this setting: LPCR_A53_BSC[8]=0; MST_CPU_MAPPING[2]=1
Otherwise, use this: LPCR_A53_BSC[8]=1; MST_CPU_MAPPING[2]=0
0 GPC will not send out power off requirement
1 GPC will send out power off requirement
1 MASTER1 CPU Mapping
MST1_CPU_
MAPPING Supermix2noc ADB LPM handshake mask. This bit should be used together with LPCR_A53_BSC[7].
If you want power of SCU, use this setting: LPCR_A53_BSC[7]=0; MST_CPU_MAPPING[1]=1
Otherwise, use this: LPCR_A53_BSC[7]=1; MST_CPU_MAPPING[1]=0
0 GPC will not send out power off requirement
1 GPC will send out power off requirement
0 MASTER0 CPU Mapping
MST0_CPU_
MAPPING SCU LPM handshake mask. This bit should be used together with LPCR_A7_BSC[6].
If you want power of SCU, use this setting: LPCR_A7_BSC[6]=0; MST_CPU_MAPPING[0]=1
Otherwise, use this: LPCR_A7_BSC[6]=1; MST_CPU_MAPPING[0]=0
0 GPC will not send out power off requirement
1 GPC will send out power off requirement
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General Power Controller (GPC)
5.2.10.6 Memory low power control register (GPC_MLPCR)
Address: 303A_0000h base + 20h offset = 303A_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMLP_RET_PGEN MEM_EXT_CNT
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROMLP_PDN_
MEMLP_RET_
MEMLP_CTL_
R
SEL
DIS
DIS
MEMLP_ENT_CNT Reserved
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
GPC_MLPCR field descriptions
Field Description
31–24 Delay counter for “retnx” and “pgen”
MEMLP_RET_
PGEN
23–16 Delay counter to start existing from memory low power
MEM_EXT_CNT
15–8 Delay counter to make sure all clock off after pll_dis_req is issued by smc
MEMLP_ENT_
CNT
7–3 This field is reserved.
- Reserved
2 ROM shut down control
ROMLP_PDN_
DIS 0 Enable ROM shut down control(should also enable RAM low power control);
1 Disable ROM shut down control
1 Retention select
MEMLP_RET_
SEL 0 retention mode 2
1 retention mode 1
0 RAM low-power control
MEMLP_CTL_
DIS 0 Enable RAM low power control
1 Disable RAM low power control
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5.2.10.7 PGC acknowledge signal selection of A53 platform
(GPC_PGC_ACK_SEL_A53)
The register can only be accessed by A53 platform
Address: 303A_0000h base + 24h offset = 303A_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A53_PGC_PDN_
A53_PGC_PUP_
R
ACK
ACK
Reserved
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC_PGC_PDN_
NOC_PGC_PUP_
A53_PLAT_PGC_
A53_PLAT_PGC_
A53_C3_PGC_
A53_C3_PGC_
A53_C2_PGC_
A53_C2_PGC_
A53_C1_PGC_
A53_C1_PGC_
A53_C0_PGC_
A53_C0_PGC_
R
PDN_ACK
PDN_ACK
PDN_ACK
PDN_ACK
PDN_ACK
PUP_ACK
PUP_ACK
PUP_ACK
PUP_ACK
PUP_ACK
ACK
ACK
Reserved Reserved
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_ACK_SEL_A53 field descriptions
Field Description
31 Select power up acknowledge signal of A53 (dummy) PGC as the power up acknowledge for A53 LPM.
A53_PGC_PUP_
ACK
30 Select power down acknowledge signal of A53 (dummy) PGC as the power down acknowledge for A53
A53_PGC_PDN_ LPM.
ACK
29–14 This field is reserved.
- Reserved
13 Select power down acknowledge signal of NOC PGC as the power up acknowledge for A53 LPM.
NOC_PGC_
PUP_ACK
12 Select power down acknowledge signal of NOC PGC as the power down acknowledge for A53 LPM.
NOC_PGC_
PDN_ACK
11–10 This field is reserved.
- Reserved
9 Select power down acknowledge signal of A53 PLATFORM PGC as the power up acknowledge for A53
A53_PLAT_ LPM.
PGC_PUP_ACK
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General Power Controller (GPC)
GPC_PGC_ACK_SEL_A53 field descriptions (continued)
Field Description
8 Select power down acknowledge signal of A53 PLATFORM PGC as the power down acknowledge for A53
A53_PLAT_ LPM.
PGC_PDN_ACK
7 Select power down acknowledge signal of A53 CORE3 PGC as the power up acknowledge for A53 LPM.
A53_C3_PGC_
PUP_ACK
6 Select power down acknowledge signal of A53 CORE3 PGC as the power down acknowledge for A53
A53_C3_PGC_ LPM.
PDN_ACK
5 Select power down acknowledge signal of A53 CORE2 PGC as the power up acknowledge for A53 LPM.
A53_C2_PGC_
PUP_ACK
4 Select power down acknowledge signal of A53 CORE2 PGC as the power down acknowledge for A53
A53_C2_PGC_ LPM.
PDN_ACK
3 Select power down acknowledge signal of A53 CORE1 PGC as the power up acknowledge for A53 LPM.
A53_C1_PGC_
PUP_ACK
2 Select power down acknowledge signal of A53 CORE1 PGC as the power down acknowledge for A53
A53_C1_PGC_ LPM.
PDN_ACK
1 Select power down acknowledge signal of A53 CORE0 PGC as the power up acknowledge for A53 LPM.
A53_C0_PGC_
PUP_ACK
0 Select power down acknowledge signal of A53 CORE0 PGC as the power down acknowledge for A53
A53_C0_PGC_ LPM.
PDN_ACK
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5.2.10.8 PGC acknowledge signal selection of M7 platform
(GPC_PGC_ACK_SEL_M7)
This register can only be accessed by the M7 platform.
NOTE
“dummy” PGC cannot be mapped to time slot control. “virtual”
PGC can be mapped to time slot control. When virtual PGC is
used, below setting is required -
GPC_MISC[M7_PDN_REQ_MASK] should be set to 1’b1 and
arrange virtual GPC in same slot with MIX. power/up slot (See
example code 3). MIX PGC may possibly power down later
than A53 platform power down when virtual PGC is used.
Address: 303A_0000h base + 28h offset = 303A_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M7_DUMMY_PGC_
M7_DUMMY_PGC_
R
PDN_ACK
PUP_ACK
Reserved
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_VIRTUAL_PGC_
M7_VIRTUAL_PGC_
NOC_PGC_PDN_
NOC_PGC_PUP_
PDN_ACK
PUP_ACK
ACK
ACK
Reserved Reserved
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_ACK_SEL_M7 field descriptions
Field Description
31 Select power up acknowledge signal of M7 (dummy) PGC as the power up acknowledge for M7 LPM.
M7_DUMMY_
PGC_PUP_ACK
30 Select power down acknowledge signal of M7 (dummy) PGC as the power down acknowledge for M7
M7_DUMMY_ LPM.
PGC_PDN_ACK
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General Power Controller (GPC)
GPC_PGC_ACK_SEL_M7 field descriptions (continued)
Field Description
29–14 This field is reserved.
- Reserved
13 Select power down acknowledge signal of NOC PGC as the power up acknowledge for M7 LPM.
NOC_PGC_
PUP_ACK
12 Select power down acknowledge signal of NOC PGC as the power down acknowledge for M7 LPM.
NOC_PGC_
PDN_ACK
11–2 This field is reserved.
- Reserved
1 Select power up acknowledge signal of M7 virtual PGC as the power up acknowledge for M7 LPM. M7
M7_VIRTUAL_ virtual PGC only acknowledge power up request in the end of current slot time
PGC_PUP_ACK
0 Select power down acknowledge signal of M7 virtual PGC as the power down acknowledge for M7 LPM.
M7_VIRTUAL_ M7 virtual PGC only acknowledge power down request in the end of current slot time
PGC_PDN_ACK
5.2.10.9 GPC Miscellaneous register (GPC_MISC)
Address: 303A_0000h base + 2Ch offset = 303A_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M7_BYPASS_PUP
MIPI_LDO_EN_
A53_BYPASS_
R
PUP_MASK
_MASK
CTRL
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_PDN_REQ_MA
M7_SLEEP_HOLD
GPC_IRQ_MASK
HOLD_REQ_B
A53_SLEEP_
R
_REQ_B
SK
Reserved Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
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GPC_MISC field descriptions
Field Description
31 MIPI LDO enable control. Default is 1'b1.
MIPI_LDO_EN_
CTRL
30–26 This field is reserved.
- Reserved
25
M7_BYPASS_PU
P_MASK
24
A53_BYPASS_
PUP_MASK
23–9 This field is reserved.
- Reserved
8 M7 power-down mask
M7_PDN_REQ_
MASK 0 M7 power down request to virtual M7 PGC will be masked.
1 M7 power down request to virtual M7 PGC will not be masked. Set this bit to 1’b1 when M7 virtual
PGC is used.
7–6 This field is reserved.
- Reserved
5 GPC interrupt/event masking
GPC_IRQ_MASK
0 Not masked
1 Interrupt / event is masked
4–2 This field is reserved.
- Reserved
1 A53 sleep hold
A53_SLEEP_
HOLD_REQ_B 0 Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
1 Don’t hold A53 platform in sleep mode.
0 M7 sleep hold
M7_SLEEP_HOL
D_REQ_B 0 Hold M7 platform in sleep mode. This bit is a software control bit to M7 platform.
1 Don’t hold M7 platform in sleep mode.
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5.2.10.10 IRQ masking register 1 of A53 core0
(GPC_IMR1_CORE0_A53)
The five IMRn_CORE0_A53 (n = 1,2,3,4,5) registers are used as interrupt mask for A53
core0.
Address: 303A_0000h base + 30h offset = 303A_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1_CORE0_A53 field descriptions
Field Description
IMR1_CORE0_A A53 core0 IRQ[31:0] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.11 IRQ masking register 2 of A53 core0
(GPC_IMR2_CORE0_A53)
Address: 303A_0000h base + 34h offset = 303A_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR2_CORE0_A53 field descriptions
Field Description
IMR2_CORE0_A A53 core0 IRQ[63:32] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.12 IRQ masking register 3 of A53 core0
(GPC_IMR3_CORE0_A53)
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Address: 303A_0000h base + 38h offset = 303A_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR3_CORE0_A53 field descriptions
Field Description
IMR3_CORE0_A A53 core0 IRQ[95:64] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.13 IRQ masking register 4 of A53 core0
(GPC_IMR4_CORE0_A53)
Address: 303A_0000h base + 3Ch offset = 303A_003Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR4_CORE0_A53 field descriptions
Field Description
IMR4_CORE0_A A53 core0 IRQ[127:96] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.14 IRQ masking register 5 of A53 core0
(GPC_IMR5_CORE0_A53)
Address: 303A_0000h base + 40h offset = 303A_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR5_CORE0_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR5_CORE0_A53 field descriptions
Field Description
IMR5_CORE0_A A53 core0 IRQ[159:128] masking bits:
53
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GPC_IMR5_CORE0_A53 field descriptions (continued)
Field Description
0 IRQ not masked
1 IRQ masked
5.2.10.15 IRQ masking register 1 of A53 core1
(GPC_IMR1_CORE1_A53)
The five IMRn_CORE1_A53 (n = 1,2,3,4,5) registers are used as interrupt mask for A53
core1.
Address: 303A_0000h base + 44h offset = 303A_0044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1_CORE1_A53 field descriptions
Field Description
IMR1_CORE1_A A53 core1 IRQ[31:0] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.16 IRQ masking register 2 of A53 core1
(GPC_IMR2_CORE1_A53)
Address: 303A_0000h base + 48h offset = 303A_0048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR2_CORE1_A53 field descriptions
Field Description
IMR2_CORE1_A A53 core1 IRQ[63:32] masking bits:
53
0 IRQ not masked
1 IRQ masked
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5.2.10.17 IRQ masking register 3 of A53 core1
(GPC_IMR3_CORE1_A53)
Address: 303A_0000h base + 4Ch offset = 303A_004Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR3_CORE1_A53 field descriptions
Field Description
IMR3_CORE1_A A53 core1 IRQ[95:64] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.18 IRQ masking register 4 of A53 core1
(GPC_IMR4_CORE1_A53)
Address: 303A_0000h base + 50h offset = 303A_0050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR4_CORE1_A53 field descriptions
Field Description
IMR4_CORE1_A A53 core1 IRQ[127:96] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.19 IRQ masking register 5 of A53 core1
(GPC_IMR5_CORE1_A53)
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General Power Controller (GPC)
Address: 303A_0000h base + 54h offset = 303A_0054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR5_CORE1_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR5_CORE1_A53 field descriptions
Field Description
IMR5_CORE1_A A53 core1 IRQ[159:128] masking bits:
53
0 IRQ not masked
1 IRQ masked
5.2.10.20 IRQ masking register 1 of M7 (GPC_IMR1_M7)
The five IMRn_M7 (n = 1,2,3,4,5) registers are used as interrupt mask for M7.
Address: 303A_0000h base + 58h offset = 303A_0058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_M7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1_M7 field descriptions
Field Description
IMR1_M7 M7 IRQ[31:0] masking bits:
0 IRQ not masked
1 IRQ masked
5.2.10.21 IRQ masking register 2 of M7 (GPC_IMR2_M7)
Address: 303A_0000h base + 5Ch offset = 303A_005Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_M7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR2_M7 field descriptions
Field Description
IMR2_M7 M7 IRQ[63:32] masking bits:
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GPC_IMR2_M7 field descriptions (continued)
Field Description
0 IRQ not masked
1 IRQ masked
5.2.10.22 IRQ masking register 3 of M7 (GPC_IMR3_M7)
Address: 303A_0000h base + 60h offset = 303A_0060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_M7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR3_M7 field descriptions
Field Description
IMR3_M7 M7 IRQ[95:64] masking bits:
0 IRQ not masked
1 IRQ masked
5.2.10.23 IRQ masking register 4 of M7 (GPC_IMR4_M7)
Address: 303A_0000h base + 64h offset = 303A_0064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_M7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR4_M7 field descriptions
Field Description
IMR4_M7 M7 IRQ[127:96] masking bits:
0 IRQ not masked
1 IRQ masked
5.2.10.24 IRQ masking register 5 of M7 (GPC_IMR5_M7)
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General Power Controller (GPC)
Address: 303A_0000h base + 68h offset = 303A_0068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR5_M7
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR5_M7 field descriptions
Field Description
IMR5_M7 M7 IRQ[159:128] masking bits:
0 IRQ not masked
1 IRQ masked
5.2.10.25 IRQ status register 1 of A53 (GPC_ISR1_A53)
The five ISRn_A53 (n = 1,2,3,4,5) registers, all of them are read only register
Address: 303A_0000h base + 80h offset = 303A_0080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR1_A53
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR1_A53 field descriptions
Field Description
ISR1_A53 A53 IRQ[31:0] status
5.2.10.26 IRQ status register 2 of A53 (GPC_ISR2_A53)
Address: 303A_0000h base + 84h offset = 303A_0084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR2_A53
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR2_A53 field descriptions
Field Description
ISR2_A53 A53 IRQ[63:32] status
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5.2.10.27 IRQ status register 3 of A53 (GPC_ISR3_A53)
Address: 303A_0000h base + 88h offset = 303A_0088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR3_A53
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR3_A53 field descriptions
Field Description
ISR3_A53 A53 IRQ[95:64] status
5.2.10.28 IRQ status register 4 of A53 (GPC_ISR4_A53)
Address: 303A_0000h base + 8Ch offset = 303A_008Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR4_A53
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR4_A53 field descriptions
Field Description
ISR4_A53 A53 IRQ[127:96] status
5.2.10.29 IRQ status register 5 of A53 (GPC_ISR5_A53)
Address: 303A_0000h base + 90h offset = 303A_0090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR5_A53
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
GPC_ISR5_A53 field descriptions
Field Description
ISR5_A53 A53 IRQ[159:128] status
5.2.10.30 IRQ status register 1 of M7 (GPC_ISR1_M7)
The five ISRn_M7 (n = 1,2,3,4,5) registers, all of them are read only register
Address: 303A_0000h base + 94h offset = 303A_0094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR1_M7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR1_M7 field descriptions
Field Description
ISR1_M7 M7 IRQ[31:0] status
5.2.10.31 IRQ status register 2 of M7 (GPC_ISR2_M7)
Address: 303A_0000h base + 98h offset = 303A_0098h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR2_M7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR2_M7 field descriptions
Field Description
ISR2_M7 M7 IRQ[63:32] status
5.2.10.32 IRQ status register 3 of M7 (GPC_ISR3_M7)
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Address: 303A_0000h base + 9Ch offset = 303A_009Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR3_M7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR3_M7 field descriptions
Field Description
ISR3_M7 M7 IRQ[95:64] status
5.2.10.33 IRQ status register 4 of M7 (GPC_ISR4_M7)
Address: 303A_0000h base + A0h offset = 303A_00A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR4_M7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR4_M7 field descriptions
Field Description
ISR4_M7 M7 IRQ[127:96] status
5.2.10.34 IRQ status register 5 of M7 (GPC_ISR5_M7)
Address: 303A_0000h base + A4h offset = 303A_00A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ISR5_M7
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ISR5_M7 field descriptions
Field Description
ISR5_M7 M7 IRQ[159:128] status
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General Power Controller (GPC)
5.2.10.35 CPU PGC software power up trigger
(GPC_CPU_PGC_SW_PUP_REQ)
Address: 303A_0000h base + D0h offset = 303A_00D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_SW_PU
CORE2_A53_SW_PU
CORE1_A53_SW_PU
CORE0_A53_SW_PU
SCU_A53_SW_PUP_
R
P_REQ
P_REQ
P_REQ
P_REQ
REQ
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_CPU_PGC_SW_PUP_REQ field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software power up trigger for SCU A53 PGC
SCU_A53_SW_P
UP_REQ
3 Software power up trigger for Core3 A53 PGC
CORE3_A53_S
W_PUP_REQ
2 Software power up trigger for Core2 A53
CORE2_A53_S
W_PUP_REQ
1 Software power up trigger for Core1 A53 PGC
CORE1_A53_S
W_PUP_REQ
0 Software power up trigger for Core0 A53 PGC
CORE0_A53_S
W_PUP_REQ
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5.2.10.36 MIX PGC software power up trigger
(GPC_MIX_PGC_SW_PUP_REQ)
Address: 303A_0000h base + D4h offset = 303A_00D4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC_SW_PUP_
R
MF_S
W_P
REQ
Reserved
UP_R
W EQ
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_MIX_PGC_SW_PUP_REQ field descriptions
Field Description
31–2 This field is reserved.
- Reserved
1 Software power up trigger for NOC PGC
NOC_SW_PUP_
REQ
0 Software power up trigger for MIX PGC
MF_SW_PUP_R
EQ
5.2.10.37 PU PGC software up trigger (GPC_PU_PGC_SW_PUP_REQ)
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General Power Controller (GPC)
Address: 303A_0000h base + D8h offset = 303A_00D8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEDIA_ISP_DWP_SW_
MIPI_PHY2_SW_PUP_
HSIOMIX_SW_PUP_
DDRMIX_SW_PUP_
R
PUP_REQ
REQ
REQ
REQ
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU_3D_SW_PUP_RE
GPU_2D_SW_PUP_RE
VPU_G2_SW_PUP_RE
VPU_G1_SW_PUP_RE
VPU_VC8K_SW_PUP_
VPUMIX_SW_PUP_RE
USB2_PHY_SW_PUP_
USB1_PHY_SW_PUP_
MIPI_PHY1_SW_PUP_
HDMI_PHY_SW_PUP_
GPU_SHARE_LOGIC_
MEDIMIX_SW_PUP_R
AUDIOMIX_SW_PUP_
PCIE_PHY_SW_PUP_
HDMIMIX_SW_PUP_
MLMIX_PHY_SW_
R
SW_PUP_REQ
PUP_REQ
REQ
REQ
REQ
REQ
REQ
REQ
REQ
REQ
EQ
Q
Q
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PU_PGC_SW_PUP_REQ field descriptions
Field Description
31–20 This field is reserved.
- Reserved
19 Software power up trigger for DDRMIX
DDRMIX_SW_
PUP_REQ
18 Software power up trigger for MEDIA_ISP_DWP
MEDIA_ISP_
DWP_SW_PUP_
REQ
17 Software power up trigger for HSIOMIX
HSIOMIX_SW_
PUP_REQ
16 Software power up trigger for MIPI_PHY2
MIPI_PHY2_
SW_PUP_REQ
15 Software power up trigger for HDMI_PHY
HDMI_PHY_SW_
PUP_REQ
14 Software power up trigger for HDMIMIX
HDMIMIX_SW_
PUP_REQ
13 Software power up trigger for VPU_VC8K
VPU_VC8K_SW
_PUP_REQ
Table continues on the next page...
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GPC_PU_PGC_SW_PUP_REQ field descriptions (continued)
Field Description
12 Software power up trigger for VPU_G2
VPU_G2_SW_P
UP_REQ
11 Software power up trigger for VPU_G1
VPU_G1_SW_P
UP_REQ
10 Software power up trigger for MEDIMIX
MEDIMIX_SW_P
UP_REQ
9 Software power up trigger for GPU_3D
GPU_3D_SW_P
UP_REQ
8 Software power up trigger for VPUMIX
VPUMIX_SW_P
UP_REQ
7 Software power up trigger for GPU_SHARE_LOGIC
GPU_SHARE_L
OGIC_SW_PUP_
REQ
6 Software power up trigger for GPU_2D
GPU_2D_SW_P
UP_REQ
5 Software power up trigger for AUDIOMIX
AUDIOMIX_SW_
PUP_REQ
4 Software power up trigger for MLMIX
MLMIX_PHY_
SW_PUP_REQ
3 Software power up trigger for USB2_PHY
USB2_PHY_SW
_PUP_REQ
2 Software power up trigger for USB1_PHY
USB1_PHY_SW
_PUP_REQ
1 Software power up trigger for PCIE_PHY
PCIE_PHY_SW_
PUP_REQ
0 Software power up trigger for MIPI_PHY1
MIPI_PHY1_SW
_PUP_REQ
5.2.10.38 CPU PGC software down trigger
(GPC_CPU_PGC_SW_PDN_REQ)
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General Power Controller (GPC)
Address: 303A_0000h base + DCh offset = 303A_00DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_SW_PU
CORE2_A53_SW_PD
CORE1_A53_SW_PD
CORE0_A53_SW_PD
SCU_A53_SW_PUP_
R
N_REQ
N_REQ
N_REQ
P_REQ
REQ
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_CPU_PGC_SW_PDN_REQ field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software power up trigger for SCU A53 PGC
SCU_A53_SW_P
UP_REQ
3 Software power up trigger for Core3 A53 PGC
CORE3_A53_S
W_PUP_REQ
2 Software power down trigger for Core2 A53 PGC
CORE2_A53_S
W_PDN_REQ
1 Software power down trigger for Core1 A53 PGC
CORE1_A53_S
W_PDN_REQ
0 Software power down trigger for Core0 A53 PGC
CORE0_A53_S
W_PDN_REQ
5.2.10.39 MIX PGC software power down trigger
(GPC_MIX_PGC_SW_PDN_REQ)
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Address: 303A_0000h base + E0h offset = 303A_00E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC_SW_PDN_
MF_SW_PDN_R
R
REQ
EQ
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_MIX_PGC_SW_PDN_REQ field descriptions
Field Description
31–2 This field is reserved.
- Reserved
1 Software power down trigger for NOC PGC
NOC_SW_PDN_
REQ
0 Software power down trigger for MIX PGC
MF_SW_PDN_R
EQ
5.2.10.40 PU PGC software down trigger
(GPC_PU_PGC_SW_PDN_REQ)
Address: 303A_0000h base + E4h offset = 303A_00E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSIOMIX_SW_PDN_REQ
DDRMIX_SW_PDN_REQ
MEDIA_ISP_DWP_SW_
MIPI_PHY2_SW_PDN_
R
PDN_REQ
REQ
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDMIMIX_SW_PDN_REQ
MEDIMIX_SW_PDN_REQ
AUDIOMIX_SW_PDN_RE
PCIE_PHY_SW_PDN_RE
GPU_3D_SW_PDN_REQ
GPU_2D_SW_PDN_REQ
VPU_G1_SW_PDN_REQ
VPUMIX_SHARE_LOGIC
VPU_VC8K_SW_PDN_R
USB2_PHY_SW_PDN_R
USB1_PHY_SW_PDN_R
MIPI_PHY1_SW_PDN_R
GPU_SHARE_LOGIC_S
MLMIX_SW_PDN_REQ
HDMI_PHY_SW_PDN_
_SW_PDN_REQ
_SW_PDN_REQ
R
W_PDN_REQ
REQ
EQ
EQ
EQ
EQ
Q
Q
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PU_PGC_SW_PDN_REQ field descriptions
Field Description
31–20 This field is reserved.
- Reserved
19 Software power down trigger for DDRMIX
DDRMIX_SW_
PDN_REQ
18 Software power down trigger for MEDIA_ISP_DWP
MEDIA_ISP_
DWP_SW_PDN_
REQ
17 Software power down trigger for HSIOMIX
HSIOMIX_SW_
PDN_REQ
16 Software power down trigger for MIPI_PHY2
MIPI_PHY2_
SW_PDN_REQ
15 Software power down trigger for HDMI_PHY
HDMI_PHY_SW_
PDN_REQ
14 Software power down trigger for HDMIMIX
HDMIMIX_SW_
PDN_REQ
13 Software power down trigger for VPU_VC8K
VPU_VC8K_SW
_PDN_REQ
12 Software power down trigger for VPU_G2
_SW_PDN_REQ
11 Software power down trigger for VPU_G1
VPU_G1_SW_P
DN_REQ
10 Software power down trigger for MEDIMIX
MEDIMIX_SW_P
DN_REQ
9 Software power down trigger for GPU_3D
GPU_3D_SW_P
DN_REQ
Table continues on the next page...
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GPC_PU_PGC_SW_PDN_REQ field descriptions (continued)
Field Description
8 Software power down trigger for VPUMIX_SHARE_LOGIC
VPUMIX_SHARE
_LOGIC_SW_PD
N_REQ
7 Software power down trigger for GPU_SHARE_LOGIC
GPU_SHARE_L
OGIC_SW_PDN
_REQ
6 Software power down trigger for GPU_2D
GPU_2D_SW_P
DN_REQ
5 Software power down trigger for AUDIOMIX
AUDIOMIX_SW_
PDN_REQ
4 Software power down trigger for MLMIX
MLMIX_SW_PD
N_REQ
3 Software power down trigger for USB2_PHY
USB2_PHY_SW
_PDN_REQ
2 Software power down trigger for USB1_PHY
USB1_PHY_SW
_PDN_REQ
1 Software power down trigger for PCIE_PHY
PCIE_PHY_SW_
PDN_REQ
0 Software power down trigger for MIPI_PHY1
MIPI_PHY1_SW
_PDN_REQ
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General Power Controller (GPC)
5.2.10.41 Advanced Low power control register of CM4 platform
(GPC_GPC_LPCR_CM4_AD)
Address: 303A_0000h base + ECh offset = 303A_00ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
cm4_sleep_hold_ack_
m4_sleep_hold_req_b
cm4_gate_hclk_sync1
cm4_is_halted_sync1
cm4_sleeping_sync1
src_cm4_core_rst_b
src_cm4_plat_rst_b
cm4_lookup_sync1
R
cm4_sleep_deep_
b_sync1
sync1
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_GPC_LPCR_CM4_AD field descriptions
Field Description
31 cm4 sleep hold requested
m4_sleep_hold_
req_b
30 cm4 sleep hold acknowledged
cm4_sleep_hold_
ack_b_sync1
29 cm4 hclk gated
cm4_gate_hclk_
sync1
28 cm4 in deep sleep now
cm4_sleep_
deep_sync1
27 cm4 sleeping now
cm4_sleeping_
sync1
26 cm4 is lookup
cm4_lookup_
sync1
25 cm4 is halted
cm4_is_halted_
sync1
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_GPC_LPCR_CM4_AD field descriptions (continued)
Field Description
24 cm4_plat rst_b assert
src_cm4_plat_
rst_b
23 cm4_core rst_b assert
src_cm4_core_
rst_b
- This field is reserved.
Reserved
5.2.10.42 CPU PGC software up trigger status1
(GPC_CPU_PGC_PUP_STATUS1)
CPU_PGC_PUP_STATUS1 is a read only register, represents the results for power up
software trigger for CPU type PGCs.
The field description is show in table below, the value of “1’b1” represent the software
power up trigger failed because the relevant PGC is in a power down process. The
relevant bit will be cleared after a success operation of power up software trigger for
CPU type PGCs.
Address: 303A_0000h base + 108h offset = 303A_0108h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_PUP_STATUS
CORE2_A53_PUP_STATUS
CORE1_A53_PUP_STATUS
CORE0_A53_PUP_STATUS
SCU_A53_PUP_REQ
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_CPU_PGC_PUP_STATUS1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4
SCU_A53_PUP_
REQ
3
CORE3_A53_PU
P_STATUS
2
CORE2_A53_PU
P_STATUS
1
CORE1_A53_PU
P_STATUS
0
CORE0_A53_PU
P_STATUS
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5.2.10.43 A53 MIX software up trigger status register
(GPC_A53_MIX_PGC_PUP_STATUSn)
A53_MIX_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the
results for power up software trigger from A53 platform to MIX type PGCs.
A53_MIX_PGC_PUP_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
A53_MIX_PGC_PUP_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power up software trigger for MIX type PGCs.
A53_MIX_PGC_PUP_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
Address: 303A_0000h base + 10Ch offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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NXP Semiconductors 591
General Power Controller (GPC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_MIX_PGC_PUP_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_A53_MIX_PGC_PUP_STATUSn field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0
A53_MIX_PGC_
PUP_STATUS
5.2.10.44 M7 MIX PGC software up trigger status register
(GPC_M7_MIX_PGC_PUP_STATUSn)
M7_MIX_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the
results for power up software trigger from M7 platform to MIX type PGCs.
M7_MIX_PGC_PUP_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
M7_MIX_PGC_PUP_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power up software trigger for MIX type PGCs.
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Chapter 5 Clocks and Power Management
M7_MIX_PGC_PUP_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power up software trigger for MIX type PGCs.
Address: 303A_0000h base + 118h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_MIX_PGC_PUP_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
GPC_M7_MIX_PGC_PUP_STATUSn field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0
M7_MIX_PGC_
PUP_STATUS
5.2.10.45 A53 PU software up trigger status register
(GPC_A53_PU_PGC_PUP_STATUSn)
A53_PU_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the results
for power up software trigger from A53 platform to PU type PGCs.
A53_PU_PGC_PUP_STATUS0: value of “1’b1” represent the software power up trigger
failed because domain control condition. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
A53_PU_PGC_PUP_STATUS1: value of “1’b1” represent the software power up trigger
failed because the relevant PGC is in a power up process. The relevant bit will be cleared
after a success operation of power up software trigger for PU type PGCs.
A53_PU_PGC_PUP_STATUS2: value of “1’b1” represent the software power up trigger
failed because time slot control is busy. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
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Chapter 5 Clocks and Power Management
Address: 303A_0000h base + 124h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A53_MEDIA_ISP_DWP_PUP_STATUS
A53_MIPI_PHY2_PUP_STATUS
A53_HSIOMIX_PUP_STATUS
A53_DDRMIX_PUP_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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NXP Semiconductors 595
596
W
R
Reset
Bit
-
0
15
A53_HDMI_PHY_PUP_STATUS
Field
31–20
0
14
A53_HDMIMIX_PUP_STATUS
0
13
A53_VPU_VC8K_PUP_STATUS
Reserved
0
General Power Controller (GPC)
12
A53_VPU_G2_PUP_STATUS
This field is reserved.
0
11
A53_VPU_G1_PUP_STATUS
0
10
A53_MEDIMIX_PUP_STATUS
9
0
A53_GPU_3D_PUP_STATUS
8
0
A53_VPUMIX_SHARE_LOGIC_PUP_STATUS
7
0
A53_GPU_SHARE_LOGIC_PUP_STATUS
6
Description
A53_GPU_2D_PUP_STATUS
Table continues on the next page...
5
0
A53_AUDIOMIX_PUP_STATUS
4
0
A53_MLMIX_PUP_STATUS
3
0
A53_USB2_PHY_PUP_STATUS
GPC_A53_PU_PGC_PUP_STATUSn field descriptions
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
2
0
A53_USB1_PHY_PUP_STATUS
1
0
A53_PCIE_PHY_PUP_STATUS
0
0
A53_MIPI_PHY1_PUP_STATUS
NXP Semiconductors
Chapter 5 Clocks and Power Management
GPC_A53_PU_PGC_PUP_STATUSn field descriptions (continued)
Field Description
19
A53_DDRMIX_
PUP_STATUS
18
A53_MEDIA_
ISP_DWP_PUP_
STATUS
17
A53_HSIOMIX_
PUP_STATUS
16
A53_MIPI_
PHY2_PUP_
STATUS
15
A53_HDMI_
PHY_PUP_
STATUS
14
A53_HDMIMIX_
PUP_STATUS
13
A53_VPU_VC8K
_PUP_STATUS
12
A53_VPU_G2_P
UP_STATUS
11
A53_VPU_G1_P
UP_STATUS
10
A53_MEDIMIX_P
UP_STATUS
9
A53_GPU_3D_P
UP_STATUS
8
A53_VPUMIX_S
HARE_LOGIC_P
UP_STATUS
7
A53_GPU_SHAR
E_LOGIC_PUP_
STATUS
6
A53_GPU_2D_
PUP_STATUS
Table continues on the next page...
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General Power Controller (GPC)
GPC_A53_PU_PGC_PUP_STATUSn field descriptions (continued)
Field Description
5
A53_AUDIOMIX_
PUP_STATUS
4
A53_MLMIX_
PUP_STATUS
3
A53_USB2_PHY
_PUP_STATUS
2
A53_USB1_PHY
_PUP_STATUS
1
A53_PCIE_PHY_
PUP_STATUS
0
A53_MIPI_PHY1
_PUP_STATUS
5.2.10.46 M7 PU PGC software up trigger status register
(GPC_M7_PU_PGC_PUP_STATUSn)
M7_PU_PGC_PUP_STATUSn (n = 0,1,2) are a read only register, represents the results
for power up software trigger from M7 platform to PU type PGCs.
M7_PU_PGC_PUP_STATUS0: value of “1’b1” represent the software power up trigger
failed because domain control condition. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
M7_PU_PGC_PUP_STATUS1: value of “1’b1” represent the software power up trigger
failed because the relevant PGC is in a power up process. The relevant bit will be cleared
after a success operation of power up software trigger for PU type PGCs.
M7_PU_PGC_PUP_STATUS2: value of “1’b1” represent the software power up trigger
failed because time slot control is busy. The relevant bit will be cleared after a success
operation of power up software trigger for PU type PGCs.
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Chapter 5 Clocks and Power Management
Address: 303A_0000h base + 130h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M7_MEDIA_ISP_DWP_PUP_STATUS
M7_MIPI_PHY2_PUP_STATUS
M7_HSIOMIX_PUP_STATUS
M7_DDRMIX_PUP_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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600
W
R
Reset
Bit
-
19
0
15
M7_HDMI_PHY_PUP_STATUS
Field
31–20
M7_DDRMIX_
PUP_STATUS
0
14
M7_HDMIMIX_PUP_STATUS
0
13
M7_VPU_VC8K_PUP_STATUS
Reserved
0
General Power Controller (GPC)
12
M7_VPU_G2_PUP_STATUS
This field is reserved.
0
11
M7_VPU_G1_PUP_STATUS
0
10
M7_MEDIMIX_PUP_STATUS
9
0
M7_GPU3D_PUP_STATUS
8
0
M7_VPUMIX_SHARE_LOGIC_PUP_STATUS
7
0
M7_GPU_SHARE_LOGIC_PUP_STATUS
6
Description
M7_GPU2D_PUP_STATUS
Table continues on the next page...
5
0
M7_AUDIOMIX_PUP_STATUS
4
0
M7_MLMIX_PUP_STATUS
3
GPC_M7_PU_PGC_PUP_STATUSn field descriptions
0
M7_USB2_PHY_PUP_STATUS
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2
0
M7_USB1_PHY_PUP_STATUS
1
0
M7_PCIE_PHY_PUP_STATUS
0
0
M7_MIPI_PHY1_PUP_STATUS
NXP Semiconductors
Chapter 5 Clocks and Power Management
GPC_M7_PU_PGC_PUP_STATUSn field descriptions (continued)
Field Description
18
M7_MEDIA_ISP_
DWP_PUP_
STATUS
17
M7_HSIOMIX_
PUP_STATUS
16
M7_MIPI_PHY2_
PUP_STATUS
15
M7_HDMI_PHY_
PUP_STATUS
14
M7_HDMIMIX_
PUP_STATUS
13
M7_VPU_VC8K_
PUP_STATUS
12
M7_VPU_G2_
PUP_STATUS
11
M7_VPU_G1_
PUP_STATUS
10
M7_MEDIMIX_P
UP_STATUS
9
M7_GPU3D_
PUP_STATUS
8
M7_VPUMIX_
SHARE_LOGIC_
PUP_STATUS
7
M7_GPU_SHAR
E_LOGIC_PUP_
STATUS
6
M7_GPU2D_
PUP_STATUS
5
M7_AUDIOMIX_
PUP_STATUS
4
M7_MLMIX_
PUP_STATUS
Table continues on the next page...
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General Power Controller (GPC)
GPC_M7_PU_PGC_PUP_STATUSn field descriptions (continued)
Field Description
3
M7_USB2_PHY_
PUP_STATUS
2
M7_USB1_PHY_
PUP_STATUS
1
M7_PCIE_PHY_
PUP_STATUS
0
M7_MIPI_PHY1_
PUP_STATUS
5.2.10.47 CPU PGC software dn trigger status1
(GPC_CPU_PGC_PDN_STATUS1)
CPU_PGC_PDN_STATUS1 is a read only register, represents the results for power DN
software trigger for CPU type PGCs.
The field description is show in table below, the value of “1’b1” represent the software
power DN trigger failed because the relevant PGC is in a power down process. The
relevant bit will be cleared after a success operation of power DN software trigger for
CPU type PGCs.
Address: 303A_0000h base + 13Ch offset = 303A_013Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 5 Clocks and Power Management
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_PDN_STATUS
CORE2_A53_PDN_STATUS
CORE1_A53_PDN_STATUS
CORE0_A53_PDN_STATUS
SCU_A53_PDN_REQ
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_CPU_PGC_PDN_STATUS1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4
SCU_A53_PDN_
REQ
3
CORE3_A53_PD
N_STATUS
2
CORE2_A53_PD
N_STATUS
1
CORE1_A53_PD
N_STATUS
0
CORE0_A53_PD
N_STATUS
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General Power Controller (GPC)
5.2.10.48 A53 MIX software down trigger status register
(GPC_A53_MIX_PGC_PDN_STATUSn)
A53_MIX_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power down software trigger from A53 platform to MIX type PGCs.
A53_MIX_PGC_PDN_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
A53_MIX_PGC_PDN_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power down software trigger for MIX type PGCs.
A53_MIX_PGC_PDN_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
Address: 303A_0000h base + 140h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 5 Clocks and Power Management
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_MIX_PGC_PDN_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_A53_MIX_PGC_PDN_STATUSn field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0
A53_MIX_PGC_
PDN_STATUS
5.2.10.49 M7 MIX PGC software power down trigger status register
(GPC_M7_MIX_PGC_PDN_STATUSn)
M7_MIX_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power down software trigger from M7 platform to MIX type PGCs.
M7_MIX_PGC_PDN_STATUS0: value of “1’b1” represent the software power up
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
M7_MIX_PGC_PDN_STATUS1: value of “1’b1” represent the software power up
trigger failed because the relevant PGC is in a power up process. The relevant bit will be
cleared after a success operation of power down software trigger for MIX type PGCs.
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General Power Controller (GPC)
M7_MIX_PGC_PDN_STATUS2: value of “1’b1” represent the software power up
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power down software trigger for MIX type PGCs.
Address: 303A_0000h base + 14Ch offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_MIX_PGC_PDN_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 5 Clocks and Power Management
GPC_M7_MIX_PGC_PDN_STATUSn field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0
M7_MIX_PGC_
PDN_STATUS
5.2.10.50 A53 PU PGC software down trigger status
(GPC_A53_PU_PGC_PDN_STATUSn)
A53_PU_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the
results for power DN software trigger from A53 platform to PU type PGCs.
A53_PU_PGC_PDN_STATUS0: value of “1’b1” represent the software power DN
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
A53_PU_PGC_PDN_STATUS1: value of “1’b1” represent the software power DN
trigger failed because the relevant PGC is in a power DN process. The relevant bit will be
cleared after a success operation of power DN software trigger for PU type PGCs.
A53_PU_PGC_PDN_STATUS2: value of “1’b1” represent the software power DN
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
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General Power Controller (GPC)
Address: 303A_0000h base + 158h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A53_MEDIA_ISP_DWP_PDN_STATUS
A53_MIPI_PHY2_PDN_STATUS
A53_HSIOMIX_PDN_STATUS
A53_DDRMIX_PDN_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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W
R
Reset
Bit
-
0
15
A53_HDMI_PHY_PDN_STATUS
Field
31–20
0
14
A53_HDMIMIX_PDN_STATUS
NXP Semiconductors
0
13
A53_VPU_VC8K_PDN_STATUS
Reserved
0
12
A53_VPU_G2_PDN_STATUS
This field is reserved.
0
11
A53_VPU_G1_PDN_STATUS
0
10
A53_MEDIMIX_PDN_STATUS
9
0
A53_GPU_3D_PDN_STATUS
8
0
A53_VPUMIX_SHARE_LOGIC_PDN_STATUS
7
0
A53_GPU_SHARE_LOGIC_PDN_STATUS
6
Description
A53_GPU_2D_PDN_STATUS
Table continues on the next page...
5
0
A53_AUDIOMIX_PDN_STATUS
4
0
A53_MLMIX_PDN_STATUS
3
0
A53_USB2_PHY_PDN_STATUS
GPC_A53_PU_PGC_PDN_STATUSn field descriptions
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
2
0
A53_USB1_PHY_PDN_STATUS
1
0
A53_PCIEPHY_PDN_STATUS
0
0
A53_MIPI_PHY1_PDN_STATUS
609
Chapter 5 Clocks and Power Management
General Power Controller (GPC)
GPC_A53_PU_PGC_PDN_STATUSn field descriptions (continued)
Field Description
19
A53_DDRMIX_
PDN_STATUS
18
A53_MEDIA_
ISP_DWP_PDN_
STATUS
17
A53_HSIOMIX_
PDN_STATUS
16
A53_MIPI_
PHY2_PDN_
STATUS
15
A53_HDMI_
PHY_PDN_
STATUS
14
A53_HDMIMIX_
PDN_STATUS
13
A53_VPU_VC8K
_PDN_STATUS
12
A53_VPU_G2_P
DN_STATUS
11
A53_VPU_G1_P
DN_STATUS
10
A53_MEDIMIX_P
DN_STATUS
9
A53_GPU_3D_P
DN_STATUS
8
A53_VPUMIX_S
HARE_LOGIC_P
DN_STATUS
7
A53_GPU_SHAR
E_LOGIC_PDN_
STATUS
6
A53_GPU_2D_
PDN_STATUS
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_A53_PU_PGC_PDN_STATUSn field descriptions (continued)
Field Description
5
A53_AUDIOMIX_
PDN_STATUS
4
A53_MLMIX_
PDN_STATUS
3
A53_USB2_PHY
_PDN_STATUS
2
A53_USB1_PHY
_PDN_STATUS
1
A53_PCIEPHY_
PDN_STATUS
0
A53_MIPI_PHY1
_PDN_STATUS
5.2.10.51 M7 PU PGC software down trigger status
(GPC_M7_PU_PGC_PDN_STATUSn)
M7_PU_PGC_PDN_STATUSn (n = 0,1,2) are a read only register, represents the results
for power DN software trigger from M7 platform to PU type PGCs.
M7_PU_PGC_PDN_STATUS0: value of “1’b1” represent the software power DN
trigger failed because domain control condition. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
M7_PU_PGC_PDN_STATUS1: value of “1’b1” represent the software power DN
trigger failed because the relevant PGC is in a power DN process. The relevant bit will be
cleared after a success operation of power DN software trigger for PU type PGCs.
M7_PU_PGC_PDN_STATUS2: value of “1’b1” represent the software power DN
trigger failed because time slot control is busy. The relevant bit will be cleared after a
success operation of power DN software trigger for PU type PGCs.
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General Power Controller (GPC)
Address: 303A_0000h base + 164h offset + (4d × i), where i=0d to 2d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
M7_MEDIA_ISP_DWP_PDN_STATUS
M7_MIPI_PHY2_PDN_STATUS
M7_HSIOMIX_PDN_STATUS
M7_DDRMIX_PDN_STATUS
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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W
R
Reset
Bit
-
19
0
15
M7_HDMI_PHY_PDN_STATUS
Field
31–20
M7_DDRMIX_
PDN_STATUS
0
14
M7_HDMIMIX_PDN_STATUS
NXP Semiconductors
0
13
M7_VPU_VC8K_PDN_STATUS
Reserved
0
12
M7_VPU_G2_PDN_STATUS
This field is reserved.
0
11
M7_VPU_G1_PDN_STATUS
0
10
M7_MEDIMIX_PDN_STATUS
9
0
M7_GPU3D_PDN_STATUS
8
0
M7_VPUMIX_SHARE_LOGIC_PDN_STATUS
7
0
M7_GPU_SHARE_LOGIC_PDN_STATUS
6
Description
M7_GPU_2D_PDN_STATUS
Table continues on the next page...
5
0
M7_AUDIOMIX_PDN_STATUS
4
0
M7_MLMIX_PDN_STATUS
3
GPC_M7_PU_PGC_PDN_STATUSn field descriptions
M7_USB2_PHY_PDN_STATUS
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
2
0
M7_USB1_PHY_PDN_STATUS
1
0
M7_PCIE_PHY_PDN_STATUS
0
0
M7_MIPI_PHY1_PDN_STATUS
613
Chapter 5 Clocks and Power Management
General Power Controller (GPC)
GPC_M7_PU_PGC_PDN_STATUSn field descriptions (continued)
Field Description
18
M7_MEDIA_ISP_
DWP_PDN_
STATUS
17
M7_HSIOMIX_
PDN_STATUS
16
M7_MIPI_PHY2_
PDN_STATUS
15
M7_HDMI_PHY_
PDN_STATUS
14
M7_HDMIMIX_
PDN_STATUS
13
M7_VPU_VC8K_
PDN_STATUS
12
M7_VPU_G2_
PDN_STATUS
11
M7_VPU_G1_
PDN_STATUS
10
M7_MEDIMIX_P
DN_STATUS
9
M7_GPU3D_
PDN_STATUS
8
M7_VPUMIX_
SHARE_LOGIC_
PDN_STATUS
7
M7_GPU_SHAR
E_LOGIC_PDN_
STATUS
6
M7_GPU_2D_
PDN_STATUS
5
M7_AUDIOMIX_
PDN_STATUS
4
M7_MLMIX_
PDN_STATUS
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_M7_PU_PGC_PDN_STATUSn field descriptions (continued)
Field Description
3
M7_USB2_PHY_
PDN_STATUS
2
M7_USB1_PHY_
PDN_STATUS
1
M7_PCIE_PHY_
PDN_STATUS
0
M7_MIPI_PHY1_
PDN_STATUS
5.2.10.52 A53 MIX PDN FLG (GPC_A53_MIX_PDN_FLG)
This is flag bit relevant domain control, represents A53 CPU platform wants to power
down MIX PGC. The register can only be accessed by A53 platform.
Address: 303A_0000h base + 170h offset = 303A_0170h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_MIX_PDN_F
R
LAG
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_A53_MIX_PDN_FLG field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0 A53 MIX power-down flag
A53_MIX_PDN_
FLAG
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General Power Controller (GPC)
5.2.10.53 A53 PU PDN FLG (GPC_A53_PU_PDN_FLG)
The register field is show in the table below. The 1’b1 represents A53 CPU platform
wants to power down certain PU PGC. The register is a read only register. The register
bits will be set when corresponding A53 software power down trigger happens and will
be clear when corresponding A53 software power up trigger happens.
Address: 303A_0000h base + 174h offset = 303A_0174h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved A53_PU_PDN_FLG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_A53_PU_PDN_FLG field descriptions
Field Description
31–20 This field is reserved.
- Reserved
A53_PU_PDN_ A53 PGC power-down flag
FLG
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5.2.10.54 M7 MIX PDN FLG (GPC_M7_MIX_PDN_FLG)
This is flag bit relevant domain control, represents M7 CPU platform wants to power
down MIX PGC. The register can only be accessed by M7 platform.
Address: 303A_0000h base + 178h offset = 303A_0178h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M7_MIX_PDN_
R
FLAG
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_M7_MIX_PDN_FLG field descriptions
Field Description
31–1 This field is reserved.
- Reserved
0 M7_MIX power-down flag
M7_MIX_PDN_
FLAG
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5.2.10.55 M7 PU PDN FLG (GPC_M7_PU_PDN_FLG)
The register field is show in the table below. The 1’b1 represents M7 CPU platform
wants to power down certain PU PGC. The register is a read only register. The register
bits will be set when corresponding M7 software power down trigger happens and will be
clear when corresponding M7 software power up trigger happens.
Address: 303A_0000h base + 17Ch offset = 303A_017Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved M7_PU_PDN_FLG
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_M7_PU_PDN_FLG field descriptions
Field Description
31–20 This field is reserved.
- Reserved
M7_PU_PDN_ M7 power-down flag
FLG
5.2.10.56 Basic Low power control register of A53 platform
(GPC_LPCR_A53_BSC2)
Address: 303A_0000h base + 180h offset = 303A_0180h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved LPM3 LPM2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_LPCR_A53_BSC2 field descriptions
Field Description
31–4 This field is reserved.
- Reserved
3–2 CORE3 Setting the low power mode that system will enter on next assertion of dsm_request signal.
LPM3
00 Remain in RUN mode
01 Transfer to WAIT mode
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GPC_LPCR_A53_BSC2 field descriptions (continued)
Field Description
10 Transfer to STOP mode
11 Reserved
LPM2 CORE2 Setting the low power mode that system will enter on next assertion of dsm_request signal.
00 Remain in RUN mode
01 Transfer to WAIT mode
10 Transfer to STOP mode
11 Reserved
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W
R
Reset
Bit
0
31
GPC_AUDIOMIX_PWRDNACKN
0
30
GPC_MEDIAMIX_NOC_ADBS_PWRDNACKN
0
29
GPC_HDMIMIX_NOC_PWRDNACKN
0
General Power Controller (GPC)
28
GPC_NOC2HSIO_ADBS_PWDWNACKN
0
27
GPC_NOC2DDRMIX_PWRDNACKN
0
26
GPC_VPUMIX_NOX_PWDWNACKN
0
25
GPC_GPUMIX_NOC_ADBS_PWRDNACKN
Address: 303A_0000h base + 190h offset = 303A_0190h
0
24
GPC_NOC2MLMIX_PWDWNACKN
0
23
GPC_MLMIX_ADBS_PWRDNACKN
0
22
GPC_SUPERMIX2NOC_ADBS_PWDWNACKN
0
21
GPC_NOC2SUPERMIX_ADBS_PWDWNACKN
0
20
GPC_NOC2AUDIOMIX_PWDWNACKN
0
19
GPC_DDR1_CACTIVE
5.2.10.57 Power handshake register (GPC_PU_PWRHSK)
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18
GPC_DDR1_CTRL_REQACK
0
17
GPC_DDR1_CTRL_CLKACTIVE
0
16
GPC_DDR1_CTRL_LWPWACKN
NXP Semiconductors
Chapter 5 Clocks and Power Management
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPC_MEDIAMIX_NOC_ADBS_PWRDNREQN
GPC_GPUMIX_NOC_ADBS_PWRDNREQN
GPC_NOC2HSIO_ADBS_PWRDNREQN
GPC_SUPERMIX2NOC_PWRDNREQN
GPC_NOC2SUPERMIX_PWRDNREQN
GPC_AUDIOMIX_NOC_PWRDNREQN
GPC_NOC2AUDIOMIX_PWRDNREQN
GPC_HDMIMIX_NOC_PWRDNREQN
GPC_NOC2DDRMIX_PWRDNREQN
GPC_VPUMIX_NOC_PWRDNREQN
GPC_MLMIX_ADBS_PWRDNREQN
GPC_NOC2MLMIX_PWRDNREQN
R
GPC_DDR1_CORE_CSYSREQ
GPC_DDR1_AXI_CSYSREQ
Reserved
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
GPC_PU_PWRHSK field descriptions
Field Description
31 Audiomix noc power down ackn. Read 0 before power down audiomix switchable domain or main noc
GPC_AUDIOMIX_ domain
PWRDNACKN
30 Mediamix noc and adbs power down ackn. Read 0 before power down mediamix default domain or
GPC_MEDIAMIX_ main noc domain
NOC_ADBS_
PWRDNACKN
29 Hdmimix noc power down ackn. Read 0 before power down hdmimix switchable domain or main noc
GPC_HDMIMIX_ domain
NOC_PWRDNACKN
28 Main noc 2 hsio and adbs power down ackn. Read 0 before power down main noc or hsio switchable
GPC_NOC2HSIO_ domain
ADBS_
PWDWNACKN
27 Main noc 2 ddrmix power down ackn. Read 0 before power down main noc or ddrmix switchable
GPC_ domain
NOC2DDRMIX_
PWRDNACKN
26 Vpumix noc power down ackn. Read 0 before power down vpumix default share logic domain or main
GPC_VPUMIX_ noc domain
NOX_PWDWNACKN
25 gpumix noc and adbs power down ackn. Read 0 before power down gpumix default share logic
GPC_GPUMIX_ domain or main noc domain
NOC_ADBS_
PWRDNACKN
Table continues on the next page...
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General Power Controller (GPC)
GPC_PU_PWRHSK field descriptions (continued)
Field Description
24 Main noc 2 mlmix power down ackn. Read 0 before power down mlmix switchable domain or main
GPC_NOC2MLMIX_ noc domain
PWDWNACKN
23 Mlmix adbs power down ackn. Read 0 before power down mlmix switchable domain or main noc
GPC_MLMIX_ domain
ADBS_
PWRDNACKN
22 Supermix 2 noc adbs power down ackn. Read 0 before power down main noc domain. It can be
GPC_ covered by hardware handshake follow.
SUPERMIX2NOC_
ADBS_
PWDWNACKN
21 Main noc 2 Supermix adbs power down ackn. Read 0 before power down main noc domain. It can be
GPC_ covered by hardware handshake follow.
NOC2SUPERMIX_
ADBS_
PWDWNACKN
20 Main noc 2 audiomix power down ackn. Read 0 before power down main noc or audiomix switchable
GPC_ domain
NOC2AUDIOMIX_
PWDWNACKN
19 DDR1 AXI Clock Active
GPC_DDR1_
CACTIVE
18 DDR1 AXI Low-Power Request ack
GPC_DDR1_CTRL_
REQACK
17 DDR1 controller Hardware Low-Power Clock active
GPC_DDR1_CTRL_
CLKACTIVE
16 DDR1 controller Hardware Low_Power ack
GPC_DDR1_CTRL_
LWPWACKN
15 Audiomix noc power down request. Write 0 and wait according ackn before power down audiomix
GPC_AUDIOMIX_ switchable domain or main noc domain
NOC_PWRDNREQN
14 Mediamix noc and adbs power down request. Write 0 and wait according ackn before power down
GPC_MEDIAMIX_ mediamix default domain or main noc domain
NOC_ADBS_
PWRDNREQN
13 Hdmimix noc power down request. Write 0 and wait according ackn before power down hdmimix
GPC_HDMIMIX_ switchable domain or main noc domain
NOC_PWRDNREQN
12 Main noc 2 hsio and adbs power down request. Write 0 and wait according ackn before power down
GPC_NOC2HSIO_ main noc or hsio switchable domain
ADBS_
PWRDNREQN
Table continues on the next page...
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GPC_PU_PWRHSK field descriptions (continued)
Field Description
11 Main noc 2 ddrmix power down request. Write 0 and wait according ackn before power down main
GPC_ noc or ddrmix switchable domain
NOC2DDRMIX_
PWRDNREQN
10 Vpumix noc power down request. Write 0 and wait according ackn before power down vpumix default
GPC_VPUMIX_ share logic domain or main noc domain
NOC_PWRDNREQN
9 gpumix noc and adbs power down request. Write 0 and wait according ackn before power down
GPC_GPUMIX_ gpumix default share logic domain or main noc domain
NOC_ADBS_
PWRDNREQN
8 Main noc 2 mlmix power down request. Write 0 and wait according ackn before power down mlmix
GPC_NOC2MLMIX_ switchable domain or main noc domain
PWRDNREQN
7 Mlmix adbs power down request. Write 0 and wait according ackn before power down mlmix
GPC_MLMIX_ switchable domain or main noc domain
ADBS_
PWRDNREQN
6 Supermix 2 noc adbs power down request. Write 0 and wait according ackn before power down main
GPC_ noc domain. It can be covered by hardware handshake follow.
SUPERMIX2NOC_
PWRDNREQN
5 DISPMIX ADB400 power down request. Active 0
GPC_
NOC2SUPERMIX_
PWRDNREQN
4 Main noc 2 audiomix power down request. Write 0 and wait according ackn before power down main
GPC_ noc or audiomix switchable domain
NOC2AUDIOMIX_
PWRDNREQN
3–2 This field is reserved.
- Reserved
1 DDR1 AXI Low-Power Request
GPC_DDR1_AXI_
CSYSREQ
0 DDR1 controller Hardware Low-Power Request
GPC_DDR1_CORE_
CSYSREQ
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5.2.10.58 IRQ masking register 1 of A53 core2
(GPC_IMR1_CORE2_A53)
The five IMRn_CORE2_A53 (n = 1,2,3,4,5) registers are used as interrupt mask for A53
core2.
Address: 303A_0000h base + 194h offset = 303A_0194h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1_CORE2_A53 field descriptions
Field Description
IMR1_CORE2_ A53 core2 IRQ[31:0] masking bits:
A53
0 IRQ not masked
1 IRQ masked
5.2.10.59 IRQ masking register 2 of A53 core2
(GPC_IMR2_CORE2_A53)
Address: 303A_0000h base + 198h offset = 303A_0198h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR2_CORE2_A53 field descriptions
Field Description
IMR2_CORE2_ A53 core2 IRQ[63:32] masking bits:
A53
0 IRQ not masked
1 IRQ masked
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5.2.10.60 IRQ masking register 3 of A53 core2
(GPC_IMR3_CORE2_A53)
Address: 303A_0000h base + 19Ch offset = 303A_019Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR3_CORE2_A53 field descriptions
Field Description
IMR3_CORE2_ A53 core2 IRQ[95:64] masking bits:
A53
0 IRQ not masked
1 IRQ masked
5.2.10.61 IRQ masking register 4 of A53 core2
(GPC_IMR4_CORE2_A53)
Address: 303A_0000h base + 1A0h offset = 303A_01A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR4_CORE2_A53 field descriptions
Field Description
IMR4_CORE2_ A53 core2 IRQ[127:96] masking bits:
A53
0 IRQ not masked
1 IRQ masked
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5.2.10.62 IRQ masking register 5 of A53 core2
(GPC_IMR5_CORE2_A53)
Address: 303A_0000h base + 1A4h offset = 303A_01A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR5_CORE2_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR5_CORE2_A53 field descriptions
Field Description
IMR5_CORE2_ A53 core2 IRQ[159:128] masking bits:
A53
0 IRQ not masked
1 IRQ masked
5.2.10.63 IRQ masking register 1 of A53 core3
(GPC_IMR1_CORE3_A53)
The five IMRn_CORE2_A53 (n = 1,2,3,4,5) registers are used as interrupt mask for A53
core3.
Address: 303A_0000h base + 1A8h offset = 303A_01A8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR1_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR1_CORE3_A53 field descriptions
Field Description
IMR1_CORE3_ A53 core3 IRQ[31:0] masking bits:
A53
0 IRQ not masked
1 IRQ masked
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5.2.10.64 IRQ masking register 2 of A53 core3
(GPC_IMR2_CORE3_A53)
Address: 303A_0000h base + 1ACh offset = 303A_01ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR2_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR2_CORE3_A53 field descriptions
Field Description
IMR2_CORE3_ A53 core3 IRQ[63:32] masking bits:
A53
0 IRQ not masked
1 IRQ masked
5.2.10.65 IRQ masking register 3 of A53 core3
(GPC_IMR3_CORE3_A53)
Address: 303A_0000h base + 1B0h offset = 303A_01B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR3_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR3_CORE3_A53 field descriptions
Field Description
IMR3_CORE3_ A53 core3 IRQ[95:64] masking bits:
A53
0 IRQ not masked
1 IRQ masked
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5.2.10.66 IRQ masking register 4 of A53 core3
(GPC_IMR4_CORE3_A53)
Address: 303A_0000h base + 1B4h offset = 303A_01B4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IMR4_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR4_CORE3_A53 field descriptions
Field Description
IMR4_CORE3_ A53 core3 IRQ[127:96] masking bits:
A53
0 IRQ not masked
1 IRQ masked
5.2.10.67 IRQ masking register 5 of A53 core3
(GPC_IMR5_CORE3_A53)
Address: 303A_0000h base + 1B8h offset = 303A_01B8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
IM5_CORE3_A53
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_IMR5_CORE3_A53 field descriptions
Field Description
IM5_CORE3_ A53 core3 IRQ[159:128] masking bits:
A53
0 IRQ not masked
1 IRQ masked
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5.2.10.68 PGC acknowledge signal selection of A53 platform for PUs
(GPC_ACK_SEL_A53_PU)
Address: 303A_0000h base + 1BCh offset = 303A_01BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VPU_G2_PGC_PDN_ACK
VPU_G1_PGC_PDN_ACK
VPU_G2_PGC_PUP_ACK
VPU_G1_PGC_PUP_ACK
GPU3D_PGC_PDN_ACK
GPU3D_PGC_PUP_ACK
VPU_VC8K_PGC_PDN_
HDMI_PHY_PGC_PDN_
VPU_VC8K_PGC_PUP_
LOGIC_PGC_PDN_ACK
HDMI_PHY_PGC_PUP_
LOGIC_PGC_PUP_ACK
HDMIMIX_PGC_PDN_
HDMIMIX_PGC_PUP_
MEDIMIX_PGC_PDN_
MEDIMIX_PGC_PUP_
VPUMIX_SHARE_
VPUMIX_SHARE_
R
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU_2D_PGC_PUP_ACK
MLMIX_PGC_PDN_ACK
USB2_PHY_PGC_PDN_
USB1_PHY_PGC_PDN_
MIPI_PHY1_PGC_PDN_
MLMIX_PGC_PUP_ACK
USB2_PHY_PGC_PUP_
USB1_PHY_PGC_PUP_
MIPI_PHY1_PGC_PUP_
AUDIOMIX_PGC_PDN_
PCIE_PHY_PGC_PDN_
AUDIOMIX_PGC_PUP_
PCIE_PHY_PGC_PUP_
GPU_SHARE_LOGIC_
GPU_SHARE_LOGIC_
GPU_2D_PGC_PDN_
R
PGC_PDN_ACK
PGC_PUP_ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ACK_SEL_A53_PU field descriptions
Field Description
31 Select power down acknowledge signal of HDMI_PHY PGC as the power up acknowledge for A53 LPM
HDMI_PHY_
PGC_PUP_ACK
30 Select power down acknowledge signal of HDMI_PHY PGC as the power down acknowledge for A53
HDMI_PHY_ LPM
PGC_PDN_ACK
29 Select power down acknowledge signal of HDMIMIX PGC as the power up acknowledge for A53 LPM
HDMIMIX_PGC_
PUP_ACK
28 Select power down acknowledge signal of HDMIMIX PGC as the power down acknowledge for A53 LPM
HDMIMIX_PGC_
PDN_ACK
27 Select power down acknowledge signal of VPU_VC8K PGC as the power up acknowledge for A53 LPM
VPU_VC8K_
PGC_PUP_ACK
26 Select power down acknowledge signal of VPU_VC8K PGC as the power down acknowledge for A53
VPU_VC8K_ LPM
PGC_PDN_ACK
Table continues on the next page...
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General Power Controller (GPC)
GPC_ACK_SEL_A53_PU field descriptions (continued)
Field Description
25 Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for A53 LPM
VPU_G2_PGC_
PUP_ACK
24 Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for A53 LPM
VPU_G2_PGC_
PDN_ACK
23 Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for A53 LPM
VPU_G1_PGC_
PUP_ACK
22 Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for A53 LPM
VPU_G1_PGC_
PDN_ACK
21 Select power down acknowledge signal of MEDIMIX PGC as the power up acknowledge for A53 LPM
MEDIMIX_PGC_
PUP_ACK
20 Select power down acknowledge signal of MEDIMIX PGC as the power down acknowledge for A53 LPM
MEDIMIX_PGC_
PDN_ACK
19 Select power down acknowledge signal of GPU3D PGC as the power up acknowledge for A53 LPM
GPU3D_PGC_
PUP_ACK
18 Select power down acknowledge signal of GPU3D PGC as the power down acknowledge for A53 LPM
GPU3D_PGC_
PDN_ACK
17 Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power up acknowledge
VPUMIX_ for A53 LPM
SHARE_LOGIC_
PGC_PUP_ACK
16 Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power down
VPUMIX_ acknowledge for A53 LPM
SHARE_LOGIC_
PGC_PDN_ACK
15 Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power up acknowledge for
GPU_SHARE_ A53 LPM
LOGIC_PGC_
PUP_ACK
14 Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power down acknowledge
GPU_SHARE_ for A53 LPM
LOGIC_PGC_
PDN_ACK
13 Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for A53 LPM
GPU_2D_PGC_
PUP_ACK
12 Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for A53 LPM
GPU_2D_PGC_
PDN_ACK
11 Select power down acknowledge signal of AUDIOMIX PGC as the power up acknowledge for A53 LPM
AUDIOMIX_
PGC_PUP_ACK
Table continues on the next page...
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GPC_ACK_SEL_A53_PU field descriptions (continued)
Field Description
10 Select power down acknowledge signal of AUDIOMIX PGC as the power down acknowledge for A53 LPM
AUDIOMIX_
PGC_PDN_ACK
9 Select power down acknowledge signal of MLMIX PGC as the power up acknowledge for A53 LPM
MLMIX_PGC_
PUP_ACK
8 Select power down acknowledge signal of MLMIX PGC as the power down acknowledge for A53 LPM
MLMIX_PGC_
PDN_ACK
7 Select power down acknowledge signal of USB2_PHY PGC as the power up acknowledge for A53 LPM
USB2_PHY_
PGC_PUP_ACK
6 Select power down acknowledge signal of USB2_PHY PGC as the power down acknowledge for A53
USB2_PHY_ LPM
PGC_PDN_ACK
5 Select power down acknowledge signal of USB1_PHY PGC as the power up acknowledge for A53 LPM
USB1_PHY_
PGC_PUP_ACK
4 Select power down acknowledge signal of USB1_PHY PGC as the power down acknowledge for A53
USB1_PHY_ LPM
PGC_PDN_ACK
3 Select power down acknowledge signal of PCIE_PHY PGC as the power up acknowledge for A53 LPM
PCIE_PHY_
PGC_PUP_ACK
2 Select power down acknowledge signal of PCIE_PHY PGC as the power down acknowledge for A53 LPM
PCIE_PHY_
PGC_PDN_ACK
1 Select power down acknowledge signal of MIPI_PHY1 PGC as the power up acknowledge for A53 LPM
MIPI_PHY1_
PGC_PUP_ACK
0 Select power down acknowledge signal of MIPI_PHY1 PGC as the power down acknowledge for A53
MIPI_PHY1_ LPM
PGC_PDN_ACK
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General Power Controller (GPC)
5.2.10.69 PGC acknowledge signal selection of A53 platform for PUs
(GPC_ACK_SEL_A53_PU1)
Address: 303A_0000h base + 1C0h offset = 303A_01C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIOMIX_PGC_PDN_
HSIOMIX_PGC_PUP_
DDRMIX_PGC_PDN_
DDRMIX_PGC_PUP_
MEDIA_ISP_DWP_
MEDIA_ISP_DWP_
MIPI_PHY2_PGC_
MIPI_PHY2_PGC_
PGC_PDN_ACK
PGC_PUP_ACK
R
PDN_ACK
PUP_ACK
ACK
ACK
ACK
ACK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ACK_SEL_A53_PU1 field descriptions
Field Description
31–8 This field is reserved.
- Reserved
7 Select power down acknowledge signal of DDRMIX PGC as the power up acknowledge for A53 LPM
DDRMIX_PGC_
PUP_ACK
6 Select power down acknowledge signal of DDRMIX PGC as the power down acknowledge for A53 LPM
DDRMIX_PGC_
PDN_ACK
5 Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power up acknowledge for A53
MEDIA_ISP_ LPM
DWP_PGC_
PUP_ACK
4 Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power down acknowledge for
MEDIA_ISP_ A53 LPM
DWP_PGC_
PDN_ACK
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Chapter 5 Clocks and Power Management
GPC_ACK_SEL_A53_PU1 field descriptions (continued)
Field Description
3 Select power down acknowledge signal of HSIOMIX PGC as the power up acknowledge for A53 LPM
HSIOMIX_PGC_
PUP_ACK
2 Select power down acknowledge signal of HSIOMIX PGC as the power down acknowledge for A53 LPM
HSIOMIX_PGC_
PDN_ACK
1 Select power down acknowledge signal of MIPI_PHY2 PGC as the power up acknowledge for A53 LPM
MIPI_PHY2_
PGC_PUP_ACK
0 Select power down acknowledge signal of MIPI_PHY2 PGC as the power down acknowledge for A53
MIPI_PHY2_ LPM
PGC_PDN_ACK
5.2.10.70 PGC acknowledge signal selection of M7 platform for PUs
(GPC_ACK_SEL_M7_PU)
Address: 303A_0000h base + 1C4h offset = 303A_01C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VPU_G2_PGC_PDN_ACK
VPU_G1_PGC_PDN_ACK
VPU_G2_PGC_PUP_ACK
VPU_G1_PGC_PUP_ACK
GPU3D_PGC_PDN_ACK
GPU3D_PGC_PUP_ACK
VPU_VC8K_PGC_PDN_
HDMI_PHY_PGC_PDN_
VPU_VC8K_PGC_PUP_
LOGIC_PGC_PDN_ACK
HDMI_PHY_PGC_PUP_
LOGIC_PGC_PUP_ACK
HDMIMIX_PGC_PDN_
HDMIMIX_PGC_PUP_
MEDIMIX_PGC_PDN_
MEDIMIX_PGC_PUP_
VPUMIX_SHARE_
VPUMIX_SHARE_
R
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU_2D_PGC_PUP_ACK
MLMIX_PGC_PDN_ACK
USB2_PHY_PGC_PDN_
USB1_PHY_PGC_PDN_
MIPI_PHY1_PGC_PDN_
MLMIX_PGC_PUP_ACK
USB2_PHY_PGC_PUP_
USB1_PHY_PGC_PUP_
MIPI_PHY1_PGC_PUP_
AUDIOMIX_PGC_PDN_
PCIE_PHY_PGC_PDN_
AUDIOMIX_PGC_PUP_
PCIE_PHY_PGC_PUP_
GPU_SHARE_LOGIC_
GPU_SHARE_LOGIC_
GPU_2D_PGC_PDN_
R
PGC_PDN_ACK
PGC_PUP_ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
GPC_ACK_SEL_M7_PU field descriptions
Field Description
31 Select power down acknowledge signal of HDMI_PHY PGC as the power up acknowledge for M7 LPM
HDMI_PHY_
PGC_PUP_ACK
30 Select power down acknowledge signal of HDMI_PHY PGC as the power down acknowledge for M7 LPM
HDMI_PHY_
PGC_PDN_ACK
29 Select power down acknowledge signal of HDMIMIX PGC as the power up acknowledge for M7 LPM
HDMIMIX_PGC_
PUP_ACK
28 Select power down acknowledge signal of HDMIMIX PGC as the power down acknowledge for M7 LPM
HDMIMIX_PGC_
PDN_ACK
27 Select power down acknowledge signal of VPU_VC8K PGC as the power up acknowledge for M7 LPM
VPU_VC8K_
PGC_PUP_ACK
26 Select power down acknowledge signal of VPU_VC8K PGC as the power down acknowledge for M7 LPM
VPU_VC8K_
PGC_PDN_ACK
25 Select power down acknowledge signal of VPU_G2 PGC as the power up acknowledge for M7 LPM
VPU_G2_PGC_
PUP_ACK
24 Select power down acknowledge signal of VPU_G2 PGC as the power down acknowledge for M7 LPM
VPU_G2_PGC_
PDN_ACK
23 Select power down acknowledge signal of VPU_G1 PGC as the power up acknowledge for M7 LPM
VPU_G1_PGC_
PUP_ACK
22 Select power down acknowledge signal of VPU_G1 PGC as the power down acknowledge for M7 LPM
VPU_G1_PGC_
PDN_ACK
21 Select power down acknowledge signal of MEDIMIX PGC as the power up acknowledge for M7 LPM
MEDIMIX_PGC_
PUP_ACK
20 Select power down acknowledge signal of MEDIMIX PGC as the power down acknowledge for M7 LPM
MEDIMIX_PGC_
PDN_ACK
19 Select power down acknowledge signal of GPU3D PGC as the power up acknowledge for M7 LPM
GPU3D_PGC_
PUP_ACK
18 Select power down acknowledge signal of GPU3D PGC as the power down acknowledge for M7 LPM
GPU3D_PGC_
PDN_ACK
17 Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power up acknowledge
VPUMIX_ for M7 LPM
SHARE_LOGIC_
PGC_PUP_ACK
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Chapter 5 Clocks and Power Management
GPC_ACK_SEL_M7_PU field descriptions (continued)
Field Description
16 Select power down acknowledge signal of VPUMIX_SHARE_LOGIC PGC as the power down
VPUMIX_ acknowledge for M7 LPM
SHARE_LOGIC_
PGC_PDN_ACK
15 Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power up acknowledge for
GPU_SHARE_ M7 LPM
LOGIC_PGC_
PUP_ACK
14 Select power down acknowledge signal of GPU_SHARE_LOGIC PGC as the power down acknowledge
GPU_SHARE_ for M7 LPM
LOGIC_PGC_
PDN_ACK
13 Select power down acknowledge signal of GPU_2D PGC as the power up acknowledge for M7 LPM
GPU_2D_PGC_
PUP_ACK
12 Select power down acknowledge signal of GPU_2D PGC as the power down acknowledge for M7 LPM
GPU_2D_PGC_
PDN_ACK
11 Select power down acknowledge signal of AUDIOMIX PGC as the power up acknowledge for M7 LPM
AUDIOMIX_
PGC_PUP_ACK
10 Select power down acknowledge signal of AUDIOMIX PGC as the power down acknowledge for M7 LPM
AUDIOMIX_
PGC_PDN_ACK
9 Select power down acknowledge signal of MLMIX PGC as the power up acknowledge for M7 LPM
MLMIX_PGC_
PUP_ACK
8 Select power down acknowledge signal of MLMIX PGC as the power down acknowledge for M7 LPM
MLMIX_PGC_
PDN_ACK
7 Select power down acknowledge signal of USB2_PHY PGC as the power up acknowledge for A53 LPM
USB2_PHY_
PGC_PUP_ACK
6 Select power down acknowledge signal of USB2_PHY PGC as the power down acknowledge for M7 LPM
USB2_PHY_
PGC_PDN_ACK
5 Select power down acknowledge signal of USB1_PHY PGC as the power up acknowledge for M7 LPM
USB1_PHY_
PGC_PUP_ACK
4 Select power down acknowledge signal of USB1_PHY PGC as the power down acknowledge for M7 LPM
USB1_PHY_
PGC_PDN_ACK
3 Select power down acknowledge signal of PCIE_PHY PGC as the power up acknowledge for M7 LPM
PCIE_PHY_
PGC_PUP_ACK
2 Select power down acknowledge signal of PCIE_PHY PGC as the power down acknowledge for M7 LPM
PCIE_PHY_
PGC_PDN_ACK
Table continues on the next page...
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General Power Controller (GPC)
GPC_ACK_SEL_M7_PU field descriptions (continued)
Field Description
1 Select power down acknowledge signal of MIPI_PHY1 PGC as the power up acknowledge for M7 LPM
MIPI_PHY1_
PGC_PUP_ACK
0 Select power down acknowledge signal of MIPI_PHY1 PGC as the power down acknowledge for M7 LPM
MIPI_PHY1_
PGC_PDN_ACK
5.2.10.71 PGC acknowledge signal selection of M7 platform for PUs
(GPC_ACK_SEL_M7_PU1)
Address: 303A_0000h base + 1C8h offset = 303A_01C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIOMIX_PGC_PDN_
HSIOMIX_PGC_PUP_
DDRMIX_PGC_PDN_
DDRMIX_PGC_PUP_
MEDIA_ISP_DWP_
MEDIA_ISP_DWP_
MIPI_PHY2_PGC_
MIPI_PHY2_PGC_
PGC_PDN_ACK
PGC_PUP_ACK
PDN_ACK
PUP_ACK
ACK
ACK
ACK
ACK
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_ACK_SEL_M7_PU1 field descriptions
Field Description
31–8 This field is reserved.
- Reserved
7 Select power down acknowledge signal of DDRMIX PGC as the power up acknowledge for M7 LPM
DDRMIX_PGC_
PUP_ACK
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Chapter 5 Clocks and Power Management
GPC_ACK_SEL_M7_PU1 field descriptions (continued)
Field Description
6 Select power down acknowledge signal of DDRMIX PGC as the power down acknowledge for M7 LPM
DDRMIX_PGC_
PDN_ACK
5 Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power up acknowledge for M7
MEDIA_ISP_ LPM
DWP_PGC_
PUP_ACK
4 Select power down acknowledge signal of MEDIA_ISP_DWP PGC as the power down acknowledge for
MEDIA_ISP_ M7 LPM
DWP_PGC_
PDN_ACK
3 Select power down acknowledge signal of HSIOMIX PGC as the power up acknowledge for M7 LPM
HSIOMIX_PGC_
PUP_ACK
2 Select power down acknowledge signal of HSIOMIX PGC as the power down acknowledge for M7 LPM
HSIOMIX_PGC_
PDN_ACK
1 Select power down acknowledge signal of MIPI_PHY2 PGC as the power up acknowledge for M7 LPM
MIPI_PHY2_
PGC_PUP_ACK
0 Select power down acknowledge signal of MIPI_PHY2 PGC as the power down acknowledge for M7 LPM
MIPI_PHY2_
PGC_PDN_ACK
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General Power Controller (GPC)
5.2.10.72 PGC CPU A53 mapping (GPC_PGC_CPU_A53_MAPPING)
Address: 303A_0000h base + 1CCh offset = 303A_01CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIPI_PHY2_DOMAIN
HDMI_PHY_DOMAIN
HDMIMIX_DOMAIN
MEDIA_ISP_DWP_
HSIOMIX_DOMAIN
DDRMIX_DOMAIN
R
DOMAIN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9
GPU_SHARE_LOGIC_ 8 7 6 5 4 3 2 1 0
MIX0_SUPERMIXM7_
VPU_VC8K_DOMAIN
USB2_PHY_DOMAIN
USB1_PHY_DOMAIN
MIPI_PHY1_DOMAIN
MIX1_NOC_DOMAIN
AUDIOMIX_DOMAIN
PCIE_PHY_DOMAIN
MEDIMIX_DOMAIN
GPU_2D_DOMAIN
VPU_G2_DOMAIN
VPU_G1_DOMAIN
VPUMIX_SHARE_
GPU3D_DOMAIN
MLMIX_DOMAIN
LOGIC_DOMAIN
R
DOMAIN
DOMAIN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_CPU_A53_MAPPING field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21 DDR mapping
DDRMIX_
DOMAIN 0 Don’t map DDR to A53 domain
1 Map DDR to A53 domain
20 MEDIA_ISP_DWP_DOMAIN mapping
MEDIA_ISP_
DWP_DOMAIN 0 Don’t map MEDIA_ISP_DWP_DOMAIN to A53 domain
1 Map DDR to MEDIA_ISP_DWP_DOMAIN domain
19 HSIOMIX mapping
HSIOMIX_
DOMAIN 0 Don’t map HSIOMIX to A53 domain
1 Map HSIOMIX to A53 domain
18 MIPI PHY2 mapping
MIPI_PHY2_
DOMAIN 0 Don’t map MIPI PHY2 to A53 domain
1 Map MIPI PHY2 to A53 domain
17 HDMI PHY mapping
HDMI_PHY_
DOMAIN
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Chapter 5 Clocks and Power Management
GPC_PGC_CPU_A53_MAPPING field descriptions (continued)
Field Description
0 Don’t map HDMI PHY to A53 domain
1 Map HDMI PHY to A53 domain
16 HDMI mapping
HDMIMIX_
DOMAIN 0 Don’t map HDMI to A53 domain
1 Map HDMI to A53 domain
15 VPU_VC8K mapping
VPU_VC8K_
DOMAIN 0 Don’t map VPU_VC8K to A53 domain
1 Map VPU_VC8K to A53 domain
14 VPU_G2 mapping
VPU_G2_
DOMAIN 0 Don’t map VPU_G1 to A53 domain
1 Map VPU_G1 to A53 domain
13 VPU_G1 mapping
VPU_G1_
DOMAIN 0 Don’t map VPU_G1 to A53 domain
1 Map VPU_G1 to A53 domain
12 MEDIMIX mapping
MEDIMIX_
DOMAIN 0 Don’t map MEDIMIX to A53 domain
1 Map MEDIMIX to A53 domain
11 GPU3D mapping
GPU3D_DOMAIN
0 Don’t map GPU2D to A53 domain
1 Map GPU2D to A53 domain
10 VPUMIX Share Logic mapping
VPUMIX_
SHARE_LOGIC_ 0 Don’t map VPUMIX Share Logic to A53 domain
DOMAIN 1 Map VPUMIX Share Logic to A53 domain
9 GPU_SHARE_LOGIC mapping
GPU_SHARE_
LOGIC_DOMAIN 0 Don’t map GPU Share Logic to A53 domain
1 Map GPU Share Logic to A53 domain
8 GPU2D mapping
GPU_2D_
DOMAIN 0 Don’t map GPU2D to A53 domain
1 Map GPU2D to A53 domain
7 AUDIOMIX mapping
AUDIOMIX_
DOMAIN 0 Don’t map AUDIOMIX to A53 domain
1 Map AUDIOMIX to A53 domain
6 MLMIX mapping
MLMIX_DOMAIN
0 Don’t map MLMIX to A53 domain
1 Map MLMIX to A53 domain
5 USB2_PHY mapping
USB2_PHY_
DOMAIN
Table continues on the next page...
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General Power Controller (GPC)
GPC_PGC_CPU_A53_MAPPING field descriptions (continued)
Field Description
0 Don’t map USB2_PHY to A53 domain
1 Map USB2_PHY to A53 domain
4 USB1_PHY mapping
USB1_PHY_
DOMAIN 0 Don’t map USB1_PHY to A53 domain
1 Map USB1_PHY to A53 domain
3 PCIE_PHY mapping
PCIE_PHY_
DOMAIN 0 Don’t map PCIE_PHY to A53 domain
1 Map PCIE_PHY to A53 domain
2 MIPI_PHY1 mapping
MIPI_PHY1_
DOMAIN 0 Don’t map MIPI_PHY1 to A53 domain
1 Map MIPI_PHY1 to A53 domain
1 MIX1 (NOC) mapping
MIX1_NOC_
DOMAIN 0 Don’t map NOC to A53 domain
1 Map NOC to A53 domain
0 MIX0 (SUPERMIXM7) mapping
MIX0_
SUPERMIXM7_ 0 Don’t map M7 to A53 domain
DOMAIN 1 Map M7 to A53 domain
5.2.10.73 PGC CPU M7 mapping (GPC_PGC_CPU_M7_MAPPING)
Address: 303A_0000h base + 1D0h offset = 303A_01D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MIPI_PHY2_DOMAIN
HDMI_PHY_DOMAIN
HDMIMIX_DOMAIN
MEDIA_ISP_DWP_
HSIOMIX_DOMAIN
DDRMIX_DOMAIN
R
DOMAIN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU_SHARE_LOGIC_
MIX0_SUPERMIXM7_
VPU_VC8K_DOMAIN
USB2_PHY_DOMAIN
USB1_PHY_DOMAIN
MIPI_PHY1_DOMAIN
MIX1_NOC_DOMAIN
AUDIOMIX_DOMAIN
PCIE_PHY_DOMAIN
MEDIMIX_DOMAIN
GPU_2D_DOMAIN
VPU_G2_DOMAIN
VPU_G1_DOMAIN
VPUMIX_SHARE_
GPU3D_DOMAIN
MLMIX_DOMAIN
LOGIC_DOMAIN
R
DOMAIN
DOMAIN
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 5 Clocks and Power Management
GPC_PGC_CPU_M7_MAPPING field descriptions
Field Description
31–22 This field is reserved.
- Reserved
21 DDR mapping
DDRMIX_
DOMAIN 0 Don’t map DDR to M7 domain
1 Map DDR to M7 domain
20 MEDIA_ISP_DWP_DOMAIN mapping
MEDIA_ISP_
DWP_DOMAIN 0 Don’t map MEDIA_ISP_DWP_DOMAIN to M7 domain
1 Map MEDIA_ISP_DWP_DOMAIN to M7 domain
19 HSIOMIX mapping
HSIOMIX_
DOMAIN 0 Don’t map HSIOMIX to M7 domain
1 Map HSIOMIX to M7 domain
18 MIPI PHY2 mapping
MIPI_PHY2_
DOMAIN 0 Don’t map MIPI PHY2 to M7 domain
1 Map MIPI PHY2 to M7 domain
17 HDMI PHY mapping
HDMI_PHY_
DOMAIN 0 Don’t map HDMI PHY to M7 domain
1 Map HDMI PHY to M7 domain
16 HDMI mapping
HDMIMIX_
DOMAIN 0 Don’t map HDMI to M7 domain
1 Map HDMI to M7 domain
15 VPU_VC8K mapping
VPU_VC8K_
DOMAIN 0 Don’t map VPU_VC8K to M7 domain
1 Map VPU_VC8K to M7 domain
14 VPU_G2 mapping
VPU_G2_
DOMAIN 0 Don’t map VPU_G1 to M7 domain
1 Map VPU_G1 to M7 domain
13 VPU_G1 mapping
VPU_G1_
DOMAIN 0 Don’t map VPU_G1 to M7 domain
1 Map VPU_G1 to M7 domain
12 MEDIMIX mapping
MEDIMIX_
DOMAIN 0 Don’t map MEDIMIX to M7 domain
1 Map MEDIMIX to M7 domain
11 GPU3D mapping
GPU3D_DOMAIN
0 Don’t map GPU2D to M7 domain
1 Map GPU2D to M7 domain
Table continues on the next page...
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General Power Controller (GPC)
GPC_PGC_CPU_M7_MAPPING field descriptions (continued)
Field Description
10 VPUMIX Share Logic mapping
VPUMIX_
SHARE_LOGIC_ 0 Don’t map VPUMIX Share Logic to M7 domain
DOMAIN 1 Map VPUMIX Share Logic to M7 domain
9 GPU_SHARE_LOGIC mapping
GPU_SHARE_
LOGIC_DOMAIN 0 Don’t map GPU Share Logic to M7 domain
1 Map GPU Share Logic to M7 domain
8 GPU2D mapping
GPU_2D_
DOMAIN 0 Don’t map GPU2D to M7 domain
1 Map GPU2D to M7 domain
7 AUDIOMIX mapping
AUDIOMIX_
DOMAIN 0 Don’t map AUDIOMIX to M7 domain
1 Map AUDIOMIX to M7 domain
6 MLMIX mapping
MLMIX_DOMAIN
0 Don’t map MLMIX to M7 domain
1 Map MLMIX to M7 domain
5 USB2_PHY mapping
USB2_PHY_
DOMAIN 0 Don’t map USB2_PHY to M7 domain
1 Map USB2_PHY to M7 domain
4 USB1_PHY mapping
USB1_PHY_
DOMAIN 0 Don’t map USB1_PHY to M7 domain
1 Map USB1_PHY to M7 domain
3 PCIE_PHY mapping
PCIE_PHY_
DOMAIN 0 Don’t map PCIE_PHY to M7 domain
1 Map PCIE_PHY to M7 domain
2 MIPI_PHY1 mapping
MIPI_PHY1_
DOMAIN 0 Don’t map MIPI_PHY1 to M7 domain
1 Map MIPI_PHY1 to M7 domain
1 MIX1 (NOC) mapping
MIX1_NOC_
DOMAIN 0 Don’t map MIX1_NOC to M7 domain
1 Map MIX1_NOC to M7 domain
0 MIX0 (SUPERMIXM7) mapping
MIX0_
SUPERMIXM7_ 0 Don’t map MIX0_SUPERMIXM7 to M7 domain
DOMAIN 1 Map MIX0_SUPERMIXM7 to M7 domain
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Chapter 5 Clocks and Power Management
5.2.10.74 Slot configure register for CPUs (GPC_SLTn_CFG)
There are 27 slots in each SLTn_CFG(n = 0~26) that define the power up or power down
behavior of one or more A53 core, NOC, or SCU PGC in each slot. This array contains
slots 0 to 14, see Memory Map for slots 15 to 19.
In each “SLTn_cfg”, 2 bits (slt_cfg[1:0])are reserved for each PGC:
• 2’b01 (slot controller will power down relevant PGC in corresponding slot if
hardware power down request asserted)
• 2’b10 (slot controller will power up relevant PGC in corresponding slot if hardware
power up request asserted)
• 2’b00 or 2’b11 (not power down or power up behavior in relevant slot)
The specific bits assignment for each PGC is shown in the table below.
PGCx PGCx-1 .. PGC2 PGC1 PGC0
SLT0_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLT1_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
: slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
SLTn_CFG slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0] slt_cfg[1:0]
Address: 303A_0000h base + 200h offset + (4d × i), where i=0d to 26d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CORE3_A53_PDN_
CORE2_A53_PDN_
CORE1_A53_PDN_
CORE0_A53_PDN_
CORE3_A53_PUP_
CORE2_A53_PUP_
CORE1_A53_PUP_
CORE0_A53_PUP_
NOC_PDN_SLOT_
NOC_PUP_SLOT_
SCU_PDN_SLOT_
SCU_PUP_SLOT_
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
SLOT_CONTROL
R
CONTROL
CONTROL
CONTROL
CONTROL
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 643
General Power Controller (GPC)
GPC_SLTn_CFG field descriptions
Field Description
31–14 This field is reserved.
-
13 NOC Power-up slot control
NOC_PUP_
SLOT_
CONTROL
12 NOC Power-down slot control
NOC_PDN_
SLOT_
CONTROL
11–10 This field is reserved.
-
9 SCU Power-up slot control
SCU_PUP_
SLOT_
CONTROL
8 SCU Power-down slot control
SCU_PDN_
SLOT_
CONTROL
7 CORE3 A53 Power-up slot control
CORE3_A53_
PUP_SLOT_
CONTROL
6 CORE3 A53 Power-down slot control
CORE3_A53_
PDN_SLOT_
CONTROL
5 CORE2 A53 Power-up slot control
CORE2_A53_
PUP_SLOT_
CONTROL
4 CORE2 A53 Power-down slot control
CORE2_A53_
PDN_SLOT_
CONTROL
3 CORE1 A53 Power-up slot control
CORE1_A53_
PUP_SLOT_
CONTROL
2 CORE1 A53 Power-down slot control
CORE1_A53_
PDN_SLOT_
CONTROL
1 CORE0 A53 Power-up slot control
CORE0_A53_
PUP_SLOT_
CONTROL
Table continues on the next page...
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644 NXP Semiconductors
W
R
W
R
Reset
Bit
Reset
Bit
PUs.
0
GPU_SHARE_LOGIC_ HDMI_PHY_PUP_SLOT_
0
0
15
31
Field
PUP_SLOT_CONTROL CONTROL
CONTROL
PDN_SLOT_
CORE0_A53_
GPU_SHARE_LOGIC_ HDMI_PHY_PDN_SLOT_
0
0
14
30
PDN_SLOT_CONTROL CONTROL
NXP Semiconductors
GPU_2D_PUP_SLOT_ HDMIMIX_PUP_SLOT_
0
0
13
29
CONTROL CONTROL
GPU_2D_PDN_SLOT_ HDMIMIX_PDN_SLOT_
0
0
12
28
CONTROL CONTROL
AUDIOMIX_PUP_SLOT_ VPU_VC8K_PUP_SLOT_
0
0
11
27
CONTROL CONTROL
AUDIOMIX_PDN_SLOT_ VPU_VC8K_PDN_SLOT_
0
0
10
26
CONTROL CONTROL
MLMIX_PUP_SLOT_ VPU_G2_PUP_SLOT_
0
0
CORE0 A53 Power-down slot control
25
CONTROL CONTROL
MLMIX_PDN_SLOT_ VPU_G2_PDN_SLOT_
0
0
24
CONTROL CONTROL
USB2_PHY_PUP_SLOT_ VPU_G1_PUP_SLOT_
Address: 303A_0000h base + 280h offset + (8d × i), where i=0d to 26d
0
0
23
CONTROL CONTROL
USB2_PHY_PDN_SLOT_ VPU_G1_PDN_SLOT_
0
0
22
Description
CONTROL CONTROL
USB1_PHY_PUP_SLOT_ MEDIMIX_PUP_SLOT_
0
0
21
CONTROL CONTROL
USB1_PHY_PDN_SLOT_ MEDIMIX_PDN_SLOT_
0
0
20
CONTROL CONTROL
GPC_SLTn_CFG field descriptions (continued)
PCIE_PHY_PUP_SLOT_ GPU3D_PUP_SLOT_
0
0
19
CONTROL CONTROL
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
PCIE_PHY_PDN_SLOT_ GPU3D_PDN_SLOT_
2
0
0
18
CONTROL CONTROL
MIPI_PHY1_PUP_SLOT_ VPUMIX_SHARE_LOGIC_
1
0
0
17
CONTROL PUP_SLOT_CONTROL
MIPI_PHY1_PDN_SLOT_ VPUMIX_SHARE_LOGIC_
0
0
0
5.2.10.75 Slot configure register for PGC PUs (GPC_SLTn_CFG_PU)
16
There are 27 slots in each SLTn_CFG_PU (n = 0~26) that define the power up or power
down behavior of PU PGC in each slot. See PGC power domains section for list of PGC
CONTROL PDN_SLOT_CONTROL
645
Chapter 5 Clocks and Power Management
General Power Controller (GPC)
GPC_SLTn_CFG_PU field descriptions
Field Description
31 HDMI_PHY power up slot control
HDMI_PHY_
PUP_SLOT_
CONTROL
30 HDMI_PHY power down slot control
HDMI_PHY_
PDN_SLOT_
CONTROL
29 HDMIMIX power up slot control
HDMIMIX_PUP_
SLOT_
CONTROL
28 HDMIMIX power down slot control
HDMIMIX_PDN_
SLOT_
CONTROL
27 VPU_VC8K power up slot control
VPU_VC8K_
PUP_SLOT_
CONTROL
26 VPU_VC8K power down slot control
VPU_VC8K_
PDN_SLOT_
CONTROL
25 VPU_G2 power up slot control
VPU_G2_PUP_
SLOT_
CONTROL
24 VPU_G2 power down slot control
VPU_G2_PDN_
SLOT_
CONTROL
23 VPU_G1 power up slot control
VPU_G1_PUP_
SLOT_
CONTROL
22 VPU_G1 power down slot control
VPU_G1_PDN_
SLOT_
CONTROL
21 MEDIMIX power up slot control
MEDIMIX_PUP_
SLOT_
CONTROL
20 MEDIMIX power down slot control
MEDIMIX_PDN_
SLOT_
CONTROL
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_SLTn_CFG_PU field descriptions (continued)
Field Description
19 GPU3D power up slot control
GPU3D_PUP_
SLOT_
CONTROL
18 GPU3D power down slot control
GPU3D_PDN_
SLOT_
CONTROL
17 VPUMIX_SHARE_LOGIC power up slot control
VPUMIX_
SHARE_LOGIC_
PUP_SLOT_
CONTROL
16 VPUMIX_SHARE_LOGIC power down slot control
VPUMIX_
SHARE_LOGIC_
PDN_SLOT_
CONTROL
15 GPU_SHARE_LOGIC power up slot control
GPU_SHARE_
LOGIC_PUP_
SLOT_
CONTROL
14 GPU_SHARE_LOGIC power down slot control
GPU_SHARE_
LOGIC_PDN_
SLOT_
CONTROL
13 GPU_2D power up slot control
GPU_2D_PUP_
SLOT_
CONTROL
12 GPU_2D power down slot control
GPU_2D_PDN_
SLOT_
CONTROL
11 AUDIOMIX power up slot control
AUDIOMIX_
PUP_SLOT_
CONTROL
10 AUDIOMIX power down slot control
AUDIOMIX_
PDN_SLOT_
CONTROL
9 MLMIX power up slot control
MLMIX_PUP_
SLOT_
CONTROL
Table continues on the next page...
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NXP Semiconductors 647
General Power Controller (GPC)
GPC_SLTn_CFG_PU field descriptions (continued)
Field Description
8 MLMIX power down slot control
MLMIX_PDN_
SLOT_
CONTROL
7 USB2_PHY power up slot control
USB2_PHY_
PUP_SLOT_
CONTROL
6 USB2_PHY power down slot control
USB2_PHY_
PDN_SLOT_
CONTROL
5 USB1_PHY power up slot control
USB1_PHY_
PUP_SLOT_
CONTROL
4 USB1_PHY power down slot control
USB1_PHY_
PDN_SLOT_
CONTROL
3 PCIE_PHY power up slot control
PCIE_PHY_
PUP_SLOT_
CONTROL
2 PCIE_PHY power down slot control
PCIE_PHY_
PDN_SLOT_
CONTROL
1 MIPI_PHY1 power up slot control
MIPI_PHY1_
PUP_SLOT_
CONTROL
0 MIPI_PHY1 power down slot control
MIPI_PHY1_
PDN_SLOT_
CONTROL
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Chapter 5 Clocks and Power Management
5.2.10.76 Extended slot configure register for PGC PUs
(GPC_SLTn_CFG_PU1)
Address: 303A_0000h base + 284h offset + (8d × i), where i=0d to 26d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIPI_PHY2_PDN_SLOT_
MIPI_PHY2_PUP_SLOT_
MEDIA_ISP_DWP_PDN_
MEDIA_ISP_DWP_PUP_
HSIOMIX_PDN_SLOT_
HSIOMIX_PUP_SLOT_
DDRMIX_PDN_SLOT_
DDRMIX_PUP_SLOT_
SLOT_CONTROL
SLOT_CONTROL
M7_PDN_SLOT_
M7_PUP_SLOT_
R
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GPC_SLTn_CFG_PU1 field descriptions
Field Description
31–10 This field is reserved.
- Reserved
9 M7 power up slot control
M7_PUP_SLOT_
CONTROL
8 M7 power down slot control
M7_PDN_SLOT_
CONTROL
7 DDRMIX power up slot control
DDRMIX_PUP_
SLOT_
CONTROL
6 DDRMIX power down slot control
DDRMIX_PDN_
SLOT_
CONTROL
Table continues on the next page...
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NXP Semiconductors 649
General Power Controller (GPC)
GPC_SLTn_CFG_PU1 field descriptions (continued)
Field Description
5 MEDIA_ISP_DWP power up slot control
MEDIA_ISP_
DWP_PUP_
SLOT_
CONTROL
4 MEDIA_ISP_DWP power down slot control
MEDIA_ISP_
DWP_PDN_
SLOT_
CONTROL
3 HSIOMIX power up slot control
HSIOMIX_PUP_
SLOT_
CONTROL
2 HSIOMIX power down slot control
HSIOMIX_PDN_
SLOT_
CONTROL
1 MIPI_PHY2 power up slot control
MIPI_PHY2_
PUP_SLOT_
CONTROL
0 MIPI_PHY2 power down slot control
MIPI_PHY2_
PDN_SLOT_
CONTROL
5.2.11 GPC PGC Memory Map/Register Definition
There are numerous PGC inside GPCv2, with 4 different types: CPU/SCU/MIX/PU.
Each PGC type has 4 different control words PGC_CTRL, PGC_PUPSCR,
PGC_PDNSCR, and PGC_SR. Different PGC types may have different field definition in
these four registers. There is another extra control word PGC_AUXSW which has
different field definition for SCU type PGC.
The total GPC memory map is 4KB
Table 5-11. Memory Regions
Address Range(offset) Region
0x000 - 0x3FF GPC configuration register
0x400 - 0x7FF Reserved
0x800 - 0x9FF CPU and SCU type PGC register base address
Table continues on the next page...
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Chapter 5 Clocks and Power Management
Table 5-11. Memory Regions (continued)
Address Range(offset) Region
0xA00 - 0xAFF MIX type PGC register base address
0xB00 - 0xFFF PU type PGC register base address
Each PGC (CPU type, MIX type, PU type) will occupy 64 Bytes address space, the
specific base address of each PGC are listed as below.
• 0x800 ~ 0x83F: PGC for A53 core0
• 0x840 ~ 0x87F: PGC for A53 core1
• 0x880 ~ 0x8BF: PGC for A53 core2
• 0x8C0 ~ 0x8FF: PGC for A53 core3
• 0x900 ~ 0x93F: PGC for A53 SCU
• 0xA40 ~ 0xA7F: PGC for NOC mix
• 0xB00 ~ 0xB3F: PGC for MIPI PHY1 (PU0)
• 0xB40 ~ 0xB7F: PGC for PCIE PHY (PU1)
• 0xB80 ~ 0xBBF: PGC for USB1_PHY (PU2)
• 0xBC0 ~ 0xBFF: PGC for USB2_PHY (PU3)
• 0xC00 ~ 0xC3F: PGC for ML (PU4)
• 0xC40 ~ 0xC7F: PGC for AUDIO (PU5)
• 0xC80 ~ 0xCBF: PGC for GPU2D (PU6)
• 0xCC0 ~ 0xCFF: PGC for GPU Shared Logic (PU7)
• 0xD00 ~ 0xD3F: PGC for VPU Shared Logic (PU8)
• 0xD40 ~ 0xD7F: PGC for GPU3D (PU9)
• 0xD80 ~ 0xDBF: PGC for Medi (PU10)
• 0xDC0 ~ 0xDFF: PGC for VPU_G1 (PU11)
• 0xE00 ~ 0xE3F: PGC for VPU_G2 (PU12)
• 0xE40 ~ 0xE7F: PGC for VPU VC8000E (PU13)
• 0xE80 ~ 0xEBF: PGC for HDMI (PU14)
• 0xEC0 ~ 0xEFF: PGC for HDMI PHY (PU15)
• 0xF00 ~ 0xF3F: PGC for MIPI PHY2 (PU16)
• 0xF40 ~ 0xF7F: PGC for HSIO (PU17)
• 0xF80 ~ 0xFBF: PGC for ISP DWP (PU18)
• 0xFC0 ~ 0xFFF: PGC for DDR (PU19)
GPC_PGC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Control Register for PGC CPUs
303A_0800 32 R/W 0604_0202h 5.2.11.1/706
(GPC_PGC_A53CORE0_CTRL)
Table continues on the next page...
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General Power Controller (GPC)
GPC_PGC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Up Sequence Control Register
303A_0804 32 R/W 0009_97C1h 5.2.11.2/708
(GPC_PGC_A53CORE0_PUPSCR)
GPC PGC Down Sequence Control Register
303A_0808 32 R/W 2100_0801h 5.2.11.3/709
(GPC_PGC_A53CORE0_PDNSCR)
303A_080C GPC PGC Status Register (GPC_PGC_A53CORE0_SR) 32 R/W 0000_1000h 5.2.11.4/710
GPC PGC Control Register for PGC CPUs
303A_0840 32 R/W 0604_0202h 5.2.11.1/706
(GPC_PGC_A53CORE1_CTRL)
GPC PGC Up Sequence Control Register
303A_0844 32 R/W 0009_97C1h 5.2.11.2/708
(GPC_PGC_A53CORE1_PUPSCR)
GPC PGC Down Sequence Control Register
303A_0848 32 R/W 2100_0801h 5.2.11.3/709
(GPC_PGC_A53CORE1_PDNSCR)
303A_084C GPC PGC Status Register (GPC_PGC_A53CORE1_SR) 32 R/W 0000_1000h 5.2.11.4/710
GPC PGC Control Register for PGC CPUs
303A_0880 32 R/W 0604_0202h 5.2.11.1/706
(GPC_PGC_A53CORE2_CTRL)
GPC PGC Up Sequence Control Register
303A_0884 32 R/W 0009_97C1h 5.2.11.2/708
(GPC_PGC_A53CORE2_PUPSCR)
GPC PGC Down Sequence Control Register
303A_0888 32 R/W 2100_0801h 5.2.11.3/709
(GPC_PGC_A53CORE2_PDNSCR)
303A_088C GPC PGC Status Register (GPC_PGC_A53CORE2_SR) 32 R/W 0000_1000h 5.2.11.4/710
GPC PGC Control Register for PGC CPUs
303A_08C0 32 R/W 0604_0202h 5.2.11.1/706
(GPC_PGC_A53CORE3_CTRL)
GPC PGC Up Sequence Control Register
303A_08C4 32 R/W 0009_97C1h 5.2.11.2/708
(GPC_PGC_A53CORE3_PUPSCR)
GPC PGC Down Sequence Control Register
303A_08C8 32 R/W 2100_0801h 5.2.11.3/709
(GPC_PGC_A53CORE3_PDNSCR)
303A_08CC GPC PGC Status Register (GPC_PGC_A53CORE3_SR) 32 R/W 0000_1000h 5.2.11.4/710
GPC PGC Control Register for PGC CPUs
303A_0900 32 R/W 0604_0202h 5.2.11.1/706
(GPC_PGC_A53SCU_CTRL)
GPC PGC Up Sequence Control Register
303A_0904 32 R/W 0009_97C1h 5.2.11.2/708
(GPC_PGC_A53SCU_PUPSCR)
GPC PGC Down Sequence Control Register
303A_0908 32 R/W 2100_0801h 5.2.11.3/709
(GPC_PGC_A53SCU_PDNSCR)
303A_090C GPC PGC Status Register (GPC_PGC_A53SCU_SR) 32 R/W 0000_1000h 5.2.11.4/710
GPC PGC Control Register for PGC MIX.
303A_0A40 32 R/W 0604_0202h 5.2.11.5/713
(GPC_PGC_NOC_MIX_CTRL)
GPC PGC Up Sequence Control Register
303A_0A44 32 R/W 0009_97C1h 5.2.11.6/714
(GPC_PGC_NOC_MIX_PUPSCR)
GPC PGC Down Sequence Control Register
303A_0A48 32 R/W 2100_0801h 5.2.11.7/715
(GPC_PGC_NOC_MIX_PDNSCR)
303A_0A4C GPC PGC Status Register (GPC_PGC_NOC_MIX_SR) 32 R/W 0000_1000h 5.2.11.8/716
GPC PGC Control Register for PGC PUs
303A_0B00 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU0_CTRL)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_PGC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0B04 32 R/W 0009_97C1h
(GPC_PGC_PU0_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0B08 32 R/W 2100_0801h
(GPC_PGC_PU0_PDNSCR) 721
5.2.11.12/
303A_0B0C GPC PGC Status Register (GPC_PGC_PU0_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0B40 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU1_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0B44 32 R/W 0009_97C1h
(GPC_PGC_PU1_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0B48 32 R/W 2100_0801h
(GPC_PGC_PU1_PDNSCR) 721
5.2.11.12/
303A_0B4C GPC PGC Status Register (GPC_PGC_PU1_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0B80 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU2_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0B84 32 R/W 0009_97C1h
(GPC_PGC_PU2_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0B88 32 R/W 2100_0801h
(GPC_PGC_PU2_PDNSCR) 721
5.2.11.12/
303A_0B8C GPC PGC Status Register (GPC_PGC_PU2_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0BC0 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU3_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0BC4 32 R/W 0009_97C1h
(GPC_PGC_PU3_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0BC8 32 R/W 2100_0801h
(GPC_PGC_PU3_PDNSCR) 721
5.2.11.12/
303A_0BCC GPC PGC Status Register (GPC_PGC_PU3_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0C00 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU4_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0C04 32 R/W 0009_97C1h
(GPC_PGC_PU4_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0C08 32 R/W 2100_0801h
(GPC_PGC_PU4_PDNSCR) 721
5.2.11.12/
303A_0C0C GPC PGC Status Register (GPC_PGC_PU4_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0C40 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU5_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0C44 32 R/W 0009_97C1h
(GPC_PGC_PU5_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0C48 32 R/W 2100_0801h
(GPC_PGC_PU5_PDNSCR) 721
Table continues on the next page...
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General Power Controller (GPC)
GPC_PGC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.11.12/
303A_0C4C GPC PGC Status Register (GPC_PGC_PU5_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0C80 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU6_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0C84 32 R/W 0009_97C1h
(GPC_PGC_PU6_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0C88 32 R/W 2100_0801h
(GPC_PGC_PU6_PDNSCR) 721
5.2.11.12/
303A_0C8C GPC PGC Status Register (GPC_PGC_PU6_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0CC0 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU7_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0CC4 32 R/W 0009_97C1h
(GPC_PGC_PU7_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0CC8 32 R/W 2100_0801h
(GPC_PGC_PU7_PDNSCR) 721
5.2.11.12/
303A_0CCC GPC PGC Status Register (GPC_PGC_PU7_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0D00 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU8_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0D04 32 R/W 0009_97C1h
(GPC_PGC_PU8_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0D08 32 R/W 2100_0801h
(GPC_PGC_PU8_PDNSCR) 721
5.2.11.12/
303A_0D0C GPC PGC Status Register (GPC_PGC_PU8_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0D40 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU9_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0D44 32 R/W 0009_97C1h
(GPC_PGC_PU9_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0D48 32 R/W 2100_0801h
(GPC_PGC_PU9_PDNSCR) 721
5.2.11.12/
303A_0D4C GPC PGC Status Register (GPC_PGC_PU9_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0D80 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU10_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0D84 32 R/W 0009_97C1h
(GPC_PGC_PU10_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0D88 32 R/W 2100_0801h
(GPC_PGC_PU10_PDNSCR) 721
5.2.11.12/
303A_0D8C GPC PGC Status Register (GPC_PGC_PU10_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0DC0 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU11_CTRL)
Table continues on the next page...
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Chapter 5 Clocks and Power Management
GPC_PGC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0DC4 32 R/W 0009_97C1h
(GPC_PGC_PU11_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0DC8 32 R/W 2100_0801h
(GPC_PGC_PU11_PDNSCR) 721
5.2.11.12/
303A_0DCC GPC PGC Status Register (GPC_PGC_PU11_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0E00 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU12_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0E04 32 R/W 0009_97C1h
(GPC_PGC_PU12_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0E08 32 R/W 2100_0801h
(GPC_PGC_PU12_PDNSCR) 721
5.2.11.12/
303A_0E0C GPC PGC Status Register (GPC_PGC_PU12_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0E40 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU13_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0E44 32 R/W 0009_97C1h
(GPC_PGC_PU13_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0E48 32 R/W 2100_0801h
(GPC_PGC_PU13_PDNSCR) 721
5.2.11.12/
303A_0E4C GPC PGC Status Register (GPC_PGC_PU13_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0E80 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU14_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0E84 32 R/W 0009_97C1h
(GPC_PGC_PU14_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0E88 32 R/W 2100_0801h
(GPC_PGC_PU14_PDNSCR) 721
5.2.11.12/
303A_0E8C GPC PGC Status Register (GPC_PGC_PU14_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0EC0 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU15_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0EC4 32 R/W 0009_97C1h
(GPC_PGC_PU15_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0EC8 32 R/W 2100_0801h
(GPC_PGC_PU15_PDNSCR) 721
5.2.11.12/
303A_0ECC GPC PGC Status Register (GPC_PGC_PU15_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0F00 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU16_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0F04 32 R/W 0009_97C1h
(GPC_PGC_PU16_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0F08 32 R/W 2100_0801h
(GPC_PGC_PU16_PDNSCR) 721
Table continues on the next page...
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GPC_PGC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
5.2.11.12/
303A_0F0C GPC PGC Status Register (GPC_PGC_PU16_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0F40 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU17_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0F44 32 R/W 0009_97C1h
(GPC_PGC_PU17_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0F48 32 R/W 2100_0801h
(GPC_PGC_PU17_PDNSCR) 721
5.2.11.12/
303A_0F4C GPC PGC Status Register (GPC_PGC_PU17_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0F80 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU18_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0F84 32 R/W 0009_97C1h
(GPC_PGC_PU18_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0F88 32 R/W 2100_0801h
(GPC_PGC_PU18_PDNSCR) 721
5.2.11.12/
303A_0F8C GPC PGC Status Register (GPC_PGC_PU18_SR) 32 R/W 0000_1000h
722
GPC PGC Control Register for PGC PUs
303A_0FC0 32 R/W 0604_0202h 5.2.11.9/719
(GPC_PGC_PU19_CTRL)
GPC PGC Up Sequence Control Register 5.2.11.10/
303A_0FC4 32 R/W 0009_97C1h
(GPC_PGC_PU19_PUPSCR) 720
GPC PGC Down Sequence Control Register 5.2.11.11/
303A_0FC8 32 R/W 2100_0801h
(GPC_PGC_PU19_PDNSCR) 721
5.2.11.12/
303A_0FCC GPC PGC Status Register (GPC_PGC_PU19_SR) 32 R/W 0000_1000h
722
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5.2.11.1 GPC PGC Control Register for PGC CPUs
(GPC_PGC_nCTRL)
GPC PGC Control Register for the PGC CPUs. See the PGC Memory Map for the
assignments.
Address: 303A_0000h base + 800h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved DFTRAM_TCD1 L2RSTDIS PCR
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
GPC_PGC_nCTRL field descriptions
Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
23–22 This field is reserved.
- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved
Table continues on the next page...
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GPC_PGC_nCTRL field descriptions (continued)
Field Description
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
PCR Power Control
NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.
0 Do not switch off power even if pdn_req is asserted.
1 Switch off power when pdn_req is asserted.
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5.2.11.2 GPC PGC Up Sequence Control Register
(GPC_PGC_nPUPSCR)
GPC PGC Up Sequence Control Register
Address: 303A_0000h base + 804h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SW2ISO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
SW2ISO SW
Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
GPC_PGC_nPUPSCR field descriptions
Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 This field is reserved.
- Reserved
SW
After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW
before asserting switch_b
NOTE: SW must not be programmed to zero.
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5.2.11.3 GPC PGC Down Sequence Control Register
(GPC_PGC_nPDNSCR)
GPC PGC Down Sequence Control Register
Address: 303A_0000h base + 808h offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
GPC_PGC_nPDNSCR field descriptions
Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b
NOTE: ISO2SW must not be programmed to zero.
7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation
NOTE: ISO must not be programmed to zero.
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5.2.11.4 GPC PGC Status Register (GPC_PGC_nSR)
GPC PGC Status Register
Address: 303A_0000h base + 80Ch offset + (64d × i), where i=0d to 4d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L2RSTDIS_
Reserved DEASSERT_
CNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L2RETN_FLAG
ALLOFF_FLAG
PSR
R
Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_nSR field descriptions
Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
Table continues on the next page...
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GPC_PGC_nSR field descriptions (continued)
Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.
NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from ALL_OFF mode.
1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag
NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from L2 retention mode.
1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.
0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.
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General Power Controller (GPC)
5.2.11.5 GPC PGC Control Register for PGC MIX.
(GPC_PGC_NOC_MIX_CTRL)
GPC PGC Control Register.
Address: 303A_0000h base + A40h offset = 303A_0A40h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
MIX_
Reserved DFTRAM_TCD1 L2RSTDIS
PCR
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
GPC_PGC_NOC_MIX_CTRL field descriptions
Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
23–22 This field is reserved.
- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved
Table continues on the next page...
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GPC_PGC_NOC_MIX_CTRL field descriptions (continued)
Field Description
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
MIX_PCR Power Control
NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.
0 Do not switch off power even if pdn_req is asserted.
1 Switch off power when pdn_req is asserted.
5.2.11.6 GPC PGC Up Sequence Control Register
(GPC_PGC_NOC_MIX_PUPSCR)
GPC PGC Up Sequence Control Register
Address: 303A_0000h base + A44h offset = 303A_0A44h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SW2ISO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SCALL_OUT
PUP_WAIT_
SW2ISO Reserved
Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
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GPC_PGC_NOC_MIX_PUPSCR field descriptions
Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 After SCALL asserting to 1’b0, wait handshake signal SCALL_OUT to return to 1’b0 (This register control
PUP_WAIT_ only for MIX Type PGC)
SCALL_OUT
- This field is reserved.
Reserved
5.2.11.7 GPC PGC Down Sequence Control Register
(GPC_PGC_NOC_MIX_PDNSCR)
GPC PGC Down Sequence Control Register
Address: 303A_0000h base + A48h offset = 303A_0A48h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
GPC_PGC_NOC_MIX_PDNSCR field descriptions
Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b
NOTE: ISO2SW must not be programmed to zero.
7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation
NOTE: ISO must not be programmed to zero.
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5.2.11.8 GPC PGC Status Register (GPC_PGC_NOC_MIX_SR)
GPC PGC Status Register
Address: 303A_0000h base + A4Ch offset = 303A_0A4Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L2RSTDIS_
Reserved DEASSERT_
CNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L2RETN_FLAG
ALLOFF_FLAG
PSR
R
Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_NOC_MIX_SR field descriptions
Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
Table continues on the next page...
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GPC_PGC_NOC_MIX_SR field descriptions (continued)
Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.
NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from ALL_OFF mode.
1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag
NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from L2 retention mode.
1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.
0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.
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5.2.11.9 GPC PGC Control Register for PGC PUs (GPC_PGC_nCTRL)
GPC PGC Control Register for the PUs. See the PGC Memory Map for the assignments.
Address: 303A_0000h base + B00h offset + (64d × i), where i=0d to 19d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MEMPWR_TCD1_TDR_TRM Reserved L2RETN_TCD1_TDR
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved DFTRAM_TCD1 L2RSTDIS PCR
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
GPC_PGC_nCTRL field descriptions
Field Description
31–30 This field is reserved.
- Reserved
29–24
MEMPWR_ After scu pdn_req, count this value to assert A53 mempwr to 1’b1
TCD1_TDR_
TRM NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
23–22 This field is reserved.
- Reserved
21–16
L2RETN_TCD1_ After scu pdn_req, count this value to assert A53 l2retn to 1’b0
TDR
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
15–14 This field is reserved.
- Reserved
13–8
DFTRAM_TCD1 After scu pdn_req, count this value to assert A53 dftram to 1’b1
Table continues on the next page...
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GPC_PGC_nCTRL field descriptions (continued)
Field Description
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–1
L2RSTDIS After scu pdn_req, count this value to assert A53 l2rstdis to 1’b1, it will be clear automatically once any of
A53 core0/core1/core2/core3 is wakeup
NOTE: Can’t be programmed to zero (This register control only for SCU Type PGC)
0
PCR Power Control
NOTE: PCR must not change from power-down request (pdn_req) assertion until the target subsystem is
completely powered up.
0 Do not switch off power even if pdn_req is asserted.
1 Switch off power when pdn_req is asserted.
5.2.11.10 GPC PGC Up Sequence Control Register
(GPC_PGC_nPUPSCR)
GPC PGC Up Sequence Control Register
Address: 303A_0000h base + B04h offset + (64d × i), where i=0d to 19d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SW2ISO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
SW2ISO SW
Reset 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1
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GPC_PGC_nPUPSCR field descriptions
Field Description
31–23 This field is reserved.
- Reserved
22–7 After asserting switch_b, the PGC waits a number of clocks equal to the value of SW2ISO before negating
SW2ISO isolation.
6 This field is reserved.
- Reserved
SW
After a power-up request (pup_req assertion), the PGC waits a number of clocks equal to the value of SW
before asserting switch_b
NOTE: SW must not be programmed to zero.
5.2.11.11 GPC PGC Down Sequence Control Register
(GPC_PGC_nPDNSCR)
GPC PGC Down Sequence Control Register
Address: 303A_0000h base + B08h offset + (64d × i), where i=0d to 19d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reserved
Reset 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved ISO2SW Reserved ISO
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
GPC_PGC_nPDNSCR field descriptions
Field Description
31–14 This field is reserved.
- Reserved
13–8
ISO2SW After asserting isolation(by pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO2SW before negating switch_b
NOTE: ISO2SW must not be programmed to zero.
7–6 This field is reserved.
- Reserved
ISO
After a power-down request (pdn_req assertion), the PGC waits a number of clocks equal to the value of
ISO before asserting isolation
NOTE: ISO must not be programmed to zero.
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5.2.11.12 GPC PGC Status Register (GPC_PGC_nSR)
GPC PGC Status Register
Address: 303A_0000h base + B0Ch offset + (64d × i), where i=0d to 19d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L2RSTDIS_
Reserved DEASSERT_
CNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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General Power Controller (GPC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
L2RETN_FLAG
ALLOFF_FLAG
PSR
R
Reserved
L2RSTDIS_DEASSERT_CNT PUP_CLK_DIV_SEL
Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
GPC_PGC_nSR field descriptions
Field Description
31–18 This field is reserved.
- Reserved
17–8
L2RSTDIS_ Count this value to de-assert L2RSTDISABLE to LOW after CPU0 or CPU1 power up
DEASSERT_
CNT NOTE: This value can’t be programmed to zero (This register control only for SCU Type PGC)
7 This field is reserved.
- Reserved
6–3 Clock divider select for the clock of power up counter(count_clk is 32KHz for CPU/SCU type PGC,
PUP_CLK_DIV_ ipg_clk(66MHz) for MIX/PU Type PGC)
SEL
0000 1
0001 1/2 count_clk
0010 1/4 count_clk
0011 1/8 count_clk
0100 1/16 count_clk
0101 1/32 count_clk
0110 1/64 count_clk
0111 1/128 count_clk
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GPC_PGC_nSR field descriptions (continued)
Field Description
1000 1/256 count_clk
1001 1/512 count_clk
1010 1/1024 count_clk
1011 1/2056 count_clk
1100 1/4096 count_clk
1101 1/8192 count_clk
1110 1/16384 count_clk
1111 1/32768 count_clk
2
ALLOFF_FLAG All-off flag.
NOTE: Software should write “1” to clear this flag after A53 is wakeup from ALL_OFF mode, otherwise, it
will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from ALL_OFF mode.
1 A53 is wakeup from ALL_OFF mode.
1
L2RETN_FLAG L2 Retention Flag
NOTE: Software should write “1” to clear this flag after A53 is wakeup from L2 retention mode, otherwise
it will always keep to 1 (This register control only for SCU Type PGC)
0 A53 is not wakeup from L2 retention mode.
1 A53 is wakeup from L2 retention mode.
0 Power status. When in functional (or software-controlled debug) mode, PGC hardware sets PSR as soon
PSR as any of the power control output changes its state to one. Write one to clear this bit. Software should
clear this bit after power up; otherwise, PSR continues to reflect the power status of the initial power down.
0 The target subsystem was not powered down for the previous power-down request.
1 The target subsystem was powered down for the previous power-down request.
5.3 Crystal Oscillator (XTALOSC)
5.3.1 Overview
The chip has two XTAL modules, 24MHz XTAL module and 32KHz XTAL module.
The 24MHz XTAL module is instantiated from the XTAL IP, which includes:
• 24MHz crystal oscillator to generate reference clock
• Digital control logics for the XTAL
The 32KHz XTAL module uses a different IP and it is used as the clock source for the
RTC, located in the SNVS.
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Crystal Oscillator (XTALOSC)
5.3.1.1 Block Diagram
The figure below shows the OSC IP integration diagram:
OSC IP
+
–
Internal
Circuitry
XTALI XTALO
On chip
Rs
Rfb
CL1 CL2
Figure 5-17. OSC IP Integration Diagram
5.3.2 Functional Description
The 24MHz oscillator will be used as the primary clock source for the PLLs to generate
the clock for CPU, BUS, and high-speed interfaces. For all PLLs, the 24MHz clock from
the oscillator can be used as the PLL reference clock directly.
The OSC IP used by the 24MHz XTAL module has three modes, Internal clock
generation mode, External clock receive mode and Retention mode.
During internal clock generation mode, a suitable quartz crystal is connected between
PADI and PADO to generate the clock signal at the CK pin.
During external clock generation mode, the cell acts like a buffer, reflecting the PADI
signal at CK.
The RTO (retention enable) signal retains the previous state of all the core input control
signals. Logic at the RTO signal enables the retention operation.
Each XTAL module supports the following modes through register configuration:
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• Normal oscillator mode - In normal mode, the XTAL IP generates stable square
wave based on the crystal oscillator input.
• Bypass mode - In bypass mode, an external clock can be input through the XTAL
pad.
5.3.3 Memory Map and Register Definition
XTALOSC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
OSC Normal Clock Generation Control Register0
3027_0000 32 R/W 0000_0000h 5.3.3.1/726
(XTALOSC_SYS_OSCNML_CTL0)
OSC Normal Clock Generation Control Register1
3027_0004 32 R/W 0000_0000h 5.3.3.2/727
(XTALOSC_SYS_OSCNML_CTL1)
5.3.3.1 OSC Normal Clock Generation Control Register0
(XTALOSC_SYS_OSCNML_CTL0)
OSC Normal Clock Generation Control Register0
Address: 3027_0000h base + 0h offset = 3027_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved RTO SP SF1 SF0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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XTALOSC_SYS_OSCNML_CTL0 field descriptions
Field Description
31 Enable Oscillator
EN
30–5 This field is reserved.
- Reserved
4 Retention Enable
RTO
3 This field is reserved.
- Reserved
2 Select Power
SP
1 Select Frequency1
SF1
0 Select Frequency0
SF0
5.3.3.2 OSC Normal Clock Generation Control Register1
(XTALOSC_SYS_OSCNML_CTL1)
OSC Normal Clock Generation Control Register1
Address: 3027_0000h base + 4h offset = 3027_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLK_CKE_OVERRIDE
R
CLK_CKE
Reserved
Reserved
Reserved LOCK_COUNT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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XTALOSC_SYS_OSCNML_CTL1 field descriptions
Field Description
31–12 This field is reserved.
- Reserved
11–4 Lock Signal Gen Counter
LOCK_COUNT
3 This field is reserved.
- Reserved
2 Oscillator Clock Gating Enable
CLK_CKE
1 Oscillator Clock Gating Enable Override
CLK_CKE_
OVERRIDE
0 This field is reserved.
- Reserved
5.4 Thermal Monitoring Unit (TMU)
5.4.1 Overview
The Thermal Monitoring Unit (TMU) monitors and reports the temperature from one or
more remote temperature measurement sites located on chip.
5.4.1.1 Features
The temperature management unit features:
• Temperature measurement range -40-105°C.
• Monitoring
• Single-, or multi-site monitoring
• Out-of-range indication
• High/low temperature range monitoring
• Immediate and average temperature monitoring
• Average temperature monitoring programmable low-pass filtering
• Programmable monitoring thresholds for normal and critical
• Reporting
• Immediate and average temperature reporting
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5.4.2 Functional description
The TMU has access to two temperature measurement sites located on the chip. The main
probe is located inside of the ANAMIX, while the remote probe is located near the ARM
core. The TMU monitors these sites and can signal an alarm if a programmed threshold is
ever exceeded. The upper and lower temperature range is continuously captured. A set of
reporting registers allow for reading the current temperature at monitored sites.
5.4.3 Application Information
5.4.3.1 Re-enabling the TMU with different threshold setting
If the TMU was enabled with a specified threshold setting, the sequence to re-enable the
TMU with a different threshold setting is provided below.
In the following steps, the TMU is being re-enabled with a new High Temperature
Average threshold value:
1. Disable the TMU by setting TMU_TER[EN] = 0
2. Disable the threshold if it was set before, by setting TMU_TMHTATR[ENx] = 0
3. Set the new threshold value by programming TMU_TMHTATR[TEMPx]
4. Enable the TMU by setting TMU_TER[EN] = 1
5. A delay of at least 5us is needed here to reset the TMU internal states of the last run.
Otherwise, the old values might still be used, leading to unexpected results.
6. Enable the threshold by setting TMU_TMHTATR[ENx] = 1
The above sequence also applies for setting new High Temperature Immediate and High
Temperature Average Critical threshold values. Please program the appropriate register
(TMU_TMHTITR or TMU_TMHTACTR) in steps 2 and 3.
5.4.4 TMU Memory Map/Register Definition
TMU memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3026_0000 TMU Enable register (TMU_TER) 32 R/W 4000_0001h 5.4.4.1/731
3026_0004 TMU Probe Select register (TMU_TPS) 32 R/W C000_0000h 5.4.4.2/732
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TMU memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3026_0008 TMU Interrupt Enable register (TMU_TIER) 32 R/W 0000_0000h 5.4.4.3/733
3026_000C TMU Interrupt Detect register (TMU_TIDR) 32 R/W 0000_0000h 5.4.4.4/734
TMU Monitor High Temperature Immediate Threshold
3026_0010 32 R/W 0000_0000h 5.4.4.5/735
register (TMU_TMHTITR)
TMU Monitor High Temperature Average threshold register
3026_0014 32 R/W 0000_0000h 5.4.4.6/736
(TMU_TMHTATR)
TMU Monitor High Temperature Average Critical Threshold
3026_0018 32 R/W 0000_0000h 5.4.4.7/737
register (TMU_TMHTACTR)
3026_001C TMU Sensor Calibration register (TMU_TSCR) 32 R 0000_0000h 5.4.4.8/738
TMU Report Immediate Temperature Site register n
3026_0020 32 R 0000_0000h 5.4.4.9/739
(TMU_TRITSR)
TMU Report Average Temperature Site register n
3026_0024 32 R 0000_0000h 5.4.4.10/740
(TMU_TRATSR)
3026_0028 TMU AS Register (TMU_TASR) 32 R/W 0000_0000h 5.4.4.11/741
3026_002C TMU TMC Register (TMU_TTMC) 32 R/W 0000_0000h 5.4.4.12/742
3026_0030 TMU CALIV0 Register (TMU_TCALIV0) 32 R/W 0000_0000h 5.4.4.13/742
3026_0034 TMU CALIV1 Register (TMU_TCALIV1) 32 R/W 0000_0000h 5.4.4.14/743
3026_0038 TMU CALIV_M40 Register (TMU_TCALIV_M40) 32 R/W 0000_0000h 5.4.4.15/744
3026_003C TMU TRIM register (TMU_TRIM) 32 R/W 0000_0080h 5.4.4.16/745
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5.4.4.1 TMU Enable register (TMU_TER)
Address: 3026_0000h base + 0h offset = 3026_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
ADC_PD
EN
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
ALPF
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
TMU_TER field descriptions
Field Description
31 Enable the temperature sensor
EN
0 Disable
1 Enable
30 ADC power down controll bit
ADC_PD
This bit needs to be 0 to enable TMU
0 normal operating mode
1 power down mode
29–2 This field is reserved.
RESERVED
ALPF Average low pass filter setting.
The average temperature is calculated as: ALPF x Current_Temp + (1 - ALPF) x Average_Temp. If no
previous (average) temperature is valid, current temperature is used. For proper operation, this field
should only change when monitoring is disabled.
00 1.0
01 0.5
10 0.25
11 0.125
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5.4.4.2 TMU Probe Select register (TMU_TPS)
Address: 3026_0000h base + 4h offset = 3026_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
PROBE_SEL
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TPS field descriptions
Field Description
31–30 Probe selection bit
PROBE_SEL
This field should only change when TER.EN=1'b0.
00 select the main probe only
01 select the remote probe(near A53) only
1x select both 2 probes
RESERVED This field is reserved.
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5.4.4.3 TMU Interrupt Enable register (TMU_TIER)
Address: 3026_0000h base + 8h offset = 3026_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R RESERVED
ATCTEIE1
ATCTEIE0
ATTEIE1
ATTEIE0
ITTEIE1
ITTEIE0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TIER field descriptions
Field Description
31 Immediate temperature threshold exceeded interrupt enable of probe1.
ITTEIE1
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
30 Average temperature threshold exceeded interrupt enable of probe1.
ATTEIE1
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
29 Average temperature critical threshold exceeded interrupt enable of probe1.
ATCTEIE1
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
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TMU_TIER field descriptions (continued)
Field Description
28 This field is reserved.
RESERVED
27 Immediate temperature threshold exceeded interrupt enable of probe0.
ITTEIE0
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set.
26 Average temperature threshold exceeded interrupt enable of probe0.
ATTEIE0
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set.
25 Average temperature critical threshold exceeded interrupt enable of probe0.
ATCTEIE0
0 Disabled.
1 Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set.
RESERVED This field is reserved.
5.4.4.4 TMU Interrupt Detect register (TMU_TIDR)
Address: 3026_0000h base + Ch offset = 3026_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
ATCTE1
ATCTE0
ATTE1
ATTE0
ITTE1
ITTE0
R RESERVED
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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TMU_TIDR field descriptions
Field Description
31 Immediate temperature threshold exceeded of probe1.
ITTE1
0 No threshold exceeded.
1 Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-
of-range measured temperature above 125 degree C.
30 Average temperature threshold exceeded of probe1.
ATTE1
0 No threshold exceeded.
1 Average temperature threshold, as defined by TMHTATR, has been exceeded.
29 Average temperature critical threshold exceeded of probe1.
ATCTE1
0 No threshold exceeded.
1 Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
28 This field is reserved.
RESERVED
27 Immediate temperature threshold exceeded of probe0.
ITTE0
0 No threshold exceeded.
1 Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-
of-range measured temperature above 125 degree C.
26 Average temperature threshold exceeded of probe0.
ATTE0
0 No threshold exceeded.
1 Average temperature threshold, as defined by TMHTATR, has been exceeded.
25 Average temperature critical threshold exceeded of probe0.
ATCTE0
0 No threshold exceeded.
1 Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
RESERVED This field is reserved.
5.4.4.5 TMU Monitor High Temperature Immediate Threshold register
(TMU_TMHTITR)
Address: 3026_0000h base + 10h offset = 3026_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
EN1 EN0 TEMP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
TEMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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TMU_TMHTITR field descriptions
Field Description
31 Enable threshold for probe1.
EN1
0 Disabled.
1 Threshold enabled.
30 Enable threshold for probe0.
EN0
0 Disabled.
1 Threshold enabled.
29–24 This field is reserved.
RESERVED
23–16 High temperature immediate threshold value. Determines the current upper temperature threshold when
TEMP1 EN=1.
-40~125 degree C Sensor range.
bit23 is sign bit.
Other values are Reserved
15–8 This field is reserved.
RESERVED
TEMP0 High temperature immediate threshold value. Determines the current upper temperature threshold when
EN=1.
-40~125 degree C Sensor range.
bit7 is sign bit.
Other values are Reserved
5.4.4.6 TMU Monitor High Temperature Average threshold register
(TMU_TMHTATR)
Address: 3026_0000h base + 14h offset = 3026_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
EN1 EN0 TEMP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
TEMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TMHTATR field descriptions
Field Description
31 Enable threshold for probe1.
EN1
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TMU_TMHTATR field descriptions (continued)
Field Description
0 Disabled.
1 Threshold enabled.
30 Enable threshold for probe0.
EN0
0 Disabled.
1 Threshold enabled.
29–24 This field is reserved.
RESERVED
23–16 High temperature average threshold value. Determines the average upper temperature threshold when
TEMP1 EN=1.
-40-125 degree C Sensor range.
bit23 is sign bit.
Other values are Reserved
15–8 This field is reserved.
RESERVED
TEMP0 High temperature average threshold value. Determines the average upper temperature threshold when
EN=1.
-40-125 degree C Sensor range.
bit7 is sign bit.
Other values are Reserved
5.4.4.7 TMU Monitor High Temperature Average Critical Threshold
register (TMU_TMHTACTR)
Address: 3026_0000h base + 18h offset = 3026_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
EN1 EN0 TEMP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
TEMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TMHTACTR field descriptions
Field Description
31 Enable threshold for probe1.
EN1
0 Disabled.
1 Threshold enabled.
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TMU_TMHTACTR field descriptions (continued)
Field Description
30 Enable threshold for probe0.
EN0
0 Disabled.
1 Threshold enabled.
29–24 This field is reserved.
RESERVED
23–16 High temperature average critical threshold value for probe1. Determines the average upper critical
TEMP1 temperature threshold when EN=1.
-40-125 degree C Sensor range.
bit23 is sign bit.
other values reserved
15–8 This field is reserved.
RESERVED
TEMP0 High temperature average critical threshold value for probe0. Determines the average upper critical
temperature threshold when EN=1.
-40-125 degree C Sensor range.
bit7 is sign bit.
other values reserved
5.4.4.8 TMU Sensor Calibration register (TMU_TSCR)
Address: 3026_0000h base + 1Ch offset = 3026_001Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R V1 V0 RESERVED SNSR1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED SNSR0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TSCR field descriptions
Field Description
31 Measured temperature ready of probe1
V1
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [SNSR1] value after this bit is set.
30 Measured temperature ready of probe0
V0
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TMU_TSCR field descriptions (continued)
Field Description
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [SNSR0] value after this bit is set.
29–28 This field is reserved.
RESERVED
27–16 Raw sensor value of probe1
SNSR1
15–12 This field is reserved.
RESERVED
SNSR0 Raw sensor value of probe0
5.4.4.9 TMU Report Immediate Temperature Site register n
(TMU_TRITSR)
Address: 3026_0000h base + 20h offset = 3026_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R V1 V0 RESERVED TEMP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED TEMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TRITSR field descriptions
Field Description
31 Measured temperature ready of probe1
V1
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
30 Measured temperature ready of probe0
V0
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
29–24 This field is reserved.
RESERVED
23–16 Last calibratied temperature of probe1 reading at site when V=1.TRITSR[23] is sign bit, 1 means negative,
TEMP1 0 means positive.
15–8 This field is reserved.
RESERVED
TEMP0 Last calibratied temperature of probe0 reading at site when V=1.TRITSR[7] is sign bit, 1 means negative,
0 means positive.
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5.4.4.10 TMU Report Average Temperature Site register n
(TMU_TRATSR)
Address: 3026_0000h base + 24h offset = 3026_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R V1 V0 RESERVED TEMP1
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED TEMP0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TRATSR field descriptions
Field Description
31 Measured temperature ready of probe1
V1
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [TEMP1] value after this bit is set.
30 Measured temperature ready of probe0
V0
0 Not ready. First measurement still pending.
1 Ready. Extra 1us delay is needed to read the first [TEMP0] value after this bit is set.
29–24 This field is reserved.
RESERVED
23–16 Average temperature of probe1 reading at site when V=1. TRATSR[23] is sign bit, 1 means negative, 0
TEMP1 means positive.
15–8 This field is reserved.
RESERVED
TEMP0 Average temperature of probe0 reading at site when V=1. TRATSR[7] is sign bit, 1 means nagetive, 0
means positive.
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5.4.4.11 TMU AS Register (TMU_TASR)
Address: 3026_0000h base + 28h offset = 3026_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
BUF_SLOP_SEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED BUF_VERF_
W SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TASR field descriptions
Field Description
31–20 This field is reserved.
RESERVED
19–16 Amplifier gain setting bits.
BUF_SLOP_SEL
4'b0000 6.34 mV
4'b0001 6.485 mV
4'b0010 6.63 mV
4'b0011 6.775 mV
4'b0100 6.92 mV
4'b0101 7.065 mV
4'b0110 7.21 mV
4'b0111 7.355 mV
4'b1000 7.5 mV
4'b1001 7.645 mV
4'b1010 7.79 mV
4'b1011 7.935 mV
4'b1100 8.08 mV
4'b1101 8.225 mV
4'b1110 8.37 mV
4'b1111 8.515 mV
15–2 This field is reserved.
RESERVED
BUF_VERF_SEL Reference voltage setting bits for the amplifier in the Positive-TC generator block.
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5.4.4.12 TMU TMC Register (TMU_TTMC)
Address: 3026_0000h base + 2Ch offset = 3026_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
TMUX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TTMC field descriptions
Field Description
31–3 This field is reserved.
RESERVED
TMUX Test-mux address setting bits. Only used for debugging purpose.
3'b000 ADC Function Test
3'b001 PTAT Voltage Monitoring
3'b010 Reference-top Voltage Monitoring
3'b011 Reference Voltage (for Amp.) Monitoring
3'b100 N/A
3'b101 VBE Voltage Monitoring
3'b110 N/A (Default)
3'b111 N/A
5.4.4.13 TMU CALIV0 Register (TMU_TCALIV0)
Address: 3026_0000h base + 30h offset = 3026_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
EN SNSR105C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
SNSR25C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TCALIV0 field descriptions
Field Description
31 Enable 105C calibration value used in 1p calibration. If enable, 105C sensor value take the priority. Used
EN for probe0
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TMU_TCALIV0 field descriptions (continued)
Field Description
0 Disable.
1 Enable.
30–28 This field is reserved.
RESERVED
27–16 105C sensor value of probe0 read from FUSE, system should program it before enable TMU if enable 1P
SNSR105C calibration.
15–12 This field is reserved.
RESERVED
SNSR25C 25C sensor value of probe0 read from FUSE(default 1p value), system should program it before enable
TMU if enable 1P calibration.
5.4.4.14 TMU CALIV1 Register (TMU_TCALIV1)
Address: 3026_0000h base + 34h offset = 3026_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED
EN SNSR105C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED
SNSR25C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TCALIV1 field descriptions
Field Description
31 Enable 105C calibration value used in 1p calibration. If enable, 105C sensor value take the priority. Used
EN for probe1
0 Disable.
1 Enable.
30–28 This field is reserved.
RESERVED
27–16 105C sensor value of probe1 read from FUSE, system should program it before enable TMU if enable 1P
SNSR105C calibration.
15–12 This field is reserved.
RESERVED
SNSR25C 25C sensor value of probe1 read from FUSE(default 1p value), system should program it before enable
TMU if enable 1P calibration.
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5.4.4.15 TMU CALIV_M40 Register (TMU_TCALIV_M40)
Address: 3026_0000h base + 38h offset = 3026_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R RESERVED RESERVED
SNSR_M40C_1 SNSR_M40C_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TMU_TCALIV_M40 field descriptions
Field Description
31–28 This field is reserved.
RESERVED
27–16 m40C sensor value of probe1 read from FUSE, used for software 3p calibration if needed
SNSR_M40C_1
15–12 This field is reserved.
RESERVED
SNSR_M40C_0 m40C sensor value of probe0 read from FUSE, used for software 3p calibration if needed
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5.4.4.16 TMU TRIM register (TMU_TRIM)
Address: 3026_0000h base + 3Ch offset = 3026_003Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RESERVED RESERVED
BGR BJT_CUR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VREFT_FLAG
VBE_FLAG
R RESERVED RESERVED
EN_VREFT_TRIM
EN_VBE_TRIM
EN_CH
VLSB
Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
TMU_TRIM field descriptions
Field Description
31–28 Curvature trimming bits for voltage change in BGR
BGR
27–24 This field is reserved.
RESERVED
23–20 Current trimming ports for BJT
BJT_CUR
19–16 This field is reserved.
RESERVED
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TMU_TRIM field descriptions (continued)
Field Description
15–12 LSB voltage of DAC trimming
VLSB
11–8 This field is reserved.
RESERVED
7 Offset calibration enable
EN_CH
6 Verf calibration enable
EN_VREFT_
TRIM
5 Vbe calibration enable
EN_VBE_TRIM
4–2 This field is reserved.
RESERVED
1 Flag of the Vbe trim
VBE_FLAG
0 Flag of the Vref trim
VREFT_FLAG
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Chapter 6
SNVS, Reset, Fuse, and Boot
6.1 System Boot
6.1.1 Overview
The boot process begins at the Power-On Reset (POR) where the hardware reset logic
forces the Arm core to begin the execution starting from the on-chip boot ROM.
The boot ROM code uses the state of the internal register BOOT_MODE[3:0] as well as
the state of various eFUSEs settings to determine the boot flow behavior of the device.
The main features of the ROM include:
• Support for booting from various boot devices
• Serial downloader support (USB)
• High Assurance Boot
The boot ROM supports these boot devices:
• Serial NOR Flash via FlexSPI
• Serial NAND Flash via FlexSPI
• NAND flash
• SD/eMMC
• Serial (SPI) NOR
The boot ROM code also allows to download the programs to be run on the device. The
example is a provisioning program that can make further use of the serial connection to
provide a boot device with a new image. Typically, the provisioning program is
downloaded to the internal RAM and allows to program the boot devices, such as the
SD/MMC flash. The ROM serial downloader uses a high-speed USB in a non-stream
mode connection.
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A key feature of the boot ROM is the ability to perform a secure boot, also known as a
High-Assurance Boot (HAB). This is supported by the HAB security library which is a
subcomponent of the ROM code. The HAB uses a combination of hardware and software
together with the Public Key Infrastructure (PKI) protocol to protect the system from
executing unauthorized programs. Before the HAB allows the user image to execute, the
image must be signed. The signing process is done during the image build process by the
private key holder and the signatures are then included as a part of the final program
image. If configured to do so, the ROM verifies the signatures using the public keys
included in the program image. A secure boot with HAB can be performed on all boot
devices supported on the chip in addition to the serial downloader. The HAB library in
the boot ROM also provides the API functions, allowing the additional boot chain
components (bootloaders) to extend the secure boot chain. The out-of-fab setting for the
SEC_CONFIG is the open configuration, in which the ROM/HAB performs the image
authentication, but all authentication errors are ignored and the image is still allowed to
execute.
6.1.2 Boot modes
During boot, the core's behavior is defined by the boot mode pin settings, as described in
Boot mode pin settings.
6.1.2.1 Boot mode pin settings
The device supports 16 boot modes but only several are supported on the chip and the
others are reserved for future use. The boot mode is selected based on the binary value
stored in the internal BOOT_MODE[3:0] register.
The BOOT_MODE[3:0] is initialized by sampling the BOOT_MODE[3:0] inputs on the
rising edge of the POR_B. After these inputs are sampled, their subsequent state does not
affect the contents of the BOOT_MODE[3:0] internal register. The state of the internal
BOOT_MODE[3:0] register may be read from the IPP_BOOT_MODE[3:0] field of the
SRC Boot Mode Register (SRC_SBMR2). The available boot modes are: Boot From
Fuses, serial boot via USB, and Internal Boot. See this table for settings:
Table 6-1. Boot MODE pin settings
Boot Device Select BOOT_MODE [3] BOOT_MODE [2] BOOT_MODE [1] BOOT_MODE [0]
Boot from internal fuses 0 0 0 0
USB Serial Download 0 0 0 1
USDHC3 (eMMC) 0 0 1 0
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Table 6-1. Boot MODE pin settings (continued)
Boot Device Select BOOT_MODE [3] BOOT_MODE [2] BOOT_MODE [1] BOOT_MODE [0]
USDHC2 (SD) 0 0 1 1
NAND 8-bit single device, 0 1 0 0
256 pages
NAND 8-bit single device, 0 1 0 1
512 pages
FlexSPI 3B Read 0 1 1 0
FlexSPI Hyperflash 3.3V 0 1 1 1
eCSPI Boot 1 0 0 0
Reserved 1 0 0 1
FLEXSPI Serial NAND - 1 0 1 0
2k page
FLEXSPI Serial NAND - 1 0 1 1
4k page
6.1.2.2 High-level boot sequence
The figure found here show the high-level boot ROM code flow.
Figure 6-1. Boot flow
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6.1.2.3 Boot From Fuses mode (BOOT_MODE[3:0] = 0000b)
A value of 0000b in the BOOT_MODE[3:0] register selects the Boot From Fuses mode.
This mode is similar to the Internal Boot mode described in Internal Boot mode with one
difference. In this mode, the ROM code retrieves boot mode settings from the boot mode
fuses.The boot ROM code uses the boot eFUSE settings only. This mode also supports a
secure boot using HAB.
If set to Boot From Fuses or FORCE_BT_FROM_FUSE=1, the boot flow is controlled
by the BT_FUSE_SEL eFUSE value. If BT_FUSE_SEL = 0, indicating that the boot
device (for example, flash, SD/MMC) was not programmed yet, the boot flow jumps
directly to the Serial Downloader. If BT_FUSE_SEL = 1, the normal boot flow is
followed, where the ROM attempts to boot from the selected boot device.
The first time a board is used, the default eFUSEs may be configured incorrectly for the
hardware on the platform. In such case, the Boot ROM code may try to boot from a
device that does not exist. This may cause an electrical/logic violation on some pads.
Using the Boot From Fuses mode addresses this problem.
Setting the BT_FUSE_SEL=0 forces the ROM code to jump directly to the Serial
Downloader. This allows a bootloader to be downloaded which can then provision the
boot device with a program image and blow the BT_FUSE_SEL and the other boot
configuration eFUSEs. After the reset, the boot ROM code determines that the
BT_FUSE_SEL is blown (BT_FUSE_SEL = 1) and the ROM code performs an internal
boot according to the new eFUSE settings. This allows the user to set
BOOT_MODE[3:0]=0000b on a production device and burn the fuses on the same
device (by forcing the entry to the Serial Downloader), without changing the value of the
BOOT_MODE[3:0] or the pullups/pulldowns on the BOOT_MODE[3:0] pins.
6.1.2.4 Internal Boot mode
Any of the values from Table 6-8 in the BOOT_MODE[3:0] register selects the Internal
Boot mode. In this mode, the processor continues to execute the boot code from the
internal boot ROM.
The boot code performs the hardware initialization, loads the program image from the
chosen boot device, performs the image validation using the HAB library (see Boot
security settings), and then jumps to an address derived from the program image. If an
error occurs during the internal boot, the boot code jumps to the Serial Downloader (see
Serial Downloader).
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When set to the Internal Boot, the boot flow may be controlled by a combination of
eFUSE settings and Boot Mode pins. The fuse (BT_FUSE_SEL) will not impact the
behavior of ROM in Internal Boot Mode.
6.1.2.5 Boot security settings
The internal boot modes use one of three security configurations.
• Closed: This level is intended for use with shipping-secure products. All HAB
functions are executed and the security hardware is initialized (the Security
Controller or SNVS enters the Secure state), the DCD is processed if present, and the
program image is authenticated by the HAB before its execution. All detected errors
are logged, and the boot flow is aborted with the control being passed to the serial
downloader. At this level, the execution does not leave the internal ROM unless the
target executable image is authenticated.
• Open: This level is intended for use in non-secure products or during the
development phases of a secure product. All HAB functions are executed as for a
closed device. The security hardware is initialized (except for the SNVS which is left
in the Non-Secure state), the DCD is processed if present, and the program image is
authenticated by the HAB before its execution. All detected errors are logged, but
have no influence on the boot flow which continues as if the errors did not occur.
This configuration is useful for a secure product development because the program
image runs even if the authentication data is missing or incorrect, and the error log
can be examined to determine the cause of the authentication failure.
• Field Return: This level is intended for the parts returned from the shipped products.
NOTE
Refer to the chip's Security Reference Manual for more details
on security configuration.
6.1.3 Device configuration
This section describes the external inputs that control the behavior of the Boot ROM
code.
This includes the boot device selection ( SD, MMC, and so on), boot device
configuration (SD bus width, speed, and so on), and other. In general, the source for this
configuration should come from the eFUSEs embedded inside the chip. However, certain
configuration parameters can be sourced from the BOOT_MODE[3:0] pins (with Internal
Boot mode), allowing further flexibility during the development process.
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6.1.3.1 Boot eFUSE descriptions
This table is a comprehensive list of the configuration parameters that the ROM uses.
Table 6-2. Boot eFUSE descriptions
Fuse Address Configuration Definition Shipped value Settings1
BT_FUSE_SEL OEM In the Boot From Fuse 0 If Boot From Fuse
mode mode
0x470[28]
(BOOT_MODE[3:0] = (BOOT_MODE[3:0] =
0000b), the 0000b) or
BT_FUSE_SEL fuse FORCE_BT_FROM_F
indicates whether the USE=1 :
bit configuration eFuses
0—The BOOT
are programmed.
configuration eFuses
are not programmed
yet. The boot flow
jumps to the serial
downloader.
1—The BOOT
configuration eFuses
are programmed. The
regular boot flow is
performed.
SDP_DISABLE OEM Serial download disable 0 0 - Enable
bit
0x480[21] 1 - Disable
L1 I-Cache DISABLE OEM L1 I Cache disable bit 0 0—L1 I Cache is
used by the boot during enabled by the ROM
0x480[12]
the entire execution. during the boot.
1—L1 I Cache is
disabled by the ROM
during the boot.
BT_FREQ OEM Boot frequency 0 0—Arm—1000 MHz
selection
0x480[9] 1—Arm—500 MHz
LPB_BOOT OEM USB Low-Power Boot 00 0x—LPB Disable
0x480[15:14] 10—Divide by 2
11—Divide by 4
BT_LPB_POLARITY OEM USB Low-Power Boot 0 0—Low on the GPIO
GPIO polarity pad indicates the
0x480[13]
lowpower condition.
1—High on the GPIO
pad indicates the low-
power condition.
WDOG_ENABLE OEM Watchdog reset counter 0 0—The watchdog reset
enable counter is disabled
0x480[10]
during the serial
downloader.
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Table 6-2. Boot eFUSE descriptions (continued)
1—The watchdog reset
counter is enabled
during the serial
downloader.
MMC_DLL_DLY[6:0] OEM uSDHC Delay Line 0000000 uSDHC Delay Line
settings settings
0x490[14:8]
USDHC_PAD_SETTIN OEM Override values for the 00000000 Override the following
GS SD/MMC and NAND IO PAD settings:
boot modes
0x490[31:24] [1:0] Driver Strength
NAND_PAD_SETTIN [2] Slew Rate
GS
[3] Hysteresis
0x4A0[31:24]
[4] Pull/Keeper select
[6:5] Pull up/down
config
[7] Reserved.
1. 0 = intact fuse and 1= blown fuse
6.1.4 Device initialization
This section describes the details of the ROM and provides the initialization details.
This includes details on:
• The ROM memory map
• The RAM memory map
• On-chip blocks that the ROM must use or change the POR register default values
• Clock initialization
• Enabling the MMU/L2 cache
• Exception handling and interrupt handling
6.1.4.1 Internal ROM/RAM memory map
These figures show the iROM memory map:
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0x0003FFFF 0x0097FFFF
ROM BOOTSTRAP CODE
0x00000A00
ROM API TABLE
0x00000980
OCRAM FREE AREA
HAB API TABLE
0x00000900
ROM VERSION AND
COPYRIGHT INFORMATION
0x00000800 0x00918000
ROM BOOTSTRAP CODE
0x00000400
RESERVED FOR ROM
VECTORS
0x00000000 0x00900000
ROM Memory Map OCRAM Memory Map
Figure 6-2. Internal ROM and RAM memory map
NOTE
If no ROM/HAB APIs are being used, the entire OCRAM
region can be used freely after the boot.
6.1.4.2 Boot block activation
The boot ROM affects a number of different hardware blocks which are activated and
play a vital role in the boot flow.
The ROM configures and uses the following blocks (listed in an alphabetical order)
during the boot process. Note that the blocks actually used depend on the boot mode and
the boot device selection:
• APBH—the DMA engine to drive the GPMI module
• BCH—62-bit error correction hardware engine with the AXI bus master and a
private connection to the GPMI
• CCM—Clock Control Module
• ECSPI—Enhanced Configurable Serial Peripheral Interface
• FlexSPI—Flexible SPI Interface which supports serial NOR devices
• GPMI—NAND controller pin interface
• OCOTP_CTRL—On-Chip OTP Controller; the OCOTP contains the eFUSEs
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• IOMUXC—I/O Multiplexer Control which allows the GPIO use to override the
eFUSE boot settings;
• IOMUXC GPR—I/O Multiplexer Control General-Purpose Registers
• CAAM—Cryptographic Acceleration and Assurance Module
• SNVS—Secure Non-Volatile Storage
• SRC—System Reset Controller
• USB—used for the serial download of a boot device provisioning program
• USDHC—Ultra-Secure Digital Host Controller
• WDOG-1—Watchdog timer
6.1.4.3 Clocks at boot time
The following table shows the PLLs and clock source settings in ROM code.
Table 6-3. PLL setting by ROM
PLL name Frequency Comment
ARM_PLL 1000 MHz -
SYS_PLL1 800 MHz -
SYS_PLL2 1000 MHz -
NOTE
All other PLLs are in the default status.
NOTE
Refer to Low-power boot for low-power boot frequencies.
Table 6-4. Clock root setting by ROM
Clock Name Frequency (MHz) Source Enable
ARM_A53_ROOT 1000 ARM_PLL_CLK Yes
ARM_M7_CLK_ROOT 200 SYSTEM_PLL2_200M_CLK No
AHB_CLK_ROOT 133 SYSTEM_PLL1_133M_CLK Yes
MAIN_AXI_CLK_ROOT 400 SYSTEM_PLL1_800M_CLK Yes
NAND_CLK_ROOT 500 SYSTEM_PLL2_500M_CLK Enabled by driver
NAND_USDHC_BUS_CLK_R 266 SYSTEM_PLL1_266M_CLK Enabled by driver
OOT
USB_BUS_CLK_ROOT SYSTEM_PLL2_500M_CLK Enabled by driver
NOC_CLK_ROOT 400 SYSTEM_PLL1_800M_CLK Yes
USDHC1_CLK_ROOT 200 SYSTEM_PLL1_400M_CLK Enabled by driver
USDHC2_CLK_ROOT 200 SYSTEM_PLL1_400M_CLK Enabled by driver
USDHC3_CLK_ROOT 200 SYSTEM_PLL1_400M_CLK Enabled by driver
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Table 6-4. Clock root setting by ROM (continued)
Clock Name Frequency (MHz) Source Enable
USB_PHY_REF_CLK_ROOT SYSTEM_PLL1_100M_CLK Enabled by driver
ECSPI1_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
ECSPI2_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
ECSPI3_CLK_ROOT 50 SYSTEM_PLL2_200M_CLK No
WRCLK_CLK_ROOT SYSTEM_PLL1_40M_CLK No
NOTE
All other clock roots are in the default status.
Table 6-5. NAND_CLK_ROOT setting
NAND data rate NAND_CLK_ROOT source Frequency
Async/Legacy NAND SYSTEM_PLL1_400M_CLK 25 MHz
Sync 40M SYSTEM_PLL1_400M_CLK 40 MHz
Toggle/Sync 66M SYSTEM_PLL1_400M_CLK 66 MHz
Toggle 80M SYSTEM_PLL1_400M_CLK 80 MHz
Sync 100M SYSTEM_PLL1_400M_CLK 100 MHz
Toggle/Sync 133M SYSTEM_PLL1_400M_CLK 133 MHz
Sync 160M SYSTEM_PLL1_400M_CLK 133 MHz
Toggle/Sync 200M SYSTEM_PLL1_400M_CLK 200 MHz
NOTE
The NAND_CLK_ROOT source depends on the NAND data
rate.
The ROM code disables the clocks listed in the following table, except for the boot
devices listed in the "Enabled for boot device" column below.
Table 6-6. CCGR setting by ROM
Gating Register LPCG Enable Enabled for boot device
CCM_CCGR0 DVFS
CCM_CCGR1 Anamix Yes
CCM_CCGR2 CPU Yes
CCM_CCGR3 CSU Yes
CCM_CCGR4 Debug Yes
CCM_CCGR5 DRAM1
CCM_CCGR6 Reserved Yes
CCM_CCGR7 ECSPI1 Yes
CCM_CCGR8 ECSPI2 Yes
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Table 6-6. CCGR setting by ROM (continued)
Gating Register LPCG Enable Enabled for boot device
CCM_CCGR9 ECSPI3 Yes
CCM_CCGR10 ENET1 Yes
CCM_CCGR11 GPIO1 Yes
CCM_CCGR12 GPIO2 Yes
CCM_CCGR13 GPIO3 Yes
CCM_CCGR14 GPIO4 Yes
CCM_CCGR15 GPIO5 Yes
CCM_CCGR16 GPT1 Yes
CCM_CCGR17 GPT2 Yes
CCM_CCGR18 GPT3
CCM_CCGR19 GPT4
CCM_CCGR20 GPT5
CCM_CCGR21 GPT6
CCM_CCGR22 HS
CCM_CCGR23 I2C1
CCM_CCGR24 I2C2
CCM_CCGR25 I2C3
CCM_CCGR26 I2C4
CCM_CCGR27 IOMUX Yes
CCM_CCGR28 IPMUX1 Yes
CCM_CCGR29 IPMUX2 Yes
CCM_CCGR30 IPMUX3 Yes
CCM_CCGR31 Reserved Yes
CCM_CCGR32 Reserved Yes
CCM_CCGR33 MU
CCM_CCGR34 OCOTP Yes
CCM_CCGR35 OCRAM Yes
CCM_CCGR36 OCRAM_s Yes
CCM_CCGR37 PCIE
CCM_CCGR38 PERFMON1
CCM_CCGR39 PERFMON2
CCM_CCGR40 PWM1
CCM_CCGR41 PWM2
CCM_CCGR42 PWM3
CCM_CCGR43 PWM4
CCM_CCGR44 QoS Yes
CCM_CCGR45 Reserved Yes
CCM_CCGR46 QoS_ENET Yes
CCM_CCGR47 FLEXSPI Yes
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Table 6-6. CCGR setting by ROM (continued)
Gating Register LPCG Enable Enabled for boot device
CCM_CCGR48 RAWNAND Yes
CCM_CCGR49 RDC
CCM_CCGR50 ROM Yes
CCM_CCGR51 I2C5
CCM_CCGR52 I2C6
CCM_CCGR53 CAN1 Yes
CCM_CCGR54 CAN2 Yes
CCM_CCGR55 Reserved Yes
CCM_CCGR56 Reserved Yes
CCM_CCGR57 SCTR
CCM_CCGR58 SDMA1
CCM_CCGR59 ENET_QoS
CCM_CCGR60 SEC_DEBUG
CCM_CCGR61 SEMA1
CCM_CCGR62 SEMA2
CCM_CCGR63 IRQ_STEER Yes
CCM_CCGR64 SIM_ENET Yes
CCM_CCGR65 SIM_m Yes
CCM_CCGR66 SIM_main Yes
CCM_CCGR67 SIM_s Yes
CCM_CCGR68 SIM_wakeup Yes
CCM_CCGR69 GPU2D Yes
CCM_CCGR70 GPU3D Yes
CCM_CCGR71 SNVS Yes
CCM_CCGR72 TRACE Yes
CCM_CCGR73 UART1
CCM_CCGR74 UART2
CCM_CCGR75 UART3
CCM_CCGR76 UART4
CCM_CCGR77 USB Yes
CCM_CCGR78 Reserved Yes
CCM_CCGR79 USB_PHY
CCM_CCGR80 Reserved Yes
CCM_CCGR81 USDHC1
CCM_CCGR82 USDHC2
CCM_CCGR83 WDOG1 Yes
CCM_CCGR84 WDOG2
CCM_CCGR85 WDOG3
CCM_CCGR86 VPU_G1
Table continues on the next page...
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Table 6-6. CCGR setting by ROM (continued)
Gating Register LPCG Enable Enabled for boot device
CCM_CCGR87 GPU
CCM_CCGR88 NOC_WRAPPER Yes
CCM_CCGR89 VPU_ENCODER
CCM_CCGR90 VPU_G2
CCM_CCGR91 NPU Yes
CCM_CCGR92 HSIO Yes
CCM_CCGR93 MEDIA Yes
CCM_CCGR94 USDHC3 Yes
CCM_CCGR95 HDMI Yes
CCM_CCGR96 XTAL Yes
CCM_CCGR97 PLL Yes
CCM_CCGR98 TSENSOR Yes
CCM_CCGR99 VPU
CCM_CCGR100 MRPR Yes
CCM_CCGR101 AUDIO Yes
CCM_CCGR102 Reserved Yes
6.1.4.4 Enabling MMU and caches
The boot ROM includes a feature that enables the Memory Management Unit (MMU)
and the caches to improve the boot speed.
The L1 instruction cache is enabled at the very beginning, unless the
ICACHE_DISABLE fuse is blown. The MMU is always enabled and ROM enables it at
the very beginning, after enabling the L1 ICACHE. The L1 data cache is enabled during
image authentication and will be disabled after the image authentication is completed.
The fuse, DCACHE_DIS, is used to control L1 DCACHE enable/disable. By default
(fuse not programmed), ROM enables the L1 DCACHE.
6.1.4.5 Exception handling
The exception vectors located at the start of the ROM are used to map all the Arm
exceptions (except the reset exception) to a duplicate exception vector table in the
internal RAM.
During the boot phase of CPU0, the RAM vectors point to the serial downloader in the
ROM.
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After the boot, the program image can overwrite the vectors as required. The code shown
below is used to map the ROM exception vector table to the duplicate exception vector
table in the RAM.
When an exception occurs, ROM does not move into USB serial download mode.
Instead, ROM will set a flag (EXCEPTION_OCCURED) in the SRC GPR, and then reset
the chip.
Mapping ROM Exception Vector Table
rom_vectors
B startup ; offset is 0x000
ALIGN 0x80
B default_exception_handler ; offset is 0x080
ALIGN 0x80
B default_exception_handler ; offset is 0x100
ALIGN 0x80
B default_exception_handler ; offset is 0x180
ALIGN 0x80
B sync_exception_handler ; offset is 0x200
ALIGN 0x80
B default_exception_handler ; offset is 0x280
ALIGN 0x80
B default_exception_handler ; offset is 0x300
ALIGN 0x80
B default_exception_handler ; offset is 0x380
6.1.4.6 Interrupt handling during boot
No special interrupt-handling routines are required during the boot process. The
interrupts are disabled during the boot ROM execution and may be enabled in a later boot
stage.
6.1.4.7 Persistent bits
Some modes of the boot ROM require the registers that keep their values after a warm
reset. The SRC General-Purpose registers are used for this purpose.
See this table for persistent bits list and description:
Table 6-7. Persistent bits
Bit name Bit location Description
- SRC_GPR2[31:0] Holds the FlexSPI NOR auto probe persistent
content.
PERSIST_EXCEPTION_OCCURED SRC_GPR10[17] Exception cause reset
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6.1.5 Boot devices (internal boot)
The chip supports these boot flash devices:
• Serial NOR flash via FlexSPI interface
• Serial NAND flash via FlexSPI, with options for 2k page and 4k page
• Raw NAND (MLC and SLC), and Toggle-mode NAND flash through GPMI-2
interface, located at CS0. Page sizes of 2 KB, 4 KB, and 8 KB. The bus widths of 8-
bit with 2 through 62-bit BCH hardware ECC (Error Correction) are supported.
• SD/MMC/eSD/SDXC/eMMC via USDHC interface, supporting high capacity cards.
The selection of the external boot device type is controlled by BOOT_MODE[3:0]. See
the table below for more details:
Table 6-8. Boot device selection
BOOT_MODE[3:0] Boot device
0010 eMMC boot - by default, boots from USDHC3 port. Can be
overridden by fuses settings.
0011 SD boot - by default, boots from USDHC2 port. Can be
overridden by fuses settings.
0100 NAND 8-bit single device - 256 pages in block
0101 NAND 8-bit single device - 512 pages in block
0110 FlexSPI - 3B Read
0111 FlexSPI - Hyperflash 3.3V
1000 eCSPI Boot
1001 Reserved
1010 FLEXSPI Serial NAND - 2k page
1011 FLEXSPI Serial NAND - 4k page
6.1.5.1 Serial NAND Flash Boot over FlexSPI
The boot ROM supports a number of Serial NAND Flash devices from different vendors.
The Embedded Error Correction and Control (ECC) module in SPI NAND devices are
used to detect and correct the errors.
6.1.5.1.1 NAND Flash Boot Flow and Boot Control Blocks (BCB)
There are two BCB data structures:
• FCB
• DBBT
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As part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for a Firmware Configuration Block (FCB) that contains the optimum NAND
timings, page address of Discovered Bad Block Table (DBBT) Search Area and start
page address of primary and secondary firmware.
The hardware ECC level to use is embedded inside FCB block. The FCB data structure is
also protected using ECC. Driver reads raw 2112 bytes of first sector and runs through
software ECC engine that determines whether FCB data is valid or not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments page
number to Search Stride number of pages to read for the next BCB until SearchCount
pages have been read.
If search fails to find a valid FCB, the NAND driver responds with an error and the boot
ROM enters into serial download mode.
The FCB contains the page address of DBBT Search Area, and the page address for
primary and secondary boot images. DBBT is searched in DBBT Search Area just like
how FCB is searched. After the FCB is read, the DBBT is loaded, and the primary or
secondary boot image is loaded using starting page address from FCB.
Figure 6-3 shows the state diagram of FCB search.
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START
Current Page = 0,
Search Stride = Stride Size Fuse Value,
Search Count = Boot Search Count Fuse Value
Read 4K, ReadCount++
Current Page += Search
Stride
YES
Read Count <
Is Valid FCB? NO
Search Count
YES NO
Recovery Device/
NCB Found
Serial Loader
Figure 6-3. FCB Search Flow
Once FCB is found, the boot ROM searches for the Discovered Bad Blocks Table
(DBBT). If DBBT Search Area is 0 in FCB, then ROM assumes that there are no bad
blocks on NAND device boot area. See Figure 6-4 for the DBBT search flow.
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START
Current Page = DBBT Start Page,
Search Stride = Stride Size Fuse Value,
Search Count = 4
Read 4K, ReadCount++
Current Page += Search
Stride
YES
Read Count <
Is Valid DBBT? NO
Search Count
YES
NO
DBBT Found, Copy to IRAM
DBBT Not Found
DBBT Found
Figure 6-4. DBBT Search Flow
6.1.5.1.2 Firmware Configuration Block
The FCB is at the first page in the first good block. The FCB should be present at each
search stride of the search area.
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The search area contains copies of the FCB at each stride distance, in case the first Serial
NAND block becomes corrupted, the ROM will find its copy in the next Serial NAND
block. The search area should span over at least two Serial NAND blocks. The location
information for DBBT search area and images are all specified in the FCB. Table 25-9
show the Flash Control Block Structure.
Table 6-9. Flash Control Block Structure
Name Offset Size Bytes Description
crcChecksum 0x000 4 Checksum
fingerprint 0x004 4 0x4E46_4342
ASCII: “NFCB”
version 0x008 4 0x0000_0001
DBBTSearchStartPage 0x00C 4 Start Page address for bad
block table search area
searchStride 0x010 2 Search stride for DBBT and
FCB search. Not used by
ROM Max value is 8.
searchCount 0x012 2 Copies of DBBT and FCB.
Not used by ROM, max value
is 8.
firmwareCopies 0x014 4 Firmware copies
Valid range 1-8.
Reserved 0x018 40 Reserved for future use
Must be set to 0.
firmwareInfoTable 0x40 64 This table consists of (up to 8
entries):
Field Size Descrip
tion
StartPag 4 Start
e page of
this
firmware
pageCo 4 Pages in
unt this
firmware
Reserved 0x080 128 Reserved
Must be set to 0
spiNandConfigBlock 0x100 512 Serial NAND configuration
block over FlexSPI
Reserved 0x300 256 Must be set to 0
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NOTE
1. The “crcChecksum” is calculated with an MPEG2 variant
of CRC-32. See Table 6-10 for more details.
2. The “crcChecksum” calculation starts from fingerprint to
the end of FCB, 1020 bytes in total.
3. the “spiNandConfigBlock” is FlexSPI NAND
configuration block which consists of common FlexSPI
memory configuration block and Serial NAND specified
configuration parameters. See Serial Flash boot through
SPI for more details.
Table 6-10. CRC-32 variant algorithm
Property Description
Width 32 bits
Polynomial 0x04C11BD7
Init Value 0xFFFFFFFF
Reflect in False
Reflect Out False
XOR Out 0x00000000
6.1.5.1.3 Discovered Bad Blocks Table (DBBT)
Table 6-11. DBBT Structure
Name Offset Size in Bytes Decription
crcChecksum 0x000 4 Checksum
Fingerprint 0x004 4 32-bit word with a value of
0x4442_4254, in asci “DBBT”
Version 0x008 4 32-bit version number, this
version of DBBT is
0x00000001
- 0x00C 4 Reserved
badBlockNumber 0x010 4 Number of bad blocks
Reserved 0x014 12 Must be filled with 0x00s
Bad Block entries 0x020-0x41F 256 Bad Block entries, only the
first “badBlockNumber”
entries are valid, the
remaining entries must be
filled with 0x00s
NOTE
1. Maximum bad block number is 256.
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2. crcChecksum is calculated with the same algorithm as the
one in FCB, from Fingerprint to the end of DBBT, 1052
bytes in total.
6.1.5.1.4 Bad block handling in ROM
During the firmware boot, at the block boundary, the Bad Block table is searched for a
match to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block checked.
If the Bad Block table start page is null, check the manufactory made Bad Block marker.
The location of the Bad Block maker is at the first three or last three pages in every block
of the NAND flash. The NAND manufacturers normally use one byte in the spare area of
certain pages within a block to mark that a block is bad or not. A value of 0xFF means
good block, non-FF means bad block.
To preserve the BI (bad block information), the flash updater or gang programmer
applications must swap the Bad Block Information (BI) data to byte 0 of the metadata
area for every page before programming the NAND flash. When the ROM loads the
firmware, it copies back the value at metadata[0] to the BI offset in the page data. This
figure shows how the factory bad block marker is preserved:
Bad block information at
column address 2048
64 B
2 KB Main area spare
512 main parity 512 main parity 512 main parity 512 main parity
meta
data Bad block information at
fourth block of data area
Swap byte
Figure 6-5. Factory bad block marker preservation
In the FCB structure, there are two elements (m_u32BadBlockMarkerByte and
m_u32BadBlockMarkerStartBit) to indicate the byte and bit place in the page data that
the manufacturer marked the bad block marker.
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6.1.5.2 Serial NOR Flash Boot via FlexSPI
6.1.5.2.1 Serial NOR eFUSE Configuration
Table 6-12. Fuse definition for Serial NOR over FlexSPI
Fuse Config Config Definitions Shipped Value Settings
BOOT_MODE[3:1] OEM Boot device selection 0 011 - Boot from FlexSPI
BOOT_MODE[0] OEM FlexSPI interface 0 0 - Flash with 3B READ
selection
1 - FlexSPI Hyperflash
3.3V
470[1:0] OEM FLEXSPI_AUTO_PRO 0 0 – QuadSPI NOR
BE_TYPE
1 – MXIC Octal
FLEXSPI Flash
2 – Micron Octal
AutoProbe Type
3 – Adesto Octal
470[2] OEM FLEXSPI_AUTO_PRO 0 0 – Disabled
BE_EN
1 – Enabled
FLEXSPI Flash
AutoProbe Enable
0x470[4:3] (Main) OEM OVERRIDE_FLEXSPI_ 0 00 - Flex SPI
BT_SEL_VAL (Hyperflash 1.8V)
FlexSPI Boot Selection 01 - Flex SPI (Flash
Override Value with 4B READ(0x13)
default supported)
10 - Default Octal mode
(Micron)
11 – Default Octal
Mode (Mixc)
0x470[5] (Main) OEM OVERRIDE_FLEXSPI_ 0 0 - Do not override
BT_SEL
1 - Override
Override FlexSPI boot
selection
0x480[2:0] OEM FLEXSPI_FEQ_SEL 0 0 - 100 MHz
FLEXSPI Flash 1 - 133 MHz
Frequency
2 - 166 MHz
3 - 200 MHz
4 - 80 MHz
5 - 20 MHz
Others – Reserved
480[6:3] OEM FLEXSPI_DUMMY_CY 0 0 – Dummy cycles is
CLE_SEL auto-probed
FLEXSPI Flash Dummy Others – Actual dummy
Cycle cycles for Read
command
Table continues on the next page...
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Table 6-12. Fuse definition for Serial NOR over FlexSPI (continued)
Fuse Config Config Definitions Shipped Value Settings
480[19:18] OEM FLEXSPI_HOLD_TIME 0 0 – 500us
_SEL
1 – 1ms
Hold time before read
2 – 3ms
from device
3 – 10ms
NOTE
If the xSPI FLASH Auto Probe feature is enabled, the
following is the logic how this feature works with other fuse
combinations:
• Flash Type - If Flash type is 0, the "xSPI FLASH Auto
Probe Type" takes effect for the Flash type selection. If
Flash Type is greater than or equal to 1, the "Flash Type"
Fuse is used for Flash type selection, ROM will issue
specific command to probe the presence of Serial NOR
FLASH.
• xSPI FLASH Frequency - This field is used for specifying
the Flash working frequency.
6.1.5.2.2 FlexSPI Serial NOR Flash Boot Operation
The Boot ROM attempts to boot from Serial NOR flash if the BOOT_MODE[3:1] fuses
are programmed to 0b011 as shown in the Serial NOR eFUSE Configuration table, then
the ROM will initialize FlexSPI interface as selected in the BOOT_MODE[0] settings of
the FlexSPI eFUSE configuration. FlexSPI interface initialization is a two-step process.
The ROM expects the 512-byte FlexSPI NOR configuration parameters as explained in
next section to be present at offset 0x400 in Serial NOR flash. The ROM reads these
configuration parameters using the read command configured in the LUT of the FlexSPI
interface with Serial clock operating at 30 MHz.
In the second step, ROM configures FlexSPI1 interface with the parameters provided in
configuration block read from Serial NOR flash and starts the boot procedure. Refer to
Table 25-14 for details regarding FlexSPI configuration parameters and to the FlexSPI
NOR boot flow chart for detailed boot flow chart of FlexSPI NOR.
Both booting an XIP and non XIP image are supported from Serial NOR Flash. For XIP
boot, the image has to be built for FlexSPI address space and for non XIP the image can
be built to execute from Internal RAM.
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6.1.5.2.3 FlexSPI NOR boot flow chart
Start
Configure FlexSPI Pinmux and
Clock to 30MHz to perform basic
read operation
Get Configuration parameter
Configure IOMUXC, LUT,
controller and clock based on the
configuration parameter read from
Flash device
Configure Flash device to desired
mode based on configuration
parameter
Set boot device parameter( initial
image address, memory range,
etc).
No
Image == XIP Copy image to OCRAM
Yes
Execute the image from FlexSPI1 Execute Image from
address space OCRAM
End
Figure 6-6. FlexSPI NOR boot flow
6.1.5.3 Serial NOR and NAND configuration based on FlexSPI
interface
The ROM SW supports Serial NOR and Serial NAND based on FlexSPI module, using a
448-bytes common FlexSPI configuration block and several specified parameters for
Serial NOR and Serial NAND respectively. See below sections for more details.
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6.1.5.3.1 FlexSPI Configuration Block
FlexSPI Configuration block consists of parameters regarding specific Flash devices
including read command sequence, quad mode enablement sequence (optional), etc.
Table 6-13. FlexSPI Configuration block
Name Offset Size(bytes) Description
Tag 0x000 4 0x42464346, ascii:” FCFB”
Version 0x004 4 0x56010000
[07:00] bugfix = 0
[15:08] minor = 0
[23:16] major = 1
[31:24] ascii ‘V’
- 0x008 4 Reserved
readSampleClkSrc 0x00C 1 0 – internal loopback
1 – loopback from DQS pad
3 – Flash provided DQS
dataHoldTime 0x00D 1 Serial Flash CS Hold Time
Recommend default value is
0x03
dataSetupTime 0x00E 1 Serial Flash CS setup time
Recommended default value
is 0x03
columnAdressWidth 0x00F 1 3 – For HyperFlash
12/13 – For Serial NAND, see
datasheet to find correct value
0 – Other devices
deviceModeCfgEnable 0x010 1 Device Mode Configuration
Enable feature
0 – Disabled
1 – Enabled
- 0x011 3 Reserved
deviceModeSeq 0x014 4 Sequence parameter for
device mode configuration
deviceModeArg 0x018 4 Device Mode argument,
effective only when
deviceModeCfgEnable = 1
configCmdEnable 0x01C 1 Config Command Enable
feature
0 – Disabled
1 – Enabled
- 0x01D 3 Reserved
configCmdSeqs 0x020 16 Sequences for Config
Command, allow 4 separate
Table continues on the next page...
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Table 6-13. FlexSPI Configuration block (continued)
Name Offset Size(bytes) Description
configuration command
sequences.
cfgCmdArgs 0x030 16 Arguments for each separate
configuration command
sequence.
controllerMiscOption 0x040 4 Bit0 – differential clock enable
Bit1 – CK2 enable, must set
to 0 in this silicon
Bit2 – ParallelModeEnable,
must set to 0 for this silicon
Bit3 –
wordAddressableEnable
Bit4 – Safe Configuration
Frequency enable set to 1 for
the devices that support DDR
Read instructions
Bit5 – Pad Setting Override
Enable
Bit6 – DDR Mode Enable, set
to 1 for device supports DDR
read command
deviceType 0x044 1 1 – Serial NOR
2 – Serial NAND
sflashPadType 0x045 1 1 – Single pad
2 – Dual pads
4 – Quad pads
8 – Octal pads
serialClkFreq 0x046 1 Chip specific value, for this
silicon
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
5 – 80 MHz
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
Other value: 30 MHz
lutCustomSeqEnable 0x047 1 0 – Use pre-defined LUT
sequence index and number
1 - Use LUT sequence
parameters provided in this
block
Table continues on the next page...
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Table 6-13. FlexSPI Configuration block (continued)
Name Offset Size(bytes) Description
- 0x048 8 Reserved
sflashA1Size 0x050 4 For SPI NOR, need to fill with
actual size
For SPI NAND, need to fill
with actual size * 2
sflashA2Size 0x054 4 The same as above
sflashB1Size 0x058 4 The same as above
sflashB2Size 0x05C 4 The same as above
csPadSettingOverride 0x060 4 Set to 0 if it is not supported
sclkPadSettingOverride 0x064 4 Set to 0 if it is not supported
dataPadSettingOverride 0x068 4 Set to 0 if it is not supported
dqsPadSettingOverride 0x06C 4 Set to 0 if it is not supported
timeoutInMs 0x070 0 Maximum wait time during
read busy status
0 – Disabled timeout checking
feature Other value – Timeout
if the wait time exceeds this
value.
commandInterval 0x074 4 Unit: ns
Currently, it is used for SPI
NAND only at high frequency
dataValidTime 0x078 4 Time from clock edge to data
valid edge, unit ns. This field
is used when the FlexSPI
Root clock is less than 100
MHz and the read sample
clock source is device
provided DQS signal without
CK2 support.
[31:16] data valid time for
DLLB in terms of 0.1 ns
[15:0] data valid time for DLLA
in terms of 0.1 ns
busyOffset 0x07C 2 busy bit offset, valid range :
0-31
busyBitPolarity 0x07E 2 0 – busy bit is 1 if device is
busy
1 – busy bit is 0 if device is
busy
lookupTable 0x080 256 Lookup table
lutCustomSeq 0x180 48 Customized LUT sequence,
see below table for details.
0x1B0 16 Reserved for future use
Note:
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1. To customize the LUT sequence for some specific device, users need to enable
“lutCustomSeqEnable” and fill in corresponding “lutCustomSeq” field specified by
command index below.
2. For Serial (SPI) NOR, the pre-defined LUT index is as follows:
Table 6-14. LUT sequence definition for Serial NOR
Command Index Name Index in lookup table Description
0 Read 0 Read command
Sequence
1 ReadStatus 1 Read Status
command
2 WriteEnable 3 Write Enable
command sequence
3 EraseSector 5 Erase Sector
Command
4 PageProgram 9 Page Program
Command
5 ChipErase 11 Full Chip Erase
6 Dummy 15 Dummy Command as
needed
Reserved 2,4,6,7,8,10,12,13,14 All reserved indexes
can be freely used for
other purpose
6.1.5.3.2 Serial NOR configuration block (512 bytes)
Table 6-15. Serial NOR configuration block
Name Offset Size (Bytes) Description
memCfg 0 448 The common memory
configuration block, see
FlexSPI configuration block
for more details
pageSize 0x1C0 4 Page size in terms of bytes,
not used by ROM
sectorSize 0x1C4 4 Sector size in terms of bytes,
not used by ROM
ipCmdSerialClkFreq 0x1C8 4 Chip specific value, not used
by ROM For Ultra
0 – No change, keep current
serial clock unchanged
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
5 – 80 MHz
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Table 6-15. Serial NOR configuration block (continued)
Name Offset Size (Bytes) Description
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
Reserved 0x1CC 52 Reserved for future use
6.1.5.3.3 Serial NAND configuration block(512 bytes)
Table 6-16. Serial NAND configuration block
Name Offset Size (Bytes) Description
memCfg 0 448 The common memory
configuration block, see
FlexSPI configuration block
for more details
pageDataSize 0x1C0 4 Page size in terms of bytes,
usually, it is 2048 or 4096
pageTotalSize 0x1C4 4 It equals to 2 ^ width of
column adddress
pagesPerBlock 0x1C8 4 Pages in one block
bypassReadStatus 0x1CC 1 0 – Read Status Register
1 – Bypass Read status
register
bypassEccRead 0x1CD 1 0 – Perform ECC read
1 – Bypass ECC read
hasMultiPlanes 0x1CE 1 0 – Only 1 plane
1 – Has two planes
skippOddBlocks 0x1CF 1 0 – Read Odd blocks
1 – Skip Odd blocks
eccCheckCustomEnable 0x1D0 1 0 – Use the common ECC
check command and ECC
related masks
1 - Use ECC check related
masks provided in this
configuration block
ipCmdSerialClkFreq 0x1D1 1 Chip specific value, not used
by ROM
0 – No change, keep current
serial clock unchanged
1 – 30 MHz
2 – 50 MHz
3 – 60 MHz
4 – 75 MHz
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Table 6-16. Serial NAND configuration block (continued)
Name Offset Size (Bytes) Description
5 – 80 MHz
6 – 100 MHz
7 – 133 MHz
8 – 166 MHz
readPageTimeUs 0x1D2 2 Wait time during page read,
this field will take effect on if
the bypassReadStatus is set
to 1
eccStatusMask 0x1D4 4 ECC Status Mask
eccFailureMask 0x1D8 4 ECC Check Failure mask
blocksPerDevice 0x1DC 4 Blocks in a Serial NAND
Reserved 0x1ED 32 Reserved for future use
Below is an example of Serial NAND configuration block for Winbond
W25N01GVZEIG:
const flexspi_nand_config_t kSerialNandCfgBlk =
{
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.dataHoldTime = 3,
.dataSetupTime = 3,
.columnAddressWidth = 12,
.deviceModeCfgEnable = 1,
.deviceModeSeq = { 1, 2 },
.deviceType = kFlexSpiDeviceType_SerialNAND,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_50MHz,
.lutCustomSeqEnable = 0,
.sflashA1Size = 128 * 1024 * 1024U * 2, // Flash size = 2 * actual data size
(exclude spare space)
.lookupTable =
{
// Read cache 4 I/0
[4 * NOR_CMD_LUT_SEQ_IDX_READ] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB,
CADDR_SDR, FLEXSPI_4PAD, 0x10),
[4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD,
0x04, READ_SDR, FLEXSPI_4PAD, 0x80),
// Clear Status1 flag
[4 * 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x1F, CMD_SDR, FLEXSPI_1PAD,
0xA0),
[4 * 2 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x00, STOP, FLEXSPI_1PAD,
0x00),
// Read Page
[4 * NAND_CMD_LUT_SEQ_IDX_READPAGE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x13, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Read Status
[4 * NAND_CMD_LUT_SEQ_IDX_READSTATUS] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x0F, CMD_SDR, FLEXSPI_1PAD, 0xC0),
[4 * NAND_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(READ_SDR,
FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0),
// Write Enable
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[4 * NAND_CMD_LUT_SEQ_IDX_WRITEENABLE] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x06, STOP, FLEXSPI_1PAD, 0),
// Page Program Load 4x
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMLOAD] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x32, CADDR_SDR, FLEXSPI_1PAD, 0x10),
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMLOAD + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR,
FLEXSPI_4PAD, 0x40, STOP, FLEXSPI_1PAD, 0),
// Page Program Execute
[4 * NAND_CMD_LUT_SEQ_IDX_PROGRAMEXECUTE] = FLEXSPI_LUT_SEQ(CMD_SDR,
FLEXSPI_1PAD, 0x10, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Erase Sector
[4 * NAND_CMD_LUT_SEQ_IDX_ERASEBLOCK] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Read ECC status
[4 * NAND_CMD_LUT_SEQ_IDX_READECCSTAT] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD,
0x0F, CMD_SDR, FLEXSPI_1PAD, 0xC0),
[4 * NAND_CMD_LUT_SEQ_IDX_READECCSTAT + 1] = FLEXSPI_LUT_SEQ(READ_SDR,
FLEXSPI_1PAD, 0x01, STOP, FLEXSPI_1PAD, 0),
},
},
.pageDataSize = 2048,
.pageTotalSize = 4096,
.pagesPerBlock = 64,
};
6.1.5.4 NAND flash
The boot ROM supports a number of MLC/SLC NAND flash devices from different
vendors and LBA NAND flash devices. The Error Correction and Control (ECC)
subblock (BCH) is used to detect the errors.
6.1.5.4.1 NAND eFUSE configuration
The boot ROM determines the configuration of the external NAND flash by parameters,
either provided by the eFUSE, or sampled on the BOOT_MODE[3:0] pins during boot.
See Table 6-17 for parameters details.
Table 6-17. NAND boot eFUSE descriptions
Fuse Config Definition Shipped Settings
value
4A0[15] OEM BT_TOGGLE_MODE 0 0—raw NAND
1—toggle mode NAND
470[7:6] OEM OVERRIDE_NAND_PG_PER_B 0 RAWNAND:
LK_VAL 00 - 32 pages
01 - 64 pages
Pages in block
10 - 128 pages
11 - 32 pages
FlexSPI NAND:
00 - 64 pages
01 - 128 pages
10 - 256 pages
11 - 32 pages
Table continues on the next page...
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Table 6-17. NAND boot eFUSE descriptions (continued)
Fuse Config Definition Shipped Settings
value
4B0[11:10] OEM Row address cycles 00 00—3
01—2
10—4
11—5
4A0[12:9] OEM Toggle mode 33 MHz preamble 000 0000—16 GPMICLK cycles
delay, read latency
0001—1 GPMICLK cycles
0010—2 GPMICLK cycles
0011—3 GPMICLK cycles
0100—4 GPMICLK cycles
0101—5 GPMICLK cycles
0110—6 GPMICLK cycles
0111—7 GPMICLK cycles
1000—8 GPMICLK cycles
1001—9 GPMICLK cycles
1010—10 GPMICLK cycles
1011—11 GPMICLK cycles
1100—12 GPMICLK cycles
1101—13 GPMICLK cycles
1110—14 GPMICLK cycles
1111—15 GPMICLK cycles
4A0[14:13] OEM Boot search count 00 00—2
01—2
10—4
11—8
0x4B0[7] OEM Override pad settings 0 Override the NAND pad settings
0—use the default values
1—use the PAD_SETTINGS value
0x4A0[31:24] OEM PAD_SETTINGS[7:0] 0 NAND pad settings value
0x4B0[15:12] OEM READ_RETRY_SEQ_ID[3:0] 0000 0000—don't use the ROM
embedded read-retry sequence
0001—use Micron 20 nm read-retry
sequence
0010—use Toshiba A19nm read-
retry sequence
0011—use Toshiba 19nm read-
retry sequence
0100—use SanDisk 19nm read-
retry sequence
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Table 6-17. NAND boot eFUSE descriptions
Fuse Config Definition Shipped Settings
value
0101—use SanDisk 1ynm read-
retry sequence
0110 to 1111—reserved
6.1.5.4.2 NAND flash boot flow and Boot Control Blocks (BCB)
There are two BCB data structures:
• FCB
• DBBT
As a part of the NAND media initialization, the ROM driver uses safe NAND timings to
search for the Firmware Configuration Block (FCB) that contains the optimum NAND
timings, the page address of the Discovered Bad Block Table (DBBT) Search Area, and
the start page address of the primary and secondary firmware.
The hardware ECC level to use is embedded inside the FCB block. The FCB data
structure is also protected using the ECC. The driver reads raw 2112 bytes of the first
sector and runs through the software ECC engine that determines whether the FCB data is
valid or not.
If the FCB is found, the optimum NAND timings are loaded for further reads. If the ECC
fails, or the fingerprints do not match, the Block Search state machine increments the
page number to the Search Stride number of pages to read for the next BCB until the
SearchCount pages have been read.
If the search fails to find a valid FCB, the NAND driver responds with an error and the
boot ROM enters the serial download mode.
The FCB contains the page address of the DBBT Search Area, and the page address for
primary and secondary boot images. The DBBT is searched in the DBBT Search Area,
just like the FCB is searched. After the FCB is read, the DBBT is loaded, and the primary
or secondary boot image is loaded using the starting page address from the FCB.
This figure shows the state diagram of the FCB search:
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START
Current Page = 0,
Search Stride = Stride Size Fuse Value,
Search Count = Boot Search Count Fuse Value
Read 4K, ReadCount++
Current Page += Search
Stride
YES
Read Count <
Is Valid FCB? NO
Search Count
YES NO
Recovery Device/
NCB Found
Serial Loader
Figure 6-7. FCB search flow
When the FCB is found, the boot ROM searches for the Discovered Bad Blocks Table
(DBBT). If the DBBT Search Area is 0 in the FCB, the ROM assumes that there are no
bad blocks on the NAND device boot area. See this figure for the DBBT search flow:
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START
Current Page = DBBT Start Page,
Search Stride = Stride Size Fuse Value,
Search Count = 4
Read 4K, ReadCount++
Current Page += Search
Stride
YES
Read Count <
Is Valid DBBT? NO
Search Count
YES
NO
DBBT Found, Copy to IRAM
DBBT Not Found
DBBT Found
Figure 6-8. DBBT search flow
6.1.5.4.3 Firmware configuration block
The FCB is the first sector in the first good block. The FCB must be present at each
search stride of the search area.
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The search area contains copies of the FCB at each stride distance, so, in case the first
NAND block becomes corrupted, the ROM finds its copy in the next NAND block. The
search area must span over at least two NAND blocks. The location information for the
DBBT search area, FW1, and FW2 are all specified in the FCB. This table shows the
flash control block structure:
Table 6-18. Flash control block structure
Name Start byte Size in bytes Description
Reserved 0 4 Reserved for Fingerprint #1(Checksum)
FingerPrint 4 4 32-bit word with a value of 0x20424346, in ascii
"FCB"
Version 8 4 32-bit version number; this version of FCB is
0x00000001
m_NANDTiming 12 8 8 B of data for eight NAND timing parameters
from the NAND datasheet. The eight
parameters are:
m_NandTiming[0]=data_setup,
m_NandTiming[1]=data_hold,
m_NandTiming[2]=address_setup,
m_NandTiming[3]=dsample_time,
m_NandTiming[4]=nand_timing_state,
m_NandTiming[5]=REA,
m_NandTiming[6]=RLOH,
m_NandTiming[7]=RHOH.
The ROM only uses the first four parameters,
but the FCB provides space for other four
parameters to be used by the bootloader or
other applications.
PageDataSize 20 4 The number of bytes of data in a page.
Typically, this is 2048 bytes for 2112 bytes
page size or 4096 bytes for 4314/4224 bytes
page size or 8192 for 8568 bytes page size.
TotalPageSize 24 4 The total number of bytes in a page. Typically,
2112 for 2-KB page or 4224 or 4314 for 4-KB
page or 8568 for 8-KB page.
SectorsPerBlock 28 4 The number of pages per block. Typically 64 or
128 or depending on the NAND device type.
NumberOfNANDs 32 4 Not used by ROM
TotalInternalDie 36 4 Not used by ROM
CellType 40 4 Not used by ROM
EccBlockNEccType 44 4 Value from 0 to is used to set the BCH Error
Corrrection level 0, 2, 4, .. or 62 for Block BN of
ECC page, used in configuring the BCH62
page layout registers.
EccBlock0Size 48 4 Size of block B0 used in configuring the BCH62
page-layout registers.
Table continues on the next page...
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Table 6-18. Flash control block structure (continued)
Name Start byte Size in bytes Description
EccBlockNSize 52 4 Size of block BN used in configuring the
BCH62 page-layout registers.
EccBlock0EccType 56 4 Value from 0 to used to set the BCH Error
Corrrection level 0, 2, 4, .. or 62 for Block BN of
ECC page, used in configuring the BCH62
page layout registers.
MetadataBytes 60 4 Size of metadata bytes used in configuring the
BCH62 page-layout registers.
NumEccBlocksPerPage 64 4 Number of the ECC blocks BN not including
B0. This value is used in configuring the
BCH62 page-layout registers.
EccBlockNEccLevelSDK 68 4 Not used by ROM
EccBlock0SizeSDK 72 4 Not used by ROM
EccBlockNSizeSDK 76 4 Not used by ROM
EccBlock0EccLevelSDK 80 4 Not used by ROM
NumEccBlocksPerPageSDK 84 4 Not used by ROM
MetadataBytesSDK 88 4 Not used by ROM
EraseThreshold 92 4 Not used by ROM
Firmware1_startingPage 104 4 Page number address where the first copy of
bootable firmware is located.
Firmware2_startingPage 108 4 Page number address where the second copy
of bootable firmware is located.
PagesInFirmware1 112 4 Size of the first copy of firmware in pages.
PagesInFirmware2 116 4 Size of the second copy of firmware in pages.
DBBTSearchAreaStartAddress 120 4 Page address for the bad block table search
area.
BadBlockMarkerByte 124 4 This is an input offset in the BCH page for the
ROM to swap with the first byte of metadata
after reading a page using the BCH62. The
ROM supports the restoration of manufacturer-
marked bad block markers in the page and this
offset is the bad block marker offset location.
BadBlockMarkerStartBit 128 4 This is an input bit offset in the
BadBlockMarkerByte for the ROM to use when
swapping eight bits with the first byte of
metadata.
BBMarkerPhysicalOffset 132 4 This is the offset where the manufacturer
leaves the bad block marker on a page.
BCHType 136 4 0 for BCH20 and 1 for BCH62. The chip is
backwards compatible to BCH20 and this field
tells the ROM to use the BCH20 or BCH62
block.
TMTiming2_ReadLatency 140 4 Toggle mode NAND timing parameter read
latency, the ROM uses this value to configure
the timing2 register of the GPMI.
Table continues on the next page...
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Table 6-18. Flash control block structure (continued)
Name Start byte Size in bytes Description
TMTiming2_PreambleDelay 144 4 Toggle mode NAND timing parameter
Preamble Delay. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_CEDelay 148 4 Toggle mode NAND timing parameter CE
Delay. The ROM uses this value to configure
the timing2 register of the GPMI.
TMTiming2_PostambleDelay 152 4 Toggle mode NAND timing parameter
Postamble Delay. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_CmdAddPause 156 4 Toggle mode NAND timing parameter Cmd
Add Pause. The ROM uses this value to
configure the timing2 register of the GPMI.
TMTiming2_DataPause 160 4 Toggle mode NAND timing parameter Data
Pause. The ROM uses this value to configure
the timing2 register of the GPMI.
TMSpeed 164 4 This is the toggle mode speed for the ROM to
configure the gpmi clock. 0 for 33 MHz, 1 for 40
MHz, and 2 for 66 MHz.
TMTiming1_BusyTimeout 168 4 Toggle mode NAND timing parameter Busy
Timeout. The ROM uses this value to configure
the timing1 register of the GPMI.
DISBBM 172 4 If 0, the ROM swaps the BadBlockMarkerByte
with metadata[0] after reading a page using the
BCH62. If the value is 1, the ROM does not
swap.
BBMark_spare_offset 176 4 The offset in the metadata place which stores
the data in the bad block marker place.
Onfi_sync_enable 180 4 Enable the Onfi nand sync mode support.
Onfi_sync_speed 184 4 Speed for the Onfi nand sync mode:
0 - 24 MHz, 1 - 33 MHz, 2 - 40 MHz, 3 - 50
MHz, 4 - 66 MHz, 5 - 80 MHz, 6 - 100 MHz, 7 -
133 MHz, 8 - 160 MHz, 9 - 200 MHz
Onfi_syncNANDData 188 28 The parameters for the Onfi nand sync mode
timing. They are read latency, ce_delay,
preamble_delay, postamble_delay,
cmdadd_pause, data_pause, and
busy_timeout.
DISBB_Search 216 4 Disable the bad block search function when
reading the firmware, only using DBBT.
The FCB data structure is protected using a 62-bit ECC. The layout of the FCB page is
illustrated in this figure:
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Meta D0 D1 D2 D3
parity
parity
parity
parity
32B 128B 128B 128B 128B
D4 D5 D6 D7
parity
parity
parity
parity
128B 128B 128B 128B
Figure 6-9. Layout of the FCB page
The detailed parameters of the FCB pages are listed in this table:
Table 6-19. Parameters setting for FCB page
Parameter Value
TotalPageSize 2048+64=2112
MetadataBytes 32
EccBlock0Size 128
EccBlock0EccType 31
BCHType 0
EccBlockNSize 128
EccBlockNEccType 31
NumEccBlocksPerPage 7
To reduce the disturbances caused by a neighboring cell in the FCB page in the NAND
chip, a randomizer is enabled when reading the FCB page. BCH ECC has a Randomizer
module that is interfaced through the GPMI APBHDMA chain. The Randomizer can
generate random data based on BCH ECC encoded/decoded data. It can be employed to
reduce the disturbances caused by a neighboring cell in the NAND chip, thus reducing bit
errors. The randomizer is used to reduce the bit errors in the FCB. Ensure that the
randomizer is enabled when burning the FCB pages in the NAND flash. To control the
randomizer for the pages (except for FCB), a new field called Randomizer_Enable is
added into the FCB structure. If the Randomizer_Enable field is set to 0, the randomizer
is disabled. Reading the pages (except for FCB) being set to a non-zero value enables the
randomizer. For detailed randomizer information, see Randomizer.
6.1.5.4.4 Discovered Bad Block Table (DBBT)
See this table for the DBBT format:
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Table 6-20. DBBT structure
Name Start byte Size in bytes Description
Reserved 0 4 -
FingerPrint 4 4 32-bit word with a value of 0x44424254,in
ascii "DBBT"
Version 8 4 32-bit version number; this version of
DBBT is 0x00000001
Reserved 12 4 -
DBBT_NUM_OF_PAGES 16 4 Size of the DBBT in pages
Reserved 20 4*PageSize-20 -
Reserved 4*PageSize 4 -
Number of Entries 4*PageSize + 4 4 Number of bad blocks
Bad Block Number 1 4*PageSize + 8 4 First bad block number
Bad Block Number 2 4*PageSize + 12 4 Second bad block number
... ... ... ...
Bad Block Number n 4*PageSize + 4*(n+1) 4 The nth bad block
6.1.5.4.5 Bad block handling in ROM
During the firmware boot, at the block boundary, the Bad Block table is searched for a
match to the next block.
If no match is found, the next block can be loaded. If a match is found, the block must be
skipped and the next block checked.
If the Bad Block table start page is null, check the manufactory made Bad Block marker.
The location of the Bad Block maker is at the first three or last three pages in every block
of the NAND flash. The NAND manufacturers normally use one byte in the spare area of
certain pages within a block to mark that a block is bad or not. A value of 0xFF means
good block, non-FF means bad block.
To preserve the BI (bad block information), the flash updater or gang programmer
applications must swap the Bad Block Information (BI) data to byte 0 of the metadata
area for every page before programming the NAND flash. When the ROM loads the
firmware, it copies back the value at metadata[0] to the BI offset in the page data. This
figure shows how the factory bad block marker is preserved:
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Bad block information at
column address 2048
64 B
2 KB Main area spare
512 main parity 512 main parity 512 main parity 512 main parity
meta
data Bad block information at
fourth block of data area
Swap byte
Figure 6-10. Factory bad block marker preservation
In the FCB structure, there are two elements (m_u32BadBlockMarkerByte and
m_u32BadBlockMarkerStartBit) to indicate the byte and bit place in the page data that
the manufacturer marked the bad block marker.
6.1.5.4.6 Toggle mode DDR NAND boot
If the BT_TOGGLEMODE efuse is blown, the ROM does the following to boot from the
Samsung's toggle mode DDR NAND.
6.1.5.4.6.1 GPMI and BCH clocks configuration
The ROM sets the clock source and the dividers in the CCM registers.
If the 0x4A0[15] is set (toggle mode), the GPMI/BCH CLK source is PLL2PFD4, and
running at 66 MHz, otherwise the GPMI/ BCH CLK souce is PLL3, running at 24 MHz.
The ROM sets the default values to timing0, timing1, and timing2 gpmi registers for 24
MHz clock speed. It uses the 0x4A0[12:9] fuse to configure the GPMI timing2 register
parameters preamble delay and read latency. The default value for these parameters is 2
when the fuses are not blown.
The default timing parameter values used by the ROM for the toggle-mode device are:
• Timing0.ADDRESS_SETUP = 5
• Timing0.DATA_SETUP = 10
• Timing0.DATA_HOLD = 10
• Timing1.DEVICE_BUSY_TIMEOUT = 0 x 500
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• Timing2.READ_LATENCY = 0x4A0[12:9] fuse selection, if blown, otherwise 2
• Timing2.CE_DELAY = 2
• Timing2.PREAMBLE_DELAY = 0x4A0[12:9] fuse selection, if blown, otherwise 2
• Timing2.POSTAMBLE_DELAY = 3
• Timing2.CMDADD_PAUSE = 4
• Timing2.DATA_PAUSE = 6
The default timing parameters can be overriden by the TMTiming2_ReadLatency,
TMTiming2_PreambleDelay, TMTiming2_CEDelay, TMTiming2_PostambleDelay,
TMTiming2_CmdAddPause, and TMTiming2_DataPause parameters of the FCB.
6.1.5.4.6.2 Setup DMA for DDR transfers
In the DMA descriptors, the GPMI is configured to read the page data at a double data
rate, the word length is set to 16, and the transfer count to a half of the page size.
6.1.5.4.6.3 Reconfigure timing and speed using values in FCB
After reading the FCB page with the GPMI set to default timings and a speed of 33 MHz,
the ROM reconfigures the CCM dividers to run the gpmi/bch clks to a desired speed
specified in the FCB for the rest of the boot process. The GPMI timing registers are also
reconfigured to the values specified in the FCB.
The GPMI speed can be configured using the FCB parameter TMSpeed:
• 0—25 MHz
• 1—33 MHz
• 2—40 MHz
• 3—50 MHz
• 4—66 MHz
• 5—80 MHz
• 6—100 MHz
• 7—133 MHz
• 8—133 MHz
• 9—200 MHz
The GPMI timing0 register fields data_setup, data_hold, and address_setup are set to the
values specified for the data_setup and data_hold and address_setup in the FCB member
m_NANDTiming.
The GPMI timing1.DEVICE_BUSY_TIMEOUT is set to the value specified in the FCB
member TMTiming1_BusyTimeout.
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The GPMI timing2 register values are set using the FCB members
TMTiming2.READ_LATENCY, CE_DELAY, PREAMBLE_DELAY,
POSTAMBLE_DELAY, CMDADD_PAUSE, and DATA_PAUSE.
6.1.5.4.7 Typical NAND page organization
6.1.5.4.7.1 BCH ECC page organization
The first data block is called block 0 and the rest of the blocks are called block N. A
separate ECC level scan is used for block 0 and block N.
The metadata bytes must be located at the beginning of a page, starting at byte 0,
followed by the data block 0, the ECC bytes for data block 0, the block 1 and its ECC
bytes, and so on, up until the N data blocks. The ECC level for the block 0 can be
different from the ECC level for the rest of the blocks.
For the NAND boot with page-size restrictions and the data block size restricted to 512
B, only few combinations of the ECC for block 0 and block N are possible.
This figure shows the valid layout for 2112-byte sized page.
Block0 Block1 Block2 Block3
M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 6-11. Valid layout for 2112-byte sized page
The example below is for 13 bits of parity (GF13). The number of ECC bits required for
a data block is calculated using the (ECC_Correction_Level * 13) bits.
In the above layout, the ECC size for EccB0 and EccBN must be selected to not exceed a
total page size of 2112 bytes. The EccB0 and EccBN can be one of the 2, 4, 6, 8, 10, 12,
14, 16, 18, and 20 bits on the ECC correction level. The total bytes are:
[M + (data_block_size x 4) + ([EccB0 + (EccBN x 3)] x 13) / 8] <= 2112;
M = metadata bytes and data_block_size is 512.
There are four data blocks of 512 bytes each in a page of 2-KB page sized NAND. The
values of EccB0 and EccBN must be such that the above calculation does not result in a
value greater than 2112 bytes.
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Block0 Block1 Block2 Block3
M 512 bytes EccB0 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Block4 Block5 Block6 Block7
512 bytes EccBN 512 bytes EccBN 512 bytes EccBN 512 bytes EccBN
Figure 6-12. Valid layout for 4-KB sized page
Different NAND manufacturers have different sizes for a 4-KB page; 4314 bytes is
typical.
[M + (data_block_size x 8) + ([EccB0 + (EccBN x 7)] x 13) / 8] <= 4314;
M= metadata bytes and data_block_size is 512.
There are eight data blocks of 512 bytes each in a page of a 4-KB page sized NAND. The
values of the EccB0 and EccBN must be such that the above calculation does not result in
a value greater than the size of a page in a 4-KB page NAND.
6.1.5.4.7.2 Metadata
The number of bytes used for the metadata is specified in the FCB. The metadata for the
BCH encoded pages is placed at the beginning of a page. The ROM only cares about the
first byte of metadata to swap it with a bad block marker byte in the page data after each
page read; it is important to have at least one byte for the metadata bytes field in the FCB
data structure.
6.1.5.4.8 IOMUX configuration for NAND
The following table shows the RawNAND IOMUX pin configuration.
Table 6-21. NAND IOMUX pin configuration
Signal Pad name
NAND_ALE NAND_ALE.alt0
NAND_CE0_B NAND_CE0_B.alt0
NAND_CE1_B NAND_CE1_B.alt0
NAND_CE2_B NAND_CE2_B.alt0
NAND_CE3_B NAND_CE3_B.alt0
NAND_CLE NAND_CLE.alt0
NAND_DATA00 NAND_DATA00.alt0
Table continues on the next page...
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Table 6-21. NAND IOMUX pin configuration (continued)
Signal Pad name
NAND_DATA01 NAND_DATA01.alt0
NAND_DATA02 NAND_DATA02.alt0
NAND_DATA03 NAND_DATA03.alt0
NAND_DATA04 NAND_DATA04.alt0
NAND_DATA05 NAND_DATA05.alt0
NAND_DATA06 NAND_DATA06.alt0
NAND_DATA07 NAND_DATA07.alt0
NAND_DQS NAND_DQS.alt0
NAND_RE_B NAND_RE_B.alt0
NAND_READY_B NAND_READY_B.alt0
NAND_WE_B NAND_WE_B.alt0
NAND_WP_B NAND_WP_B.alt0
6.1.5.5 Expansion device
The ROM supports booting from the MMC/eMMC and SD/eSD compliant devices.
6.1.5.5.1 Expansion device eFUSE configuration
The SD/MMC/eSD/eMMC/SDXC boot can be performed using either USDHC ports,
based on the setting of the BOOT_MODE[3:0].
All USDHC ports support the fast boot. See this table for details:
Table 6-22. USDHC boot eFUSE descriptions
Fuse Config Definition Shipped Settings
value
0x470[15:12] OEM BOOT_MODE_FUSES 0 0010 - USDHC3 (eMMC boot only, SD3 8-
bit)
Boot device selection
0011 - USDHC2 (SD boot only, SD2)
490[6] OEM Fast boot support 000 0 - Normal boot
1 - Fast boot
490[5:4] OEM Bus width 000 00 - 8-bit
01 - 4-bit
10 - 8-bit DDR (MMC 4.4)
11 - 4-bit DDR (MMC 4.4)
490[3:2] OEM Speed mode SD speed selection
00 - Normal/SDR12
01 - High/SDR25
Table continues on the next page...
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Table 6-22. USDHC boot eFUSE descriptions (continued)
Fuse Config Definition Shipped Settings
value
10 - SDR50
11 - SDR104
MMC speed selection
00 - Normal
01 - High
490[1] OEM USDHC IO Voltage Selection USDHC1 IO VOLTAGE SELECTION (for
Normal boot mode)
0 - 3.3 V
1 - 1.8 V
470[10:9] OEM OVERRIDE_USDHC_BT_SE 00 00 - USDHC1 SD
L_VAL
01 - USDHC1 eMMC
10 - USDHC2 eMMC
11 - USDHC3 SD
490[7] OEM SD power cycle enable/ 0 SD power cycle/eMMC reset
eMMC reset enable
0 - Disabled
1 - Enabled
0x490[14:8] OEM SD/MMC DLL DLY config 0 Delay target for USDHC DLL, it is applied
to the slave mode target delay or overrides
the mode target delay, depending on the
DLL override fuse bit value.
0x490[15] OEM USDHC DLL override 0 0 - No override
enabled
1 - Override
0x490[16] OEM USDHC DLL enabled 0 0 - Disable the DLL for SD/eMMC
1 - Enable the DLL for SD/eMMC
0x490[18] OEM USDHC_IOMUX_SION_BIT_ 0 0 - Disable
ENABLE
1 - Enable
0x490[21] OEM Issue pre-idle command 0 0 - Enable
enabled (for eMMC4.4)
1 - Disable
0x490[23] OEM Disable SDMMC manufacture 0 0 - Enable
mode
1 - Disable
0X490[31:24] OEM USDHC pad setting override 0 Override pad settings
0x4A0[0] OEM Fast boot acknowledge 0 0 - Boot Ack disabled
enable
1 - Boot Ack enabled
0x4A0[2] OEM uSDHC power-off polarity 0 0 - Low
selection
1 - High
0x4A0[3] OEM uSDHC power cycle delay 0 0 - 5 ms
selection
1 - 2.5 ms
0x4A0[5:4] OEM uSDHC power cycle interval 0 00 - 20 ms
01 - 10 ms
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-22. USDHC boot eFUSE descriptions
Fuse Config Definition Shipped Settings
value
10 - 5 ms
11 - 2.5 ms
The boot code supports these standards:
• MMCv4.4 or less
• eMMCv5.1 or less
• SDv2.0 or less
• eSDv2.10 rev-0.9, with or without FAST_BOOT
• SDXCv3.0
The MMC/SD/eSD/SDXC/eMMC can be connected to any of the USDHC blocks and
can be booted by copying 4 KB of data from the MMC/SD/eSD/eMMC device to the
internal RAM. After checking the Image Vector Table header value (0xD1) from
program image, the ROM code performs a DCD check. After a successful DCD
extraction, the ROM code extracts from the Boot Data Structure the destination pointer
and length of image to be copied to the RAM device from where the code execution
occurs.
The maximum image size to load into the SD/MMC boot is 32 MB. This is due to a
limited number of uSDHC ADMA Buffer Descriptors allocated by the ROM.
NOTE
The initial 4 KB of the program image must contain the IVT,
DCD, and the Boot Data structures.
Table 6-23. SD/MMC frequencies
SD MMC MMC (DDR mode)
Identification (KHz) 347.22
Normal-speed mode (MHz) 25 20 25
High-speed mode (MHz) 50 40 50
UHSI SDR50 (MHz) 100
UHSI SDR104 (MHz) 200
NOTE
The boot ROM code reads the application image length and the
application destination pointer from the image.
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6.1.5.5.2 MMC and eMMC boot
This table provides the MMC and eMMC boot details.
Table 6-24. MMC and eMMC boot details
Normal boot mode During the initialization (normal boot mode), the MMC
frequency is set to 347.22 KHz. When the MMC card enters
the identification portion of the initialization, the voltage
validation is performed, and the ROM boot code checks the
high-voltage settings and the card capacity. The ROM boot
code supports both the high-capacity and low-capacity MMC/
eMMC cards. After the initialization phase is complete, the
ROM boot code switches to a higher frequency (20 MHz in
the normal boot mode or 40 MHz in the high-speed mode).
The eMMC is also interfaced via the USDHC and follows the
same flow as the MMC.
The boot partition can be selected for an MMC4.x card after
the card initialization is complete. The ROM code reads the
BOOT_PARTITION_ENABLE field in the Ext_CSD[179] to get
the boot partition to be set. If there is no boot partition
mentioned in the BOOT_PARTITION_ENABLE field or the
user partition was mentioned, the ROM boots from the user
partition.
eMMC4.3 or eMMC4.4 device supporting special boot mode If using an eMMC4.3 or eMMC4.4 device that supports the
special boot mode, it can be initiated by pulling the CMD line
low. If the BOOT ACK is enabled, the eMMC4.3/eMMC4.4
device sends the BOOT ACK via the DATA lines and the
ROM can read the BOOT ACK [S010E] to identify the
eMMC4.3/eMMC4.4 device. If the BOOT ACK is enabled, the
ROM waits 50 ms to get the BOOT ACK. If BOOT ACK is
disabled ROM waits 1 second for data. If the BOOT ACK or
data was received, the eMMC4.3/eMMC4.4 is booted in the
"boot mode", otherwise the eMMC4.3/eMMC4.4 boots as a
normal MMC card from the selected boot partition. This boot
mode can be selected by the 0x490[6] (fast boot) fuse. The
BOOT ACK is selected by the 0x4A0[0] fuse.
eMMC4.4 device If using the eMMC4.4 device, the Double Data Rate (DDR)
mode can be used. This mode can be selected by the
0x490[5:4] (bus width) fuse.
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Chapter 6 SNVS, Reset, Fuse, and Boot
Start
Check data bus width fuse.
. Accordingly
do the IOMUX config
eSDHC Software Reset, Set RSTA
Set Identification Frequency
(Approx 400 KHz)
Check MMC and Fast Boot Yes
6
Selection Fuse
No
Set INITA to send 80 SDCLK to card
Card SW Reset (CMD0)
No
Command Successful? 5
Yes
SD MMC
1 Check SD/MMC Selection fuse 2
Figure 6-13. Expansion device boot flow (1 of 6)
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System Boot
Set Strong pull-up
For CMD line
Start GPT with 1s delay MMC Boot Set MMC card CSD Set operating frequency MMC Boot
Voltage Validation (Issue CMD9) to 20 MHz Device Init
for CMD1
Set Weak pull-up Put card data Transfer
For CMD line Mode (Issue CMD7)
Issue CMD1 with HV Increment loop counter
Yes
No No
Command Successful? Command Successful?
No Yes
Command Successful? 5
No Send CMD13 to read
Yes Set RCA (Issue CMD3) status
Yes Loop Cntr < 3000 and Yes
Busy Bit == 1 Yes
looping period < 1s Card State ==
No 5
Command Successful? TRANS?
No
Is Response OCR for Yes Yes
Card Is HC MMC
HC Get CID from card(Issue No
Spec ver >= 4.0?
CMD2)
No Yes
Card Is LC MMC
Send CMD8 to get
Ext_CSD
No Bus width No High Speed mode Extract the boot partition
fuse <> 1? fuse == 0? to set
Yes Yes No
Send switch command Got valid partition?
Send switch command
to change bus width and
to set high frequency
DDR mode Yes
Yes Yes
No No Send switch command
4 Switch Successful? Switch Successful? to select partition
Yes Yes
Change ESDHC bus Set operating frequency
width to 40 MHz
Start MMC Boot
Switch Command
Send CMD6 with switch
argument
No
Command Successful?
Yes
Set CMD13 poll timeout
to 100ms
Send CMD13 to read
status
No
Command Successful?
No Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes
Switch failed Switch succeeded Switch failed
End
Figure 6-14. Expansion device (MMC) boot flow (2 of 6)
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Chapter 6 SNVS, Reset, Fuse, and Boot
Issue CMD8 with HV
(3.3V) SD Boot
Voltage Validation
No Issue CMD8 with LV No
Command Successful? Command Successful?
(1.8V)
Yes Yes
Card is HC/LC HV SD
ver 2.x
Set ACMD41 ARG to LV Card is LC SD Card is LC SD
and HC ver 2.x ver 1.x
Set ACMD41 ARG to HV No
UHSI mode Set ACMD41 ARG bit 29
and HC selected? for FAST BOOT
Yes
Start GPT delay of1s for Set ACMD41 ARG to HV
Set ACMD41 ARG bit 24
ACMD41 and LC
for 1.8v switch
Issue CMD55
Set ACMD41 ARG bit 28
for SDXC power control
No
Command Successful?
Yes Yes
FAST_BOOT Yes
selected? No Loop Cntr < 3000 and
Issue ACMD41 2
looping period < 1s
No
No
Command Successful?
No UHSI mode No Yes
Busy Bit == 1 Issue ACMD41
selected？
Yes
Bit 24 of response No
2
0 set?
Yes
No Is Response OCR for Yes
Card is LC SD Card is HC SD
HC
Figure 6-15. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 1
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8 SD Boot
Switch Voltage
Send CMD11 to switch
voltage
No
Command Successful?
Yes
No
DATA lines driven low?
Yes
switch supply voltage
to 1.8v
delay for 5ms
set DATA line voltage
high poll timeout to
1ms
No
Voltage high No DATA lines
poll timeout? driven high?
Yes Yes
Switch failed Switch succeeded
2 7
Figure 6-16. Expansion device (SD/eSD/SDXC) boot flow (3 of 6) part 2
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Chapter 6 SNVS, Reset, Fuse, and Boot
Get CID from card(Issue
CMD2)
SD Boot
Device Initialization
Yes Yes Set operating frequency
Command Successful? Get RCA (Issue CMD3) Command Successful?
to 20 MHz
No No
Put card data Transfer
5 Mode (Issue CMD7)
No
No
Card State == Send CMD13 to read Yes
TRANS? Command Successful?
status
Yes
Yes
UHSI mode selected? 9
No
Yes Yes Send ACMD6 with bus Command Successful?
Bus width Send CMD55 Command Successful?
fuse <> 1? width argument Yes
No No
No
Change USDHC bus Yes Set CMD13 poll timeout
Success? Check Status
width to 100ms
No
High Speed mode
fuse == 0? Yes
Send CMD6 with high Yes Set operating frequency
No Command Successful?
speed argument to 40 MHz
No
Send CMD43 to select
10
partition 1
No
Command Successful? 4
Yes Set CMD13 poll timeout
to 15ms
FAST_BOOT Yes
Card is eSD
selected? Set CMD13 poll timeout Check Status
No to 1s
9 SD Boot
UHSI init
Check response of
CMD7
Yes No
Card is locked?
No
No Send ACMD6 with Yes
Command Successful? Command Successful? Send CMD55
argument of 4 bit width
Yes
Set CMD13 poll timeout Yes Change USDHC bus
Check Status Success?
to 100ms width
No
No Send CMD6 with clock Get clock speed from
Command Successful?
speed argument fuse
Yes
Change USDHC clock Loopback clock Yes Set loopback clock bit in
speed fuse set? USDHC register
No
Init failed
11
Figure 6-17. Expansion device (MMCSD/eSD/SDXC) boot flow (4 of 6)
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SD Boot USB Boot
Check Status
Serial Boot
Start 5
Send CMD13 to read
status USB Flow
(Serial Boot)
No No
Command Successful?
Yes
CMD13 Poll No Card State ==
timeout? TRANS?
Yes Yes
Failure Success Failure
End
4 SD/MMC Boot
Data Read
No Set block length 512
DDR Mode Selected?
bytes (Issue CMD16)
Yes
Init ADMA buffer Yes
Command Successful?
descriptors
No
Send CMD18 (multiple
block read)
Set CMD18 poll timeout
to 1s
Wait for command
completion or timeout
No
Command Successful? 5
Yes
End
Figure 6-18. Expansion device (SD/eSD) boot flow (5 of 6)
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Chapter 6 SNVS, Reset, Fuse, and Boot
6
eMMC 4.x Boot
Fast Boot
High Speed mode Yes Set operating frequency
fuse == 0? to 40 MHz
No
Set operating frequency
to 20 MHz
Change ESDHC bus
width and configure DLL
Setup ADMA BD[0]
length to 2K and BD[1]
to 32 bytes
Wait for block gap or Yes Wait for block gap or
Set CMD line low Reached block gap? timeout
timeout
Set ESDHC poll counter Analyze IVT and setup
No ADMA buffer descriptors
to 50ms
to final destination
Wait for acknowledge
token or timeout Continue data trasmition
Acknowledge token Yes Set GPT poll counter to Wait for block gap or
accepted? 1s timeout
No
End
2
SD Boot
11 sample point tuning
Set bottom boundary to
current value
Get start point and
ramping step from fuse
Increase current value
Set the USDHC into with ramping step
tuning mode
Yes
Set the USDHC into Exceed limit?
tuning mode
No
Configure the block
Set delay cell number to
length and block number
current value
Configure the block Send CMD19 to request
length and block number the tuning block
Send CMD19 to request
the tuning block Check the tuning status
Check the tuning status Yes
Tuning passed?
No
No
Exceed limit? No
Tuning passed?
Set upper boundary to
Yes last value
Yes
Increase current value
Tuning failed with ramping step Set delay cell number to
Tuning passed average of bottom and
upper boundary value
4 10
Figure 6-19. Expansion device boot flow (6 of 6)
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6.1.5.5.3 SD, eSD, and SDXC
After the normal boot mode initialization begins, the SD/eSD/SDXC frequency is set to
347.22 kHz. During the identification phase, the SD/eSD/SDXC card voltage validation
is performed. During the voltage validation, the boot code first checks with the high-
voltage settings; if that fails, it checks with the low-voltage settings.
The capacity of the card is also checked. The boot code supports the high-capacity and
low-capacity SD/eSD/SDXC cards after the voltage validation card initialization is done.
During the card initialization, the ROM boot code attempts to set the boot partition for all
SD, eSD, and SDXC devices. If this fails, the boot code assumes that the card is a normal
SD or SDXC card. If it does not fail, the boot code assumes it is an eSD card. After the
initialization phase is over, the boot code switches to a higher frequency (25 MHz in the
normal-speed mode or 50 MHz in the high-speed mode).
For the UHSI cards, the clock speed fuses can be set to SDR50 or SDR104 on USDHC1
ports. This enables the voltage switch process to set the signaling voltage to 1.8 V during
the voltage validation. The bus width is fixed at a 4-bit width and a sampling point tuning
process is needed to calibrate the number of the delay cells. The SD clock speed can be
selected by the 0x490[3:2].
The UHSI calibration start value (MMC_DLL_DLY[6:0]) and the step value can be set
to optimize the sample point tuning process.
If the SD Power Cycle Enable eFuse is 1, the ROM sets the SD_RST pad low, waits for 5
ms, and then sets the SD_RST pad high. If the SD_RST pad is connected to the SD
power supply enable logic on board, it enables the power cycle of the SD card. This may
be crucial in case the SD logic is in the 1.8 V states and must be reset to the 3.3 V states.
6.1.5.5.4 IOMUX configuration for SD/MMC
Table 6-25. SD/MMC IOMUX pin configuration
Signal USDHC1 USDHC2 USDHC3
CD_B GPIO1_IO06.alt5 SD2_CD_B.alt0 I2C2_SCL.alt2
CLK SD1_CLK.alt0 SD2_CLK.alt0 NAND_WE_B.alt2
CMD SD1_CMD.alt0 SD2_CMD.alt0 NAND_WP_B.alt2
DATA0 SD1_DATA0.alt0 SD2_DATA0.alt0 NAND_DATA04.alt2
DATA1 SD1_DATA1.alt0 SD2_DATA1.alt0 NAND_DATA05.alt2
DATA2 SD1_DATA2.alt0 SD2_DATA2.alt0 NAND_DATA06.alt2
DATA3 SD1_DATA3.alt0 SD2_DATA3.alt0 NAND_DATA07.alt2
DATA4 SD1_DATA4.alt0 - NAND_RE_B.alt2
DATA5 SD1_DATA5.alt0 - NAND_CE2_B.alt2
Table continues on the next page...
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-25. SD/MMC IOMUX pin configuration (continued)
Signal USDHC1 USDHC2 USDHC3
DATA6 SD1_DATA6.alt0 - NAND_CE3_B.alt2
DATA7 SD1_DATA7.alt0 - NAND_CLE.alt2
RESET_B SD1_RESET_B.alt0 SD2_RESET_B.alt0 GPIO1_IO09.alt4
VSELECT GPIO1_IO03.alt1 GPIO1_IO04.alt1 GPIO1_IO11.alt4
6.1.5.6 Serial NOR through SPI
The chip supports booting from serial memory devices, such as EEPROM and serial
flash, using the SPI.
These ports are available for serial boot: eCSPI (eCSPI1, eCSPI2, eCSPI3) interfaces.
6.1.5.6.1 Serial(SPI) NOR eFUSE configuration
The boot ROM code determines the type of device using the following parameters, either
provided by the eFUSE settings or sampled on the BOOT_MODE[3:0] pins, during boot.
See this table for details:
Table 6-26. Serial(SPI) NOR boot eFUSE descriptions
Fuse Config Definition Shipped Settings
value
480[31:29] OEM ECSPI port selection 000 000 - eCSPI1
001 - eCSPI2
010 - eCSPI3
480[28] OEM SPI addressing 0 0 - 3 B (24-bit)
1 - 2 B (16-bit)
0x480[25] OEM Recovery boot enable 0 0 – Disabled
1 – Enabled
480[27:26] OEM CS selection (SPI only) 00 00 – CS#0
The ECPSI-1/ECPSI-2/ECPSI-3 block can be used as a boot device using the ECSPI
interface for the serial(SPI) NOR boot. The SPI interface is configured to operate at 12.5
MHz for 3-byte addressing devices and at 3.125 MHz for 2-byte addressing devices.
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The boot ROM copies 4 KB of data from the serial ROM device to the internal RAM.
After checking the Image Vector Table header value (0xD1) from the program image, the
ROM code performs a DCD check. After a successful DCD extraction, the ROM code
extracts the destination pointer and length of image from the Boot Data Structure to be
copied to the RAM device from where the code execution occurs.
NOTE
The Initial 4 KB of program image must contain the IVT, DCD,
and the Boot Data Structures.
6.1.5.6.2 ECSPI boot
The Enhanced Configurable SPI (ECSPI) interface is configured in the master mode and
the EEPROM device is connected to the ECSPI interface as a slave.
The boot ROM code copies 4 KB of data from the EEPROM device to the internal RAM.
If the DCD verification is successful, the ROM code copies the initial 4 KB of data, as
well as the rest of the image extracted from the application image, directly to the
application destination. The ECSPI can read data from the EEPROM using 2- or 3-byte
addressing. Its burst length is 32 B.
When using the SPI as a boot device, the chip supports booting from both the serial
EEPROM and serial flash devices. The boot code determines which device is being used
by reading the appropriate eFUSE/I/O values at the boot (see Table 6-26 for details).
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Start
No Configure CSPI clock
END
divider==success
Yes
EEPROM Read data NO
Set instruction length
address cycle according If read data length>0
to fuses
Yes
If read data length
greater than (burst Assign MSB as read
instruction (0x30)
length-instruction
and other 2/3 byte dest
length)
address in data pointer
Yes
Assign MSB as read
NO
instruction (0x30) and other Send read instruction to
2/3 byte dest address read remaining length
of data
in data pointer
Send read instruction to NO
read burst length of data If read instruction status
is CSPI_SUCCESS
If read instruction status Yes
is CSPI_SUCCESS
Read remaining length
Yes of data and copy to B
Read burst length of destination pointer
data and copy to
destination pointer
NO
Disable CSPI
Increment destination
pointer and reduce
length of data read
END
Figure 6-20. CSPI flow chart
6.1.5.6.2.1 ECSPI IOMUX pin configuration
The contacts assigned to the signals used by the CSPI blocks are shown in this table:
Table 6-27. ECSPI IOMUX pin configuration
Signal eCSPI1 eCSPI2 eCSPI3
MISO ECSPI1_MISO.alt0 ECSPI2_MISO.alt0 UART2_RXD.alt1
Table continues on the next page...
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System Boot
Table 6-27. ECSPI IOMUX pin configuration (continued)
MOSI ECSPI1_MOSI.alt0 ECSPI2_MOSI.alt0 UART1_TXD.alt1
SCLK ECSPI1_SCLK.alt0 ECSPI2_SCLK.alt0 UART1_RXD.alt1
SS0 ECSPI1_SS0.alt0 ECSPI2_SS0.alt0 UART2_TXD.alt1
6.1.6 Boot image
After the initial image (4KB) is loaded, ROM will check the image header’s validity. The
header must meet the following requirements:
• Reserved1 and Reserved2 of IVT must be 0.
• Device Configuration Data (DCD) of IVT must be 0.
• TAG of IVT header must be 0xD120004x
• SPL image's entry, boot_data, self, CSF in IVT need in IRAM_FREE_SPACE or
FlexSPI space
• The address of the image’s entry, boot data and CSF (if CSF is not NULL) must be
out of IVT header range
• Image’s boot_data must be in initial 4k image
• Image target address should be 4 bytes aligned, and the image need in
IRAM_FREE_SPACE range or FlexSPI space. No plugin support.
• The first 4KB of IRAM_FREE_SPACE is used as an initial image buffer. If image
target address is not equal to the base address of IRAM_FREE_SPACE, it should be
out of the first 4KB range of IRAM_FREE_SPACE.
NOTE
The addresses referred in IVT header, boot data or CSF is from
the boot core’s view (A53 core).
6.1.6.1 Primary Image boot
Boot from the device selected by the boot configuration pin or eFuse (Primary Device).
The Primary Image (the image at the beginning of the boot device with the image offset)
will be selected.
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Chapter 6 SNVS, Reset, Fuse, and Boot
6.1.6.2 Secondary Image Boot
If booting from the device selected by the boot configuration pin or eFuse (Primary
Device) fails, ROM will try to boot from the Secondary Image, the offset is relative to the
beginning of the boot device (which is provisioned in the fuse
IMG_CNTN_SET1_OFFSET).
The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows:
• Secondary boot is disabled if fuse value is bigger than 10, n = fuse value bigger than
10.
• n == 0: Offset = 4MB
• n == 2: Offset = 1MB
• Others & n <= 10 : Offset = 1MB*2^n
• For FlexSPI NOR boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7.
6.1.6.3 Primary image offset and IVT offset
ROM supports one single image for all boot devices. The image offset and IVT offset for
the supported boot devices is provided below.
Table 6-28. Primary image offset and IVT offset details
Primary Image Offset IVT Offset
SD 32KB (for GPT) 0
EMMC 0, if the image is in boot partition and 32K if it is in user 0
partition
NAND 0 0
FlexSPI NOR 4KB 0
SPI 0 0
FlexSPI NAND 0 0
NOTE
• Primary Image Offset - The image offset on device against
to the beginning of boot device.
• IVT Offset - The IVT header offset in boot image against
to the beginning of boot image.
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6.1.6.4 Typical image placement in boot device
The beginning of boot device
...
Primary Image Offset
IVT Header Offset
IVT Header
SPL
CSF
(for SPL and its header)
Others
(should be handled by SPL)
...
Secondary Image Offset
IVT Header Offset
IVT Header
SPL
CSF
(for SPL and its header)
Others
(should be handled by SPL)
Figure 6-21. Typical image placement
• For the primary image offset and IVT offset details, please refer to Primary image
offset and IVT offset.
• The secondary image offset is specified by fuses, please refer to the fuse map
chapter.
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Chapter 6 SNVS, Reset, Fuse, and Boot
6.1.7 USB boot
ROM supports both of the USB ports on the chip for boot purposes. Only one port can be
selected as the boot connection. The port that is active first wins the selection.
USB boot in ROM code works as a HID device. ROM takes USB as a normal boot
device. The difference from the SD card here is that the USB is a 'stream' device, which
is the same as eMMC fast boot. ROM must 'read' it one by one byte, and it can not
specify the offset for the reading. This means that the image for USB boot must be
continuous.
USB Serial Download boot can be disabled by fuse.
The USB HID device VID/PID and strings are listed in the following table:
Table 6-29. VID/PID and strings for USB HID device
Descriptor Value
VID 0x1FC9
PID 0x0146
bcdDevice 0x0001
String Descriptor0 bLength : 0x04 (4 bytes)
bDescriptorType : 0x03 (String Descriptor)
Language ID[0] : 0x0409 (English - United States)
String Descriptor1 bLength : 0x3A (58 bytes)
bDescriptorType : 0x03 (String Descriptor)
Language 0x0409 : "NXP SemiConductor Inc "
String Descriptor2 bLength : 0x1E (30 bytes)
bDescriptorType : 0x03 (String Descriptor)
Language 0x0409 : "SE Blank 865"
String Descriptor4 bLength : 0x22 (34 bytes)
bDescriptorType : 0x03 (String Descriptor)
Language 0x0409 : This value depends on chip uuid.
6.1.8 Low-power boot
The ROM supports the low-power boot. If the LPB_BOOT fuses are blown, the chip
checks if there is a low-power condition via the pad. If there is a low-power boot
condition, the ROM applies division factors on the Arm, DDR, AXI, and AHB root
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clocks based on the LPB_BOOT fuses value (see the table below). The polarity of the
low-power boot condition on the pad is set by the BT_LPB_POLARITY fuse (see the
following figure).
Table 6-30. Low-power boot frequencies
LPB_BOOT Boot Frequencies=0 Boot Frequencies=1
00 ARM_A53_CLK_ROOT= 1000 MHz ARM_A53_CLK_ROOT= 500 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 400 MHz MAIN_AXI_CLK_ROOT= 200 MHz
01 ARM_A53_CLK_ROOT= 1000 MHz ARM_A53_CLK_ROOT= 500 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 400 MHz MAIN_AXI_CLK_ROOT= 200 MHz
10 ARM_A53_CLK_ROOT= 500 MHz ARM_A53_CLK_ROOT= 250 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 200 MHz MAIN_AXI_CLK_ROOT= 100 MHz
11 ARM_A53_CLK_ROOT= 250 MHz ARM_A53_CLK_ROOT= 125 MHz
AHB_CLK_ROOT= 133 MHz AHB_CLK_ROOT= 133 MHz
MAIN_AXI_CLK_ROOT= 100 MHz MAIN_AXI_CLK_ROOT= 50 MHz
Start
LPB_BOOT fuses equal Yes
00?
No
No
GPIO1_9 pad equals
LPB_POLARITY fuse?
Yes
Setup post dividers and root
Setup post dividers and root
clock selectors according to
clock selectors according to
Boot Freqiencies and
Boot Freqiencies fuse
LPB_BOOT fuses
Enable PLLs
End
Figure 6-22. Low-power boot flow
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Chapter 6 SNVS, Reset, Fuse, and Boot
6.1.9 SD/MMC manufacture mode
When the internal boot and recover boot (if enabled) failed, the boot goes to the
SD/MMC manufacture mode before the serial download mode. In the manufacture mode,
one bit bus width is used despite of the fuse setting.
In the manufacture mode, the SD or MMC card will be scanned on the uSDHC2. If a card
is detected and a valid boot image is found in the card, the boot image is loaded and
executed. Pad of SD1_CD is used to detect whether a card is inserted or not.
By default, the SD/MMC manufacture mode is enabled. Blow the fuse of the
RECOVERY_SDMMC_BOOT_DIS to disable it.
NOTE
A secondary boot is not supported in the SD/MMC manufacture
mode.
6.1.9.1 Using manufacture mode / serial download mode with eMMC
Manufacture mode is intended to allow a system to boot from a SD/MMC card on a
board with unprogrammed boot media or to upgrade the image on a boot device. For
manufacture mode, the boot ROM assumes if there is a SD/MMC card present indicated
by the uSDHC card detect (CD) signal pulled low, then there is a valid image on the card.
If an unprogrammed eMMC device is connected to the uSDHC port(s) on which
manufacture mode is supported and the CD signal is low, the ROM will attempt
manufacturing mode with the eMMC device, which does not contain a valid image. The
ROM loads the invalid image, and this will cause the ROM code to fail to enter serial
download mode, resulting in a reset of the system by the ROM. To enter serial download
mode in this case, the CD pin should be pulled up so the ROM does not detect a eMMC
device present and will bypass the manufacture mode to enter serial download mode.
6.1.10 High-Assurance Boot (HAB)
The High Assurance Boot (HAB) component of the ROM protects against the potential
threat of attackers modifying the areas of code or data in the programmable memory to
make it behave in an incorrect manner. The HAB also prevents the attempts to gain
access to features which must not be available.
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The integration of the HAB feature with the ROM code ensures that the chip does not
enter an operational state if the existing hardware security blocks detected a condition
that may be a security threat or if the areas of memory deemed to be important were
modified. The HAB uses the RSA digital signatures to enforce these policies.
CAAM
Flash
ROM
HAB
Core Processor
SNVS
RAM
Figure 6-23. Secure boot components
The figure above illustrates the components used during a secure boot using HAB. The
HAB interfaces with the SNVS to make sure that the system security state is as expected.
The HAB also uses the CAAM hardware block to accelerate the SHA-256 message
digest operations performed during the signature verifications and AES-128 operations
for the encrypted boot operations. The HAB also includes a software implementation of
SHA-256 for cases where a hardware accelerator can't be used. The RSA key sizes
supported are 1024, 2048, 3072, and 4096 bits. The RSA signature verification operations
are performed by a software implementation contained in the HAB library. The main
features supported by the HAB are:
• X.509 public key certificate support
• CMS signature format support
• Proprietary encrypted boot support. Note that the encrypted boot depends on the
CAAM hardware module. When the CAAM is disabled (when the
EXPORT_CONTROL fuse is blown), the encrypted boot is not available.
NOTE
NXP provides the reference Code Signing Tool (CST) for key
generation, certificate generation, and code signing for use with
the HAB library. The CST can be found by searching for
"IMX_CST_TOOL_NEW" at http://www.nxp.com.
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Chapter 6 SNVS, Reset, Fuse, and Boot
NOTE
For further details on using the secure boot feature using HAB,
refer to Secure Boot on i.MX Series (AN4581).
6.1.10.1 HAB API vector table addresses
For devices that perform a secure boot, the HAB library may be called by the boot stages
that execute after the ROM code.
NOTE
For additional information on the secure boot including the
HAB API, refer to HABv4 RVT Guidelines and
Recommendations (AN12263).
6.1.11 Boot information for software
To address the requirement that the boot image may need to get the basic boot
information when getting out of the boot process, the boot software information
(Boot_SW_Info) is provisioned by the ROM.
The software must read the ROM address 0x9e8 to get the base address of the
Boot_SW_Info data structure, and parse the Boot_SW_Info content to get the boot
information.
Table 6-31. Boot_SW_Info structure
Offset Byte3 Byte2 Byte1 Byte0
0x0 Reserved Boot Device Type Boot Device Instance Reserved
0x4 Arm core frequency (in Hz)
0x8 AXI bus frequency (in Hz)
0xC DDR frequency (in Hz)
0x10 GPT1 input clock frequency (in Hz)
0x14 Reserved
0x18
0x1C
NOTE
The boot ROM sets the GPT1 in a free-running mode with a
32-kHz input clock.
Boot device type mapping:
• 0x1 - SD card or eSD chip
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Fusemap
• 0x2 - MMC card or eMMC chip
• 0x3 - NAND chip
• 0x4 - FLEXSPI NOR
• 0x6 - ECSPI EEPROM
• 0x8 - FLEXSPI NAND
Boot device instance: The instance index of the boot device, starting from 0.
6.2 Fusemap
6.2.1 Boot Fusemap
The boot mode utilizes 4 dedicated BOOT_MODE (BOOT_MODE[3:0]) pins. The
following section details the various modes and selection of the required boot devices.
Table 6-32. Boot Device Select
Boot Device Select BOOT CODE BOOT_MODE BOOT_MODE BOOT_MODE BOOT_MODE
[3] [2] [1] [0]
Boot from internal fuses 0x00 0 0 0 0
USB Serial Download 0x01 0 0 0 1
USDHC3 (eMMC boot only, SD3 8-bit) 0x02 0 0 1 0
USDHC2 (SD boot only, SD2) 0x03 0 0 1 1
NAND 8-bit single device, 256 pages 0x04 0 1 0 0
NAND 8-bit single device, 512 pages 0x05 0 1 0 1
FlexSPI 3B Read 0x06 0 1 1 0
FlexSPI Hyperflash 3.3V 0x07 0 1 1 1
eCSPI Boot 0x08 1 0 0 0
FLEXSPI Serial NAND 2k page 0x0A 1 0 1 0
FLEXSPI Serial NAND 4k page 0x0B 1 0 1 1
NOTE
Fuses marked as “Reserved” are reserved for NXP internal (and
future) use only. Customers should not attempt to burn these, as
the IC behavior may be unpredictable. The reserved fuses can
be read as either 0 or 1.
Table 6-33. Boot Fusemap
Addr 7 6 5 4 3 2 1 0
0x470[7:0] OVERRIDE_NAND_PG_ OVERRIDE OVERRIDE_FLEXSPI_B FLEXSPI_A FLEXSPI_AUTO_PROBE
PER_BLK_VAL _FLEXSPI_ T_SEL_VAL UTO_PROB _TYPE
BT_SEL E_EN
Table continues on the next page...
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-33. Boot Fusemap (continued)
Addr 7 6 5 4 3 2 1 0
RAWNAND: 0 - Do not 00 - FlexSPI (Hyperflash 0 - Disable 00 - QuadSPI NOR
00 - 32 pages override 1.8V)
1 - Enable 01 - MacronixOctal
01 - 64 pages
1 - Override 01 - FlexSPI (Flash with
10 - 128 pages 10 - MicronOctal
4B READ (1x13 default
11 - 32 pages
supported)) 11 - AdestoOctal
FlexSPI NAND: 10 - Default Octal mode
00 - 64 pages (Micron)
01 - 128 pages
11 - Default Octal mode
10 - 256 pages
(Macronix)
11 - 32 pages
0x470[15:8] BOOT_MODE_FUSES OVERRIDE OVERRIDE_USDHC_BT OVERRIDE
_USDHC_B _SEL_VAL _NAND_PG
Boot Rom will retrieve boot mode from these fuses
T_SEL _PER_BLK
instead of BOOT_MODE pins if: 00 - uSDHC1 SD
0 - Do not 0 - Do not
(BOOT_MODE_PINS=0 or 01 - uSDHC1 eMMC
override override
FORCE_BT_FROM_FUSE = 1) and
10 - uSDHC2 eMMC
BT_FUSE_SEL=1 1 - Override 1 - Override
11 - uSDHC3 SD
0x480[7:0] Reserved FLEXSPI_DUMMY_CYCLE_SEL FLEXSPI_FEQ_SEL
0 – Dummy cycle is auto-probed 000 - 100 MHz
Other values – Actual dummy cycles for Read 001 - 133 MHz
command
010 - 166 MHz
011 - 200 MHz
100 - 80 MHz
101 - 20 MHz
0x480[15:8] BT_LPB (Core/DDR/Bus) BT_LPB_P ICACHE_DI Reserved WDOG_EN BT_FREQ_ DCACHE_D
OLARITY S SEL (Arm/ IS
'00'/'01' - LPB Disable '0' -
(GPIO DDR)
L1 I-Cache Disabled Disable L1
'10' - Div by 2 polarity)
DISABLE 0 - 800 / and L2 D-
'1' - Enabled
'11' - Div by 4 800 MHz Cache
0 - L1 I
Cache is 1 - 400 /
enabled by 400 MHz
the ROM
during the
boot.
1 - L1 I
Cache is
disabled by
the ROM
during the
boot.
0x480[23:16] NOC_ID_R Reserved SDP_DISA FORCE_BT FLEXSPI_HOLD_TIME_ WDOG_TIMEOUT_SELE
EMAP_BYP BLE _FROM_FU SEL CT
ASS SE
Disable 00 - 500us 00 - 2.0s
USB serial
01 - 1ms 01 - 1.5s
download
10 - 3ms 10 - 1.0s
11 - 10ms 11 - 0.5s
Table continues on the next page...
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Fusemap
Table 6-33. Boot Fusemap (continued)
Addr 7 6 5 4 3 2 1 0
Boot from
programme
d fuses, not
Boot Mode
Pins
0x480[31:24] ECSPI_PORT_SEL ECSPI_AD ECSPI_CS_SEL (SPI RECOVER_ DCACHE_B
DR_SEL only) ECSPI_BO YPASS_DI
000 - eCSPI1
OT_EN S
0 - 3-bytes 00 - CS#0 (default)
001 - eCSPI2
(24-bit) '0' -
01 - CS#1
010 - eCSPI3 Disabled
1 - 2-bytes
10 - CS#2
(16-bit) '1' - Enabled
11 - CS#3
0x490[7:0] USDHC_P EMMC_FA SDMMC_BUS_WIDTH SD_SPEED: USDHC_V USDHC_M
WR_EN ST_BT OL_SEL FG_VOL_S
00 - 8-bit 00 - Normal/SDR12
EL
0 - No 0 - Regular For Normal
01 - 4-bit 01 - High/SDR25
power cycle Boot Mode For Mfg
1 - Fast
10 - 8-bit DDR (MMC 4.4) 10 - SDR50 IO Voltage Mode IO
1 - Enabled Boot
Voltage
11 - 4-bit DDR (MMC 4.4) 11 - SDR104 0 - 3.3V
0 - 3.3V
EMMC_SPEED: 1 - 1.8V
1 - 1.8V
00 - Normal
01 - High
0x490[15:8] USDHC_DL SDMMC_DLL_DLY[6:0]
L_SEL
Delay target for USDHC DLL, it is applied to slave mode target delay or override mode target
0 - DLL delay depends on DLL Override fuse bit value.
Slave Mode
1 - DLL
Override
Mode
0x490[23:16] RECOVER IMG_CNTN_SET1_OFFSET USDHC_PA Reserved USDHC_DL
Y_SDMMC D_SION_E L_EN
_BOOT_DI N
0 - Disable
S
0 - Disable DLL for SD/
0 - Enable eMMC
1 - Enable
1 - Disable 1 - Enable
DLL for SD/
eMMC
0x490[31:24] USDHC_OVRD_PAD_SETTING_LOW8 [7:0]
0x4A0[7:0] SD_CALI_STEP USDHC_PWR_INTERVA USDHC_P USDHC_P USDHC_O EMMC_FA
L WR_DELAY WR_POLA VRD_PAD_ ST_BT_AC
'00' - 1
RITY SETTING_ K
00 - 20ms 0 - 5ms
UP1
0 - Low 0 - Boot Ack
01 - 10ms 1 - 2.5ms
Disabled
1 - High
10 - 5ms
1 - Boot Ack
11 - 2.5 Enabled
0x4A0[15:8] BT_TOGGL NAND_FCB_SERCH_CO NAND_TG_PREAMBLE_RD_LATENCY NAND_RST
E_MODE UNT _TIME
Table continues on the next page...
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-33. Boot Fusemap (continued)
Addr 7 6 5 4 3 2 1 0
00 - 2 (Toggle Mode 33MHz Preamble Delay, Read
Latency)
01 - 2
'000' - 16 GPMICLK cycles.
10 - 4
'001' - 1 GPMICLK cycles.
11 - 8
'010' - 2 GPMICLK cycles.
'011' - 3 GPMICLK cycles.
'100' - 4 GPMICLK cycles.
'101' - 5 GPMICLK cycles.
'110' - 6 GPMICLK cycles.
'111' - 7 GPMICLK cycles.
'1111'- 15 GPMICLK cycles.
0x4A0[23:16] Reserved
0x4A0[31:24] NAND_OVERRIDE_PAD_SETTING[7:0]
0x4B0[7:0] Reserved NAND_GPMI_DDR_DLL_VAL (GPMI Read DDR Reserved NAND_CS_NUM (Nand
DLL Target Value) Number Of Devices)
0000 - 7 00 - 1
0001 - 1 01 - 2
0111 - 0 10 - 4
1111 - 15 11 - Reserved
0x4B0[15:8] NAND_READ_RETRY_SEQ_ID[3:0]1 NAND_ROW_ADDR_BY Reserved
TES
0000 - Do not use read retry (RR) sequence
embedded in ROM 00 - 3
0001 - Micron 20nm RR sequence 01 - 2
0010 - Kioxia A19nm RR sequence 10 - 4
0011 - Kioxia 19nm RR sequence 11 - 5
0100 - SanDisk 19nm RR sequence
0101 - SanDisk 1ynmRR sequence
0110 - SK Hynix 20nm A Die RR sequence
0111 - SK Hynix 26nm RR sequence
Others - Reserved
0x4B0[31:16] Reserved
1. Testing has been performed on select memory devices. Please contact your NXP representative for more details.
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Fusemap
6.2.2 Lock Fusemap
Table 6-34 describes the functions of various lock fuses.
Table 6-34. Lock Fuses
Addr 7 6 5 4 3 2 1 0
0x400[7:0] Reserved
0x400[15:8] MAC_ADDR_LOCK USB_ID_LOCK Reserved
1x - OP 1x - OP
x1 - WP x1 - WP
0x400[23:16] GP2_LOCK GP1_LOCK Reserved
1x - OP 1x - OP
x1 - WP x1 - WP
0x400[31:24] Reserved
0x410[7:0] Reserved GP4_LOCK Reserved
1x – OP
x1 – WP
0x410[15:8] GP8_LOCK GP7_LOCK GP6_LOCK Reserved
1x – OP 1x – OP 1x – OP
x1 – WP x1 – WP x1 – WP
0x410[23:16] Reserved GP9_LOCK
1x – OP
x1 – WP
0x410[31:24] Reserved
6.2.3 Fusemap Descriptions Table
NOTE
Definitions for fuse settings are as follows:
• Unlock - The controlled field can be read, sensed, burned,
or overridden in the corresponding OCOTP shadow
register.
• Lock - The controlled field cannot be read, burned, or
overridden.
• Override Protect (OP) - The controlled field cannot
overwrite the corresponding OCOTP shadow register
content. The controlled field can sense or burn fuses, and
read the corresponding OCOTP shadow register.
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Chapter 6 SNVS, Reset, Fuse, and Boot
• Write Protect (WP) - The controlled field cannot burn a
fuse. The controlled field can be sensed (fuse), read or
overridden in the corresponding OCOTP shadow register.
• OP + WP - The controlled field cannot burn (fuses) or
overwrite the corresponding OCOTP shadow register. The
controlled field can only sense (fuses) or read the
corresponding OCOTP shadow register.
NOTE
For security related fuses, please refer to the chip's Security
Reference Manual.
Table 6-35. Fusemap Descriptions
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x400[11:0] Reserved 12 Reserved Reserved Reserved
0x400[13:12] USB_ID_LOCK 2 Lock for USB_PID and 00 - Unlock OCOTP
USB_VID fuses.
10 - OP
01 - WP
11 - OP + WP
0x400[15:14] MAC_ADDR_LOCK 2 Lock for MAC_ADDR fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[19:16] Reserved 4 Reserved Reserved Reserved
0x400[21:20] GP1_LOCK 2 Lock for GP1 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[23:22] GP2_LOCK 2 Lock for GP2 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x400[31:24] Reserved 8 Reserved Reserved Reserved
0x410[3:0] Reserved 4 Reserved Reserved Reserved
0x410[5:4] GP4_LOCK 2 Lock for GP4 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x410[9:6] Reserved 4 Reserved Reserved Reserved
0x410[11:10] GP6_LOCK 2 Lock for GP6 fuses. 00 - Unlock OCOTP
Table continues on the next page...
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Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
10 - OP
01 - WP
11 - OP + WP
0x410[13:12] GP7_LOCK 2 Lock for GP7 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x410[15:14] GP8_LOCK 2 Lock for GP8 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x410[17:16] GP9_LOCK 2 Lock for GP9 fuses. 00 - Unlock OCOTP
10 - OP
01 - WP
11 - OP + WP
0x410[31:18] Reserved 14 Reserved Reserved Reserved
0x420[10:0] UNIQUE_ID[42:0] 43 Unique ID - SJC, SW
0x430[15:11] UNIQUE_ID[47:43] 5 Unique ID - SJC, SW
0x430[23:16] UNIQUE_ID[55:48] 8 Unique ID - SJC, SW
0x430[31:24] UNIQUE_ID[63:56] 8 Unique ID - SJC, SW
0x440[7:0] Reserved 8 Reserved Reserved Reserved
0x440[13:8] SPEED_GRADING[ 6 Burned by tester program, SPE SPE MHz P/N PROD / SW
5:0] for indicating IC core speed. ED_ ED_ Cod
(Hot burn may not be used). GRA GRA e
DIN DIN
G[5: G[3:
4] 0]
xx 0000 2300 23
xx 0001 2200 22
xx 0010 2100 21
xx 0011 2000 20
xx 0100 1900 19
xx 0101 1800 18
xx 0110 1700 17
xx 0111 1600 16
xx 1000 1500 15
xx 1001 1400 14
Table continues on the next
page...
Table continues on the next page...
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
SPE SPE MHz P/N
ED_ ED_ Cod
GRA GRA e
DIN DIN
G[5: G[3:
4] 0]
xx 1010 1300 13
xx 1011 1200 12
xx 1100 1100 11
xx 1101 1000 10
xx 1110 900 09
xx 1111 800 08
0x440[15:14] Reserved 2 Reserved Reserved Reserved
0x440[16] Reserved 1 Reserved Reserved Reserved
0x440[17] Reserved 1 Reserved Reserved Reserved
0x440[19:18] Reserved 2 Reserved Reserved Reserved
0x440[20] Reserved 1 Reserved Reserved Reserved
0x440[21] M7_DISABLE 1 Disable M7 Core. 0 - enabled M7
1 - disabled
0x440[23:22] Reserved 2 Reserved Reserved Reserved
0x440[24] VPU_G1_DISABLE 1 Disable G1 Decoder in VPU 0 - enabled VPU
1 - disabled
0x440[25] VPU_G2_DISABLE 1 Disable G2 Decoder in VPU 0 - enabled VPU
1 - disabled
0x440[27:26] Reserved 2 Reserved Reserved Reserved
0x440[28] CAN_DISABLE 1 Disable CAN functionality 0 - enabled CAN
1 - disabled (Disables both
CAN and CAN-FD
functionality)
0x440[29] CAN_FD_DISABLE 1 Disable CAN-FD 0 - enabled CAN
functionality
1 - disabled (Disables CAN-
FD, but CAN function is
operational if CAN_DISABLE
fuse is enabled)
0x440[30] VPU_VC8000E_DI 1 Disable VC8000E Encoder 0 - enabled VPU
SABLE in VPU
1 - disabled
0x440[31] Reserved 1 Reserved Reserved Reserved
0x450[0] IMG_ISP1_DISABL 1 Disable IMAGING_ISP1 IP 0 - enabled ISP
E
1 - disabled
Table continues on the next page...
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Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x450[1] IMG_ISP2_DISABL 1 Disable IMAGING_ISP2 IP 0 - enabled ISP
E
1 - disabled
0x450[2] IMG_DEWARP_DI 1 Disable IMAGING_DEWARP 0 - enabled DEWARP
SABLE IP
1 - disabled
0x450[3] NPU_DISABLE 1 Disable NPU IP 0 - enabled NPU
1 - disabled
0x450[4] AUDIO_PROCESS 1 Disable HiFi4 DSP IP 0 - enabled AUDIO
OR_DISABLE
1 - disabled
0x450[5] ASRC_DISABLE 1 Disable Audio ASRC IP 0 - enabled ASRC
1 - disabled
0x450[6] GPU2D_DISABLE 1 Disable GPU 2D IP 0 - enabled GPU
1 - disabled
0x450[7] GPU3D_DISABLE 1 Disable GPU 3D IP. 0 - enabled GPU
1 - disabled
0x450[8] USB1_DISABLE 1 Disable USB1 Controller IP. 0 - enabled USB
1 - disabled
0x450[9] USB2_DISABLE 1 Disable USB2 Controller IP. 0 - enabled USB
1 - disabled
0x450[10] Reserved 1 Reserved Reserved Reserved
0x450[11] PCIE1_DISABLE 1 Disable PCIe-1 IP. 0 - enabled PCIE
1 - disabled
0x450[12] Reserved 1 Reserved Reserved Reserved
0x450[13] ENET1_DISABLE 1 Disable ENET-1 IP. 0 - enabled ENET
1 - disabled
0x450[14] ENET2_DISABLE 1 Disable ENET-2 IP. 0 - enabled ENET
1 - disabled
0x450[15] MIPI_CSI1_DISABL 1 Disable MIPI CSI-1 IP. 0 - enabled MIPI CSI
E
1 - disabled
0x450[16] MIPI_CSI2_DISABL 1 Disable MIPI CSI-2 IP. 0 - enabled MIPI CSI
E
1 - disabled
0x450[17] MIPI_DSI1_DISABL 1 Disable MIPI DSI-1 IP. 0 - enabled MIPI DSI
E
1 - disabled
0x450[18] Reserved 1 Reserved Reserved Reserved
0x450[19] LVDS1_DISABLE 1 Disable LVDS-1 IP 0 - enabled LVDS
1 - disabled
0x450[20] LVDS2_DISABLE 1 Disable LVDS-2 IP 0 - enabled LVDS
1 - disabled
Table continues on the next page...
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x450[21] Reserved 1 Reserved Reserved Reserved
0x450[23:22] Reserved 2 Reserved Reserved Reserved
0x450[24] Reserved 1 Reserved Reserved Reserved
0x450[28:25] Reserved 4 Reserved Reserved Reserved
0x450[29] Reserved 1 Reserved Reserved Reserved
0x450[30] EARC_RX_DISABL 1 Disable eARC-RX IP 0 - enabled EARC
E
1 - disabled
0x450[31] Reserved 1 Reserved Reserved Reserved
0x460[6:0] Reserved 7 Reserved Reserved Reserved
0x460[31:7] GP4 25 General Purpose fuse - SW
register #4
0x470[1:0] FLEXSPI_AUTO_P 2 FLEXSPI Flash AutoProbe 00 - QuadSPI NOR SW(ROM)
ROBE_TYPE Type
01 - MacronixOctal
10 - MicronOctal
11 - AdestoOctal
0x470[2] FLEXSPI_AUTO_P 1 FLEXSPI Flash AutoProbe 0 - Disable SW(ROM)
ROBE_EN Enable
1 - Enable
0x470[4:3] OVERRIDE_FLEXS 2 FlexSPI Boot Selection 00 - FlexSPI (Hyperflash SW(ROM)
PI_BT_SEL_VAL Override Value 1.8V)
01 - FlexSPI (Flash with 4B
READ(1x13) default
supported)
10 - Default Octal mode
(Micron)
11 - Default Octal mode
(Macronix)
0x470[5] OVERRIDE_FLEXS 1 Override FlexSPI Boot 0 - Do not override SW(ROM)
PI_BT_SEL Selection
1 - Override
0x470[7:6] OVERRIDE_NAND 2 Pages in block override RAWNAND: SW(ROM)
_PG_PER_BLK_VA value • 00 - 32 pages
L • 01 - 64 pages
• 10 - 128 pages
• 11 - 32 pages
FlexSPI NAND:
• 00 - 64 pages
• 01 - 128 pages
• 10 - 256 pages
• 11 - 32 pages
0x470[8] OVERRIDE_NAND 1 Override pages in block 0 - Do not override SW(ROM)
_PG_PER_BLK
1 - Override
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Fusemap
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x470[10:9] OVERRIDE_USDH 2 USDHC boot Select override 00 - uSDHC1 SD SW(ROM)
C_BT_SEL_VAL value
01 - uSDHC1 eMMC
10 - uSDHC2 eMMC
11 - uSDHC3 SD
0x470[11] OVERRIDE_USDH 1 Override USDHC boot 0 - Do not override SW(ROM)
C_BT_SEL selection
1 - Override
0x470[15:12] BOOT_MODE_FUS 4 Boot Rom will retrieve boot Please refer to Table 6-32 SW(ROM)
ES mode from these fuses
instead of BOOT_MODE
pins if:
(BOOT_MODE_PINS=0 or
FORCE_BT_FROM_FUSE =
1) and BT_FUSE_SEL=1
0x470[24:16] Reserved 9 Reserved Reserved Reserved
0x470[27:25] Reserved 3 Reserved Reserved Reserved
0x470[28] BT_FUSE_SEL 1 In the Boot From Fuse mode If Boot From Fuse mode SRC SW(ROM)
(BOOT_MODE[3:0] = (BOOT_MODE[3:0] = 0000b)
0000b), the BT_FUSE_SEL or FORCE_BT_FROM_F
fuse indicates whether the USE=1 :
bit configuration eFuses are
0—The BOOT configuration
programmed.
eFuses are not programmed
yet. The boot flow jumps to
the serial downloader.
1—The BOOT configuration
eFuses are programmed.
The regular boot flow is
performed.
0x470[29] FORCE_COLD_BO 1 Force cold boot when core Fuse Function: SRC SW(ROM)
OT(SBMR) comes out of reset.
0 – Default behavior,
Reflected in SBMR register
allowing a fast recovery from
of SRC.
low power modes. That is,
the ROM is allowed to jump
to the address previously
programmed in the SRC
persistent register.
1 – Fast recovery path in the
ROM is not allowed and a
cold boot is always
performed. Customers
wanting a higher level of
security should burn this
fuse.
0x470[31:30] Reserved 2 Reserved Reserved Reserved
0x480[2:0] FLEXSPI_FEQ_SE 3 FLEXSPI Flash Frequency 000 - 100 MHz SW(ROM)
L
001 - 133 MHz
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
010 - 166 MHz
011 - 200 MHz
100 - 80 MHz
101 - 20 MHz
0x480[6:3] FLEXSPI_DUMMY_ 4 FLEXSPI Flash Dummy 0 – Dummy cycle is auto- SW(ROM)
CYCLE_SEL Cycle probed
Other values – Actual
dummy cycles for Read
command
0x480[7] Reserved 1 Reserved Reserved Reserved
0x480[8] DCACHE_DIS 1 Disable L1 and L2 Dcache SW(ROM)
0x480[9] BT_FREQ_SEL 1 Boot frequency selection BT_FREQ_SEL (Arm/DDR) SW(ROM)
0 - 800 / 800 MHz
1 - 400 / 400 MHz
0x480[10] WDOG_EN 1 Watchdog reset counter 0 - Disabled SW(ROM)
enable
1 - Enabled
0x480[11] Reserved 1 Reserved Reserved Reserved
0x480[12] ICACHE_DIS 1 L1 I-Cache DISABLE 0 - L1 I Cache is enabled by SW(ROM)
the ROM during the boot.
1 - L1 I Cache is disabled by
the ROM during the boot.
0x480[13] BT_LPB_POLARIT 1 USB Low-Power Boot GPIO 0 - Low on the GPIO pad SW(ROM)
Y polarity indicates the low power
condition.
1 - High on the GPIO pad
indicates the low power
condition.
0x480[14:15] BT_LPB 2 USB Low-Power Boot 0x - LPB Disable SW(ROM)
10 - Div by 2
11 - Div by 4
0x480[17:16] WDOG_TIMEOUT_ 2 Watchdog timeout select 00 - 2.0s SW(ROM)
SELECT
01 - 1.5s
10 - 1.0s
11 - 0.5s
0x480[19:18] FLEXSPI_HOLD_TI 2 Hold time before read from 00 - 500us SW(ROM)
ME_SEL device
01 - 1ms
10 - 3ms
11 - 10ms
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Fusemap
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x480[20] FORCE_BT_FROM 1 Boot from programmed 1 - boot flow is controlled by SW(ROM)
_FUSE fuses, not Boot Mode Pins. the BT_FUSE_SEL fuse
value
0x480[21] SDP_DISABLE 1 Disable USB serial download SW(ROM)
0x480[22] Reserved 1 Reserved Reserved Reserved
0x480[23] NOC_ID_REMAP_ 1 NOC_ID_REMAP_BYPASS SW(ROM)
BYPASS
0x480[24] DCACHE_BYPASS 1 DCACHE_BYPASS_DIS SW(ROM)
_DIS
0x480[25] RECOVER_ECSPI 1 OEM Recovery boot enable 0 - Disabled SW(ROM)
_BOOT_EN
1 - Enabled
0x480[27:26] ECSPI_CS_SEL 2 CS selection (SPI only) 00 - CS#0 (default) SW(ROM)
01 - CS#1
10 - CS#2
11 - CS#3
0x480[28] ECSPI_ADDR_SEL 1 SPI addressing 0 - 3-bytes (24-bit) SW(ROM)
1 - 2-bytes (16-bit)
0x480[31:29] ECSPI_PORT_SEL 3 ECSPI port selection 000 - eCSPI1 SW(ROM)
001 - eCSPI2
010 - eCSPI3
0x490[0] USDHC_MFG_VOL 1 For Mfg Mode IO Voltage 0 - 3.3V SW(ROM)
_SEL
1 - 1.8V
0x490[1] USDHC_VOL_SEL 1 For Normal Boot Mode IO 0 - 3.3V SW(ROM)
Voltage
1 - 1.8V
0x490[3:2] SD_SPEED 2 Speed mode SD_SPEED: SW(ROM)
• 00 - Normal/SDR12
• 01 - High/SDR25
• 10 - SDR50
• 11 - SDR104
EMMC_SPEED:
• 00 - Normal
• 01 - High
0x490[5:4] SDMMC_BUS_WID 2 SDMMC Bus width 00 - 8-bit SW(ROM)
TH
01 - 4-bit
10 - 8-bit DDR (MMC 4.4)
11 - 4-bit DDR (MMC 4.4)
0x490[6] EMMC_FAST_BT 1 Fast boot support 0 - Regular SW(ROM)
1 - Fast Boot
0x490[7] USDHC_PWR_EN 1 SD power cycle enable/ 0 - No power cycle SW(ROM)
eMMC reset enable
1 - Enabled
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x490[14:8] SDMMC_DLL_DLY[ 7 SD/MMC DLL DLY config Delay target for USDHC SW(ROM)
6:0] DLL. It is applied to slave
mode target delay or
override mode target delay.
Depends on DLL Override
fuse bit value.
0x490[15] USDHC_DLL_SEL 1 USDHC DLL override enable 0 - DLL Slave Mode SW(ROM)
1 - DLL Override Mode
0x490[16] USDHC_DLL_EN 1 USDHC DLL enable 0 - Disable DLL for SD/ SW(ROM)
eMMC
1 - Enable DLL for SD/
eMMC
0x490[17] Reserved 1 Reserved Reserved SW(ROM)
0x490[18] USDHC_PAD_SIO 1 USDHC IOMUX SION bit 0 - Disable SW(ROM)
N_EN enable
1 - Enable
0x490[22:19] IMG_CNTN_SET1_ 4 Secondary Image Boot • Secondary boot is SW(ROM)
OFFSET Offset disabled if fuse value
is bigger than 10, n =
fuse value bigger than
10.
• n == 0: Offset = 4MB
• n == 2: Offset = 1MB
• Others & n <= 10 :
Offset = 1MB*2^n
• For FlexSPI NOR
boot, the valid values
are: 0, 1, 2, 3, 4, 5, 6,
and 7.
0x490[23] RECOVERY_SDM 1 Disable SDMMC 0 - Enable SW(ROM)
MC_BOOT_DIS manufacture mode
1 - Disable
0x490[31:24] USDHC_OVRD_PA 8 USDHC pad setting override Override pad settings SW(ROM)
D_SETTING_LOW
8[7:0]
0x4A0[0] EMMC_FAST_BT_ 1 Fast boot acknowledge 0 - Boot Ack Disabled SW(ROM)
ACK enable
1 - Boot Ack Enabled
0x4A0[1] USDHC_OVRD_PA 1 USDHC_OVRD_PAD_SETT SW(ROM)
D_SETTING_UP1 ING_UP1
0x4A0[2] USDHC_PWR_POL 1 USDHC power-off polarity 0 - Low SW(ROM)
ARITY selection
1 - High
0x4A0[3] USDHC_PWR_DEL 1 USDHC power cycle delay 0 - 5ms SW(ROM)
AY selection
1 - 2.5ms
0x4A0[5:4] USDHC_PWR_INT 2 USDHC power cycle interval 00 - 20ms SW(ROM)
ERVAL
01 - 10ms
10 - 5ms
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Fusemap
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
11 - 2.5ms
0x4A0[7:6] SD_CALI_STEP 2 SD_CALI_STEP 00 - 1 SW(ROM)
Others - N/A
0x4A0[8] NAND_RST_TIME 1 NAND reset time SW(ROM)
0x4A0[12:9] NAND_TG_PREAM 4 Toggle Mode 33MHz 000 - 16 GPMICLK cycles. SW(ROM)
BLE_RD_LATENC Preamble Delay, Read
001 - 1 GPMICLK cycles.
Y Latency.
010 - 2 GPMICLK cycles.
011 - 3 GPMICLK cycles.
100 - 4 GPMICLK cycles.
101 - 5 GPMICLK cycles.
110 - 6 GPMICLK cycles.
111 - 7 GPMICLK cycles.
1111 - 15 GPMICLK cycles.
0x4A0[14:13] NAND_FCB_SERC 2 Boot search count 00 - 2 SW(ROM)
H_COUNT
01 - 2
10 - 4
11 - 8
0x4A0[15] BT_TOGGLE_MOD 1 Boot toggle mode 0 - raw NAND SW(ROM)
E
1 - toggle mode NAND
0x4A0[23:16] Reserved 8 Reserved Reserved SW(ROM)
0x4A0[31:24] NAND_OVERRIDE 8 NAND_OVERRIDE_PAD_S NAND pad settings value SW(ROM)
_PAD_SETTING[7: ETTING[7:0]
0]
0x4B0[1:0] NAND_CS_NUM 2 Nand Number Of Devices 00 - 1 SW(ROM)
01 - 2
10 - 4
11 - Reserved
0x4B0[2] Reserved 1 Reserved Reserved SW(ROM)
0x4B0[6:3] NAND_GPMI_DDR 4 GPMI Read DDR DLL 0000 - 7 SW(ROM)
_DLL_VAL Target Value
0001 - 1
0111 - 0
1111 - 15
0x4B0[9:7] Reserved 3 Reserved Reserved SW(ROM)
0x4B0[11:10] NAND_ROW_ADD 2 Row address cycles 00 - 3 SW(ROM)
R_BYTES
01 - 2
10 - 4
11 - 5
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Chapter 6 SNVS, Reset, Fuse, and Boot
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0x4B0[15:12] NAND_READ_RET 4 NAND_READ_RETRY_SEQ 0000 - don't use read SW(ROM)
RY_SEQ_ID[3:0] _ID1 retry(RR) sequence
embedded in ROM
0001 - Micron 20nm RR
sequence
0010 - Kioxia A19nm RR
sequence
0011 - Kioxia 19nm RR
sequence
0100 - SanDisk 19nm RR
sequence
0101 - SanDisk 1ynmRR
sequence
0110 - SK Hynix 20nm A Die
RR sequence
0111 - SK Hynix 26nm RR
sequence
Others - Reserved
0x4B0[31:16] Reserved 16 Reserved Reserved Reserved
0x4C0 - Reserved 704 Reserved Reserved Reserved
0x610
0x620[15:0] USB_VID[31:0] 16 USB VID - SW
0x620[31:16] USB_PID[31:0] 16 USB PID - SW
0x630[31:0] Reserved 32 Reserved Reserved Reserved
0x640[15:0] MAC_0_ADDR[47:0 48 Reserved for customers/SW - SW
]
0x650[31:16] MAC_1_ADDR[47:0 48 Reserved for customers/SW - SW
]
0x670[31:0] Reserved 32 Reserved Reserved >Reserved
0x680 - Reserved 256 Reserved Reserved Reserved
0x6F0
0x700 - Reserved 256 Reserved Reserved Reserved
0x770
0x780 - GP1[63:0] 64 General Purpose fuse - SW
0x790 register #1
0x7A0 - GP2[63:0] 64 General Purpose fuse - SW
0x7B0 register #2
0x7C0[31:0] Reserved 32 Reserved Reserved Reserved
0x7D0 - Reserved 64 Reserved Reserved Reserved
0x7E0
0x7F0 - Reserved 3104 Reserved Reserved Reserved
0xDF0
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On-Chip OTP Controller (OCOTP_CTRL)
Table 6-35. Fusemap Descriptions (continued)
Fuse Fuses Name Numbe Fuses Function Setting Used by
Address r of
Fuses
0xE00 - UNIQUE_ID[127:64 64 Unique ID - SJC, SW
0xE10 ]
0xE20 - Reserved 64 Reserved Reserved Reserved
0xE30
0xE40 - GP6[127:0] 128 General Purpose fuse - PROD / SW
0xE70 register #6
0xE80 - GP7[127:0] 128 General Purpose fuse - PROD / SW
0xEB0 register #7
0xEC0 - GP8[127:0] 128 General Purpose fuse - PROD / SW
0xEF0 register #8
0xF00 - GP9[127:0] 128 General Purpose fuse - PROD / SW
0xF30 register #9
0xF40 - Reserved - Reserved Reserved Reserved
0x1BF0
1. Testing has been performed on select memory devices. Please contact your NXP representative for more details.
6.3 On-Chip OTP Controller (OCOTP_CTRL)
6.3.1 Overview
This section contains information describing the On-Chip OTP controller
(OCOTP_CTRL) along with details about the block functionality and implementation.
In this document, the words "eFuse" and "OTP" are interchangeable. OCOTP refers to
the hardware block itself.
6.3.1.1 Block Diagram
The system level block diagram for OCOTP is provided below.
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OCOTP_CTRL
APB Interface
IP bus
Ocotp control register ip2apb
HW Capability Bus Other
Blocks
Shadow Regs To JTAG
HWV_REG Bus
Blocks
STICKY_REG Bus Other
Blocks
Ocotp Controller/State Machine
OTP
Memory
Figure 6-24. OCOTP System Level Block Diagram
6.3.1.2 Features
The OCOTP provides the following features :
• 32-bit word restricted program and read to
• Loading and housing of eFuse content into shadow registers
• Memory-mapped (restricted) access to shadow registers
• Provides program-protect and read-protect of eFuse
• Provides override and read protection of shadow register
6.3.2 Functional Description
6.3.2.1 Operations
The IP bus interface of the OCOTP has the following functions.
• Configure control registers for programming and reading all the fuse words
• Override and read shadow registers
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On-Chip OTP Controller (OCOTP_CTRL)
OCOTP configuration for programs and reads are performed on 32-bit words for software
(SW) convenience. For writes, the 32-bit word reflects the "write-mask". Bit fields with 0
will not be programmed and bit fields with 1 will be programmed.
6.3.2.1.1 Shadow Register Reload
All fuse words in efuse box are shadowed. This means that at reset, fuse values are read
and then copied into memory-mapped shadow registers. If fuses are subsequently
programmed, the shadow registers should be reloaded to keep them coherent with the
fuse bank arrays.
The "reload shadows" feature allows the user to force a reload of the shadow registers
without having to reset the device. To force a reload, complete the following steps:
1. Set the TIMING[STROBE_READ] field value appropriately.
2. Set the TIMING[RELAX] field value appropriately.
3. Check that CTRL[BUSY] and CTRL[ERROR] are clear. Overlapped accesses are
not supported by the controller. Any pending write, read, or reload must be
completed before a new access can be requested.
4. Set the CTRL[RELOAD_SHADOWS] bit. OCOTP will read all the fuses one by one
and put it into corresponding shadow register.
5. Wait for CTRL[BUSY] and CTRL[RELOAD_SHADOWS] to be cleared by the
controller.
The controller will automatically clear the CTRL[RELOAD_SHADOWS] bit after the
successful completion of the operation.
6.3.2.1.2 Fuse and Shadow Register Read
All shadow registers are always readable through the IPS bus except some secret key
regions. When their corresponding fuse lock bits are set, the shadow registers also
become read locked. After read locking, reading from these registers will return
0xBADABADA.
In addition, CTRL[ERROR] will be set. It must be cleared by software before any new
write, read, or reload access can be issued. Subsequent reads to unlocked shadow
registers will still work successfully.
To read fuse words directly from the fusebox instead of the shadow registers, complete
the following steps:
1. Program TIMING[STROBE_READ] and TIMING[RELAX] fields with timing
values to match the current frequency of the ipg_clk. OTP read will work at
maximum bus frequencies as long as the TIMING parameters are set correctly.
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Chapter 6 SNVS, Reset, Fuse, and Boot
2. Check that CTRL[BUSY] and CTRL[ERROR] are clear. Overlapped accesses are
not supported by the controller. Any pending write, read, or reload must be
completed before a read access can be requested.
3. Write the requested fuse address to CTRL[ADDR].
4. Set READ_CTRL[READ_FUSE] to start the read operation.
5. Wait for the controller to clear CTRL[BUSY]. A read request to a protected or
locked region will result in no OTP access and no setting of CTRL[BUSY]. In
addition, CTRL[ERROR] will be set. It must be cleared by software before any new
access can be issued.
6. Read READ_FUSE_DATA to get fuse word value. READ_FUSE_DATA will be
0xBADABADA when CTRL[ERROR] is set.
6.3.2.1.3 Fuse and Shadow Register Writes
Shadow register bits can be overridden by software until the corresponding fuse lock bit
for the region is set. When the lock shadow bit is set, the shadow registers for that lock
region become write locked. The LOCKn register also has no overwrite or fuse lock bits,
but it is always read-only.
In order to avoid "rogue" code performing erroneous writes to OTP, a special unlocking
sequence is required for writes to the fuse banks. To program fuse bank complete the
following steps:
1. Program the following fields with timing values to match the frequency of ipg_clk:
• TIMING[STROBE_PROG]
• TIMING[RELAX]
OTP writes will work at maximum bus frequencies as long as the TIMING
parameters are set correctly.
2. Check that CTRL[BUSY] and CTRL[ERROR] are clear. Overlapped accesses are
not supported by the controller. Any pending write, read, or reload must be
completed before a write access can be requested.
3. Write the requested address to CTRL[ADDR] and program the unlock code into
CTRL[WR_UNLOCK]. The unlock code must be programmed for each write access.
The unlock code is documented in the register description. Both the unlock code and
address can be written in the same operation.
4. Write the data to the DATA register. This will automatically set CTRL[BUSY] and
clear CTRL[WR_UNLOCK]. Bit fields with 1's will result in that OTP bit being
programmed. Bit fields with 0's will be ignored. At the same time that the write is
accepted, the controller makes an internal copy of CTRL[ADDR] which cannot be
updated until the next write sequence is initiated. This copy guarantees that
erroneous writes to CTRL[ADDR] will not affect an active write operation. During
the write operation, DATA cannot be modified.
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On-Chip OTP Controller (OCOTP_CTRL)
5. Wait for the controller to clear CTRL[BUSY]. A write request to a protected or
locked region will result in no OTP access and no setting of CTRL[BUSY]. In
addition CTRL[ERROR] will be set. It must be cleared by software before any new
write access can be issued.
It should be noted that write latencies to OTP are numbers of 10 micro-seconds per word.
The write latency is based on the number of "1" bits being written. For example, to
program half the fuse bits in one 32-bt word requires 10 us x 16.
6.3.2.1.4 Error Conditions
The CTRL[ERROR] bit will be set under the following conditions:
• A write is performed to a shadow register during a shadow reload
(CTRL[RELOAD_SHADOWS] is set). In addition, the contents of the shadow
register shall not be updated.
• A write is performed to a shadow register which has been locked.
• A read is performed to a shadow register which has been read locked.
• A program is performed to a fuse word which has been locked.
• A read is performed to a fuse word which has been read locked.
• Overlapping access - a read, write, or reload is attempted while a read, write, or
reload is already in progress.
6.3.2.1.5 Write Postamble
Due to internal electrical characteristics of the OTP during writes, all OTP operations
(direct reads, shadow reloads, or other writes) following a write must wait at least 2 µs
after CTRL[BUSY] clears. The delay guarantees programming voltages on-chip reach a
steady state when exiting a write sequence.
A recommended software sequence to meet the postamble requirements is as follows:
1. Issue the write and poll for CTRL[BUSY].
2. After CTRL[BUSY] is clear, wait 2 µs.
3. Perform the next OTP operation.
6.3.2.2 Fuse Shadow Memory Footprint
The OTP memory footprint is shown in the following figure. The registers are grouped
by lock region. Their names correspond to the fusemap names.
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RESERVED RESERVED GP9
0x1F 0x3F 0xB3
RESERVED GP9
0x3E 0xB2
RESERVED GP9
0x3D 0xB1
RESERVED GP9
0x3C 0xB0
GP2 GP8
0x3B 0xAF
GP2 GP8
0x3A 0xAE
GP1 GP8
0x39 0xAD
RESERVED GP1 GP8
0x10 0x38 0xAC
RESERVED RESERVED GP7
0x0F 0x37 0xAB
RESERVED GP7
0x0E 0xAA
RESERVED GP7
0x0D 0xA9
Shadow RESERVED GP7
0x0C 0xA8
Registers
BOOT_CFG GP6
0x0B 0xA7
BOOT_CFG GP6
0x0A 0xA6
BOOT_CFG GP6
0x09 0xA5
BOOT_CFG RESERVED GP6
0x08 0x28 0xA4
BOOT_CFG RESERVED RESERVED RESERVED
0x07 0x27 0xA3 0x17F
GP4 MAC
0x06 0x26
RESERVED MAC
0x05 0x25
RESERVED MAC
0x04 0x24
RESERVED RESERVED
0x03 0x23
RESERVED USB_ID
0x02 0x22
LOCK1 RESERVED
0x01 0x21
LOCK0 RESERVED RESERVED RESERVED
0x00 0x20 0x40 0xB4
Figure 6-25. OTP Memory Footprint
6.3.2.3 OTP Read/Write Timing Parameters
The timing fields contained in the TIMING register that specify counter limit values,
which are used to time how long the state machine remains in the various states, as well
as specify the STROBE signal timing.
The timing parameters are specified in ipg_clk cycles. Since the ipg_clk frequency can be
set to a range of values, these parameters must be adjusted with the clock to yield the
appropriate delay.
The TIMING[RELAX] field specifies how long to remain in states to meet setup and
hold timing requirement in fuse spec. This parameter should be set by the following
equation:
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On-Chip OTP Controller (OCOTP_CTRL)
tRELAX = tHP_PG = (TIMING[RELAX]+1)/ipg_frequency > 16.2ns
TIMING[RELAX] field is used to create other setup and hold timing delays in addition to
tHP_PG. For all timing to be met, this is the max delay that must be programmed.
Except for setup and hold timing delay, there are 2 timing parameters for STROBE signal
pulse width in program and read.
The TIMING[STROBE_PROG] field specifies the period of the STROBE signal for fuse
writes and is given in units of ipg_clk cycles. This value should be specified so that the
requirement for the time when the STROBE signal is asserted high is met: 9000ns <
tPGM < 11000ns is met. Even though a range is given for tPGM, it is advised in
[eFUSE] to program for a value of 10000ns. Therefore, this field should be set according
to the following equation:
tPGM = ((TIMING[STROBE_PROG]+1)- 2*(TIMING[RELAX]+1))/ipg_frequency
= 10000ns.
The TIMING[STROBE_READ] field specifies the period of the STROBE signal for fuse
reads and is given in units of ipg_clk cycles. This field should be set according to the
following equation:
tRD = ((TIMING[STROBE_READ]+1)- 2*(TIMING[RELAX]+1))/ipg_frequency >
36ns.
The figure below illustrates the relationship between the STROBE signal in programming
and reading mode, as well as the timing PIO register fields that affect it. The
implementation uses one counter to generate the STROBE waveform within one period
and a second counter counts the number of cycles to create for programming the
designated word.
ADDRESS
STROBE
(tSTROBE READ or
tSTROBE_PROG) +1
tRELAX + 1 tRELAX + 1
Figure 6-26. STROBE Signal Creation and Timing
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6.3.2.4 Resets
The OCOTP is always active. The shadow registers automatically load the appropriate
OTP contents after reset is deasserted. During this load-time CTRL[BUSY] is set.
6.3.2.5 Clocks
The table found here describes the clock sources for OCOTP. Please see the chip-specific
clocking section for clock setting, configuration and gating information.
Table 6-36. OCOTP Clocks
Clock name Description
ipg_clk Peripheral clock
ipg_clk_s Peripheral access clock
6.3.3 External Signals
There are no external signals pinned out for OCOTP.
6.3.4 Fuse Map
See the Fusemap chapter of this reference manual for more information.
6.3.5 Memory Map/Register Definition
The OCOTP Memory Map/Register Definition can be found here.
NOTE
Writing or reading an unimplemented register address in the
OCOTP Controller will not send a bus error and read data will
be 0.
6.3.5.1 register descriptions
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.1 OCOTP memory map
OCOTP base address: 3035_0000h
Offset Register Width Access Reset value
(In bits)
0h OTP Controller Control Register (HW_OCOTP_CTRL) 32 RW 0000_0000h
4h OTP Controller Control Register (HW_OCOTP_CTRL_SET) 32 RW 0000_0000h
8h OTP Controller Control Register (HW_OCOTP_CTRL_CLR) 32 RW 0000_0000h
Ch OTP Controller Control Register (HW_OCOTP_CTRL_TOG) 32 RW 0000_0000h
10h OTP Controller Timing Register (HW_OCOTP_TIMING) 32 RW 0148_1299h
20h OTP Controller Write Data Register (HW_OCOTP_DATA) 32 RW 0000_0000h
30h OTP Controller Write Data Register (HW_OCOTP_READ_CTRL) 32 RW 0000_0000h
40h OTP Controller Read Data Register 32 RW 0000_0000h
(HW_OCOTP_READ_FUSE_DATA)
90h OTP Controller Version Register (HW_OCOTP_VERSION) 32 RO 0400_0000h
400h Value of OTP Bank0 Word0 (Lock controls) (HW_OCOTP_LOCK0) 32 RO 0000_0000h
410h Value of OTP Bank0 Word1 (Lock controls) (HW_OCOTP_LOCK1) 32 RO FFFF_FFFFh
460h Value of OTP Bank1 Word2 (HW_OCOTP_GP4) 32 RW 0000_0000h
470h Value of OTP Bank1 Word3 (Boot Configuration Info.) 32 RW 0000_0000h
(HW_OCOTP_BOOT_CFG0)
480h Value of OTP Bank2 Word0 (Boot Configuration Info.) 32 RW 0000_0000h
(HW_OCOTP_BOOT_CFG1)
490h Value of OTP Bank2 Word1 (Boot Configuration Info.) 32 RW 0000_0000h
(HW_OCOTP_BOOT_CFG2)
4A0h Value of OTP Bank2 Word2 (Boot Configuration Info.) 32 RW 0000_0000h
(HW_OCOTP_BOOT_CFG3)
4B0h Value of OTP Bank2 Word3 (BOOT Configuration Info.) 32 RW 0000_0000h
(HW_OCOTP_BOOT_CFG4)
620h Value of OTP Bank8 Word2 (USB ID info) (HW_OCOTP_USB_ID) 32 RW 0000_0000h
640h Value of OTP Bank9 Word0 (MAC Address) 32 RW 0000_0000h
(HW_OCOTP_MAC_ADDR0)
650h Value of OTP Bank9 Word1 (MAC Address) 32 RW 0000_0000h
(HW_OCOTP_MAC_ADDR1)
660h Value of OTP Bank9 Word2 (MAC Address) 32 RW 0000_0000h
(HW_OCOTP_MAC_ADDR2)
780h Value of OTP Bank14 Word0 () (HW_OCOTP_GP1_0) 32 RW 0000_0000h
790h Value of OTP Bank14 Word1 () (HW_OCOTP_GP1_1) 32 RW 0000_0000h
7A0h Value of OTP Bank14 Word2 () (HW_OCOTP_GP2_0) 32 RW 0000_0000h
7B0h Value of OTP Bank14 Word3 () (HW_OCOTP_GP2_1) 32 RW 0000_0000h
E40h Value of OTP Bank41 Word0 () (HW_OCOTP_GP6_0) 32 RW 0000_0000h
E50h Value of OTP Bank41 Word1 () (HW_OCOTP_GP6_1) 32 RW 0000_0000h
E60h Value of OTP Bank41 Word2 () (HW_OCOTP_GP6_2) 32 RW 0000_0000h
E70h Value of OTP Bank41 Word3 () (HW_OCOTP_GP6_3) 32 RW 0000_0000h
E80h Value of OTP Bank42 Word0 () (HW_OCOTP_GP7_0) 32 RW 0000_0000h
Table continues on the next page...
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Offset Register Width Access Reset value
(In bits)
E90h Value of OTP Bank42 Word1 () (HW_OCOTP_GP7_1) 32 RW 0000_0000h
EA0h Value of OTP Bank42 Word2 () (HW_OCOTP_GP7_2) 32 RW 0000_0000h
EB0h Value of OTP Bank42 Word3 () (HW_OCOTP_GP7_3) 32 RW 0000_0000h
EC0h Value of OTP Bank43 Word0 () (HW_OCOTP_GP8_0) 32 RW 0000_0000h
ED0h Value of OTP Bank43 Word1 () (HW_OCOTP_GP8_1) 32 RW 0000_0000h
EE0h Value of OTP Bank43 Word2 () (HW_OCOTP_GP8_2) 32 RW 0000_0000h
EF0h Value of OTP Bank43 Word3 () (HW_OCOTP_GP8_3) 32 RW 0000_0000h
F00h Value of OTP Bank44 Word0 () (HW_OCOTP_GP9_0) 32 RW 0000_0000h
F10h Value of OTP Bank44 Word1 () (HW_OCOTP_GP9_1) 32 RW 0000_0000h
F20h Value of OTP Bank44 Word2 () (HW_OCOTP_GP9_2) 32 RW 0000_0000h
F30h Value of OTP Bank44 Word3 () (HW_OCOTP_GP9_3) 32 RW 0000_0000h
6.3.5.1.2 OTP Controller Control Register (HW_OCOTP_CTRL)
6.3.5.1.2.1 Offset
Register Offset Description
HW_OCOTP_CTRL 0h OTP Controller Control Register
HW_OCOTP_CTRL_SET 4h Writing a 1 to a bit in this register sets the
corresponding bit in HW_OCOTP_CTRL
HW_OCOTP_CTRL_CL 8h Writing a 1 to a bit in this register clears the
R corresponding bit in HW_OCOTP_CTRL
HW_OCOTP_CTRL_TO Ch Writing a 1 to a bit in this register toggles the
G corresponding bit in HW_OCOTP_CTRL
6.3.5.1.2.2 Function
The OCOTP Control and Status Register provides the necessary software interface for
performing read and write operations to the On-Chip OTP (One-Time Programmable
ROM). The control fields such as WR_UNLOCK, ADDR and BUSY/ERROR may be
used in conjuction with the HW_OCOTP_DATA register to perform write operations.
Read operations to the On-Chip OTP are involving ADDR, BUSY/ERROR bit field and
HW_OCOTP_READ_CTRL register. Read value is saved in
HW_OCOTP_READ_FUSE_DATA register.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
WR_UNLOCK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUSY
R
0
RELOAD_SHADOWS
Reserved
ERROR
ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.2.4 Fields
Field Function
31-16 Write 0x3E77 to enable OTP write accesses. NOTE: This register must be unlocked on a write-by-write
basis (a write is initiated when HW_OCOTP_DATA is written), so the UNLOCK bitfield must contain the
WR_UNLOCK
correct key value during all writes to HW_OCOTP_DATA, otherwise a write shall not be initiated. This
field is automatically cleared after a successful write completion (clearing of BUSY).
15 Reserved
—
14-12 Reserved
—
11 Set to force re-loading the shadow registers (HW/SW capability and LOCK). This operation will
automatically set BUSY. Once the shadow registers have been re-loaded, BUSY and
RELOAD_SHAD
RELOAD_SHADOWS are automatically cleared by the controller.
OWS
10 Set by the controller when an access to a locked region(OTP or shadow register) is requested. Must be
cleared before any further access can be performed. This bit can only be set by the controller. This bit is
ERROR
also set if the Pin interface is active and software requests an access to the OTP. In this instance, the
ERROR bit cannot be cleared until the Pin interface access has completed. Reset this bit by writing a one
to the SCT clear address space and not by a general write.
9 OTP controller status bit. When active, no new write access or read access to OTP(including
RELOAD_SHADOWS) can be performed. Cleared by controller when access complete. After reset (or
BUSY
after setting RELOAD_SHADOWS), this bit is set by the controller until the HW/SW and LOCK registers
are successfully copied, after which time it is automatically cleared by the controller.
8-0 OTP write and read access address register.
ADDR
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6.3.5.1.3 OTP Controller Timing Register (HW_OCOTP_TIMING)
6.3.5.1.3.1 Offset
Register Offset
HW_OCOTP_TIMING 10h
6.3.5.1.3.2 Function
This register specifies timing parameters for programming and reading the OCOTP fuse
array.
6.3.5.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
WAIT STROBE_READ
W
Reset 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RELAX STROBE_PROG
W
Reset 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 1
6.3.5.1.3.4 Fields
Field Function
31-28 Reserved
—
27-22 This count value specifies time interval between auto read and write access in one time program. It is
given in number of ipg_clk periods.
WAIT
21-16 This count value specifies the strobe period in one time read OTP. Trd = ((STROBE_READ+1)-
2*(RELAX+1)) /ipg_clk_freq. It is given in number of ipg_clk periods.
STROBE_READ
15-12 This count value specifies the time to add to all default timing parameters other than the Tpgm and Trd. It
is given in number of ipg_clk periods.
RELAX
11-0 This count value specifies the strobe period in one time write OTP. Tpgm = ((STROBE_PROG+1)-
2*(RELAX+1)) /ipg_clk_freq. It is given in number of ipg_clk periods.
STROBE_PRO
G
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6.3.5.1.4 OTP Controller Write Data Register (HW_OCOTP_DATA)
6.3.5.1.4.1 Offset
Register Offset
HW_OCOTP_DATA 20h
6.3.5.1.4.2 Function
This register is used in conjuction with HW_OCOTP_CTRL to perform one-time writes
to the OTP. Please see the "Software Write Sequence" section for operating details.
6.3.5.1.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.4.4 Fields
Field Function
31-0 Used to initiate a write to OTP. Please see the "Software Write Sequence" section for operating details.
DATA
6.3.5.1.5 OTP Controller Write Data Register (HW_OCOTP_READ_CTRL)
6.3.5.1.5.1 Offset
Register Offset
HW_OCOTP_READ_CT 30h
RL
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6.3.5.1.5.2 Function
This register is used in conjuction with HW_OCOTP_CTRL to perform one time read to
the OTP. Please see the "Software read Sequence" section for operating details.
6.3.5.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
READ_FUSE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.5.4 Fields
Field Function
31-1 Reserved
—
0 Used to initiate a read to OTP. Please see the "Software read Sequence" section for operating details.
READ_FUSE
6.3.5.1.6 OTP Controller Read Data Register
(HW_OCOTP_READ_FUSE_DATA)
6.3.5.1.6.1 Offset
Register Offset
HW_OCOTP_READ_FU 40h
SE_DATA
6.3.5.1.6.2 Function
The data read from OTP
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6.3.5.1.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.6.4 Fields
Field Function
31-0 The data read from OTP
DATA
6.3.5.1.7 OTP Controller Version Register (HW_OCOTP_VERSION)
6.3.5.1.7.1 Offset
Register Offset
HW_OCOTP_VERSION 90h
6.3.5.1.7.2 Function
This register indicates the RTL version in use.
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6.3.5.1.7.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R MAJOR MINOR
W
Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R STEP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.7.4 Fields
Field Function
31-24 Fixed read-only value reflecting the MAJOR field of the RTL version.
MAJOR
23-16 Fixed read-only value reflecting the MINOR field of the RTL version.
MINOR
15-0 Fixed read-only value reflecting the stepping of the RTL version.
STEP
6.3.5.1.8 Value of OTP Bank0 Word0 (Lock controls) (HW_OCOTP_LOCK0)
6.3.5.1.8.1 Offset
Register Offset
HW_OCOTP_LOCK0 400h
6.3.5.1.8.2 Function
Shadowed memory mapped access to OTP Bank 0, word 0.
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6.3.5.1.8.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R GP2 GP1
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAC_ADDR
USB_ID
Reserved
Reserved
Reserved
Reserved
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.8.4 Fields
Field Function
31-24 Reserved
—
23-22 Status of shadow register and OTP write lock for gp2 region.
GP2 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
21-20 Status of shadow register and OTP write lock for gp1 region.
GP1 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
19-16 Reserved
—
15-14 Status of shadow register and OTP write lock for mac_addr region.
MAC_ADDR 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
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Field Function
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
13-12 Status of shadow register and OTP write lock for usb_id region.
USB_ID 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
11 Reserved
—
10-9 Reserved
—
8-4 Reserved
—
3-0 Reserved
—
6.3.5.1.9 Value of OTP Bank0 Word1 (Lock controls) (HW_OCOTP_LOCK1)
6.3.5.1.9.1 Offset
Register Offset
HW_OCOTP_LOCK1 410h
6.3.5.1.9.2 Function
Shadowed memory mapped access to OTP Bank 0, word 1.
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6.3.5.1.9.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R GP9
Reserved
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R GP8 GP7 GP6 GP4
Reserved Reserved
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6.3.5.1.9.4 Fields
Field Function
31-18 Reserved
—
17-16 Status of shadow register and OTP write lock for gp9 region.
GP9 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
15-14 Status of shadow register and OTP write lock for gp8 region.
GP8 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
13-12 Status of shadow register and OTP write lock for gp7 region.
GP7 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
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Field Function
11-10 Status of shadow register and OTP write lock for gp6 region.
GP6 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
9-6 Reserved
—
5-4 Status of shadow register and OTP write lock for gp8 region.
GP4 00 - Unlock (The controlled field can be read, sensed, burned or overridden in the corresponded OCOTP
shadow register)
10 - OP (Override Protect, the controlled field can be read, sensed or burned, but can't be overridden in
the corresponded OCOTP shadow register)
01 - WP (Write Protect, the controlled field can be read, sensed or overridden in the corresponded
OCOTP shadow register, but can't be burned)
11 - OP + WP (The controlled field can be read or sensed only, but can't be burned or overridden in the
corresponded OCOTP shadow register)
3-0 Reserved
—
6.3.5.1.10 Value of OTP Bank1 Word2 (HW_OCOTP_GP4)
6.3.5.1.10.1 Offset
Register Offset
HW_OCOTP_GP4 460h
6.3.5.1.10.2 Function
Shadowed memory mapped access to OTP Bank 1, word 2.
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6.3.5.1.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.10.4 Fields
Field Function
31-7 Reflects value of OTP Bank 1, word 2, bits [31:7].
BITS
6-0 Reserved
—
6.3.5.1.11 Value of OTP Bank1 Word3 (Boot Configuration Info.)
(HW_OCOTP_BOOT_CFG0)
6.3.5.1.11.1 Offset
Register Offset
HW_OCOTP_BOOT_CF 470h
G0
6.3.5.1.11.2 Function
Shadowed memory mapped access to OTP Bank 1, word 3.
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6.3.5.1.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.11.4 Fields
Field Function
31-0 Reflects value of OTP Bank 1, word 3. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.
BITS
6.3.5.1.12 Value of OTP Bank2 Word0 (Boot Configuration Info.)
(HW_OCOTP_BOOT_CFG1)
6.3.5.1.12.1 Offset
Register Offset
HW_OCOTP_BOOT_CF 480h
G1
6.3.5.1.12.2 Function
Shadowed memory mapped access to OTP bank 2, word 0.
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6.3.5.1.12.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.12.4 Fields
Field Function
31-0 Reflects value of OTP bank 2, word 0. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.
BITS
6.3.5.1.13 Value of OTP Bank2 Word1 (Boot Configuration Info.)
(HW_OCOTP_BOOT_CFG2)
6.3.5.1.13.1 Offset
Register Offset
HW_OCOTP_BOOT_CF 490h
G2
6.3.5.1.13.2 Function
Shadowed memory mapped access to OTP bank 2, word 1.
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6.3.5.1.13.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.13.4 Fields
Field Function
31-0 Reflects value of OTP bank 2, word 1. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.
BITS
6.3.5.1.14 Value of OTP Bank2 Word2 (Boot Configuration Info.)
(HW_OCOTP_BOOT_CFG3)
6.3.5.1.14.1 Offset
Register Offset
HW_OCOTP_BOOT_CF 4A0h
G3
6.3.5.1.14.2 Function
Shadowed memory mapped access to OTP bank 2, word 2.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.14.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.14.4 Fields
Field Function
31-0 Reflects value of OTP bank 2, word 2. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.
BITS
6.3.5.1.15 Value of OTP Bank2 Word3 (BOOT Configuration Info.)
(HW_OCOTP_BOOT_CFG4)
6.3.5.1.15.1 Offset
Register Offset
HW_OCOTP_BOOT_CF 4B0h
G4
6.3.5.1.15.2 Function
Shadowed memory mapped access to OTP bank 2, word 3.
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6.3.5.1.15.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.15.4 Fields
Field Function
31-0 Reflects value of OTP bank 2, word 3. These bits become read-only after the
HW_OCOTP_LOCK_BOOT_CFG[1] bit is set.
BITS
6.3.5.1.16 Value of OTP Bank8 Word2 (USB ID info) (HW_OCOTP_USB_ID)
6.3.5.1.16.1 Offset
Register Offset
HW_OCOTP_USB_ID 620h
6.3.5.1.16.2 Function
Shadowed memory mapped access to OTP Bank 8, word 2.
6.3.5.1.16.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.16.4 Fields
Field Function
31-0 Reflects value of OTP Bank 8, word 2.
BITS
6.3.5.1.17 Value of OTP Bank9 Word0 (MAC Address)
(HW_OCOTP_MAC_ADDR0)
6.3.5.1.17.1 Offset
Register Offset
HW_OCOTP_MAC_ADD 640h
R0
6.3.5.1.17.2 Function
Shadowed memory mapped access to OTP Bank 9, word 0.
6.3.5.1.17.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.17.4 Fields
Field Function
31-0 Reflects value of OTP Bank 9, word 0.
BITS
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6.3.5.1.18 Value of OTP Bank9 Word1 (MAC Address)
(HW_OCOTP_MAC_ADDR1)
6.3.5.1.18.1 Offset
Register Offset
HW_OCOTP_MAC_ADD 650h
R1
6.3.5.1.18.2 Function
Shadowed memory mapped access to OTP Bank 9, word 1.
6.3.5.1.18.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.18.4 Fields
Field Function
31-0 Reflects value of OTP Bank 9, word 1.
BITS
6.3.5.1.19 Value of OTP Bank9 Word2 (MAC Address)
(HW_OCOTP_MAC_ADDR2)
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.19.1 Offset
Register Offset
HW_OCOTP_MAC_ADD 660h
R2
6.3.5.1.19.2 Function
Shadowed memory mapped access to OTP Bank 9, word 2.
6.3.5.1.19.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.19.4 Fields
Field Function
31-0 Reflects value of OTP Bank 9, word 2.
BITS
6.3.5.1.20 Value of OTP Bank14 Word0 () (HW_OCOTP_GP1_0)
6.3.5.1.20.1 Offset
Register Offset
HW_OCOTP_GP1_0 780h
6.3.5.1.20.2 Function
Shadowed memory mapped access to OTP Bank 14, word 0.
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6.3.5.1.20.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.20.4 Fields
Field Function
31-0 Reflects value of OTP Bank 14, word 0.
BITS
6.3.5.1.21 Value of OTP Bank14 Word1 () (HW_OCOTP_GP1_1)
6.3.5.1.21.1 Offset
Register Offset
HW_OCOTP_GP1_1 790h
6.3.5.1.21.2 Function
Shadowed memory mapped access to OTP Bank 14, word 1.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.21.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.21.4 Fields
Field Function
31-0 Reflects value of OTP Bank 14, word 1.
BITS
6.3.5.1.22 Value of OTP Bank14 Word2 () (HW_OCOTP_GP2_0)
6.3.5.1.22.1 Offset
Register Offset
HW_OCOTP_GP2_0 7A0h
6.3.5.1.22.2 Function
Shadowed memory mapped access to OTP Bank 14, word 2.
6.3.5.1.22.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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6.3.5.1.22.4 Fields
Field Function
31-0 Reflects value of OTP Bank 14, word 2.
BITS
6.3.5.1.23 Value of OTP Bank14 Word3 () (HW_OCOTP_GP2_1)
6.3.5.1.23.1 Offset
Register Offset
HW_OCOTP_GP2_1 7B0h
6.3.5.1.23.2 Function
Shadowed memory mapped access to OTP Bank 14, word 3.
6.3.5.1.23.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.23.4 Fields
Field Function
31-0 Reflects value of OTP Bank 14, word 3.
BITS
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.24 Value of OTP Bank41 Word0 () (HW_OCOTP_GP6_0)
6.3.5.1.24.1 Offset
Register Offset
HW_OCOTP_GP6_0 E40h
6.3.5.1.24.2 Function
Shadowed memory mapped access to OTP Bank 41, word 0.
6.3.5.1.24.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.24.4 Fields
Field Function
31-0 Reflects value of OTP Bank 41, word 0.
BITS
6.3.5.1.25 Value of OTP Bank41 Word1 () (HW_OCOTP_GP6_1)
6.3.5.1.25.1 Offset
Register Offset
HW_OCOTP_GP6_1 E50h
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6.3.5.1.25.2 Function
Shadowed memory mapped access to OTP Bank 41, word 1.
6.3.5.1.25.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.25.4 Fields
Field Function
31-0 Reflects value of OTP Bank 41, word 1.
BITS
6.3.5.1.26 Value of OTP Bank41 Word2 () (HW_OCOTP_GP6_2)
6.3.5.1.26.1 Offset
Register Offset
HW_OCOTP_GP6_2 E60h
6.3.5.1.26.2 Function
Shadowed memory mapped access to OTP Bank 41, word 2.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.26.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.26.4 Fields
Field Function
31-0 Reflects value of OTP Bank 41, word 2.
BITS
6.3.5.1.27 Value of OTP Bank41 Word3 () (HW_OCOTP_GP6_3)
6.3.5.1.27.1 Offset
Register Offset
HW_OCOTP_GP6_3 E70h
6.3.5.1.27.2 Function
Shadowed memory mapped access to OTP Bank 41, word 3.
6.3.5.1.27.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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6.3.5.1.27.4 Fields
Field Function
31-0 Reflects value of OTP Bank 41, word 3.
BITS
6.3.5.1.28 Value of OTP Bank42 Word0 () (HW_OCOTP_GP7_0)
6.3.5.1.28.1 Offset
Register Offset
HW_OCOTP_GP7_0 E80h
6.3.5.1.28.2 Function
Shadowed memory mapped access to OTP Bank 42, word 0.
6.3.5.1.28.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.28.4 Fields
Field Function
31-0 Reflects value of OTP Bank 42, word 0.
BITS
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.29 Value of OTP Bank42 Word1 () (HW_OCOTP_GP7_1)
6.3.5.1.29.1 Offset
Register Offset
HW_OCOTP_GP7_1 E90h
6.3.5.1.29.2 Function
Shadowed memory mapped access to OTP Bank 42, word 1.
6.3.5.1.29.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.29.4 Fields
Field Function
31-0 Reflects value of OTP Bank 42, word 1.
BITS
6.3.5.1.30 Value of OTP Bank42 Word2 () (HW_OCOTP_GP7_2)
6.3.5.1.30.1 Offset
Register Offset
HW_OCOTP_GP7_2 EA0h
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6.3.5.1.30.2 Function
Shadowed memory mapped access to OTP Bank 42, word 2.
6.3.5.1.30.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.30.4 Fields
Field Function
31-0 Reflects value of OTP Bank 42, word 2.
BITS
6.3.5.1.31 Value of OTP Bank42 Word3 () (HW_OCOTP_GP7_3)
6.3.5.1.31.1 Offset
Register Offset
HW_OCOTP_GP7_3 EB0h
6.3.5.1.31.2 Function
Shadowed memory mapped access to OTP Bank 42, word 3.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.31.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.31.4 Fields
Field Function
31-0 Reflects value of OTP Bank 42, word 3.
BITS
6.3.5.1.32 Value of OTP Bank43 Word0 () (HW_OCOTP_GP8_0)
6.3.5.1.32.1 Offset
Register Offset
HW_OCOTP_GP8_0 EC0h
6.3.5.1.32.2 Function
Shadowed memory mapped access to OTP Bank 43, word 0.
6.3.5.1.32.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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6.3.5.1.32.4 Fields
Field Function
31-0 Reflects value of OTP Bank 43, word 0.
BITS
6.3.5.1.33 Value of OTP Bank43 Word1 () (HW_OCOTP_GP8_1)
6.3.5.1.33.1 Offset
Register Offset
HW_OCOTP_GP8_1 ED0h
6.3.5.1.33.2 Function
Shadowed memory mapped access to OTP Bank 43, word 1.
6.3.5.1.33.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.33.4 Fields
Field Function
31-0 Reflects value of OTP Bank 43, word 1.
BITS
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.34 Value of OTP Bank43 Word2 () (HW_OCOTP_GP8_2)
6.3.5.1.34.1 Offset
Register Offset
HW_OCOTP_GP8_2 EE0h
6.3.5.1.34.2 Function
Shadowed memory mapped access to OTP Bank 43, word 2.
6.3.5.1.34.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.34.4 Fields
Field Function
31-0 Reflects value of OTP Bank 43, word 2.
BITS
6.3.5.1.35 Value of OTP Bank43 Word3 () (HW_OCOTP_GP8_3)
6.3.5.1.35.1 Offset
Register Offset
HW_OCOTP_GP8_3 EF0h
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6.3.5.1.35.2 Function
Shadowed memory mapped access to OTP Bank 43, word 3.
6.3.5.1.35.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.35.4 Fields
Field Function
31-0 Reflects value of OTP Bank 43, word 3.
BITS
6.3.5.1.36 Value of OTP Bank44 Word0 () (HW_OCOTP_GP9_0)
6.3.5.1.36.1 Offset
Register Offset
HW_OCOTP_GP9_0 F00h
6.3.5.1.36.2 Function
Shadowed memory mapped access to OTP Bank 44, word 0.
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On-Chip OTP Controller (OCOTP_CTRL)
6.3.5.1.36.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.36.4 Fields
Field Function
31-0 Reflects value of OTP Bank 44, word 0.
BITS
6.3.5.1.37 Value of OTP Bank44 Word1 () (HW_OCOTP_GP9_1)
6.3.5.1.37.1 Offset
Register Offset
HW_OCOTP_GP9_1 F10h
6.3.5.1.37.2 Function
Shadowed memory mapped access to OTP Bank 44, word 1.
6.3.5.1.37.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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6.3.5.1.37.4 Fields
Field Function
31-0 Reflects value of OTP Bank 44, word 1.
BITS
6.3.5.1.38 Value of OTP Bank44 Word2 () (HW_OCOTP_GP9_2)
6.3.5.1.38.1 Offset
Register Offset
HW_OCOTP_GP9_2 F20h
6.3.5.1.38.2 Function
Shadowed memory mapped access to OTP Bank 44, word 2.
6.3.5.1.38.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.38.4 Fields
Field Function
31-0 Reflects value of OTP Bank 44, word 2.
BITS
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Secure Non-Volatile Storage (SNVS)
6.3.5.1.39 Value of OTP Bank44 Word3 () (HW_OCOTP_GP9_3)
6.3.5.1.39.1 Offset
Register Offset
HW_OCOTP_GP9_3 F30h
6.3.5.1.39.2 Function
Shadowed memory mapped access to OTP Bank 44, word 3.
6.3.5.1.39.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BITS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.3.5.1.39.4 Fields
Field Function
31-0 Reflects value of OTP Bank 44, word 3.
BITS
6.4 Secure Non-Volatile Storage (SNVS)
6.4.1 Overview
The Secure Non-Volatile Storage (SNVS) is a companion module to the CAAM module.
The SNVS non-security functionality is described in this document, but the SNVS
security functionality is described only in the Security Reference Manual.
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Chapter 6 SNVS, Reset, Fuse, and Boot
6.4.1.1 Block diagram
The following figure illustrates the structure of SNVS.
Interrupts IP Bus System Reset
32
HP
IP Bus Interface Periodic Interrupt
and Control
Time Alarm
Real-time Counter
HP-LP Interface
VCC
Chip Power Domain
Internal
LP-HP Bus
LP Control
Chip Power Supply
General Purpose
Registers
pmic_en_b VCC
PMIC
Control LP Power Domain
ONOFF (btn)
LP
LP Power Supply
set_pwr_off_irq
Security Event
LP Power-On-Reset
VDD_SNVS_IN
Chip Power Fail
PMIC_ON_REQ
LP POR HP Power
Module Fail Detector
Figure 6-27. SNVS Block Diagram
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Secure Non-Volatile Storage (SNVS)
6.4.1.2 Features
The following table summarizes the features of SNVS:
Table 6-37. SNVS feature list
Feature Description Links for Further
Information
Real time counter • The RTC is driven by a dedicated clock, which is off when the SNVS_HP Real Time
(RTC) system power is down. Counter
• Programmable time alarm interrupt
General-purpose • The general-purpose register is available to software to store 128 Using the General-
register bits of data. Purpose Register
• The general-purpose register is zeroized when a security violation is
detected.
• If the SNVS_LP power input is connected to an uninterrupted power
supply (see SNVS power domains), the general-purpose register
value is retained even if the main chip is powered down.
Register access • Some registers/values can be written only once per boot cycle. privileged and non-
restrictions privileged registers
Wakeup from power off • Input signal from off chip requests SNVS_LP to power on the main LP Wake-Up Interrupt
SoC (Assuming that the SNVS_LP power input is connected to an Enable
uninterrupted power supply (see SNVS power domains).
• Hardware debounces the input signal using software-specified signal
bounce characteristics
6.4.2 SNVS functional description
SNVS implements several non-security features that involve software interaction:
• reading or writing the Realtime Counter (RTC) (This is a non-privileged operation.) -
software can also instruct SNVS to load the current SRTC value into the RTC
• reading or writing the General Purpose Register (GPR) (Note that there may be a
significant delay when reading or writing registers in the LP section if the LP clock is
different from the HP clock.)
The following sections describe in more detail the operation of SNVS.
6.4.2.1 SNVS power domains
In some versions of SNVS (including this version), the LP (Low Power) section is
implemented in an independent power domain from the HP (High Power) section, and
most other logic on the chip. Throughout the SNVS documentation whenever mention is
made of "always-on" logic, this assumes a version of SNVS that implements an
independent power domain for the LP section, and that the power for this section is
supplied by an uninterrupted power supply. The purpose for the independent power
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domain is so that data can be retained and certain logic can remain functional even when
the main chip logic is powered down. But this is possible only if the LP domain remains
powered via an uninterrupted power supply when the main chip power domain is
powered off. Usually this uninterrupted power supply would be a battery, with possibly
some power management logic to power the LP section from main power (and perhaps
recharge the battery) when main power is on, and switch to battery power when the main
power is off. In versions of SNVS with an independent LP power domain the LP section
can be electrically isolated from the rest of the chip logic to ensure that its logic does not
get corrupted when the main chip is powered down. If the battery runs down or is
removed, an LP POR will occur when the LP section next powers up. Note that some
OEMs may choose to connect LP power to HP/main chip power and dispense with a
battery. In that case the SNVS will operate the same as an SNVS without an independent
LP power domain. No state will be retained in the LP section when the chip is powered
down, and an LP POR will occur whenever there is an HP POR.
6.4.2.2 Runtime Procedures
SNVS implements a number of features that are intended to be accessed by software at
runtime (as opposed to accessed at boot time). These features include:
• Real Time Clock (see SNVS_HP Real Time Counter)
• General Purpose Register (see Using the General-Purpose Register)
Procedures for using these features are described in the following sections.
6.4.2.2.1 Using SNVS Timer Facilities
SNVS incorporates timer facilities that can optionally generate an interrupt at a specified
time. As described in the following sections, SNVS_HP incorporates a Real Time
Counter that is available for general use, and SNVS_LP incorporates a Secure Real Time
Counter intended for security applications.
6.4.2.2.1.1 SNVS_HP Real Time Counter
SNVS_HP implements a real time counter that can be read or written by any application;
it has no privileged software access restrictions. When the chip is powered down the RTC
is not active and it is reset at chip POR. The RTC can be used to generate a functional
interrupt request either at a specific time, or at a specific frequency, or both. To generate
an interrupt request at a specific time HPTA_EN is set to 0, the desired time is written to
HPTA_MS and HPTA_LS and then HPTA_EN is set to 1. HPTA_EN, HPTA_MS and
HPTA_LS can be written by any software that has access to SNVS registers; there are no
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privileged access restrictions. The counter can be synchronized to the SNVS_LP SRTC
by writing to the HP_TS bit of SNVS_HP Control Register. This is particularly useful if
the SNVS_LP is powered from an uninterrupted power source because the RTC can then
be set from a chip-internal time source.
6.4.2.2.1.2 RTC/SRTC control bits setting
All SNVS registers are programmed from the register bus, consequently any software-
initiated changes are synchronized with the IP clock. Several registers can also change
synchronously with the RTC/SRTC clock after they are programmed. To avoid IP clock
and RTC/SRTC clock synchronization issues, the following values can be changed only
when the corresponding function is disabled.
Table 6-38. RTC/SRTC synchronized values list
Function Value/register Control bit setting
HP section
HP Real Time Counter HPRTCMR and HPRTCLR Registers RTC_EN = 0 : HPRTCMR/HPRTCLR
can be programmed
RTC_EN = 1 : HPRTCMR/HPRTCLR
cannot be programmed
HP Time Alarm HPTAMR and HPTALR Registers HPTA_EN = 0 : HPTAMR/HPTALR can
be programmed
HPTA_EN = 1 : HPTAMR/HPTALR
cannot be programmed
LP section
LP Secure Real Time Counter LPRTCMR and LPRTCLR Registers SRTC_ENV = 0 : LPRTCMR/LPRTCLR
can be programmed
SRTC_ENV = 1 : LPRTCMR/LPRTCLR
cannot be programmed
LP Time Alarm LPTAR Register LPTA_EN = 0 : LPTAR can be
programmed
LPTA_EN = 1 : LPTAR cannot be
programmed
Use the following steps to program synchronized values:
1. Check the enable bit value. If set, clear it.
2. Verify that the enable bit is cleared. There are two reasons to verify the enable bit's
setting:
• Enable bit clearing does not happen immediately; it takes three IP clock cycles and
two RTC/SRTC clock cycles to change the enable bit's value.
• If the enable bit is locked for programming, it cannot be cleared.
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3. Program the desired value.
4. Set the enable bit; it takes three IP clock cycles and two RTC/SRTC clock cycles for
the bit to set.
NOTE
Incrementing the value programmed into RTC/SRTC registers
by two compensates for the two RTC/SRTC clock cycle delay
that is required to enable the counter.
6.4.2.2.1.3 Reading RTC and SRTC values
Software should follow the following procedure to ensure that it has read correct data
from the RTC (HPRTCMR and HPRTCLR) and SRTC (LPSRTCMR and LPSRTCLR)
registers:
• Read the most-significant half and the least-significant half of the RTC/SRTC and
then read both halves again. If the values read are the same both times, the value is
correct.
• If the two consecutive pairs of reads yield different results, perform two more reads.
The worst case scenario may require three sessions of two consecutive pairs of reads.
There are several reasons that the values may be incorrectly read initially:
• Synchronization issues between the RTC/SRTC clock and the system clock
• Since the counter continues to increment, there may be a carry from the least-
significant 32-bits to the most-significant bits in between reading the two halves of
the counter
6.4.2.2.2 Using Other SNVS Registers
The sections below describe how to use the General Purpose Register.
6.4.2.2.2.1 Using the General-Purpose Register
SNVS implements a 128-bit general-purpose register allows software to store a small
amount of data. To maintain backward compatibility with versions of SNVS that
implement only a 32-bit general purpose register, the most-significant word of the
general purpose register is aliased to the original legacy address, and to maintain
backward compatibility with versions of snvs_module_name that implement a 128-bit
general purpose register, the most-significant half of the general purpose register is
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aliased to the previous legacy address address. The data in the GPR will be retained
during system power-down mode as long as the SNVS_LP remains powered by an
uninterrupted power source.
6.4.2.3 Clocks
The SNVS has the following clock sources:
• System peripheral clock input. This clock is used by the SNVS's internal logic, for
example, the Security State Machine. This clock can be gated outside of the module
when the SNVS indicates that it is not in use.
• HP RTC clock. This clock is used by SNVS_HP real-time counter. This clock does
not need to be synchronous with other clocks.
6.4.2.4 Reset
The table below shows the different resets associated with this module.
Table 6-39. Reset summary
Reset Source Characteristics Internally resets
HP hard ipg_hard_async_re active-low, All SNVS_HP and SNVS_LP registers and flops.
set_b
asynchronous
LP Power On lp_por_b active-low, All SNVS_LP registers and flops.
Reset (POR)
asynchronous
LP software software active-high, All SNVS_LP registers and flops. The LP software reset can be
reset asserted if not disabled.
synchronous,
one cycle
6.4.3 External Signals
Table 6-40. External Signals
Signal Description Direction
PMIC_ON_REQ PMIC ON Request signal I
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6.4.4 Initialization of SNVS
SNVS is implemented in two sections (HP and LP) that both must be initialized by
software. If the SNVS_LP is powered by an uninterrupted power source that is separate
from main SoC power, then SNVS can operate in either of two modes, depending upon
whether the main SoC power is on or off.
• During main SoC power-down SNVS_HP is powered-down, but SNVS_LP is
powered from the backup power supply and is electrically isolated from the rest of
the chip. In this mode SNVS_LP keeps its registers' values but the LP registers
cannot be read or written.
• During main SoC power-up the isolation of SNVS_LP is disabled and both
SNVS_HP and SNVS_LP are powered from the main SoC power. Both LP and HP
registers can be read and written (locks and privilege modes permitting). Signals
between the SNVS_HP and SNVS_LP sections are enabled and all SNVS functions
are operational.
Since the HP and LP sections reside in different power domains, the POR for the two
sections can occur at different times. If the SNVS_LP section remains powered by an
uninterrupted power source when the main SoC power is off, SNVS_LP is initialized
rarely, typically once when the device is first powered on and again whenever the battery
is replaced. During main SoC power-up the isolation of SNVS_LP is disabled and both
SNVS_HP and SNVS_LP are powered from the main SoC power. Signals between the
SNVS_HP and SNVS_LP sections are enabled and all SNVS functions are operational.
The SNVS_HP section is powered from the main SoC power, so it must be initialized
after the device is powered on. If the SNVS_LP section is powered from the main SoC
power rather than from an uninterrupted power source, the SNVS_LP section must also
be initialized at SoC POR.
• Initializing the LP section
• The following steps should be completed to properly initialize the SNVS LP
section (required only on LP POR, i.e. when the battery is replaced):
• Initializing the HP section
• The following steps should be completed to properly initialize the SNVS HP
section (required on HP POR, i.e. SoC POR):
• Perform normal boot to put the SNVS into a functional state (Non-secure,
Trusted, Secure) (see HP Command Register, SSM_ST bitfield).
• Program SNVS general functions/configurations (see HP Control Register).
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6.4.5 Memory Map and register definition
This section contains detailed register descriptions for the SNVS registers. Each
description includes a standard register diagram and register table. The register table
provides detailed descriptions of the register bit and field functions, in bit order.
SNVS registers consist of two types:
• Privileged read/write accessible
• Non-privileged read/write accessible
Privileged read/write accessible registers can only be accessed for read/write by
privileged software. Unauthorized write accesses are ignored, and unauthorized read
accesses return zero. Non-privileged software can access privileged access registers when
the non-privileged software access enable bit is set in the SNVS_HP Command Register.
• Non-Secure
• Trusted
• Secure
Non-privileged read/write accessible registers are read/write accessible by any software.
The LP register values are set only on LP POR and are unaffected by System (HP) POR.
The HP registers are set only on System POR and are unaffected by LP POR.
The following table shows the SNVS main memory map.
NOTE
For more information on security-related bitfields, see the
Security Reference Manual.
6.4.5.1 SNVS register descriptions
6.4.5.1.1 SNVS memory map
SNVS base address: 3037_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
4 SNVS_HP Command Register (HPCOMR) 32 RW 0000_0000
8 SNVS_HP Control Register (HPCR) 32 RW 0000_0000
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Offset (hex) Register Width Access Reset value
(hex)
(In bits)
14 SNVS_HP Status Register (HPSR) 32 RW 8000_0000
24 SNVS_HP Real Time Counter MSB Register (HPRTCMR) 32 RW 0000_0000
28 SNVS_HP Real Time Counter LSB Register (HPRTCLR) 32 RW 0000_0000
2C SNVS_HP Time Alarm MSB Register (HPTAMR) 32 RW 0000_0000
30 SNVS_HP Time Alarm LSB Register (HPTALR) 32 RW 0000_0000
34 SNVS_LP Lock Register (LPLR) 32 RW 0000_0000
38 SNVS_LP Control Register (LPCR) 32 RW 0000_0020
4C SNVS_LP Status Register (LPSR) 32 RW 0000_0008
68 SNVS_LP General Purpose Register 0 (legacy alias) 32 RW 0000_0000
(LPGPR0_legacy_alias)
90 - 9C SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3) 32 RW 0000_0000
BF8 SNVS_HP Version ID Register 1 (HPVIDR1) 32 RO 003E_0103
BFC SNVS_HP Version ID Register 2 (HPVIDR2) 32 RO 0600_0300
6.4.5.1.2 SNVS_HP Command Register (HPCOMR)
The SNVS_HP Command Register contains the command, configuration, and control bits
for the SNVS block. This is a privileged write register.
6.4.5.1.2.1 Offset
Register Offset
HPCOMR 4h
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6.4.5.1.2.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
NPSWA_EN
Reserved
Reserved
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LP_SWR_DIS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LP_SWR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.2.3 Fields
Field Description
31 Non-Privileged Software Access Enable
NPSWA_EN When set, allows non-privileged software to access all SNVS registers, including those that are privileged
software read/write access only.
0 Only privileged software can access privileged registers
1 Any software can access privileged registers
30-20 Reserved
—
19 Reserved
—
18 Reserved
—
17 Reserved
—
16 Reserved
—
15-14 Reserved
—
13 Reserved
—
12-11 Reserved
—
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Field Description
10 Reserved
—
9 Reserved
—
8 Reserved
—
7-6 Reserved
—
5 LP Software Reset Disable
LP_SWR_DIS When set, disables the LP software reset. Once set, this bit can only be reset by the system reset.
0 - LP software reset is enabled
1 - LP software reset is disabled
4 LP Software Reset.
LP_SWR When set to 1, the registers in the SNVS_LP section are reset.
0 - No Action
1 - Reset LP section
3 Reserved
—
2 Reserved
—
1 Reserved
—
0 Reserved
—
6.4.5.1.3 SNVS_HP Control Register (HPCR)
The SNVS_HP Control Register contains various control bits of the HP section of SNVS.
This is not a privileged write register.
6.4.5.1.3.1 Offset
Register Offset
HPCR 8h
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6.4.5.1.3.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BTN_CONFIG
BTN_MASK
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HPCALB_VAL
HPCALB_EN
HPTA_EN
RTC_EN
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.3.3 Fields
Field Description
31-28 Reserved
—
27 Button Interrupt Mask
BTN_MASK This bit is used to mask the button (BTN) interrupt request.
0: Interrupt disabled
1: Interrupt enabled
26-24 Button Configuration
BTN_CONFIG This field is used to configure which feature of the button (BTN) input signal constitutes "active".
000: Button signal is active high
001: Button signal is active low
010: Button signal is active on the falling edge
011: Button signal is active on the rising edge
100: Button signal is active on any edge
All other patterns are Reserved
23-17 Reserved
—
16 Reserved
—
15 Reserved
—
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Field Description
14-10 HP Calibration Value
HPCALB_VAL Defines signed calibration value for the HP Real Time Counter. This field can be programmed only when
RTC Calibration is disabled (HPCALB_EN is not set). This is a 5-bit 2's complement value, hence the
allowable calibration values are in the range from -16 to +15 counts per 32768 ticks of the counter.
00000 - +0 counts per each 32768 ticks of the counter
00001 - +1 counts per each 32768 ticks of the counter
00010 - +2 counts per each 32768 ticks of the counter
01111 - +15 counts per each 32768 ticks of the counter
10000 - -16 counts per each 32768 ticks of the counter
10001 - -15 counts per each 32768 ticks of the counter
11110 - -2 counts per each 32768 ticks of the counter
11111 - -1 counts per each 32768 ticks of the counter
9 Reserved
—
8 HP Real Time Counter Calibration Enabled
HPCALB_EN Indicates that the time calibration mechanism is enabled.
0 - HP Timer calibration disabled
1 - HP Timer calibration enabled
7-2 Reserved
—
1 HP Time Alarm Enable
HPTA_EN When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to
the value of the HP Real Time Counter. This bit syncs with the 32KHz clock. It won't update with the bus
clock.
0 - HP Time Alarm Interrupt is disabled
1 - HP Time Alarm Interrupt is enabled
0 HP Real Time Counter Enable
RTC_EN This bit syncs with the 32KHz clock. It won't update with the bus clock.
0 - RTC is disabled
1 - RTC is enabled
6.4.5.1.4 SNVS_HP Status Register (HPSR)
The HP Status Register reflects the internal state of the SNVS. This is not a privileged
write register.
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6.4.5.1.4.1 Offset
Register Offset
HPSR 14h
6.4.5.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reserved
Reserved
Reserved
Reserved
R
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPDIS
HPTA
BTN
R
BI
Reserved
Reserved
Reserved
Reserved
Reserved
W1C
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.4.3 Fields
Field Description
31 Reserved
—
30-28 Reserved
—
27 Reserved
—
26-25 Reserved
—
24-16 Reserved
—
15-12 Reserved
—
11-8 Reserved
—
7 Button Interrupt
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Field Description
BI Signal ipi_snvs_btn_int_b was asserted.
6 Button
BTN Value of the BTN input. This is the external button used for PMIC control.
0: BTN not pressed
1: BTN pressed
5 Reserved
—
4 Low Power Disable
LPDIS If 1, the low power section has been disabled by means of an input signal to SNVS.
3-2 Reserved
—
1 Reserved
—
0 HP Time Alarm
HPTA Indicates that the HP Time Alarm has occurred since this bit was last cleared.
0 - No time alarm interrupt occurred.
1 - A time alarm interrupt occurred.
6.4.5.1.5 SNVS_HP Real Time Counter MSB Register (HPRTCMR)
The SNVS_HP Real Time Counter MSB register contains the 15 most-significant bits of
the HP Real Time Counter. This is not a privileged write register.
6.4.5.1.5.1 Offset
Register Offset
HPRTCMR 24h
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6.4.5.1.5.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
RTC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.5.3 Fields
Field Description
31-15 Reserved
—
14-0 HP Real Time Counter
RTC The most-significant 15 bits of the RTC. This register can be programmed only when RTC is not active
(RTC_EN bit is not set).
6.4.5.1.6 SNVS_HP Real Time Counter LSB Register (HPRTCLR)
The SNVS_HP Real Time Counter LSB register contains the 32 least-significant bits of
the HP real time counter. This is not a privileged write register.
6.4.5.1.6.1 Offset
Register Offset
HPRTCLR 28h
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6.4.5.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
RTC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RTC
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.6.3 Fields
Field Description
31-0 HP Real Time Counter
RTC least-significant 32 bits. This register can be programmed only when RTC is not active (RTC_EN bit is not
set).
6.4.5.1.7 SNVS_HP Time Alarm MSB Register (HPTAMR)
The SNVS_HP Time Alarm MSB register contains the most-significant bits of the
SNVS_HP Time Alarm value. This is not a privileged write register.
6.4.5.1.7.1 Offset
Register Offset
HPTAMR 2Ch
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6.4.5.1.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HPTA_MS
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.7.3 Fields
Field Description
31-15 Reserved
—
14-0 HP Time Alarm, ms
HPTA_MS HP Time Alarm, most-significant 15 bits.
This register can be programmed only when HP time alarm is disabled (HPTA_EN bit is not set).
6.4.5.1.8 SNVS_HP Time Alarm LSB Register (HPTALR)
The SNVS_HP Time Alarm LSB register contains the 32 least-significant bits of the
SNVS_HP Time Alarm value. This is not a privileged write register.
6.4.5.1.8.1 Offset
Register Offset
HPTALR 30h
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6.4.5.1.8.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
HPTA_LS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HPTA_LS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.8.3 Fields
Field Description
31-0 HP Time Alarm, ls
HPTA_LS HP Time Alarm, 32 least-significant bits.
This register can be programmed only when HP time alarm is disabled (HPTA_EN bit is not set).
6.4.5.1.9 SNVS_LP Lock Register (LPLR)
The SNVS_LP Lock Register contains lock bits for the SNVS_LP registers. This is a
privileged write register.
6.4.5.1.9.1 Offset
Register Offset
LPLR 34h
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6.4.5.1.9.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
Reserved
Reserved
GPR_HL
Reserved
Reserved
Reserved
Reserved
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.9.3 Fields
Field Description
31-29 Reserved
—
28 Reserved
—
27 Reserved
—
26 Reserved
—
25 Reserved
—
24 Reserved
—
23-10 Reserved
—
9 Reserved
—
8 Reserved
—
7 Reserved
—
6 Reserved
—
5 General Purpose Register Hard Lock
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Field Description
GPR_HL When set, prevents any writes to the GPR. Once set, this bit can only be reset by the LP POR.
0 - Write access is allowed.
1 - Write access is not allowed.
4 Reserved
—
3 Reserved
—
2 Reserved
—
1 Reserved
—
0 Reserved
—
6.4.5.1.10 SNVS_LP Control Register (LPCR)
The SNVS_LP Control Register contains various control bits of the LP section of SNVS.
This is a privileged write register.
6.4.5.1.10.1 Offset
Register Offset
LPCR 38h
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6.4.5.1.10.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BTN_PRESS_TIME
PK_OVERRIDE
DEBOUNCE
ON_TIME
Reserved
Reserved
PK_EN
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPWUI_EN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DP_EN
TOP
W
Reset 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
6.4.5.1.10.3 Fields
Field Description
31-25 Reserved
—
24 Reserved
—
23 PMIC On Request Override
PK_OVERRIDE The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override. That signal is
used to override the IOMUX control for the PMIC I/O pad.
22 PMIC On Request Enable
PK_EN The value written to PK_EN will be asserted on output signal snvs_lp_pk_en. That signal is used to turn
off the pullup/pulldown circuitry in the PMIC I/O pad.
21-20 ON_TIME Config
ON_TIME The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is
asserted to turn on the SoC power.
00: 500msec off->on transition time
01: 50msec off->on transition time
10: 100msec off->on transition time
11: 0msec off->on transition time
19-18 Debounce Time Config
DEBOUNCE This field configures the amount of debounce time for the BTN input signal.
00: 50msec debounce
01: 100msec debounce
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Field Description
10: 500msec debounce
11: 0msec debounce
17-16 Button Press Time Out config
BTN_PRESS_TI This field configures the button press time out values for the PMIC Logic.
ME
00 : 5 secs
01 : 10 secs
10 : 15 secs
11 : long press disabled (pmic_en_b will not be asserted regardlessof how long BTN is asserted)
15 Reserved
—
14-10 Reserved
—
9 Reserved
—
8 Reserved
—
7 Reserved
—
6 Turn off System Power
TOP Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power.
This bit will clear once power is off. This bit is only valid when the Dumb PMIC is enabled.
0 - Leave system power on.
1 - Turn off system power.
5 Dumb PMIC Enabled
DP_EN When set, software can control the system power. When cleared, the system requires a Smart PMIC to
automatically turn power off.
0 - Smart PMIC enabled.
1 - Dumb PMIC enabled.
4 Reserved
—
3 LP Wake-Up Interrupt Enable
LPWUI_EN This interrupt line should be connected to the external pin and is intended to inform the external chip
about an SNVS_LP event (MC rollover, SRTC rollover, or time alarm ). This wake-up signal can be
asserted only when the chip (HP section) is powered down, and the LP section is isolated.
0 LP wake-up interrupt is disabled.
1 LP wake-up interrupt is enabled.
2 Reserved
—
1 Reserved
—
0 Reserved
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Secure Non-Volatile Storage (SNVS)
Field Description
—
6.4.5.1.11 SNVS_LP Status Register (LPSR)
The SNVS_LP Status Register reflects the internal state and behavior of the SNVS_LP.
This is a privileged write register.
6.4.5.1.11.1 Offset
Register Offset
LPSR 4Ch
6.4.5.1.11.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W1C SPOF
R
EO
Reserved
Reserved
Reserved
Reserved
Reserved
W1C
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C Reserved
W1C Reserved
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
6.4.5.1.11.3 Fields
Field Description
31 Reserved
—
30 Reserved
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Field Description
—
29-20 Reserved
—
19 Reserved
—
18 Set Power Off
SPOF The SPO bit is set when the power button is pressed longer than the configured debounce time. Writing
to the SPO bit will clear the set_pwr_off_irq interrupt.
0 - Set Power Off was not detected.
1 - Set Power Off was detected.
17 Emergency Off
EO This bit is set when a power off is requested.
0 - Emergency off was not detected.
1 - Emergency off was detected.
16 Reserved
—
15-11 Reserved
—
10 Reserved
—
9 Reserved
—
8-7 Reserved
—
6-4 Reserved
—
3 Reserved
—
2 Reserved
—
1-0 Reserved
—
6.4.5.1.12 SNVS_LP General Purpose Register 0 (legacy alias)
(LPGPR0_legacy_alias)
See register SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3).
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Secure Non-Volatile Storage (SNVS)
6.4.5.1.12.1 Offset
Register Offset
LPGPR0_legacy_alias 68h
6.4.5.1.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.12.3 Fields
Field Description
31-0 General Purpose Register
GPR When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
6.4.5.1.13 SNVS_LP General Purpose Registers 0 .. 3 (LPGPR0 - LPGPR3)
The SNVS_LP General Purpose Register is a 128-bit read/write register located in
SNVS_LP, which can be used by any application for retaining data during an SoC power-
down mode. This is a privileged read/write register. The full GPR register is accessed as
4 32-bit registers located in successive word addresses starting at offset 90h. For
backward compatibility with earlier versions of SNVS, LPGPR0 is also aliased at its
original offset of 68h. New software should access the GPR register at the preferred
offset of 90h.
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6.4.5.1.13.1 Offset
Register Offset
LPGPR0 90h
LPGPR1 94h
LPGPR2 98h
LPGPR3 9Ch
6.4.5.1.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
GPR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.4.5.1.13.3 Fields
Field Description
31-0 General Purpose Register
GPR When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
6.4.5.1.14 SNVS_HP Version ID Register 1 (HPVIDR1)
The SNVS_HP Version ID Register 1 is a non-privileged read-only register that contains
the current version of the SNVS. The version consists of a module ID, a major version
number, and a minor version number.
6.4.5.1.14.1 Offset
Register Offset
HPVIDR1 BF8h
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6.4.5.1.14.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IP_ID
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MAJOR_REV MINOR_REV
W
Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
6.4.5.1.14.3 Fields
Field Description
31-16 Block ID
IP_ID SNVS block ID
15-8 Major Version Number
MAJOR_REV SNVS block major version number
7-0 Minor Version Number
MINOR_REV SNVS block minor version number
6.4.5.1.15 SNVS_HP Version ID Register 2 (HPVIDR2)
The SNVS_HP Version ID Register 2 is a non-privileged read-only register that indicates
the current version of the SNVS. Version ID register 2 consists of the following fields:
integration options, ECO revision, and configuration options.
6.4.5.1.15.1 Offset
Register Offset
HPVIDR2 BFCh
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6.4.5.1.15.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IP_ERA
Reserved
W
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R ECO_REV
Reserved
W
Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
6.4.5.1.15.3 Fields
Field Description
31-24 IP Era
IP_ERA 00h - Era 1 or 2
03h - Era 3
04h - Era 4
05h - Era 5
06h - Era 6
23-16 Reserved
—
15-8 ECO Revision
ECO_REV SNVS ECO Revision
The engineering change order revision number for this release of SNVS.
7-0 Reserved
—
6.5 System Reset Controller (SRC)
6.5.1 Overview
The System Reset Controller (SRC) is responsible for the generation of all the system
reset signals and boot argument latching.
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6.5.1.1 Features
The SRC includes the following features.
• Receives and handles the resets from all the reset sources
• Resets the appropriate domains based upon the resets sources and the nature of the
reset
• Latches the SRC_BOOT_MODE pins and common configuration signals from the
internal fuse
6.5.2 Functional Description
The reset controller determines the source and the type of reset, such as POR, COLD, and
performs the necessary reset qualification and stretching sequences. Based on the type of
reset, the reset logic generates the reset sequence for the entire IC. Whenever the chip is
powered on, the reset is issued through SRC_ONOFF signal and the entire chip is reset.
6.5.2.1 Reset and Power-up Flow
The chip presumes the following reset and power-up flow:
External
PMIC
(button) POR_B
SRC_POR_B
PMIC_STBY_REQ GPC
PMIC_ON_REQ SoC resets
SNVS ipp_reset_b
wake-up
alarm
FSM irq
SRC
ONOFF
(No Connect)
ipp_user_reset_b
TEST_MODE
PMIC_ON_REQ acts as power-on alarm:
0->1 = power-on by alarm
PMIC_STBY_REQ enters and exits PMIC standby
0->1 = enter standby
1-> 0 = wake-up from standby
Figure 6-28. Chip reset scheme under external PMIC control
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Reset
Button press longer
than the max timeout or
Software enabled shutdown
ON
Wakeup or button press longer OFF
than Off to On configuration
Figure 6-29. Chip on/off state flow diagram
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System Reset Controller (SRC)
6.5.2.2 Finite-State Machine (FSM)
ON
alarm positive edge
button pressed < 5s. button pressed > 5s.
emgergency off
generate irq
log emgergency off
alarm negative edge
OFF
button pressed (any duration)
Figure 6-30. FSM
6.5.2.3 Power mode transitions
Table 6-41. Power mode transitions
Power mode Configuration with external PMIC Configuration with internal PMIC
ON, first time 1. SoC power supply is connected to SNVS. 1. SoC power supply is connected to SNVS.
2. When button is pressed, PMIC powers 2. When button is pressed, 'state' goes ON,
on. PMIC_ON_REQ goes '1'.
3. External regulator is enabled.
Normal ON to OFF, 1. Button is pressed for a short duration on 1. SoC button is pressed for a short duration of
by button the external PMIC. 50ms/100ms/500ms, which can be selected by
2. Interrupt request (irq) is sent to SoC from configuring SNVS_LP register
external PMIC. “SNVS_REG_LPCR” bit[19:18].
3. SoC is programming PMIC for power off 2. Interrupt request (irq) is sent to SoC from FSM.
when standby is asserted.
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Table 6-41. Power mode transitions (continued)
Power mode Configuration with external PMIC Configuration with internal PMIC
4. In CCM STOP mode, Standby is 3. If SNVS_REG_LPCR bit[6]), is configured to
asserted, PMIC gates SoC supplies. be 1, then after about 16~18 cycles (32K
clock), PMIC_ON_REQ will be 0.
5. External regulator goes OFF.
Emergency ON to 1. Button is pressed for an extended time on 1. Button is pressed for longer than 5 seconds on
OFF, by button the external PMIC. the SoC.
2. PMIC is powering off. 2. FSM validates button pressed for 5 seconds.
3. Emergency power off is logged,
PMIC_ON_REQ goes '0', alarm_mask goes '1'.
4. External regulator goes OFF.
OFF to ON, by 1. Button is pressed on the external PMIC. 1. Button is pressed on the SoC.
button 2. PMIC powers ON. 2. PMIC_ON_REQ goes '1', alarm_mask goes '0'.
3. External regulator powers ON.
OFF to ON, by timer 1. Timer alarm in SNVS is programmed by 1. Timer alarm in SNVS is programmed by
alarm software before SoC goes OFF. software before SoC goes OFF.
2. SoC enters OFF mode. 2. SoC enters OFF mode.
3. Upon timer limit, wake up alarm goes '0'. 3. Upon timer limit, wake up alarm goes '0'.
PMIC_ON_REQ goes '1'. PMIC_ON_REQ goes '1'.
4. PMIC receives assertion of 4. External regulator is enabled by
PMIC_ON_REQ and wakes up. PMIC_ON_REQ = 1.
6.5.2.4 Reset Control
This section details the reset control of this device.
6.5.2.4.1 Reset inputs and outputs
The reset control logic receives reset requests from all potential reset sources. All the
immediate sources of reset are directly passed to the reset stretching block, whereas the
resets requiring qualification are passed on to the reset qualification logic before they are
sent to the reset stretching block.
All reset inputs and outputs are described in the following figure:
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System Reset Controller (SRC)
SRC
COLD System module reset (system_early_rst_b)
CSU Reset (csu_reset_b)
COLD
Functional module reset (system_rst_b)
SRC_ONOFF (ipp_user_reset_b)
COLD
WDOG_RST_B_DEB (wdog_rst_b) Arm Reset (arm_rst_b)
COLD
SJC S/W Reset (jtag_sw_rst) M7 Reset (m7c_rst_b, m7p_rst_b)
POR (no SJC)
SJC_TRST_B (jtag_rst_b) EIM Reset (eim_rst_b)
POR
SRC_POR_B (ipp_reset_b)
Arm POR (arm_por_rst_b)
SJC Reset (sjc_por_rst_b)
Figure 6-31. SRC inputs and outputs
The reset types and modules they affect are shown in Table 6-42. As there is no chip
POR, the POR_B is used to reset the entire chip including test logic and JTAG modules.
NOTE
All resets are expected to be active low except jtag_sw_rst.
Table 6-42. SRC reset functionality
SoC Modules POR COLD
System modules (PLLs, fuses, etc) yes yes
Functional modules yes yes
Arm yes yes
Arm SoC yes yes
M7 Core yes yes
M7 Platform yes yes
Arm POR yes no
Arm debug yes no
SJC yes no
SRTC yes no
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The reset priorities are POR (strongest) and COLD (weakest). If a stronger reset is
asserted during the sequence of a weaker reset, then the weaker sequence will be
overridden, and the stronger reset sequence will commence. There is no priority within a
reset type (POR, etc). If a reset is asserted during the reset sequence of the same type, the
reset sequence will be interrupted and restarted.
The following lists the functionality of each of these reset outputs:
• system_early_rst_b - Resets the system modules that need to start first as CCM,
OCOTP_CTRL, FUSEBOX, etc.
• system_rst_b - Resets functional modules
• arm_rst_b - Resets Arm module (on regular system reset)
• arm_por_rst_b - Resets Arm POR input
• arm_soc_rst_b - Reset for Arm SOC
• m7c_rst_b - Reset for M7 core
• m7p_rst_b - Reset for M7 platform
• arm_dbg_rst_b - Reset debug logic of Arm
• test_logic_rst_b - Reset test logic (IOMUXC, DAP)
• sjc_por_rst_b - Reset to SJC
• srtc_rst_b - Resets SRTC
NOTE
It is assumed that each reset source will deassert after its
assertion, either due to reset generated to the system from SRC,
or by negation of the reset source (if it came from an external
source to the chip). In the latter case, the reset source is
assumed to be held for at least 2 XTALI clocks so it can be
sampled by SRC.
6.5.2.4.2 Reset Handling
6.5.2.4.2.1 POR (SRC_POR_B)
SRC_POR_B is an external reset signal of the SRC module. When the chip is powered
up, the reset signal is passed through the POR_B pin indicating power-up sequence. The
SRC resets the entire chip including the JTAG (SJC) module. All SRC registers will be
reset during the POR sequence.
As soon as SRC_POR_B occurs, all resets are asserted and the entire chip is reset by
SRC. The SRC_POR_B is stretched for 2 XTALI cycles and the stretching sequence
takes place after 2 XTALI clocks of POR_B pin deassertion.
The srtc_rst_b signal is deasserted together with SRC_POR_B signal. The output are also
deasserted after the stretching of SRC_POR_B has deasserted.
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The sjc_por_rst_b signal is deasserted together with SRC_POR_B signal. The output is
also deasserted after the stretching of SRC_POR_B has deasserted.
After the above resets deassert, system_early_rst_b reset is deasserted after 2 XTALI
clocks. The system_early_rst_b is used for the CCM and PLL-IPs to start generating PLL
clock ouputs and the system root clocks.
When the system root clocks are ready, the CCM will assert system_clk_ready signal.
This signal is generated during the start sequence in the CCM and it involves the
preparation of the PLLs to generate clock roots for functional operation.
SRC then enables OCOTP_CTRL and fusebox clocks, so that fuses can be loaded to
OCOTP_CTRL.
• SRC will prepare the boot information
• After 8 ipg cycles, resets to all modules will be de-asserted
• After 8 ipg cycles, system clocks will be enabled (en_system_clk).
6.5.2.4.2.2 COLD RESET
The sequence is similar to SRC_POR_B except the memory repair operation is not
performed.
After the reset source deasserts, system_early_rst_b reset is deasserted after at least 2
XTALI clocks. The system_early_rst_b is used for the CCM and PLL-IPs to start
generating PLL clock outputs and the system root clocks.
After the system root clocks are ready, the CCM will assert system_clk_ready signal.
This signal is generated during the start sequence in the CCM and it involves the
preparation of the PLLs to generate clock roots for functional operation. See CCM for
more information.
After system_clk_ready arrives at the SRC, it will enable OCOTP_CTRL and fusebox
clocks, so that fuses can be loaded to OCOTP_CTRL. OCOTP_CTRL will notify with
iim_ready_flag when the fusebox loading finishes.
• SRC will prepare the boot information
• After 8 ipg cycles resets to all modules will be deasserted
• After 8 ipg cycles, system clocks will be enabled (en_system_clk).
6.5.2.5 Parallel Reset Requests
SRC will follow the following rules in the case of parallel reset requests:
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1. The order of strength of resets is POR - strongest, COLD - weakest
2. If a stronger reset is asserted during weaker reset sequence, then the stronger reset
will take over and the stronger reset process will commence. The following cases fall
into this category:
• POR reset request in the middle of cold reset process - the cold will be stopped
and the POR sequence will start.
3. If a weaker reset is asserted during stronger reset sequence, then the stronger reset
sequence will continue without interference. If at the end of the stronger reset process
the weaker request is still asserted then the weaker sequence will commence. The
following cases fall into this category:
• COLD reset requests in the middle of POR reset process - the POR process will
continue without interference.
4. If a similar reset request is asserted during the process of reset handling, then the
process of reset handling will start over (with the same process). The following cases
fall into this category:
• POR reset request in the middle of POR reset process - the POR process will
start over.
• COLD reset request in the middle of COLD reset process - the COLD process
will start over.
6.5.2.6 Boot Mode Control
6.5.2.6.1 BOOT_MODE Pin Latching
The exact boot sequence is controlled by the values of the BOOT_MODE pins on this
device.
The value of the BOOT_MODE pins will be latched on de-assertion of POR reset. After
latching, the values of the BOOT_MODE pins are used to determine the booting options
of the core as described in the SRC_SBMRx registers.
The boot mode general purpose bits can be provided to the SRC from either e-fuses or
GPIO signals. The gpio_bt_sel e-fuse defines the source to be used to derive the boot
information. When gpio_bt_sel is set, e-fuses are used. When cleared, GPIO signals are
used.
The boot information is provided in SRC_SBMR1 and SRC_SBMR2 registers. The
figure below shows the selection of boot mode information.
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BOOT_MODE1
BOOT_MODE0
BOOT_MODE0
BOOT_MODE1
GPIO_BT_SEL_FUSE
BOOT_MODE0
BOOT_MODE1
BOOT_CFG[19:16]
BOOT_CFG[15:8]
0
BOOT_CFG[7:0]
SRC_SBMR1
Register
chip
fuses BOOT_CFG[19:16]
e-fuse signals
BOOT_CFG[15:8] 1
BOOT_CFG[7:0]
Figure 6-32. Boot mode information
6.5.3 External Signals
The following table describes the external signals of SRC.
6.5.4 Initialization
6.5.4.1 Power-On Reset and power sequencing
The SRC module generates an internal POR_B signal that is logically AND'ed with any
externally applied SRC_POR_B signal. The internal POR_B signal will be held low until
all of the following conditions are met:
• 4ms after the external power supply VDDHIGH_IN is valid
• 1ms after the VDD_SOC_CAP supply is valid
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The 4ms and 1ms delays are derived from counting the 32 kHz RTC clock cycles; the
accuracy depends on the accuracy of the RTC.
6.5.4.1.1 External POR using SRC_POR_B
If the external SRC_POR_B signal is used to control the processor POR, SRC_POR_B
must remain low (asserted) until the VDD_ARM_CAP and VDD_SOC_CAP supplies
are stable.
6.5.4.1.2 Internal POR
If the external SRC_POR_B signal is not used (always held high or left unconnected), the
processor defaults to the internal POR function (PMU controls generation of the POR
based on the power supplies).
If the internal POR function is used, the following power supply requirements must be
met:
• VDD_ARM_IN and VDD_SOC_IN may be supplied from the same source, or
• VDD_SOC_IN can be supplied before VDD_ARM_IN with a maximum delay of 1
ms.
6.5.5 SRC Memory Map/Register Definition
SRC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3039_0000 SRC Reset Control Register (SRC_SCR) 32 R/W 0000_00A0h 6.5.5.1/915
3039_0004 A53 Reset Control Register (SRC_A53RCR0) 32 R/W 000A_0000h 6.5.5.2/917
3039_0008 A53 Reset Control Register (SRC_A53RCR1) 32 R/W 0000_0001h 6.5.5.3/922
3039_000C M7 Reset Control Register (SRC_M7RCR) 32 R/W 0000_00A8h 6.5.5.4/925
SUPERMIX Reset Control Register
3039_0018 32 R/W 0000_0000h 6.5.5.5/927
(SRC_SUPERMIX_RCR)
3039_001C AUDIOMIX Reset Control Register (SRC_AUDIOMIX_RCR) 32 R/W 0000_0000h 6.5.5.6/929
3039_0020 USB PHY1 Reset Control Register (SRC_USBPHY1_RCR) 32 R/W 0000_0000h 6.5.5.7/930
3039_0024 USB PHY2 Reset Control Register (SRC_USBPHY2_RCR) 32 R/W 0000_0000h 6.5.5.8/932
3039_0028 MLMIX Reset Control Register (SRC_MLMIX_RCR) 32 R/W 0000_0000h 6.5.5.9/933
3039_002C PCIE PHY Reset Control Register (SRC_PCIEPHY_RCR) 32 R/W 0000_000Ah 6.5.5.10/935
3039_0030 HDMI Reset Control Register (SRC_HDMI_RCR) 32 R/W 0000_0000h 6.5.5.11/938
3039_0034 MEDIAMIX Reset Control Register (SRC_MEDIA_RCR) 32 R/W 0000_0000h 6.5.5.12/939
3039_0038 GPU2D Reset Control Register (SRC_GPU2D_RCR) 32 R/W 0000_0000h 6.5.5.13/941
Table continues on the next page...
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SRC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3039_003C GPU3D Reset Control Register (SRC_GPU3D_RCR) 32 R/W 0000_0000h 6.5.5.14/942
3039_0040 GPU Reset Control Register (SRC_GPU_RCR) 32 R/W 0000_0000h 6.5.5.15/944
3039_0044 VPU Reset Control Register (SRC_VPU_RCR) 32 R/W 0000_0000h 6.5.5.16/945
3039_0048 VPU G1 Reset Control Register (SRC_VPU_G1_RCR) 32 R/W 0000_0000h 6.5.5.17/947
3039_004C VPU G2 Reset Control Register (SRC_VPU_G2_RCR) 32 R/W 0000_0000h 6.5.5.18/948
VPU VC8000E Reset Control Register
3039_0050 32 R/W 0000_0000h 6.5.5.19/950
(SRC_VPUVC8KE_RCR)
3039_0054 NOC Wrapper Reset Control Register (SRC_NOC_RCR) 32 R/W 0000_0000h 6.5.5.20/951
3039_0058 SRC Boot Mode Register 1 (SRC_SBMR1) 32 R 0000_0000h 6.5.5.21/953
3039_005C SRC Reset Status Register (SRC_SRSR) 32 R/W 0000_0001h 6.5.5.22/953
3039_0068 SRC Interrupt Status Register (SRC_SISR) 32 R/W 0000_0000h 6.5.5.23/956
3039_006C SRC Interrupt Mask Register (SRC_SIMR) 32 R/W 0000_03FFh 6.5.5.24/958
3039_0070 SRC Boot Mode Register 2 (SRC_SBMR2) 32 R 0000_0000h 6.5.5.25/960
3039_0074 SRC General Purpose Register 1 (SRC_GPR1) 32 R/W 0000_0000h 6.5.5.26/962
3039_0078 SRC General Purpose Register 2 (SRC_GPR2) 32 R/W 0000_0000h 6.5.5.27/962
3039_007C SRC General Purpose Register 3 (SRC_GPR3) 32 R/W 0000_0000h 6.5.5.28/962
3039_0080 SRC General Purpose Register 4 (SRC_GPR4) 32 R/W 0000_0000h 6.5.5.29/963
3039_0084 SRC General Purpose Register 5 (SRC_GPR5) 32 R/W 0000_0000h 6.5.5.30/963
3039_0088 SRC General Purpose Register 6 (SRC_GPR6) 32 R/W 0000_0000h 6.5.5.31/964
3039_008C SRC General Purpose Register 7 (SRC_GPR7) 32 R/W 0000_0000h 6.5.5.32/964
3039_0090 SRC General Purpose Register 8 (SRC_GPR8) 32 R/W 0000_0000h 6.5.5.33/964
3039_0094 SRC General Purpose Register 9 (SRC_GPR9) 32 R/W 0000_0000h 6.5.5.34/965
3039_0098 SRC General Purpose Register 10 (SRC_GPR10) 32 R/W 0000_0000h 6.5.5.35/965
SRC DDR Controller Reset Control Register
3039_1000 32 R/W 0000_000Fh 6.5.5.36/966
(SRC_DDRC_RCR)
3039_1008 HDMIPHY Reset Control Register (SRC_HDMIPHY_RCR) 32 R/W 0000_0000h 6.5.5.37/968
3039_100C MIPI PHY1 Reset Control Register (SRC_MIPIPHY1_RCR) 32 R/W 0000_0000h 6.5.5.38/969
3039_1010 MIPI PHY2 Reset Control Register (SRC_MIPIPHY2_RCR) 32 R/W 0000_0000h 6.5.5.39/971
3039_1014 HSIO Reset Control Register (SRC_HSIO_RCR) 32 R/W 0000_0000h 6.5.5.40/972
MEDIAMIX ISP and Dewarp Reset Control Register
3039_1018 32 R/W 0000_0000h 6.5.5.41/974
(SRC_MEDIAISPDWP_RCR)
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6.5.5.1 SRC Reset Control Register (SRC_SCR)
The reset control register (SCR), contains bits that control operation of the reset
controller.
Address: 3039_0000h base + 0h offset = 3039_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
R
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASK_TEMPSENSE_
Reserved Reserved
RESET
W
Reset 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
SRC_SCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
Table continues on the next page...
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SRC_SCR field descriptions (continued)
Field Description
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–8 This field is reserved.
- Reserved
7–4 Mask tempsense_reset source. If these 4 bits are coded from A to 5 then, the tempsense_reset input to
MASK_ SRC will be masked and the tempsense_reset will not create a reset to the chip.
TEMPSENSE_
RESET 0101 tempsense_reset is masked
1010 tempsense_reset is not masked
- This field is reserved.
Reserved
6.5.5.2 A53 Reset Control Register (SRC_A53RCR0)
The A53 Reset Control Register (A53RCR), contains bits that control the A53 reset
generation.
Address: 3039_0000h base + 4h offset = 3039_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A53_SOC_DBG_
A53_L2RESET
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
RESET
LOCK
Reserved Reserved MASK_WDOG1_RST
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_DBG_RESET3
A53_DBG_RESET2
A53_DBG_RESET1
A53_DBG_RESET0
A53_ETM_RESET3
A53_ETM_RESET2
A53_ETM_RESET1
A53_ETM_RESET0
A53_CORE_POR_
A53_CORE_POR_
A53_CORE_POR_
A53_CORE_POR_
R
A53_CORE_
A53_CORE_
A53_CORE_
A53_CORE_
RESET3
RESET2
RESET1
RESET0
RESET3
RESET2
RESET1
RESET0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_A53RCR0 field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–22 This field is reserved.
- Reserved
21
A53_L2RESET Software reset for A53 Snoop Control Unit (SCU).
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert SCU reset
1 assert SCU reset
20
A53_SOC_DBG_ Software reset for system level debug reset. It initializes the shared Debug APB, the CTI, and the CTM. It
RESET also causes:
• A53_dbgreset[3:0] and A53_etmreset[3:0] to be asserted
• debug logic in the processor power domain and in the debug power domain to be reset
Table continues on the next page...
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SRC_A53RCR0 field descriptions (continued)
Field Description
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert system level debug reset
1 assert system level debug reset
19–16
MASK_WDOG1_ Mask wdog1_rst_b source. If these 4 bits are coded from A to 5 then, the wdog1_rst_b input to SRC will
RST be masked and the wdog1_rst_b will not create a reset to the chip.
NOTE: During the time the WDOG event is masked using SRC logic, it is likely that the WDOG Reset
Status Register (WRSR) bit 1 (which indicates a WDOG timeout event) will get asserted.
software / OS developer must prepare for this case. Re-enabling the WDOG is possible, by un-
masking it in SRC, though it must be preceded by servicing the WDOG. However, for the case
that the event has been asserted, the status bit (WRSR bit-1) will remain asserted, regardless of
servicing the WDOG module.
(Hardware reset is the only way to cause the de-assertion of that bit). Any other code will be coded to
1010 i.e. wdog1_rst_b is not masked
0101 wdog1_rst_b is masked
1010 wdog1_rst_b is not masked
15 Software reset for core3 ETM only.
A53_ETM_
RESET3 NOTE: This is a self clearing bit. Once it is set to 1, the rest process will begin, and once it finished, this
bit will be self-cleared.
0 do not assert core3 ETM reset
1 assert core3 ETM reset
14 Software reset for core2 ETM only.
A53_ETM_
RESET2 NOTE: This is a self clearing bit. Once it is set to 1, the rest process will begin, and once it finished, this
bit will be self-cleared.
0 do not assert core2 ETM reset
1 assert core2 ETM reset
13
A53_ETM_ Software reset for core1 ETM only.
RESET1
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core1 ETM reset
1 assert core1 ETM reset
12
A53_ETM_ Software reset for core0 ETM only.
RESET0
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core0 ETM reset
1 assert core0 ETM reset
11
A53_DBG_ Software reset for core3 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET3 core3 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.
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SRC_A53RCR0 field descriptions (continued)
Field Description
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core3 debug reset
1 assert core3 debug reset
10
A53_DBG_ Software reset for core2 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET2 core2 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core2 debug reset
1 assert core2 debug reset
9
A53_DBG_ Software reset for core1 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET1 core1 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core1 debug reset
1 assert core1 debug reset
8
A53_DBG_ Software reset for core0 debug only. It initialize the debug, and breakpoint and watchpoint logic in the
RESET0 core1 processor power domain. It also reset the debug logic for core1 processor, which is in the debug
power domain.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core0 debug reset
1 assert core0 debug reset
7
A53_CORE_ Software reset for core3 only. It initializes the processor logic in the core1 processor power domains, not
RESET3 including the debug, breakpoint and watchpoint logic.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core3 reset
1 assert core3 reset
6
A53_CORE_ Software reset for core2 only. It initializes the processor logic in the core1 processor power domains, not
RESET2 including the debug, breakpoint and watchpoint logic.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core2 reset
1 assert core2 reset
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SRC_A53RCR0 field descriptions (continued)
Field Description
5
A53_CORE_ Software reset for core1 only. It initializes the processor logic in the core1 processor power domains, not
RESET1 including the debug, breakpoint and watchpoint logic.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core1 reset
1 assert core1 reset
4
A53_CORE_ Software reset for core0 only. It initializes the processor logic in the core0 processor power domains, not
RESET0 including the debug, breakpoint and watchpoint logic.
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core0 reset
1 assert core0 reset
3
A53_CORE_ POR reset for A53 core3 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET3 breakpoint and watchpoint logic in the core3 processor power domains
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core3 reset
1 assert core3 reset
2
A53_CORE_ POR reset for A53 core2 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET2 breakpoint and watchpoint logic in the core2 processor power domains
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core2 reset
1 assert core2 reset
1
A53_CORE_ POR reset for A53 core1 only. It initializes all the core1 processor logic, including CPU Debug, and
POR_RESET1 breakpoint and watchpoint logic in the core1 processor power domains
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core1 reset
1 assert core1 reset
0
A53_CORE_ POR reset for A53 core0 only. It initializes all the core0 processor logic, including CPU Debug, and
POR_RESET0 breakpoint and watchpoint logic in the core0 processor power domains
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared.
0 do not assert core0 reset
1 assert core0 reset
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6.5.5.3 A53 Reset Control Register (SRC_A53RCR1)
The A53 Reset Control Register (A53RCR), contains bits that control the A53 reset
generation.
Address: 3039_0000h base + 8h offset = 3039_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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System Reset Controller (SRC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
A53_CORE0_ENABLE
R
A53_CORE3_ENABLE
A53_CORE2_ENABLE
A53_CORE1_ENABLE
Reserved A53_RST_SLOW
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SRC_A53RCR1 field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
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SRC_A53RCR1 field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–7 This field is reserved.
- Reserved
6–4 A53_RST_SLOW
A53_RST_SLOW
3 core 3 enable
A53_CORE3_
ENABLE 0 core3 is disabled
1 core3 is enabled
2 core 2 enable
A53_CORE2_
ENABLE 0 core2 is disabled
1 core2 is enabled
1 core 1 enable
A53_CORE1_
ENABLE 0 core1 is disabled
1 core1 is enabled
0 Always 1, can't be changed.
A53_CORE0_
ENABLE
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6.5.5.4 M7 Reset Control Register (SRC_M7RCR)
The M7 Reset Control Register (M7RCR), contains bits that control the M7 reset
generation.
Address: 3039_0000h base + Ch offset = 3039_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDOG3_RST_OPTION_
SW_M7C_NON_SCLR_
WDOG3_RST_OPTION
SW_M7C_RST
ENABLE_M7
Reserved
RST
M7
Reserved MASK_WDOG3_RST
Reset 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
SRC_M7RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
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SRC_M7RCR field descriptions (continued)
Field Description
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–10 This field is reserved.
- Reserved
9 Wdog3_rst_b option
WDOG3_RST_
OPTION 0 Wdog3_rst_b asserts M7 reset
1 Wdog3_rst_b asserts global reset
8 Wdog3_rst_b option for M7. This bit is only effective when wdog3_rst_option is set to 1.
WDOG3_RST_
OPTION_M7 0 wdgo3_rst_b Reset M7 core only
1 Reset both M7 core and platform
7–4
MASK_WDOG3_ Mask wdog3_rst_b source. If these 4 bits are coded from A to 5 then, the wdog3_rst_b input to SRC will
RST be masked and the wdog3_rst_b will not create a reset to the chip.
NOTE: During the time the WDOG3 event is masked using SRC logic, it is likely that the WDOG3 Reset
Status Register (WRSR) bit 1 (which indicates a WDOG3 timeout event) will get asserted.
Software / OS developer must prepare for this case. Re-enabling the WDOG3 is possible, by un-
masking it in SRC, though it must be preceded by servicing the WDOG3. However, for the case
that the event has been asserted, the status bit (WRSR bit-1) will remain asserted, regardless of
servicing the WDOG3 module.
(Hardware reset is the only way to cause the de-assertion of that bit). Any other code will be coded to
1010 i.e. wdog3_rst_b is not masked
0101 wdog3_rst_b is masked
1010 wdog3_rst_b is not masked
3 Enable M7
ENABLE_M7
0 M7 is disabled
1 M7 is enabled
2 This field is reserved.
- Reserved
Table continues on the next page...
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SRC_M7RCR field descriptions (continued)
Field Description
1
SW_M7C_RST Self-clearing SW reset for M7 core
NOTE: This is a self clearing bit. Once it is set to 1, the reset process will begin, and once it finishes, this
bit will be self cleared. Software can determine that the reset has finished once this bit is cleared.
Software can also configure SRC to generate interrupt once the software has finished. Please
refer to SRC_SISR register for details.
0 do not assert M7 core reset
1 assert M7 core reset
0 Non-self-clearing SW reset for M7 core
SW_M7C_NON_
SCLR_RST 0 do not assert M7 core reset
1 assert M7 core reset
6.5.5.5 SUPERMIX Reset Control Register (SRC_SUPERMIX_RCR)
The SUPERMIX Reset Control Register contains bits that control the SUPERMIX reset
generation.
Address: 3039_0000h base + 18h offset = 3039_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUPERMIX_
R
Reserved RESET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_SUPERMIX_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
Table continues on the next page...
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SRC_SUPERMIX_RCR field descriptions (continued)
Field Description
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for SUPERMIX
SUPERMIX_
RESET 0 Do not assert SUPERMIX reset
1 Assert SUPERMIX reset
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6.5.5.6 AUDIOMIX Reset Control Register (SRC_AUDIOMIX_RCR)
The AUDIOMIX Reset Control Register contains bits that control the AUDIOMIX reset
generation.
Address: 3039_0000h base + 1Ch offset = 3039_001Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUDIOMIX_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_AUDIOMIX_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
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SRC_AUDIOMIX_RCR field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for AUDIOMIX
AUDIOMIX_
RESET 0 Do not assert AUDIOMIX reset
1 Assert AUDIOMIX reset
6.5.5.7 USB PHY1 Reset Control Register (SRC_USBPHY1_RCR)
The USB PHY1 Reset Control Register (SRC_IP_RCR2), contains bits that control the
USB PHY1 reset generation.
Address: 3039_0000h base + 20h offset = 3039_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB1_PHY_RES
Reserved
ET
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_USBPHY1_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for USB 1 PHY
USB1_PHY_RES
ET 0 Don't reset USB 1 PHY
1 Reset USB 1 PHY
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6.5.5.8 USB PHY2 Reset Control Register (SRC_USBPHY2_RCR)
The USB PHY2 Reset Control Register (SRC_IP_RCR2), contains bits that control the
USB PHY2 reset generation.
Address: 3039_0000h base + 24h offset = 3039_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USB2_PHY_RES
R
Reserved
ET
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_USBPHY2_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
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SRC_USBPHY2_RCR field descriptions (continued)
Field Description
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 0 Don't reset USB 2 PHY
USB2_PHY_RES 1 Reset USB 2 PHY
ET
6.5.5.9 MLMIX Reset Control Register (SRC_MLMIX_RCR)
The MLMIX Reset Control Register contains bits that control the MLMIX reset
generation.
Address: 3039_0000h base + 28h offset = 3039_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MLMIX_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_MLMIX_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for MLMIX
MLMIX_RESET
0 Do not assert MLMIX reset
1 Assert MLMIX reset
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6.5.5.10 PCIE PHY Reset Control Register (SRC_PCIEPHY_RCR)
The PCIE PHY Control Register (SRC_PCIEPHY_RCR), contains bits that control the
PCIE PHY reset generation.
Address: 3039_0000h base + 2Ch offset = 3039_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PCIE_CTRL_APP_XFER_
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
PENDING
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIE_PHY_POWER_ON_
PCIE_CTRL_APPS_CLK_
PCIE_CTRL_APPS_EXIT
PCIE_CTRL_APPS_PME
PCIE_CTRL_APPS_RST
PCIE_CTRL_APPS_EN
PCIE_CTRL_CFG_L1_
PCIE_CTRL_SYS_INT
PCIE_CTRL_APPS_
PCIE_CTRL_APPS_
PCIE_CTRL_APPS_
PCIEPHY_BTNRST
PCIE_CTRL_APP_
PCIEPHY_PERST
R
UNLOCK_MSG
TURNOFF
Reserved
Reserved
READY
ENTER
RESET
REQ
AUX
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
SRC_PCIEPHY_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
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SRC_PCIEPHY_RCR field descriptions (continued)
Field Description
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–17 This field is reserved.
- Reserved
16 PCIE_CTRL_APP_XFER_PENDING
PCIE_CTRL_
APP_XFER_
PENDING
15 PCIE_CTRL_APP_UNLOCK_MSG
PCIE_CTRL_
APP_UNLOCK_
MSG
14 PCIE_CTRL_SYS_INT
PCIE_CTRL_
SYS_INT
13 This field is reserved.
-
12 Pcie_ctrl_cfg_l1_aux_clk_switch_core_clk_gate_en
PCIE_CTRL_
CFG_L1_AUX
11 Pcie_ctrl_apps_pm_xmt_turnoff
PCIE_CTRL_
APPS_
TURNOFF
10 Pcie_ctrl_apps_pm_xmt_pme
PCIE_CTRL_
APPS_PME
9 Pcie_ctrl_app_req_exit_l1
PCIE_CTRL_
APPS_EXIT
8 Pcie_ctrl_app_req_entr_l1
PCIE_CTRL_
APPS_ENTER
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SRC_PCIEPHY_RCR field descriptions (continued)
Field Description
7 Pcie_ctrl_app_ready_entr_l23
PCIE_CTRL_
APPS_READY
6 Pcie_ctrl_app_ltssm_enable
PCIE_CTRL_
APPS_EN
5 Pcie_ctrl_app_init_rst
PCIE_CTRL_
APPS_RST
4 Pcie_ctrl_app_clk_req_n
PCIE_CTRL_
APPS_CLK_REQ
3 Pciephy_perst
PCIEPHY_
PERST
2 PCIE PHY button
PCIEPHY_BTNR
ST
1 This field is reserved.
- Reserved
0 PCIE_PHY_POWER_ON_RESET
PCIE_PHY_
POWER_ON_
RESET
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6.5.5.11 HDMI Reset Control Register (SRC_HDMI_RCR)
The HDMI Control Register contains bits that control the HDMI reset generation.
Address: 3039_0000h base + 30h offset = 3039_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDMI_PHY_APB_
R
RESET
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_HDMI_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
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SRC_HDMI_RCR field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Active 1
HDMI_PHY_
APB_RESET
6.5.5.12 MEDIAMIX Reset Control Register (SRC_MEDIA_RCR)
The MEDIAMIX Control Register contains bits that control the MEDIAMIX (expect
ISP/Dewrap) reset generation.
Address: 3039_0000h base + 34h offset = 3039_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MEDIAMIX_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_MEDIA_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 MEDIAMIX reset for MEDIAMIX, expect ISP/Dewrap
MEDIAMIX_
RESET 0 Don't reset MEDIAMIX
1 Reset MEDIAMIX
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6.5.5.13 GPU2D Reset Control Register (SRC_GPU2D_RCR)
Address: 3039_0000h base + 38h offset = 3039_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU2D_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPU2D_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
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SRC_GPU2D_RCR field descriptions (continued)
Field Description
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 GPU shared logic reset
GPU2D_RESET
active 1
6.5.5.14 GPU3D Reset Control Register (SRC_GPU3D_RCR)
Address: 3039_0000h base + 3Ch offset = 3039_003Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU3D_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPU3D_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
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SRC_GPU3D_RCR field descriptions (continued)
Field Description
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 GPU3D reset
GPU3D_RESET
active 1
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6.5.5.15 GPU Reset Control Register (SRC_GPU_RCR)
The GPU Control Register contains bits that control the GPU reset generation.
Address: 3039_0000h base + 40h offset = 3039_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPU_RESET
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPU_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
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SRC_GPU_RCR field descriptions (continued)
Field Description
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 GPU shared logic reset
GPU_RESET
6.5.5.16 VPU Reset Control Register (SRC_VPU_RCR)
The VPU Control Register contains bits that control the VPU reset generation.
Address: 3039_0000h base + 44h offset = 3039_0044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPU_RESET
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_VPU_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
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SRC_VPU_RCR field descriptions (continued)
Field Description
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 VPU shared logic reset
VPU_RESET
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6.5.5.17 VPU G1 Reset Control Register (SRC_VPU_G1_RCR)
Address: 3039_0000h base + 48h offset = 3039_0048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPU_G1_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_VPU_G1_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
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SRC_VPU_G1_RCR field descriptions (continued)
Field Description
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 VPU G1 reset
VPU_G1_RESET
active 1
6.5.5.18 VPU G2 Reset Control Register (SRC_VPU_G2_RCR)
Address: 3039_0000h base + 4Ch offset = 3039_004Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPU_G2_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_VPU_G2_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
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SRC_VPU_G2_RCR field descriptions (continued)
Field Description
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 VPU G2 reset
VPU_G2_RESET
active 1
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6.5.5.19 VPU VC8000E Reset Control Register
(SRC_VPUVC8KE_RCR)
Address: 3039_0000h base + 50h offset = 3039_0050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPU_VPUVC8KE_
R
RESET
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_VPUVC8KE_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
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SRC_VPUVC8KE_RCR field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 VPU VC8000E reset
VPU_
active 1
VPUVC8KE_
RESET
6.5.5.20 NOC Wrapper Reset Control Register (SRC_NOC_RCR)
Address: 3039_0000h base + 54h offset = 3039_0054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOC_RESET
R
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_NOC_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
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SRC_NOC_RCR field descriptions (continued)
Field Description
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 NOC reset
NOC_RESET
active 1
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6.5.5.21 SRC Boot Mode Register 1 (SRC_SBMR1)
The Boot Mode register (SBMR) contains bits that reflect the status of Boot Mode Pins
of the chip. The reset value is configuration dependent (depending on boot/fuses/IO
pads).
Address: 3039_0000h base + 58h offset = 3039_0058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R BOOT_CFG
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_SBMR1 field descriptions
Field Description
31–20 This field is reserved.
- Reserved
BOOT_CFG Refer to fusemap.
6.5.5.22 SRC Reset Status Register (SRC_SRSR)
The SRSR is a write to one clear register which records the source of the reset events for
the chip. The SRC reset status register will capture all the reset sources that have
occurred. This register is reset on ipp_reset_b. This is a read-write register.
For bit[9-0] - writing zero does not have any effect. Writing one will clear the
corresponding bit. The individual bits can be cleared by writing one to that bit. When the
system comes out of reset, this register will have bits set corresponding to all the reset
sources that occurred during system reset. Software has to take care to clear this register
by writing one after every reset that occurs so that the register will contain the
information of recently occurred reset.
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Address: 3039_0000h base + 5Ch offset = 3039_005Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ipp_user_reset_b
wdog2_rst_b
wdog3_rst_b
wdog1_rst_b
csu_reset_b
ipp_reset_b
jtag_sw_rst
jtag_rst_b
R 0 0
tempsense_rst_b
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SRC_SRSR field descriptions
Field Description
31–10 This read-only field is reserved and always has the value 0.
Reserved
9 Temper Sensor software reset. Indicates whether the reset was the result of software reset from on-chip
tempsense_rst_b Temperature Sensor.
0 Reset is not a result of software reset from Temperature Sensor.
1 Reset is a result of software reset from Temperature Sensor.
8 IC Watchdog2 Time-out reset. Indicates whether the reset was the result of the watchdog2 time-out event.
wdog2_rst_b
0 Reset is not a result of the watchdog4 time-out event.
1 Reset is a result of the watchdog4 time-out event.
7 IC Watchdog3 Time-out reset. Indicates whether the reset was the result of the watchdog3 time-out event.
wdog3_rst_b
0 Reset is not a result of the watchdog3 time-out event.
1 Reset is a result of the watchdog3 time-out event.
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SRC_SRSR field descriptions (continued)
Field Description
6 JTAG software reset. Indicates whether the reset was the result of software reset from JTAG.
jtag_sw_rst
0 Reset is not a result of software reset from JTAG.
1 Reset is a result of software reset from JTAG.
5 HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG.
jtag_rst_b
0 Reset is not a result of HIGH-Z reset from JTAG.
1 Reset is a result of HIGH-Z reset from JTAG.
4 IC Watchdog1 Time-out reset. Indicates whether the reset was the result of the watchdog time-out event.
wdog1_rst_b
0 Reset is not a result of the watchdog1 time-out event.
1 Reset is a result of the watchdog1 time-out event.
3 Indicates whether the reset was the result of the ipp_user_reset_b qualified reset.
ipp_user_reset_b
0 Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
1 Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
2 Indicates whether the reset was the result of the csu_reset_b input.
csu_reset_b
NOTE: If case the csu_reset_b occurred during a WARM reset process, during the phase that ipg_clk is
not available yet, then the occurrence of CSU reset will not be reflected in this bit.
0 Reset is not a result of the csu_reset_b event.
1 Reset is a result of the csu_reset_b event.
1 This read-only field is reserved and always has the value 0.
Reserved
0 Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence)
ipp_reset_b
0 Reset is not a result of ipp_reset_b pin.
1 Reset is a result of ipp_reset_b pin.
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6.5.5.23 SRC Interrupt Status Register (SRC_SISR)
Address: 3039_0000h base + 68h offset = 3039_0068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DISPLAY_PASSED_RESET
USBPHY2_PASSED_RESE
USBPHY1_PASSED_RESE
GPU_PASSED_RESET
PCIE1_PHY_PASSED_
M7C_PASSED_RESET
VPU_PASSED_RESET
M7P_PASSED_RESET
RESET
R
T
T
Reserved
Reserved
Reserved
Reserved
Reserved
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_SISR field descriptions
Field Description
31–12 This field is reserved.
- Reserved
11 Interrupt generated to indicate that VPU passed software reset and is ready to be used
VPU_PASSED_
RESET 0 interrupt generated not due to VPU reset
1 interrupt generated due to VPU reset
10 Interrupt generated to indicate that GPU passed software reset and is ready to be used
GPU_PASSED_
RESET 0 interrupt generated not due to GPU reset
1 interrupt generated due to GPU reset
9 Interrupt generated to indicate that m7 platform passed software reset and is ready to be used
M7P_PASSED_
RESET 0 interrupt generated not due to m7 platform reset
1 interrupt generated due to m7 platform reset
8 Interrupt generated to indicate that m7 core passed software reset and is ready to be used
M7C_PASSED_
RESET 0 interrupt generated not due to m7core reset
1 interrupt generated due to m7core reset
7 Interrupt generated to indicate that DISPLAY passed software reset and is ready to be used
DISPLAY_
PASSED_ 0 Interrupt generated not due to DISPLAY passed reset
RESET 1 Interrupt generated due to DISPLAY passed reset
6 This field is reserved.
- Reserved
5 Interrupt generated to indicate that PCIE1 PHY passed software reset and is ready to be used
PCIE1_PHY_
PASSED_ 0 Interrupt generated not due to PCIE1 PHY passed reset
RESET 1 Interrupt generated due to PCIE1 PHY passed reset
4 This field is reserved.
- Reserved
3 Interrupt generated to indicate that USB PHY2 passed software reset and is ready to be used
USBPHY2_PASS
ED_RESET 0 Interrupt generated not due to USB PHY2 passed reset
1 Interrupt generated due to USB PHY2 passed reset
2 Interrupt generated to indicate that USB PHY1 passed software reset and is ready to be used
USBPHY1_PASS
ED_RESET 0 Interrupt generated not due to USB PHY1 passed reset
1 Interrupt generated due to USB PHY1 passed reset
1 This field is reserved.
- Reserved
0 This field is reserved.
- Reserved
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6.5.5.24 SRC Interrupt Mask Register (SRC_SIMR)
Address: 3039_0000h base + 6Ch offset = 3039_006Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK_USBPHY2_PASSE
MASK_USBPHY1_PASSE
MASK_M7C_PASSED_R
MASK_M7P_PASSED_R
MASK_GPU_PASSED_
MASK_VPU_PASSED_
MASK_PCIE_PHY_
MASK_DISPLAY_
PASSED_RESET
PASSED_RESET
R
D_RESET
D_RESET
Reserved
Reserved
RESET
RESET
ESET
ESET
Reserved Reserved
Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
SRC_SIMR field descriptions
Field Description
31–12 This field is reserved.
- Reserved
11 Mask interrupt generation due to VPU passed reset
MASK_VPU_
PASSED_ 0 do not mask interrupt due to VPU passed reset - interrupt will be created
RESET 1 mask interrupt due to VPU passed reset
10 Mask interrupt generation due to GPU passed reset
MASK_GPU_
PASSED_ 0 do not mask interrupt due to GPU passed reset - interrupt will be created
RESET 1 mask interrupt due to GPU passed reset
9 mask interrupt generation due to m7 platform passed reset
MASK_M7P_PA
SSED_RESET 0 do not mask interrupt due to m7 platform passed reset - interrupt will be created
1 mask interrupt due to m7 platform passed reset
8 mask interrupt generation due to m7 core passed reset
MASK_M7C_PA
SSED_RESET 0 do not mask interrupt due to m7 core passed reset - interrupt will be created
1 mask interrupt due to m7 core passed reset
Table continues on the next page...
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System Reset Controller (SRC)
SRC_SIMR field descriptions (continued)
Field Description
7 Mask interrupt generation due to display passed reset
MASK_
DISPLAY_ 0 do not mask interrupt due to display passed reset - interrupt will be created
PASSED_ 1 mask interrupt due to display passed reset
RESET
6 This field is reserved.
- Reserved
5 Mask interrupt generation due to PCIE PHY passed reset
MASK_PCIE_
PHY_PASSED_ 0 do not mask interrupt due to PCIE PHY passed reset - interrupt will be created
RESET 1 mask interrupt due to PCIE PHY passed reset
4 This field is reserved.
- Reserved
3 mask interrupt generation due to USB PHY2 passed reset
MASK_USBPHY
2_PASSED_RES 0 do not mask interrupt due to USB PHY2 passed reset - interrupt will be created
ET 1 mask interrupt due to USB PHY2 passed reset
2 mask interrupt generation due to USB PHY1 passed reset
MASK_USBPHY
1_PASSED_RES 0 do not mask interrupt due to USB PHY1 passed reset - interrupt will be created
ET 1 mask interrupt due to USB PHY1 passed reset
- This field is reserved.
Reserved
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6.5.5.25 SRC Boot Mode Register 2 (SRC_SBMR2)
The Boot Mode register (SBMR), contains bits that reflect the status of Boot Mode Pins
of the chip. The default values for those bits depends on the values of pins/fuses during
reset sequence.
Address: 3039_0000h base + 70h offset = 3039_0070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 IPP_BOOT_MODE 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC_CONFIG[1:0]
BT_FUSE_SEL
FORCE_COLD_
R 0 0
BOOT
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_SBMR2 field descriptions
Field Description
31–28 This read-only field is reserved and always has the value 0.
Reserved
27–24 IPP_BOOT_MODE shows the latched state of the BOOT_MODE3, BOOT_MODE2, BOOT_MODE1 and
IPP_BOOT_ BOOT_MODE0 signals on the rising edge of POR_B. See the Boot mode pin settings section of System
MODE Boot.
23–8 This read-only field is reserved and always has the value 0.
Reserved
7–5 See Fusemap for additional information.
FORCE_COLD_
BOOT
4 BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse. See
BT_FUSE_SEL Fusemap for additional information on this fuse.
3 This field is reserved.
- Reserved
2 This read-only field is reserved and always has the value 0.
Reserved
SEC_ SEC_CONFIG[1] shows the state of the SEC_CONFIG[1] fuse and SEC_CONFIG[0] shows the state of
CONFIG[1:0] the SEC_CONFIG[0] fuse. See Fusemap for additional information on this fuse.
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6.5.5.26 SRC General Purpose Register 1 (SRC_GPR1)
Address: 3039_0000h base + 74h offset = 3039_0074h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C0_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR1 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
C0_START_ Core0 start reset address:
ADDRH
RVBARADDR0 = {SRC_GPR1[15:0], SRC_GPR2[21:2]}
6.5.5.27 SRC General Purpose Register 2 (SRC_GPR2)
Address: 3039_0000h base + 78h offset = 3039_0078h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C0_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR2 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
C0_START_ Core0 start reset address:
ADDRL
RVBARADDR0 = {SRC_GPR1[15:0], SRC_GPR2[21:2]}
6.5.5.28 SRC General Purpose Register 3 (SRC_GPR3)
Address: 3039_0000h base + 7Ch offset = 3039_007Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C1_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_GPR3 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
C1_START_ Core1 start reset address:
ADDRH
RVBARADDR1 = {SRC_GPR3[15:0], SRC_GPR4[21:2]}
6.5.5.29 SRC General Purpose Register 4 (SRC_GPR4)
Address: 3039_0000h base + 80h offset = 3039_0080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C1_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR4 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
C1_START_ Core1 start reset address:
ADDRL
RVBARADDR1 = {SRC_GPR3[15:0], SRC_GPR4[21:2]}
6.5.5.30 SRC General Purpose Register 5 (SRC_GPR5)
Address: 3039_0000h base + 84h offset = 3039_0084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C2_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR5 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
C2_START_ Core2 start reset address:
ADDRH
RVBARADDR2 = {SRC_GPR5[15:0], SRC_GPR6[21:2]}
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6.5.5.31 SRC General Purpose Register 6 (SRC_GPR6)
Address: 3039_0000h base + 88h offset = 3039_0088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C2_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR6 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
C2_START_ Core2 start reset address:
ADDRL
RVBARADDR2 = {SRC_GPR5[15:0], SRC_GPR6[21:2]}
6.5.5.32 SRC General Purpose Register 7 (SRC_GPR7)
Address: 3039_0000h base + 8Ch offset = 3039_008Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C3_START_ADDRH
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR7 field descriptions
Field Description
31–16 This field is reserved.
- Reserved
C3_START_ Core3 start reset address:
ADDRH
RVBARADDR3 = {SRC_GPR7[15:0], SRC_GPR8[21:2]}
6.5.5.33 SRC General Purpose Register 8 (SRC_GPR8)
Address: 3039_0000h base + 90h offset = 3039_0090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved C3_START_ADDRL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_GPR8 field descriptions
Field Description
31–22 This field is reserved.
- Reserved
C3_START_ Core3 start reset address:
ADDRL
RVBARADDR3 = {SRC_GPR7[15:0], SRC_GPR8[21:2]}
6.5.5.34 SRC General Purpose Register 9 (SRC_GPR9)
Reserved for Internal Use.
Address: 3039_0000h base + 94h offset = 3039_0094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR9 field descriptions
Field Description
- This field is reserved.
Reserved.
6.5.5.35 SRC General Purpose Register 10 (SRC_GPR10)
Address: 3039_0000h base + 98h offset = 3039_0098h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_GPR10 field descriptions
Field Description
- This field is reserved.
Reserved.
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6.5.5.36 SRC DDR Controller Reset Control Register
(SRC_DDRC_RCR)
DDR Controller Reset Control Register
Address: 3039_0000h base + 1000h offset = 3039_1000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDRC1_SYS_RST
DDRC1_CORE_
DDRC1_PRST
DDRC1_PHY_
DDRC1_PHY_
DDRC1_PHY_
R
PWROKIN
RESET
WRST
RST
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
SRC_DDRC_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
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SRC_DDRC_RCR field descriptions (continued)
Field Description
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain0 cannot write to this register.
1 This register is assigned to domain0. The master from domain0 can write to this register
23–6 This field is reserved.
- Reserved
5 Active 1
DDRC1_PHY_
WRST
4 Active 1
DDRC1_SYS_
RST
3 0 De-assert DDR controller
DDRC1_PHY_ 1 Assert DDR Controller
PWROKIN
2 0 De-assert DDR controller
DDRC1_PHY_ 1 Assert DDR Controller
RESET
1 DDR Controller core_ddrc_rstn and aresetn.
DDRC1_CORE_
RST 0 De-assert DDR controller aresetn and core_ddrc_rstn
1 Assert DDR Controller preset and DDR PHY reset
0
DDRC1_PRST DDR Controller preset and DDR PHY reset.
NOTE: This reset can only be released when DDR Controller clock inputs are active and stable for 30
cycles
0 De-assert DDR Controller preset and DDR PHY reset reset
1 Assert DDR Controller preset and DDR PHY reset
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6.5.5.37 HDMIPHY Reset Control Register (SRC_HDMIPHY_RCR)
The HDMI PHY Reset Control Register contains bits that control the HDMI PHY reset
generation.
Address: 3039_0000h base + 1008h offset = 3039_1008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDMIPHY_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_HDMIPHY_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
Table continues on the next page...
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SRC_HDMIPHY_RCR field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for HDMI PHY
HDMIPHY_
RESET 0 Do not assert HDMI PHY reset
1 Assert HDMI PHY reset
6.5.5.38 MIPI PHY1 Reset Control Register (SRC_MIPIPHY1_RCR)
The MIPI PHY1 Reset Control Register contains bits that control the MIPI PHY1 reset
generation.
Address: 3039_0000h base + 100Ch offset = 3039_100Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MIPIPHY1_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SRC_MIPIPHY1_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for MIPI PHY1
MIPIPHY1_
RESET 0 Do not assert MIPI PHY1 reset
1 Assert MIPI PHY1 reset
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6.5.5.39 MIPI PHY2 Reset Control Register (SRC_MIPIPHY2_RCR)
The MIPI PHY2 Reset Control Register contains bits that control the MIPI PHY2 reset
generation.
Address: 3039_0000h base + 1010h offset = 3039_1010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIPIPHY2_
RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_MIPIPHY2_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
Table continues on the next page...
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SRC_MIPIPHY2_RCR field descriptions (continued)
Field Description
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for MIPI PHY2
MIPIPHY2_
RESET 0 Do not assert MIPI PHY2 reset
1 Assert MIPI PHY2 reset
6.5.5.40 HSIO Reset Control Register (SRC_HSIO_RCR)
The HSIOMIX Reset Control Register contains bits that control the HSIOMIX reset
generation.
Address: 3039_0000h base + 1014h offset = 3039_1014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIO_RESET
Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_HSIO_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
Table continues on the next page...
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SRC_HSIO_RCR field descriptions (continued)
Field Description
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for HSIOMIX
HSIO_RESET
0 Do not assert HSIOMIX reset
1 Assert HSIOMIX reset
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6.5.5.41 MEDIAMIX ISP and Dewarp Reset Control Register
(SRC_MEDIAISPDWP_RCR)
The MEDIAMIX ISP and Dewarp Reset Control Register contains bits that control the
MEDIAMIX ISP and Dewarp reset generation.
Address: 3039_0000h base + 1018h offset = 3039_1018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R DOMAIN3
DOMAIN2
DOMAIN1
DOMAIN0
DOM_EN
LOCK
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEDIAISPDWP_
R
RESET
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRC_MEDIAISPDWP_RCR field descriptions
Field Description
31
DOM_EN Domain Control enable for this register.
NOTE: [31:30] and [27:24] areas are not controlled by this bit. [31:30] and [27:24] area can be modified
by any masters from any domains when Lock bit is not set.
0 Disables domain control. All of this register’s bits except [31:30] and [27:24] can be modified by any
masters
1 Enables domain control. All of this register’s bits except [31:30] and [27:24] can only be modified by
the masters from the domains specified in [27:24] area.
30
LOCK Domain control bits lock
NOTE: Lock bit is a write-once register, once it is set to 1, it can’t be write to 0
0 [31] and [27:24] bits can be modified
1 [31] and [27:24] bits cannot be modified
29–28 This field is reserved.
- Reserved
27 Domain3 assignment control. Effective when dom_en is set to 1.
DOMAIN3
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SRC_MEDIAISPDWP_RCR field descriptions (continued)
Field Description
0 This register is not assigned to domain3. The master from domain3 cannot write to this register.
1 This register is assigned to domain3. The master from domain3 can write to this register
26 Domain2 assignment control. Effective when dom_en is set to 1.
DOMAIN2
0 This register is not assigned to domain2. The master from domain2 cannot write to this register.
1 This register is assigned to domain2. The master from domain2 can write to this register
25 Domain1 assignment control. Effective when dom_en is set to 1.
DOMAIN1
0 This register is not assigned to domain1. The master from domain1 cannot write to this register.
1 This register is assigned to domain1. The master from domain1 can write to this register
24 Domain0 assignment control. Effective when dom_en is set to 1.
DOMAIN0
0 This register is not assigned to domain0. The master from domain3 cannot write to this register.
1 This register is assigned to domain0. The master from domain3 can write to this register
23–1 This field is reserved.
- Reserved
0 Self-clearing SW reset for MEDIAMIX ISP and Dewarp
MEDIAISPDWP_
RESET 0 Do not assert MEDIAMIX ISP and Dewarp reset
1 Assert MEDIAMIX ISP and Dewarp reset
6.6 Watchdog Timer (WDOG)
6.6.1 Overview
The Watchdog Timer (WDOG) protects against system failures by providing a method by
which to escape from unexpected events or programming errors.
Once the WDOG is activated, it must be serviced by the software on a periodic basis. If
servicing does not take place, the timer times out. Upon timeout, the WDOG asserts the
internal system reset signal, WDOG_RESET_B_DEB to the System Reset Controller
(SRC).
There is also a provision for WDOG(ipp_wdog) signal assertion by timeout counter
expiration. There is an option of programmable interrupt generation before the counter
actually times out. The time at which the interrupt needs to be generated prior to counter
timeout is programmable. There is a power down counter which is enabled out of any
reset (POR, Warm/Cold). This counter has a fixed timeout period of 16 seconds, upon
which it asserts the WDOG(ipp_wdog) signal.
Flow diagrams for the timeout counter, power down counter and interrupt operations are
are shown in Flow Diagrams.
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6.6.1.1 Block Diagram
LOW POWER
WAIT Mode
LOW POWER
STOP/ DOZE Low Power
Mode Control
Time-Out Counter
DEBUG Mode
Low Frequency
Reference Clock
WDOG-1 Reset Reset
wdog_rst
Generation Logic
Pre Time-Out Interrupt Interrupt
Peripheral Bus
Control Logic
TIMEOUT
Low Frequency
WDOG-1 Generation WDOG-1
Reference Clock Power Down Counter
Logic
Figure 6-33. WDOG Diagram
6.6.1.2 Features
The WDOG features are listed below:
• Configurable timeout counter with timeout periods from 0.5 to 128 seconds which,
after timeout expiration, result in the assertion of WDOG_RESET_B_DEB reset
signal.
• Time resolution of 0.5 seconds
• Configurable timeout counter that can be programmed to run or stop during low-
power modes
• Configurable timeout counter that can be programmed to run or stop during DEBUG
mode
• Programmable interrupt generation prior to timeout
• The duration between interrupt and timeout events can be programmed from 0 to
127.5 seconds in steps of 0.5 seconds.
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• Power down counter with fixed timeout period of 16 seconds, which if not disabled
after reset will assert WDOG_B (ipp_wdog) signal low
• Power down counter will be enabled out of any reset (POR, Warm / Cold reset) by
default.
6.6.2 Functional description
This section provides a complete functional description of the block.
6.6.2.1 Watchdog mechanism and system integration
The modules are disabled by default (after reset). WDOG1 will be configured during boot
while WDOG2 is dedicated for secure world purposes and will be activated by TZ
software if required. The TZ watchdog (TZ watchdog) module protects against TZ
starvation by providing a method of escaping normal mode and forcing a switch to the
TZ mode.TZ starvation is a situation where the normal OS prevents switching to the TZ
mode. Such a situation is undesirable as it can compromise the system’s security.
Once the TZ WDOG module is activated, it must be serviced by TZ on a periodic basis.
If servicing does not take place, the timer times out. Upon a timeout, the TZ WDOG
asserts a TZ-mapped interrupt that forces switching to the TZ mode. If it is still not
serviced, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG
module cannot be programmed or de-activated by normal mode software.
The WDOG modules operate as follows:
• If servicing does not take place, the timer times out and the wdog_rst_b signal is
activated (low)
• Interrupt can be generated before the counter actually times out
• The wdog_rst_b signal can be activated by software
• There is a power-down counter which gets enabled out of any reset. This counter has
a fixed timeout period of 16 seconds upon which it will assert the ipp_wdog_b
signal.
6.6.2.2 Timeout event
The WDOG provides timeout periods from 0.5 to 128 seconds with a time resolution of
0.5 seconds.
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The user can determine the timeout period by writing to the WDOG timeout field
(WT[7:0]) in the Watchdog Control Register (WCR). The WDOG must be enabled by
setting the WDE bit of Watchdog Control Register (WCR) for the timeout counter to start
running. After the WDOG is enabled, the counter is activated, loads the timeout value
and begins to count down from this programmed value. The timer will time out when the
counter reaches zero and the WDOG outputs a system reset signal,
WDOG_RESET_B_DEB and asserts WDOG_B (ipp_wdog_b) (WDT bit should be set
in Watchdog Control Register (WCR)).
However, the timeout condition can be prevented by reloading the counter with the new
timeout value (WT[7:0] of WDOG_WCR) if a service routine (see Servicing WDOG to
reload the counter) is performed before the counter reaches zero. If any system errors
occur which prevent the software from servicing the Watchdog Service Register (WSR),
the timeout condition occurs. By performing the service routine, the WDOG reloads its
counter to the timeout value indicated by bits WT[7:0] of the Watchdog Control Register
(WCR) and it restarts the countdown.
A system reset will reset the counter and place it in the idle state at any time during the
countdown. The counter flow diagram is shown in Flow Diagrams.
NOTE
The timeout value is reloaded to the counter either at the time
WDOG is enabled or after the service routine has been
performed.
6.6.2.2.1 Servicing WDOG to reload the counter
To reload a timeout value to the counter, the proper service sequence begins by writing
0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WSR). Any number
of instructions can be executed between the two writes. If the WDOG_WSR is not loaded
with 0x_5555 prior to writing 0x_AAAA to the WDOG_WSR, the counter is not
reloaded. If any value other than 0x_AAAA is written to the WDOG_WSR after
0x_5555, the counter is not reloaded. This service sequence will reload the counter with
the timeout value WT[7:0] of Watchdog Control Register (WCR). The timeout value can
be changed at any point; it is reloaded when WDOG is serviced by the core.
6.6.2.3 Interrupt event
Prior to timeout, the WDOG can generate an interrupt which can be considered a warning
that timeout will occur shortly.
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The duration between interrupt event and timeout event can be controlled by writing to
the WICT field of Watchdog Interrupt Control Register (WICR). It can vary between 0
and 127.5 seconds. If the WDOG is serviced (Servicing WDOG to reload the counter)
before the interrupt generation, the counter will be reloaded with the timeout value
WT[7:0] of Watchdog Control Register (WCR) and the interrupt will not be triggered.
6.6.2.4 Power-down counter event
The power-down counter inside WDOG will be enabled out of reset. This counter has a
fixed timeout value of 16 seconds, after which it will drive the WDOG_B (ipp_wdog)
signal low.
To prevent this, the software must disable this counter by clearing the PDE bit of
Watchdog Miscellaneous Control Register (WMCR) within 16 seconds of reset
deassertion. Once disabled, this counter can't be enabled again until the next system reset
occurs. This feature is intended to prevent the hanging up of cores after reset, as WDOG
is not enabled out of reset.
6.6.2.5 Low power modes
6.6.2.5.1 STOP and DOZE mode
If the WDOG timer disable bit for low power STOP and DOZE mode (WDZST) bit in
the Watchdog Control Register (WCR), is cleared, the WDOG timer continues to operate
using the low frequency reference clock. If the low power enable (WDZST) bit is set, the
WDOG timer operation will be suspended in low power STOP or DOZE mode. Upon
exiting low power STOP or DOZE mode, the WDOG operation returns to what it was
prior to entering the STOP or DOZE mode.
6.6.2.5.2 WAIT mode
If the WDOG timer disable bit for low power WAIT mode (WDW) bit in the Watchdog
Control Register (WCR), is cleared, the WDOG timer continues to operate using the low
frequency reference clock i.e ipg_clk_32k clock (32.768 kHz frequency clock). If the low
power WAIT enable (WDW) bit is set, the WDOG timer operation will be suspended.
Upon exiting low power WAIT mode, the WDOG operation returns to what it was prior
to entering the WAIT mode.
NOTE
The WDOG timer won't be able to detect events that happen for
periods shorter than one low frequency reference clock cycle.
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For example, in repeated WAIT mode entry or exit, if the RUN
mode time is less than one low frequency reference clock cycle
and if the WDW bit is set, the WDOG timer may never time
out, even though the system is in RUN mode for a finite
duration; WDOG may not see a low frequency reference clock
edge during its wake time.
6.6.2.6 Debug mode
The WDOG timer can be configured for continual operation, or for suspension during
debug mode. If the WDOG debug enable (WDBG) bit is set in the Watchdog Control
Register (WCR), the WDOG timer operation is suspended in debug mode. If the WDBG
bit is set and the debug mode (ipg_debug signal assertion) is entered, WDOG timer
operation is suspended after two low frequency reference (ipg_clk_32k) clocks. Similarly,
WDOG timer operation continues after two low frequency reference clocks of debug
mode exit. Register read and write accesses in debug mode continue to function
normally. Also, while in debug mode, the WDE bit of Watchdog Control Register (WCR)
can be enabled/disabled directly. If the WDOG debug enable (WDBG) bit is cleared then
WDOG timer operation is not suspended. The power-down counter is not affected by
debug mode entry/exit.
NOTE
If the WDE bit of Watchdog Control Register (WCR) is set/
cleared while in debug mode, it remains set/cleared even after
exiting debug mode.
6.6.2.7 Operations
6.6.2.7.1 Watchdog reset generation
The WDOG generated reset signal WDOG_RESET_B_DEB is asserted by the following
operations:
• A software write to the Software Reset Signal (SRS) bit of the Watchdog Control
Register (WCR).
• WDOG timeout. See Timeout event.
The wdog_rst_b will be asserted for one clock cycle of low frequency reference clock for
both a timeout condition and a software write occurrence. It remains asserted for 1 clock
cycle of low frequency reference clock even if a system reset is asserted in between.
Figure 6-35 shows the timing diagram of this signal due to a timeout condition.
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6.6.2.7.2 WDOG_B generation
The WDOG asserts WDOG_B in the following scenarios:
• Software write to WDA bit of Watchdog Control Register (WCR). WDOG_B signal
remains asserted as long as the WDA bit is "0".
• WDOG timeout condition, WDT bit of Watchdog Control Register (WCR) must be
set for this scenario. A description of the timeout condition can be found in the
Timeout event. WDOG_B (ipp_wdog) signal remains asserted until a power-on reset
(POR) occurs. It gets cleared after the POR occurs (not due to any other system
reset). Figure 6-36 shows the timing diagram of WDOG_B (ipp_wdog) due to
timeout condition.
• WDOG power-down counter timeout, PDE bit of Watchdog Miscellaneous Control
Register (WMCR) should not be cleared for this scenario. A description of this
counter can be found in the Power-down counter event. WDOG_B (ipp_wdog) signal
remains asserted for one clock cycle of low frequency reference clock (ipg_clk_32k).
Figure 6-34 shows the scenarios under which WDOG_B(ipp_wdog_b) gets asserted.
Watchdog Misc. Control Register (WDOG_WMCR)
Watchdog Control Register (WDOG_WCR)
WDOG_WCR[WDT]
WDOG_WCR[WDA]
WDOG_WMCR[PDE]
Low Frequency Power Down Counter Logic
Reference Clock
WDOG-1 Time Out Counter WDOG-1
Figure 6-34. WDOG_B (ipp_wdog) generation
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Low frequency
reference clock
Time-out
Counter 01 00
wdog_rst
System reset
WDOG-1
Figure 6-35. WDOG timeout condition/WDT bit is not set
Low frequency
reference clock
Time-out
Counter 01 00
wdog_rst
System reset
Power on reset
WDOG-1
Figure 6-36. WDOG timeout condition/WDT bit is set
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6.6.2.8 Clocks
This section describes clocks and special clocking requirements of the block.
The WDOG uses the low frequency reference clock for its counter and control
operations. The peripheral bus clock is used for register read/write operations.
The following table describes the clock sources for WDOG. Please see for clock setting,
configuration and gating information.
Table 6-43. WDOG Clocks
Clock name Clock Root Description
ipg_clk ipg_clk_root IP Global functional clock. All functionality inside the WDOG module is
synchronized to this clock.
ipg_clk_s ipg_clk_root IP slave bus clock. This clock is synchronized to ipg_clk and is only used
for register read/write operations.
ipg_clk_32k ckil_sync_clk_root Low frequency (32.768 kHz) clock that continues to run in low-power
mode. It is assumed that the Clock Controller will provide this clock signal
synchronized to ipg_clk in the normal mode, and switch to a non-
synchronized signal in low-power mode when the ipg_clk is off.
6.6.2.9 Reset
The block is reset by a system reset and the WDOG counter will be disabled. The power-
down counter is enabled and starts counting.
6.6.2.10 Interrupt
The WDOG has the feature of Interrupt generation before timeout.
The interrupt will be generated only if the WIE bit in Watchdog Interrupt Control
Register (WICR) is set. The exact time at which the interrupt should occur (prior to
timeout) depends on the value of WICT field of Watchdog Interrupt Control Register
(WICR). For example, if the WICT field has a value 0x04, then the interrupt will be
generated two seconds prior to timeout. Once the interrupt is triggered the WTIS bit in
Watchdog Interrupt Control Register (WICR) will be set. The software needs to clear this
bit to deassert the interrupt. If the WDOG is serviced before the interrupt generation then
the counter will be reloaded with the timeout value WT[7:0] of Watchdog Control
Register (WCR) and interrupt would not be triggered.
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6.6.2.11 Flow Diagrams
The flow diagrams for WDOG operation are shown below.
Reset no
(Cold/Warm)
negated?
yes
Counter in
IDLE State
start counter
Decrement counter
yes
PDE bit
cleared?
no
Is no
count=0?
yes
Assert WDOG
Figure 6-37. Power-Down Counter Flow Diagram
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Reset no
Negated?
yes
Enable interrupt
& WDOG timer
Decrement counter
yes Interrupt
count=0?
no
Is
WDOG yes
serviced? Reload counter
no
yes Interrupt
Assert interrupt Count=0?
Figure 6-38. Interrupt Generation Flow Diagram
6.6.3 External signals
Table 6-44. WDOG External Signals
Signal Description Direction
WDOG_ANY Global WDOG signal IO
WDOG_B This signal will power down the chip. IO
WDOG_RESET_B_DEB This signal is a reset source for the chip. O
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6.6.4 Initialization
The following sequence should be performed for WDOG initialization.
• PDE bit of Watchdog Miscellaneous Control Register (WMCR) should be cleared to
disable the power down counter.
• WT field of Watchdog Control Register (WCR) should be programmed for sufficient
timeout value.
• WDOG should be enabled by setting WDE bit of Watchdog Control Register (WCR)
so that the timeout counter loads the WT field value of Watchdog Control Register
(WCR) and starts counting.
6.6.5 WDOG Memory Map/Register Definition
6.6.5.1 WDOG register descriptions
The WDOG has user-accessible, 16-bit registers used to configure, operate, and monitor
the state of the Watchdog Timer. Byte operations can be performed on these registers. If
a 32-bit access is performed,the WDOG will not generate a peripheral bus error but will
behave normally, like a 16-Bit access, making read/write possible. A 32-Bit access
should be avoided, as the system may go to an unknown state.
6.6.5.1.1 WDOG memory map
WDOG1 base address: 3028_0000h
WDOG2 base address: 3029_0000h
WDOG3 base address: 302A_0000h
Offset (hex) Register Width Access Reset value
(hex)
(In bits)
0 Watchdog Control Register (WCR) 16 RW 0030
2 Watchdog Service Register (WSR) 16 RW 0000
4 Watchdog Reset Status Register (WRSR) 16 RO 0000
6 Watchdog Interrupt Control Register (WICR) 16 RW 0004
8 Watchdog Miscellaneous Control Register (WMCR) 16 RW 0001
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6.6.5.1.2 Watchdog Control Register (WCR)
The Watchdog Control Register (WDOG_WCR) controls the WDOG operation.
• WDZST, WDBG and WDW are write-once only bits. Once the software does a write
access to these bits, they will be locked and cannot be reprogrammed until the next
system reset assertion.
• WDE is a write one once only bit. Once software performs a write "1" operation to
this bit it cannot be reset/cleared until the next system reset.
• WDT is also a write one once only bit. Once software performs a write "1" operation
to this bit it cannot be reset/cleared until the next POR. This bit does not get reset/
cleared due to any system reset.
6.6.5.1.2.1 Offset
Register Offset
WCR 0h
6.6.5.1.2.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDZST
WDBG
WDW
WDT
WDA
WDE
SRE
SRS
WT
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
6.6.5.1.2.3 Fields
Field Description
15-8 WT
WT Watchdog Time-out Field. This 8-bit field contains the time-out value that is loaded into the Watchdog
counter after the service routine has been performed or after the Watchdog is enabled. After reset,
WT[7:0] must have a value written to it before enabling the Watchdog otherwise count value of zero
which is 0.5 seconds is loaded into the counter.
NOTE: The time-out value can be written at any point of time but it is loaded to the counter at the time
when WDOG is enabled or after the service routine has been performed. For more information
see Timeout event .
00000000 - - 0.5 Seconds (Default).
00000001 - - 1.0 Seconds.
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Field Description
00000010 - - 1.5 Seconds.
00000011 - - 2.0 Seconds.
11111111 - - 128 Seconds.
7 WDW
WDW Watchdog Disable for Wait. This bit determines the operation of WDOG during Low Power WAIT mode.
This is a write once only bit.
0 - Continue WDOG timer operation (Default).
1 - Suspend WDOG timer operation.
6 Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset
Signal (SRS).
SRE
0 - Reserved
1 - This bit must be set to 1.
5 WDA
WDA WDOG_B assertion. Controls the software assertion of the WDOG_B signal.
0 - Assert WDOG_B output.
1 - No effect on system (Default).
4 SRS
SRS Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal
WDOG_RESET_B_DEB . This bit automatically resets to "1" after it has been asserted to "0".
NOTE: This bit does not generate the software reset to the block.
0 - Assert system reset signal.
1 - No effect on the system (Default).
3 WDT
WDT WDOG_B Time-out assertion. Determines if the WDOG_B gets asserted upon a Watchdog Time-out
Event. This is a write-one once only bit.
NOTE: There is no effect on WDOG_RESET_B_DEB (WDOG Reset) upon writing on this bit. WDOG_B
gets asserted along with WDOG_RESET_B_DEB if this bit is set.
0 - No effect on WDOG_B (Default).
1 - Assert WDOG_B upon a Watchdog Time-out event.
2 WDE
WDE Watchdog Enable. Enables or disables the WDOG block. This is a write one once only bit. It is not
possible to clear this bit by a software write, once the bit is set.
NOTE: This bit can be set/reset in debug mode (exception).
0 - Disable the Watchdog (Default).
1 - Enable the Watchdog.
1 WDBG
WDBG Watchdog DEBUG Enable. Determines the operation of the WDOG during DEBUG mode. This bit is write
once only.
0 - Continue WDOG timer operation (Default).
1 - Suspend the watchdog timer.
0 WDZST
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Field Description
WDZST Watchdog Low Power. Determines the operation of the WDOG during low-power modes. This bit is write
once-only.
NOTE: The WDOG can continue/suspend the timer operation in the low-power modes (STOP and
DOZE mode).
0 - Continue timer operation (Default).
1 - Suspend the watchdog timer.
6.6.5.1.3 Watchdog Service Register (WSR)
When enabled, the WDOG requires that a service sequence be written to the Watchdog
Service Register (WSR) to prevent the timeout condition.
NOTE
Executing the service sequence will reload the WDOG timeout
counter.
6.6.5.1.3.1 Offset
Register Offset
WSR 2h
6.6.5.1.3.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
WSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.6.5.1.3.3 Fields
Field Description
15-0 WSR
WSR Watchdog Service Register. This 16-bit field contains the Watchdog service sequence. Both writes must
occur in the order listed prior to the time-out, but any number of instructions can be executed between the
two writes. The service sequence must be performed as follows:
0101010101010101 - Write to the Watchdog Service Register (WDOG_WSR).
1010101010101010 - Write to the Watchdog Service Register (WDOG_WSR).
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6.6.5.1.4 Watchdog Reset Status Register (WRSR)
The WRSR is a read-only register that records the source of the output reset assertion. It
is not cleared by a hard reset. Therefore, only one bit in the WRSR will always be
asserted high. The register will always indicate the source of the last reset generated due
to WDOG. Read access to this register is with one wait state. Any write performed on
this register will generate a Peripheral Bus Error .
A reset can be generated by the following sources, as listed in priority from highest to
lowest:
• Watchdog Time-out
• Software Reset
6.6.5.1.4.1 Offset
Register Offset
WRSR 4h
6.6.5.1.4.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SFTW
TOUT
POR
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.6.5.1.4.3 Fields
Field Description
15-5 Reserved.
—
4 POR
POR Power On Reset. Indicates whether the reset is the result of a power on reset.
0 - Reset is not the result of a power on reset.
1 - Reset is the result of a power on reset.
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Field Description
3-2 Reserved.
—
1 TOUT
TOUT Timeout. Indicates whether the reset is the result of a WDOG timeout.
0 - Reset is not the result of a WDOG timeout.
1 - Reset is the result of a WDOG timeout.
0 SFTW
SFTW Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit
0 - Reset is not the result of a software reset.
1 - Reset is the result of a software reset.
6.6.5.1.5 Watchdog Interrupt Control Register (WICR)
The WDOG_WICR controls the WDOG interrupt generation.
6.6.5.1.5.1 Offset
Register Offset
WICR 6h
6.6.5.1.5.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W1C WTIS
R
0
WICT
WIE
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
6.6.5.1.5.3 Fields
Field Description
15 WIE
WIE Watchdog Timer Interrupt enable bit. Reset value is 0.
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Field Description
NOTE: This bit is a write once only bit. Once the software does a write access to this bit, it will get
locked and cannot be reprogrammed until the next system reset assertion
0 - Disable Interrupt (Default).
1 - Enable Interrupt.
14 WTIS
WTIS Watchdog TImer Interrupt Status bit will reflect the timer interrupt status, whether interrupt has occurred
or not. Once the interrupt has been triggered software must clear this bit by writing 1 to it.
0 - No interrupt has occurred (Default).
1 - Interrupt has occurred
13-8 Reserved.
—
7-0 WICT
WICT Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must
the interrupt occur. The reset value is 0x04 implies interrupt will occur 2 seconds before time-out. The
maximum value that can be programmed to WICT field is 127.5 seconds with a resolution of 0.5 seconds.
NOTE: This field is write once only. Once the software does a write access to this field, it will get locked
and cannot be reprogrammed until the next system reset assertion.
00000000 - WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
00000001 - WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
00000100 - WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
11111111 - WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
6.6.5.1.6 Watchdog Miscellaneous Control Register (WMCR)
WDOG_WMCR Controls the Power Down counter operation.
6.6.5.1.6.1 Offset
Register Offset
WMCR 8h
6.6.5.1.6.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
PDE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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Watchdog Timer (WDOG)
6.6.5.1.6.3 Fields
Field Description
15-1 Reserved.
—
0 PDE
PDE Power Down Enable bit. Reset value of this bit is 1, which means the power down counter inside the
WDOG is enabled after reset. The software must write 0 to this bit to disable the counter within 16
seconds of reset de-assertion. Once disabled this counter cannot be enabled again. See Power-down
counter event for operation of this counter.
NOTE: This bit is write-one once only bit. Once software sets this bit it cannot be reset until the next
system reset.
0 - Power Down Counter of WDOG is disabled.
1 - Power Down Counter of WDOG is enabled (Default).
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Chapter 7
Interrupts and DMA
7.1 Interrupts and DMA Events
7.1.1 Overview
This chapter provides the interrupt assignments of the Arm domain in A53 Interrupts,
CM7 Interrupts, and the DMA events in SDMA event mapping
NOTE
JPEG is not supported.
7.1.2 A53 Interrupts
The Global Interrupt Controller (GIC) collects up to 160 interrupt requests from all the
chip sources and provides an interface to the Cortex A53 CPU.
Each interrupt can be configured as a normal or a secure interrupt. Software force
registers and software priority masking are also supported. The following table describes
the A53 interrupt sources.
Table 7-1. Arm Domain Interrupt Summary
IRQ Module Logic Interrupt Description
0 Boot - Used to notify cores on exception condition while
boot
1 DAP - DAP Interrupt
2 SDMA1 - AND of all 48 SDMA1 interrupts (events) from all
the channels
3 GPU3D - GPU3D Interrupt
4 SNVS_LP_WRAPPER OR ON-OFF button press shorter than 5 secs (pulse
event)
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
4 SNVS_HP_WRAPPER OR ON-OFF button press shorter than 5 secs (pulse
event)
5 LCDIF1 - LCDIF1 Interrupt
6 LCDIF2 - LCDIF2 Interrupt
7 VPU - VPU G1 Decoder Interrupt
8 VPU - VPU G2 Decoder Interrupt
9 QOS - QOS Interrupt
10 WDOG3 - Watchdog Timer reset
11 HS - HS Interrupt Request
12 APBHDMA OR4 GPMI operation channel 0 description complete
interrupt
12 APBHDMA OR4 GPMI operation channel 1 description complete
interrupt
12 APBHDMA OR4 GPMI operation channel 2 description complete
interrupt
12 APBHDMA OR4 GPMI operation channel 3 description complete
interrupt
13 NPU - Machine Learning Processor Interrupt
14 RAWNAND - BCH operation complete interrupt
15 RAWNAND - GPMI operation TIMEOUT ERROR interrupt
16 ISI - ISI Camera Channel 0 Interrupt
17 MIPI_CSI1 - MIPI CSI 1 Interrupt
18 MIPI_DSI - MIPI DSI Interrupt
19 SNVS_HP_WRAPPER - SRTC Consolidated Interrupt. Non TZ.
20 SNVS_HP_WRAPPER - SRTC Security Interrupt. TZ.
21 CSU - CSU Interrupt Request. Indicates to the
processor that one or more alarm inputs were
asserted
22 USDHC1 - uSDHC1 Enhanced SDHC Interrupt Request
23 USDHC2 - uSDHC2 Enhanced SDHC Interrupt Request
24 USDHC3 - uSDHC3 Enhanced SDHC Interrupt Request
25 GPU2D - GPU2D Interrupt
26 UART1 - UART-1 ORed interrupt
27 UART2 - UART-2 ORed interrupt
28 UART3 - UART-3 ORed interrupt
29 UART4 - UART-4 ORed interrupt
30 VPU - VPU Encoder Interrupt
31 ECSPI1 - eCSPI1 interrupt request line to the core.
32 ECSPI2 - eCSPI2 interrupt request line to the core.
33 ECSPI3 - eCSPI3 interrupt request line to the core.
34 SDMA3 - AND of all 48 SDMA3 interrupts (events) from all
the channels
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Chapter 7 Interrupts and DMA
Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
35 I2C1 - I2C-1 Interrupt
36 I2C2 - I2C-2 Interrupt
37 I2C3 - I2C-3 Interrupt
38 I2C4 - I2C-4 Interrupt
39 RDC - RDC Interrupt
40 USB1 - USB-1 Interrupt
41 USB2 - USB-2 Interrupt
42 ISI - ISI Camera Channel 1 Interrupt
43 HDMI_TX - HDMI TX Subsystem Interrupt
44 MICFIL - Digital Microphone interface voice activity
detector event interrupt
45 MICFIL - Digital Microphone interface voice activity
detector error interrupt
46 GPT6 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
47 SCTR - System Counter Interrupt [0]
48 SCTR - System Counter Interrupt [1]
49 ANAMIX OR TempSensor (Temperature alarm).
49 ANAMIX OR TempSensor (Temperature critical alarm).
50 SAI3 OR4 SAI3 Receive Interrupt
50 SAI3 OR4 SAI3 Receive Async Interrupt
50 SAI3 OR4 SAI3 Transmit Interrupt
50 SAI3 OR4 SAI3 Transmit Async Interrupt
51 GPT5 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
52 GPT4 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
53 GPT3 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
54 GPT2 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
55 GPT1 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
56 GPIO1 - Active HIGH Interrupt from INT7 from GPIO
57 GPIO1 - Active HIGH Interrupt from INT6 from GPIO
58 GPIO1 - Active HIGH Interrupt from INT5 from GPIO
59 GPIO1 - Active HIGH Interrupt from INT4 from GPIO
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
60 GPIO1 - Active HIGH Interrupt from INT3 from GPIO
61 GPIO1 - Active HIGH Interrupt from INT2 from GPIO
62 GPIO1 - Active HIGH Interrupt from INT1 from GPIO
63 GPIO1 - Active HIGH Interrupt from INT0 from GPIO
64 GPIO1 - Combined interrupt indication for GPIO1 signal 0
throughout 15
65 GPIO1 - Combined interrupt indication for GPIO1 signal
16 throughout 31
66 GPIO2 - Combined interrupt indication for GPIO2 signal 0
throughout 15
67 GPIO2 - Combined interrupt indication for GPIO2 signal
16 throughout 31
68 GPIO3 - Combined interrupt indication for GPIO3 signal 0
throughout 15
69 GPIO3 - Combined interrupt indication for GPIO3 signal
16 throughout 31
70 GPIO4 - Combined interrupt indication for GPIO4 signal 0
throughout 15
71 GPIO4 - Combined interrupt indication for GPIO4 signal
16 throughout 31
72 GPIO5 - Combined interrupt indication for GPIO5 signal 0
throughout 15
73 GPIO5 - Combined interrupt indication for GPIO5 signal
16 throughout 31
74 ISP1 OR ISP 1 ISP Interrupts
74 ISP1 OR ISP 1 SMIA Interrupts
74 ISP1 OR ISP 1 MIPI1 Interrupts
74 ISP1 OR ISP 1 MIPI2 Interrupts
75 ISP2 OR ISP 2 ISP Interrupts
75 ISP2 OR ISP 2 SMIA Interrupts
75 ISP2 OR ISP 2 MIPI1 Interrupts
75 ISP2 OR ISP 2 MIPI2 Interrupts
76 I2C5 - I2C-5 Interrupt
77 I2C6 - I2C-6 Interrupt
78 WDOG1 - Watchdog 1 Timer reset
79 WDOG2 - Watchdog 2 Timer reset
80 MIPI_CSI2 - MIPI CSI 2 Interrupt
81 PWM1 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
82 PWM2 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
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Chapter 7 Interrupts and DMA
Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
83 PWM3 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
84 PWM4 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
85 CCMSRCGPCMIX - CCM, Interrupt Request 1
86 CCMSRCGPCMIX - CCM, Interrupt Request 2
87 CCMSRCGPCMIX - GPC, Interrupt Request 1
88 MU1 - Interrupt to A53 (A53,M7 MU)
89 CCMSRCGPCMIX - SRC interrupt request
90 SAI5 OR4 SAI5 Receive Interrupt
90 SAI5 OR4 SAI5 Receive Async Interrupt
90 SAI5 OR4 SAI5 Transmit Interrupt
90 SAI5 OR4 SAI5 Transmit Async Interrupt
90 SAI6 OR4 SAI6 Receive Interrupt
90 SAI6 OR4 SAI6 Receive Async Interrupt
90 SAI6 OR4 SAI6 Transmit Interrupt
90 SAI6 OR4 SAI6 Transmit Async Interrupt
91 CAAM - RTIC Interrupt
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
94 CCMSRCGPCMIX - Combined CPU WDOG interrupts (4x) out of
SRC.
95 SAI1 OR4 SAI1 Receive Interrupt
95 SAI1 OR4 SAI1 Receive Async Interrupt
95 SAI1 OR4 SAI1 Transmit Interrupt
95 SAI1 OR4 SAI1 Transmit Async Interrupt
96 SAI2 OR4 SAI2 Receive Interrupt
96 SAI2 OR4 SAI2 Receive Async Interrupt
96 SAI2 OR4 SAI2 Transmit Interrupt
96 SAI2 OR4 SAI2 Transmit Async Interrupt
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
97 MU1 - Interrupt to M7 (A53, M7 MU)
98 DDR OR DRAM controller Interrupt for DRAM controller's
performance monitor
98 DDR OR DRAM controller Scrubber Interrupt indicating
one full address range sweep
99 DDR - DRAM Controller Error Interrupt for DFI error
100 Dewarp - Dewarp Interrupt
101 CPU - Error indicator for AXI transaction with a write
response error condition.
102 CPU - Error indicator for L2 RAM double-bit ECC error.
103 SDMA2 - AND of all 48 SDMA2 interrupts (events) from all
the channels
104 SJC - Interrupt triggered by SJC register
105 CAAM_WRAPPER - CAAM interrupt queue for JQ
106 CAAM_WRAPPER - CAAM interrupt queue for JQ
107 Flexspi - Flexspi Interrupt
108 TZASC - TZASC (PL380) interrupt
109 MICFIL - Digital Microphone interface interrupt
110 MICFIL - Digital Microphone interface error interrupt
111 SAI7 OR4 SAI7 Receive Interrupt
111 SAI7 OR4 SAI7 Receive Async Interrupt
111 SAI7 OR4 SAI7 Transmit Interrupt
111 SAI7 OR4 SAI7 Transmit Async Interrupt
112 perfmon1 - General interrupt
113 perfmon2 - General interrupt
114 CAAM_WRAPPER - CAAM interrupt queue for JQ
115 CAAM_WRAPPER - Recoverable error interrupt
116 HS - HS Interrupt Request
117 CM7 OR CTI trigger outputs from CM7 platform
117 CM7 OR CTI trigger outputs from CM7 platform
118 ENET1 OR4 MAC 0 Receive Buffer Done
118 ENET1 OR4 MAC 0 Receive Frame Done
118 ENET1 OR4 MAC 0 Transmit Buffer Done
118 ENET1 OR4 MAC 0 Transmit Frame Done
119 ENET1 OR4 MAC 0 Receive Buffer Done
119 ENET1 OR4 MAC 0 Receive Frame Done
119 ENET1 OR4 MAC 0 Transmit Buffer Done
119 ENET1 OR4 MAC 0 Transmit Frame Done
120 ENET1 OR MAC 0 Periodic Timer Overflow
120 ENET1 OR MAC 0 Time Stamp Available
120 ENET1 OR MAC 0 Payload Receive Error
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
120 ENET1 OR MAC 0 Transmit FIFO Underrun
120 ENET1 OR MAC 0 Collision Retry Limit
120 ENET1 OR MAC 0 Late Collision
120 ENET1 OR MAC 0 Ethernet Bus Error
120 ENET1 OR MAC 0 MII Data Transfer Done
120 ENET1 OR MAC 0 Receive Buffer Done
120 ENET1 OR MAC 0 Receive Frame Done
120 ENET1 OR MAC 0 Transmit Buffer Done
120 ENET1 OR MAC 0 Transmit Frame Done
120 ENET1 OR MAC 0 Graceful Stop
120 ENET1 OR MAC 0 Babbling Transmit Error
120 ENET1 OR MAC 0 Babbling Receive Error
120 ENET1 OR MAC 0 Receive Flush Frame0
120 ENET1 OR MAC 0 Receive Flush Frame1
120 ENET1 OR MAC 0 Receive Flush Frame2
120 ENET1 OR MAC 0 Wakeup Request (sync)
120 ENET1 OR MAC 0 Babbling Receive Error
120 ENET1 OR MAC 0 Wakeup Request (sync)
121 ENET1 - MAC 0 1588 Timer Interrupt – synchronous
122 ASRC - ASRC Interrupt
123 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
124 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
125 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
126 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
127 PCIE_CTRL1 OR Channels [63:32] interrupts requests
127 PCIE_CTRL1 OR Channels [63:32] interrupts requests
128 AUDIO_XCVR - eARC Interrupt 0
129 AUDIO_XCVR - eARC Interrupt 1
130 AUD2HTX - Audio to HDMI TX Audio Link Master Interrupt
131 EDMA1 - Audio Subsystem eDMA Error Interrupt
132 EDMA1 - Audio Subsystem eDMA Channel Interrupts,
Logical OR of channels [15:0]
133 EDMA1 - Audio Subsystem eDMA Channel Interrupts,
Logical OR of channels [31:16]
134 ENET_QOS - ENET QOS TSN Interrupt from PMT
135 ENET_QOS OR4 ENET QOS TSN LPI RX exit Interrupt
135 ENET_QOS OR4 ENET QOS TSN Host System Interrupt
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
135 ENET_QOS OR4 ENET QOS TSN Host System RX Channel
Interrupts, Logical OR of channels[4:0]
135 ENET_QOS OR4 ENET QOS TSN Host System TX Channel
Interrupts, Logical OR of channels[4:0]
136 MU2 - Interrupt to A53 (A53, Audio Processor MU)
137 MU2 - Interrupt to Audio Processor (A53, Audio
Processor MU)
138 MU3 - Interrupt to M7 (M7, Audio Processor MU)
139 MU3 - Interrupt to Audio Processor (M7, Audio
Processor MU)
140 PCIE_CTRL1 - RC/EP message transaction Interrupt
141 PCIE_CTRL1 - RC/EP PME Message and Error Interrupt
142 CAN_FD1 OR CAN-FD1 Interrupt from busoff
142 CAN_FD1 OR CAN-FD1 Interrupt from CAN line error
142 CAN_FD1 OR CAN-FD1 ORed interrupts from ipi_int_MB
142 CAN_FD1 OR CAN-FD1 Rx warning Interrupt
142 CAN_FD1 OR CAN-FD1 Tx warning Interrupt
142 CAN_FD1 OR CAN-FD1 Interrupt from wake up
142 CAN_FD1 OR CAN-FD1 Interrupt from match in PN
142 CAN_FD1 OR CAN-FD1 Interrupt from timeout in PN
142 CAN_FD1 OR CAN-FD1 Busoff done interrupt
142 CAN_FD1 OR CAN-FD1 FD error interrupt
143 CAN_FD1 OR CAN-FD1 Correctable error interrupt
143 CAN_FD1 OR CAN-FD1 Non correctable error int host
143 CAN_FD1 OR CAN-FD1 Non correctable error int internal
144 CAN_FD2 OR CAN-FD2 Interrupt from busoff
144 CAN_FD2 OR CAN-FD2 Interrupt from CAN line error
144 CAN_FD2 OR CAN-FD2 ORed interrupts from ipi_int_MB
144 CAN_FD2 OR CAN-FD2 Rx warning Interrupt
144 CAN_FD2 OR CAN-FD2 Tx warning Interrupt
144 CAN_FD2 OR CAN-FD2 Interrupt from wake up
144 CAN_FD2 OR CAN-FD2 Interrupt from match in PN
144 CAN_FD2 OR CAN-FD2 Interrupt from timeout in PN
144 CAN_FD2 OR CAN-FD2 Busoff done interrupt
144 CAN_FD2 OR CAN-FD2 FD error interrupt
145 CAN_FD2 OR CAN-FD2 Correctable error interrupt
145 CAN_FD2 OR CAN-FD2 Non correctable error int host
145 CAN_FD2 OR CAN-FD2 Non correctable error int internal
146 AUDIO_XCVR - eARC PHY - SPDIF wakeup interrupt
147 DDR OR DRAM Controller Error Interrupt for address
protection fault.
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Table 7-1. Arm Domain Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
147 DDR OR DRAM Controller Error Interrupt for correctable
ECC error detected
147 DDR OR DRAM Controller Error Interrupt for uncorrectable
ECC error detected
148 USB1 - USB-1 Wake-up Interrupt
149 USB2 - USB-2 Wake-up Interrupt
150-159 Reserved - Reserved
7.1.3 CM7 Interrupts
The Nested Vectored Interrupt Controller (NVIC) collects up to 160 interrupt requests
from all chip sources and provides an interface to the Cortex M7 Core.
The following table describes the M7 interrupt sources.
Table 7-2. CM7 Interrupt Summary
IRQ Module Logic Interrupt Description
0 Reserved - Reserved
1 DAP - DAP Interrupt
2 SDMA1 - AND of all 48 SDMA1 interrupts (events) from all
the channels
3 GPU3D - GPU3D Interrupt
4 SNVS_LP_WRAPPER OR ON-OFF button press shorter than 5 secs (pulse
event)
4 SNVS_HP_WRAPPER OR ON-OFF button press shorter than 5 secs (pulse
event)
5 LCDIF1 - LCDIF1 Interrupt
6 LCDIF2 - LCDIF2 Interrupt
7 VPU - VPU G1 Decoder Interrupt
8 VPU - VPU G2 Decoder Interrupt
9 QOS - QOS Interrupt
10 WDOG3 - Watchdog Timer reset
11 HS_CP1 - HS Interrupt Request (CP1_semaphore_int)
12 APBHDMA OR4 GPMI operation channel 0 description complete
interrupt
12 APBHDMA OR4 GPMI operation channel 1 description complete
interrupt
12 APBHDMA OR4 GPMI operation channel 2 description complete
interrupt
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
12 APBHDMA OR4 GPMI operation channel 3 description complete
interrupt
13 NPU - Machine Learning Processor Interrupt
14 RAWNAND - BCH operation complete interrupt
15 RAWNAND - GPMI operation TIMEOUT ERROR interrupt
16 ISI - ISI Camera Channel 0 Interrupt
17 MIPI_CSI1 - MIPI CSI 1 Interrupt
18 MIPI_DSI - MIPI DSI Interrupt
19 SNVS_HP_WRAPPER - SRTC Consolidated Interrupt. Non TZ.
20 SNVS_HP_WRAPPER - SRTC Security Interrupt. TZ.
21 CSU - CSU Interrupt Request. Indicates to the
processor that one or more alarm inputs were
asserted
22 USDHC1 - uSDHC1 Enhanced SDHC Interrupt Request
23 USDHC2 - uSDHC2 Enhanced SDHC Interrupt Request
24 USDHC3 - uSDHC3 Enhanced SDHC Interrupt Request
25 GPU2D - GPU2D Interrupt
26 UART1 - UART-1 ORed interrupt
27 UART2 - UART-2 ORed interrupt
28 UART3 - UART-3 ORed interrupt
29 UART4 - UART-4 ORed interrupt
30 VPU - VPU Encoder Interrupt
31 ECSPI1 - eCSPI1 interrupt request line to the core.
32 ECSPI2 - eCSPI2 interrupt request line to the core.
33 ECSPI3 - eCSPI3 interrupt request line to the core.
34 SDMA3 - AND of all 48 SDMA3 interrupts (events) from all
the channels
35 I2C1 - I2C-1 Interrupt
36 I2C2 - I2C-2 Interrupt
37 I2C3 - I2C-3 Interrupt
38 I2C4 - I2C-4 Interrupt
39 RDC - RDC Interrupt
40 USB1 - USB-1 Interrupt
41 USB2 - USB-2 Interrupt
42 ISI - ISI Camera Channel 1 Interrupt
43 HDMI_TX - HDMI TX Subsystem Interrupt
44 MICFIL - Digital Microphone interface voice activity
detector event interrupt
45 MICFIL - Digital Microphone interface voice activity
detector error interrupt
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
46 GPT6 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
47 SCTR - System Counter Interrupt [0]
48 SCTR - System Counter Interrupt [1]
49 ANAMIX OR TempSensor (Temperature alarm).
49 ANAMIX OR TempSensor (Temperature critical alarm).
50 SAI3 OR4 SAI3 Receive Interrupt
50 SAI3 OR4 SAI3 Receive Async Interrupt
50 SAI3 OR4 SAI3 Transmit Interrupt
50 SAI3 OR4 SAI3 Transmit Async Interrupt
51 GPT5 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
52 GPT4 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
53 GPT3 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
54 GPT2 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
55 GPT1 - OR of GPT Rollover interrupt line, Input Capture
1 & 2 lines, Output Compare 1, 2 & 3 Interrupt
lines
56 GPIO1 - Active HIGH Interrupt from INT7 from GPIO
57 GPIO1 - Active HIGH Interrupt from INT6 from GPIO
58 GPIO1 - Active HIGH Interrupt from INT5 from GPIO
59 GPIO1 - Active HIGH Interrupt from INT4 from GPIO
60 GPIO1 - Active HIGH Interrupt from INT3 from GPIO
61 GPIO1 - Active HIGH Interrupt from INT2 from GPIO
62 GPIO1 - Active HIGH Interrupt from INT1 from GPIO
63 GPIO1 - Active HIGH Interrupt from INT0 from GPIO
64 GPIO1 - Combined interrupt indication for GPIO1 signal 0
throughout 15
65 GPIO1 - Combined interrupt indication for GPIO1 signal
16 throughout 31
66 GPIO2 - Combined interrupt indication for GPIO2 signal 0
throughout 15
67 GPIO2 - Combined interrupt indication for GPIO2 signal
16 throughout 31
68 GPIO3 - Combined interrupt indication for GPIO3 signal 0
throughout 15
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
69 GPIO3 - Combined interrupt indication for GPIO3 signal
16 throughout 31
70 GPIO4 - Combined interrupt indication for GPIO4 signal 0
throughout 15
71 GPIO4 - Combined interrupt indication for GPIO4 signal
16 throughout 31
72 GPIO5 - Combined interrupt indication for GPIO5 signal 0
throughout 15
73 GPIO5 - Combined interrupt indication for GPIO5 signal
16 throughout 31
74 ISP1 OR ISP 1 ISP Interrupts
74 ISP1 OR ISP 1 SMIA Interrupts
74 ISP1 OR ISP 1 MIPI1 Interrupts
74 ISP1 OR ISP 1 MIPI2 Interrupts
74 ISP1 OR ISP 1 Memory Interface Interrupts
75 ISP2 OR ISP 2 ISP Interrupts
75 ISP2 OR ISP 2 SMIA Interrupts
75 ISP2 OR ISP 2 MIPI1 Interrupts
75 ISP2 OR ISP 2 MIPI2 Interrupts
75 ISP2 OR ISP 2 Memory Interface Interrupts
76 I2C5 - I2C-5 Interrupt
77 I2C6 - I2C-6 Interrupt
78 WDOG1 - Watchdog 1 Timer reset
79 WDOG2 - Watchdog 2 Timer reset
80 MIPI_CSI2 - MIPI CSI 2 Interrupt
81 PWM1 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
82 PWM2 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
83 PWM3 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
84 PWM4 - Cumulative interrupt line. OR of Rollover Interrupt
line, Compare Interrupt line and FIFO Waterlevel
crossing interrupt line
85 CCMSRCGPCMIX - CCM, Interrupt Request 1
86 CCMSRCGPCMIX - CCM, Interrupt Request 2
87 CCMSRCGPCMIX - GPC, Interrupt Request 1
88 MU1 - Interrupt to A53 (A53,M7 MU)
89 CCMSRCGPCMIX - SRC interrupt request
90 SAI5 OR4 SAI5 Receive Interrupt
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
90 SAI5 OR4 SAI5 Receive Async Interrupt
90 SAI5 OR4 SAI5 Transmit Interrupt
90 SAI5 OR4 SAI5 Transmit Async Interrupt
90 SAI6 OR4 SAI6 Receive Interrupt
90 SAI6 OR4 SAI6 Receive Async Interrupt
90 SAI6 OR4 SAI6 Transmit Interrupt
90 SAI6 OR4 SAI6 Transmit Async Interrupt
91 CAAM - RTIC Interrupt
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
92 CPU OR Performance Unit Interrupts from Quad-A53
platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
93 CPU OR CTI trigger outputs from Quad-A53 platform
94 CCMSRCGPCMIX - Combined CPU WDOG interrupts (4x) out of
SRC.
95 SAI1 OR4 SAI1 Receive Interrupt
95 SAI1 OR4 SAI1 Receive Async Interrupt
95 SAI1 OR4 SAI1 Transmit Interrupt
95 SAI1 OR4 SAI1 Transmit Async Interrupt
96 SAI2 OR4 SAI2 Receive Interrupt
96 SAI2 OR4 SAI2 Receive Async Interrupt
96 SAI2 OR4 SAI2 Transmit Interrupt
96 SAI2 OR4 SAI2 Transmit Async Interrupt
97 MU1 - Interrupt to M7 (A53, M7 MU)
98 DDR OR DRAM controller Interrupt for DRAM controller's
performance monitor
98 DDR OR DRAM controller Scrubber Interrupt indicating
one full address range sweep
99 DDR - DRAM Controller Error Interrupt for DFI error
100 Dewarp - Dewarp Interrupt
101 CPU - Error indicator for AXI transaction with a write
response error condition.
102 CPU - Error indicator for L2 RAM double-bit ECC error.
103 SDMA2 - AND of all 48 SDMA2 interrupts (events) from all
the channels
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
104 SJC - Interrupt triggered by SJC register
105 CAAM_WRAPPER - CAAM interrupt queue for JQ
106 CAAM_WRAPPER - CAAM interrupt queue for JQ
107 Flexspi - Flexspi Interrupt
108 TZASC - TZASC (PL380) interrupt
109 MICFIL - Digital Microphone interface interrupt
110 MICFIL - Digital Microphone interface error interrupt
111 SAI7 OR4 SAI7 Receive Interrupt
111 SAI7 OR4 SAI7 Receive Async Interrupt
111 SAI7 OR4 SAI7 Transmit Interrupt
111 SAI7 OR4 SAI7 Transmit Async Interrupt
112 perfmon1 - General interrupt
113 perfmon2 - General interrupt
114 CAAM_WRAPPER - CAAM interrupt queue for JQ
115 CAAM_WRAPPER - Recoverable error interrupt
116 HS_CP0 - HS Interrupt Request (CP0_semaphore_int)
117 CM7 OR CTI trigger outputs from CM7 platform
117 CM7 OR CTI trigger outputs from CM7 platform
118 ENET1 OR4 MAC 0 Receive Buffer Done
118 ENET1 OR4 MAC 0 Receive Frame Done
118 ENET1 OR4 MAC 0 Transmit Buffer Done
118 ENET1 OR4 MAC 0 Transmit Frame Done
119 ENET1 OR4 MAC 0 Receive Buffer Done
119 ENET1 OR4 MAC 0 Receive Frame Done
119 ENET1 OR4 MAC 0 Transmit Buffer Done
119 ENET1 OR4 MAC 0 Transmit Frame Done
120 ENET1 OR MAC 0 Periodic Timer Overflow
120 ENET1 OR MAC 0 Time Stamp Available
120 ENET1 OR MAC 0 Payload Receive Error
120 ENET1 OR MAC 0 Transmit FIFO Underrun
120 ENET1 OR MAC 0 Collision Retry Limit
120 ENET1 OR MAC 0 Late Collision
120 ENET1 OR MAC 0 Ethernet Bus Error
120 ENET1 OR MAC 0 MII Data Transfer Done
120 ENET1 OR MAC 0 Receive Buffer Done
120 ENET1 OR MAC 0 Receive Frame Done
120 ENET1 OR MAC 0 Transmit Buffer Done
120 ENET1 OR MAC 0 Transmit Frame Done
120 ENET1 OR MAC 0 Graceful Stop
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
120 ENET1 OR MAC 0 Babbling Transmit Error
120 ENET1 OR MAC 0 Babbling Receive Error
120 ENET1 OR MAC 0 Receive Flush Frame0
120 ENET1 OR MAC 0 Receive Flush Frame1
120 ENET1 OR MAC 0 Receive Flush Frame2
120 ENET1 OR MAC 0 Wakeup Request (sync)
120 ENET1 OR MAC 0 Babbling Receive Error
120 ENET1 OR MAC 0 Wakeup Request (sync)
121 ENET1 - MAC 0 1588 Timer Interrupt – synchronous
122 ASRC - ASRC Interrupt
123 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
124 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
125 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
126 PCIE_CTRL1 - Coming from GLUE logic, of set/reset FF, driven
by PCIE signals.
127 PCIE_CTRL1 OR Channels [63:32] interrupts requests
127 PCIE_CTRL1 OR Channels [63:32] interrupts requests
128 AUDIO_XCVR - eARC Interrupt 0
129 AUDIO_XCVR - eARC Interrupt 1
130 AUD2HTX - Audio to HDMI TX Audio Link Master Interrupt
131 EDMA1 - Audio Subsystem eDMA Error Interrupt
132 EDMA1 - Audio Subsystem eDMA Channel Interrupts,
Logical OR of channels [15:0]
133 EDMA1 - Audio Subsystem eDMA Channel Interrupts,
Logical OR of channels [31:16]
134 ENET_QOS - ENET QOS TSN Interrupt from PMT
135 ENET_QOS OR4 ENET QOS TSN LPI RX exit Interrupt
135 ENET_QOS OR4 ENET QOS TSN Host System Interrupt
135 ENET_QOS OR4 ENET QOS TSN Host System RX Channel
Interrupts, Logical OR of channels[4:0]
135 ENET_QOS OR4 ENET QOS TSN Host System TX Channel
Interrupts, Logical OR of channels[4:0]
136 MU2 - Interrupt to A53 (A53, Audio Processor MU)
137 MU2 - Interrupt to Audio Processor (A53, Audio
Processor MU)
138 MU3 - Interrupt to M7 (M7, Audio Processor MU)
139 MU3 - Interrupt to Audio Processor (M7, Audio
Processor MU)
140 PCIE_CTRL1 - RC/EP message transaction Interrupt
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Table 7-2. CM7 Interrupt Summary (continued)
IRQ Module Logic Interrupt Description
141 PCIE_CTRL1 - RC/EP PME Message and Error Interrupt
142 CAN_FD1 OR CAN-FD1 Interrupt from busoff
142 CAN_FD1 OR CAN-FD1 Interrupt from CAN line error
142 CAN_FD1 OR CAN-FD1 ORed interrupts from ipi_int_MB
142 CAN_FD1 OR CAN-FD1 Rx warning Interrupt
142 CAN_FD1 OR CAN-FD1 Tx warning Interrupt
142 CAN_FD1 OR CAN-FD1 Interrupt from wake up
142 CAN_FD1 OR CAN-FD1 Interrupt from match in PN
142 CAN_FD1 OR CAN-FD1 Interrupt from timeout in PN
142 CAN_FD1 OR CAN-FD1 Busoff done interrupt
142 CAN_FD1 OR CAN-FD1 FD error interrupt
143 CAN_FD1 OR CAN-FD1 Correctable error interrupt
143 CAN_FD1 OR CAN-FD1 Non correctable error int host
143 CAN_FD1 OR CAN-FD1 Non correctable error int internal
144 CAN_FD2 OR CAN-FD2 Interrupt from busoff
144 CAN_FD2 OR CAN-FD2 Interrupt from CAN line error
144 CAN_FD2 OR CAN-FD2 ORed interrupts from ipi_int_MB
144 CAN_FD2 OR CAN-FD2 Rx warning Interrupt
144 CAN_FD2 OR CAN-FD2 Tx warning Interrupt
144 CAN_FD2 OR CAN-FD2 Interrupt from wake up
144 CAN_FD2 OR CAN-FD2 Interrupt from match in PN
144 CAN_FD2 OR CAN-FD2 Interrupt from timeout in PN
144 CAN_FD2 OR CAN-FD2 Busoff done interrupt
144 CAN_FD2 OR CAN-FD2 FD error interrupt
145 CAN_FD2 OR CAN-FD2 Correctable error interrupt
145 CAN_FD2 OR CAN-FD2 Non correctable error int host
145 CAN_FD2 OR CAN-FD2 Non correctable error int internal
146 AUDIO_XCVR - eARC PHY - SPDIF wakeup interrupt
147 DDR OR DRAM Controller Error Interrupt for address
protection fault.
147 DDR OR DRAM Controller Error Interrupt for correctable
ECC error detected
147 DDR OR DRAM Controller Error Interrupt for uncorrectable
ECC error detected
148 USB1 - USB-1 Wake-up Interrupt
149 USB2 - USB-2 Wake-up Interrupt
150-159 Reserved - Reserved
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7.1.4 Audio DSP Interrupts
The Audio DSP has 32 interrupt inputs, configured as shown in the following table.
Interrupts 19-27 come from the 3-channel Interrupt Steer (IRQ_STEER) block. These 9
interrupts from the SoC are generated by an instance of the IRQ_STEER, which is used
to reduce the160 system interrupt request sources down to 9 interrupts for the Audio
DSP.
Table 7-3. Audio DSP Interrupts
IRQ Type Level Source Description
0-1 Level 1 - Reserved
2 Timer.0 2 Internal -
3 Timer.1 3 Internal -
4-6 Edge 2 - Reserved
7 Level 2 MU2 and MU3 From MU2 and MU3
(the two MU instances
for communication with
the Audio DSP).
8 Sw 1 Internal -
9 Sw 2 Internal -
10 Writeerr 2 Internal -
11 - 18 Level 2 - Reserved
19 Level 2 irqstr_irq[0] From IRQ_STEER
20 Level 2 irqstr_irq[1] From IRQ_STEER
21 Level 2 irqstr_irq[2] From IRQ_STEER
22 Level 2 irqstr_irq[3] From IRQ_STEER
23 Level 2 irqstr_irq[4] From IRQ_STEER
24 Level 2 irqstr_irq[5] From IRQ_STEER
25 Level 2 irqstr_irq[6] From IRQ_STEER
26 Level 2 irqstr_irq[7] From IRQ_STEER
27 Level 2 irqstr_irq[8] From IRQ_STEER
28 - 30 Level 2 - Reserved
31 profiling 3 - -
All the 3 channels of the IRQ_STEER module are mapped to the Audio DSP (HiFi4).
The input and output IRQ mapping is shown in the table below.
Table 7-4. IRQ_STEER Mapping
Input IRQ Channel # Output IRQ Audio DSP IRQ
IRQ_IN[31:0] CH0 IRQ[0] HIFI_IRQ[19]
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Table 7-4. IRQ_STEER Mapping (continued)
Input IRQ Channel # Output IRQ Audio DSP IRQ
IRQ_IN[63:32] IRQ[1] HIFI_IRQ[20]
IRQ_IN[95:64]
IRQ_IN[127:96] IRQ[2] HIFI_IRQ[21]
IRQ_IN[159:128]
IRQ_IN[31:0] CH1 IRQ[3] HIFI_IRQ[22]
IRQ_IN[63:32] IRQ[4] HIFI_IRQ[23]
IRQ_IN[95:64]
IRQ_IN[127:96] IRQ[5] HIFI_IRQ[24]
IRQ_IN[159:128]
IRQ_IN[31:0] CH2 IRQ[6] HIFI_IRQ[25]
IRQ_IN[63:32] IRQ[7] HIFI_IRQ[26]
IRQ_IN[95:64]
IRQ_IN[127:96] IRQ[8] HIFI_IRQ[27]
7.1.5 HDMI Interrupts
The 1-channel IRQ_STEER module for the HDMI subsystem combines the subsystem's
15 internal interrupts into 1 external interrupt that is routed to the GIC (IRQ[43]).
The HDMI subsystem interrupts are mapped to the IRQ_STEER as shown in the table
below.
Table 7-5. HDMI Interrupts
IRQ Source IRQ_STEER Input Description
u_hdmi_tx.ointerrupt u_irq_steer.irq_in[0] HDMI TX General Interrupt
u_hdmi_tx.ointerruptwakeup u_irq_steer.irq_in[1] HDMI TX Wakeup Interrupt
Reserved u_irq_steer.irq_in[2] Reserved
u_blk_ctl.htx_hpd_low2high u_irq_steer.irq_in[3] HDMI TX HPD – HDMI Cable Connect
Interrupt
u_blk_ctl.htx_hpd_high2low u_irq_steer.irq_in[4] HDMI TX HPD – HDMI Cable
Disconnect Interrupt
u_blk_ctl.htx_ready_low2high u_irq_steer.irq_in[5] HDMI TX PHY powered down Interrupt
u_blk_ctl.htx_ready_high2low u_irq_steer.irq_in[6] HDMI TX PHY powered up & ready to
transmit Interrupt
u_snps_trng_tx.O_irq u_irq_steer.irq_in[7] Ring Oscillator Interrupt
u_lcdif.lcdif_irq u_irq_steer.irq_in[8] LCDIF General Interrupt
Reserved u_irq_steer.irq_in[9] Reserved
u_vsfd.hrv_mwr_irq_out u_irq_steer.irq_in[10] HRV_MWR General Interrupt
u_vsfd.plb_irq_out u_irq_steer.irq_in[11] Pixel Line Buffer General Interrupt
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Table 7-5. HDMI Interrupts (continued)
IRQ Source IRQ_STEER Input Description
u_video_link_slv.htx_pvi_irq_out u_irq_steer.irq_in[12] HDMI TX Pixel Link General Interrupt
u_fdcc.fdcc_irq u_irq_steer.irq_in[13] Frequency Dynamic Clock Comp
Interrupt
u_pai.htx_pai_irq u_irq_steer.irq_in[14] Audio Link General Interrupt
The IRQ_STEER module for the HDMI subsystem has 1 channel, while the IRQ_STEER
module for the Audio DSP has 3 channels. Please note this difference when referring to
the registers in the IRQ_STEER chapter.
7.1.6 SDMA event mapping
The following table shows the DMA request signals for peripherals in the chip.
NOTE
For the eDMA module, when using the End of Packet feature,
the user should set the following CHn_SBR register bits
appropriately.
• Bit 22 is for local (means go straight to peripheral) read
from peripheral
• Bit 21 is for local (means go straight to peripheral) write to
peripheral
Table 7-6. SDMA1 event mapping
SDMA Module Description
0 ECSPI1 eCSPI1 Rx request
1 ECSPI1 eCSPI1 Tx request
2 ECSPI2 eCSPI2 Rx request
3 ECSPI2 eCSPI2 Tx request
4 ECSPI3 eCSPI3 Rx request
5 ECSPI3 eCSPI3 Tx request
6 - Reserved
7 - Reserved
8 CAN_FD1 CAN-FD1 DMA event
9 CAN_FD2 CAN-FD2 DMA event
10 - Reserved
11 - Reserved
12 - Reserved
13 - Reserved
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Table 7-6. SDMA1 event mapping (continued)
SDMA Module Description
14 IOMUX External DMA from pad through IOMUX #1
15 IOMUX External DMA from pad through IOMUX #2
16 I2C5 I2C5 DMA event
17 I2C6 I2C6 DMA event
18 I2C1 I2C1 DMA event
19 I2C2 I2C2 DMA event
20 I2C3 I2C3 DMA event
21 I2C4 I2C4 DMA event
22 UART1 Rx FIFO
23 UART1 Tx FIFO
24 UART2 Rx FIFO
25 UART2 Tx FIFO
26 UART3 Rx FIFO
27 UART3 Tx FIFO
28 UART4 Rx FIFO
29 UART4 Tx FIFO
30 - Reserved
31 - Reserved
32 ENET_QOS ENET_QOS 1588 Event 0
33 ENET_QOS ENET_QOS 1588 Event 1
34 ENET_QOS ENET_QOS 1588 Event 2
35 ENET_QOS ENET_QOS 1588 Event 3
36 Flexspi Flexspi DMA TX request
37 Flexspi Flexspi DMA RX request
38 GPT1 GPT1 counter event
39 GPT2 GPT2 counter event
40 GPT3 GPT3 counter event
41 - Reserved
42 - Reserved
43 - Reserved
44 ENET1 ENET1 1588 Event 2
45 ENET1 ENET1 1588 Event 0
46 ENET1 ENET1 1588 Event 3
47 ENET1 ENET1 1588 Event 1
Table 7-7. SDMA2/SDMA3 event mapping
SDMA Module Description
0 SAI1 SAI-1 receive DMA request
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Table 7-7. SDMA2/SDMA3 event mapping (continued)
SDMA Module Description
1 SAI1 SAI-1 transmit DMA request
2 SAI2 SAI-2 receive DMA request
3 SAI2 SAI-2 transmit DMA request
4 SAI3 SAI-3 receive DMA request
5 SAI3 SAI-3 transmit DMA request
6 - Reserved
7 - Reserved
8 SAI5 SAI-5 receive DMA request
9 SAI5 SAI-5 transmit DMA request
10 SAI6 SAI-6 receive DMA request
11 SAI6 SAI-6 transmit DMA request
12 SAI7 SAI-7 receive DMA request
13 SAI7 SAI-7 transmit DMA request
14 IOMUX external DMA from pad through IOMUX #1
15 IOMUX external DMA from pad through IOMUX #2
16 ASRC ASRC Context 0 receive DMA request
17 ASRC ASRC Context 0 transmit DMA request
18 ASRC ASRC Context 1 receive DMA request
19 ASRC ASRC Context 1 transmit DMA request
20 ASRC ASRC Context 2 receive DMA request
21 ASRC ASRC Context 2 transmit DMA request
22 ASRC ASRC Context 3 receive DMA request
23 ASRC ASRC Context 3 transmit DMA request
24 MICFIL PDM Digital Microphone Interface DMA request
25 - Reserved
26 AUD2HTX AUDIO Link Master To HDMI TX DMA request
27 - Reserved
28 - Reserved
29 - Reserved
30 AUDIO_XCVR eARC RX DMA request
31 AUDIO_XCVR eARC TX DMA request
32 - Reserved
33 - Reserved
34 - Reserved
35 - Reserved
36 - Reserved
37 - Reserved
38 GPT4 GPT4 counter event
39 GPT5 GPT5 counter event
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Table 7-7. SDMA2/SDMA3 event mapping (continued)
SDMA Module Description
40 GPT6 GPT6 counter event
41 - Reserved
42 - Reserved
43 - Reserved
44 - Reserved
45 - Reserved
46 - Reserved
47 - Reserved
7.2 Smart Direct Memory Access Controller (SDMA)
7.2.1 Overview
The Smart Direct Memory Access (SDMA) controller offers highly-competitive DMA
features combined with software-based virtual-DMA flexibility. It enables data transfers
between peripheral I/O devices and internal/external memories.
The SDMA controller helps maximize system performance by off-loading the Arm core
in dynamic data routing.
7.2.1.1 Block Diagram
The figure below shows a block diagram of the SDMA controller. It includes the custom
RISC core along with its RAM, ROM, DMA units, and the scheduler.
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AP Peripherals AP Memory
32 32
Peripheral Burst
DMA DMA
32 32
Functional Units Bus
AP
AP
Peripheral
Control
Bus 32
Scheduler On CE JTAG
DMA SDMA Core
48 Interface
Requests
data instructions
32 16
System Bus
32 32 32 32
SDMA
SPBA RAM ROM
REGISTERS
32
External to SDMA
Per #1 Per #... Per #14
Figure 7-1. SDMA Block Diagram
The SDMA core executes short routines that perform DMA transfers; these routines are
called scripts. The SDMA core interfaces to its own memory via the SDMA system bus.
The SDMA system bus supports a 32-bit data path and a 16-bit address bus. The system
bus datapath is used for both 16-bit instruction (program) memory access and 32-bit data
access. DMA units interface to the core via the Functional Unit Bus and use dedicated
registers to perform DMA transfers.
The SDMA memory contains a ROM and a RAM. The ROM contains startup scripts (for
example, boot code) and other common utilities, which are referenced by the scripts that
reside in the RAM. The internal RAM is divided into a context area and a script area
(more details about this mapping are available in Instruction Memory Map and Data
Memory Map).
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Every transfer channel requires one context area to keep the contents of all the core and
unit registers while inactive. Channel scripts are downloaded into the internal RAM by
the SDMA using a dedicated channel that is started during the boot sequence. Downloads
are invoked using commands and pointers provided by the Arm platform. Every channel
contains a corresponding channel script located in RAM and/or ROM that can be
reconfigured independently as-needed. Channel scripts can be stored in an external
memory and downloaded when needed. The SDMA can be configured with any mixture
of scripts to enable an endless combination of supported services.
The scheduler monitors and detects DMA requests, mapping them to channels, and
mapping individual channels to a pre-configured priority. At any given point, the
scheduler presents the highest priority channel that requires service to the SDMA core. A
special SDMA core instruction is used to "conditionally yield" the current channel being
executed to an eligible channel that requires service. If (and only if) there is an eligible
channel pending, will the current channel execution be preempted.
There are two yield instructions that differently determine the eligible channels: In the
first version, eligible channels are pending channels with a strictly higher priority than the
current channel priority. In the second version (yieldge), eligible channels are pending
channels with a priority that is greater or equal to the current channel priority. The
scheduler detects devices that need service through its 48 DMA request inputs. After a
request is detected, the scheduler determines the channel(s) that is (are) triggered by this
request and marks it (them) as pending in the "Channel Pending (EP)" register. The
priorities of all the pending channels are continuously evaluated in order to update the
highest pending priority. The channel pending flag is cleared by the channel script when
the transfer has completed.
The Arm platform control block contains the control registers used to configure the 32
individual channels. There are 48 Channel Enable registers, and every register maps one
DMA request to any desired combination of channels. The 32 Priority registers are used
to assign a programmable 1-of-7 level priority to every possible channel. This block also
contains all other control registers that the Arm platform can access.
The 48 DMA requests that are connected to the scheduler come from a variety of sources.
The "receive register full" and "transmit register empty" signals found in the UART and
USB ports are typical examples of DMA requests that can be connected to the SDMA.
These requests can be used to trigger a specific SDMA channel, or several channels.
There is an OnCE compatible debug port for product development. The OnCE includes
support for setting breakpoints, single-step and trace, and register dump capability. In
addition, all memory locations are accessible from the debug port.
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7.2.1.2 Features
The following are the SDMA features:
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
• Hardware or software driven triggers for each channel
• 48 hardware driven triggers that can be mapped to any channel.
• Memory accesses including linear addressing, FIFO addressing and 2D addressing
• Fast context-switching with two-level, priority-based preemptive multi-tasking
• 16-bit instruction-set micro-RISC engine (the SDMA core)
• Two DMA units with some or all the following features:
• Auto-flush and prefetch capability
• Flexible address management (increment, decrement, and no address changes on
source and destination address)
• Misaligned data-transfer support
• Uni-directional and bi-directional flows (copy mode)
• Up to eight-word buffers for configurable burst transfers
• Support of byte-swapping
• An available API and library of scripts
• Little-Endian and Big-Endian modes
• Hardware handshakes for low-power entry sequence
• Security support to lock contents of the SDMA script RAM.
• 4-Kbyte ROM containing startup scripts (for example, boot code) and other common
utilities that can be referenced by RAM-located scripts
• 8-Kbyte RAM area is divided into a processor context area and a code space area
used to store channel scripts that are downloaded from the system memory
• Debug support, including a OnCE port, real-time monitors, and embedded cross-
trigger events
• Supported clock frequencies in process:
• Configurable clock options for the SDMA core and the Arm platform DMA
units
• 1:2 ratio with maximum of SDMA core running at Arm platform Peripheral
Bus speed and DMA running at max DMA frequency.
• 1:1 ratio when both SDMA core and Arm platform DMA clocks are set to
the Arm platform Peripheral Bus speed.
• Peripheral bus interface for configuration register programming by the Arm platform
• The SDMA RISC engine (arithmetic and logic operations), which is referred to as the
"SDMA core."
• An internal peripheral bus connected to the Shared Peripherals Bus Interface (SPBA)
that enables access to up to 14 shared peripherals. SDMA supports 32-bit accesses to
word peripherals and 16-bit accesses to half-word peripherals.
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• The peripheral DMA unit that is hooked-up to the Arm platform Crossbar Switch to
service Arm peripherals
• The burst DMA unit is able to perform burst accesses to the external memory
• All the DMA units are 32-bit AHB masters. They are connected to different buses,
thus allowing concurrent accesses.
7.2.2 External Signals
The table found here describes the external signals of SDMA.
7.2.3 Functional Description
The figure below shows the SDMA topology, and is composed of the following
components:
• SDMA Core (SDMA Core)
• SDMA Scheduler (Scheduler)
• Functional Units:
• Burst DMA (Burst DMA Unit)
• Peripheral DMA (Peripheral DMA Unit)
• Arm platform Control for Arm control register access.
• Internal RAM and ROM Memory (SDMA Programming Model)
• OnCE debug Port (The OnCE Controller)
The functional unit bus provides access by the SDMA core to the DMA units. The system
bus provides access to SDMA internal memory and also supports up to 14 peripherals.
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Periph Periph Periph
Periph Periph Periph
AIPS MemCtrl RAM
External Memory
EMI
AIPS
Platform
Xbar
AP
Switch
StarCore
Platform
Per DMA Burst DMA BP DMA Xbar
Unit unit unit Switch
functional units bus
MemCtrl
AP Peripheral Bus AP Control ROM
SDMA
OnCE
DMA Requests Scheduler µRISC RAM
core M2/M1
BP Peripheral Bus BP Control Regs
peripheral bus
AP BP
Peripheral SPBA Peripheral
Bus Bus
Per# 1 ... Per# 14
Figure 7-2. SDMA Connections
7.2.3.1 SDMA Core
The SDMA core is a customized RISC-like processor that is specifically developed to
control DMA units and perform L1 tasks like byte-stuffing or framing.
The SDMA core incorporates on-chip debug capability using the OnCE.
The SDMA core is based on a 32-bit register architecture with 16-bit instructions. There
are eight general purpose 32-bit registers, four flags (T, LM, SF, and DF), and four PCU
registers (PC, RPC, SPC, and EPC) that can address 16,384 16-bit instructions.
7.2.3.1.1 SDMA Core Structure
The figure found here shows the structure of the SDMA core. It also shows the different
registers, calculation resources, and possible data movements.
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DECR
GREG0
32
32
GREG1
GREG2
ALU
GREG3
32
GREG4
32
32 GREG5
GREG6
8
SF DF T LM
GREG7
Flags
General Registers
Instruction Decoder
5
16
Instruction
AGU
32 8 32 16
PC
RPC
14 14
SPC
(instruction)
EPC
address
address
address
data
data
data
PCU
FUBUS DMBUS IBUS
Figure 7-3. SDMA Core
• The Program Control Unit (PCU) is described in Program Control Unit (PCU). It
handles the state of the core and generates the instruction fetch addresses.
Instructions are retrieved from the Instruction Bus (IBUS) and stored in the SDMA
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core instruction register prior to their decoding. The PCU contains the following
registers:
• The Program Counter (PC) contains the address of the current instruction.
• The Return Program Counter (RPC) contains the address of the instruction that
follows a jump to the subroutine.
• The Start Program Counter (SPC) contains the address of the first instruction of
the current hardware loop.
• End Program Counter (EPC) contains the address of the last instruction of the
current hardware loop.
• The other core registers are the general purpose registers (GREGn) and the flags.
• The general purpose registers can be used to hold data and addresses. They can
be loaded with immediate values (for example, 8-bit data that are encoded in the
instruction), results of calculations that were performed with the ALU, 32-bit
data that comes from the memory or peripherals via the Data Memory Bus
(DMBUS), 32-bit data that comes from the DMAs via the Functional Units Bus
(FUBUS) or another general purpose register. Their content can be the operands
of the ALU, the data to send on either bus (DMBUS or FUBUS), or a pointer to
memory (DMBUS address).
• The general register 0 (GREG0) is also the hardware loop counter. In hardware
loops, it cannot be used for any other purpose. This register uses a dedicated
decrement unit (DECR) shown in Figure 7-3.
• The flags reflect the status of operations:
• SF and DF are set when the last load or store on either bus (FUBUS or
DMBUS) received an error response.
• LM is set when the core is executing instructions inside a hardware loop.
• T is set when the ALU operation result was 0 or the loop counter reaches 0
(the latter is preponderant when an ALU operation is the last instruction of a
hardware loop).
• The ALU has two operands: any general register and either a second general register
or an immediate value. The result is always stored into the first general register. A
NOP function can be utilized by moving a register's contents into itself (For example,
the instruction: mov R0,R0).
• The 16-bit instructions are fetched via the instruction bus (IBUS) whose address is
driven by the PC. The SDMA RAM and ROM are visible to the core as 16-bit
devices through this interface.
• The memory (RAM and ROM), memory mapped registers, and external peripherals
are accessed via the DMBUS. The address is always taken from a general register
whose content is added to a 5-bit immediate value. This is the only available
addressing mode. The DMBUS is a 32-bit data bus. Except for the peripherals that
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are external to the SDMA, the address accuracy is the 32-bit word (for example,
adding 1 to an address points to the next word, not the next byte).
• The functional units are accessed via the FUBUS connection. The data is exchanged
with any general register, but the address (which in fact is the instruction and the
selector of the functional unit) comes from an 8-bit field of the corresponding load or
store.
7.2.3.1.2 Program Control Unit (PCU)
This part of the SDMA core is dedicated to the control of the RISC engine, as implied by
the instructions that are executed. Its behavior is determined by the instruction type and
the inputs of the SDMA.
It contains the PC, RPC, SPC, and EPC registers that are described in SDMA Core
Structure.
7.2.3.1.2.1 Instruction Types
The state sequence and the delay of execution vary according to the type of the
instruction. There are six possible categories of instructions, as follows:
1. Standard: Most of the instructions belong to this category, and always last 1 cycle.
2. ldf/stf: These are respectively the load and store instructions that access the
functional units. They last 1+n cycles where n is the number of wait-states of the
targeted functional unit.
3. ld/st: These are the load and store instructions that access the memory and
peripherals. They last 1+n cycles where n is the number of wait-states of the targeted
device (1 for the ROM, RAM, and memory mapped registers, 1 + the external
peripheral wait-states). These instructions always last at least two cycles, but the core
is able to handle them in one cycle. The first wait-state is inserted outside the core.
4. Branch: These are all the instructions that cause the Program Counter to point to
another instruction other than the following one (for example, one that breaks the
sequential flow). There are the absolute jumps, the conditional branches, the jump to
the sub-routines, and the return from the sub-routine.
5. Loop,Modified Load or Store: The hardware loop instruction modifies the potential
behavior of any load or store inside the loop (for example, when the LM flag is set).
A jump may be implied after any such load or store if it received an error. The error
causes an early exit of the loop, which means a jump to the instruction that follows
the one that is pointed to by EPC. An additional cycle is required by the PCU to
perform the jump (+1 to the ld/st/ldf/stf original execution delay). Although there is
usually an implicit jump after the last instruction of the loop when the PC goes back
to SPC, this is performed at no cycle cost.
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6. Done: The done, yield, or yieldge instructions are used to control channel switching.
When no channel switching is performed, these instructions last a single cycle. When
there is a change of channel or context switch, the delay is variable and depends on
many factors (as detailed in Context Switching).
7.2.3.1.2.2 PCU States
The PCU state is visible through outputs of the SDMA (see Real-Time Debug Outputs)
or the OnCE status register(see OnCE Status Register (OSTAT)).
The PCU state is a four-bit field that can take the values shown in the following table.
Figure 7-4 shows the possible state transitions and the corresponding conditions.
Table 7-8. PCU States
Value State Description
0 Program This is the usual instruction cycle.
1 Data This state is inserted when there are wait-states during a load or a store on the
data bus (ld/st type).
2 Change of Flow This is the second cycle of any instruction that breaks the sequence of
instructions (branch and done types). This state lasts only a single cycle; it is
always followed by the Program state.
3 Error in Loop This state is used when an error causes a hardware loop exit (loop-modified load
or store type). This state only lasts a single cycle; it is always followed by the
Program state.
4 Debug The SDMA is stopped in debug mode.
5 Functional Unit This state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf/stf type).
6 Sleep No script is running: The core is idle after saving the last channel context.
7 Save The context switch FSM is saving the current channel.
8 Program in Sleep Same as Program except there is no associated channel, this state is used when
instructions are executed after entering debug mode, whereas the core was in
either Sleep mode.
9 Data in Sleep This is the same as Data except there is no associated channel.
10 Change of Flow in Sleep This is the same as Change of Flow except there is no associated channel. This
state only lasts a single cycle, and is always followed by the Program in Sleep
state.
11 Error in Loop in Sleep This is the same as Error in Loop except there is no associated. channel. This
state only lasts a single cycle, and is always followed by the Program in Sleep
state.
12 Debug in Sleep This is the same as Debug except the core was put in debug mode when no
channel was active.
13 Functional Unit in Sleep This is the same as Functional Unit except there is no associated channel.
14 Sleep after Reset This shows that no script is running, and the core is idle after a reset. When a
channel becomes active, no context is restored but the core starts its boot
program located at address 0 (or the address available in register in Channel 0
Boot Address (SDMAARM_CHN0ADDR)).
15 Restore The context switch FSM is restoring the next channel context.
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Id/st
loop-modified
Idf/stf
error in
loop-modified
error in
ack
Data load/store Error in Loop
loop-modified
error in
in Id/st
wait-states
Functional Unit Change of Flow
ack
branch
in Idf/stf
wait-states
Program
PC is
context Restored
switch
pending
(done) channel(s)
Save Restore
no more
channels
pending pending
channel(s) channel(s)
run_core run_core
when coming from when coming from
Sleep after Reset Sleep
Sleep Debug
Sleep
After Reset in Sleep
debug debug
request request
reset debug
exec_once or request or
exec_core exec_once
completed done
Program
in Sleep debug
debug request or
request wait-states exec_once
branch in Idf/stf completed
Change of Flow ack Functional Unit
in Sleep in Sleep
debug
debug request or
request wait-states exec_once
error in
in Id/st completed
loop-modified
Error in Loop load/store Data
in Sleep in Sleep
ack
error in
loop-modified error in
ldf/stf loop-modified
ld/st
Figure 7-4. PCU State Diagram
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7.2.3.1.3 SDMA Core Memory
The SDMA has two memory spaces: one for the instructions and one for the data. As
both spaces share the same resources (ROM and RAM devices), the system bus manages
possible conflicts when the core accesses the same resource for both an instruction read
and a data read or write.
Program and data memory is further described in Address Space.
Instructions of 16-bit width are stored in 32-bit wide devices and can be accessed as data.
The mapping is Big Endian: an even instruction address (terminated by 0) accesses the
most significant part of the 32-bit data (bits [31:16]), and an odd instruction address
(terminated by 1) accesses the least significant part of the 32-bit data (bits [15:0]).
Instructions can be fetched out of internal ROM or RAM.
Data can be read from ROM, RAM, memory mapped registers, and external peripherals,
and written to the same devices (except the ROM).
The ROM contains bootload scripts, channel scripts, and common subroutines which may
be referenced by channel scripts elsewhere in the ROM or RAM.
The RAM is divided into a context area and a code space area which may be used to store
channel scripts. The RAM contains undefined values after a hardware reset. Channel
scripts and initial context values are downloaded into RAM using channel 0 which is
reserved for bootload functions.
7.2.3.2 Scheduler
All channel scheduling hardware is included in the Scheduler.
7.2.3.2.1 Primary Functions
The scheduler is a hardware-based design used to coordinate the timely execution of 32
virtual DMA channels by the SDMA core on the basis of channel status and priority.
The scheduler performs the following functions:
• Monitors, detects, and registers the occurrence of any one of the 48 DMA requests
• Links a specific request to a channel or group of channels (channel mapping)
• Ignores requests that are not mapped to a previously configured channel
• Maintains a list of all the channels that are requesting service
• Assigns a pre-programmed priority level (1 of 7) to every channel requesting service
• Detects and flags overrun/underrun conditions
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7.2.3.2.2 Channels and DMA Requests
7.2.3.2.2.1 Channels
A Virtual Channel (hereafter simply called a channel) manages a flow of data through the
SDMA. Flows are typically unidirectional.
The SDMA can have up to 32 simultaneously operating channels, numbered from 0 to
31. Channel 0 is usually dedicated to control the SDMA script downloading. All the
channels can be assigned by the Arm platform software.
7.2.3.2.2.2 DMA Requests
A DMA request is caused by externally (for example, external to the SDMA) controlled
conditions (for example, UART receive FIFO reaches a threshold). The SDMA currently
supports up to 48 DMA requests.
7.2.3.2.2.3 Mapping from DMA Requests to Channels and Priorities
A channel can stall waiting on a single DMA request. A single DMA request can awake
more than one channel (in fact, any request can awake any combination of channels).
The mapping between DMA requests and channels is program-controlled. There is a
storage element assigned for each of the 48 requests that contains a bitmap table of the
channels that are awakened by the event.
Every channel also has a three-bit register that indicates its priority.
7.2.3.2.3 Scheduler Functional Description
Scheduler Overview describes the behavior of the SDMA scheduler-from the channel
enabling conditions to the highest priority pending channel selection.
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7.2.3.2.3.1 Scheduler Overview
The scheduler algorithm is built in hardware. It is provided with possibilities for the Arm
platform to control its behavior.
The scheduler processes incoming DMA requests, maps detected requests to 0, one, or
several channels, maintains a list of channels that are requesting service (pending
channels), identifies the top priority and its associated channel, and selects the next active
channel when the current channel yields.
The following figure shows a functional overview.
Channel Enable for DMA request 0 CHNENBL_0
Channel Enable for DMA request 46 CHNENBL_46 Channel Error
Channel Enable for DMA request 47 CHNENBL_47 CHNERR
48
32
48 6 DMA request 32
DMA DMA requests Channel overflow
to pending channel
requests scanning detection
mapping
32
32
Channel Pending from External DMA Requests EP
32 5
External DMA request Override EO Runnable channels
32 Current Channel
Arm Platform Channel Enable HE evaluation
32
Arm Channel Enable Overide HO
32
Channel 31 Priority CHNPRI31 32
Next channel 5
Channel 30 Priority CHNPRI30 32 Current Channel
decision tree
Channel 0 Priority CHNPRI0 32
16 5
Decision Status PSW Next Channel
Figure 7-5. SDMA Hardware Scheduler
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7.2.3.2.3.2 DMA Requests Scanning
The scheduler contains a 48-bit edge detection device that detects the rising edge of every
DMA request and transmits the request number to the next stage.
The DMA requests are assumed to be generated on the same reference clock as the
SDMA core clock; they are detected as soon as the signal goes from a 1-to-n-cycles low
state to a 1-to-m-cycles high state.
This system is able to detect single-cycle pulses as well as level-based DMA requests
such as a FIFO threshold crossing. In this case, the SDMA provides a memory mapped
register that can be used by the channel script to monitor the DMA requests lines, and
thus determines whether the data transfer is done or not done, and then continues with the
transfer or closes the channel.
When several DMA requests are detected at the same time, they are forwarded to the next
scheduler stage at the rate of one request per cycle. No request is lost.
SDMA clock
Long Pulse
Level
Short Pulse
Requests are detected here
Figure 7-6. Examples of Valid DMA Requests
The DMA request inputs are connected to various sources that depend on the SoC. The
exact list of DMA request inputs and their associated number is available in each
respective project-specific chapter.
7.2.3.2.3.3 Mapping DMA Requests to Pending Channels
Whenever a DMA request is detected by the first stage, its number is used in the second
stage to determine the channels that have to be activated.
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This is performed with an array of 48 registers that are 32 bits wide: There are 48
Channel Enable Registers (CHNENBLn), one register per DMA request. The DMA
request number selects the Channel Enable Registers, and every bit of this 32-bit register
indicates that the corresponding channel must be activated when it is a 1.
This information is passed on the EP register. For every bit of the Channel Enable
Register that is set, the corresponding bit of the EP register is also set, and the remaining
bits of EP are left unchanged. The transformation of EP is summarized by the following
equation:
EP = EP or CHNENBLn
The EP register is used to know which channels require service because they received a
DMA request.
Typical contents of the CHNENBLn registers are all 0s, except for a single bit set. For
example, a DMA request triggers one channel, but all 0s or several 1s are possible. One
DMA request could activate several channels, and the channel execution sequence can be
controlled by the channel priorities and numbers, as explained in the next sections. The
following table illustrates an example configuration.
NOTE
From the table, the DMA request 0 is programmed to
simultaneously trigger channels 0, 1, and 31. Also, DMA
requests 30-47 are not used in this example. The remaining
channels 2 to 30, are configured to be triggered by DMA
requests 29 to 1, respectively.
Table 7-9. Channel Enable RAM Programming Example
Channel
3 0
DMA Request Number
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 7-9. Channel Enable RAM Programming Example (continued)
Channel
3 0
DMA Request Number
6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
9 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
10 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 7-9. Channel Enable RAM Programming Example (continued)
Channel
3 0
DMA Request Number
38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
43 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
45 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
46 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.2.3.2.3.4 Channel Overflow
A channel overflow occurs when a DMA request requires service from channel n by
setting bit n of the register EP, but this bit is already set, meaning channel n is already
pending. This can come from an overrun/underrun condition.
This detection is possible only when the DMA requests are pulses, because a level-based
DMA request stays high until it is serviced, even though an underrun or overrun
condition occurs, thus preventing another edge detection of the DMA request.
The channel overflow information is saved in the 32-bit CHNERR register (1 bit per
channel). You can configure the SDMA to trigger an interrupt to the Arm platform when
there are 1s in CHNERR. Every bit of CHNERR is masked with the corresponding bit of
INTRMASK and if it gives a 1, the corresponding bit of INTR is set, triggering the
interrupt.
7.2.3.2.3.5 Runnable Channels Evaluation
The EP register is used in conjunction with several other 32-bit registers to determine the
channels that are runnable.
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Registers EO, DO, HO and HE, are controlled by the Arm platform. EP is controlled by
the DMA requests and their mapping to channels.
Several channels may be runnable at any given time. The ith channel is runnable if (and
only if) the condition below is true:
(HE[i] or HO[i]) and (DO[i]) and (EP[i] or EO[i])
After reset, the HE[i], HO[i], EP[i], and EO[i] bits are all cleared whereas the DO[i] bits
are all set. The functions associated with DO are not available for this device. When
DO[i] is set, the scheduler condition becomes:
(HE[i] or HO[i]) and (EP[i] or EO[i])
The registers in these equations are controlled as follows:
• Arm platform (host) channel enable flag HE[i] may be set or cleared by the Arm
platform with the HSTART and STOP_STAT registers. It can also be cleared by the
ith channel script.
Typical usage is for the Arm platform to set this flag to activate the channel. The flag
is cleared by the SDMA core when the transfer is done.
• Externally triggered channel pending flag EP[i] is set by the scheduler when the
channel was activated by a DMA request. It can be cleared by the ith channel script.
• The Arm platform channel override flag HO[i] may be set or cleared by the Arm
platform. When set, it enables the ith channel to run without the involvement of the
Arm platform.
Typical usage is for the Arm platform to set this flag for channels that do not need
Arm platform supervision such as channels that are controlled by DMA request
events (EP).
• DO should always be set to 1 so that the runnable channel evaluation considers only
HO, HE, EP, and EO.
• Externally triggered channel override flag EO[i] may be set or cleared by the Arm
platform. When set, it prevents the ith channel from stopping and stalling on
incoming peripheral DMA requests. This is the case when the channel is not handling
data transfers with peripherals (for example, a memory to memory transfer).
The SDMA can clear the HE[i], and EP[i] bits by means of a done or notify instruction.
The done instruction causes a reschedule; thus, enabling another channel to preempt the
current one, while the notify instruction does not. The done and notify instructions can
clear either HE[i] or EP[i] (never more than one at a time).
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Table 7-10. Runnable Channel Selection Control
Register Set by Cleared By
HO Write to HOSTOVR register Write to HOSTOVR register
HE Write to HSTART register Write to STOP_STAT register or by the channel script
with the done or notify instructions.
DO Write to DSPOVR register Write to DSPOVR register
EO Write to EVTOVER register Write to EVTOVER register
EP Set by external DMA request event input. By the channel script with the done or notify instructions
7.2.3.2.3.6 Next Channel Decision Tree
The next channel number is computed from the runnable channels list, the current
channel number, and their respective priorities.
It is re-evaluated every cycle, but is only used when the current channel yields or
terminates by executing a yield, yieldge, or done instruction.
The decision tree is based on the selection of the runnable channel that has the highest
priority.
The highest priority channel is selected according to the following rules:
• Runnable channels are sorted by priority.
• If one of the channels with the highest priority had been preempted by a channel with
a higher priority, but did not want to yield to a channel of the same priority (for
example, it executed a yield, not a yieldge), it is elected as the next channel.
• The channels that belong to the highest priority group are sorted by their number and
the channel that has the highest number in this group becomes the next channel. For
example, if priorities are the same, channel 31 will be selected before channel 30.
When the current channel requires a reschedule with a yield(ge) or a done instruction, the
context switch decision is based on the instruction parameter, the current channel number
and priority, and the next channel number and priority. The possible cases are all listed in
the following table. The grayed cells correspond to unusual cases that should not occur
with a typical usage of the SDMA.
Table 7-11. Channel Switching Decision with a yield, yield(ge), or done
Instruction Current Next Channel Priorities New Running Channel/Comments
Channel Comparison
yield (done 0) Runnable Not runnable none Current
Runnable Runnable Current > Next Current
Current = Next Current
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Table 7-11. Channel Switching Decision with a yield, yield(ge), or done (continued)
Instruction Current Next Channel Priorities New Running Channel/Comments
Channel Comparison
Current < Next Next, 1
Not runnable Not runnable none none, 2
(occurs when the channel was disabled by the
Arm platform)
Not runnable Runnable none Next1
(occurs when the channel was disabled by the
Arm platform)
yieldge (done 1) Runnable Not runnable none Current
Runnable Runnable Current > Next Current
Current = Next Next1
Current < Next Next1
Not runnable Not runnable none none2
(occurs when the channel was disabled by the
Arm platform)
Not runnable Runnable none Next1
(occurs when the channel was disabled by the
Arm platform)
done (done>1) Not runnable Not runnable none none2
Runnable Not runnable none Current3
(occurs when the done instruction does not
disable the channel runnable condition)
Not runnable Runnable none Next1
Runnable Runnable none Current3
(occurs when the done instruction does not
disable the channel runnable condition)
1. Current channel script execution is stopped, its context is saved; the next channel context is restored and its script
execution resumes
2. Current channel context is saved and SDMA enters IDLE mode
3. Current channel context is saved, then restored, and the current channel script resumes execution
Finally, when the SDMA is in IDLE mode and a runnable channel is elected as the next
channel, its context is immediately restored and the script execution resumes.
The combinatorial-decision tree supports dynamic modifications of the EP, EO, HE, HO,
and DO flags as well as dynamic modifications of the channel priorities. The propagation
times are detailed in Scheduler Pipeline Timing Diagram.
The decision tree status is available in the PSW register, which is continuously updated.
It contains the next channel priority, the next channel number, the current channel
priority, and the current channel number. When a priority is read as 0, it means the
channel is not runnable.
A few examples of decisions are presented below:
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• Channel 31 is running with priority 5, channels 13 and 24 are pending with the same
priority 5; channel 24 is eligible as the next channel since 24 > 13.
• Channel 31 is running with priority 7, channels 13 and 24 are pending with priority
5; channel 31 is the next channel because its priority is greater than the other pending
channels.
• Channels 7, 23, and 29 are pending with the same priority. Channel 7 is active and
runs a yieldge; it is preempted by channel 29. After a period of time, channel 29 runs
a yieldge, it is then preempted by channel 23 that is the selected channel since
channel 29 is the current channel. Later, channel 23 runs a yieldge and is preempted
by channel 29. Channels 23 and 29 will go on switching after every yieldge until one
of them terminates. It is only at that point that channel 7 becomes eligible again.
• Channel 11 is running with priority 3, and channel 15 is pending with priority 4.
When the channel 31 script executes a yield instruction, it gets preempted by channel
15; then channels 6 and 18 with priority 3 become pending. Because channel 11 was
preempted after executing a yield and there is no pending channel with a strictly
greater priority, it is eligible as the next channel (although its number 11 < 18).
7.2.3.2.3.7 Scheduler State Diagram
The Figure 7-7 summarizes the behavior of the SDMA scheduler with details about the
exact mechanism of the priority decision tree. It is important to understand the scheduler
is a hardwired pipeline, which means all the stages are performed simultaneously every
cycle, but a change on any given stage is reflected on the next stage after the delays
presented in Scheduler Pipeline Timing Diagram.
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SDMA AP
DMA Mapping to new ctrl regs ctrl regs
request pending channels update update
#n
done
Repeat 32 times
for every channel #i
is channel #i Yes Set error for
already channel #i
Sort channels pending?
per priority
No Evaluate channel #i
runnable condition
Sort highest priority
channels per number
No is channel #i
Next channel = Channel #i
priority(i) = 0 runnable?
highest number among
highest priority channels
Yes
Channel #i
priority(i) = CHNPRI(i)
yield AND
Yes INT (priority(current))>
INT(priority(next))
No is channel #i the Yes
current channel
yieldge AND
Yes priority (current)>
priority (next) No
Channel #i
No priority(i) = priority(i) + 0.5
Stop the current channel Yes
done
and save its context Channel #i
Channel #i Yes
was preempted
priority(i) = priority(i) + 0.25
after a yield?
No
No
is the
current channel active: Yes
priority (current)>0?
No
is the next
Yes channel active:
priority (current)>0?
No
Restore the next channel SDMA core
context and run it is in IDLE mode
END
Figure 7-7. Scheduler State Diagram
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7.2.3.2.3.8 Scheduler Pipeline Timing Diagram
The SDMA scheduler process of DMA-request and control-register modifications is not
immediate.
The figure below shows the exact delays of all the tasks. The reference clock is the
SDMA core clock.
SDMA Clock
1 2 3 4 5 6 1 2 3
DMA Request
mapping to EP
control regs update
(EP, HE, DO, HO)
runnable channels
decision
next channel
Figure 7-8. Scheduler Timing Diagram
Two numbers can be inferred from this timing diagram. First, it takes six SDMA core
clock cycles to update the next channel from a DMA request. Second, it takes three
SDMA core clock cycles to update the next channel from a direct modification of the
condition registers (EP, DO, HE, or HO) by any processor. The processors that can
modify these bits include SDMA with a done instruction or the Arm platform with a
write access through the corresponding control port on their respective peripheral bus).
7.2.3.2.3.9 Channel-DMA Request Mapping
The 48 DMA request inputs to the SDMA scheduler are listed in project-specific
chapters. Refer to the respective chapters for this information.
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7.2.3.2.3.10 Examples: How to Start a Channel
A channel can be started when the following equation is true for channel i:
(HE[i] or HO[i]) and (DO[i]) and (EP[i] or EO[i])
Once this equation is true, the scheduler can start this channel according to the priority of
all pending channels. Several examples of configuration are listed below:
1. To start a channel triggered by Arm platform software:
• Initially, configure HO[i]=0, DO[i]=1, and EO[i]=1 using registers indicated in
Table 7-10.
• Arm platform software triggers the channel by writing to the HSTART register
to set HE[i]=1, thereby setting the above equation true.
2. To start a channel triggered by DMA request event.
• Initially, configure HO[i]=1, DO[i]=1, and EO[i]=0 using registers indicated in
Table 7-10.
• The DMA request is asserted to trigger the channel by setting EP[i]=1, which
makes the above equation true.
7.2.3.2.4 Context Switching
On execution of a done or yield(ge) instruction, the current channel may be changed
either because it has finished (which necessarily happens when the done instruction is
executed), or it was preempted by a higher priority channel (which is possible but not
systematic when the yield(ge) is executed).
Upon a channel change the SDMA goes through a context switch procedure.
When the current channel yields or ends, the context for that channel is saved into the
context RAM locations for that channel. When the next channel starts running, its context
is first restored from RAM.
Since context RAM is not yet initialized by reset, there will be no context restore at the
beginning of the first channel (bootload channel) run after reset. It is expected that the
bootload channel will be used to initialize the context for all other channels. When the
bootload channel finishes running or yields, SDMA will enter its SAVE state and save
that channel's context into RAM. Then, if the bootload channel is called again later, the
context will be restored from RAM when the channel starts again.
The context structure for each channel is defined in Context Switching-Programming and
Table 7-16. There will be one context area reserved for each channel. When a channel
ends or yields, the SDMA core registers are automatically saved into the context RAM
and later restored from the context RAM when the channel is next run. The total RAM
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space reserved for 32-channel contexts is either 3K or 4K depending on whether the
SMSZ bit is set in the CHN0ADDR register, which enables an additional 8 words of
scratch RAM for each context.
7.2.3.2.4.1 Context Switch Modes
The exact procedure to save the context of the old channel, and to restore the context of
the new channel depends on the context switch mode selected by the Arm platform in the
CONFIG control register.
The following are the context switch modes:
• By default, the "dynamic" context switch is set. This mode provides the most
efficient context switch for an average of eight cycles to stop the current channel,
save its context, restore the next channel context, and resume its execution. It
consists of saving modified registers of the current channel in the background (for
example, during the channel execution)-which leaves very few registers to save when
the switch is decided-resuming execution of the next channel as soon as possible (for
example, when the minimal set of registers is restored), and continuing the restore
phase during this execution.
• In "dynamic with no loop" mode, the same principle is followed except the modified
registers are only saved in the background when the loop flag is not set. This mode
offers almost the same effectiveness as the previous one, but it prevents the system
from accessing the RAM during loops to save power. This is the recommended mode
for an efficient context-switch when the loop bodies are short.
• In "dynamic power" mode, no background saving is performed, which reduces power
consumption to the minimum. The modified registers are only saved when the
context switch starts. The restore phase is the same as before. This is the mode that
achieves the optimal power consumption at the cost of a slower context-switch.
• In a "static" context switch, all the registers are saved when a context switch is
decided, and all the registers are restored before starting the execution of the new
channel. This mode enables a predictable behavior of the context switch since all the
registers are restored prior to the channel start and all registers are saved after the
channel termination.
NOTE
Static context mode should be used for the first channel called
after reset to ensure that the all context RAM for that channel is
initialized during the context SAVE phase when the channel is
done or yields. Subsequent calls to the same channel or
different channels may use any of the dynamic context modes.
This will ensure that all context locations for the bootload
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channel are initialized, and prevent undefined values in context
RAM from being loaded during the context restore if the
channel is re-started later.
7.2.3.2.4.2 Context Switch Procedure
The Program Control Unit goes into the save state, the current context is spilled into
memory, and the next channel context is restored according to the context-switch mode
that was selected by the Arm platform.
The context switch procedure is as follows:
1. Load the current context's spill base address.
2. Spill the modified registers of the current channel to memory according to the
selected context switch mode while the channel is running.
On a done or yield(ge) that causes the channel preemption, the PCU goes into the
save state. In static mode, all the registers are saved; whereas, in either dynamic
mode, the registers that were modified but not yet saved are then saved, and the PCU
registers and flags are finally saved.
3. Put the SDMA core into sleep and wait for new channels to be serviced. This step is
skipped if there are pending channels when the current channel is saved.
As soon as there is at least one pending channel, the PCU goes into its restore state to
restore the context of the channel that was elected by the scheduler.
Once a channel is elected, it remains the current channel until its script requests a
rescheduling operation with a done or yield(ge) instruction. That means the current
channel cannot be modified by the Arm platform, even if it is no more runnable or if
its priority is modified.
The Arm platform can however force a reschedule by writing the corresponding bit
in the CONFIG register, which has the same effect as if the script had executed a
done instruction. That feature should only be used to stop the SDMA in emergency
cases.
4. Load the context base-address of the new channel.
In "static" mode, all the registers are restored. In either "dynamic" modes, only the
PCU registers are restored.
The new channel is running. In "static" mode, no more activity regarding context
restoring or saving is performed. In either "dynamic" modes, the registers are
restored in the background every time an access to the context RAM is possible, and
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priority is given to restoring the registers that are required by the next instruction to
be executed. When a register has not been restored and the next instruction needs it,
this instruction gets stalled until the register was restored.
In "dynamic" and "dynamic with no loop" modes, background saving of dirty
registers is performed every time an access to the context RAM is possible and
allowed by the context switch mode.
NOTE
The contents of a channel context space in the context
RAM depends on the selected context switch mode. In
"dynamic" and "dynamic with no loop" modes, the contents
of the context RAM tend to match the contents of the
SDMA registers (except for the PCU registers and flags
that are never saved in the background). In "dynamic
power" and "static" modes, the contents of the context
RAM remain unchanged until the channel terminates with a
done or gets preempted.
7.2.3.2.4.3 Context Map in Memory
Refer to Context Switching-Programming.
7.2.3.3 Functional Units
The functional units are small systems that are used by the SDMA core to handle data
transfers between the core and a bus domain external to the SDMA.
The SDMA core is able to control and exchange data with these systems by sending
instructions and reading or writing data from/to the functional units' registers via the
FUBUS. This is done with the ldf and stf instructions.
The following sections provide introductions to the available functional units. Functional
Units Programming Model provides descriptions the functional units' behaviors.
7.2.3.3.1 Burst DMA Unit
The burst DMA unit enables the SDMA core to perform data transfers to and from the
Arm platform memory.
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It is optimized for accessing SDRAM-like devices. It does not provide control to assign a
privilege level to the DMA access. The burst DMA unit provides the SDMA with means
to do the following:
• Perform up to 8-beat read and write bursts to the Arm platform memory, which
optimizes throughput when accessing SDRAM-type devices because of an internal,
36-byte FIFO
• Access the Arm platform memory at once or twice the SDMA core frequency
• Copy data from one Arm platform memory location to another Arm platform
memory location at the Arm platform bus speed, which provides a very high
throughput
• Control the method for addressing the Arm platform memory (automatic increment
of addresses or frozen addresses-the former aimed at accessing RAM-like memory
and the latter aimed at accessing single-address FIFOs)
• Enable or disable automatic prefetch when reading data from the Arm platform
memory. When the prefetch mode is selected, the burst DMA automatically triggers
external bursts to fill its FIFO without waiting for the SDMA core to request the
corresponding data, greatly improving throughput.
• Rely on the DMA to automatically flush its FIFO content when there is enough data
to generate an 8-beat burst to the Arm platform memory. Or, it forces a flush when a
data transfer must terminate.
• In the former case, the SDMA core may only be stalled when it tries writing data and
there is not enough room left in the FIFO. In the latter case, the core is stalled until
the data is effectively written to the Arm platform memory.
In automatic flush mode, the core receives an acknowledge that does not reflect the
actual error status when the data is effectively written into the Arm platform
memory. This error status is retrieved by a later access to the burst DMA.
Terminating a write data transfer with a forced flush command guarantees that any
bus error to the Arm platform memory is caught.
• Handle address alignment issues between the Arm platform memory map and the
SDMA core data. This enables the core to read or write 32-bit data from the burst
DMA, whereas the corresponding Arm platform address is not 32-bit aligned. This
drastically improves the SDMA scripts' efficiency since the same loop that transfers
32 bits at a time can be used regardless of the start and end addresses in the Arm
platform memory space.
This unit structure and registers are described in Burst DMA Structure and Burst DMA
Registers.
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7.2.3.3.1.1 Burst DMA Structure
The burst DMA is essentially made up of a 36-byte FIFO, address registers, and a
controlling state-machine. The 36-byte FIFO enables eight-word buffering with address
alignment, and the state-machine manages clock adaptation when required.
The burst DMA is depicted in the figure below.
DMA interface to AP memory
read and write address control
32 32
data
Setup and FSM State (MS)
36-byte
FIFO Source Address (MSA)
(MD) Burst DMA
Control
Destination Address (MDA)
32 32 32
FUBUS
Figure 7-9. Burst DMA Structure
7.2.3.3.1.2 Burst DMA Registers
There are four registers, as follows, that may be accessed from the SDMA core:
• MSA (Memory Source Address) - Holds the source byte address in the Arm platform
memory map for reading data from this location. This register is automatically
modified every time the core reads new data from the FIFO.
• MDA (Memory Destination Address) - Holds the destination byte address in the Arm
platform memory map for writing data to this location. This register is automatically
modified every time the core writes new data into the FIFO.
• MD (Memory Data) - Labels the 36-byte FIFO access point: Reading a byte,
halfword, or word from MD respectively retrieves the first 1, 2, or 4 bytes of the
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FIFO (for example, the bytes that were stored first by the DMA state-machine when
transferring data from the Arm platform memory).
• When the FIFO does not hold as many bytes as required by the SDMA core, the core
is stalled until the missing bytes are read from the Arm platform memory. In the case
of prefetch mode, the DMA controller decides when it should start a burst to Arm
platform memory in order to reduce the risk to not have the required data for the
future accesses of the core. When there is no prefetching, a burst is triggered when
the required data is not available in the FIFO.
Writing a byte, halfword, or word to MD stores 1, 2, or 4 bytes, respectively, at the
end of the FIFO (for example, these bytes are transmitted to the Arm platform
memory after all the other bytes that were previously stored in the FIFO). When the
FIFO does not have enough room left to hold the written data, the SDMA core is
stalled until a sufficient amount of FIFO contents are flushed out to the Arm platform
memory. Flushing is decided by the DMA controller when there are enough bytes in
the FIFO to perform the largest allowed burst to Arm platform memory (the exact
size depends on the burst start address and the AHB 1 Kbyte boundary rule).
However, the SDMA core has the ability to force the flushing operation at any time,
for example, when at the end of the data transfer, prior to channel closure.
• MS (Memory Setup) - Contains the state of the burst DMA control, the two flags that
define whether each address register is incremented after every access to the external
memory, and another flag that is set when a bus error occurred.
7.2.3.3.1.3 Burst DMA Data Transfers
Three typical usages have been identified that involve the burst DMA: the data transfer
startpoint, the endpoint, or both.
Every case requires a different procedure, as listed in the following sections:
7.2.3.3.1.3.1 Data Retrieval from the Arm platform Memory
The following steps retrieve data from Arm platform memory using the burst DMA unit:
• Set up the MS flags to reflect the mode for the source address (incremented or frozen
according to the type of accessed device: memory or peripheral FIFO), then initialize
the source address register itself (MSA).
• Read data from the FIFO using the ldf MD instruction as many times as needed. If an
error occurred during the fetch from Arm platform memory, the DMA control tags
the error status on the data and the SDMA core SF flag is set when reading this data
from the FIFO.
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7.2.3.3.1.3.2 Storing Data Into the Arm platform Memory
The following steps store data from Arm platform memory using the burst DMA unit:
• Set up the MS flags to reflect the mode for the destination address (incremented or
frozen according to the type of accessed device: memory or peripheral FIFO), then
initialize the destination address register itself (MDA).
• Store data into the FIFO using the stf MD instruction as many times as needed.
• When the transfer is finished and if the DMA worked in automatic flush mode, force
the flush of the FIFO. This instruction is stalled until all the FIFO data is effectively
sent to the Arm platform memory and the error status of the transfer is available in
the DF flag.
7.2.3.3.1.3.3 Transferring Data Between Two Arm platform Memory Locations-Burst DMA
Unit
The following steps copy data between two Arm platform memory locations using the
burst DMA unit:
• Set up the MS flags to reflect the modes for the source and destination addresses (all
the combinations are possible), then initialize the source address register (MSA) and
the destination address register (MDA). Both addresses must be word-aligned.
• Use as many stf MD instructions with the COPY flag as needed. Every instruction
triggers a burst read of a given number of words from the source address (this
number is provided to the burst DMA via the SDMA core general purpose register,
which is referenced in the stf instruction). Once all the data is loaded into the FIFO,
the DMA empties it with a write burst of the same count to the destination address.
The DMA acknowledges prior to instruction completion, which frees the SDMA core
for other tasks at no delay cost.
• Once the transfer is done, there should be a final access to the burst DMA to check
the error status.
7.2.3.3.2 Peripheral DMA Unit
The peripheral DMA unit is the second functional unit that connects the SDMA to the
Arm platform memory.
Unlike the burst DMA, it does not support burst transfers and is optimized for accessing
peripherals. It does not provide control to assign a privilege level to the DMA access. Its
feature list comprises the following:
• Access to the Arm platform peripherals or memory at once or twice the SDMA core
frequency
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• Data copy from one Arm platform memory location to another Arm platform
memory location at memory bus speed, improving throughput
• Control of the method for addressing the Arm platform memory (automatic
increment or decrement of addresses or frozen addresses, the first ones aimed at
accessing RAM-like memory and the last one aimed at accessing single-address
FIFOs)
• Selectable automatic prefetch when reading data from the Arm platform memory. In
prefetch mode, the peripheral DMA automatically fetches another data-without
waiting for the SDMA core to request it-when its data register is empty, which
improves the throughput
• Selectable automatic flush. In this mode, the SDMA core may only be stalled when it
tries writing data and the previous write operation is not finished yet; whereas, in
forced flush mode, the core is stalled until the data is effectively written to the Arm
platform memory.
• In automatic flush mode, the core receives an acknowledge that does not reflect the
actual error status when the data is effectively written into the Arm platform memory
or the peripheral. This error status is retrieved by a later access to the peripheral
DMA. Terminating a write data transfer with a forced flush command guarantees that
any bus error to the Arm platform memory has been caught.
This unit structure and registers are described in Peripheral DMA Structure and
Peripheral DMA Registers.
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7.2.3.3.2.1 Peripheral DMA Structure
The peripheral DMA is made up of a 32-bit data register, two address registers, and a
controlling state-machine. The state-machine manages clock adaptation, when required.
It is shown in the following figure.
DMA interface to AP memory and peripherals
read and write address
control
data 32 32
Setup and FSM State (PS)
Source Address (PSA)
Peripheral DMA
Control
Destination Address (PDA)
Data Register (PD)
32 32 32
FUBUS
Figure 7-10. Peripheral DMA structure
7.2.3.3.2.2 Peripheral DMA Registers
According to Figure 7-10, the peripheral DMA has four registers that may be read or
written by the SDMA core:
• PD (Peripheral Data) is the DMA 32-bit data register.
• PSA (Peripheral Source Address) holds the source byte address in the Arm platform
memory map for reading data from this location. This register is automatically
modified every time the core reads a new data from PD.
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• PDA (Peripheral Destination Address) holds the destination byte address in the Arm
platform memory map for writing data to this location. This register is automatically
modified every time the core writes a new data into PD.
• PS (Peripheral Setup) contains the state of the peripheral DMA control, two
configuration fields that define the way address registers are modified after every
data access, two additional configuration fields that define the data size to access the
source and destination devices, and another field that contains the latest transfer error
status.
7.2.3.3.2.3 Peripheral DMA Data Transfers
There are three typical usages that involve the peripheral DMA, whether it is the data
transfer start-point, endpoint, or both.
Every case requires a different procedure, as described in Data Retrieval from the Arm
platform Memory or Peripheral, Storing Data into the Arm platform Memory or
Peripheral, and Transferring Data Between Two Arm platform Memory Locations-
Peripheral DMA Unit.
7.2.3.3.2.3.1 Data Retrieval from the Arm platform Memory or Peripheral
The following steps retrieve data from Arm platform memory using the peripheral DMA
unit:
• Set up the PS fields to reflect the mode and data size for the source (incremented,
decremented, or frozen address register; 8-bit, 16-bit, or 32-bit data transfers), then
initialize the source address register itself (PSA) with an address that is aligned to the
programmed data size.
• Read data from PD using the ldf PD instruction as many times as needed. If an error
occurs during the fetch from the Arm platform memory or peripheral, the DMA
control tags the error status on the data and the SDMA core SF flag is set when
reading this data from PD.
7.2.3.3.2.3.2 Storing Data into the Arm platform Memory or Peripheral
The following steps store data to Arm platform memory using the peripheral DMA unit:
• Set up the PS fields to reflect the mode and data size for the destination
(incremented, decremented, or frozen address register; 8-bit, 16-bit, or 32-bit data
transfers), then initialize the destination address register itself (PDA) with an address
that is aligned to the programmed data size.
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• Store data into PD using the stf PD instruction as many times as needed.
• When the transfer is finished and if the peripheral DMA worked in automatic flush
mode, force the flush of PD. This instruction is stalled until PD contents are
effectively sent to the Arm platform memory or peripheral, and the error status of the
transfer is available in the DF flag.
7.2.3.3.2.3.3 Transferring Data Between Two Arm platform Memory Locations-Peripheral
DMA Unit
The following steps copy data between two Arm platform memory locations using the
peripheral DMA unit:
• Set up the PS fields to reflect the modes and data size for the source and destination
addresses (all the combinations of addressing modes are possible, but both data sizes
must be identical), then initialize the source address register (PSA) and the
destination address register (PDA). Both addresses must be aligned with the
programmed data size.
• Use as many stf PD instructions with the COPY flag as needed. Every instruction
triggers a single read from the source address; a single write of the received data
immediately follows. The DMA acknowledges prior to instruction completion, which
frees the SDMA core for other tasks at no delay cost.
• Once the transfer is done, there should be a final access to the peripheral DMA to
check the error status.
7.2.3.4 SDMA Security Support
The SDMA provides support to SDMA software to block unauthorized updates to the
scripts in RAM.
SDMA supports the following Security modes:
• Open Mode: has full control to load scripts and context into SDMA RAM. This is the
default mode.
• Locked Mode: The Arm platform loads scripts and channel contexts at startup when
it is still executing known safe software. When finished, it locks the SDMA to
prevent further updates to RAM and selected registers. More details described in
Locked Mode.
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7.2.3.4.1 Locked Mode
The LOCK bit in the SDMA_LOCK register provides support for SDMA scripts to
freeze RAM contents after the initial bootload routine to prevent future unauthorized
updates to SDMA RAM.
After initial RAM contents are uploaded, Arm platform software can set the LOCK bit to
secure the RAM contents to prevent future updates by an unauthorized. After the LOCK
bit is written with a '1', the SDMA is "locked" until reset.
The LOCK bit can be read in the SDMA's internal memory map in the LOCK register
(see Section SDMA LOCK (SDMAARM_SDMA_LOCK)). SDMA scripts which load
information into RAM can check the value of the LOCK bit to determine if an upload to
RAM is allowed. If not allowed, the script can refuse to allow the request to copy data
into the RAM to continue. The exact use of the LOCK bit in SDMA scripts for security
control will be described in SDMA software documentation (see SDMA Scripts).
While SDMA is locked, attempts to write to the SDMA_LOCK, CHN0ADR,
ILLINSTADDR, and ONCE_ENB registers will be ignored. All registers remain
readable. Writes to other registers are still allowed.
Once the SDMA is locked, the LOCK bit can only be cleared by a reset. A hardware reset
will always clear the LOCK bit. A software reset initiated by writing to the RESET
register will only clear the LOCK bit if the SRESET_LOCK_CLR bit in the
SDMA_LOCK register is set. Since SDMA_LOCK register cannot be updated if SDMA
is locked, the SRESET_LOCK_CLR bit must be configured before setting the LOCK bit.
The SREST_LOCK_CLR bit will also be cleared by resets that clear the LOCK bit.
The SDMA RISC core uses the ILLINST and CHN0ADDR registers as pointers to
determine where to jump to after an illegal instruction or upon boot after a reset. The
LOCK bit prevents updates to these registers to protect against unauthorized changes to
these pointers.
While SDMA is locked, the ONCE_ENB register cannot be written to prevent the OnCE
under Arm platform control from being used to gain access to SDMA internal memory. If
Arm platform control of the OnCE is enabled before setting the LOCK bit, the Arm
platform can use the ONCE for debug purpose after LOCK is set.
7.2.3.5 OnCE and PCU Debug States
The SDMA has two different debug modes in which the OnCE performs debug
instructions.
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Refer to Figure 7-4 for an example of the PCU states in debug. The following are the two
debug states:
• When a channel is running (that is, when CCR and CCPRI are different from 0,
which can be read in the PSW register), SDMA can execute a SoftBkpt instruction
from the channel script or receive a debug request. When either happens, the SDMA
enters its "Classical" Debug state, which is described in OnCE and Real-Time
Debug.
• When a channel is not running, the SDMA can be in Sleep state or in Sleep after
Reset state. If a debug request is sent to the core, it enters its Debug in Sleep state.
This debug mode works similarly to the "Classical" Debug state, except it returns to
the original state (Sleep or Sleep after Reset) when the debug mode is left via the
exec_core instruction of the OnCE. From this Debug in Sleep state, the SDMA can
execute a program whereas no channel is running. If a new debug request is sent to
the core or if a SoftBkpt is executed, it comes back to this Debug in Sleep state.
The OnCE is provided with several instructions that can be executed when the core is in
either debug state. The following table summarizes the behavior of these OnCE debug
instructions. There exists other secondary OnCE instructions that are described in OnCE
and Real-Time Debug.
Table 7-12. SDMA in Debug Mode
Instruction Debug Debug in Sleep
exec_once exec_once <instruction> exec_once <instruction>
SDMA executes the <instruction> and returns to the SDMA executes the <instruction> and returns to the
Debug state. The Program Counter (PC) is not Debug in Sleep state. The Program Counter (PC) is
incremented. This command must not be used with an not incremented. This command must not be used
instruction that modifies the PC value. with an instruction that modifies the PC value.
run_core run_core <instruction> run_core <instruction>
SDMA executes the <instruction>, leaves the Debug SDMA executes the <instruction> and returns to its
state and continues executing the channel script from Sleep or Sleep after Reset initial state. This command
the position where it stopped. This command must not must not be used with an instruction that modifies the
be used with an instruction that modifies the PC PC value.
value.
exec_core exec_core <instruction> exec_core <instruction>
It is similar to run_core except it requires an If the previous state was Sleep after Reset, the SDMA
instruction that changes the PC value (jump, returns to this state, and Chn0Addr value overrides
branch...): the SDMA jumps to the new PC value, the PC value.
leaves the Debug state and starts executing
Otherwise, the SDMA jumps to the new PC value and
instructions from this new PC value.
starts executing instructions from this new PC.
NOTE
The feature exec_core in Debug in Sleep after Sleep after Reset
was added for the Channel boot (channel 0) to allow the
debugger to return to Sleep after Reset state with a new PC
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value. The SDMA will be ready to boot at the Chn0Addr
address.
7.2.3.6 SDMA Clocks and Low Power Modes
The SDMA receives several root clocks from the SoC clock controller block and
performs adaptive clock gating to optimize its power consumption. From a user
standpoint, clock gating and power mode selection are fully automatized inside the
SDMA.
Root clock control is available from the SoC clock controller block.
There are numerous clock sources that are used in the SDMA. They belong to one of two
possible clock domains listed in the following table, and have frequency constraints
within each domain. Clocks are considered asynchronous between domains.
Within the Arm platform/SDMA clock domain, all clocks must come from the same
DPLL. The Arm platform DMA interfaces (peripheral DMA and burst DMA) receive
their clock from the Arm platform DMA clock source whose frequency can be once or
twice the frequency of the SDMA core clock. The DMA interfaces are designed to work
at the Arm platform DMA frequency, but the SDMA core is physically limited to a
maximum 104 MHz frequency. Since this is lower than the maximum Arm platform
DMA frequency, the SDMA core clock is tied to the Arm platform peripheral clock
frequency.
The Arm platform Peripheral Bus Clock source must be an exact sub-frequency of the
SDMA Core clock source (any integer value greater or equal to 1).
Table 7-13. Clocking Scheme
Clock Domain Source Clock Comments
Arm platform SDMA core Source clock for the core and all its operations; this clock is thus used by most
of the SDMA sub-blocks.
(SDMA main core)
Arm platform DMA DMA interface for the peripheral DMA and the burst DMA. It is balanced with
the main clock source, and its frequency is either once or twice the main clock
frequency.
Arm platform peripheral Connection to the Arm platform peripheral bus. It is a sub-frequency of the
main clock frequency.
JTAG TCK Clock for JTAG access, limited to maximum of 1/8 of the SDMA core clock
frequency.
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The JTAG clock is sampled by the SDMA main clock to determine its rising edge. This
simplifies design and clock management, but it also adds a ratio constraint between those
two clocks. It is guaranteed the JTAG interface works properly when the frequency of
TCK is lower than 1/8th of the frequency of the SDMA main clock (which is about 8
MHz when the SDMA core clock frequency is 66 MHz).
7.2.3.6.1 Clock Gating and Low Power Modes
The SDMA automatically performs power saving without requiring user involvement. It
implements two levels of automatic clock gating.
7.2.3.6.1.1 Coarse Clock Gating
Every sub-block clock comes from one of the five available sources, and is gated with the
sub-block specific enabling condition.
The following table displays the sub-block clocks and their source. It also indicates the
relationships that may exist between different sub-blocks clock enables.
Table 7-14. Sub-blocks Clocks
Sub-block Source Clocks Enabling Condition and Comments Related Enabling
Conditions
Core SDMA Main The core sub-block clock is running when the core is not in one of None
Core its sleep states (Sleep or Sleep after Reset) or there is a pending
channel. Typically, the core sub-block clock is stopped once all the
channels are processed and the core enters its sleep state. A new
pending channel awakes the core sub-block clock.
Memories SDMA Main The clock activation only occurs during a core access. Disabled when
Core Core sub-block
clock is disabled or
no memory access
in progress
Scheduler SDMA Main Its clock only runs when scheduling is needed: for example, when None
Core there are pending channels, upon reception of a DMA request, and
anytime the Arm platform modifies the channel running conditions.
Arm platform SDMA Main The Arm platform peripheral clock is solely used to determine the None
Control Core frequency ratio with the SDMA main clock. The control registers'
clock is based on SDMA main clock; it is active when the Arm
&
platform or the SDMA modifies the contents of one of these
Arm platform registers.
peripheral
Burst DMA SDMA Main The burst DMA has two clocks: The first clock is derived from the Disabled when
Core SDMA main core clock and drives registers that are connected to Core sub-block
the FUBUS. The second clock is derived from the Arm platform clock is disabled
&
DMA clock and drives registers that are connected to the Arm
Arm platform platform DMA bus outside the SDMA. Both clocks are enabled
DMA
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Table 7-14. Sub-blocks Clocks (continued)
Sub-block Source Clocks Enabling Condition and Comments Related Enabling
Conditions
during active phases of data transfers (for example, these clocks
are turned off when the burst DMA is not used by the running
channel script).
Peripheral DMA SDMA Main The peripheral DMA has two clocks: The first clock is derived from Disabled when
Core SDMA main clock and drives registers that are connected to the Core sub-block
FUBUS. The second clock is derived from the Arm platform DMA clock is disabled
&
clock and drives registers that are connected to the Arm platform
Arm platform DMA bus outside the SDMA. Both clocks are enabled during active
DMA phases of data transfers (for example, these clocks are turned off
when the peripheral DMA is not used by the running channel
script).
OnCE SDMA Main The OnCE clock is derived from main source clock. It is disabled by When enabled, all
Core default. In order to use the OnCE, its clock must be explicitly turned other clocks are
on, either by enabling the OnCE access from the Arm platform systematically on
peripheral bus (register ONCE_ENB), or by driving the (clock gating is off)
clk_gating_off input pin high. This is a SDMA input whose driver
depends on the SoC implementation (typically a JTAG controller).
The OnCE also receives the TCK input, which is the JTAG clock. It
does not use it as a functional clock; the TCK input is sampled
instead. Refer to Synchronization Implementation.
7.2.3.6.1.2 Refined Clock Gating
The SDMA implements a second level of clock gating on a register-per-register basis.
Unlike the first level that covers all the SDMA flip-flops, except the synchronizers (only
five flip-flops are always running), the second level is only available for eligible
registers, which amounts to about 90% of the SDMA flip-flops.
These gated registers are only clocked when the hardware logic detects a new data
loading. This additional gating further reduces dynamic power consumption.
7.2.3.6.1.3 Low Power Modes and User Control
Power savings are automatically managed by the SDMA hardware without any user
involvement; however, one can distinguish three different power modes: SLEEP, RUN,
and DEBUG.
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The following table describes these modes, and shows how to switch from one mode to
another.
Table 7-15. Power Modes
Power Sub-blocks Comments
Mode
Core Mem Sche Arm Burs Perip OnC
ories duler platf t heral E
orm DMA DMA
Cont
rol
SLEEP off1 off wait2 wait off off off Set when the PCU state is either Sleep or Sleep after Reset
and the SDMA is not in DEBUG mode. This is the default
mode after reset.
RUN on3 wait wait wait wait wait off Set for the other PCU states that are reachable out of debug:
Program, Data, Change of Flow, Error in Loop, Debug,
Functional Unit, Save, or Restore.
DEBUG on on on on on on on Set regardless of the PCU state when clock gating is turned
off to use the OnCE features (either clk_gating_off pin high
or ONCE_ENB[0] set).
1. off: no clock
2. wait: only clocked when accessed or stimulated
3. on: clock is always running
It is possible to control the SDMA power mode. The procedures to force the SDMA into
either mode are described in SLEEP Mode.
7.2.3.6.1.3.1 SLEEP Mode
This is the default mode after reset; therefore, resetting the SDMA forces this mode.
However, the common procedure is as follows:
• Ensure the clk_gating_off pin is low and ONCE_ENB[0] is cleared.
• Disable all channels (via the STOP_STAT control register, and the HO, DO, EO if
necessary).
• Wait for the active channels to complete or force a reschedule via the reschedule bit
in the RESET register.
• The SDMA is in SLEEP mode making it possible to completely shut off its clock
from the chip level clock controller using the procedure described in Stop Mode
Response.
7.2.3.6.1.3.2 RUN Mode
This is the default mode when a channel is running:
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• Ensure the clk_gating_off pin is low and ONCE_ENB[0] is cleared.
• Activate at least one channel (via the HSTART control registers, a DMA request,
and/or the HO, DO, EO register bits).
7.2.3.6.1.3.3 DEBUG Mode
The DEBUG mode must be set when one needs to use the debugging facilities of the
SDMA.
• Ensure the SDMA clocks are running from the CCM.
• Set the clk_gating_off pin high or use the SDMA to set ONCE_ENB[0].
7.2.3.6.1.4 Stop Mode Response
The SDMA receives a stop request from the chip level clock controller. This request may
be asserted when the chip enters the stop low power mode.
If the SDMA is running when the request is received, then the SDMA will complete all
pending channels before returning to the SLEEP state. The SDMA sends an
acknowledgement to the clock controller when the SLEEP state is entered indicating that
the SDMAs clocks can be turned off.
7.2.3.6.2 Reset
After reset (either received from the reset block or a software reset required by the Arm
platform), the SDMA is in IDLE mode. It will start its boot code located at address 0
once a channel is activated.
Activating a channel can be done by the Arm platform after programming a positive
priority and setting the channel bit in the EVTPEND register.
There will not be a context RESTORE for the first channel (bootload channel) called
after a reset because the context data in RAM has not been initialized. Static context
mode should be used for the first channel called after reset to ensure that the all context
RAM for that channel is initialized. Subsequent calls to the same channel or different
channels may use any of the dynamic context modes
7.2.3.7 Software Interface
Appendix A fully describes the SDMA Application Programming Interface (API).
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7.2.3.8 Initialization Information
This section discusses the following:
• Hardware Reset
• Channel Script Execution
• Initialization and Script Execution Setup Sequence
7.2.3.8.1 Hardware Reset
After reset, the program RAM, context RAM, data RAM, and RAM containing the
channel enable registers (CHNENBLn) have unpredictable contents.
The active register set is assigned to channel 0 and the PC is initialized to all zeros.
However, since the channel enable register is all zeros, there are no active channels and
the SDMA is halted waiting for the boot channel to start.
The Arm platform will have to setup the SDMA in order to boot it. The CONFIG register
must be initialized to determine the DMA/core clock ratio (1 or 2). Channel Enable
Registers must also be initialized.
To start up the SDMA, the Arm platform first creates some channel control blocks (CCB)
and buffer descriptors (BD) in Arm platform memory for the boot channel (channel 0)
and then initializes the channel 0 pointer register (SDMA_MC0PTR) to the address of the
first control block. Data Structures for Boot Code and Channel Scripts provides an
overview of the data structure for the CCB and BD's. The SDMA_HSTART,
SDMA_HOSTOVR and SDMA_EVTOVR registers are then configured according to
Runnable Channels Evaluation to allow channel 0 to run.
Upon being enabled, the SDMA begins executing the script located at the address
indicated by the Channel 0 Boot Address register (SDMA_CHN0ADDR) in the program
memory. The reset value of SDMA_CHN0ADDR points to the default bootload script in
ROM. This ROM script will read the channel 0 pointer register (SDMA_MC0PTR) to
determine the location of the Channel Control Block (SDMA_CCB) in Arm platform
memory. The script will then begin fetching by DMA the first channel control block
which contains a pointer to the location channel 0 Buffer Descriptor chain which is also
fetched via DMA. If the buffer descriptor contains a valid command, the script interprets
the command in each buffer descriptor and proceeds to implement the command and
move on to the next buffer descriptor control block. The buffer descriptor commands for
channel zero are typically set up to load SDMA's program RAM, Data RAM, and initial
values for the channel contexts. Some channel scripts expect particular parameters to be
passed
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There are two ways to make the SDMA boot on a user-defined script. The OnCE (either
via its JTAG interface or its Arm platform Control interface) can be used to download
any code in the SDMA RAM and force the SDMA to boot on that code. Also, the
SDMA_CHN0ADDR register in the Arm platform programming model can be modified
to point to user code in RAM which would need to either have been loaded via the ONCE
or default bootload routine (ex before a S/W reset).
7.2.3.8.2 Channel Script Execution
The execution of an SDMA script depends on both the instructions that make up the
script, the data context upon which it operates, and commands or parameters allowed to
the buffer. All these items must be initialized before the script is allowed to execute.
Each of the 32 channels has a separate context, but may share scripts and locations in
data RAM.
Channels are initialized by the Arm platform by using channel 0 to download any
required scripts and data values and the channels initial context. The context contains all
the initial values of the SDMA core registers. This includes the Program Counter (PC)
which is set to the start of the desired script in SDMA program memory.
The Arm platform selects which trigger conditions that must occur for the channel to start
by configuring the SDMA_CHNENBL, SDMA_HOSTOVR and SDMA_EVTOVR
registers. The trigger events include Arm platform setting HE (SDMA_HSTART) or a
hardware DMA request asserts an event input to SDMA. The channel can become active
according to its priority compared with other runnable channels when the selected
trigger(s) cause the condition described in Runnable Channels Evaluation to evaluate as
true.
The specific parameters to be passed to each script in the buffer descriptor or context are
documented in the software documentation for each script. Please refer to SDMA Scripts
for complete script documentation. Buffer Descriptor Format provides an overview of the
buffer descriptor format.
7.2.3.8.3 Initialization and Script Execution Setup Sequence
To summarize, the following steps are minimally required to setup SDMA and run
channel scripts.
• Perform Hardware Reset. The program RAM, context RAM, data RAM and
SDMA_CHNENBLn registers have unpredictable contents after this reset.
• Initialize SDMA_CHNENBLn registers to map DMA request events to desired
channels.
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• Configure SDMA_CHNPRIn registers to select priority for runnable channels. A
non-zero priority is required for the channel to run.
• Configure the SDMA_CONFIG register to select DMA to SDMA core clock ratio .
• Set up channel control blocks and buffer descriptors in Arm platform to specify the
loading of SDMA program RAM and channel contexts for each SDMA channel to be
used. Reference Data Structures for Boot Code and Channel Scripts.
• Configure SDMA_MC0PTR register with base address of Arm platform Channel
Control Block base address.
• Initialize SDMA_CHNENBLn registers to map DMA request events to associated
channel. Reference Mapping DMA Requests to Pending Channels.
• Configure SDMA_CHNPRIn registers to set priority for each channel to be run.
• For each channel to be run, configure SDMA_HOSTOVR (HO) and
SDMA_EVTOVR (EO) registers to select which events (hardware and/or software
trigger events) must occur for the channel to be runnable. Reference Runnable
Channels Evaluation.
• Set bit 0 of the SDMA_HSTART register to set HE[0] and allow Channel 0 to run
(assumes EO[0] andDO[0] were both set in previous step). This will cause SDMA to
load the program RAM and channel contexts configured previously.
• Wait for Channel 0 to finish running. This is indicated by HI[0]=1 in the
SDMA_SDMA_INTR register, or by optional interrupt to the Arm platform.
• Set the LOCK bit in the SDMA_SDMA_LOCK register to prevent un-authorized
uploads of data to SDMA RAM.
• Additional channel scripts can now be run by enabling the selected software or
hardware trigger event according to Runnable Channels Evaluation.
7.2.3.9 SDMA Programming Model
This section describes the programming model for the SDMA RISC engine, including its
processor, memory, and internal control registers.
All addresses are related to the internal SDMA memory map, which is completely
different from the Arm platform memory maps. The Arm platform processor has no
access to any hardware resource described, except when those resources are described in
Arm Platform Memory Map and Control Register Summary. .
7.2.3.9.1 State and Registers Per Channel
The SDMA can be seen as a set of 32 identical devices that are able to perform one data
transfer channel each. Only one channel can work at a time, but every channel state is
available at any time.
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This chapter lists the components of every channel state.
7.2.3.9.2 General Purpose Registers
Each channel has eight general purpose registers of 32 bits for use by scripts. General
register 0 has a dedicated function for the loop instruction, but otherwise can be used for
any purpose.
7.2.3.9.3 Functional Unit State
Each channel context has some state that is part of the functional units.
The specific allocation of this state is part of the functional unit definition that is
described in Burst DMA Unit Programming, Peripheral DMA Unit Programming .
This state must be saved/restored on context switches.
7.2.3.9.3.1 Program Counter Register (PC)
The PC is 14 bits. Since instructions are 16 bits in width and all memory in the SDMA is
32 bits in width, the low order bit of the PC selects which half of the 32-bit word contains
the current instruction.
A low order bit of zero selects the most significant half of the word.1
7.2.3.9.3.2 Flags
Each channel has the following four flags:
• The T bit reflects the status of some arithmetic and test instructions. It is set when the
result of an addition or a subtraction is zero and cleared otherwise. It is also the copy
of the tested bits. Finally, it can also be set when the loop counter (GReg0) reaches
zero. When the last instruction of the hardware loop is an operation that can modify
the T flag, its effect on T is discarded and replaced by the GReg0 status.
• Two additional bits, SF and DF, are used to indicate error conditions resulting from
loading data sources and storing to destinations, respectively. Access errors set these
bits, and successful transactions clear them. They can also be cleared by specific
instructions (CLRF and loop). The source fault (SF) is updated by the loads LD and
LDF; the destination fault (DF) is updated by the stores ST and STF.
1. For example, big-Endian.
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• Access errors are caused by several conditions including writing to the ROM, writing
to a read-only memory mapped register, accessing an unmapped address, or any
transfer error received by a peripheral when it is accessed.
The SF and DF flags have a major impact on the behavior of the hardware loop: If
SF or DF is set when starting a hardware loop and it is not masked by the loop
instruction, the loop body will not be executed. Inside the loop body, if a load or
store sets the corresponding SF or DF flag, the loop exits immediately. Testing the
status of the T flag at the end of the loop (as well as testing both SF and DF) tells if
the loop exited abnormally as any anticipated exit prevents GReg0 from reaching the
zero value and thus setting the T flag. This is also valid if the fault occurs at the last
instruction of the last loop.
• The last flag is the loop mode flag, LM, which is composed of two bits. The most
significant bit indicates when the processor is currently operating in loop mode. It is
set by the loop instruction and is cleared after execution of the last instruction of the
last loop. The least significant bit is set when the program counter points to the last
instruction of a loop on the last path. It is used for a channel that is restored with this
configuration to know that the next program counter is EPC. As with the dynamic
context switch Greg0, which indicates when the program must get out of the loop, it
can be restored only on the last instruction of the loop. This, however, is too late to
fetch the next instruction after the loop.
7.2.3.9.3.3 Return Program Counter (RPC)
The RPC is 14 bits. It is set by the jump to the subroutine instructions and used by the
return from the subroutine instructions.
Instructions are available to transfer its contents to and from a general register.
7.2.3.9.3.4 Loop Mode Start Program Counter (SPC)
The SPC is 14 bits. It is set by the loop instruction to the location immediately following
it.
7.2.3.9.3.5 Loop Mode End Program Counter (EPC)
The EPC is 14 bits. It is set by the loop instruction to the location of the next instruction
after the loop.
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7.2.3.9.4 Context Switching-Programming
Each channel has a separate context consisting of the eight general purpose registers and
additional registers representing the state of the functional units.
The active registers and functional units contain the context of the active channel. The
context of inactive channels is stored in SDMA RAM, which is part of the SDMA
address space.
In a function of the selected context switching mode (Context Switching), modified
registers by the program can be saved in the channel RAM space while the program is
going on. In every cycle, a write access to the RAM is possible.
On a done or yield(ge) instruction, SDMA goes into "real" context switching. In one of
the dynamic modes, modified registers not previously saved, as well as the PC-Loop
registers, are stored into the context area of the channel that will be closed. The new PC-
Loop registers are loaded from the context area of the new channel. All other registers are
restored while the program is executed, giving priority to registers used by the decoded
instruction. Therefore, in the best case, only the PC and Loop registers should be saved
and restored during this context-switching phase, which only requires five SDMA cycles.
In static mode, the context switch stores all registers in the old channel RAM space, and
restores all registers from the new channel RAM space. It requires 26 SDMA cycles.
The address of the context memory for channel i is CONTEXT_BASE + 24*i or
CONTEXT_BASE + 32*i where CONTEXT_BASE equals 0x0800. The table below
presents the layout of a channel context in memory:
Table 7-16. Layout of a Channel Context in Memory for SDMA
OFFSET 31 30 29-16 15 14 13-0
0 SF - RPC T - PC
1 LM EPC DF - SPC
2 GR0
3 GR1
4 GR2
5 GR3
6 GR4
7 GR5
8 GR6
9 GR7
10 MDA (burst DMA)
11 MSA (burst DMA)
12 MS (burst DMA)
13 MD (burst DMA)
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Table 7-16. Layout of a Channel Context in Memory for SDMA (continued)
14 PDA (peripheral DMA)
15 PSA (peripheral DMA)
16 PS (peripheral DMA)
17 PD (peripheral DMA)
18
19
20 Reserved1
21 Reserved1
22 Reserved1
23 Reserved1
24 Scratch RAM (optional)
25 Scratch RAM (optional)
26 Scratch RAM (optional)
27 Scratch RAM (optional)
28 Scratch RAM (optional)
29 Scratch RAM (optional)
30 Scratch RAM (optional)
31 Scratch RAM (optional)
7.2.3.9.5 Address Space
The SDMA has four internal buses which are listed here.
• The Instruction bus reads instructions from the memory. Its address map is described
in Instruction Memory Map.
• The Data bus (DMBUS) accesses the same memories as those visible on the
Instruction bus, some memory-mapped registers (scheduler status and OnCE
registers), and up to 14 peripherals. Its address map is described in Data Memory
Map.
• The Functional Units bus (FUBUS) accesses the , Burst DMA, Peripheral DMA .
The addressing mechanism is further detailed in Functional Units Programming
Model.
• The Context Switch bus reads/writes registers into context-switch RAM space. It is a
64-bit bus dedicated for accessing this RAM space for updating the context of the
running channel. While the program is going on, this bus has the lowest priority
compared to the Instruction and Data buses, except for restoring a register needed for
the decoded instruction to be executed. On the save part of a context switch (when
the PCU is in its slave state), this is the only one used. On the restore part, the
Instruction bus has the priority to read the next instruction at the restored PC and
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otherwise the Context Switch bus is used. It is not possible to control the actual data
transfers that occur on this bus.
7.2.3.9.5.1 Instruction Memory Map
The instruction memory map is based on a 14-bit address bus and a 16-bit data
(instruction) bus.
Instructions are fetched from either program ROM or program RAM. An SDMA script is
able to change the contents of the program RAM, which is also visible from the data bus.
The first two instruction locations (at 0 and 1) are special. Location 0 is where the PC is
set on reset. Location 1 is where the PC is set upon the execution of an illegal instruction.
It is expected that both of these locations will contain a jmp to handle routines.
Table 7-17. SDMA Instruction Memory Space
Device SDMA Base Address Label Block WS Description
Address (Hex) Name
ROM 0x0000 ↓ SDMA_IBUS_ROM_ADDR - 0 4 Kbyte internal ROM with
0x07FF boot code and standard
routines.
RAM 0x1000 ↓ SDMA_IBUS_RAM_ADDR - 0 8 Kbyte internal RAM with
0x1FFF channels context and user
data/routines.
7.2.3.9.5.2 Data Memory Map
All of the data accessible to SDMA scripts make up the data memory space of the
SDMA.
This address space has several components:
• ROM (also visible on the Instruction bus)
• RAM (also visible on the Instruction bus)
• Shared Peripherals Registers
• SDMA Internal Registers (scheduler, OnCE, and registers that are also accessible by
the Arm platform)
SDMA scripts can read and write to the context RAM, data RAM, shared peripheral
registers, and internal registers.
The address range is 16 bits and the data width is 32 bits. When accessing peripheral
registers (USB and so on), the data width may be different. The exact address map for the
peripherals depends on the project (as presented in each respective chapter).
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Data access is performed with ld and st instructions that take the address from a general
purpose register in the core (GRegn). The mapping between the general purpose register
contents and the address bus is given in the following table:
Table 7-18. GRegn to DMBUS Address Mapping
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sz 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
address
Grayed bits are simply discarded but they must be cleared to ensure forward-script
compatibility.
• sz (bit 31) indicates the peripheral data width: 0 is used for a 32-bit peripheral and 1
is used for a 16-bit peripheral.
• address (bits 15 down to 0) is the address of the accessed resource (internal memory,
internal register, or shared peripheral).
Table 7-19. SDMA Data Memory Space
Device SDMA Address (Hex) Size Description
ROM 0x0000 → 0x03FF 4 Kbyte 4 Kbyte internal ROM with boot code and standard routines
Reserved 0x0400 → 0x07FF 4 Kbyte 4 Kbyte Reserved
RAM 0x0800 → 0x0FFF 8 Kbyte 8 Kbyte internal RAM with channels contexts and user data/routines
per1 0x1000 → 0x1FFF 16 Kbyte peripheral 1 memory space (4 Kbyte peripheral's address space)
per2 0x2000 → 0x2FFF 16 Kbyte peripheral 2 memory space (4 Kbyte peripheral's address space)
per3 0x3000 → 0x3FFF 16 Kbyte peripheral 3 memory space (4 Kbyte peripheral's address space)
per4 0x4000 → 0x4FFF 16 Kbyte peripheral 4 memory space (4 Kbyte peripheral's address space)
per5 0x5000 → 0x5FFF 16 Kbyte peripheral 5 memory space (4 Kbyte peripheral's address space)
per6 0x6000 → 0x6FFF 16 Kbyte peripheral 6 memory space (4 Kbyte peripheral's address space)
Registers 0x7000 → 0x7FFF 16 Kbyte Memory mapped registers
per7 0x8000 → 0x8FFF 16 Kbyte peripheral 7 memory space (4 Kbyte peripheral's address space)
per8 0x9000 → 0x9FFF 16 Kbyte peripheral 8 memory space (4 Kbyte peripheral's address space)
per9 0xA000 → 0xAFFF 16 Kbyte peripheral 9 memory space (4 Kbyte peripheral's address space)
per10 0xB000 → 0xBFFF 16 Kbyte peripheral 10 memory space (4 Kbyte peripheral's address space)
per11 0xC000 → 0xCFFF 16 Kbyte peripheral 11 memory space (4 Kbyte peripheral's address space)
per12 0xD000 → 0xDFFF 16 Kbyte peripheral 12 memory space (4 Kbyte peripheral's address space)
per13 0xE000 → 0xEFFF 16 Kbyte peripheral 13 memory space (4 Kbyte peripheral's address space)
per14 0xF000 → 0xFFFF 16 Kbyte peripheral 14 memory space (4 Kbyte peripheral's address space)
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7.2.3.10 SDMA Initialization
Appendix A describes the setup of the SDMA . This section provides a quick description
of several initialization procedures.
NOTE
There may be differences with the actual implementation in the
API.
7.2.3.10.1 Hardware Reset-SDMA
After reset, the RAM that holds contexts, data, scripts, and the DMA request-channels
matrix has unpredictable content.
The core registers are all reset to 0, including the PC; the PCU state is Sleep after Reset.
No channel can be activated because all of the priorities are also reset to 0.
7.2.3.10.2 Standard Boot Sequence
The following is the standard boot sequence:
1. Initialize the CONFIG register-detailed in Configuration Register
(SDMAARM_CONFIG)-to determine the Arm platform DMA/core clock ratio (1 or
2)
2. Initialize the DMA request-channels matrix (seeChannel Enable RAM
(SDMAARM_CHNENBLn) ).
3. Program the channel control registers-Channel Event Override
(SDMAARM_EVTOVR), Channel BP Override (SDMAARM_DSPOVR), Channel
BP Override (SDMA_HOSTOVR), and Channel Event Pending
(SDMAARM_EVTPEND)-according to the channel allocation.
4. Perform any necessary setup as required by the standard boot script in ROM (this is
described in Appendix A).
5. Trigger channel 0 with the Channel Start (SDMAARM_HSTART) register, which
starts the execution of the ROM script starting at address 0. This boot downloads
channel scripts and contexts in RAM.
7.2.3.10.3 User-Defined Boot Sequence
The following is a user-defined boot sequence:
1. Initialize the Configuration Register (SDMAARM_CONFIG)Channel Enable RAM
(SDMAARM_CHNENBLn), Channel Event Override (SDMAARM_EVTOVR),
Channel BP Override (SDMAARM_DSPOVR), Channel Arm platform Override
(SDMAARM_HOSTOVR), and Channel Event Pending (SDMAARM_EVTPEND).
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2. Use the OnCE (either via its JTAG interface or its Arm platform control registers) to
download any code in the SDMA RAM. Accessing the Memory describes how to
write data to the RAM via the OnCE.
3. Use the OnCE instructions to make the PC default value point to the new boot script
start address, or rely on the ROM startup script, which first jumps to the address in
Channel 0 Boot Address (SDMAARM_CHN0ADDR). (This register default address
points to the standard boot script.)
7.2.3.10.4 Script Loading and Context Initialization
The execution of an SDMA script depends on both the instructions that make up the
script and the data context upon which it operates. Both must be initialized before the
script is allowed to execute.
Each of the 32 channels has a separate data context, but may share scripts and locations
in the data RAM.
The Arm platform manages the space in program RAM and data RAM. It also manages
the assignment of SDMA channels to the device drivers that need them. Channels are
initialized by the Arm platform via the channel 0 boot script. The boot channel
downloads any required scripts with their data and the channels' initial contexts. Every
context contains all the initial values of the registers, including the PC. Then the Arm
platform can enable any channel that becomes active and begins fetching and executing
instructions from its script.
7.2.3.11 Instruction Description
The following sections introduce the instruction of the SDMA.
Instruction set details are available in Instruction Set.
7.2.3.11.1 Scheduling Instructions
The following are scheduling instructions:
• done-The instruction causes certain scheduling or interrupt bits to be set or cleared,
which may cause a change in the schedule-ability of the running channel. Then the
instruction causes the SDMA to evaluate the current scheduling priorities and to
choose the highest priority ready channel. If this channel is not the current channel, a
context switch will take place. If there are no runnable channels, the SDMA will
enter the stopped mode. The done 5 has a special usage reserved for debug, as
explained in Debug Instructions.
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• yield-These instructions are special cases of the done instruction. They do not modify
the scheduling bits, but allow the highest pending channel (if it exists) to preempt the
current channel if the pending channel priority is strictly greater than the current
channel priority.
• yieldge-These instructions are special cases of the done instruction. They do not
modify the scheduling bits, but allow the highest pending channel (if it exists) to
preempt the current channel if the pending channel priority is strictly greater or equal
to the current channel priority.
• notify-The notify instruction affects the scheduling bits, but does not cause
rescheduling.
7.2.3.11.2 Conditional Branch Instructions
The conditional branch instructions of an 8-bit displacement, which is sign-extended and
added to the current PC (which points to the next instruction) if the condition is satisfied.
Otherwise, control passes to the next sequential instruction.
• BF-Branch if False. The branch is taken if the T bit in the processor status is zero
(false).
• BT-Branch if True. The branch is taken if the T bit in the processor status is one
(true).
• BSF-Branch if Source Fault. The branch is taken if the SF bit in the processor status
is one.
• BDF-Branch if Destination Fault. The branch is taken if the DF bit in the processor
status is one.
7.2.3.11.3 Unconditional Jump Instructions
There are two varieties of unconditional control transfers: an absolute transfer and a
through-register transfer.
Absolute transfers have a 14-bit address field that replaces the current PC.
• JMP-Jump. Causes the processor to jump to an absolute address encoded in the
instruction itself.
• JSR-Jump to Subroutine. Causes the processor to jump to a subroutine, the address of
which is encoded in the instruction itself.
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• JMPR-Jump through Register. Causes the processor to jump to an absolute address
contained in a General register. This instruction is meant to be used when more than
one level of subroutines are required.
• JSRR-Jump to Subroutine through Register. Causes the processor to jump to a
subroutine, the address of which is contained in a General register. This instruction is
meant to be used when more than one level of subroutines are required.
7.2.3.11.4 Subroutine Return Instructions
The following are subroutine return instructions:
• RET-Return from Subroutine. The RET restores the contents of RPC to PC.
• LDRPC-Load from RPC to Register. THe LDRPC instruction is meant to be used
when more than one level of subroutines are required. It stores the contents of RPC
in any General register.
7.2.3.11.5 Loop Instruction
The following is a loop instruction:
LOOP-Enters Loop Mode. Before entering loop mode, the loop instruction can optionally
clear the fault flags (SF and/or DF) based on a 2-bit field in the instruction. This feature is
linked to the fact that setting SF or DF in loop mode will cause an immediate exit of the
loop.
7.2.3.11.6 Miscellaneous Instructions
The following are miscellaneous instructions:
• CLRF-Clear Fault Flags. This instruction clears any combination of SF and DF.
• MOV r,s-This moves data from GReg[s] to GReg[r].
• LDI r,immediate-This loads GReg[r] with a zero-extended immediate value.
7.2.3.11.7 Logic Instructions
The following are logic instructions:
• XORr,s-This performs an exclusive or between GReg[r] and GReg[s], and stores the
result in GReg[r].
• XORIr,immediate-This performs an exclusive or between GReg[r] and a zero-
extended immediate value, and stores the result in GReg[r].
• ORr,s-This performs an or between GReg[r] and GReg[s], and stores the result in
GReg[r].
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• ORIr,immediate-This performs an or between GReg[r] and a zero-extended
immediate value and, stores the result in GReg[r].
• ANDNr,s-This performs an and between GReg[r] and the negated GReg[s], and
stores the result in GReg[r].
• ANDNIr,immediate-This performs an and between GReg[r] and the negated zero-
extended immediate value, and stores the result in GReg[r].
• ANDr,s-This performs an and between GReg[r] and GReg[s], and stores the result in
GReg[r].
• ANDIr,immediate-This performs an and between GReg[r] and a zero-extended
immediate value, and stores the result in GReg[r].
7.2.3.11.8 Arithmetic Instructions
Arithmetic instructions modify the T bit in the processor status according to the result of
the operation. The T bit is set if the result is zero, otherwise it is cleared.
• ADD r,s-This performs the addition of GReg[r] and GReg[s], and stores the result in
GReg[r].
• ADDI r,immediate-This performs the addition of GReg[r] and a zero-extended
immediate value, and stores the result in GReg[r].
• SUB r,s-This performs the subtraction of GReg[s] from GReg[r], and stores the result
in GReg[r].
• SUBIr,immediate-This performs the subtraction of a zero-extended immediate value
from GReg[r], and stores the result in GReg[r].
7.2.3.11.9 Compare Instructions
Compare instructions modify the T bit in the processor status according to the result of
the operation. The T bit is set if the comparison is true, otherwise it is cleared.
NOTE
Only one version of the immediate form is implemented. Non-
equality comparisons to immediate values will require two
instructions.
• CMPEQ r,s-This sets T when registers GReg[r] and GReg[s] are equal.
• CMPEQIr,immediate-This sets T when register GReg[r] and the zero-extended
immediate value are equal.
• CMPLTr,s-This sets T when register GReg[r] is less than and not equal to GReg[s].
The comparison is signed.
• CMPHS r,s-This sets T when register GReg[r] is greater than or equal to GReg[s].
The comparison is signed.
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7.2.3.11.10 Test Instructions
Test instructions modify the T bit in the processor status according to the result of the
operation. The T bit is set if any bit in the result is one, otherwise it is cleared.
• TSTr,s-This performs an and between GReg[r] and GReg[s], and sets T if the result
is not zero.
• TSTIr,immediate-This performs an and between GReg[r] and a zero-extended
immediate value, and sets T if the result is not zero.
7.2.3.11.11 Byte Permutation Instructions
These instructions shuffle the bytes in a register. For the purpose of describing these
instructions, have the bytes in a register be numbered from the most significant as b3, b2,
b1, b0.
• RORBr-The rotate right byte. The result is b0, b3, b2, b1.
• REVBr-The reverse bytes in word. The result is b0, b1, b2, b3.
• REVBLOr-The reverse, two low-order bytes. The result is b3, b2, b0, b1.
7.2.3.11.12 Bit Shift Instructions
The following are bit shift instructions:
• ROR1r-The rotate right 1 bit. This instruction does a circular right shift of 1 bit.
• LSR1r-The logical shift right 1 bit. This instruction shifts all bits to the right by 1.
The high order bit is replaced by a 0.
• ASR1r-The arithmetic shift right 1 bit. This instruction shifts all bits to the right by 1.
The high order bit is replaced by itself.
• LSL1r-The logical shift left 1 bit. This instruction shifts all bits to the left by 1. The
low order bit is replaced by zero.
7.2.3.11.13 Bit Manipulation Instructions
• BCLRIr,n-The bit clear is immediate; clears bit number i in register r.
• BSETIr,n-The bit set is immediate; sets bit number i in register r.
• BTSTIr,n-The bit test is immediate; tests bit number i in register r (T becomes equal
to the selected register bit).
7.2.3.11.14 SDMA Memory Access Instructions
All memory accesses are 32 bits.
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Any memory location that is implemented with less than 32 bits (for example, peripheral
registers) causes unimplemented bits to be read as 0s.
All memory accesses will cause either the SF or DF flags in the processor status to be set
if they cause a fault.
What constitutes a fault, especially when accessing peripheral registers, is a property of
the memory location.
• LDr,(b,d)-The load instruction creates an address by adding the displacement field
(d) to the contents of the base register (b). The SDMA location at the resulting
address is read and placed in the destination register (r).
• STr,(b,d)-The store instruction creates an address in the same manner as the load
instruction. The register (r) is stored in the SDMA location at the resulting address.
7.2.3.11.15 Functional Unit Instructions
The functional unit instructions have an 8-bit field that is placed on the functional unit
bus.
Some of these bits are used to select which functional unit should be involved in the
transfer. The remaining bits are decoded by the selected functional unit so their specific
use depends on the functional unit. See Functional Units Programming Model.
There are two functional unit instructions, as follows:
• LDFr,fub-The 8-bit field is placed on the functional unit bus and a read is issued to
the selected functional unit. As a result of this instruction, the SF may be set in the
processor status.
• STFr,fub-The 8-bit field is placed on the functional unit bus and a write is issued to
the selected functional unit. As a result of this instruction, the DF may be set in the
processor status.
7.2.3.11.16 Illegal Instructions
All instruction encodings that are illegal cause the following actions:
• The current PC (which points to one beyond the offending instruction) is put in the
EPC register.
• The loop mode bit is cleared.
• The PC is set to the value stored in the Illegal Instruction Trap Address
(SDMAARM_ILLINSTADDR) register (the default value is 0x0001).
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ILLEGAL-Although any instruction other than those indicated in the SDMA
specification will trigger the illegal instruction mechanism, the ILLEGAL instruction
code is preferred as it will always be kept as illegal in the possible future versions of the
SDMA core.
7.2.3.11.17 Debug Instructions
The following are debug instructions:
• SOFTBKPT-The software breakpoint instruction causes the core to stop and enter
debug mode. The core can then be accessed and started by the OnCE debug block
only.
• done 5-This instruction is used for debugging, as it copies the contents of the PCU
registers and flags to the context memory. Information on this instruction is
described in Saving the Context.
• CpShReg-This instruction copies the context memory into the PCU registers and
flags. Modifying the corresponding memory location before executing this
instruction enables you to have the channel continue from a new instruction address.
This instruction is described in Restoring the Context.
7.2.3.12 Functional Units Programming Model
The functional unit instructions cause an 8-bit code, found in the low eight bits of the
instruction, to be asserted on the functional unit control bus.
Some of these bits are used to select one of several functional units. Functional units
which can be selected include SDMA registers such as MSA and MSD which are not
mapped in the SDMA memory map, and are accessible only through the functional unit
bus. These Functional Unit Registers are listed in the following table. In order to establish
a programming convention, assume the selection bits are some number of the most
significant bits of the 8-bit code. Furthermore, some number of the least significant bits is
decoded by a given functional unit to establish the type of operation to perform.
Table 7-20. Functional Unit Registers
Functional Unit Register Register Name Section/Page
Burst DMA Unit SDMSA Memory Source Address Register Memory Source Address
Programming Register (MSA)
MDA Memory Destination Address Register Memory Destination
Address Register (MDA)
MD Memory Data Buffer Register Memory Data Buffer
Register (MD)
Table continues on the next page...
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Table 7-20. Functional Unit Registers (continued)
Functional Unit Register Register Name Section/Page
(Write) Burst DMA Write
(stf)
(Read) Burst DMA Read
(ldf)
MS Memory State Register State Register (MS)
Peripheral DMA Unit PSA Peripheral Source Address Register Peripheral Source Address
Programming Register (PSA)
PDA Peripheral Destination Address Register Peripheral Destination
Address Register (PDA)
PD Peripheral Data Buffer Register Peripheral Data Register
(PD)
(Write) Peripheral DMA
Write (stf)-Write Mode
(Read) Peripheral DMA
Read (ldf)-Read Mode
PS Peripheral State Register Peripheral State Register
(PS)
More information regarding the functional units can be found in Peripheral DMA Unit,
and Burst DMA Unit.
7.2.3.12.1 Burst DMA Unit Programming
The DMA instructions control the DMA state machine and may cause a DMA cycle on
the associated memory bus.
There are four registers associated with the burst DMA unit: a Memory Source Address
register (MSA), a Memory Destination Address register (MDA), a Memory Data buffer
(MD), and a state register (MS). The burst DMA has two different uses:
• A data transfer between External Memory Interface and SDMA general register
• A data transfer in copy mode where blocks of data are transferred from the source
address to the destination address
7.2.3.12.1.1 Memory Source Address Register (MSA)
The source address register contains the pointer into EXTMC memory associated with
the next read data transfer. It has byte granularity.
Reading the register with the ldf instruction has no side effects, and gives the address
value in the EXTMC memory of the next data that is read by the SDMA during an ldf
MD instruction.
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Writing the source address register has two side effects: If the prefetch bit is set, a DMA
read cycle (8-word read access) is issued with the new address. Any data still located in
the buffer is lost. If there is valid write data in the buffer, it is necessary to force the
DMA to completely flush it out before modifying MSA to guarantee all the data is
effectively written to memory.
The MSA register has two modes of programming:
• Frozen-In frozen mode, the MSA register is not modified after DMA accesses.
• Incremented (default mode)-In incremental mode, MSA is incremented by the
number of bytes transferred during read cycles.
7.2.3.12.1.2 Memory Destination Address Register (MDA)
The destination address register contains the pointer into EXTMC memory associated
with the next write data transfer. It has byte granularity.
Reading the MDA register with the ldf instruction has no side effects. It gives the address
value in the EXTMC memory where the next SDMA data (stf r,MD instruction) is stored
when MD FIFO is flushed.
Writing the destination address register has one side effect. Any data still located in the
buffer is lost. If there is valid write data in the buffer, it is necessary to force the DMA to
completely flush it out before modifying MDA to guarantee all the data is effectively
written to memory.
The MDA register has two modes of programming:
• Frozen-In frozen mode, the MDA register is not modified after DMA accesses.
• Incremented (default mode)-The MDA register is incremented by the number of
bytes transferred during write cycles.
7.2.3.12.1.3 Memory Data Buffer Register (MD)
The data buffer register consists of a bank of 36 bytes that behave like FIFO.
This FIFO stores the eight words received when a read burst is triggered by the DMA
(DMA is in read mode).
The MD register is in write mode after a writing in MDA or after an stf MD instruction.
In that case, a burst write access is automatically triggered when there are more than eight
words in MD. For bandwidth optimization, any transfers between DMA and the EXTMC
controller are based on burst accesses.
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An ldf r,MD|SIZE instruction that reads the data buffer may cause a DMA cycle, as
follows:
• If there are less bytes in the FIFO than the size parameter of the instruction. For
instance, if only two bytes are available in MD and a 4-byte read is requested, a burst
read access is executed to complete the two bytes.
• If the prefetch bit is set, and after reading there is enough space in the FIFO to store a
full burst, a burst read access is triggered.
An stf r,MD|SIZE instruction that writes to the data buffer may cause a DMA cycle if the
number of written bytes in MD is higher than 32 (eight words) or if the flush bit is set.
When DMA is used for data transfer between SDMA and EXTMC (reading or writing),
no immediate error is possible because the block manages a data misalignment issue;
therefore, it is allowed to read/write a word to/from a half-word address. However, the
addresses (source or destination) must belong to the EXTMC memory mapping. The only
potential error, in this mode, would be the error sent back by the EXTMC controller
when an access to a super-user page is detected. The whole transfer on the DMA
associated bus will be considered successful when there are no errors seen on the bus
during the transfer. In copy mode, an immediate error could be returned to SDMA as
described in Burst DMA Unit Error Management.
7.2.3.12.1.4 State Register (MS)
The state register contains the DMA state-machine value. It can be accessed in case of an
error received during a transfer. MS is also accessed to set-up the conditional yielding
feature.
The initialization value of this register is 0 and it consists of the following:
Table 7-21. SDMA_MS Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 spriv stype 0 0 dpriv dtype
W
R 0 0 0 0 y d e 0 0 n
W
Table 7-22. SDMA_MS Field Descriptions
Field Description
31-22 Reserved
Table continues on the next page...
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Table 7-22. SDMA_MS Field Descriptions (continued)
Field Description
21 The spriv value is ignored for this device.
spriv 0 = valid value
1 = Reserved
20 Source Mode. Indicates if MSA has to be incremented (or not) during accesses.
stype 0 Frozen-MSA is not modified.
1 Incremented-MSA is incremented by the number of transferred bytes during read access.
19-18 Reserved
17 The dpriv value is ignored for this device.
dpriv 0 = valid value
1 = Reserved
16 Destination Mode. Indicates if MDA has to be incremented (or not) during accesses.
dtype 0 Frozen-MDA is not modified.
1 Incremented-MDA is incremented by the number of transferred bytes during write access.
15-12 Reserved
11 Conditional Yielding selector. When selected, theyield/yieldge instructions will not switch channels if
the Burst DMA is in Write Mode, and it has less than four bytes in its FIFO. This is aimed at
y
reducing the number of inefficient FIFO flushes due to context switches.
0 Always yields
1 Yields conditionally (when there are less than four bytes in the FIFO in write mode)
10 Access Direction or DMA Mode. DMA is in write mode when data was written into MD by stf MD
instructions, or if a previous DMA cycle on the external bus was a write access. Writing MDA or
d
MSA changes the DMA mode to the respective value. DMA is in read mode when a previous DMA
cycle was a read access, and DMA stays in read mode when data is read by SDMA with an ldf MD
instruction. Reading MDA or MSA does not change the DMA mode.
0 Read Mode
1 Write Mode
9-8 Error. Indicates if the previous access was acknowledged with a bus error.
e 00 No error was received.
01 reserved
10 Error mode
11 error read burst
7-6 Reserved
5-0 Number of bytes in the MD FIFO.
n
7.2.3.12.1.5 Burst DMA Write (stf)
When received from a stf instruction, the function code bits are interpreted as follows,
depending on the addressed register:
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Table 7-23. STF Code Bits
Register 7 6 5 4 3 2 1 0
MSA s p freeze r spriv
MDA dpriv
MD f cpy sz
MS
Table 7-24. STF Code Bit Field Descriptions
Field Description
7-6 Functional Unit selector
s 00 for Burst DMA
5 Prefetch Flag
p (MSA) 0 No prefetch
1 Prefetch required from new MSA
5 Forced Flush Flag
f (MD) 0 Automatic flush
1 FIFO contents are flushed (including the new written data).
4 Address Freeze Mode
freeze (MSA/MDA) 0 Address is normally incremented.
1 Address is frozen.
4 Copy Mode selection
cpy (MD) 0 Write Mode
1 Copy Mode
3-2 Register selection
r 00 MSA
01 MDA
10 MD
11 MS
1-0 Transfer Size
sz (MD/MS) 00 size 0 (no data stored in the FIFO)
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
0 The spriv value is ignored for this device.
spriv (MSA) 0 = valid value
1 = Reserved
0 The dpriv value is ignored for this device.
dpriv (MDA) 0 = valid value
1 = Reserved
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The possible write instructions are listed in the table below (unused bits should always be
cleared).
Table 7-25. Burst DMA STF Instruction List
Binary Assembly Comments
00_0_0_00_00 stf r,MSA Writes content of the SDMA general register (r) to the source address
register. MSA is in incremented mode.
00_0_1_00_00 stf r,MSA|FR Writes content of the SDMA general register (r) to the source address
register. MSA is in frozen mode.
00_1_0_00_00 stf r,MSA|PF Writes content of the SDMA general register (r) to the source address
register, and starts a read burst access. MSA is in incremented mode.
00_1_1_00_00 stf r,MSA|PF|FR Writes content of the SDMA general register (r) to the source address
register, and starts a read burst access.
00_0_0_01_00 stf r,MDA Writes content of the SDMA general register (r) to the destination address
register. MDA is in incremented mode.
00_0_1_01_00 stf r,MDA|FR Writes content of the SDMA general register (r) to the destination address
register. MDA is in frozen mode.
00_1_0_10_00 stf r,MD|SZ0|FL No data transfers between the SDMA and MD, but all valid written data of
the MD is flushed to the memory. An acknowledge or error is sent back to
the SDMA core on transfer completion.
00_0_0_10_01 stf r,MD|SZ8 8-bit (byte) transfer to write buffer MD
00_1_0_10_01 stf r,MD|SZ8|FL 8-bit (byte) transfer to write buffer MD and flush after transfer. All valid
written data of the MD is flushed to memory.
00_0_0_10_10 stf r,MD|SZ16 16-bit (half-word) transfer to write buffer MD
00_1_0_10_10 stf r,MD|SZ16|FL 16-bit (half-word) transfer to write buffer MD and flush after transfer. All
valid written data of the MD is flushed to memory.
00_0_0_10_11 stf r,MD|SZ32 32-bit (word) transfer to write buffer MD
00_1_0_10_11 stf r,MD|SZ32|FL 32-bit (word) transfer to write buffer MD and flush after transfer. All valid
written data of MD is flushed to memory.
00_0_1_10_00 stf r,MD|CPY No data transfer between SDMA and MD but starts a copy transfer whose
length is given by the 4 LSB of r register. (Maximum burst length is eight
words.)
00_0_0_11_11 stf r,MS 32-bit (word) transfer to status register MS
00_0_0_11_00 stf r,MS|SZ0 Clears the error flag (if set). Other MS bits are unchanged; this instruction is
also known as clref MS.
NOTE
When a flush bit is set, the SDMA flushes the FIFO including
the newly written data. An acknowledge is sent to the core
before the flush completes (except if size 0 is used). The goal of
this flush bit is to force a flush, but it is recommended to use it
only when needed (for example, when finishing a row of pixels
during 2D data transfers). Indeed, if this bit is omitted and if
there are more than 32 bytes in the FIFO, a burst write access is
automatically triggered.
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Since all the stf r,MD instructions (including the copy mode)
acknowledge the SDMA core before the store is effective
(except if size 0 is used), it is recommended to perform an ldf
from MS before terminating a channel in order to check the
final error status. (The ldf from MS will stall the core until all
the data was flushed out and the transfer status is known.)
After every stf MD instruction, the MDA is incremented by the
number of bytes that are written in MD, except when it is
programmed in frozen mode.
7.2.3.12.1.6 Burst DMA Read (ldf)
When received from an ldf instruction, the function code bits are interpreted as follows,
depending on the addressed register:
Table 7-26. LDF Code Bits
Register 7 6 5 4 3 2 1 0
MSA s r
MDA
MD p sz
MS
Table 7-27. LDF Code Bit Field Descriptions
Field Description
7-6 Functional Unit selector
s 00 for Burst DMA
5 Prefetch Flag
p (MD) 0 no prefetch
1 automatic prefetch
3-2 Register selection
r 00 MSA
01 MDA
10 MD
11 MS
1-0 Transfer Size
sz (MD) 00 reserved
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
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The table below lists the possible write instructions (unused bits should always be
cleared).
Table 7-28. Burst DMA LDF Instruction List
Binary Assembly Comments
00_0_0_00_00 ldf r,MSA Copies the source address register value into an SDMA general register. It
gives the memory address of the next data that will be read with an ldf MD
instruction.
00_0_0_01_00 ldf r,MDA Copies the destination address register value into an SDMA general
register. It gives the memory address where the next incoming data will be
flushed.
00_0_0_10_01 ldf r,MD|SZ8 8-bit (byte) read
00_1_0_10_01 ldf r,MD|SZ8|PF 8-bit (byte) read. If after this reading and the MD FIFO is empty, a burst
read access at the MSA address is triggered.
00_0_0_10_10 ldf r,MD|SZ16 16-bit (half-word) read
00_1_0_10_10 ldf r,MD|SZ16|PF 16-bit (half-word) read. If after this reading, and the MD FIFO is empty, a
burst read access at the MSA address is triggered.
00_0_0_10_11 ldf r,MD|SZ32 32-bit (word) read
00_1_0_10_11 ldf r,MD|SZ32|PF 32-bit (word) read. If after this reading and the MD FIFO is empty, a burst
read access at the MSA address is triggered.
00_0_0_11_00 ldf r,MS Copy the status register value into an SDMA general register.
NOTE
Read data is 0-extended before writing in the SDMA general
registers. When reading the MD register, the DMA takes data
from the FIFO if it is available. If part or whole data is not in
the FIFO, an external burst read access is performed to provide
the missing data. The SDMA is stalled as long as the required
read data is not complete.
After every reading, MSA is incremented by the number of read
bytes from MD FIFO, except when MSA is programmed in
frozen mode.
7.2.3.12.1.7 Prefetch/Flush and Auto-Flush Management-Burst DMA Unit
The prefetch and auto-flush management enables the SDMA RISC machine to go on
while a DMA access is performed.
When the RISC core requires a prefetch (p = 1) to the Burst DMA, it will receive an
immediate transfer acknowledge before the DMA has finished the external access. This
enables the RISC core to do other things like accessing another DMA machine.
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The basic principle in prefetch mode is for the DMA to anticipate data reads from the
SDMA RISC engine by fetching external bursts of data as soon as there is enough space
in the DMA FIFO to store it. If ever the RISC engine required data that is not available in
the FIFO, the read acknowledge is delayed until the data is available, but it does not have
to wait until the burst completes.
The auto-flush basic principle is similar: An automatic flush is triggered every time there
are eight words to be written in the FIFO. If the FIFO is full and the RISC engine
requires another write, it is stalled until the burst has started and enough space was freed
in the FIFO to store that new data. This means the SDMA RISC engine does not have to
wait for the completion of a burst to receive its acknowledge and continue its processing.
In particular, an auto-flush is executed when DMA is in write mode and if the following
is true:
• If the FIFO is empty and the first write is to a word-aligned address of any size (ex:
the 2 LSB of MDA[1:0]= 0x0), the auto-flush is triggered immediately after the write
of the 32'nd byte.
• If the FIFO is empty, and if MDA is an odd byte address (1, 3, 5, 7,...) and an stf
MD|SZ8 is executed, the byte is flushed to memory. Once MDA increments to a
word aligned address, the auto-flush will be triggered every 32 bytes.
• If the FIFO is empty, and if MDA is a half-word address (2, 6, 0xA,...) and an stf
MD|SZ16 is executed, the two bytes of the incoming data are flushed to memory.
Once MDA increments to a word aligned address, the auto-flush will be triggered
every 32 bytes.
• If the FIFO is empty, and if MDA is not a word-aligned address (ex 1, 2, 3, 5, 6, 7,
9,...), and an stf MD|SZ32 is executed, the first 1 to 3 bytes will be flushed up to the
next word aligned address. Afterwards, an auto-flush will be triggered each time the
FIFO receives 32-bytes.
• Therefore, if an stf MD|SZ32 is executed with MDA equal to 0x1 and with an empty
MD FIFO, the bytes located at addresses 1, 2, and 3 are flushed, and the byte located
at address 4 remains in MD FIFO. This solves the misalignment issue. Additionally,
the next write instructions (stf) complete the FIFO until it contains eight words; then
a burst write is executed by the DMA to empty the FIFO. Protocol on the external
bus does not support bursts of different data types (byte, half-word, or word).
For example, consider the case where data is written using a byte access, stf MD|
SZ8. The value of MDA during the very first byte write determines when the auto-
flush will occur as follows:
• If MDA=0x0, the flush occurs following the write of byte 32
• If MDA=0x1, the flush occurs following the write of byte 1, byte 3 and byte 35.
• If MDA=0x2, the flush occurs following the write of byte 2 and byte 34.
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• If MDA=0x3, the flush occurs following the write of byte 1 and byte 33.
• If MDA=0x4, the flush occurs following the write of byte 32
The flush command forces the DMA to flush all MD valid bytes to the EXTMC
controller. An acknowledge is sent immediately to the SDMA, and any potential error is
reported on a future access. It is thus essential to conclude a transfer with a last read from
MS, which will stall the core until all data was flushed out and returned to the transfer
status (acknowledge or error).
NOTE
During this kind of auto-flush (which occurs only at the
beginning of a misaligned write transfer) no acknowledge is
sent back to the SDMA, which is stalled until a flush is
completed.
7.2.3.12.1.8 Data Alignment and Endianness-Burst DMA Unit
7.2.3.12.1.8.1 Burst DMA in Read Mode
For every read access to MD, the data returned to the SDMA core and the new FIFO state
depends on the MSA status and the access size.
The FIFO is considered as a stack of 36 bytes: Data is fetched externally on a 32-bit bus,
but the valid bytes only are stored in the FIFO and left-aligned (for a transfer of
consecutive words, it is only the first word that may be truncated). The following table
shows the FIFO byte alignment strategy and the corresponding MSA, the returned data,
and the new FIFO state for any access size of an internal read from MD.
Table 7-29. FIFO Read Configuration
Before read Internal read Read data After read
access size
MSA[1:0] FIFO state MSA[1:0] FIFO state
00 x0 x1 x2 x3 sz8 00 00 00 x0 01 x1 x2 x3 y0
y0 y1 y2 y3 y1 y2 y3 z0
z0 z1 z2 z3 sz16 00 00 x0 x1 10 x2 x3 y0 y1
and so on... y2 y3 z0 z1
sz32 x0 x1 x2 x3 00 y0 y1 y2 y3
z0 z1 z2 z3
01 x1 x2 x3 y0 sz8 00 00 00 x1 10 x2 x3 y0 y1
y1 y2 y3 z0 y2 y3 z0 z1
z1 z2 z3 t0 sz16 00 00 x1 x2 11 x3 y0 y1 y2
and so on... y3 z0 z1 z2
sz32 x1 x2 x3 y0 01 y1 y2 y3 z0
Table continues on the next page...
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Table 7-29. FIFO Read Configuration (continued)
Before read Internal read Read data After read
access size
MSA[1:0] FIFO state MSA[1:0] FIFO state
z1 z2 z3 t0
10 x2 x3 y0 y1 sz8 00 00 00 x2 11 x3 y0 y1 y2
y2 y3 z0 z1 y3 z0 z1 z2
z2 z3 t0 t1 sz16 00 00 x2 x3 00 y0 y1 y2 y3
and so on... z0 z1 z2 z3
sz32 x2 x3 y0 y1 10 y2 y3 z0 z1
z2 z3 t0 t1
11 x3 y0 y1 y2 sz8 00 00 00 x3 00 y0 y1 y2 y3
y3 z0 z1 z2 z0 z1 z2 z3
z3 t0 t1 t2 sz16 00 00 x3 y0 01 y1 y2 y3 z0
and so on... z1 z2 z3 t0
sz32 x3 y0 y1 y2 11 y3 z0 z1 z2
z3 t0 t1 t2
7.2.3.12.1.8.2 Burst DMA in Write Mode
For every write access to the MD, the new FIFO state depends on the MDA status and the
access size.
The FIFO is considered as a stack of 36 bytes: Data is stored in the FIFO according to the
internal access size and the former MDA value. The following table shows the FIFO byte
alignment strategy corresponding to MDA, as well as the new FIFO state for any access
size of an internal write to MD.
Table 7-30. FIFO Write Configuration
Before write Internal write Written data After write
access size
MDA[1:0] FIFO state MDA[1:0] FIFO state
00 tt uu vv ww sz8 ?? ?? ?? x0 01 tt uu vv ww
?? ?? ?? ?? x0 ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 10 tt uu vv ww
x0 x1 ?? ??
?? ?? ?? ??
sz32 x0 x1 x2 x3 00 tt uu vv ww
x0 x1 x2 x3
?? ?? ?? ??
01 tt uu vv ww sz8 ?? ?? ?? x0 10 tt uu vv ww
Table continues on the next page...
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Table 7-30. FIFO Write Configuration (continued)
Before write Internal write Written data After write
access size
MDA[1:0] FIFO state MDA[1:0] FIFO state
xx ?? ?? ?? xx x0 ?? ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 11 tt uu vv ww
xx x0 x1 ??
?? ?? ?? ??
sz32 x0 x1 x2 x3 01 tt uu vv ww
xx x0 x1 x2
x3 ?? ?? ??
10 tt uu vv ww sz8 ?? ?? ?? x0 11 tt uu vv ww
xx yy ?? ?? xx yy x0 ??
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 00 tt uu vv ww
xx yy x0 x1
?? ?? ?? ??
sz32 x0 x1 x2 x3 10 tt uu vv ww
xx yy x0 x1
x2 x3 ?? ??
11 tt uu vv ww sz8 ?? ?? ?? x0 00 tt uu vv ww
xx yy zz ?? xx yy zz x0
?? ?? ?? ?? ?? ?? ?? ??
and so on... sz16 ?? ?? x0 x1 01 tt uu vv ww
xx yy zz x0
x1 ?? ?? ??
sz32 x0 x1 x2 x3 11 tt uu vv ww
xx yy zz x0
x1 x2 x3 ??
NOTE
If the FIFO mode changes from a write to a read mode, all
remaining written bytes in MD are lost but no error is returned.
Typically, this happens if an ldf MD is executed after stf MD
instructions. Before a mode change, it is recommended to force
the flush of a potential remaining byte by a stfMD|SZ0|FL
instruction. In the same way, if a FIFO mode changes from a
read to a write mode, all prefetched data present in the FIFO is
lost and no error is returned.
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7.2.3.12.1.8.3 Endianness-Burst DMA Unit
Big and Little Endian are supported by the Burst DMA, but data is always stored in MD
in Big Endian.
Byte manipulation is performed when data is exchanged with an Burst controller (for
example, during read or write burst accesses).
7.2.3.12.1.9 Burst DMA Unit Copy Mode
A mechanism is available to perform fast Arm-to-Arm transfers.
Data does not flow through the SDMA core: It is kept in the DMA FIFO. This
mechanism is selected when writing MD with a special option in the instruction code
(copy flag).
It is possible to transfer up to eight words in one SDMA instruction (this does not mean
in one cycle). In this mode, every time an stf MD|CPY is executed, a read burst is
executed and directly followed by a write burst transfer. Burst transfers are limited to
eight words. The size of the transfer (in words)-given by the SDMA general register (4
LSB)-is also limited to eight. The following SDMA code shows how 100 bytes could be
copied from the MSA address to the MDA address. This is sample code only.
Burst DMA copy mode example
ldi r0,@src
stf r0,MSA // Source address setup
ldi r1,@dst
stf r1,MSA // Destination address setup
ldi r0,0x64 // data transfer counter
ldi r1,0x8
MAIN_XFER:
cmphs r0,r1 // Is r0 >= 0x8
bf LAST_XFER // If not, jump to last transfer label
stf r1,MD|CPY // Copy 8 words from MSA to MDA address.
subi r0,0x8 // Decrement counter
jmp MAIN_XFER // return to main transfer loop
LAST_XFER:
stf r0,MD|CPY
The main transfer loop is executed 12 times; then r0 equals 4 and the last transfer loop is
run.
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In this mode, an acknowledge is transmitted to the core as soon as the read burst can start;
thus, a first copy instruction returns an immediate acknowledge and subsequent copy
instructions will be acknowledged as soon as the previous copy has finished.
7.2.3.12.1.10 Burst DMA Unit Error Management
Another point to consider is the management of errors.
Because the DMA immediately sends an acknowledge to the RISC core (except for the
stf MS|SZ0|FLS instruction), it assumes no error will occur. If an error occurs, it is
flagged (transfer error acknowledge) for the following DMA access.
This should not be a problem if the DMA is used properly. The MD accesses are meant to
stall the SDMA as little as possible to optimize throughput and hide calculation time.
Therefore, final access to MS should be performed before closing a channel. This access
waits until any pending operation is finished in the burst DMA and gather any remaining
error.
In copy mode, an error could be immediately returned to the SDMA on execution of the
ldf copy or stf copy instruction. It happens when MSA or MDA are not word addresses
(for example, 0[4]). This is because copy mode must only be used for transferring a large
packet of aligned data.
When an error is received during a read transfer to the external bus, which may occur
during the burst accesses, the MD FIFO contains the valid beats of the burst, and the error
flag of MS is set to 2'b11 (error read burst). It is possible to read MS ("n" field) to know
how much valid data remains in MD and when MD is empty (after ldf instructions). The
next read MD instruction sets the MS error flag to 2'b10 (error mode), and an error is sent
back to the SDMA core. In error mode, it is possible to read MSA, which gives the
address of the error data. Any attempt to read or write MD, or to modify MDA or MSA in
error mode, gives rise to an error; therefore, an error flag must be reset by clearing MS at
the end of the SDMA code section responsible for error management.
In "error read burst" mode, writing MDA, MSA, or MD, or starting a copy transfer by a
stf MD|COPY instruction will cancel the error mode. The following table shows when an
immediate error is sent back according to the executed instruction.
Table 7-31. Possibilities in ERROR READ BURST Mode
DMA Instruction Immediate Error Comments
stf rn, MD stf rn, MSA (|U |PF) stf rn, NO Error mode is reset. MSA, MDA, or MD are updated and a
MDA DMA cycle may start. For the stf MD|COPY, a copy loop is
executed.
stf rn,MD|COPY
stf rn, MS NO MS is updated.
Table continues on the next page...
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Table 7-31. Possibilities in ERROR READ BURST Mode (continued)
DMA Instruction Immediate Error Comments
ldf rn, MS ldf rn, MSA ldf rn, MDA NO MS, MSA, and MDA could be read in ERROR READ mode
without any side effects (for example, no DMA cycle is
triggered).
ldf rn, MD YES/NO Immediate error if there is no more data available for read in
the FIFO.
When an error is received during a write transfer, the error is reported to the next DMA
access. In this case, an error is sent to the SDMA core and the DMA goes to its error
mode. Reading MS gives the number of bytes that remain in MD; reading MDA gives the
address of the error data. Any attempt to read or write MD, or to modify MDA or MSA in
error mode, give rise to an error; therefore, an error flag must be reset by clearing MS at
the end of the SDMA code section responsible for error management.
Table 7-32. Possibilities in ERROR Mode
DMA Instruction Immediate Error Comments
stf rn, MD stf rn, MSA stf rn, MDA Yes Any attempt to modify MD, MSA, MDA will raise an
immediate error and burst DMA remains in error mode. When
address registers are write-accessed, an error is returned.
stf rn, MS No This is the only way to exit error mode. MS[9:8] must be reset
by an stf MS|SZ0 instruction.
ldf rn, MS ldf rn, MSA ldf rn, MDA No MS, MSA, and MDA could be read in error mode without any
side effects (for example, no DMA cycle is triggered).
ldf rn, MD Yes Whatever the DMA direction (read or write), an ldf rn triggers
an immediate error.
7.2.3.12.1.11 Conditional Yielding-Burst DMA Unit
The standard SDMA transfer is based upon a hardware loop that has the following
structure:
Hardware Loop
loop
load Rn,source // can be ldf or ld
<computation> // can be done through functional units
store Rn,dest // can be st or stf
done 0 // yield
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This structure needs to be kept independent of the functional units' particularities
regarding the context switch. However, there can be variations in the context switch's
efficiency, which can depend on the number of data received up to that point, and on the
data itself.
The DMA, with its 8-word burst capability, has a preferable context switch period when
its address register is 8-word aligned: It is the only moment that occurs once every eight
loops when the succession of bursts is not broken by the context switch. When this is not
the case, a context switch requires the storing (or loading) of less than eight words, which
requires separate accesses and is far less efficient. The rest of the 8-word packet is stored
(or loaded) after the context restore, and this is done as separate accesses.
The proposed solution is a conditional yielding, which occurs only when the DMA is in
an optimum state. It does not require any modification to the scripts. The condition is
decided at the DMA level.
The DMA can be programmed in two modes-conditional or always-true-for every
channel, which provides complete flexibility. By default, the DMA is not in conditional
mode.
The DMA condition is computed from the FIFO fill level and the various modes, as
follows:
• When copy mode is selected, regardless of the transfer direction ('read' or 'write'), the
condition is always true.
• In read mode, the condition is always true.
• In write mode, the condition is true when there are four bytes or less in the FIFO; it is
false when there are more than four bytes. The 4-byte limit comes from the
possibility of saving those bytes as MD with absolutely no impact on the bus
accesses.
The aim at conditional yielding is to avoid splitting bus accesses (especially bursts).
7.2.3.12.2 Peripheral DMA Unit Programming
The peripheral DMA unit is connected to the Multi-Layer DMA Crossbar Switch of the
Arm platform.
Its goal is to perform data transfers between any blocks connected to the DMA bus of this
platform. These blocks are either peripherals or memories. The peripheral DMA could be
seen as the Arm platform DMA controller.
The DMA performs data transfers in three modes:
• Read mode, where data is read from peripherals or from memory connected to the
Arm platform and copied in a SDMA general register.
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• Write mode, where data of a general register has to be written in a peripheral or a
memory.
• Copy mode, where data is read from a peripheral (or memory) at a source address
(PSA) and automatically written to a peripheral (or memory) at a destination address
(PDA).
In copy mode, no SDMA general register is involved as transferred data only goes
through the data register of the DMA.
The peripheral DMA has three addressing modes: frozen, incremented, and decremented,
as follows:
• Frozen mode-When source or destination addresses are frozen, their value is not
modified after a transfer. This mode is typically used for addressing peripheral FIFOs
located at a fixed address.
• Incremented mode-When source or destination addresses are in incremented mode,
after every transfer they are incremented by the number of bytes transferred.
• Decremented mode-In decremented mode, addresses are decremented by the number
of bytes transferred.
The peripheral DMA registers are as follows:
• Two, 32-bit address registers (PSA and PDA) that respectively contain the source
address for a read access and the destination address for a write access
• A 32-bit status register (PS) that contains information on the peripheral DMA
configuration, such as the number of valid bytes in the data register, the error flag,
the source and destination address mode, and so on.
• A 32-bit data register (PD) that stores data involved in a data transfer
7.2.3.12.2.1 Peripheral Source Address Register (PSA)
The source address register contains a pointer to a source peripheral or a memory
associated with the next read data transfer. It has byte granularity.
It is based on the following:
• A 32-bit register (PSA) to store the address value
• A 2-bit register (stype) to store the source address mode (frozen, incremented, or
decremented)
• A 2-bit register (ssize) to store the source target data path size (byte, half-word, or
word)
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Reading the register with the ldf instruction has no side effects and gives the address
value of the next data that will be read by the SDMA during an ldf MD instruction.
Writing the source address register may have side effects. If there is valid write data in
the data register and the source address is changed, the write data is discarded. If the
prefetch bit is set, a DMA read cycle is issued with the new address.
When PSA is to be written, you must specify the source target address mode, providing
its size (byte, half-word, or word). This enables omission of the size field in all ldf MD
instructions. When DMA performs a read cycle, its size is given by the value of the PSA
source size register (ssize). If source is a memory in incremented mode, first programmed
in word mode (stf PSA|SZ32|I), and if an SDMA script needs to read bytes from this
memory, the size of the source target must be updated before executing new accesses.
The source address mode and its size are given by labels added to the stf PSA instruction
as described in the write section. The ssize and stype registers are part of the DMA status
register (PS).
Writing to PSA may issue an immediate error if the source size is not compatible with the
value to be written into the PSA register. For instance, writing a 2 in PSA and specifying
that it is memory-accessed in word mode creates an immediate error.
7.2.3.12.2.2 Peripheral Destination Address Register (PDA)
The destination address register contains a pointer to a source peripheral or a memory
associated with the next write data transfer. It has byte granularity.
It is based on the following:
• A 32-bit register (PDA) to store the address value
• A 2-bit register (dtype) to store the destination address mode (frozen, incremented, or
decremented)
• A 2-bit register (dsize) to store the destination target data path size (byte, half-word,
or word)
Reading the register with the ldf instruction has no side effects, and gives the address
value of the next data that will be written by SDMA during an stfMD instruction. Writing
the destination register has no side effect. Similar to the PSA register, the destination
address mode and source are specified in the stf PDA instruction and may also generate
an error in case of incorrect programming.
7.2.3.12.2.3 Peripheral Data Register (PD)
The data register of the peripheral DMA is a 32-bit register. When the destination address
is correctly set up, any writing to PD will automatically flush the new input data.
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The number of SDMA bytes that will be transferred is given by the PDA size register.
Unlike other SDMA DMAs, PD is not a FIFO: It is not used to accumulate bytes that
from the SDMA and must be packed before being sent to external memories. In read
mode, and if the source address is correctly set up, an ldf instruction will empty PD. If a
prefetch is required along with the instruction, the DMA will initiate a new read transfer.
Reading PD in prefetch mode only stalls the SDMA when the prefetched data is not yet
available. Writing PD only stalls the SDMA if the previous write operation was not
completed. As soon as the previous operation is over, the acknowledge is sent back to the
SDMA RISC engine.
An error flag-part of PS-is set when an external access fails. The error is thus reported to
the next SDMA instruction that involves the peripheral DMA.
7.2.3.12.2.4 Peripheral State Register (PS)
The state register contains the DMA state-machine value. It can be accessed in case of an
error received during a transfer.
Although all PS fields can be written by an stf instruction, it is recommended to access
only the error bit (to reset it). Modifying other PS fields will provide an un-guaranteed
DMA behavior.
The initialization value of PS is 0, and it consists of the following structure:
Table 7-33. PS Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 ssize stype dsize dtype
W
R 0 0 0 0 0 d e 0 0 0 0 0 n
W
Table 7-34. PS Field Descriptions
Field Description
31-24 Reserved
23-22 Source Target Size. Determines the size of the read transfers on the external bus. It should
match the accessed device characteristics.
ssize
00 reserved
01 Byte (8 bits)
10 half-word (16 bits)
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Table 7-34. PS Field Descriptions (continued)
Field Description
11 word (32 bits)
21-20 Source address Mode. Determines whether PSA is incremented, decremented, or kept
unmodified after every read from the external bus.
stype
00 Frozen Mode
01 Incremented Mode
10 Decremented Mode
11 reserved
19-18 Destination Target Size. Determines the size of the write transfers on the external bus. It should
match the accessed device characteristics.
dsize
00 reserved
01 Byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
17-16 Destination address Mode. Determines whether PDA is incremented, decremented, or kept
unmodified after every write on the external bus.
dtype
00 Frozen Mode
01 Incremented Mode
10 Decremented Mode
11 reserved
15-11 Reserved
10 Direction Flag or DMA Mode. DMA is in write mode when data was written into PD by stf PD
instructions, or if a previous DMA cycle on the external bus was a write access. Writing PDA or
d
PSA does not change the DMA mode.
DMA is in read mode when a previous DMA cycle was a read access, and DMA stays in read
mode when data is read by the SDMA with an ldf PD instruction. Reading PDA or PSA does not
change the DMA mode.
0 Read Mode
1 Write Mode
9-8 Error. Indicates if the previous access was acknowledged with a bus error.
e 00 No error was received.
01 reserved
10 Error mode
11 Error read
7-3 Reserved
2-0 number of bytes in PD
n
NOTE
dtype, dsize, stype, and ssize are updated when PSA and PDA
are written.
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7.2.3.12.2.5 Peripheral DMA Write (stf)-Write Mode
When written by an stf instruction, the function code bits are interpreted as follows:
Table 7-35. STF Code Bits
Register 7 6 5 4 3 2 1 0
PSA s p ar am sz
PDA
PD pdsel
PS pssel
Table 7-36. STF Code Bits Field Descriptions
Field Description
7-6 Functional Unit selector
s 11 for Peripheral DMA
5 Prefetch Flag
p (PSA) 0 no prefetch
1 automatic prefetch
4 Address Register Selector
ar (PSA/PDA) 0 PSA
1 PDA
3-2 Address Mode. Determines how PSA or PDA is modified after every read or write access to the
PD.
am (PSA/PDA)
00 Frozen-Address registers are not modified after the transfer.
01 Incremented-Address registers are incremented by the number of transferred bytes.
10 Decremented-Address registers are decremented by the number of transferred bytes.
11 Updated-PSA and PDA are not modified. Either address mode is not modified, but the width
of the data path is updated by the sz field.
1-0 Transfer Size
sz 00 reserved
01 byte (8 bits)
10 half-word (16 bits)
11 word (32 bits)
5-0 PD access selector
pdsel 001000 is the only valid option
5-0 PS access selector
pssel 111111 writes to PS
001100 only clears the error flag in PS
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Due to the large number of possible stf instructions, the following table provides only a
short list of all the possible write instructions:
Table 7-37. Peripheral DMA STF Instruction List
Binary Assembly Comments
11_00_00_01 stf Rn, PSA|SZ8 |F • Source is a byte, half-word, or word target at the Rn address. Any
11_00_00_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|F
11_00_00_11 access to the source.
stf Rn, PSA|SZ32|F • Source address is frozen.
11_10_00_01 stf Rn,PSA|SZ8 |F|PF stf • Source is a byte, half-word, or word target at the Rn address. Any
11_10_00_10 Rn,PSA |SZ16|F|PF further PD read instructions will trigger a byte, half-word, or word
11_10_00_11 access to the source.
stf Rn,PSA |SZ32|F|PF
• 1, 2, or 4 bytes are fetched from the peripheral source.
• Source address is frozen.
11_00_01_01 stf Rn, PSA|SZ8 |I stf Rn, • Source is a byte, half-word, or word target at the Rn address. Any
11_00_01_10 PSA|SZ16|I stf Rn, PSA| further PD read instructions will trigger a byte, half-word, or word
11_00_01_11 SZ32|I access to the source.
• Source address is in incremented mode: PSA = PSA + 1,2 or 4
after read PD.
11_10_01_01 stf Rn, PSA|SZ8 |I|PF stf • Source is a byte, half-word, or word target at the Rn address. Any
11_10_01_10 Rn, PSA|SZ16|I|PF stf Rn, further PD read instructions will trigger a byte, half-word, or word
11_10_01_11 PSA|SZ32|I|PF access to the source.
• Source address is in incremented mode: PSA = PSA + 1, 2, or 4
after read PD.
• 1, 2, or 4 bytes are fetched from the peripheral source.
11_00_10_01 stf Rn, PSA|SZ8 |D • Source is a byte, half-word, or word target at the Rn address. Any
11_00_10_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|D
11_00_10_11 access to the source.
stf Rn, PSA|SZ32|D • Source address is in incremented mode: PSA = PSA-1,2, or 4 after
read PD.
11_10_10_01 stf Rn, PSA|SZ8 |D|PF • Source is a byte, half-word, or word target at the Rn address. Any
11_10_10_10 further PD read instructions will trigger a byte, half-word, or word
stf Rn, PSA|SZ16|D|PF
11_10_10_11 access to the source.
stf Rn, PSA|SZ32|D|PF • Source address is in incremented mode: PSA = PSA-1,2, or 4 after
read PD.
• 1, 2, or 4 bytes are fetched from the peripheral source.
11_00_11_01 stf Rn, PSA|SZ8 |U stf Rn, • Update source pointer to memory, which becomes a pointer to a
11_00_11_10 PSA|SZ16 |U stf Rn, PSA| memory accessed in byte, half-word, or word.
11_00_11_11 SZ32 |U • PSA value is not modified by Rn.
• Bytes present in PD are lost.
11_10_11_01 stf Rn, PSA|SZ8 |PF|U stf • Update source pointer, which becomes a pointer to a target
11_10_11_10 Rn, PSA|SZ16 |PF|U accessed in byte, half-word, or word.
11_10_11_11 • PSA value is not modified by Rn.
stf Rn, PSA|SZ32 |PF|U
• Bytes present in PD are lost.
• 1, 2, or 4 bytes are fetched from the memory source.
11_01_00_01 stf Rn, PDA|SZ8 |F • Destination is a byte, half-word, or word target at the Rn address,
11_01_00_10 and any further PD write instructions will trigger byte, half-word, or
stf Rn, PDA|SZ16|F
11_01_00_11 word access to the destination.
stf Rn, PDA|SZ32|F • Destination address is frozen.
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Table 7-37. Peripheral DMA STF Instruction List (continued)
Binary Assembly Comments
11_01_01_01 stf Rn, PDA|SZ8 |I stf Rn, • Destination is a byte, half-word, or word target at the Rn address,
11_01_01_10 PDA|SZ16|I stf Rn, PDA| and any further PD write instructions will trigger byte, half-word, or
11_01_01_11 SZ32|I word access to the destination.
• Destination address is in incremented mode: PDA = PDA + 1, 2, or
4 after write PD.
11_01_10_01 stf Rn, PDA|SZ8 |D • Destination is a byte, half-word, or word target at the Rn address,
11_01_10_10 and any further PD write instructions will trigger byte, half-word, or
stf Rn, PDA|SZ16|D
11_01_10_11 word access to the destination.
stf Rn, PDA|SZ32|D • Destination address is in incremented mode: PDA = PDA-1, 2, or 4
after write PD.
11_01_11_01 stf Rn, PDA|SZ8 |U stf Rn, • Update destination pointer to memory, which becomes a pointer to
11_01_11_10 PDA|SZ16 |U stf Rn, PDA| a memory accessed in byte, half-word, or word.
11_01_11_11 SZ32 |U • PDA value is not modified by Rn
• bytes present in PD are lost
11_00_10_00 stf Rn, PD • Write "dsize" bytes of Rn in PD and automatically flush to
destination target
11_11_11_11 stf Rn, PS • Write status register
11_00_11_00 stf Rn,clrefPS • Clear error flag if set
NOTE
When writing PD, size information is not important: It is
embedded in the dsize field of PDA register. If dsize is 1, 2, or
4, then one, two, or four bytes from Rn is written to the PD
register, and automatically flushed out to the destination target.
7.2.3.12.2.6 Peripheral DMA Read (ldf)-Read Mode
When received from an ldf instruction, the function code bits are interpreted as follows.
Table 7-38. LDF Code Bits
Register 7 6 5 4 3 2 1 0
PSA s ar a
PDA
PD p cpy
PS pssel
Table 7-39. LDF Code Bits Descriptions
Field Description
7-6 Functional Unit selector
s 11 for Peripheral DMA
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Table 7-39. LDF Code Bits Descriptions (continued)
Field Description
5 Prefetch Flag
p (PD) 0 no prefetch
1 automatic prefetch
4 Address Register Selector
ar (PSA/PDA) 0 PSA
1 PDA
4 Copy Mode
cpy (PD) 0 standard access
1 copy mode access
3 Register Set selection
a 0 PSA or PDA
1 PD or PS
5-0 PS access selector
pssel 111111 is the only valid option to read PS
Table 7-40. Peripheral DMA LDF Instruction List
Binary Assembly Comments
11_0_0_0_000 ldf Rn, PSA Reads 32-bit of PSA value
11_0_1_0_000 ldf Rn, PDA Reads 32-bit of PDA value
11_0_0_1_000 ldf Rn, PD Reads programmed source size bytes of PD (0-extended)
11_1_0_1_000 ldf Rn, PD|PF Reads programmed source size bytes of PD (0-extended), and starts a
prefetch at PSA address.
11_0_1_1_000 ldf Rn, PD|COPY Starts a copy transfer from the source target at the PSA address to the
destination target at the PDA address. No data transmits through Rn, but
Rn contents are lost (Rn is loaded with PD temporary contents that are
not the copied data).
11_111111 ldf Rn, PS Reads 32-bit of PS value
NOTE
When reading PD, size information is not important: It is
embedded in the ssize field of the PSA register. If ssize is 1, 2,
or 4, the one, two, or four bytes is transferred from PD to Rn.
Read data is 0-extended.
7.2.3.12.2.7 Peripheral DMA Unit Copy Mode
Like burst DMA, the peripheral DMA unit has a copy mode that is used when data
transfers do not involve SDMA general registers.
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Data is read from the source target at a PSA address, stored in PD, and then automatically
flushed to the destination target at the PDA address. Copy mode is only available for
transfers that involve two targets of the same data path width.
Since copy mode is invoked with an ldf instruction, the loaded general purpose register
loses its previous contents. (However, the new contents are unpredictable as they depend
on temporary values that are seen on the external DMA bus.)
7.2.3.12.2.8 Error Management
Peripheral DMA generates two kinds of errors: the immediate error that sanctioned
incorrect register programming; and the error triggered by the previous access and stored
in the error flag of PS until a DMA instruction is executed.
7.2.3.12.2.8.1 Immediate Errors
The following table lists all incorrect DMA register setups.
Table 7-41. Immediate Errors with Peripheral DMA
Rn[1:0] values DMA instruction Comments
0x01 stf Rn, PSA|SZ16|F If PSA points to a half-word peripheral or to a half-word
address in memory, its value must be 0 modulo 2.
0x11 stf Rn, PSA|SZ16|I
stf Rn, PDA|SZ16|F
stf Rn, PDA|SZ16|I
0x01 stf Rn, PSA|SZ32|F If PSA points to a word peripheral or to a word address in
memory, its value must be 0 modulo 4.
0x10 stf Rn, PSA|SZ32|I
0x11 stf Rn, PDA|SZ32|F
stf Rn, PDA|SZ32|I
PSA[1:0]-PDA[1:0] DMA instruction Comments
0x01 stf Rn, PSA|SZ32|U stf When PDA or PSA is updated and becomes a pointer to a
Rn, PDA|SZ32|U word address in memory, its content must be 0 modulo 4.
0x10
0x11
0x01 stf Rn, PSA|SZ16|U When PDA or PSA is updated and becomes a pointer to a
half-word address in memory, its content must be 0 modulo
0x11 stf Rn, PDA|SZ16|U
2.
Read/Write PD instruction Comments
stf Rn,PD If PDA size (dsize) has never been set up before an stf PD instruction (dsize=0) If
PSA size (ssize) has never been set up before an ldf PD instruction (ssize=0)
ldf Rn,PD
ldf Rn,PD|CPY Copy mode is possible only between two targets whose data path width is identical.
It is P8↔P8, P16↔P16, or P32↔P32 regardless of the way the address registers are
incremented.
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7.2.3.12.2.8.2 Data Transfer Errors
When PSA and PDA are correctly set up, the only error that may arise for an ldf PD or stf
PD instruction would be the error of the previous DMA cycle.
Error handling is driven by a single consideration: When an error occurred during a data
read on the DMA interface, this error should appear as a transfer error to the core when
the core attempts to retrieve the data that was not successfully read from the accessed
device (memory or peripheral).
When an error occurred during a write access to the DMA interface, the data is still
available in PD and should not be destroyed by subsequent core accesses: The core must
be warned about the error issue.
There are three error handling mechanisms for each case: Read Error (First Phase), Write
Error and Read Error (Second Phase), and Copy Mode Errors handling.
7.2.3.12.2.8.3 Read Error (First Phase)
If an error occurred during a prefetch command, the peripheral DMA enters its ERROR
READ mode (PS[9:8]=11). In this mode, the error is reported on the next ldf PD
instruction and writing PSA, PDA, or PD will cancel the error flag.
The block returns no error mode and instructions are normally executed (a DMA cycle
may be triggered). Similarly, initiating a copy transfer will reset the error flag and start a
copy transfer. The following table details which instructions can be executed in this
mode.
Table 7-42. Possibilities in ERROR READ Mode
DMA Instruction Immediate Error Comments
stf rn, PD stf rn, PSA (|U |PF) stf rn, NO Error mode is reset, PSA or PDA are updated, or a write
PDA cycle is started. For the ldf PD|COPY, a copy loop is
executed.
ldf rn,PD|COPY
stf rn, PS NO PS is updated.
ldf rn, PS ldf rn, PSA ldf rn, PDA NO PS, PSA, and PDA could be read in ERROR READ mode
without any side effects (for example, no DMA cycle is
triggered).
ldf rn, PD YES Error of the previous read access is reported here and the
peripheral DMA enters its ERROR mode.
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7.2.3.12.2.8.4 Write Error and Read Error (Second Phase)
The peripheral DMA enters its ERROR mode (PS[9:8]=10) when the previous DMA
write cycle failed, or, as explained in Read Error (First Phase), when an ldf PD is
executed while the block is in ERROR READ mode. When a DMA cycle failed, address
registers (PSA, PDA) are not modified and continue to point to the problematic address.
In ERROR mode, stf instructions may raise an immediate error, and ldf instructions will
not (as detailed in the table below).
Table 7-43. Possibilities in ERROR Mode
DMA Instruction Immediate Error Comments
stf rn, PD stf rn, PSA stf rn, PDA YES Any attempt to modify PD, PSA, or PDA will raise an
immediate error, and the peripheral DMA stays in ERROR
mode. When address registers are write accessed, an error
is returned.
stf rn, PS NO This is the only way to exit the ERROR mode. PS[3] must be
reset by an stf PS instruction.
ldf rn, PS ldf rn, PSA ldf rn, PDA NO PS, PSA, and PDA could be read in ERROR mode without
any side effects (for example, no DMA cycle is triggered).
ldf rn, PD YES Whatever the DMA direction (read or write), an ldf rn, PD
instruction will show an immediate error.
7.2.3.12.2.8.5 Copy Mode Errors
Because copy mode is a write access that follows a read access, there are two possible
cases of bus error.
When the read access incurs a bus error, the peripheral DMA behaves exactly as
described in Read Error (First Phase) and Write Error and Read Error (Second Phase) : It
enters its ERROR READ mode, and so on.
When the error occurred during the write access of the copy transfer, the DMA enables
the core to retrieve the data that was read because it is assumed the read from the
peripheral removed the data from its source device. Therefore, the data to be flushed is
still in PD. Any subsequent access to PD triggers an error to the core, which should
execute its error handling procedure.
Once the ERROR mode is left (after writing to PS), it is possible for the core to retrieve
the data in PD with an ldf instruction or try to flush PD contents once again (for example,
when the error was due to a full FIFO and the script waited for the FIFO to be emptied)
with another ldf instruction in copy mode. This latter instruction detects that there is valid
data in PD, tries to flush it, and thus skips the read phase of the copy instruction. This is a
different behavior from the usual stf PD instruction that overwrites PD with the selected
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General Purpose register contents. The same mechanism can be used any time PD holds
data that is not written because of a bus error on the DMA interface; when the data was
written via a copy instruction, or via the usual stf PD instruction.
7.2.3.12.2.8.6 Error Check Example
The following code illustrates an example checking for both immediate and data transfer
errors on a store to the PD register. The first bdf instruction checks for an immediate
error, but if a data transfer error occurred it is reported until the next instruction to access
the Peripheral DMA. A second check of the error flags is done after the ldf PS
instruction. The value of PS here can be ignored. The act of reading any register in
Peripheral DMA while it is in an error mode that returns the error to the core to set either
the SF or DF flag. Any error returned on an ldf command sets the SF flag and any error
returned on an stf instruction sets the DF flag. This can create a situation as shown in the
example where a bus error during a DMA write which would normally be considered as a
destination fault is reported as a source fault because the error was reported to the SDMA
core during an ldf instruction.
Table 7-44. Peripheral DMA Error Check
Function Instruction Comment
clrf 0 Clear SF and DF flags
stf R4, PD Write data to memory
bdf error_routine Check for immediate error from write to
PD.
ldf r3, PS Read PS (PS value in R3 can be
ignored)
bsf error_routine Check for bus error from "stf R4,PD". SF
is set because it is a ldf instruction, even
though the original error was a
destination fault.
7.2.3.12.2.9 Peripheral DMA Unit Prefetch/Flush Management
There is no flush bit because every time data is stored in PD by a stf PD instruction-
assuming PDA is correctly programmed-it is automatically flushed to the destination.
An acknowledge is returned in the cycle of the DMA instruction, and the SDMA is only
stalled by an instruction that addresses the peripheral DMA when the previous DMA
access is not over.
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7.2.3.12.3 OnCE and Real-Time Debug
The On-Chip Emulation block (OnCE) is the debug interface to the SDMA.
It supports the access to all core internal devices (registers, memory, and so on), and
provides a set of mechanisms that control the core. The OnCE is accessed by JTAG ports
at the chip's board level, or by the host via its peripheral bus.
To reduce the size of the hardware material involved, all tasks supported by the OnCE are
performed on the SDMA core. The architecture of the SDMA OnCE is relatively simple
and very flexible.
The commands supported by the SDMA OnCE are listed in the following sections.
7.2.3.12.3.1 Memory and Register Access
A set of mechanisms is provided to access SDMA memory and register locations. Both
reading and writing are allowed. The access is supported if the processor is in debug
mode.
Those registers can also be accessed through the Arm platform Control interface when
the OnCE is controlled by the Arm platform, as described in the "Using BP" section.
7.2.3.12.3.2 Hardware Breakpoints
An event detection unit is implemented to support memory breakpoints. The unit watches
the data exchanged between the SDMA memory bus and the core.
A debug request is sent to the core when matching conditions occur. The unit supports
mixed conditions based on address range, access type, and data value. Event detection
unit configuration registers are memory mapped in the SDMA space (see Arm platform
Channel 0 Pointer (SDMAARM_MC0PTR)): You can modify them through a regular
memory access or the Arm platform control interface.
7.2.3.12.3.3 Watchpoints
One output pin is provided to monitor matching trigger conditions that are defined in the
event detection unit.
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7.2.3.12.3.4 Software Breakpoints
The SDMA instruction set contains a software breakpoint. Upon executing a software
breakpoint instruction, the core suspends normal execution and enters debug mode.
No hardware step execution mode is implemented in the OnCE, but this feature may be
implemented at the software level with this instruction.
7.2.3.12.3.5 Core Control
Commands are provided to monitor and control processor activity. You can halt the core,
rerun the core from another address location, and get processor status.
Any hardware breakpoint on the instruction bus is not supported, but this feature may be
implemented by inserting a software breakpoints program.
7.2.3.13 The OnCE Controller
The OnCE controller receives commands from the Arm platform or from the JTAG
controller. Each command is interpreted before being sent to the core.
7.2.3.13.1 OnCE Commands
A small set of commands supports the communication between the OnCE and the
external world.
This command set enables you to perform any of the following tasks: control processor
activity, save core context, and execute an SDMA instruction from the OnCE. Combined
together, these tasks perform more complex commands.
A full OnCE command contains a 4-bit instruction (the OnCE command opcode) and a
variable length data field (the OnCE data). During command execution, the OnCE data is
transferred in a OnCE internal register before being exchanged with the SDMA. Some
data values are also exported. This mechanism creates a link between the processor and
the external world. Nine commands are defined: The following table presents their
formats.
Table 7-45. OnCE Command Opcode Values
Instruction Name Action Register Data Mode
Opcode Field Size
0000 rstatus Reads the OnCE status register STATUS 16-bit normal/debug
0001 dmov Updates general register GReg1 GREG1 32-bit debug
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Table 7-45. OnCE Command Opcode Values (continued)
Instruction Name Action Register Data Mode
Opcode Field Size
0010 exec_once Runs the instruction from the SDMA INSTRUCTION 16-bit debug
instruction register
0011 run_core Returns to normal execution BYPASS 1-bit debug
0100 exec_core Returns to normal execution via a jump INSTRUCTION 16-bit debug
instruction that specifies the new address
0101 debug_rqst Stops the core after execution of current BYPASS 1-bit normal
instruction
0110 rbuffer Reads the real time buffer RTB 32-bit normal/debug
0111-1110 reserved Reserved BYPASS 1-bit normal/debug
1111 bypass Bypasses TARM platform controller BYPASS 1-bit normal/debug
Each instruction corresponds to a specific action performed on the OnCE. The nature of
the associated data field is clearly identified. The dmov command is followed by a 32-bit
data value (which is a data value for the SDMA); the exec_once and the exec_core
commands are followed by a 16-bit data value (which is an instruction for the SDMA);
the rstatus command is followed by a 16-bit control value (which is the content of the
OnCE status register); the rbuffer command is followed by a 32-bit data value. The
debug_rqst and the run_core commands are followed by a single bit data field (this is a
bypass value). Finally, the bypass instruction enables the SDMA JTAG TAP controller to
be daisy-chained with another JTAG TAP controller. This is a JTAG-only feature. The
set of commands is simple, but enables you to perform any possible task on the SDMA
during a debug process.
7.2.3.13.2 Sending Commands to the OnCE Controller
The JTAG access is the standard access to the OnCE, but sometimes the JTAG is not
available to fix some bugs (if the chip is in production for instance), an additional access
is then required. Therefore, one Arm platform access to the OnCE is provided.
7.2.3.13.2.1 Using the JTAG Interface
A serial access is performed through the five JTAG pins TCK, TRST, TMS, TDI, and
TDO. A Test Access Port controller is provided to decode the TMS control signal.
It produces shift-enable signals (shift_ir and shift_dr), and updates enable signals
(update_ir and update_dr). It is fully compliant with the IEEE 1149.1 testability (JTAG)
standard.
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During the shift_ir state, the command opcode is shifted into the OnCE controller (for
example, the signal from the TDI pin is shifted into the command register and the TDO
pin receives the signal shifted out). After transferring the four bits of the command, an
update_ir signal is asserted and the command is decoded. The target data register is now
clearly identified and the corresponding control signal is produced, as follows: bypass
enable signal (bp_en), instruction enable signal (inst_en), data enable (data_en), and
status enable signal (stat_en).
During the shift_dr state, the TDI signal is shifted into one of the following target
registers: bypass register (1 bit), SDMA instruction register (16 bits), SDMA data register
(32 bits), or OnCE status register (16 bits). The TDO pin is connected to the output of the
selected register to receive the signals shifted out.
The JTAG access is disabled when the Arm platform access is enabled.
7.2.3.13.2.2 Using the Arm platform
The Arm platform access to the OnCE is not the standard access, but it is required if the
JTAG is not available.
For example, if the SDMA ROM is out of use on a chip in production, and the Arm
platform needs to download new code and restart the SDMA, the OnCE can easily
perform this operation. This type of debug operation justifies the use of an Arm platform
access to the OnCE.
To drive the OnCE, the Arm platform uses some registers contained in the Arm platform
Control block of the SDMA. These registers are accessed through the Arm platform
peripheral bus. Most of these registers are connected to another register in the OnCE
controller. Thus, accessing one of these registers is equivalent to accessing the associated
register in the OnCE controller.
The set of registers in the Arm platform Control block is listed below:
• ONCE_ENB register (1 bit, read/write)-This 1-bit register enables the Arm platform
access to the OnCE. When this bit is set, the signals from the JTAG are ignored.
When it is cleared, all writing operations to the following registers through the Host
Control interface are ignored. This register is reset on a JTAG reset.
• ONCE_CMD register (4 bits, read/write)-This 4-bit register receives the command
opcode. It is connected to the command register in the controller. A write access to
this register causes the associated command to be executed on the OnCE. For
example, after writing "0001" in this register, a dmov command is executed.
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NOTE
On the Arm platform side, the rstatus and bypass commands are
not supported. This register is reset on a JTAG reset.
• ONCE_DATA register (32 bits, read/write)-This 32-bit register is connected to the
SDMA data register. This register is used when executing a dmov or rbuffer
command.
NOTE
Before requesting a dmov command, the 32-bit data to transfer
must be written in the ONCE_DATA register. At the end of the
execution, the register is updated with GReg1 former value.
This register is reset on a JTAG reset.
• ONCE_INSTR register (16 bits, read/write)-This 16-bit register is connected to the
SDMA instruction register. This register is used when executing an exec_core or an
exec_once command.
NOTE
Before requesting an exec_core or an exec_once command, the
appropriate instruction must be written in the ONCE_INSTR
register. This register is reset on a JTAG reset.
• ONCE_STAT register (16 bits, read only)-A read access to the ONCE_STAT
register returns the content of the OnCE status register (OSTAT). This register is
read only.
• The bypass register is not useful when the Arm platform controls the OnCE,
therefore no register is defined in the Arm platform Control block to access the
bypass register.
7.2.3.13.2.3 Conflicts Between the JTAG and the Arm platform Accesses
When Arm platform access to the SDMA OnCE is enabled (that is, when the bit in the
ONCE_ENB register is set), the JTAG access is disabled. This guarantees that the block
is not accessed at the same time on both sides.
It is possible to check whether the JTAG access to the SDMA OnCE is enabled from the
JTAG port. When the JTAG access is disabled, the SDMA TDO always returns 1. The
check requires the following steps:
• Execute a dmov command from debug mode (with neither 0xffffffff nor 0x0 as dmov
value: 0x5a5a5a5a is good).
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• Execute another dmov command (the value here is not important).
• The returned value from the latter dmov command should be the original one if the
JTAG access is enabled; if it is 0xffffffff instead of the original input value, this
means the JTAG access is disabled.
7.2.3.13.3 Executing a Command from the OnCE
All the commands defined in OnCE Commands can be accessed through the JTAG. The
Arm platform can access all these commands except the rstatus command.
On the Arm platform side, the OnCE status is directly accessed by reading the
ONCE_STAT register.
7.2.3.13.3.1 Nature of the Commands
Two types of commands may be distinguished. First, there are two commands that do not
interact with the core: rstatus and rbuffer. Those commands may be requested at any
time: They do not depend on the core status.
NOTE
Each of these commands exports a data value or a status value
from the SDMA.
There are also commands that interact with the core: dmov, run_core, exec_core,
exec_once, and debug_rqst. These commands are core status dependent, as follows:
• During user mode only the debug_rqst is taken into account.
• During debug mode, all these commands are taken into account except the
debug_rqst. For example, an exec_once command requested while not in debug
mode has no effect.
7.2.3.13.3.2 Execution Request
The SDMA starts executing a task in debug mode when requested by the OnCE
controller. The execution starting time depends on the type of access used to
communicate with the OnCE.
If the JTAG is used, the request is send after decoding the update_dr state in the TAP
controller. Therefore, always cross this state when sending a command through the
JTAG. If the OnCE is driven from the Arm platform side, the request is sent after
detecting a write access to the ONCE_CMD register. All the registers involved in this
operation must be loaded first.
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The following is an example of an exec_core command execution from the Arm platform
side: After writing '010' in the ONCE_CMD register, the OnCE controller asks the
SDMA to execute the instruction contained in the ONCE_INSTR register. The
instruction involved should be available in the ONCE_INSTR register before the
beginning of the execution.
7.2.3.13.3.3 Command Execution
The following list shows the commands and details how each command is executed:
• rstatus command execution-The rstatus command exports the content of the OnCE
status register (OSR). If the JTAG is used, the status information is captured in the
OnCE status register during the capture_dr state, and shifted out after 16 TCK clock
cycles in the shift_dr state. The rstatus command is not supported on the Arm
platform side, but a status register is provided instead. The rstatus may be performed
in both debug and user modes.
• dmov command execution-The dmov command accesses SDMA internal registers.
Executing a dmov instruction exchanges the 32-bit data values between the SDMA
data register and the general register GReg[1].
• If the JTAG is used, the content of GReg1 is captured in the SDMA data register
during the capture_dr state, then it is shifted out after 32 TCK clock cycles in the
shift_dr state. During the update_dr state, GReg1 is updated with the new, shifted-in
32-bit data value. If the OnCE is driven from the Arm platform side, the data values
contained in GReg1 and the SDMA data register are exchanged after detecting a
write access to the ONCE_CMD register. The ONCE_DATA register must therefore
be loaded first.
• exec_once command execution-The exec_once command executes the instruction
loaded in the SDMA instruction register. The command may only be requested from
debug mode. The SDMA returns to debug mode at the end of the execution.
• Change of flow instructions as well as instructions that may cause a context switch
are not supported: The comprehensive list comprises done/yield/yiedge (except done
5), BF, BT, BSF, BDF, JMP, JSR, JMPR, JSRR, RET, and LOOP, as well as all the
illegal instructions.
No other command should be requested before the SDMA returns to debug mode.
The SDMA status (for example, whether it is in debug mode or not) can be detected
by polling with the rstatus OnCE command, monitoring the debug_mode pin, or
checking the OnCE Status Register (SDMAARM_ONCE_STAT) register via the
Arm platform control interface.
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NOTE
Most of the instructions are single-cycle, which omits the
step of polling the status. Loads and stores to DMA units
are typical instructions that might require this polling.
If the JTAG is used, the 16-bit instruction is shifted in the SDMA instruction register
after 16 TCK clock cycles in the shift_dr state. A request is sent to the core when the
update_dr state is decoded in the TAP controller. If the OnCE is driven from the Arm
platform side, the request is sent to the SDMA when detecting a write access to the
ONCE_CMD register. The ONCE_INSTR register must be therefore be loaded first.
• run_core command execution-The run_core command leaves debug mode and
resume normal program execution. The next instruction executed is the last
instruction decoded before entering debug mode. Be sure to restore core context
before re-running the core. This procedure is detailed in Restoring the Context.
• If the JTAG is used, a 1-bit bypass value is shifted in the bypass register in the
shift_dr state. The SDMA is rerun when the update_dr state is decoded in the TAP
controller. If the OnCE is driven from the Arm platform side, the core is rerun when
detecting a write access to the ONCE_CMD register.
• exec_core command execution-The exec_core command resumes program execution
from any address. The 16-bit instruction provided with the exec_core overwrites the
last instruction decoded before entering debug mode. This command is designed to
support change of flow instructions, so that a program execution can be restarted
from any address. After executing an exec_core command, the SDMA leaves debug
mode. The exec_core command is usually used with a jmp instruction.
• If the JTAG is used, the 16-bit branch instruction is shifted in the SDMA instruction
register after 16 TCK clock cycles in the shift_dr state. The SDMA is rerun when the
update_dr state is decoded in the TAP controller. If the OnCE is driven from the Arm
platform side, the SDMA reruns when detecting a write access to the ONCE_CMD
register. The ONCE_INSTR register must therefore be loaded first. For example, to
restart the SDMA from the program address 0x100, the instruction loaded should be
a jump to address 0x100 instruction.
• debug_rqst command execution-The debug_rqst command puts the SDMA in debug
mode. If the JTAG is used, a 1-bit bypass value is shifted in the bypass register
during the shift_dr state. A debug request is sent to the SDMA when the update_dr
state is decoded in the TAP controller. If the OnCE is driven from the Arm platform
side, the debug request is sent when detecting a write access to the ONCE_CMD
register. When the SDMA is already in debug mode, this command is simply
ignored.
• rbuffer command execution-The rbuffer command exports the content of the real
time buffer (RTB). If the JTAG is used, the content of the real time buffer (RTB) is
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captured in the SDMA data register during the capture_dr state. The register is
completely shifted out after maintaining the shift_dr state during 32 TCK clock
cycles. If the OnCE is driven from the Arm platform side, the content of the RTB is
captured in the ONCE_DATA register after detecting a write access to the
ONCE_CMD register.
• bypass command execution-This command is only available from the JTAG
interface. It enables daisy-chaining of the SDMA JTAG TAP controller with other
JTAG TAP controllers. This command does not change the SDMA state and can be
executed in any mode (run, debug, or sleep). It selects the bypass register of the TAP
controller.
7.2.3.13.4 Registers Descriptions
See SDMACORE, and SDMAARM, for detailed information on each register.
7.2.3.13.4.1 Event Cell Counter Register (ECOUNT)
The event cell counter register is a 16-bit register that contains the number of times minus
one that an event detection occurs before generating a debug request.
This register should be written before attempting to use the event detection counter
during an event detection process. The event cell counter register is cleared on a JTAG
reset.
7.2.3.13.4.2 Event Cell Address Registers (EAA or EAB)
The event cell contains two address registers-the event cell address register (a), called
EAA, and the event cell address register (b), called EAB. Every address register is a 16-
bit register that stores a user-defined address value. This value computes one of the
following address conditions: addra_cond or addrb_cond. Every address register is
cleared on a JTAG reset.
7.2.3.13.4.3 Event Cell Address Mask Register (EAM)
The event cell address mask register is a 16-bit register that contains a user-defined
address mask value. This mask is applied to the address value latched from the memory
address bus before comparing addresses.
NOTE
There is a common address mask value for the two address
comparators. If bit i of this register is set, then bit i of the
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address value latched from the memory bus does not influence
the result of the address comparison. The event cell address
mask register is cleared on a JTAG reset.
7.2.3.13.4.4 Event Cell Data Register (ED)
The event cell data register is a 32-bit register that contains a user-defined data value.
This data value is an input for the data comparator, which generates the data_cond
condition.
The event cell data register is cleared on a JTAG reset.
7.2.3.13.4.5 Event Cell Data Mask Register (EDM)
The event cell data mask register is a 32-bit register that contains a user-defined data
mask value. This mask is applied to the data value latched from the memory bus before
comparing data.
Setting bit i of the event cell data mask register means that bit i of the data value latched
from the address bus does not influence the result of the data comparison. The event cell
data mask register is cleared on a JTAG reset.
7.2.3.13.4.6 Real Time Buffer Register (RTB)
The real Time Buffer register is a 32-bit register that stores and retrieves run-time
information without putting the SDMA in debug mode.
Refer to Real Time Buffer for more details.
7.2.3.13.4.7 Event Control Register (ECTL)
The event cell control register is a 16-bit register that defines cell event occurrence
conditions.
The event cell control register is cleared on a JTAG reset. See also OnCE Event
Detection Unit for more details.
7.2.3.13.4.8 Trace Buffer (TB)
The Trace Buffer register retrieves the information in the Trace Buffer.
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See Trace Buffer for more details.
7.2.3.13.4.9 OnCE Status Register (OSTAT)
The OnCE status register is a 16-bit register that contains processor and event detection
unit status. The OSTAT is a read-only register.
Refer to OnCE Status Register (SDMAARM_ONCE_STAT) for detailed description of
the individual fields in the OSTAT register.
The following figure shows the OSTAT structure.
Table 7-46. OnCE Status Register (OnCE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PST[3:0] RCV EDR ODR SWB MST ECDR[2:0]
Where PST[3:0] is the SDMA core state, RCV is set when the real-time buffer (RTB) is
modified. EDR, ODR, and SWB are set, respectively, when the SDMA has entered debug
mode because of an external debug request, a OnCE debug_rqst command, or a software
breakpoint. MST is set when the OnCE is controlled from the Arm platform control
interface, and when ECDR is a three-flag set that shows the event cell condition(s) that
put the core in debug mode. The OSTAT never provides more than one reason for
entering debug mode.
There are two ways of accessing OSTAT content, as follows:
1. Send an rstatus command to the OnCE controller through the JTAG, or read the
ONCE_STAT register through the Arm platform access. Executing the rstatus
command through the JTAG can be performed in both user and debug modes.
2. Perform an SDMA read access to the location in the SDMA core memory map
(OSTAT register) debug mode using the exec_once command. With this method of
access, the SDMA state reflected by the PST (processor status bit) is always DATA.
The register may also be accessed by a running application.
7.2.3.13.5 JTAG Interface Requirements
Because the signals received from the JTAG (running on TCK) are transferred to the
OnCE controller (running on the SDMA clock), a synchronization mechanism is
required.
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7.2.3.13.5.1 TCK Speed Limitation
In the JTAG top-level layer, the TDO signal is always captured on a TCK falling edge.
To guarantee a stable TDO signal from the SDMA during this operation, a falling edge
detection is performed on TCK.
Before being latched in the I flip-flop (see Figure 7-11) on TCK falling edge, the TDO
signal must be stable at the input of the flip-flop. This condition is verified if the TCK
period is superior to the following delay:
worst-case edge detection delay + negative-edge signal propagation delay + JTAG top-
level logic propagation delay
The frequency relationship, TCK < CLK/8, limitation guarantees that all operations are
performed as expected.
7.2.3.13.5.2 Synchronization Implementation
The figure found here shows the synchronization mechanism.
Flip-flops tck0, tck1, and tck2 perform falling- and rising-edge detections on TCK. They
generate the posedge_detected and negedge_detected nets that are used to sample the TDI
and TMS inputs into the respective tdi and tms flip-flops, and update the tdo flip-flop to
yield the TDO output. In the design, the only signal that might go metastable is the output
of the tck0 flip-flop. This signal is captured in the tck1 flip-flop and no logical operation
is performed on it to minimize a metastability propagation risk.
The TDI and TMS flip-flops also cannot go metastable: The propagation time of the
rising-edge detection signal through tck0, tck1, and tck2 guarantees that the TDI and
TMS inputs are stable when captured in the TDI and TMS flip-flops.
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'0' tms
'1' tdi TMS/TDI internals
TMS/TDI
posedge_detected
tck0 tck1 tck2 negedge_detected
TCK
tdo '0'
TDO
'1' TDO internal
Figure 7-11. OnCE Synchronization Layer
The following figure shows synchronization timings. It takes three CLK clock cycles to
synchronize TDI on the SDMA clock.
TCK
CLK
posedge_det
TDI
internal TDI
negedge_det
TDO
tdo set-up tdo set-up
Figure 7-12. Synchronization Timings
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7.2.3.13.5.3 JTAG Controller Start-Up Recommended Procedure
To ensure correct TAP controller initialization, it is recommended to use the following
procedure:
1. Assert JTAG reset TRSTB (for example, set low).
2. Set TMS low.
3. Wait for 1 TCK clock.
4. Release JTAG reset TRSTB (for example, set high).
5. Wait for a minimum of five TCK cycles.
7.2.3.14 Using the OnCE
This section provides the elements necessary to run the OnCE during a debug process.
In addition to the basic set of commandsdescribed in OnCE Commands, more complex
commands can be built to meet users' requirements.
7.2.3.14.1 Activating Clocks in Debug Mode
For power consumption issues, some clocks in the SDMA are disabled when not needed.
This is the case for instances when the SDMA is in sleep mode. Clock gating
management depends on the interface used to control the OnCE.
• For the JTAG access, the SDMA clock gating must be turned off via the
clk_gating_off input.
• For the Arm platform access, the SDMA clock gating is automatically turned off
when the Arm platform access is enabled (see OnCE Enable
(SDMAARM_ONCE_ENB)).
7.2.3.14.2 Getting the Current Status
Most of the commands the OnCE supports have an impact on the status of the SDMA.
It is not permissible to request the execution of an instruction on the SDMA from the
OnCE while the SDMA is not in debug mode. Such a violation may cause unpredictable
behavior, and it might be necessary to reset the SDMA.
Therefore, the value of the PST bits provided in the OnCE status register should always
be checked before sending any request to the SDMA.
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7.2.3.14.3 Methods of Entering Debug Mode
A debug request may be asserted at any time, but it is not always taken into account
immediately. Debug mode cannot be entered in the middle of an instruction, or during the
save or restore states of a context switch.
The request is ignored when the core is already in debug mode. Refer to Figure 7-4,
which shows all possible transitions to the debug state, as there are several ways to enter
debug mode.
7.2.3.14.3.1 External Debug Request During Reset
To enter debug mode after exiting reset, the external debug line has to be maintained
high. This line is handled by the JTAG top-level block.
NOTE
The SDMA detects the debug requests only if the SDMA clock
is running (see Activating Clocks in Debug Mode). The debug
request line should be not be maintained high when the SDMA
is in debug mode.
NOTE
The debug_rqst command (from the OnCE command set) is not
supported during system reset.
7.2.3.14.3.2 Debug Request During Normal Activity
During normal activity, the SDMA enters debug mode when the following is true:
1. If the debug request line from the JTAG top-level is asserted, or
2. If the OnCE controller receives a debug_rqst command.
The debug_rqst command can be sent by the JTAG access or by an access on the
Arm platform side (if the Arm platform access is enabled).
7.2.3.14.3.3 Software Breakpoint Instruction
The SDMA enters debug mode at the end of the execution of a software breakpoint
instruction. This instruction must be inserted in program flow executed by the core.
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7.2.3.14.3.4 Event Detection Unit Matching Condition
If the event detection is enabled, a debug request is sent to the core after detecting a
matching condition on the SDMA memory bus.
See OnCE Event Detection Unit for more details.
7.2.3.14.4 Executing Instructions in Debug Mode
The OnCE supports a mechanism to execute instructions in debug mode. If the SDMA is
in debug mode, then the exec_once command can be used to execute an SDMA
instruction from the OnCE controller. The SDMA returns to debug mode at the end of
each execution.
Some instructions are not supported by the exec_once command: done/yield/yiedge
(except done 5), BF, BT, BSF, BDF, JMP, JSR, JMPR, JSRR, RET, and LOOP, as well
as all the illegal instructions are not supported.
NOTE
While instructions are executed in debug mode from the OnCE,
the program counter of the SDMA is not incremented.
7.2.3.14.5 Command Sequences Examples
This section provides examples of command sequences that run the SDMA in debug
mode. These sequences are available for both the Arm platform and JTAG accesses.
The following presents the syntax used in this section. The data field provided with each
command is put in parenthesis with the command name. A '-' is used if the data field
provided is a don't care value.
my_command(data_field); // executing my_command with a data field
my_command(-); // executing my_command with a don't care data field
The value returned by the command (if there is one) is referred by an assignment. In case
the value returned by the command is not used, the assignment is omitted. For an Arm
platform access, the value returned (it is always a data value) is obtained by reading back
into the SDMA data register.
data_out = my_command(data_in); // returning a data value
To clarify the syntax, the instructions' opcodes are referred to by their names. In practice,
use the corresponding 16-bit encoding.
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7.2.3.14.5.1 Getting the SDMA Status
NOTE
Before executing any command that affects the SDMA (like
dmov or exec_once), check that the SDMA is in debug mode.
Use the following snippet:
rstatus(); // read SDMA status until the SDMA is in debug mode
...
rstatus();
If the SDMA is not in debug mode, then a debug request must be generated. In this case,
the SDMA enters debug mode at the end of the execution of the current instruction. Use
this snippet:
debug_rqst(-); // debug request
In the following sections, it is assumed that the SDMA was successfully put into debug
mode.
7.2.3.14.5.2 Saving the Context
The first debug task is to save the SDMA context, which is the content of the eight
general-purpose registers, the loop and PC-related registers, and the flags.
Use the general register GReg[1] as an intermediate register to export the entire context
of the SDMA.
The following example shows how to save GReg[0], GReg[1], GReg[2] and GReg[3].
The sequence of commands used to export additional general registers is very similar to
this.
Save GReg[0], GReg[1], GReg[2], and GReg[3]
GReg1_data = dmov(-); // the value exported is the content of
GReg[1]
exec_once("mov GReg1,GReg0"); // puts the content of GReg[0] into
GReg[1]
GReg0_data = dmov(-); // the value exported is the content of
GReg[0]
exec_once("mov GReg1, GReg2"); // puts the content of GReg[2] into
GReg[1]
GReg2_data = dmov(-); // the value exported is the content of
GReg[2]
exec_once("mov GReg1, GReg3"); // puts the content of GReg[3] into
GReg[1]
GReg3_data = dmov(-); // the value exported is the content of
GReg[3]
Get the value of the internal flags (SF, DF, T, and LM), of the loop related registers (EPC
and SPC), and of the PC-related registers (PC and RPC). Use a done 5, which is the
formatting instruction dedicated to the debug. This instruction formats the flags and the
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values contained in the registers. It also writes the resulting values into the channel
context memory. It should not be used when entering debug from the IDLE state (for
example, with no active channel script running on the SDMA), because it will update a
channel context that may belong to any channel.
exec_once("done 5"); // formatting the value of flags and registers
At this point, the channel context should be up-to-date in memory, and debug operations
should now be possible. However, the context can be exported with the following
instructions:
Exporting the Context
dmov(ctx_base_addr); // loading GReg[1] with the channel
context base address
exec_once("ld GReg0,(GReg1,0)"); // get RPC-PC into GReg0
exec_once("ld GReg1, (GReg1,1)"); // get SPC-EPC into GReg1
Loop_data = dmov(-); // read back the value of Loop registers
exec_once("mov GReg1, GReg0"); // puts the PC info into GReg1
PC_data = dmov(-); // reads back the content of the PC registers
After this sequence of operations, the entire SDMA context is exported via the OnCE.
7.2.3.14.5.3 Restoring the Context
At this point in the operation, restore the context of the SDMA. It can be different from
the original context located in memory, and the content previously saved into the
debugging application via the OnCE.
The example found hereshows how it is possible to modify the current channel context.
Modifying the Current Channel Context
dmov(Loop_data); // put Loop former value into GReg[1]
exec_once("mov GReg0, GReg1"); // copy to GReg[0]
dmov(PC_data); // put PC former value into GReg[1]
exec_once("mov GReg2, GReg1"); // copy to GReg[2]
dmov(ctx_base_addr); // put channel context base address into
GReg[1]
exec_once("st GReg0, (GReg1,1)"); // restore Loop context
exec_once("st GReg2, (GReg1,0)"); // restore PC context
Once the context in memory is the desired context (with or without applying the previous
instruction sequence), it can be restored to the real PC and loop registers in the SDMA
core:
exec_once("cpShReg"); // restore flags and PC & loop related registers
After this command, the SDMA core PC, RPC, SPC, EPC registers, as well as the flags
contain the same data as what is stored in the context RAM for the current channel.
The following example shows how to restore the context of general registers GReg[0],
GReg[1], GReg[2] and GReg[3].
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Restoring the General Register Context
dmov(GReg3_data); // put GReg[3] restore value in GReg[1]
exec_once("mov GReg3, GReg1"); // restore GReg[3]
dmov(GReg2_data); // put GReg[2] restore value in GReg[1]
exec_once("mov GReg2, GReg1"); // restore GReg[2]
dmov(GReg0_data); // put GReg[0] restore value in GReg[1]
exec_once("mov GReg0, GReg1"); // restore GReg[0]
dmov(GReg1_data); // restore GReg[1]
At this point, it is possible to restart the normal program execution.
NOTE
Every SDMA core general register value can be modified by a
mov instruction, which makes modification of these registers
easy during debug. Unfortunately, there is no such instruction
as a mov to directly modify the contents of either PCU register
or flag (PC, RPC, SPC, EPC, T, LM, SF, or DF). The cpShReg
instruction is meant to provide a means for changing these
register contents via the context memory.
7.2.3.14.5.4 Accessing the Memory
In the example shown here, it is assumed that the SDMA context is entirely saved. If true,
it is permissible to modify the general purpose registers during debugging activity.
To perform a memory read access, the target address is stored via the OnCE in GReg[1],
then the load instruction is executed on the SDMA (the data loaded from the memory
overwrites the address contained in GReg[1]), and then the result value is read back via
the OnCE.
macro READ: dmov(target_addr); // put the target
address in GReg[1]
exec_once("ld GReg1,(GReg1,0)"); // execute the
load instruction
res_data = dmov(-); // exports the result
data value
For a memory write access, the target address is written in GReg[0], and the value to
store is written in GReg[1]. Then the store instruction is executed on the SDMA.
macro WRITE: dmov(target_addr); // puts the
target address in GReg[1]
exec_once("mov GReg0,GReg1"); // puts the target
address in GReg[0]
dmov(target_data); // puts the target
data in GReg[1]
exec_once("st GReg1,(GReg0,0)"); // performs the
store operation
This sequence is shown as an example; however, many other sequences are possible.
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NOTE
This sequence of commands can also be applied to memory-
mapped registers.
7.2.3.14.5.5 Resuming Program Execution
Before resuming program execution, it is assumed that the SDMA context is properly
restored. There are two ways to restart the SDMA.
Start by executing the last instruction fetched before entering debug mode, as follows.
run_core(-); // resume execution from where we stopped before
If necessary, restart the execution from a different address. In this case, use the exec_core
command. The data field provided with this command must be the encoding of a jump
instruction.
exec_core("jmp start_addr"); // rerun the SDMA from another address
In these two examples, the SDMA exits debug mode and keeps executing the code
fetched from the memory.
7.2.3.14.5.6 Single Stepping in RAM
To execute a program step-by-step from the RAM, insert software breakpoints in the
program flow at appropriate places so that the SDMA only executes one instruction
before returning to debug mode.
First, read the next instruction to execute in the RAM. Then, depending on the value of
this instruction, compute the address where a software breakpoint instruction should be
inserted. The instruction at the corresponding address must be saved, and, the software
breakpoint instruction is inserted. After restarting the SDMA, there is only one
instruction executed before meeting the software breakpoint.
The following example shows the macro functions READ and WRITE, which correspond
to the sequence of commands (described above) used to access the memory.
NOTE
The data read from the memory are 32-bit values, while the
instructions are 16-bit values only. This is why it is best to only
use addresses divided by two when accessing the memory.
READ and WRITE Macro Functions
next_instr = READ(run_addr/2); // read the next instruction to execute
// the tool now has to compute the address where the breakpoint
// instruction should be inserted, this address is the "bkpt_addr"
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instr_save = READ(bkpt_addr/2); // save the instruction before
overwriting
STORE("bkpt instruction",bkpt_addr/2); // store the bkpt instruction
in memory
exec_core("jmp run_addr"); // rerun the SDMA
rstatus(-); // wait for the SDMA to enter debug mode
...
rstatus(-);
STORE(instr_save,bpkt_addr/2); // restore the instruction
overwritten
In case of branched conditional instructions, a breakpoint instruction should be written at
the two possible target addresses.
7.2.3.14.5.7 Single Stepping in ROM
No single-step mechanism is supported in ROM. The program code can be loaded in the
RAM, where the single-step mechanism can be executed.
7.2.3.14.6 OnCE Event Detection Unit
The event detection unit watches signals from the data memory bus (DMBUS), which the
SDMA core uses to access its RAM, ROM, and memory mapped registers.
A debug request is sent to the OnCE controller when user-defined conditions on address
and/or data values are true.
DMBUS Event detect Event event Event dbg_rqst
Detection Cell Detection
Cell Counter Logic
Figure 7-13. Event Detection Unit
A counter, provided with the detection cell, is decreased after an event detection. A
debug request is sent to the core only when the counter reaches the value of 0. It is
possible to disable the use of the counter if a debug request has to be generated after each
event detection.
The event cell is the basic block that supports hardware breakpoints on an address value
and/or data values coming from the SDMA memory bus. The trigger condition that
generates the debug request is a mixed condition based on those values.
The following figure shows the event cell architecture. The event cell contains the
address (stored in the memory address register) and the data (stored in the memory data
register) used during the last memory access. There are some user-defined reference
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values located in memory mapped registers-the event cell addresses, the event cell
address mask, the event cell data, and the event cell data mask. These registers are
accessed by standard load/store instructions just like regular memory locations.
Event Cell Control Register
Event Cell Data Register Data Comparator Memory Data Register
Event Cell Data Mask Register data_cond
Event Cell Address Register (a) Address Comparator (a) Memory Access Type Register
Event Cell Address Mask Register addra_cond
Event Cell Address Register (b) Address Comparator (b) Memory Access Register
addrb_cond
Logic
addr_cond
Logic
event_detect
Figure 7-14. Event Cell Architecture
To define a memory breakpoint, three conditions are taken into account: The first two
conditions are comparisons of the current memory address with user-defined reference
addresses (these conditions are called addressA and addressB). The third condition
consists of a comparison between the data received on the DMBUS and a user-defined
reference data (this condition is called data). An intermediate address condition is set to
express a dependency between addressA and addressB conditions.
7.2.3.14.7 Clock Gating and Reset
This section details how to use the clocks and handle the reset signals.
7.2.3.14.7.1 Clocks
Because the SDMA uses clock gating to save power, it is necessary to disable the clock
gating and force the clocks to be enabled when using the OnCE.
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When the OnCE is accessed through its JTAG interface, clock gating must be disabled
outside the SDMA via a dedicated SDMA input port clk_gating_off. The reason why
detection is not performed automatically by the SDMA internal hardware is that it would
cost power to monitor activity on the JTAG interface.
When the OnCE is accessed through the Arm platform Control interface, clock gating is
automatically turned off. This is done when bit 0 of the ONCE_ENB register (see OnCE
Enable (SDMAARM_ONCE_ENB)) is set. A write access to this register is possible
even when the OnCE clock is not running. If the Arm platform access is used, the bit in
the ONCE_ENB register must be set before any attempt to access any other OnCE
register.
7.2.3.14.7.2 Resets
The OnCE reset is different from the SDMA main reset.
Normally, activating the SDMA reset while keeping the OnCE reset inactive (when
possible) enables you to reset the core without having to reprogram the OnCE.
7.2.3.14.8 Real Time Features
To rebuild the skeleton of a program execution, it is necessary to store the addresses of
the program instructions where jumps are taken: A trace buffer is therefore provided. A
real time buffer has also been added to receive data values written during a program
execution.
The content of this register may be exported through JTAG ports without stopping the
core.
7.2.3.14.8.1 Trace Buffer
The Trace Buffer is a 32-stage buffer that contains appropriate information to identify the
32 last changes of flow detected during a program execution.
The following figure shows an overview of the Trace Buffer.
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input change of flow addresses
Trace buffer cell #0
Trace buffer cell #1
shift
...
Trace buffer cell #30
Trace buffer cell #31
output change of flow addresses
Figure 7-15. Trace Buffer
Each cell of the trace buffer contains two reference addresses and a flag. The flag is set
when the addresses stored in the cell correspond to a valid change of flow; otherwise, the
flag is cleared. The three most significant bits are unused.
After every change of flow detection, the address of current instruction and the address of
the target instruction are stored at the top of the Trace Buffer (cell #0). The flag in the
cell is set to indicate that a valid change of flow was detected. Former cell values are
shifted one level down. The Trace Buffer contains the 32 last changes of flow. All the
flags are reset on a software or a hardware reset, and after each transition from debug
mode to user mode.
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A memory mapped register of SDMA core, the Trace Buffer register (TB), is provided to
read the content of the Trace Buffer. This operation should be done in debug mode.
Performing a read access to the Trace Buffer register returns the content of the bottom of
the Trace Buffer (cell #31). After every read access, the trace buffer is shifted one level
down, and the flag at the top of the trace buffer is cleared.
A typical OnCE command sequence that retrieves the oldest change-of-flow information
is a follows:
exec_once("mov r1, TB"); // stores the oldest change-of-flow in
GReg1
dmov(-); // retrieves GReg1 contents
This sequence requires the SDMA to be put in debug mode.
7.2.3.14.8.2 Real Time Buffer
The Real Time Buffer register (RTB) is a memory mapped register that can be accessed
as a regular memory location by the SDMA core during program execution. This register
is located in the OnCE.
Executing ar rbuffer command (see The OnCE Controller for further details) exports the
content of this register through JTAG ports.
When a write access is performed at the memory location corresponding to the RTB, the
receive flag (for example, the RCV bit) is set in the OnCE Status Register (OSR). This
flag is cleared at the end of the execution of a rbuffer command.
NOTE
Every write access to the RTB memory location updates the
RTB register even if the RCV flag is set. The RTB is cleared on
a JTAG reset.
7.2.3.14.8.3 Emulation Pin
The debug_matched_event emulation pin reflects the matching condition status detected
by the Event Detection Unit.
Since it can be necessary to detect conditions without triggering debug requests, it is
possible to disable the generation of debug requests by the Event Detection Unit and still
have the matching condition available on the emulation pin. This can be done by clearing
the EN flag in the ECTL register.
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7.2.3.14.8.4 Real-Time Debug Outputs
The table found here shows the debug signals that are available at the SDMA boundaries.
Their availability at chip boundaries depends on the project.
Table 7-47. Real-Time Debug Output Pins
Pin Description
debug_core_state[3:0] The core_state bits reflect the state of the SDMA core.
• The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the
data bus (ld or st).
• The "Change of Flow" state is the second cycle of any instruction that breaks the
sequence of instructions (jumps and channel switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a
store on the functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the core idle state); the "after Reset" is
slightly different because no context restoring phase will happen when a channel is
triggered: The script located at address 0 is executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any
corresponding channel: they are used when entering debug mode after reset; the
reason is that it is necessary to return to the "Sleep after Reset" state when leaving
debug mode.
0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Context Switch Saving Channel
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change of Flow in Loop in Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
14 Sleep after Reset
15 Context Switch Restoring Channel
debug_yield Pulse that is active when a yield (done 0) or a yieldge (done 1) instruction is executed.
0-
1 yield/yieldge executed
debug_core_run Active when the SDMA core is executing instructions.
0 Debug or sleep mode
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Table 7-47. Real-Time Debug Output Pins (continued)
Pin Description
1 Run mode
debug_event_channel_sel Indicates if debug_event_channel displays current channel or last received event
0- debug_event_channel[5:0] gives the number of the current channel
1- debug_event_channel[5:0] gives the number of the last received event
debug_event_channel[5:0] Gives the number of any DMA request as soon as it is received or the number of the current
channel.
The value of debug_event_channel_sel indicates if debug_event_channel displays the
current channel or last received event. The signal debug_event_channel_sel must be
observed to determine what information is provided on debug_event_chanel at any given
time.
debug_pc[13:0] Program Counter value; it has a meaning when the core is in run mode.
debug_mode Set when the core is in debug.
0-
1 Core is in debug
debug_bus_error Set when an error was received during a load or a store (ld, st, ldf, or stf instruction) and
registered in SF or DF flag.
0 No error during last load/store
1 Error during last load/store
debug_bus_device[4:0] Indicates the device or functional unit that is accessed by the current instruction. The
debug_bus_device output is always valid when in sleep mode, debug mode, or executing any
instruction that does not access the functional units or the memory mapped devices, "no
access" is output.
0 No access
1 MSA
2 MDA
3 MD
4 MS
5 PSA
6 PDA
7 PD
8 PS
9 RESERVED
10 RESERVED
11 RESERVED
12 RESERVED
13 CA
14 CS
15 Reserved
16 Memory (RAM or ROM)
17 Memory mapped register
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Table 7-47. Real-Time Debug Output Pins (continued)
Pin Description
18 Peripheral #1
19 Peripheral #2
20 Peripheral #3
21 Peripheral #4
22 Peripheral #5
23 Peripheral #6
24 Peripheral #7
25 Peripheral #8
26 Peripheral #9
27 Peripheral #10
28 Peripheral #11
29 Peripheral #12
30 Peripheral #13
31 Peripheral #14
debug_bus_rwb Indicates the direction of the access given by debug_bus_device
0 Write access (st or stf)
1 Read access (ld or ldf)
debug_matched_dmbus Pulse indicating the OnCE event detection unit has detected a match on the data bus during
an access to memory (RAM or ROM), a memory mapped register or a peripheral that is
hooked to the SDMA.
0-
1 data bus match detected
debug_rtbuffer_write Pulse indicating when the real-time buffer is written by the core.
0-
1 RTB was modified
debug_evt_chn_lines[7:0] Eight lines that generate short pulses when DMA requests are received or channels are
(re)started. Every line is controlled through two parameters defined in registers Cross-Trigger
Events Configuration Register 1 (SDMAARM_XTRIG_CONF1) (as described in SDMAARM).
The following two parameters are available for every line:
• CNF-Indicates what is monitored on the line: 0 for a channel start, 1 for a DMA request
reception
• NUM[ 5:0]-Gives the number of the DMA request or channel to monitor
The matched_event emulation pin reflects the matching condition status detected by the
Event Detection Unit. Because it can be necessary to detect conditions without triggering
debug requests, it is possible to disable the generation of debug requests by the Event
Detection Unit and still have the matching condition available on the emulation pin. This
can be done by clearing the EN flag in the ECTL register.
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All real-time debug outputs are disabled by default (for example, they are stuck to 0) to
avoid power consumption when they are not used. They are enabled when bit 11
(RTDOBS) of the Configuration Register (SDMAARM_CONFIG) is set. Signals
provided to the system JTAG controller for SDMA debug mode status will also be
enabled when the clk_gating_off input is asserted.
7.2.4 Instruction Set
7.2.4.1 Instruction Encoding
This section presents a short summary of the instruction codes. All context switch
instructions are listed for information only; they cannot function properly out of the
context switch routine.
x...x - don't care
rrr - destination/source general register
sss - additional source general register
bbb - general register used as address base register
ddddd - address displacement
nnnnn - bit number
uuuuuuuu - function unit command bits
pppppppp - branch displacement (signed)
iiiiiiii - 8-bit immediate
jjj - control bit to clear
ff - flag to clear
00000jjj00000000 - done (done,yield,wait)
00000jjj00000001 - notify
00000xxx00000010 - reserved
00000xxx00000011 - reserved
00000xxx00000100 - reserved
0000000000000101 - softBkpt
0000000100000101 - reserved
0000001000000101 - reserved
0000001100000101 - reserved
0000010000000101 - reserved
0000010100000101 - reserved
0000011000000101 - reserved
0000011100000101 - reserved
0000000000000110 - ret
0000000100000110 - reserved
0000001000000110 - reserved
0000001100000110 - reserved
0000010000000110 - reserved
0000010100000110 - reserved
0000011000000110 - reserved
0000011100000110 - reserved
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000000ff00000111 - clrf ff
0000010000000111 - reserved
0000010100000111 - reserved
0000011000000111 - reserved
0000011100000111 - illegal
00000rrr00001000 - jmpr r
00000rrr00001001 - jsrr
00000rrr00001010 - ldrpc r
00000rrr00001011 - reserved
00000rrr000011xx - reserved
00000rrr00010000 - revb
00000rrr00010001 - revblo
00000rrr00010010 - rorb
00000rrr00010011 - reserved
00000rrr00010100 - ror1
00000rrr00010101 - lsr1
00000rrr00010110 - asr1
00000rrr00010111 - lsl1
00000rrr001nnnnn - bclri r,n
00000rrr010nnnnn - bseti r,n
00000rrr011nnnnn - btsti r,n
00000xxx10000xxx - reserved
00000rrr10001sss - mov
00000rrr10010sss - xor
00000rrr10011sss - add
00000rrr10100sss - sub
00000rrr10101sss - or
00000rrr10110sss - andn
00000rrr10111sss - and
00000rrr11000sss - tst
00000rrr11001sss - cmpeq
00000rrr11010sss - cmplt
00000rrr11011sss - cmphs
0000011011100000 - reserved
0000011011100001 - reserved
0000011011100010 - cpShReg
0000011011100011 - reserved
0000011011100100 - reserved
0000011011100101 - reserved
0000011011100110 - reserved
0000011011100111 - reserved
00000xxx11101xxx - reserved
00000xxx11110xxx - reserved
00000xxx11111xxx - reserved
00001rrriiiiiiii - ldi r,i
00010rrriiiiiiii - xori r,i
00011rrriiiiiiii - addi r,i
00100rrriiiiiiii - subi r,i
00101rrriiiiiiii - ori r,i
00110rrriiiiiiii - andni r,i
00111rrriiiiiiii - andi r,i
01000rrriiiiiiii - tsti r,i
01001rrriiiiiiii - cmpeqi r,i
01010rrrdddddbbb - ld r,(d,b)
01011rrrdddddbbb - st r,u
01100rrruuuuuuuu - ldf r,u
01101rrruuuuuuuu - stf r,u
011100xxxxxxxxxx - reserved
011101xxxxxxxxxx - reserved
011110ffnnnnnnnn - Loop ff flags are reset
01111100pppppppp - bf pc=pc+signed(pppppppp)+1
01111101pppppppp - bt pc=pc+signed(pppppppp)+1
01111110pppppppp - bsf pc=pc+signed(pppppppp)+1
01111111pppppppp - bdf pc=pc+signed(pppppppp)+1
10aaaaaaaaaaaaaa - jmp absolute
11aaaaaaaaaaaaaa - jsr absolute
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7.2.4.2 SDMA Instruction Set
This section describes all the useful instructions from the SDMA set.
Table 7-48. SDMA Instruction List
Instruction Description Page
ADD Addition ADD (Addition)
ADDI Add with Immediate Value ADDI (Add with Immediate Value)
AND Logical AND AND (Logical AND)
ANDI Logical AND with Immediate Value ANDI (Logical AND with Immediate
Value)
ANDN Logical AND NOT ANDN (Logical AND NOT)
ANDNI Logical AND with Negated Immediate ANDNI (Logical AND with Negated
Value Immediate Value)
ASR1 Arithmetic Shift Right by 1 Bit ASR1 (Arithmetic Shift Right by 1 Bit)
BCLRI Bit Clear Immediate BCLRI1 (Bit Clear Immediate)
BDF Conditional Branch if Destination Fault BDF (Conditional Branch if Destination
Fault)
BF Conditional Branch if False Functional Units Programming Model
BSETI Bit Set Immediate BSETI (Bit Set Immediate)
BSF Conditional Branch if Source Fault BSF (Conditional Branch if Source Fault)
BT Conditional Branch if True BT (Conditional Branch if True)
BTSTI Bit Test immediate BTSTI (Bit Test immediate)
CLRF Clear Arm platform flags CLRF (Clear Arm platform flags)
CMPEQ Compare for Equal CMPEQ (Compare for Equal)
CMPEQI Compare with Immediate for Equal CMPEQI (Compare with Immediate for
Equal)
CMPHS Compare for Higher or Same CMPHS (Compare for Higher or Same)
CMPLT Compare for Less Than CMPLT (Compare for Less Than)
cpShReg Update Context of PCU Registers and cpShReg (Update Context of PCU
Flags Registers and Flag)
DONE DONE, Yield DONE (DONE, Yield)
ILLEGAL ILLEGAL Instruction ILLEGAL (ILLEGAL Instruction)
JMP Unconditional Jump Immediate JMP (Unconditional Jump Immediate)
JMPR Unconditional Jump JMPR (Unconditional Jump)
JSR Unconditional Jump to Subroutine JSR (Unconditional Jump to Subroutine
Immediate Immediate)
JSRR Unconditional Jump to Subroutine JSRR (Unconditional Jump to
Subroutine)
LD Load Register LD (Load Register)
LDF Load Register from Functional Unit LDF (Load Register from Functional
Unit)
LDI Load Register with Immediate Value LDI (Load Register with Immediate
Value)
LDRPC Load from RPC to Register LDRPC (Load from RPC to Register)
Table continues on the next page...
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Table 7-48. SDMA Instruction List (continued)
Instruction Description Page
LOOP Hardware Loop LOOP (Hardware Loop)
LSL1 Logical Shift Left by 1 Bit LSL1 (Logical Shift Left by 1 Bit)
LSR1 Logical Shift Right by 1 Bit LSR1 (Logical Shift Right by 1 Bit)
MOV Logical Move MOV (Logical Move)
NOTIFY Notify to Arm platform NOTIFY (Notify to Arm platform)
OR Logical OR OR (Logical OR)
ORI Logical OR with Immediate Value ORI (Logical OR with Immediate Value)
RET Return from Subroutine RET (Return from Subroutine)
REVB Reverse Byte Order REVB (Reverse Byte Order)
REVBLO Reverse Low Order Bytes Reverse Low Order Bytes(REVBLO)
ROR1 Rotate Right by 1 Bit ROR1 (Rotate Right by 1 Bit)
RORB Rotate Right by 1 Byte RORB (Rotate Right by 1 Byte)
SOFTBKPT Software Breakpoint SOFTBKPT (Software Breakpoint)
ST Store Register ST (Store Register)
STF Store Register in Functional Unit STF (Store Register in Functional Unit)
SUB Subtract SUB (Subtract)
SUBI Subtract with Immediate SUBI (Subtract with Immediate)
TST Test with Zero TST (Test with Zero)
TSTI Test Immediate TSTI (Test Immediate)
XOR Logical Exclusive OR XOR (Logical Exclusive OR)
XORI Exclusive OR with Immediate XORI (Exclusive OR with Immediate)
7.2.4.2.1 ADD (Addition)
Operation:
GReg[r] ← GReg[s] + GReg[r]
T ← (GReg[r] == 0)
Assembler:
Syntax: add r,s
Example: add 0,3
ADD GReg[3] and GReg[0] and store the result in GReg[0]
CPU Flags: T
Cycles: 1
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Description: Performs the ADDition of the source general register s and the destination
general register r, and stores the result in the destination general register r. The T flag is
set if the result of the operation is 0. It is cleared if the result is not 0.
Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 1 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.2 ADDI (Add with Immediate Value)
Operation:
GReg[r] ← GReg[r] + immediate
T ← (GReg[r] == 0)
Assembler:
Syntax: addi r,immediate
Example: add 6,112
ADD GReg[6] and decimal value 112 and store the result in GReg[6]
CPU Flags: T
Cycles: 1
Description: Adds a 0-extended immediate value to a general register; stores the result in
the general register. The flag T is set when the result of the operation is 0; otherwise, it is
cleared. The immediate value is the low-order byte of the instruction and has a maximum
value of 255 (0xFF).
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Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 1 r r r i i i i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.3 AND (Logical AND)
Operation:
GReg[r] ← GReg[s] & GReg[r]
Assembler:
Syntax: and r,s
Example: and 1,2
AND GReg[1] and GReg[2] and store the result in GReg[1]
CPU Flags: Unaffected
Cycles: 1
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Description: Performs the AND of the source general register s and the destination
general register r, and stores the result in the destination general register r.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 1 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.4 ANDI (Logical AND with Immediate Value)
Operation:
GReg[r] ← GReg[r] & immediate
Assembler:
Syntax: andi r,immediate
Example: andi 7,45
AND GReg[7] and decimal value 45 and store the result in GReg[7]
CPU Flags: unaffected
Cycles: 1
Description: Performs an AND between a 0-extended immediate value and a general
register; stores the result in the general register. The immediate value is the low-order
byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 1 r r r i i i i i i i i
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Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.5 ANDN (Logical AND NOT)
Operation:
GReg[r] ← ~GReg[s] & GReg[r]
Assembler:
Syntax:andn r,s
Example: andn 3,4
AND GReg[3] and NOT GReg[4] (bit inverted) and store the result in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Performs the AND of the negation of the source general register s and the
destination general register r, and stores the result in the destination general register r.
Instruction Format:
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Table 7-49. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 1 0 s s s
Instruction Fields:
rrr /sss - destination register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.6 ANDNI (Logical AND with Negated Immediate Value)
Operation:
GReg[r] ← GReg[r] & ~immediate
Assembler:
Syntax: andni r,immediate
Example: andni 0,2
AND GReg[0] and decimal value -3 (inverted 32-bit value 2) and store the result in
GReg[0]
CPU Flags: unaffected
Cycles: 1
Description: Performs an AND between the negation of a 0-extended 8-bit immediate
value and a general register; stores the result in the general register. The immediate value
is the low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 1 0 r r r i i i i i i i i
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Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.7 ASR1 (Arithmetic Shift Right by 1 Bit)
Operation:
GReg[r]:{b31,b30,...,b1,b0} ← GReg[r]:{b31,b31,b30,...,b1}
Assembler:
Syntax: asr1 r
Example: asr1 3
divide by 2 the signed value of GReg[3] and store the result in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any general register to the right and keep the same sign: The
left bit (bit 31) is kept untouched.
Instruction Format:
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Table 7-50. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 1 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.8 BCLRI1 (Bit Clear Immediate)
Operation:
GReg[r]:{b31,...,b(i+1),0,b(i-1),...,b0} ← GReg[r]:{b31,...,b(i+1),b(i),b(i-1),...,b0}
Assembler:
Syntax: bclri r,i
Example: bclri 1,12
clear bit 12 in GReg[1]
CPU Flags: Unaffected
Cycles: 1
Description: Clear the bit of register r specified by the 5-bit immediate field
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 1 i i i i i
rrr - register field:
000 - GReg[0]
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001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiii - immediate value:
00000 - 0
00001 - 1
...
11110 - 30
11111 - 31
7.2.4.2.9 BDF (Conditional Branch if Destination Fault)
Operation:
if (DF == 1) PC ← PC + 1 + displacement else PC ← PC + 1
Assembler:
Syntax:bdf label
Example: bdf LLL
Jump to LLL if DF is set, or go to the next instruction if DF is cleared; the displacement
value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: If flag DF is set, jump to the new address that is calculated by adding the
sign-extended 8-bit displacement to the next PC address. If flag DF is cleared, no jump is
performed: The next instruction is located at the next PC address.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 p p p p p p p p
Instruction Fields:
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pppppppp - signed displacement field:
00000000 - 0
00000001 - 1
...
01111110 - 126
01111111 - 127
10000000 - (-128)
10000001 - (-127)
...
11111110 - (-2)
11111111 - (-1)
7.2.4.2.10 BF (Conditional Branch if False)
Operation:
if (T == 0)
PC ← PC + 1 + displacement
else
PC ← PC + 1
Assembler:
Syntax: bf label
Example: bf LLL
Jump to LLL if T is cleared, or go to the next instruction if T is set. The displacement
value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag T is cleared, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
T is set, no jump is performed: The next instruction is located at the next PC address.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 0 0 p p p p p p p p
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Instruction Fields:
pppppppp - signed displacement field:
00000000 - 0
00000001 - 1
...
01111110 - 126
01111111 - 127
10000000 - (-128)
10000001 - (-127)
...
11111110 - (-2)
11111111 - (-1)
7.2.4.2.11 BSETI (Bit Set Immediate)
Operation:
GReg[r]:{b31,...,b(i+1),1,b(i-1),...,b0} ← GReg[r]:{b31,...,b(i+1),b(i),b(i-1),...,b0}
Assembler:
Syntax: bseti r,i
Example: bseti 6,5
Set bit 5 in GReg[6]
CPU Flags: Unaffected
Cycles: 1
Description: Sets bit number i in the selected General Register.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 1 0 i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
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010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiii - bit number field:
00000 - 0
00001 - 1
...
11110 - 30
11111 - 31
7.2.4.2.12 BSF (Conditional Branch if Source Fault)
Operation:
if (SF == 1) PC ← PC + 1 + displacement else PC ← PC + 1
Assembler:
Syntax: bsf label
Example: bsf LLL
Jump to LLL if SF is set, or go to the next instruction if SF is cleared. The displacement
value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag SF is set, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
SF is cleared, no jump is performed: The next instruction is located at the next PC
address.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 0 p p p p p p p p
Instruction Fields:
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pppppppp - signed displacement field:
00000000 - 0
00000001 - 1
...
01111110 - 126
01111111 - 127
10000000 - (-128)
10000001 - (-127)
...
11111110 - (-2)
11111111 - (-1)
7.2.4.2.13 BT (Conditional Branch if True)
Operation
if (T == 1)
PC ← PC + 1 + displacement
else
PC ← PC + 1
Assembler
Syntax: bt label
bt LLL
Jump to LLL if T is set, or go to the next instruction if T is cleared. The displacement
value is calculated by the assembler.
CPU Flags: Unaffected
Cycles: 2 when the branch is done, 1 otherwise
Description: Conditional branch: If flag T is set, jump to the new address that is
calculated by adding the sign-extended 8-bit displacement to the next PC address. If flag
T is cleared, no jump is performed: The next instruction is located at the next PC address.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 0 1 p p p p p p p p
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pppppppp - signed displacement field:
00000000 - 0
00000001 - 1
...
01111110- 126
01111111 - 127
10000000 - (-128)
10000001 - (-127)
...
11111110 - (-2)
11111111 - (-1)
7.2.4.2.14 BTSTI (Bit Test immediate)
Operation:
T ← GReg[r]:b(i)
Assembler:
Syntax: btsti r,i
Example: btsti 2,29
Test bit 29 in GReg[2] and copy its value in flag T
CPU flags: T
Cycles: 1
Description: T is loaded with the value of bit number i from the selected general register.
Instruction Format:
Table 7-51. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 1 1 i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
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010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiii - bit number field:
0000 - 0
0001 - 1
...
11110 - 30
11111 - 31
7.2.4.2.15 CLRF (Clear Arm platform flags)
Operation:
if (ff%2 == 0)
SF ← 0
if (ff/2 == 0)
DF ← 0
Assembler:
Syntax: clrf ff
Example: clrf 2
Clear flag SF and keep flag DF unchanged
CPU Flags: SF, DF
Cycles: 1
Description: Clears a selection of the Arm platform fault flags: SF, DF, both SF and DF
or none can be cleared.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 f f 0 0 0 0 0 1 1 1
Instruction Fields:
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ff - flags field:
00 - clear SF and clear DF
01 - clear DF
10 - clear
SF 11 - no clear
7.2.4.2.16 CMPEQ (Compare for Equal)
Operation:
T ← (GReg[s] == GReg[r])
Assembler:
Syntax: cmpeq r,s
Example: cmpeq 7,5
Compare GReg[7] and GReg[5] and set flag T if they are equal
CPU flags: T
Cycles: 1
Description: Subtracts the destination general register r from the source general register s,
and sets T if the result is 0, clears T if the result is not 0.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 0 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
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7.2.4.2.17 CMPEQI (Compare with Immediate for Equal)
Operation:
T ← (GReg[r] == immediate)
Assembler:
Syntax: cmpeqi r,immediate
Example: cmpeqi 2,13
Compare GReg[2] and decimal value 13 and set flag T if they are equal
CPU Flags: T
Cycles: 1
Description: Subtracts the 0-extended 8-bit immediate value from the general register,
and sets T if the result is 0, clears T if the result is not 0. The immediate value is the low-
order byte of the instruction.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 r r r i i i i i i i i
Instruction Fields:
rrr - destination register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
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11111111 - 255
7.2.4.2.18 CMPHS (Compare for Higher or Same)
Operation:
T ← (GReg[r] ≥ GReg[s])
Assembler:
Syntax: cmphs r,s
Example: cmphs 0,1
Compare GReg[0] and GReg[1] and set flag T if GReg[0] is higher than or equal to
GReg[1]
CPU Flags: T
Cycles: 1
Description: Compares the destination general register r and the source general register s,
and sets T if the destination general register r is higher than or equal to the source general
register s, clears T otherwise. The comparison is unsigned.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 1 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.19 CMPLT (Compare for Less Than)
Operation:
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T ← (GReg[r] < GReg[s])
Assembler:
Syntax: cmplt r,s
Example: cmplt 7,4
Compare GReg[7] and GReg[4] and set flag T if GReg[7] is lower than GReg[4]
CPU Flags: T
Cycles: 1
Description: Compares the destination general register r and the source general register s,
and sets T if the destination general register r is lower than the source general register s,
clears T otherwise. The comparison is signed.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 1 0 s s s
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.20 cpShReg (Update Context of PCU Registers and Flag)
Assembler:
Syntax: cpShReg
CPU Flags: none
Cycles: 1
Description: SF, RPC, T, PC,LM, EPC, DF, and SPC registers are updated according to
the value of their corresponding bits in the context memory. This instruction must only be
used in debug mode via the OnCE. It reverses the done 5 operation.
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Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0
7.2.4.2.21 DONE (DONE, Yield)
Operation:
if (jjj&6 == 2) HE[CCR] ← 0
if (jjj == 3) HI[CCR] ← 1
if (jjj == 4) EP[CCR] ← 0
if ((jjj == 0) && (NCP > CCP)) CCR ← NCR
else if ((jjj == 1) && (NCP >= CCP))
CCR ← NCR
else
CCR ← NCR
(CCR stands for Current Channel Register; NCR stands for Next Channel Register)
Assembler:
Syntax: done jjj
Example: done 3
Clear HE bit for the current channel, send an interrupt to the Arm platform for the current
channel and reschedule.
CPU Flags: Unaffected
Cycles: Variable if a context switch is done, 1 otherwise
Description: Clears one of the channel enabling bits (HE or EP for the corresponding
channel number) if required. Sends an interrupt to the corresponding Arm platform by
setting the appropriate flag, if required (HI for the corresponding channel number).
Reschedules according to the mode and the NCP (Next Channel Priority) and CCP
(Current Channel Priority) values. According to the scheduling decision, the NCR (Next
Channel Register) is copied to the CCR (Current Channel Register) and channel contexts
are switched. If several channels with the same highest priority are pending, they are
ordered by their number from 31 down to 0. The higher number is selected (for example,
channel 26 is selected if channels 3, 12, 14, and 26 with the same highest priority are
pending). If no flag is modified, the reschedule can allow the replacement of the current
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channel by another channel with a priority strictly greater than the current channel
priority (yield). Or, it can allow the replacement of the current channel by another
channel with a priority greater than or equal to the current channel priority (yieldge). In
the latter case, the selected channel will always be the first one with the same priority,
starting from channel number 31 down to channel 0 (the current channel does not belong
to the set of selectable channels).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 j j j 0 0 0 0 0 0 0 0
jjj - Channel Flags field:
000 - No channel flags affected: Reschedule only if the next channel priority is greater
than current channel priority (yield)
001 - No channel flags affected: Reschedule only if the next channel priority is greater
than or equal to the current channel priority (yieldge)
010 - Clear HE for the current channel and reschedule 011 - Clear HE, set HI for the
current channel and reschedule 100 - Clear EP for the current channel and reschedule
101 - Reserved for debug to copy relevant registers into context memory
110 - RESERVED
111 - RESERVED
For the scheduling rules, refer to Scheduler Functional Description. Every possible done
instruction is further described as follows:
• done 0/yield is executed by a channel script when it accepts preemption by a higher
priority channel;
• done 1/yieldge is executed by a channel script when it accepts preemption by a
higher priority channel and it also accepts a roll-up with other channels that have the
same priority;
• done 2 is executed by a channel script that was triggered by a Arm platform start via
the Channel Start (SDMAARM_HSTART) register, when its task is completed and it
requires termination;
• done 3 is executed by a channel script that was triggered by a Arm platform start via
the Channel Start (SDMAARM_HSTART) register, when its task is completed, it
requires termination and it needs to trigger an interrupt to the Arm platform upon
closure;
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• done 4 is executed by a channel script that was triggered by a DMA request, when its
task is completed and it requires termination;
• done 5 is used in debug mode only; it copies the PCU registers and flags to the
context memory of the current channel;
7.2.4.2.22 ILLEGAL (ILLEGAL Instruction)
Operation:
PC ← 0001
Assembler:
Syntax: illegal
CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the Illegal instruction routine located at address 0001. All
unauthorized instructions result in an Illegal instruction behavior; however, the
ILLEGAL instruction must be used to guarantee software compatibility with future
versions of the SDMA.
Instruction Format
Table 7-52. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1
7.2.4.2.23 JMP (Unconditional Jump Immediate)
Operation:
PC ← absolute_address
Assembler:
Syntax: jmp label
Example: jmp LLL
The assembler translates the label to the exact address
CPU Flags:Unaffected
Cycles: 2
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Description: Jumps to the absolute address contained the lower 14 bits of the instruction
(the PC is a 14-bit register).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 a a a a a a a a a a a a a a
aaaaaaaaaaaaaa - address field:
00000000000000 - 0
00000000000001 - 1
...
11111111111110 - 16382
11111111111111 - 16383
7.2.4.2.24 JMPR (Unconditional Jump)
Operation:
PC ← GReg[r]
Assembler:
Syntax: jmpr r
Example: jmpr 0
Jump to address stored in GReg[0]
CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the absolute address contained in a General Register.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 0 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
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010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.25 JSR (Unconditional Jump to Subroutine Immediate)
Operation:
RPC ← PC + 1
PC ← absolute_address
Assembler:
Syntax: jsr r
Example:jsr LLL
Jumps to subroutine starting at LLL; the assembler translates the label to exact address
CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the subroutine located at the absolute address contained the lower
14 bits of the instruction (the PC is a 14-bit register).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 a a a a a a a a a a a a a a
aaaaaaaaaaaaaa - address field:
00000000000000 - 0
00000000000001 - 1
...
11111111111110 - 16382
11111111111111 - 16383
7.2.4.2.26 JSRR (Unconditional Jump to Subroutine)
Operation:
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RPC ← PC + 1
PC ← GReg[r]
Assembler:
Syntax: jsrr r
Example:jsrr 5
Jumps to subroutine located at address stored in GReg[5]
CPU Flags: Unaffected
Cycles: 2
Description: Jumps to the subroutine at address contained in a General Register
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 0 1
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.27 LD (Load Register)
Operation:
GReg[r] ← [GReg[b] + displacement]
if (transfer_error)
SF ← 1
else
SF ← 0
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Assembler:
Syntax: ld r,(b,displacement)
Example: ld 1,(2,23)
Loads data into GReg[1]; the data is located at address obtained by adding decimal value
23 to GReg[2]
CPU Flags: SF
Cycles: 2+n where n is 0 for ROM, RAM or memory mapped registers, and n is the
number of wait-states of the peripheral for a peripheral access
Description: Adds a 5-bit 0-extended displacement to a base address in General Register
b; the result is the address of the data to fetch on the DM bus. The data received from the
bus is stored in the destination General Register r. If an error occurs during the transfer,
the flag SF is set, else it is cleared.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 r r r d d d d d b b b
rrr / bbb - register field:
000 - GReg[0]
001 - GReg[1]
...
111 - GReg[7]
ddddd - displacement value:
00000 - 0
00001 - 1
...
11111 - 31
7.2.4.2.28 LDF (Load Register from Functional Unit)
Operation:
GReg[r] ← [fu_address]
if (transfer_error)
SF ← 1
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else
SF ←0
fu_address is an 8-bit field and depends on addressed functional unit
Assembler:
Syntax: ldf r,fu_address
Example: ldf 0,13
Loads data coming from the Burst DMA register MD into GReg[0]; it is a 32-bit access
with no prefetch
CPU Flags: SF
Cycles: 1+n where n is the number of wait-states that may be inserted by the functional
unit
Description: Sends an 8-bit address on the Functional Unit Bus (FU bus) and stores the
data received from the bus in the destination General Register r. If an error occurs during
the transfer, the flag SF is set, else it is cleared.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 0 r r r f f f f f f f f
See the following sections for more details of the LDF instruction usage with each
functional unit:
• Burst DMA Read (ldf) for Burst DMA
• Peripheral DMA Read (ldf)-Read Mode for Peripheral DMA
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
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ffffffff - functional unit source register and action (unspecified values are reserved):
00000000 - MSA
00000100 - MDA
00001001 - MD byte
00001010 - MD halfword
00001011 - MD word
00001100 - MS
00101001 - MD byte - prefetch
00101010 - MD halfword - prefetch
00101011 - MD word - prefetch
01000000 - DSA
11000000 - PSA
11001000 - PD
11010000 - PDA
11011000 - PD in copy mode (rrr contents are lost)
11101000 - PD - prefetch next data
11111111 - PS
7.2.4.2.29 LDI (Load Register with Immediate Value)
Operation:
GReg[r] ← immediate
Assembler:
Syntax: ldi r,immediate
Example: ldi 6,1
loads decimal value 1 into GReg[6]
CPU Flags: Unaffected
Cycles: 1
Description: Stores a 0-extended immediate value in a General Register. The immediate
value is the low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 r r r i i i i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.30 LDRPC (Load from RPC to Register)
Operation:
GReg[r] ← RPC
Assembler:
Syntax: ldrpc r
Example: ldrpc 3
copies RPC to GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Stores the contents of the RPC in a General Register. That instruction may
be used to have more than one level of subroutines.
Instruction Format
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 0 1 0 1 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.31 LOOP (Hardware Loop)
Operation:
if (ff%2 == 0)
SF ← 0
if (ff/2 == 0)
DF ← 0
if ((GReg[0] == 0) || (SF == 1) || (DF == 1))
PC ← PC + loop_size + 1
else
SPC ← PC + 1
EPC ← PC + loop_size + 1
LM ← 1
PC ← PC + 1
during every instruction execution in the loop:
if ((SF == 1) || (DF == 1))
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LM ← 0
PC ← EPC
else if ((PC + 1) == EPC)
GReg[0] ← GReg[0] - 1
if (GReg[0] == 0)
LM ← 0
PC ← EPC
else
PC ← SPC
else
PC ← nextPC(instruction)
after the execution of the last instruction of the loop body:
if (GReg[0] == 0)
T ← 1
else
T ← 0
Assembler:
Syntax: loop n{,ff}
Example: loop 3,1
Executes GReg[0] times the instructions comprised between PC+1 and PC+3 (included);
ff=1 clears the DF flag before starting the loop. When omitted, the ff field is set to 0
(clearing both SF and DF).
CPU Flags: LM[1:0], T
Cycles: 2 when the loop count (GReg[0]) is 0 or SF or DF is set at loop start, 1+1 when
the loop starts but exits abnormally (SF or DF set inside the loop which adds 1 cycle to
the offending load or store to jump to EPC), 1 when the loop is executed normally
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Description: The loop instruction executes a sequence of instructions several times. The
number of times is given by the contents of GReg[0], the loop counter. SDMA will jump
to the first instruction after the end of the loop if the value in GReg[0] is 0. Otherwise the
SDMA enters loop mode. It sets the most significant bit of the LM flag that will only be
reset once the last instruction of the last loop is executed. The instructions in the loop are
executed GReg[0] times. The management of fault flags (SF and DF) is as follows. When
entering the hardware loop, SF and DF can be cleared according to the ff field of the
instruction. After that operation, if any flag is still set the loop will not be executed. The
SDMA will jump to the first instruction after the end of the loop without entering loop
mode. During the execution of the loop, if any fault flag is set by a LD, LDF, ST, or STF
instruction, the SDMA will immediately exit loop mode and jump to the first instruction
after the end of the loop. In that case, GReg0 is not decremented for that last piece of the
loop body execution (even if the SF or DF flag is set at the last instruction of the loop
body). The T flag reflects the state of GReg[0] after the end of the loop, which is an
indicator of the complete execution of the loop. If the loop exited because of an error (SF
or DF set), GReg[0] will not be 0 at the end of the loop, hence T will be cleared. If the
loop executes without fault, GReg[0] will be 0 at the end of the loop, hence T will be set.
The boundary case when a source or destination fault occurs at the last instruction of the
last loop is considered as an anticipated exit of the loop, which causes the T flag to be
cleared. If the last instruction executed before leaving the hardware loop also tries to
modify the T flag, the flag is updated according to the value of GReg[0], NOT according
to the result of the last executed instruction.
Limitations:
1. 1. Jump instructions (JMP, JMPR, JSR, JSRR, BF, BT, BSF, BDF) are not allowed
inside the hardware loop.
2. 2. GReg[0] cannot be written to inside the hardware loop (it can be read).
3. 3. The empty loop (0 instruction in the body) is forbidden.
4. 4. If GReg[0] == 0 at the start of the loop, which causes a jump to EPC, the T flag is
not updated.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 0 f f n n n n n n n n
Instruction Fields:
ff - flags field:
00 - clear SF and clear DF
01 - clear DF
10 - clear SF
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11 - no clear
nnnnnnnn - loop size
00000000 - empty loop: forbidden value
00000001 - 1 instruction in the loop
00000010 - 2 instructions in the loop
...
11111111 - 255 instructions in the loop
7.2.4.2.32 LSL1 (Logical Shift Left by 1 Bit)
Operation:
GReg[r]:{b30,...,b1,b0,0} ← GReg[r]:{b31,b30,...,b1,b0}
Assembler:
Syntax: lsl1 r
Example: lsl1 2
multiplies by 2 the value in GReg[2]
CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any General Register to the left. The right bit (bit 0) is set to
0. No overflow is detected by the hardware.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 1 1
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
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111 - GReg[7]
7.2.4.2.33 LSR1 (Logical Shift Right by 1 Bit)
Operation:
GReg[r]:{0,b31,b30,...,b1} ← GReg[r]:{b31,b30,...,b1,b0}
Assembler:
Syntax: lsr1 r
Example: lsr1 4
divides by 2 the unsigned value contained in GReg[4]
CPU Flags: Unaffected
Cycles: 1
Description: Shift the bits of any General Register to the right. The left bit (bit 31) is set
to 0.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 0 1
Instruction Fields:
rrr - destination register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.34 MOV (Logical Move)
Operation:
GReg[r] ← GReg[s]
Assembler:
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Syntax: mov r,s
Example: mov 4,0
copies GReg[0] to GReg[4]
CPU Flags: Unaffected
Cycles: 1
Description: Move the contents of the source General Register s to the destination
General Register r.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 0 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.35 NOTIFY (Notify to Arm platform)
Operation:
if (jjj & 4 == 0)
if (jjj&2 == 2)
HE[CCR] ← 0
if (jjj&1== 1)
HI[CCR] ← 1
else if (jjj == 4)
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EP[CCR] ← 0
else
(CCR stands for Current Channel Register)
Assembler:
Syntax: notify jjj
Example: notify 3
clears the HE bit for the current channel and sends an interrupt to the Host for the current
channel
CPU Flags: Unaffected
Cycles: 1
Description: Clears one of the channel enabling bits (HE or EP for the corresponding
channel number) if required, sends an interrupt to the corresponding Arm platform by
setting the appropriate flag if required (HI for the corresponding channel number).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 j j j 0 0 0 0 0 0 0 1
jjj - Channel Flags field:
000 - unused
001 - set HI for the current channel
010 - clear HE for the current channel
011 - clear HE, set HI for the current channel
100 - clear EP for the current channel
101 - RESERVED
110 - RESERVED
111 - RESERVED
7.2.4.2.36 OR (Logical OR)
Operation:
GReg[r] ← GReg[s] | GReg[r]
Assembler:
Syntax: or r,s
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Example: or 3,6
ORs GReg[3] and GReg[6] and stores the result in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Performs the OR of the source General Register s and the destination
General Register r, and stores the result in the destination General Register r.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 0 1 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.37 ORI (Logical OR with Immediate Value)
Operation:
GReg[r] ← GReg[r] | immediate
Assembler:
Syntax: ori r,immediate
Example: ori 1,56
ORs GReg[1] and the decimal value 56 and stores the result in GReg[1]
CPU Flags: unaffected
Cycles: 1
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Description: Performs an OR between a 0-extended 8-bit immediate value and a General
Register; stores the result in the General Register. The immediate value is the low-order
byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 1 r r r i i i i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.38 RET (Return from Subroutine)
Operation:
PC ← RPC
Assembler:
Syntax: ret
CPU Flags: Unaffected
Cycles: 2
Description: Return from subroutine.
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Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
7.2.4.2.39 REVB (Reverse Byte Order)
Operation:
GReg[r]:{B3,B2,B1,B0} ← GReg[r]:{B0,B1,B2,B3}
Assembler:
Syntax: revb r
Example: revb 5
reverses bytes order in GReg[5]
CPU Flags: Unaffected
Cycles: 1
Description: Reverse the byte order of any General Register.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 0 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
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7.2.4.2.40 Reverse Low Order Bytes(REVBLO)
Operation:
GReg[r]:{B3,B2,B0,B1} ← GReg[r]:{B3,B2,B1,B0}
Assembler:
Syntax: revblo r
Example: revblo 0
reverses low order bytes in GReg[0]
CPU Flags: Unaffected
Cycles: 1
Description: Reverse both low order bytes of any General Register.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 0 1
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.41 ROR1 (Rotate Right by 1 Bit)
Operation:
GReg[r]:{b0,b31,b30,...,b1} ← GReg[r]:{b31,b30,...,b1,b0}
Assembler:
Syntax: ror1 r
Example: ror1 3
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rotates bits to the right in GReg[3]
CPU Flags: Unaffected
Cycles: 1
Description: Rotate the bits of any General Register to the right.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 1 0 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.42 RORB (Rotate Right by 1 Byte)
Operation:
GReg[r]:{B0,B3,B2,B1} ← GReg[r]:{B3,B2,B1,B0}
Assembler:
Syntax: rorb r
Example: rorb 2
rotates bytes to the right in GReg[2]
CPU Flags: Unaffected
Cycles: 1
Description: Rotate the bytes of any General Register to the right.
Instruction Format
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 0 0 0 1 0 0 1 0
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.43 SOFTBKPT (Software Breakpoint)
Operation:
Stops the current script and enters debug mode
Assembler:
softbkpt
CPU Flags: Unaffected
Description: When the core executes this instruction, it has the same effect as receiving a
debug request from the OnCE or via the external debug request input: the script execution
halts, the PCU enters its debug state and waits for the OnCE commands that are described
in OnCE and Real-Time Debug.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
7.2.4.2.44 ST (Store Register)
Operation:
[GReg[b] + displacement] ← GReg[r]
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if (transfer_error)
DF ← 1
else
DF ← 0
Assembler:
Syntax: st r,(b,displacement)
Example: st 7,(0,9)
stores the value from GReg[7] into memory at address obtained by adding decimal value
9 to GReg[0]
CPU Flags: DF
Cycles: 2+n where n is 0 for ROM, RAM or memory mapped registers, and n is the
number of wait-states of the peripheral for a peripheral access
Description: Adds a 5-bit 0-extended displacement to a base address in General Register
b; the result is the address of the data to store on the DM bus. The data sent on the bus
comes from the source General Register r. If an error occurs during the transfer, the flag
DF is set, else it is cleared.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 1 r r r d d d d d b b b
Instruction Fields:
rrr / bbb - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
ddddd - displacement value:
00000 - 0
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00001 - 1
...
11111 - 31
7.2.4.2.45 STF (Store Register in Functional Unit)
Operation:
[fu_address] ← GReg[r] 0
if (transfer_error) 0
DF ← 1 0
else 0
DF ← 0
fu_address is an 8-bit field
Assembler:
Syntax: stf r,fu_address
Example: stf 3,0x2B
stores the 32-bit contents of GReg[3] to the Burst DMA register MD; waits until the flush
to external memory is completed
CPU Flags: DF
Cycles: 1+n where n is the number of wait-states that may be inserted by the functional
unit
Description: Sends an 8-bit address on the Functional Unit Bus (FU bus) and sends the
contents of the source General Register r on the bus. If an error occurs during the transfer,
the flag DF is set, else it is cleared.
Table 7-53. Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 1 r r r f f f f f f f f
See the following sections for more details of the STF instruction usage with each
functional unit:
• Burst DMA Write (stf) for Burst DMA
• Peripheral DMA Write (stf)-Write Mode for Peripheral DMA
Instruction Fields:
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rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
ffffffff - functional unit destination register and action (unspecified values are reserved):
00000000 - MSA in incremented mode
00000100 - MDA in incremented mode
00001001 - MD byte
00001010 - MD halfword
00001011 - MD word
00001100 - clear MS error flag
00001111 - MS
00010000 - MSA in frozen mode
00010100 - MDA in frozen mode
00011000 - MD in copy mode - number of words in rrr
00100000 - MSA in incremented mode - start prefetch
00101000 - MD no data - flush
00101001 - MD byte - flush
00101010 - MD halfword - flush
00101011 - MD word - flush
00110000 - MSA in frozen mode - start prefetch
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11000001 - PSA in frozen mode - 8-bit data width
11000010 - PSA in frozen mode - 16-bit data width
11000011 - PSA in frozen mode - 32-bit data width
11000101 - PSA in incremented mode - 8-bit data width
11000110 - PSA in incremented mode - 16-bit data width
11000111 - PSA in incremented mode - 32-bit data width
11001000 - PD
11001001 - PSA in decremented mode - 8-bit data width
11001010 - PSA in decremented mode - 16-bit data width
11001011 - PSA in decremented mode - 32-bit data width
11001100 - clear PS error flag
11001101 - PSA data width becomes 8-bit
11001110 - PSA data width becomes 16-bit
11001111 - PSA data width becomes 32-bit
11010001 - PDA in frozen mode - 8-bit data width
11010010 - PDA in frozen mode - 16-bit data width
11010011 - PDA in frozen mode - 32-bit data width
11010101 - PDA in incremented mode - 8-bit data width
11010110 - PDA in incremented mode - 16-bit data width
11010111 - PDA in incremented mode - 32-bit data width
11011001 - PDA in decremented mode - 8-bit data width
11011010 - PDA in decremented mode - 16-bit data width
11011011 - PDA in decremented mode - 32-bit data width
11011101 - PDA data width becomes 8-bit
11011110 - PDA data width becomes 16-bit
11011111 - PDA data width becomes 32-bit
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11100001 - PSA in frozen mode - 8-bit data width - prefetch data
11100010 - PSA in frozen mode - 16-bit data width - prefetch data
11100011 - PSA in frozen mode - 32-bit data width - prefetch data
11100101 - PSA in incremented mode - 8-bit data width - prefetch data
11100110 - PSA in incremented mode - 16-bit data width - prefetch data
11100111 - PSA in incremented mode - 32-bit data width - prefetch data
11101001 - PSA in decremented mode - 8-bit data width - prefetch data
11101010 - PSA in decremented mode - 16-bit data width - prefetch data
11101011 - PSA in decremented mode - 32-bit data width - prefetch data
11101101 - PSA data width becomes 8-bit - prefetch data
11101110 - PSA data width becomes 16-bit - prefetch data
11101111 - PSA data width becomes 32-bit - prefetch data
11111111- PS
7.2.4.2.46 SUB (Subtract)
Operation:
GReg[r] ← GReg[r] - GReg[s]
T ← (GReg[r] == 0)
Assembler:
Syntax: sub r,s
Example: sub 4,7
SUBtracts GReg[7] from GReg[4] and stores the result in GReg[4]
CPU Flags: T
Cycles: 1
Description: Subtracts the source General Register s from the destination General
Register r, and stores the result in the destination General Register r. The T flag is set if
the result of the operation is 0; it is cleared if the result is not 0.
Instruction Format
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 1 0 0 s s s
Instruction Fields:
rrr / sss - register fields:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.47 SUBI (Subtract with Immediate)
Operation:
GReg[r] ← GReg[r] - immediate
T ← (GReg[r] == 0)
Assembler:
Syntax: sub r,immediate
Example: sub 1,255
SUBtracts decimal value 255 from GReg[1] and stores the result in GReg[1]
CPU Flags: T
Cycles: 1
Description: Subtracts a 0-extended 8-bit immediate value from a General Register;
stores the result in the General Register. The flag T is set when the result of the operation
is 0; otherwise, it is cleared. The immediate value is the low-order byte of the instruction
and has a maximum value of 255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 r r r i i i i i i i i
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Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.48 TST (Test with Zero)
Operation:
T ← ((GReg[s] & GReg[r]) != 0)
Assembler:
Syntax: tst r,s
Example: tst 2,3
ANDs GReg[2] and GReg[3] and sets T if the result is non-null
CPU Flags: T
Cycles: 1
Description: Performs the AND of the source General Register s and the destination
General Register r, and sets T if the result is not 0, clears T if the result is 0.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 1 0 0 0 s s s
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Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.49 TSTI (Test Immediate)
Operation:
T ← ((GReg[r] & immediate) != 0)
Assembler:
Syntax: tsti r,immediate
Example: tsti 5,13
ANDs GReg[5] and decimal value 13 and sets T if the result is non-null
CPU Flags: T
Cycles: 1
Description: Performs the AND of a 0-extended 8-bit immediate value and the
destination General Register r, and sets T if the result is not 0, clears T if the result is 0.
The immediate value is the low-order byte of the instruction and has a maximum value of
255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 r r r i i i i i i i i
Instruction Fields:
rrr - destination register field:
000 - GReg[0]
001 - GReg[1]
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010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.50 XOR (Logical Exclusive OR)
Operation:
GReg[r] ← GReg[s] ^ GReg[r]
Assembler:
Syntax: xor r,s
Example: xor 0,3
XORs GReg[0] and GReg[3] and stores the result in GReg[0]
CPU Flags: Unaffected
Cycles: 1
Description: Performs the eXclusive OR of the source General Register s and the
destination General Register r, and stores the result in the destination General Register r.
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 r r r 1 0 0 1 0 s s s
Instruction Fields:
rrr / sss - register field:
000 - GReg[0]
001 - GReg[1]
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010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
111 - GReg[7]
7.2.4.2.51 XORI (Exclusive OR with Immediate)
Operation:
GReg[r] ← GReg[r] ^ immediate
Assembler:
Syntax: xori r,immediate
Example: xor 7,5
XORs GReg[5] and decimal value 5 and stores the result in GReg[7]
CPU Flags: Unaffected
Cycles: 1
Description: Performs an eXclusive OR between a 0-extended 8-bit immediate value and
a General Register; stores the result in the General Register. The immediate value is the
low-order byte of the instruction and has a maximum value of 255 (0xFF).
Instruction Format
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 1 0 r r r i i i i i i i i
Instruction Fields:
rrr - register field:
000 - GReg[0]
001 - GReg[1]
010 - GReg[2]
011 - GReg[3]
100 - GReg[4]
101 - GReg[5]
110 - GReg[6]
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111 - GReg[7]
iiiiiiii - immediate value:
00000000 - 0
00000001 - 1
...
11111110 - 254
11111111 - 255
7.2.4.2.52 YIELD, YIELDGE (DONE, Yield)
By default, unsupported assembler syntax. Can be aliased to the corresponding done
instructions (yield = done 0; yieldge = done 1). Refer to the done instruction description
DONE (DONE, Yield) .
7.2.5 Software Restrictions
7.2.5.1 Unsupported Burst DMA Access Sequence
The SDMA does not support triggering a pre-fetch followed by a flush of the Burst DMA
without reading or writing any data. If the flush occurs while the background pre-fetch
DMA operation is still in progress, it could result in un-defined behavior.
An example of the sequence which could result in undefined results is shown in the
following example:
Instruction sequence not supported
stf r1, MSA|PF ; Update source address, triggers data pre-fetch in the
; background
mov R0,R0 ; Execute multiple assembly instructions, none of which
; read
mov R0,R0 ; or write data to/from MD
stf MD|SZ0|FL ; Flush FIFO without writing data. If the pre-fetch is still
; in progress when this instruction is executed, there
; could be undefined operation
A work-around to avoid any undesirable results is to first read MD to ensure the pre-fetch
is complete before the flush is attempted.
Work-Around to previous example
stf r1, MSA|PF ; Update source address, triggers data pre-fetch.
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mov R0,R0 ; Execute multiple assembly instructions, none of which
; read
mov R0,R0 ; or write data to/from MD
ldf r2, MD ; dummy read of MD to ensure pre-fetch is complete
; before the next instruction
stf MD|SZ0|FL ; Flush FIFO without writing data
7.2.6 Application Notes
7.2.6.1 Data Structures for Boot Code and Channel Scripts
SDMA boot code downloads the different channel contexts and the scripts that will be
executed on SDMA channels during the application.
The boot code is run after reset when channel 0 is started by the Arm platform. The boot
code is also known as channel 0 script.
The boot code is based on the Channel Control Block (CCB) and Buffer Descriptor (BD)
mechanisms that are data structures located into the Arm platform memory space. With
these data structures, it is possible to instruct SDMA to download scripts and contexts but
also to dump a context or a script to a destination data buffer. Channel scripts also use the
CCB and BD data structures to pass instructions and/or pointers to data to be copied.
The format, processing, and field definition of the CCB and BD are defined and
performed entirely by the software script rather than the SDMA hardware. An overview
of the format and structure is provided here, but for complete details refer to the SDMA
software documentation (see SDMA Scripts).
The CCB and BD data structures are accessed by SDMA using DMA and processed by
the SDMA scripts. The ROM contains common sub-routines for processing these data
structures which may be called by the bootload and channel scripts.
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Channel Control Block Buffer Descriptor Array
MC0PTR
currentBDptr Command Flags Count
baseBDptr Buffer Address
CCB0
chanDesc Extended Buffer Address
status Command Flags Count
currentBDptr Buffer Address
baseBDptr Extended Buffer Address
CCB1
chanDesc
status
Data Buffer
currentBDptr
baseBDptr
CCB31
chanDesc Data Buffer
status
Figure 7-16. Data Structures Layout
The previous figure shows an example how these data structures are linked to pass
command and pointers to data buffers. The SDMA's MC0PTR register holds the base
address of the Channel 0 Control Block (CCB0). The Channel 0 control block holds a
pointer to the array of buffer descriptors. The buffer descriptors are used to tell the
channel 0 (boot channel) what to do as described Buffer Descriptor Format.
7.2.6.1.1 Buffer Descriptor Format
Buffer descriptors are three longs (32-bit words) in size as, shown in the figure found
here.
A buffer descriptor describes the properties of the data buffer it points to. The buffer
descriptors can be used for linear or circular data buffers in the Arm platform processor
memory. The CCB contains a pointer to the base BD as well as the current BD.
Table 7-54. Buffer Descriptor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Command - - L R I C W D Count
Buffer Address
Extended Buffer Address
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Table 7-55. Buffer Descriptor Field Descriptions
Field Description
31-24 Command. The command field is used to differentiate operations performed within a script when the script
accesses this particular buffer descriptor. The use of this field can be defined by the script. The command values
Command
defined for the bootload script are defined in Buffer Descriptor Commands for Bootload scripts. Refer to the
individual script definition in script library documents in SDMA Scripts for command field definitions for other
scripts.
23 Reserved
22 Reserved
21 Last Buffer Descriptor: This bit is set in SDMA IPC scripts to indicate to the receiving Core that the transfer has
ended. Whenever the source finishes transferring the count it wanted to transfer, it sets LAST_BIT in the
L
destination BD, to let the destination know that transfer is over.This bit also tells the destination software that
when it processes the destination BDs, they need not process any BD after the BD with the LAST_BIT set.For
example, when the DSP prepares a single buffer descriptor with count equals to 25 and Arm platform prepares a
single buffer descriptor with count equals 100. When 25 bytes have been transferred from DSP to Arm platform,
the DSP buffer descriptor is normally closed while the Arm platform buffer descriptor will have the L bit set and
the byte count updated to 25.
20 erroR. Indicates an error occurred on the channel's buffer descriptor requested command. Some scripts may
overwrite the command field with an error code indicating the source of the error.
R
0 No Error
1 Error
19 Interrupt. When SDMA has finished to process data transfer attached to this buffer descriptor, send an interrupt
to the Arm platform.
I
0 No Interrupt
1 Interrupt the processor when BD is complete
18 Continuous. This buffer is allowed to receive multiple transmit buffers or is allowed to transmit to multiple receive
buffers.The Continuous bit is decoded at the end of the processing of a BD to determine if the SDMA script must
C
open a new BD to potentially continue the data transfer.
0 No further buffer descriptors
1 SDMA should move to the next Buffer descriptor after this one
17 Wrap. Indicates if this buffer descriptor is the last one for the channel control block. When encountering this bit
set, the SDMA scripts updates the CurrentBD pointer to point to the first Buffer Descriptor of the array. This bit is
W
set if the Arm platform wants to organize the array of BD in a circular way (like a ring). When all BD have been
processed and if Wrap bit and CONtinuous bit are set in the last BD, the SDMA script will wrap around and it will
try to re-open the first BD.
0 No Error
1 Wrap to first buffer descriptor after this one is processed.
16 D - "Done": bit 16: indicates the "ownership" of the buffer descriptor. When D=0 the host owns the buffer
descriptor; when D=1 SDMA owns the buffer descriptor. In the case of the channel 0, D=1 indicates the SDMA
D
has not yet processed this buffer, D=0 indicates the SDMA has processed this buffer.
0 Arm platform owns the buffer.
1 SDMA owns the buffer
15-0 Count. the count field (bit 15-0) indicates the size of the data to be transmitted, the size of the data buffer pointed
to by the buffer descriptor. The SDMA memory structure is different for program memory (16-bits shorts/half-
Count
words) and data memory (32-bits long). For channel 0 buffer descriptors, Count is expressed in 16-bit half-words
when PM is addressed and in 32-bit words when DM is addressed. Count is typically expressed in bytes for
other channel scripts, but the unit is dependant on the script.
31-0 Buffer address. Address pointer to the data buffer.
31-0 Extended buffer address. Additional pointer or other information required by some scripts.
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The buffer descriptors form an array of programmable size. If the last buffer descriptor is
marked by the Wrap flag-bit W=1, the array of buffer descriptor is treated as a ring with
some logically continuous portion owned by the Arm platform with D=0, and the
remainder owned by the SDMA with D=1. The count field of the buffer descriptor
indicates how much data has been transmitted.
If Arm platform has prepared 3 buffers to be filled by the SDMA script, it has also
prepared 3 BD, one for each buffer. The Cont and Wrap bits are used to organize the
buffers in a circular way. For example, CONTinous bit is set to 1 in the 2 first BDs and
Wrap is set in the 3rd BD. The SDMA script opens and processes BD#1. Since
CONTinous bit is set for this BD, the SDMA will open the second BD and it will process
it. Each time a BD is processed, its Done bit is reset by the SDMA. After the 3rd BD, if
CONTinous is not set but if Wrap is set, the SDMA script stops here and the next time the
channel will be triggered, the script will open the BD pointed by the currentBDptr pointer
of the CCB and it will correspond to the first buffer descriptor.
If the CONTinous bit and Wrap bits are both set in the 3rd BD, the script will close it and
it will try to open the first BD. An error may occur at this point if the BD#1 has already
been processed and its Done bit is 0. The SDMA script cannot process a BD with a Done
bit to 0. It means the BD is not ready to be processed. To avoid this situation, the
CONTinous bit should not be set for the last BD if Wrap is set, and the Interrupt flag
must set for the last BD. It will warn the owner of the BD that all the BDs have been
processed and it has to re-set to 1 the Done bit of all the BD's if it desires the SDMA to
fill them again. Basically, if the Arm platform expects the SDMA to fill up the buffers in
a circular fashion, then it's the responsibility of the Arm platform to set the Done bit of a
buffer descriptor at an appropriate time.
AP MEM
AP BD1, BD2 & BD3
Buffer 1 CD 25
(25 bytes)
CD 50
Buffer 2
Incoming Data SDMA
(50 bytes)
IWD 25
Buffer 3
(25 bytes) Interrupt to AP
(HI)
Figure 7-17. Buffer Descriptor Flow
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The previous figure shows an example buffer descriptor flow. When the incoming data is
stored and fills the first buffer of 25 bytes, the SDMA script opens the second BD
because the CONTinuous bit was set. Then next incoming data is put in the second
buffer. After receiving 50 bytes, the second buffer descriptor is also closed. The Done bit
is reset and the third BD is opened. After receiving another 25 bytes, the third buffer is
full and an interrupt is sent to the Arm platform because the Interrupt flag is set in the 3rd
BD. The CONTinuous flag is not present the transfer is over. The next time the script will
be triggered, the BD to be opened will be the first buffer descriptor since the Wrap flag
was set in the 3rd BD. It is the Arm platform responsibility to set the Done bit of all the
BD if it wants to use the same buffers.
7.2.6.1.2 Buffer Descriptor Commands for Bootload scripts
The command field of the buffer descriptor is defined separately for each script.
The following table lists the buffer descriptor commands defined for the channel 0
bootload script.
Table 7-56. Channel Zero Buffer Descriptor Commands
Command Command Description Buffer Address Extended Buffer
Address
Field
(binary)
0000_0001 C0_SET_DM Load SDMA data memory (RAM) from Arm Arm platform memory SDMA memory
platform memory buffer source address destination address
(0x01)
0000_0010 C0_GET_DM Copy SDMA data memory (RAM) to Arm Arm platform memory SDMA memory source
platform memory buffer destination address address
(0x02)
0000_0100 C0_SET_PM Load SDMA program memory (RAM) from Arm platform memory SDMA memory
Arm platform memory buffer source address destination address
(0x04)
0000_0110 C0_GET_PM Copy SDMA program memory (RAM) to Arm Arm platform memory SDMA memory source
platform memory buffer destination address address
(0x06)
cccc_c111 C0_SETCTX Load Context for channel cccc into SDMA Arm Platform memory -
RAM from Arm platform memory buffer source address
(0x07 | CHN)
cccc_c011 C0_GETCTXT Copy Context for channel ccccc from SDMA Arm platform memory -
RAM to Arm platform memory buffer destination address
(0x03 | CHN)
The Channel 0 bootload commands are summarized as follows:
• C0_SET_[PM-DM]: load the buffer descriptor data in the SDMA local memory at
the address pointed to by the "extended buffer address" field. The SDMA RAM can
be seen as a Program Memory (PM, 16-bit address) or Data Memory (DM 32-bit
address). When C0_SET_PM is used, the count field is expressed in "shorts" (16-bit
half words), this command can be used to download scripts. When C0_SET_DM is
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used, the count field is expressed in "long" (32-bit words), this command can be used
to download channel contexts to the context channel area in RAM.
• C0_GET_[PM-DM]: write to the buffer descriptor's data buffer the content of the
SDMA local memory from the address pointed to by the "extended buffer address"
field for the length defined by the count in the buffer descriptor. C0_GET_PM is
used to dump some part of the Program Memory (may be used to dump context of a
channel), therefore count is expressed in "shorts"; while C0_GET_DM is used to
dump to the buffer descriptor's data buffer, so the count field is in "longs."
• C0_SETCTX: load a context into the SDMA context page area. The handling script
decodes the channel number from the 5 MSB of the command field of the buffer
descriptor. Using the channel number the script computes the offset of the context
data pointer for the channel relative to the context page base to use as the destination
address in SDMA memory. Then the C0_SET_DM command explained above is
invoked to load SDMA RAM from memory. The counter indicates the size in words
of the context structure.
• Command value: (in binary) cccc c111, where ccccc is the channel number (5 bits).
For instance, 0x0F means set context for channel 1, 0xFF means set context for
channel 31.
• C0_GETCTX: write to the buffer descriptor's data buffer the content of the SDMA
context page area. The handling script decodes the channel number from the 5 MSB
of the command field of the buffer descriptor. Using this channel number, the script
computes the offset of the context data pointer for the channel relative to the context
page base to use as the source address for the copy. Then the C0_GET_DM
command explained above is invoked to copy the context to memory. The counter
indicates the size in words of the context structure.
• Command value: (in binary): cccc c011, where ccccc is the channel number (5 bits).
For instance, 0x03 means get context of channel 1, 0xFB means get context of
channel 31.
NOTE
To download channel context, C0_SETDM and
C0_SETCTXT command can be used but the second one is
easier because the channel number is embedded into the
command field, whereas with the C0_SETDM, the pointer
to the channel context area must be written into the
extended buffer address field of the buffer descriptor.
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7.2.6.1.3 Example of Buffer Descriptors for Channel 0.
Figure 7-19 illustrates the buffer descriptors that must be set in Arm platform memory
space, before execution of boot code, to download contexts and scripts of channels 1, 4,
and 10. After boot code execution, SDMA memory will be populated with the different
contexts and scripts as presented in the following figure.
SDMA RAM 0x800
0x820
Channel 1 Context
0x880
Channel 4 Context
0x960 Content
Channel 10 Context Area
0xC00
Channel 1 Script
Channel 4 Script
Scripts and Data
Area
Channel 10 Script
Figure 7-18. Example of SDMA RAM After Boot Session
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SDMA Register
MC0PTR
Channel Control Block
CurrentBDptr
Channel 0 Buffer Descriptor Array
BaseBDptr
chanDesc
status 31 24 23 22 21 20 19 18 17 16 15 0
00001111 0 0 1 0 1 20
Buffer Address
Extended Buffer Address (Unused)
00100111 0 0 1 0 1 20
BD1 - SET CONTEXT CH#1 Buffer Address
Interrupt = 0,
Cont=1, Done = 1
Extended Buffer Address (Unused)
BD2 - SET CONTEXT CH#4
Interrupt = 0, 01010111 0 0 1 0 1 20
Cont=1, Done = 1
Buffer Address
BD3 - SET CONTEXT CH#10
Interrupt = 0, Extended Buffer Address (Unused)
Cont=1, Done = 1
00000100 0 0 1 0 1 10
BD4 - SET_PM
Interrupt = 0, Buffer Address
Cont=1, Done = 1
Extended Buffer Address
BD5 - SET_PM
Interrupt = 0, 00000100 0 0 1 0 1 40
Cont=1, Done = 1
Buffer Address
BD6 - SET_PM
Interrupt = 1, Extended Buffer Address
Cont=0, Done = 1
00000100 0 1 0 0 1 50
Buffer Address
Extended Buffer Address
AP Memory Space
SDMA RAM Channel 1 context
(32 longs)
Channel 4 context
(32) longs)
Context Area
Channel 10 context
(32 longs)
Scripts Area
Channel 1 script
(16 shorts)
Channel 4 script
(64 shorts)
Channel 10 script
(80 shorts)
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7.2.6.1.4 Channel Context
There are 32 channel context memory structures pointed to by the local save area pointer.
These channel context memory structures are fixed.
The script in the SDMA computes the memory offset for a given channel based on the
structure length and channel number. Figure below shows the structure of the channel
context as it is saved in the SDMA local memory (RAM).
A channel context consists in 24 words, one per register. A total of 32 words are reserved
for every channel. The additional 8 words are called scratch ram and they are dedicated to
each channel. This memory area is commonly used for stack management.
The structure is divided in 4 areas:
• Channel status registers
• General purpose registers
• Functional units state registers reflecting the state of the Arm platform DMAs (Burst
and Peripheral DMA).
• Scratch RAM
The details of the channel context status registers are described in the following figure.
The PC field of the first long register must point to the SDMA RAM address where the
script that will be executed on the channel is located and this value equals the one stored
in the extended buffer address of the buffer descriptor with C0_SETPM command.
31 30 29 16 15 14 13 0
_ _
SF RPC T PC
_
LM EPC DF SPC
SF: Source fault while loading data
RPC: Return program counter
T: Test bit: status of arithmetic and test instructions
PC: Program counter
LM: Loop mode
EPC: Loop end program counter
DF: Destination fault while storing data
SPC: Loop Start program counter
Figure 7-20. SDMA State Registers (ShPC, ShLoop)
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7.2.6.2 Typical Data Transfer Supported by SDMA DMA Units
This section presents a library of SDMA scripts that perform data transfers through the
peripheral DMA and the burst DMA units.
The Arm platform memory and peripherals are devices that either the peripheral DMA or
the burst DMA can access. The scripts are given for a peripheral DMA whose address
registers are programmed in incremented mode when internal memory is involved. See
the following table for the summary.
Table 7-57. Typical Data Transfers Summary
Data Transfer Peripheral DMA Burst DMA Comments
Arm platform External Memory ↔ 3 Copy mode
Arm platform External Memory
Script example, see Burst DMA Unit Copy
Mode and External Memory to External
Memory.
Arm platform Peripheral ↔ Arm 3 Copy mode if same data path width
platform Peripheral
Script example, see Peripheral to Peripheral
Transfer.
Arm platform External Memory ↔ 3 3 Data transit through SDMA
Arm platform Peripheral
Script example, see Transfer Between
Peripheral and External Memory.
Arm platform External Memory ↔ 3 Copy mode
Arm platform Internal Memory
Script example, see Transfer Between
External Memory and Internal Memory.
Arm platform Internal Memory ↔ Arm 3 Copy mode
platform Internal Memory
Script example, see Internal Memory to
Internal Memory.
Arm platform Internal memory ↔ Arm 3 Data transit through SDMA
platform Peripheral
Script example, see Transfer Between
Peripheral and Internal Memory.
NOTE
These scripts are provided as examples of how to use DMA
blocks to perform required data transfers: They are not
"official" programs.
7.2.6.2.1 External Memory to External Memory
This section describes the SDMA script that performs data moves in external memory.
For this particular data transfer, only the burst DMA is used. It is programmed in copy
mode, so no data transmits through an SDMA general register.
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The SDMA core only monitors data transfer status. It is assumed source and destination
address values are already present in two SDMA general registers (r1 and r2). For this
example, it is also assumed that a 32-bit word-to-move for source-to-destination address
is present in r0 and equals 64.
Data Moves in External Memory
1 stf r1,MSA // Source address setup
2 stf r2,MDA // Destination address setup
3 ldi r0,0x64 // 64 words must be transferred from MSA to
MDA
4 ldi r1,0x8
MAIN_XFER:
5 cmphs r0,r1 // Is r0 >= 0x8
6 bf LAST_XFER // If not, jump to last transfer label
7 stf r1,MD|CPY // Copy 8 words from MSA to MDA address.
8 subi r0,0x8 // Decrement counter
9 jmp MAIN_XFER // return to main transfer loop
LAST_XFER:
10 stf r0,MD|CPY // perform last transfer
All instructions are performed in one cycle (jumps excepted). Instruction 7 triggers a
copy transfer: A read burst access of 8-word starts, data is staged in MD and then a write
burst of 8 words is executed. Instruction 8, 9, 5, and 6 are executed while the burst access
is in progress. If this access is not complete when instruction 7 is executed a second time,
SDMA stalls on this instruction as long as the previous copy transfer is not over. In this
case, the instruction is no longer a one-cycle instruction.
During the main loop (MAIN_XFER), r1 always equals 8, so burst lengths are 8 words.
On the last ldf |CPY instruction (10), r1 equals the reminder of r0 divided by 8; therefore,
the length of bursts triggered in copy mode equal r1 value, which is between 1 and 7.
7.2.6.2.2 Peripheral to Peripheral Transfer
For this data transfer, only the peripheral DMA is used.
It is programmed in copy mode, so no data will transmit through the SDMA general
register used in the ldf instruction, but the contents of the general register are lost. The
SDMA core only monitors the transfer.
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7.2.6.2.2.1 Source and Destination Target Have the Same Data Path Width
When the source and destination target have the same data path width, the following is
true:
• Source target is a half-word (16-bit) peripheral located at address 0x1002.
• Destination is a half-word (16-bit) peripheral located at address 0x2006.
It is assumed the address values are already present in two SDMA general registers (r1,
r2). The script for a transfer of 10 half-word is as follows:
Same Data Path Width for Source and Destination
//SETUP SECTION
1 stf r1, PSA|SZ16|F //r1=0x1002 Source address register setup
2 stf r2, PDA|SZ16|F //r2=0x2006 Destination address register
setup
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0xa //loop counter is 10
//MAIN LOOP TRANFER
copy_loop:
5 loop 2,0
6 ldf r7,PD|CPY //Reads 1 half-word from src and writes to
dest.
7 yield
8 bdf ERROR_DURING_XFER
ERROR_ADDR_SETUP:
//correction of PSA/PDA setup and jumps to main loop transfer
ERROR_DURING_XFER:
//flag error is set,
//PS can be read to know if error occurs during read or write access.
If a data transfer must occur between two word peripherals, only the setup section should
be updated. The transfer itself is always performed by the hardware loop instruction.
All instructions are executed in one cycle (change of flow excepted). On instruction 6, a
single read access is triggered, read data is staged in PD, and a write-to-destination is
executed. When the transfers are in progress, the SDMA can execute he next instructions
in parallel. If instruction 6, which performs the copy transfer, is executed while the
previous access is not over, SDMA is stalled and instruction ldf is a multi-cycle
instruction.
7.2.6.2.2.2 Source and Destination Target Have a Different Data Path Width
When the source and destination target have a different data path width, copy mode
cannot be used, and any attempt to initiate a copy transfer immediately raises an error,
which is stored in the SF flag.
The following example shows the SDMA code that could transfer 10 words from a word
(32-bit) peripheral to a half-word peripheral whose addresses are preliminary and stored
in r1 and r2.
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Different Data Path Width for Source and Destination
//SETUP SECTION
1 stf r1, PSA|SZ32|F|PF //r1=0x1000 and prefetch data
2 stf r2, PDA|SZ16|F //r2=0x2006
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0xa //loop counter is 10
//MAIN LOOP TRANFER
main_loop_xfer_16_16:
5 loop 6,0
6 ldf r7,PD //copy 32-bit of PD in r7
7 stf r7,PD //store 16 LSB of r7 in PD and a flush is
executed
8 rorb r7
9 rorb r7 //16 MSB --> 16 LSB
10 stf r7,PD //store 16 LSB of r6 in PD and a flush.
11 yield
On instruction 1, when the source address register is programmed and a data prefetch is
required, a read access is executed. In parallel, the SDMA executes instructions 2 to 5.
On instruction 6, the SDMA tries to read data that was fetched by instruction 1. If data is
ready, the ldf will be a one cycle instruction; otherwise, the SDMA is stalled as long as
the read access is not finished. Then, the 16 LSB of the read data is stored in PD and
automatically flushed to the destination peripheral. In parallel, the SDMA executes the
rotation instructions (8, 9), and stores the 16 MSB of the read data into PD. If a previous
write access is finished, instruction 10 will be a one-cycle instruction.
The main loop transfer may appear inefficient, but due to wait states imposed to the
peripheral DMA each time an external access is performed, a software pipeline is in
place. During the time needed to flush PD, the SDMA executes the move and rotation
operations. SDMA executes instructions in parallel with DMA accesses.
7.2.6.2.3 Transfer Between Peripheral and External Memory
7.2.6.2.3.1 Peripheral to External Memory Transfer
A transfer from a peripheral to the external memory controller involves the peripheral
DMA and the burst DMA.
The code for transferring 100 word from word peripheral to the external memory would
be as follows:
Peripheral to External Memory Transfer
//SETUP SECTION source and destination addresses are already in r1 and r2
1 stf r1, PSA|SZ16|F|PF //r1=0x1000 and prefetch 32-bit data
2 stf r2, MDA //r2=0x2000, setup burst DMA destination
address
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0x64 //loop counter is 100
5
//MAIN LOOP TRANFER
6 loop 3,0
7 ldf r1,PD|PF // read 32 bits of PD and initiate a new read
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access.
8 stf r1,MD|32 // store 32 bits of r1 in the MD fifo.
9 yield
10 ldf r1,PD // last word data is read
11 stf r1,MD|32|FL // to flush all remaining bytes of MD
On instruction 1, the source address register of the peripheral DMA is programmed and
data is fetched. This data is stored in PD and the SDMA reads PD during instruction 7,
which is a one-cycle instruction that is read-access finished. On the same instruction (7),
a data prefetch is required and a read access to the source peripheral is executed. In
parallel, the SDMA stored the previous read data into the data register of MD. When MD
(which is an eight-word FIFO) is full, a burst write access is executed to empty the FIFO.
As long as the next SDMA instructions do not access the burst DMA, they will be one-
cycle instructions. The following figures show how the peripheral DMA and burst DMA
work in parallel.
1 2 3
Clk
SDMA
ldf PD stf MD yield ldf PD stf MD yield Idf PD stf MD yield
Instruction
peripheral
data 0 data 1
DMA port
1 wait state 2 wait states
PD data -1 data 0 data 1
r1 data -1 data 0 data 1
MD data -1 data -1 data -1
data 0 data 0
data 1
Figure 7-21. Peripheral to External Memory Example (1)
As seen in the figure above, the read access triggered by the ldf PD instruction is
symbolized by the blue bar when in progress. After wait states, the read data (data 0, data
1) is stored in PD on the clk rising edge. On edge 2, data 0 is available in PD so it can be
transferred to the SDMA general register r1, and then stored in MD FIFO. On edge 3,
data 1 is not in PD; therefore, SDMA is stalled on the ldf instruction, which lasts two
cycles. The figure below shows an example of when MD FIFO is full with data.
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1 2 3
Clk
SDMA
ldf PD stf MD yield ldf PD stf MD yield Idf PD stf MD
Instruction
peripheral
data 8 data9
DMA port
8-word burst
Burst DMA
4 wait-states ack ack ack ack
port
PD data 7 data 8 data 9
r1 data 7 data 8 data 9
MD
data 0 data 1 data 2 data 3
data 1 data 2 data 3 data 4
data 2 data 3 data 4 data 5
data 3 data 4 data 5 data 6
data 4 data 5 data 6 data 7
data 5 data 6 data 7 data 8
data 6 data 7 data 8
data 7 data 8
Figure 7-22. Peripheral to External Memory Example (2)
In the previous figure, the write bar means the burst DMA is performing a write burst
access. The latency to have the first write acknowledge is four cycles. SDMA is stalled
on instruction stf because no acknowledge was received, MD FIFO is full, and there is no
empty slot to store data 9. When an acknowledge is sampled by the burst DMA, FIFO is
shifted and data 8 is written. As long as there is at least one empty slot in MD FIFO, the
stf MD instruction lasts one cycle.
7.2.6.2.3.2 External Memory to Peripheral Transfer
A transfer from the external memory to a peripheral involves the peripheral DMA and the
burst DMA.
The code for transferring 100 word from external memory to a word peripheral would be
as follows:
External Memory to Peripheral Transfer
//SETUP SECTION source and destination addresses are already in r1 and r2
1 stf r1, MSA|PF //r1=0x1000 and starts a 8-word read burst
2 stf r2, PDA|SZ32|P //r2=0x2010, setup peripheral DMA destination address
3 bdf ERROR_ADDR_SETUP
4 ldi r0,0x64 //loop counter is 100
//MAIN LOOP TRANFER
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6 loop 3,0
7 ldf r1,MD|32|PF // read 32 bits of MD and initiate a new read access
// if MD is empty after this reading.
8 stf r1,PD // store 32 bits of r1 in the PD.
9 yield
10 ldf r1,MD|32 // last word data is read
11 stf r1,PD // last write access
On instruction 1, a read burst of 8 words begins. Read data is staged into MD. On
instruction 7 (and if data is available in MD), 32 bits are copied into r1. Then instruction
8 writes them into PD and an automatic flush is executed. The SDMA core, peripheral
DMA, and burst DMA can work in parallel as long as no SDMA instruction tries to start
a new write access on the peripheral DMA while the previous access is still in progress,
or as long as there is data in MD when the SDMA tries to read it.
7.2.6.2.4 Transfer Between External Memory and Internal Memory
Since the internal memory (Arm platform RAM) is accessed via the peripheral DMA and
the external memory is accessed via the burst DMA, the SDMA scripts that are described
in Transfer Between Peripheral and External Memory can be reused. The exception is
that the peripheral DMA address registers (PSA or PDA, depending on the script) should
be programmed in incremented mode rather than frozen mode.
7.2.6.2.4.1 Internal Memory to Internal Memory
The internal memory can only be accessed via the peripheral DMA, so the script
described in Peripheral to Peripheral Transfer can be reused with a different
programming of the peripheral DMA address registers.
7.2.6.2.4.2 Transfer Between Peripheral and Internal Memory
For this transfer, the peripheral DMA is also used in copy mode.
The SDMA script is very similar to the one described in Peripheral to Peripheral
Transfer, except for the peripheral DMA address registers programming.
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Chapter 7 Interrupts and DMA
7.2.7 Arm Platform Memory Map and Control Register Definitions
The Arm platform controls the SDMA by means of several interface registers. Those
registers are described in the current section.
All registers are clocked with the SDMA clock (which means the Arm platform must
ensure that the SDMA clock is running when it wants to access any register).
SDMAARM memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30BD_0000 Arm platform Channel 0 Pointer (SDMAARM1_MC0PTR) 32 R/W 0000_0000h 7.2.7.1/1220
30BD_0004 Channel Interrupts (SDMAARM1_INTR) 32 w1c 0000_0000h 7.2.7.2/1220
30BD_0008 Channel Stop/Channel Status (SDMAARM1_STOP_STAT) 32 w1c 0000_0000h 7.2.7.3/1220
30BD_000C Channel Start (SDMAARM1_HSTART) 32 R/W 0000_0000h 7.2.7.4/1221
30BD_0010 Channel Event Override (SDMAARM1_EVTOVR) 32 R/W 0000_0000h 7.2.7.5/1221
30BD_0014 Channel BP Override (SDMAARM1_DSPOVR) 32 R/W FFFF_FFFFh 7.2.7.6/1222
30BD_0018 Channel Arm platform Override (SDMAARM1_HOSTOVR) 32 R/W 0000_0000h 7.2.7.7/1222
30BD_001C Channel Event Pending (SDMAARM1_EVTPEND) 32 w1c 0000_0000h 7.2.7.8/1222
30BD_0024 Reset Register (SDMAARM1_RESET) 32 R 0000_0000h 7.2.7.9/1223
7.2.7.10/
30BD_0028 DMA Request Error Register (SDMAARM1_EVTERR) 32 R 0000_0000h
1224
Channel Arm platform Interrupt Mask 7.2.7.11/
30BD_002C 32 R/W 0000_0000h
(SDMAARM1_INTRMASK) 1224
7.2.7.12/
30BD_0030 Schedule Status (SDMAARM1_PSW) 32 R 0000_0000h
1225
7.2.7.13/
30BD_0034 DMA Request Error Register (SDMAARM1_EVTERRDBG) 32 R 0000_0000h
1225
7.2.7.14/
30BD_0038 Configuration Register (SDMAARM1_CONFIG) 32 R/W 0000_0003h
1226
7.2.7.15/
30BD_003C SDMA LOCK (SDMAARM1_SDMA_LOCK) 32 R/W 0000_0000h
1227
7.2.7.16/
30BD_0040 OnCE Enable (SDMAARM1_ONCE_ENB) 32 R/W 0000_0000h
1228
7.2.7.17/
30BD_0044 OnCE Data Register (SDMAARM1_ONCE_DATA) 32 R/W 0000_0000h
1228
7.2.7.18/
30BD_0048 OnCE Instruction Register (SDMAARM1_ONCE_INSTR) 32 R/W 0000_0000h
1229
7.2.7.19/
30BD_004C OnCE Status Register (SDMAARM1_ONCE_STAT) 32 R 0000_E000h
1229
Table continues on the next page...
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SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.20/
30BD_0050 OnCE Command Register (SDMAARM1_ONCE_CMD) 32 R/W 0000_0000h
1231
Illegal Instruction Trap Address 7.2.7.21/
30BD_0058 32 R/W 0000_0001h
(SDMAARM1_ILLINSTADDR) 1231
7.2.7.22/
30BD_005C Channel 0 Boot Address (SDMAARM1_CHN0ADDR) 32 R/W 0000_0050h
1232
7.2.7.23/
30BD_0060 DMA Requests (SDMAARM1_EVT_MIRROR) 32 R 0000_0000h
1233
7.2.7.24/
30BD_0064 DMA Requests 2 (SDMAARM1_EVT_MIRROR2) 32 R 0000_0000h
1233
Cross-Trigger Events Configuration Register 1 7.2.7.25/
30BD_0070 32 R/W 0000_0000h
(SDMAARM1_XTRIG_CONF1) 1234
Cross-Trigger Events Configuration Register 2 7.2.7.26/
30BD_0074 32 R/W 0000_0000h
(SDMAARM1_XTRIG_CONF2) 1235
7.2.7.27/
30BD_0100 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI0) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0104 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI1) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0108 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI2) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_010C Channel Priority Registers (SDMAARM1_SDMA_CHNPRI3) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0110 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI4) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0114 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI5) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0118 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI6) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_011C Channel Priority Registers (SDMAARM1_SDMA_CHNPRI7) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0120 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI8) 32 R/W 0000_0000h
1236
7.2.7.27/
30BD_0124 Channel Priority Registers (SDMAARM1_SDMA_CHNPRI9) 32 R/W 0000_0000h
1236
Channel Priority Registers 7.2.7.27/
30BD_0128 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI10) 1236
Channel Priority Registers 7.2.7.27/
30BD_012C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI11) 1236
Channel Priority Registers 7.2.7.27/
30BD_0130 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI12) 1236
Channel Priority Registers 7.2.7.27/
30BD_0134 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI13) 1236
Channel Priority Registers 7.2.7.27/
30BD_0138 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI14) 1236
Table continues on the next page...
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Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.7.27/
30BD_013C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI15) 1236
Channel Priority Registers 7.2.7.27/
30BD_0140 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI16) 1236
Channel Priority Registers 7.2.7.27/
30BD_0144 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI17) 1236
Channel Priority Registers 7.2.7.27/
30BD_0148 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI18) 1236
Channel Priority Registers 7.2.7.27/
30BD_014C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI19) 1236
Channel Priority Registers 7.2.7.27/
30BD_0150 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI20) 1236
Channel Priority Registers 7.2.7.27/
30BD_0154 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI21) 1236
Channel Priority Registers 7.2.7.27/
30BD_0158 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI22) 1236
Channel Priority Registers 7.2.7.27/
30BD_015C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI23) 1236
Channel Priority Registers 7.2.7.27/
30BD_0160 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI24) 1236
Channel Priority Registers 7.2.7.27/
30BD_0164 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI25) 1236
Channel Priority Registers 7.2.7.27/
30BD_0168 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI26) 1236
Channel Priority Registers 7.2.7.27/
30BD_016C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI27) 1236
Channel Priority Registers 7.2.7.27/
30BD_0170 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI28) 1236
Channel Priority Registers 7.2.7.27/
30BD_0174 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI29) 1236
Channel Priority Registers 7.2.7.27/
30BD_0178 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI30) 1236
Channel Priority Registers 7.2.7.27/
30BD_017C 32 R/W 0000_0000h
(SDMAARM1_SDMA_CHNPRI31) 1236
7.2.7.28/
30BD_0200 Channel Enable RAM (SDMAARM1_CHNENBL0) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0204 Channel Enable RAM (SDMAARM1_CHNENBL1) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0208 Channel Enable RAM (SDMAARM1_CHNENBL2) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_020C Channel Enable RAM (SDMAARM1_CHNENBL3) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0210 Channel Enable RAM (SDMAARM1_CHNENBL4) 32 R/W 0000_0000h
1237
Table continues on the next page...
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SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30BD_0214 Channel Enable RAM (SDMAARM1_CHNENBL5) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0218 Channel Enable RAM (SDMAARM1_CHNENBL6) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_021C Channel Enable RAM (SDMAARM1_CHNENBL7) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0220 Channel Enable RAM (SDMAARM1_CHNENBL8) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0224 Channel Enable RAM (SDMAARM1_CHNENBL9) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0228 Channel Enable RAM (SDMAARM1_CHNENBL10) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_022C Channel Enable RAM (SDMAARM1_CHNENBL11) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0230 Channel Enable RAM (SDMAARM1_CHNENBL12) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0234 Channel Enable RAM (SDMAARM1_CHNENBL13) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0238 Channel Enable RAM (SDMAARM1_CHNENBL14) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_023C Channel Enable RAM (SDMAARM1_CHNENBL15) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0240 Channel Enable RAM (SDMAARM1_CHNENBL16) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0244 Channel Enable RAM (SDMAARM1_CHNENBL17) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0248 Channel Enable RAM (SDMAARM1_CHNENBL18) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_024C Channel Enable RAM (SDMAARM1_CHNENBL19) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0250 Channel Enable RAM (SDMAARM1_CHNENBL20) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0254 Channel Enable RAM (SDMAARM1_CHNENBL21) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0258 Channel Enable RAM (SDMAARM1_CHNENBL22) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_025C Channel Enable RAM (SDMAARM1_CHNENBL23) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0260 Channel Enable RAM (SDMAARM1_CHNENBL24) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0264 Channel Enable RAM (SDMAARM1_CHNENBL25) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0268 Channel Enable RAM (SDMAARM1_CHNENBL26) 32 R/W 0000_0000h
1237
Table continues on the next page...
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Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30BD_026C Channel Enable RAM (SDMAARM1_CHNENBL27) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0270 Channel Enable RAM (SDMAARM1_CHNENBL28) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0274 Channel Enable RAM (SDMAARM1_CHNENBL29) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0278 Channel Enable RAM (SDMAARM1_CHNENBL30) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_027C Channel Enable RAM (SDMAARM1_CHNENBL31) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0280 Channel Enable RAM (SDMAARM1_CHNENBL32) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0284 Channel Enable RAM (SDMAARM1_CHNENBL33) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0288 Channel Enable RAM (SDMAARM1_CHNENBL34) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_028C Channel Enable RAM (SDMAARM1_CHNENBL35) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0290 Channel Enable RAM (SDMAARM1_CHNENBL36) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0294 Channel Enable RAM (SDMAARM1_CHNENBL37) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_0298 Channel Enable RAM (SDMAARM1_CHNENBL38) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_029C Channel Enable RAM (SDMAARM1_CHNENBL39) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02A0 Channel Enable RAM (SDMAARM1_CHNENBL40) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02A4 Channel Enable RAM (SDMAARM1_CHNENBL41) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02A8 Channel Enable RAM (SDMAARM1_CHNENBL42) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02AC Channel Enable RAM (SDMAARM1_CHNENBL43) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02B0 Channel Enable RAM (SDMAARM1_CHNENBL44) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02B4 Channel Enable RAM (SDMAARM1_CHNENBL45) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02B8 Channel Enable RAM (SDMAARM1_CHNENBL46) 32 R/W 0000_0000h
1237
7.2.7.28/
30BD_02BC Channel Enable RAM (SDMAARM1_CHNENBL47) 32 R/W 0000_0000h
1237
SDMA DONE0 Configuration 7.2.7.29/
30BD_1000 32 R/W 1F1F_1F1Fh
(SDMAARM1_DONE0_CONFIG) 1237
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1159
Smart Direct Memory Access Controller (SDMA)
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SDMA DONE1 Configuration 7.2.7.30/
30BD_1004 32 R/W 1F1F_1F1Fh
(SDMAARM1_DONE1_CONFIG) 1239
30E0_0000 Arm platform Channel 0 Pointer (SDMAARM3_MC0PTR) 32 R/W 0000_0000h 7.2.7.1/1220
30E0_0004 Channel Interrupts (SDMAARM3_INTR) 32 w1c 0000_0000h 7.2.7.2/1220
30E0_0008 Channel Stop/Channel Status (SDMAARM3_STOP_STAT) 32 w1c 0000_0000h 7.2.7.3/1220
30E0_000C Channel Start (SDMAARM3_HSTART) 32 R/W 0000_0000h 7.2.7.4/1221
30E0_0010 Channel Event Override (SDMAARM3_EVTOVR) 32 R/W 0000_0000h 7.2.7.5/1221
30E0_0014 Channel BP Override (SDMAARM3_DSPOVR) 32 R/W FFFF_FFFFh 7.2.7.6/1222
30E0_0018 Channel Arm platform Override (SDMAARM3_HOSTOVR) 32 R/W 0000_0000h 7.2.7.7/1222
30E0_001C Channel Event Pending (SDMAARM3_EVTPEND) 32 w1c 0000_0000h 7.2.7.8/1222
30E0_0024 Reset Register (SDMAARM3_RESET) 32 R 0000_0000h 7.2.7.9/1223
7.2.7.10/
30E0_0028 DMA Request Error Register (SDMAARM3_EVTERR) 32 R 0000_0000h
1224
Channel Arm platform Interrupt Mask 7.2.7.11/
30E0_002C 32 R/W 0000_0000h
(SDMAARM3_INTRMASK) 1224
7.2.7.12/
30E0_0030 Schedule Status (SDMAARM3_PSW) 32 R 0000_0000h
1225
7.2.7.13/
30E0_0034 DMA Request Error Register (SDMAARM3_EVTERRDBG) 32 R 0000_0000h
1225
7.2.7.14/
30E0_0038 Configuration Register (SDMAARM3_CONFIG) 32 R/W 0000_0003h
1226
7.2.7.15/
30E0_003C SDMA LOCK (SDMAARM3_SDMA_LOCK) 32 R/W 0000_0000h
1227
7.2.7.16/
30E0_0040 OnCE Enable (SDMAARM3_ONCE_ENB) 32 R/W 0000_0000h
1228
7.2.7.17/
30E0_0044 OnCE Data Register (SDMAARM3_ONCE_DATA) 32 R/W 0000_0000h
1228
7.2.7.18/
30E0_0048 OnCE Instruction Register (SDMAARM3_ONCE_INSTR) 32 R/W 0000_0000h
1229
7.2.7.19/
30E0_004C OnCE Status Register (SDMAARM3_ONCE_STAT) 32 R 0000_E000h
1229
7.2.7.20/
30E0_0050 OnCE Command Register (SDMAARM3_ONCE_CMD) 32 R/W 0000_0000h
1231
Illegal Instruction Trap Address 7.2.7.21/
30E0_0058 32 R/W 0000_0001h
(SDMAARM3_ILLINSTADDR) 1231
7.2.7.22/
30E0_005C Channel 0 Boot Address (SDMAARM3_CHN0ADDR) 32 R/W 0000_0050h
1232
7.2.7.23/
30E0_0060 DMA Requests (SDMAARM3_EVT_MIRROR) 32 R 0000_0000h
1233
7.2.7.24/
30E0_0064 DMA Requests 2 (SDMAARM3_EVT_MIRROR2) 32 R 0000_0000h
1233
Cross-Trigger Events Configuration Register 1 7.2.7.25/
30E0_0070 32 R/W 0000_0000h
(SDMAARM3_XTRIG_CONF1) 1234
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1160 NXP Semiconductors
Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Cross-Trigger Events Configuration Register 2 7.2.7.26/
30E0_0074 32 R/W 0000_0000h
(SDMAARM3_XTRIG_CONF2) 1235
7.2.7.27/
30E0_0100 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI0) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0104 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI1) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0108 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI2) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_010C Channel Priority Registers (SDMAARM3_SDMA_CHNPRI3) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0110 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI4) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0114 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI5) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0118 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI6) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_011C Channel Priority Registers (SDMAARM3_SDMA_CHNPRI7) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0120 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI8) 32 R/W 0000_0000h
1236
7.2.7.27/
30E0_0124 Channel Priority Registers (SDMAARM3_SDMA_CHNPRI9) 32 R/W 0000_0000h
1236
Channel Priority Registers 7.2.7.27/
30E0_0128 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI10) 1236
Channel Priority Registers 7.2.7.27/
30E0_012C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI11) 1236
Channel Priority Registers 7.2.7.27/
30E0_0130 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI12) 1236
Channel Priority Registers 7.2.7.27/
30E0_0134 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI13) 1236
Channel Priority Registers 7.2.7.27/
30E0_0138 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI14) 1236
Channel Priority Registers 7.2.7.27/
30E0_013C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI15) 1236
Channel Priority Registers 7.2.7.27/
30E0_0140 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI16) 1236
Channel Priority Registers 7.2.7.27/
30E0_0144 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI17) 1236
Channel Priority Registers 7.2.7.27/
30E0_0148 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI18) 1236
Channel Priority Registers 7.2.7.27/
30E0_014C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI19) 1236
Channel Priority Registers 7.2.7.27/
30E0_0150 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI20) 1236
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1161
Smart Direct Memory Access Controller (SDMA)
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.7.27/
30E0_0154 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI21) 1236
Channel Priority Registers 7.2.7.27/
30E0_0158 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI22) 1236
Channel Priority Registers 7.2.7.27/
30E0_015C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI23) 1236
Channel Priority Registers 7.2.7.27/
30E0_0160 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI24) 1236
Channel Priority Registers 7.2.7.27/
30E0_0164 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI25) 1236
Channel Priority Registers 7.2.7.27/
30E0_0168 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI26) 1236
Channel Priority Registers 7.2.7.27/
30E0_016C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI27) 1236
Channel Priority Registers 7.2.7.27/
30E0_0170 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI28) 1236
Channel Priority Registers 7.2.7.27/
30E0_0174 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI29) 1236
Channel Priority Registers 7.2.7.27/
30E0_0178 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI30) 1236
Channel Priority Registers 7.2.7.27/
30E0_017C 32 R/W 0000_0000h
(SDMAARM3_SDMA_CHNPRI31) 1236
7.2.7.28/
30E0_0200 Channel Enable RAM (SDMAARM3_CHNENBL0) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0204 Channel Enable RAM (SDMAARM3_CHNENBL1) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0208 Channel Enable RAM (SDMAARM3_CHNENBL2) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_020C Channel Enable RAM (SDMAARM3_CHNENBL3) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0210 Channel Enable RAM (SDMAARM3_CHNENBL4) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0214 Channel Enable RAM (SDMAARM3_CHNENBL5) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0218 Channel Enable RAM (SDMAARM3_CHNENBL6) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_021C Channel Enable RAM (SDMAARM3_CHNENBL7) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0220 Channel Enable RAM (SDMAARM3_CHNENBL8) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0224 Channel Enable RAM (SDMAARM3_CHNENBL9) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0228 Channel Enable RAM (SDMAARM3_CHNENBL10) 32 R/W 0000_0000h
1237
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1162 NXP Semiconductors
Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30E0_022C Channel Enable RAM (SDMAARM3_CHNENBL11) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0230 Channel Enable RAM (SDMAARM3_CHNENBL12) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0234 Channel Enable RAM (SDMAARM3_CHNENBL13) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0238 Channel Enable RAM (SDMAARM3_CHNENBL14) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_023C Channel Enable RAM (SDMAARM3_CHNENBL15) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0240 Channel Enable RAM (SDMAARM3_CHNENBL16) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0244 Channel Enable RAM (SDMAARM3_CHNENBL17) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0248 Channel Enable RAM (SDMAARM3_CHNENBL18) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_024C Channel Enable RAM (SDMAARM3_CHNENBL19) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0250 Channel Enable RAM (SDMAARM3_CHNENBL20) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0254 Channel Enable RAM (SDMAARM3_CHNENBL21) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0258 Channel Enable RAM (SDMAARM3_CHNENBL22) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_025C Channel Enable RAM (SDMAARM3_CHNENBL23) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0260 Channel Enable RAM (SDMAARM3_CHNENBL24) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0264 Channel Enable RAM (SDMAARM3_CHNENBL25) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0268 Channel Enable RAM (SDMAARM3_CHNENBL26) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_026C Channel Enable RAM (SDMAARM3_CHNENBL27) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0270 Channel Enable RAM (SDMAARM3_CHNENBL28) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0274 Channel Enable RAM (SDMAARM3_CHNENBL29) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0278 Channel Enable RAM (SDMAARM3_CHNENBL30) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_027C Channel Enable RAM (SDMAARM3_CHNENBL31) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0280 Channel Enable RAM (SDMAARM3_CHNENBL32) 32 R/W 0000_0000h
1237
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1163
Smart Direct Memory Access Controller (SDMA)
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30E0_0284 Channel Enable RAM (SDMAARM3_CHNENBL33) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0288 Channel Enable RAM (SDMAARM3_CHNENBL34) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_028C Channel Enable RAM (SDMAARM3_CHNENBL35) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0290 Channel Enable RAM (SDMAARM3_CHNENBL36) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0294 Channel Enable RAM (SDMAARM3_CHNENBL37) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_0298 Channel Enable RAM (SDMAARM3_CHNENBL38) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_029C Channel Enable RAM (SDMAARM3_CHNENBL39) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02A0 Channel Enable RAM (SDMAARM3_CHNENBL40) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02A4 Channel Enable RAM (SDMAARM3_CHNENBL41) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02A8 Channel Enable RAM (SDMAARM3_CHNENBL42) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02AC Channel Enable RAM (SDMAARM3_CHNENBL43) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02B0 Channel Enable RAM (SDMAARM3_CHNENBL44) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02B4 Channel Enable RAM (SDMAARM3_CHNENBL45) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02B8 Channel Enable RAM (SDMAARM3_CHNENBL46) 32 R/W 0000_0000h
1237
7.2.7.28/
30E0_02BC Channel Enable RAM (SDMAARM3_CHNENBL47) 32 R/W 0000_0000h
1237
SDMA DONE0 Configuration 7.2.7.29/
30E0_1000 32 R/W 1F1F_1F1Fh
(SDMAARM3_DONE0_CONFIG) 1237
SDMA DONE1 Configuration 7.2.7.30/
30E0_1004 32 R/W 1F1F_1F1Fh
(SDMAARM3_DONE1_CONFIG) 1239
30E1_0000 Arm platform Channel 0 Pointer (SDMAARM2_MC0PTR) 32 R/W 0000_0000h 7.2.7.1/1220
30E1_0004 Channel Interrupts (SDMAARM2_INTR) 32 w1c 0000_0000h 7.2.7.2/1220
30E1_0008 Channel Stop/Channel Status (SDMAARM2_STOP_STAT) 32 w1c 0000_0000h 7.2.7.3/1220
30E1_000C Channel Start (SDMAARM2_HSTART) 32 R/W 0000_0000h 7.2.7.4/1221
30E1_0010 Channel Event Override (SDMAARM2_EVTOVR) 32 R/W 0000_0000h 7.2.7.5/1221
30E1_0014 Channel BP Override (SDMAARM2_DSPOVR) 32 R/W FFFF_FFFFh 7.2.7.6/1222
30E1_0018 Channel Arm platform Override (SDMAARM2_HOSTOVR) 32 R/W 0000_0000h 7.2.7.7/1222
30E1_001C Channel Event Pending (SDMAARM2_EVTPEND) 32 w1c 0000_0000h 7.2.7.8/1222
30E1_0024 Reset Register (SDMAARM2_RESET) 32 R 0000_0000h 7.2.7.9/1223
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1164 NXP Semiconductors
Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.10/
30E1_0028 DMA Request Error Register (SDMAARM2_EVTERR) 32 R 0000_0000h
1224
Channel Arm platform Interrupt Mask 7.2.7.11/
30E1_002C 32 R/W 0000_0000h
(SDMAARM2_INTRMASK) 1224
7.2.7.12/
30E1_0030 Schedule Status (SDMAARM2_PSW) 32 R 0000_0000h
1225
7.2.7.13/
30E1_0034 DMA Request Error Register (SDMAARM2_EVTERRDBG) 32 R 0000_0000h
1225
7.2.7.14/
30E1_0038 Configuration Register (SDMAARM2_CONFIG) 32 R/W 0000_0003h
1226
7.2.7.15/
30E1_003C SDMA LOCK (SDMAARM2_SDMA_LOCK) 32 R/W 0000_0000h
1227
7.2.7.16/
30E1_0040 OnCE Enable (SDMAARM2_ONCE_ENB) 32 R/W 0000_0000h
1228
7.2.7.17/
30E1_0044 OnCE Data Register (SDMAARM2_ONCE_DATA) 32 R/W 0000_0000h
1228
7.2.7.18/
30E1_0048 OnCE Instruction Register (SDMAARM2_ONCE_INSTR) 32 R/W 0000_0000h
1229
7.2.7.19/
30E1_004C OnCE Status Register (SDMAARM2_ONCE_STAT) 32 R 0000_E000h
1229
7.2.7.20/
30E1_0050 OnCE Command Register (SDMAARM2_ONCE_CMD) 32 R/W 0000_0000h
1231
Illegal Instruction Trap Address 7.2.7.21/
30E1_0058 32 R/W 0000_0001h
(SDMAARM2_ILLINSTADDR) 1231
7.2.7.22/
30E1_005C Channel 0 Boot Address (SDMAARM2_CHN0ADDR) 32 R/W 0000_0050h
1232
7.2.7.23/
30E1_0060 DMA Requests (SDMAARM2_EVT_MIRROR) 32 R 0000_0000h
1233
7.2.7.24/
30E1_0064 DMA Requests 2 (SDMAARM2_EVT_MIRROR2) 32 R 0000_0000h
1233
Cross-Trigger Events Configuration Register 1 7.2.7.25/
30E1_0070 32 R/W 0000_0000h
(SDMAARM2_XTRIG_CONF1) 1234
Cross-Trigger Events Configuration Register 2 7.2.7.26/
30E1_0074 32 R/W 0000_0000h
(SDMAARM2_XTRIG_CONF2) 1235
7.2.7.27/
30E1_0100 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI0) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0104 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI1) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0108 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI2) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_010C Channel Priority Registers (SDMAARM2_SDMA_CHNPRI3) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0110 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI4) 32 R/W 0000_0000h
1236
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1165
Smart Direct Memory Access Controller (SDMA)
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.27/
30E1_0114 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI5) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0118 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI6) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_011C Channel Priority Registers (SDMAARM2_SDMA_CHNPRI7) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0120 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI8) 32 R/W 0000_0000h
1236
7.2.7.27/
30E1_0124 Channel Priority Registers (SDMAARM2_SDMA_CHNPRI9) 32 R/W 0000_0000h
1236
Channel Priority Registers 7.2.7.27/
30E1_0128 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI10) 1236
Channel Priority Registers 7.2.7.27/
30E1_012C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI11) 1236
Channel Priority Registers 7.2.7.27/
30E1_0130 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI12) 1236
Channel Priority Registers 7.2.7.27/
30E1_0134 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI13) 1236
Channel Priority Registers 7.2.7.27/
30E1_0138 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI14) 1236
Channel Priority Registers 7.2.7.27/
30E1_013C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI15) 1236
Channel Priority Registers 7.2.7.27/
30E1_0140 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI16) 1236
Channel Priority Registers 7.2.7.27/
30E1_0144 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI17) 1236
Channel Priority Registers 7.2.7.27/
30E1_0148 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI18) 1236
Channel Priority Registers 7.2.7.27/
30E1_014C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI19) 1236
Channel Priority Registers 7.2.7.27/
30E1_0150 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI20) 1236
Channel Priority Registers 7.2.7.27/
30E1_0154 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI21) 1236
Channel Priority Registers 7.2.7.27/
30E1_0158 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI22) 1236
Channel Priority Registers 7.2.7.27/
30E1_015C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI23) 1236
Channel Priority Registers 7.2.7.27/
30E1_0160 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI24) 1236
Channel Priority Registers 7.2.7.27/
30E1_0164 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI25) 1236
Channel Priority Registers 7.2.7.27/
30E1_0168 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI26) 1236
Table continues on the next page...
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Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
Channel Priority Registers 7.2.7.27/
30E1_016C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI27) 1236
Channel Priority Registers 7.2.7.27/
30E1_0170 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI28) 1236
Channel Priority Registers 7.2.7.27/
30E1_0174 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI29) 1236
Channel Priority Registers 7.2.7.27/
30E1_0178 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI30) 1236
Channel Priority Registers 7.2.7.27/
30E1_017C 32 R/W 0000_0000h
(SDMAARM2_SDMA_CHNPRI31) 1236
7.2.7.28/
30E1_0200 Channel Enable RAM (SDMAARM2_CHNENBL0) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0204 Channel Enable RAM (SDMAARM2_CHNENBL1) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0208 Channel Enable RAM (SDMAARM2_CHNENBL2) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_020C Channel Enable RAM (SDMAARM2_CHNENBL3) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0210 Channel Enable RAM (SDMAARM2_CHNENBL4) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0214 Channel Enable RAM (SDMAARM2_CHNENBL5) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0218 Channel Enable RAM (SDMAARM2_CHNENBL6) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_021C Channel Enable RAM (SDMAARM2_CHNENBL7) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0220 Channel Enable RAM (SDMAARM2_CHNENBL8) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0224 Channel Enable RAM (SDMAARM2_CHNENBL9) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0228 Channel Enable RAM (SDMAARM2_CHNENBL10) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_022C Channel Enable RAM (SDMAARM2_CHNENBL11) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0230 Channel Enable RAM (SDMAARM2_CHNENBL12) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0234 Channel Enable RAM (SDMAARM2_CHNENBL13) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0238 Channel Enable RAM (SDMAARM2_CHNENBL14) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_023C Channel Enable RAM (SDMAARM2_CHNENBL15) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0240 Channel Enable RAM (SDMAARM2_CHNENBL16) 32 R/W 0000_0000h
1237
Table continues on the next page...
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Smart Direct Memory Access Controller (SDMA)
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30E1_0244 Channel Enable RAM (SDMAARM2_CHNENBL17) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0248 Channel Enable RAM (SDMAARM2_CHNENBL18) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_024C Channel Enable RAM (SDMAARM2_CHNENBL19) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0250 Channel Enable RAM (SDMAARM2_CHNENBL20) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0254 Channel Enable RAM (SDMAARM2_CHNENBL21) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0258 Channel Enable RAM (SDMAARM2_CHNENBL22) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_025C Channel Enable RAM (SDMAARM2_CHNENBL23) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0260 Channel Enable RAM (SDMAARM2_CHNENBL24) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0264 Channel Enable RAM (SDMAARM2_CHNENBL25) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0268 Channel Enable RAM (SDMAARM2_CHNENBL26) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_026C Channel Enable RAM (SDMAARM2_CHNENBL27) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0270 Channel Enable RAM (SDMAARM2_CHNENBL28) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0274 Channel Enable RAM (SDMAARM2_CHNENBL29) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0278 Channel Enable RAM (SDMAARM2_CHNENBL30) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_027C Channel Enable RAM (SDMAARM2_CHNENBL31) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0280 Channel Enable RAM (SDMAARM2_CHNENBL32) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0284 Channel Enable RAM (SDMAARM2_CHNENBL33) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0288 Channel Enable RAM (SDMAARM2_CHNENBL34) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_028C Channel Enable RAM (SDMAARM2_CHNENBL35) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0290 Channel Enable RAM (SDMAARM2_CHNENBL36) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0294 Channel Enable RAM (SDMAARM2_CHNENBL37) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_0298 Channel Enable RAM (SDMAARM2_CHNENBL38) 32 R/W 0000_0000h
1237
Table continues on the next page...
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Chapter 7 Interrupts and DMA
SDMAARM memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.7.28/
30E1_029C Channel Enable RAM (SDMAARM2_CHNENBL39) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02A0 Channel Enable RAM (SDMAARM2_CHNENBL40) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02A4 Channel Enable RAM (SDMAARM2_CHNENBL41) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02A8 Channel Enable RAM (SDMAARM2_CHNENBL42) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02AC Channel Enable RAM (SDMAARM2_CHNENBL43) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02B0 Channel Enable RAM (SDMAARM2_CHNENBL44) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02B4 Channel Enable RAM (SDMAARM2_CHNENBL45) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02B8 Channel Enable RAM (SDMAARM2_CHNENBL46) 32 R/W 0000_0000h
1237
7.2.7.28/
30E1_02BC Channel Enable RAM (SDMAARM2_CHNENBL47) 32 R/W 0000_0000h
1237
SDMA DONE0 Configuration 7.2.7.29/
30E1_1000 32 R/W 1F1F_1F1Fh
(SDMAARM2_DONE0_CONFIG) 1237
SDMA DONE1 Configuration 7.2.7.30/
30E1_1004 32 R/W 1F1F_1F1Fh
(SDMAARM2_DONE1_CONFIG) 1239
7.2.7.1 Arm platform Channel 0 Pointer (SDMAARMx_MC0PTR)
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
MC0PTR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_MC0PTR field descriptions
Field Description
MC0PTR Channel 0 Pointer contains the 32-bit address, in Arm platform memory, of channel 0 control block (the
boot channel). Appendix A fully describes the SDMA Application Programming Interface (API). The Arm
platform has a read/write access and the SDMA has a read-only access.
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Smart Direct Memory Access Controller (SDMA)
7.2.7.2 Channel Interrupts (SDMAARMx_INTR)
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HI[31:0]
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_INTR field descriptions
Field Description
HI[31:0] The Arm platform Interrupts register contains the 32 HI[i] bits. If any bit is set, it will cause an interrupt to
the Arm platform. This register is a "write-ones" register to the Arm platform. When the Arm platform sets a
bit in this register the corresponding HI[i] bit is cleared. The interrupt service routine should clear individual
channel bits when their interrupts are serviced, failure to do so will cause continuous interrupts. The
SDMA is responsible for setting the HI[i] bit corresponding to the current channel when the corresponding
done instruction is executed.
7.2.7.3 Channel Stop/Channel Status (SDMAARMx_STOP_STAT)
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_STOP_STAT field descriptions
Field Description
HE This 32-bit register gives access to the Arm platform Enable bits. There is one bit for every channel. This
register is a "write-ones" register to the Arm platform. When the Arm platform writes 1 in bit i of this
register, it clears the HE[i] and HSTART[i] bits. Reading this register yields the current state of the HE[i]
bits.
7.2.7.4 Channel Start (SDMAARMx_HSTART)
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HSTART_HE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Chapter 7 Interrupts and DMA
SDMAARMx_HSTART field descriptions
Field Description
HSTART_HE The HSTART_HE registers are 32 bits wide with one bit for every channel. When a bit is written to 1, it
enables the corresponding channel. Two physical registers are accessed with that address (HSTART and
HE), which enables the Arm platform to trigger a channel a second time before the first trigger is
processed.
• This register is a "write-ones" register to the Arm platform. Neither HSTART[i] bit can be set while
the corresponding HE[i] bit is cleared.
• When the Arm platform tries to set the HSTART[i] bit by writing a one (if the corresponding HE[i] bit
is clear), the bit in the HSTART[i] register will remain cleared and the HE[i] bit will be set.
• If the corresponding HE[i] bit was already set, the HSTART[i] bit will be set. The next time the SDMA
channel i attempts to clear the HE[i] bit by means of a done instruction, the bit in the HSTART[i]
register will be cleared and the HE[i] bit will take the old value of the HSTART[i] bit.
• Reading this register yields the current state of the HSTART[i] bits. This mechanism enables the
Arm platform to pipeline two HSTART commands per channel.
7.2.7.5 Channel Event Override (SDMAARMx_EVTOVR)
Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVTOVR field descriptions
Field Description
EO The Channel Event Override register contains the 32 EO[i] bits. A bit set in this register causes the SDMA
to ignore DMA requests when scheduling the corresponding channel.
7.2.7.6 Channel BP Override (SDMAARMx_DSPOVR)
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DO
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
SDMAARMx_DSPOVR field descriptions
Field Description
DO This register is reserved. All DO bits should be set to the reset value of 1. A setting of 0 will prevent SDMA
channels from starting according to the condition described in Runnable Channels Evaluation.
0 - Reserved
1 - Reset value.
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Smart Direct Memory Access Controller (SDMA)
7.2.7.7 Channel Arm platform Override (SDMAARMx_HOSTOVR)
Address: Base address + 18h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
HO
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_HOSTOVR field descriptions
Field Description
HO The Channel Arm platform Override register contains the 32 HO[i] bits. A bit set in this register causes the
SDMA to ignore the Arm platform enable bit (HE) when scheduling the corresponding channel.
7.2.7.8 Channel Event Pending (SDMAARMx_EVTPEND)
Address: Base address + 1Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EP
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVTPEND field descriptions
Field Description
EP The Channel Event Pending register contains the 32 EP[i] bits. Reading this register enables the Arm
platform to determine what channels are pending after the reception of a DMA request.
• Setting a bit in this register causes the SDMA to reevaluate scheduling as if a DMA request mapped
on this channel had occurred. This is useful for starting up channels, so that initialization is done
before awaiting the first request. The scheduler can also set bits in the EVTPEND register according
to the received DMA requests.
• The EP[i] bit may be cleared by the done instruction when running the channel i script. This a "write-
ones" mechanism: Writing a '0' does not clear the corresponding bit.
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Chapter 7 Interrupts and DMA
7.2.7.9 Reset Register (SDMAARMx_RESET)
Address: Base address + 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESCHED
RESET
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_RESET field descriptions
Field Description
31–2 This read-only field is reserved and always has the value 0.
Reserved
1 When set, this bit forces the SDMA to reschedule as if a script had executed a done instruction. This
RESCHED enables the Arm platform to recover from a runaway script on a channel by clearing its HE[i] bit via the
STOP register, and then forcing a reschedule via the RESCHED bit. The RESCHED bit is cleared when
the context switch starts.
0 When set, this bit causes the SDMA to be held in a software reset. The internal reset signal is held low 16
RESET cycles; the RESET bit is automatically cleared when the internal reset signal rises.
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Smart Direct Memory Access Controller (SDMA)
7.2.7.10 DMA Request Error Register (SDMAARMx_EVTERR)
Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHNERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVTERR field descriptions
Field Description
CHNERR This register is used by the SDMA to warn the Arm platform when an incoming DMA request was detected
and it triggers a channel that is already pending or being serviced. This probably means there is an
overflow of data for that channel.
• An interrupt is sent to the Arm platform if the corresponding channel bit is set in the INTRMASK
register.
• This is a "write-ones" register for the scheduler. It is only able to set the flags. The flags are cleared
when the register is read by the Arm platform or during SDMA reset.
• The CHNERR[i] bit is set when a DMA request that triggers channel i is received through the
corresponding input pins and the EP[i] bit is already set; the EVTERR[i] bit is unaffected if the Arm
platform tries to set the EP[i] bit, whereas, that EP[i] bit is already set.
7.2.7.11 Channel Arm platform Interrupt Mask
(SDMAARMx_INTRMASK)
Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
HIMASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_INTRMASK field descriptions
Field Description
HIMASK The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit HIMASK[i] is set, the HI[i] bit
is set and an interrupt is sent to the Arm platform when a DMA request error is detected on channel i (for
example, EVTERR[i] is set).
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Chapter 7 Interrupts and DMA
7.2.7.12 Schedule Status (SDMAARMx_PSW)
Address: Base address + 30h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NCP[2:0] NCR[4:0] CCP[2:0] CCR[4:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_PSW field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–13 The Next Channel Priority gives the next pending channel priority. When the priority is 0, it means there is
NCP[2:0] no pending channel and the NCR value has no meaning.
0 No running channel
1 Active channel priority
12–8 The Next Channel Register indicates the number of the next scheduled pending channel with the highest
NCR[4:0] priority.
7–4 The Current Channel Priority indicates the priority of the current active channel. When the priority is 0, no
CCP[2:0] channel is running: The SDMA is idle and the CCR value has no meaning. In the case that the SDMA has
finished running the channel and has entered sleep state, CCP will indicate the priority of previous running
channel.
0 No running channel
1 Active channel priority
CCR[4:0] The Current Channel Register indicates the number of the channel that is being executed by the SDMA.
SDMA. In the case that the SDMA has finished running the channel and has entered sleep state, CCR will
indicate the previous running channel.
7.2.7.13 DMA Request Error Register (SDMAARMx_EVTERRDBG)
Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHNERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVTERRDBG field descriptions
Field Description
CHNERR This register is the same as EVTERR, except reading it does not clear its contents. This address is meant
to be used in debug mode. The Arm platform OnCE may check this register value without modifying it.
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Smart Direct Memory Access Controller (SDMA)
7.2.7.14 Configuration Register (SDMAARMx_CONFIG)
Address: Base address + 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0
DSPDMA
RTDOBS
ACR CSM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
SDMAARMx_CONFIG field descriptions
Field Description
31–13 This read-only field is reserved and always has the value 0.
Reserved
12 This bit's function is reserved and should be configured as zero.
DSPDMA
0 - Reset Value
1 - Reserved
11 Indicates if Real-Time Debug pins are used: They do not toggle by default in order to reduce power
RTDOBS consumption.
0 RTD pins disabled
1 RTD pins enabled
10–5 This read-only field is reserved and always has the value 0.
Reserved
4 Arm platform DMA / SDMA Core Clock Ratio. Selects the clock ratio between Arm platform DMA
ACR interfaces (burst DMA and peripheral DMA) and the internal SDMA core clock. The frequency selection is
determined separately by the chip clock controller. This bit has to match the configuration of the chip clock
controller that generates the clocks used in the SDMA.
0 Arm platform DMA interface frequency equals twice core frequency
1 Arm platform DMA interface frequency equals core frequency
3–2 This read-only field is reserved and always has the value 0.
Reserved
CSM Selects the Context Switch Mode. The Arm platform has a read/write access. The SDMA cannot modify
that register. The value at reset is 3, which selects the dynamic context switch by default. That register can
be modified at anytime but the new context switch configuration will only be taken into account at the start
of the next restore phase.
NOTE: The first call to SDMA's channel 0 Bootload script after reset should use static context switch mode
to ensure the context RAM for channel 0 is initialized in the channel SAVE Phase. After Channel 0 is run
once, then any of the dynamic context modes can be used.
Table continues on the next page...
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Chapter 7 Interrupts and DMA
SDMAARMx_CONFIG field descriptions (continued)
Field Description
0 static
1 dynamic low power
2 dynamic with no loop
3 dynamic
7.2.7.15 SDMA LOCK (SDMAARMx_SDMA_LOCK)
Address: Base address + 3Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRESET_LOCK_
R 0
LOCK
CLR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_SDMA_LOCK field descriptions
Field Description
31–2 This read-only field is reserved and always has the value 0.
Reserved
1 The SRESET_LOCK_CLR bit determine if the LOCK bit is cleared on a software reset triggered by writing
SRESET_LOCK_ to the RESET register. This bit cannot be changed if LOCK=1. SREST_LOCK_CLR is cleared by
CLR conditions that clear the LOCK bit.
0 Software Reset does not clear the LOCK bit.
1 Software Reset clears the LOCK bit.
0 The LOCK bit is used to restrict access to update SDMA script memory through ROM channel zero scripts
LOCK and through the OnCE interface under Arm platform control.
The LOCK bit is set:
• The SDMA_LOCK, ONCE_ENB,CH0ADDR, and ILLINSTADDR registers cannot be written. These
registers can be read, but writes are ignored.
• SDMA software executing out of ROM or RAM may check the LOCK bit in the LOCK register Lock
Status Register (SDMACORE_SDMA_LOCK) to determine if certain operations are allowed, such
as up-loading new scripts.
Table continues on the next page...
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SDMAARMx_SDMA_LOCK field descriptions (continued)
Field Description
Once the LOCK bit is set to 1, only a reset can clear it. The LOCK bit is cleared by a hardware reset.
LOCK is cleared by a software reset only if SRESET_LOCK_CLR is set.
0 LOCK disengaged.
1 LOCK enabled.
7.2.7.16 OnCE Enable (SDMAARMx_ONCE_ENB)
Address: Base address + 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ENB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_ONCE_ENB field descriptions
Field Description
31–1 This read-only field is reserved and always has the value 0.
Reserved
0 The OnCE Enable register selects the OnCE control source: When cleared (0), the OnCE registers are
ENB accessed through the JTAG interface; when set (1), the OnCE registers may be accessed by the Arm
platform through the addresses described, as follows.
• After reset, the OnCE registers are accessed through the JTAG interface.
• Writing a 1 to ENB enables the Arm platform to access the ONCE_* as any other SDMA control
register.
• When cleared (0), all the ONCE_xxx registers cannot be written.
The value of ENB cannot be changed if the LOCK bit in the SDMA_LOCK register is set.
7.2.7.17 OnCE Data Register (SDMAARMx_ONCE_DATA)
Address: Base address + 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DATA
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMAARMx_ONCE_DATA field descriptions
Field Description
DATA Data register of the OnCE JTAG controller. Refer to OnCE and Real-Time Debug for information on this
register.
7.2.7.18 OnCE Instruction Register (SDMAARMx_ONCE_INSTR)
Address: Base address + 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INSTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_ONCE_INSTR field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
INSTR Instruction register of the OnCE JTAG controller. Refer to OnCE and Real-Time Debug for information on
this register.
7.2.7.19 OnCE Status Register (SDMAARMx_ONCE_STAT)
Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PST[3:0] RCV EDR ODR SWB MST 0 ECDR
W
Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_ONCE_STAT field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–12 The Processor Status bits reflect the state of the SDMA RISC engine. Its states are as follows:
PST[3:0] • The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the data bus (ld or
st).
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SDMAARMx_ONCE_STAT field descriptions (continued)
Field Description
• The "Change of Flow" state is the second cycle of any instruction that breaks the sequence of
instructions (jumps and channel switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the RISC engine idle state). The "after Reset" is
slightly different because no context restoring phase will happen when a channel is triggered: The
script located at address 0 will be executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any corresponding channel:
They are used when entering debug mode after reset. The reason is that it is necessary to return to
the "Sleep after Reset" state when leaving debug mode.
0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Save
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change Flow in Loop in Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
14 Sleep after Reset
15 Restore
11 After each write access to the real time buffer (RTB), the RCV bit is set. This bit is cleared after execution
RCV of an rbuffer command and on a JTAG reset.
10 This flag is raised when the SDMA has entered debug mode after an external debug request.
EDR
9 This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
ODR
8 This flag is raised when the SDMA has entered debug mode after a software breakpoint.
SWB
7 This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
MST
0 The JTAG interface controls the OnCE.
1 The Arm platform peripheral interface controls the OnCE.
6–3 This read-only field is reserved and always has the value 0.
Reserved
ECDR Event Cell Debug Request. If the debug request comes from the event cell, the reason for entering debug
mode is given by the EDR bits. If all three bits of the EDR are reset, then it did not generate any debug
request. If the cell did generate a debug request, then at least one of the EDR bits is set (the meaning of
the encoding is given below). The encoding of the EDR bits is useful to find out more precisely why the
debug request was generated. A debug request from an event cell is generated for a specific combination
of the addra_cond, addrb_cond, and data_cond conditions. The value of those fields is given by the EDR
bits.
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SDMAARMx_ONCE_STAT field descriptions (continued)
Field Description
0 1 matched addra_cond
1 1 matched addrb_cond
2 1 matched data_cond
7.2.7.20 OnCE Command Register (SDMAARMx_ONCE_CMD)
Address: Base address + 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_ONCE_CMD field descriptions
Field Description
31–4 This read-only field is reserved and always has the value 0.
Reserved
CMD Writing to this register will cause the OnCE to execute the command that is written. When needed, the
ONCE_DATA and ONCE_INSTR registers should be loaded with the correct value before writing the
command to that register. For a list of the OnCE commands and their usage, see OnCE and Real-Time
Debug.
NOTE: 7-15 reserved
0 rstatus
1 dmov
2 exec_once
3 run_core
4 exec_core
5 debug_rqst
6 rbuffer
7.2.7.21 Illegal Instruction Trap Address (SDMAARMx_ILLINSTADDR)
Address: Base address + 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ILLINSTADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
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SDMAARMx_ILLINSTADDR field descriptions
Field Description
31–14 This read-only field is reserved and always has the value 0.
Reserved
ILLINSTADDR The Illegal Instruction Trap Address is the address where the SDMA jumps when an illegal instruction is
executed. It is 0x0001 after reset.
The value of ILLINSTADDR cannot be changed if the LOCK bit in the SDMA_LOCK register is set.
7.2.7.22 Channel 0 Boot Address (SDMAARMx_CHN0ADDR)
Address: Base address + 5Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
SMSZ
CHN0ADDR
W
Reset 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
SDMAARMx_CHN0ADDR field descriptions
Field Description
31–15 This read-only field is reserved and always has the value 0.
Reserved
14 The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel
SMSZ context. After reset, it is equal to 0, which defines a RAM space of 24 words for each channel. All of this
area stores the channel context. By setting this bit, 32 words are reserved for every channel context,
which gives eight additional words that can be used by the channel script to store any type of data. Those
words are never erased by the context switching mechanism.
The value of SMSZ cannot be changed if the LOCK bit in the SDMA_LOCK register is set.
0 24 words per context
1 32 words per context
CHN0ADDR This 14-bit register is used by the boot code of the SDMA. After reset, it points to the standard boot routine
in ROM (channel 0 routine). By changing this address, you can perform a boot sequence with your own
routine. The very first instructions of the boot code fetch the contents of this register (it is also mapped in
the SDMA memory space) and jump to the given address. The reset value is 0x0050 (decimal 80).
The value of CHN0ADDR cannot be changed if the LOCK bit in the SDMA_LOCK register is set.
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7.2.7.23 DMA Requests (SDMAARMx_EVT_MIRROR)
Address: Base address + 60h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EVENTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVT_MIRROR field descriptions
Field Description
EVENTS This register reflects the DMA requests received by the SDMA for events 31-0. The Arm platform and the
SDMA have a read-only access. There is one bit associated with each of 32 DMA request events. This
information may be useful during debug of the blocks that generate the DMA requests. The EVT_MIRROR
register is cleared following read access.
0 DMA request event not pending
1 DMA request event pending
7.2.7.24 DMA Requests 2 (SDMAARMx_EVT_MIRROR2)
Address: Base address + 64h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EVENTS[47:32]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_EVT_MIRROR2 field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EVENTS[47:32] This register reflects the DMA requests received by the SDMA for events 47-32. The Arm platform and
the SDMA have a read-only access. There is one bit associated with each of DMA request events. This
information may be useful during debug of the blocks that generate the DMA requests. The
EVT_MIRROR2 register is cleared following read access.
0 - DMA request event not pending
1- DMA request event pending
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7.2.7.25 Cross-Trigger Events Configuration Register 1
(SDMAARMx_XTRIG_CONF1)
Address: Base address + 70h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CNF3
CNF2
NUM3[5:0] NUM2[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
CNF1
CNF0
NUM1[5:0] NUM0[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_XTRIG_CONF1 field descriptions
Field Description
31 This read-only field is reserved and always has the value 0.
Reserved
30 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF3 whether the event line pulse is generated by the reception of a DMA request or by the starting of a
channel script execution.
0 channel
1 DMA request
29–24 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM3[5:0] number i.
23 This read-only field is reserved and always has the value 0.
Reserved
22 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF2 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
0 channel
1 DMA request
21–16 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM2[5:0] number i.
15 This read-only field is reserved and always has the value 0.
Reserved
14 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF1 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
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SDMAARMx_XTRIG_CONF1 field descriptions (continued)
Field Description
0 channel
1 DMA request
13–8 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM1[5:0] number i.
7 This read-only field is reserved and always has the value 0.
Reserved
6 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF0 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
0 channel
1 DMA request
NUM0[5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
number i.
7.2.7.26 Cross-Trigger Events Configuration Register 2
(SDMAARMx_XTRIG_CONF2)
Address: Base address + 74h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0
CNF7
CNF6
NUM7[5:0] NUM6[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
CNF5
CNF4
NUM5[5:0] NUM4[5:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_XTRIG_CONF2 field descriptions
Field Description
31 This read-only field is reserved and always has the value 0.
Reserved
30 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF7 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
0 channel
1 DMA request
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SDMAARMx_XTRIG_CONF2 field descriptions (continued)
Field Description
29–24 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM7[5:0] number i.
23 This read-only field is reserved and always has the value 0.
Reserved
22 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF6 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
0 channel
1 DMA request
21–16 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM6[5:0] number i.
15 This read-only field is reserved and always has the value 0.
Reserved
14 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF5 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution
0 channel
1 DMA request
13–8 Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
NUM5[5:0] number i.
7 This read-only field is reserved and always has the value 0.
Reserved
6 Configuration of the SDMA event line number i that is connected to the cross-trigger. It determines
CNF4 whether the event line pulse is generated by receiving a DMA request or by starting a channel script
execution.
0 channel
1 DMA request
NUM4[5:0] Contains the number of the DMA request or channel that triggers the pulse on the cross-trigger event line
number i.
7.2.7.27 Channel Priority Registers (SDMAARMx_SDMA_CHNPRIn)
Address: Base address + 100h offset + (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CHNPRIn
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMAARMx_SDMA_CHNPRIn field descriptions
Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
CHNPRIn This contains the priority of channel number n. Useful values are between 1 and 7; 0 is reserved by the
SDMA hardware to determine when there is no pending channel. Reset value is 0, which prevents the
channels from starting.
7.2.7.28 Channel Enable RAM (SDMAARMx_CHNENBLn)
Address: Base address + 200h offset + (4d × i), where i=0d to 47d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ENBLn
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMAARMx_CHNENBLn field descriptions
Field Description
ENBLn This 32-bit value selects the channels that are triggered by the DMA request number n. If ENBLn[i] is set
to 1, bit EP[i] will be set when the DMA request n is received. These 48 32-bit registers are physically
located in a RAM, with no known reset value. It is thus essential for the Arm platform to program them
before any DMA request is triggered to the SDMA, otherwise an unpredictable combination of channels
may be started.
7.2.7.29 SDMA DONE0 Configuration (SDMAARMx_DONE0_CONFIG)
Address: Base address + 1000h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SW_DONE_DIS3
SW_DONE_DIS2
DONE_SEL3
DONE_SEL2
R 0 0
CH_SEL3 CH_SEL2
W
Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW_DONE_DIS1
SW_DONE_DIS0
DONE_SEL1
DONE_SEL0
R 0 0
CH_SEL1 CH_SEL0
W
Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1
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SDMAARMx_DONE0_CONFIG field descriptions
Field Description
31 Select Done from SW or HW for channel 3
DONE_SEL3
0 HW
1 SW
30 Disable SW Done for channel 3
SW_DONE_DIS3
0 Enable
1 Disable
29 This read-only field is reserved and always has the value 0.
Reserved
28–24 Select event for channel 3 when Done is selected from HW.
CH_SEL3
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
23 Select Done from SW or HW for channel 2
DONE_SEL2
0 HW
1 SW
22 Disable SW Done for channel 2
SW_DONE_DIS2
0 Enable
1 Disable
21 This read-only field is reserved and always has the value 0.
Reserved
20–16 Select event for channel 2 when Done is selected from HW.
CH_SEL2
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
15 Select Done from SW or HW for channel 1
DONE_SEL1
0 HW
1 SW
14 Disable SW Done for channel 1
SW_DONE_DIS1
0 Enable
1 Disable
13 This read-only field is reserved and always has the value 0.
Reserved
12–8 Select event for channel 1 when Done is selected from HW.
CH_SEL1
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
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SDMAARMx_DONE0_CONFIG field descriptions (continued)
Field Description
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7 Select Done from SW or HW for channel 0
DONE_SEL0
0 HW
1 SW
6 Disable SW Done for channel 0
SW_DONE_DIS0
0 Enable
1 Disable
5 This read-only field is reserved and always has the value 0.
Reserved
CH_SEL0 Select event for channel 0 when Done is selected from HW.
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7.2.7.30 SDMA DONE1 Configuration (SDMAARMx_DONE1_CONFIG)
Address: Base address + 1004h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SW_DONE_DIS7
SW_DONE_DIS6
DONE_SEL7
DONE_SEL6
R 0 0
CH_SEL7 CH_SEL6
W
Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW_DONE_DIS5
SW_DONE_DIS4
DONE_SEL5
DONE_SEL4
R 0 0
CH_SEL5 CH_SEL4
W
Reset 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1
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SDMAARMx_DONE1_CONFIG field descriptions
Field Description
31 Select Done from SW or HW for channel 7
DONE_SEL7
0 HW
1 SW
30 Disable SW Done for channel 7
SW_DONE_DIS7
0 Enable
1 Disable
29 This read-only field is reserved and always has the value 0.
Reserved
28–24 Select event for channel 7 when Done is selected from HW.
CH_SEL7
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
23 Select Done from SW or HW for channel 6
DONE_SEL6
0 HW
1 SW
22 Disable SW Done for channel 6
SW_DONE_DIS6
0 Enable
1 Disable
21 This read-only field is reserved and always has the value 0.
Reserved
20–16 Select event for channel 6 when Done is selected from HW.
CH_SEL6
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
15 Select Done from SW or HW for channel 5
DONE_SEL5
0 HW
1 SW
14 Disable SW Done for channel 5
SW_DONE_DIS5
0 Enable
1 Disable
13 This read-only field is reserved and always has the value 0.
Reserved
12–8 Select event for channel 5 when Done is selected from HW.
CH_SEL5
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
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SDMAARMx_DONE1_CONFIG field descriptions (continued)
Field Description
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7 Select Done from SW or HW for channel 4
DONE_SEL4
0 HW
1 SW
6 Disable SW Done for channel 4
SW_DONE_DIS4
0 Enable
1 Disable
5 This read-only field is reserved and always has the value 0.
Reserved
CH_SEL4 Select event for channel 4 when Done is selected from HW.
HW Done will be asserted when the negative edge of selected event's Event Pending (EP) is detected.
00000 - Event 0
00001 - Event 1
...
11111 - Event 31
7.2.8 BP Memory Map and Control Register Definitions
The following section describes SDMA control registers available to the BP.
NOTE
These registers are physically implemented in all platforms, but
are not accessible when the SDMA BP control port is not
connected. Reset values are calculated to allow the system to
work when those registers cannot be accessed.
All registers are clocked with the SDMA clock (which means the SDMA clock must be
running when the BP wants to access any register).
SDMABP memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30BD_0000 Channel 0 Pointer (SDMABP1_DC0PTR) 32 R/W 0000_0000h 7.2.8.1/1243
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SDMABP memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30BD_0004 Channel Interrupts (SDMABP1_INTR) 32 w1c 0000_0000h 7.2.8.2/1243
30BD_0008 Channel Stop/Channel Status (SDMABP1_STOP_STAT) 32 R/W 0000_0000h 7.2.8.3/1243
30BD_000C Channel Start (SDMABP1_DSTART) 32 R 0000_0000h 7.2.8.4/1244
30BD_0028 DMA Request Error Register (SDMABP1_EVTERR) 32 R 0000_0000h 7.2.8.5/1244
30BD_002C Channel DSP Interrupt Mask (SDMABP1_INTRMASK) 32 R/W 0000_0000h 7.2.8.6/1245
30BD_0034 DMA Request Error Register (SDMABP1_EVTERRDBG) 32 R 0000_0000h 7.2.8.7/1245
30E0_0000 Channel 0 Pointer (SDMABP3_DC0PTR) 32 R/W 0000_0000h 7.2.8.1/1243
30E0_0004 Channel Interrupts (SDMABP3_INTR) 32 w1c 0000_0000h 7.2.8.2/1243
30E0_0008 Channel Stop/Channel Status (SDMABP3_STOP_STAT) 32 R/W 0000_0000h 7.2.8.3/1243
30E0_000C Channel Start (SDMABP3_DSTART) 32 R 0000_0000h 7.2.8.4/1244
30E0_0028 DMA Request Error Register (SDMABP3_EVTERR) 32 R 0000_0000h 7.2.8.5/1244
30E0_002C Channel DSP Interrupt Mask (SDMABP3_INTRMASK) 32 R/W 0000_0000h 7.2.8.6/1245
30E0_0034 DMA Request Error Register (SDMABP3_EVTERRDBG) 32 R 0000_0000h 7.2.8.7/1245
30E1_0000 Channel 0 Pointer (SDMABP2_DC0PTR) 32 R/W 0000_0000h 7.2.8.1/1243
30E1_0004 Channel Interrupts (SDMABP2_INTR) 32 w1c 0000_0000h 7.2.8.2/1243
30E1_0008 Channel Stop/Channel Status (SDMABP2_STOP_STAT) 32 R/W 0000_0000h 7.2.8.3/1243
30E1_000C Channel Start (SDMABP2_DSTART) 32 R 0000_0000h 7.2.8.4/1244
30E1_0028 DMA Request Error Register (SDMABP2_EVTERR) 32 R 0000_0000h 7.2.8.5/1244
30E1_002C Channel DSP Interrupt Mask (SDMABP2_INTRMASK) 32 R/W 0000_0000h 7.2.8.6/1245
30E1_0034 DMA Request Error Register (SDMABP2_EVTERRDBG) 32 R 0000_0000h 7.2.8.7/1245
7.2.8.1 Channel 0 Pointer (SDMABPx_DC0PTR)
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DC0PTR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMABPx_DC0PTR field descriptions
Field Description
DC0PTR Channel 0 Pointer contains the 32-bit address, in BP memory, of the array of channel control blocks
starting with the one for channel 0 (the control channel). This register should be initialized by the BP
before it enables a channel (for example, channel 0). See the API document SDMA Scripts User Manual
for the use of this register. The BP has a read/write access and the SDMA has a read-only access.
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7.2.8.2 Channel Interrupts (SDMABPx_INTR)
Address: Base address + 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DI
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMABPx_INTR field descriptions
Field Description
DI The BP Interrupts register contains the 32 DI[i] bits. If any bit is set, it will cause an interrupt to the BP.
• This register is a "write-ones" register to the BP. When the BP sets a bit in this register, the
corresponding DI[i] bit is cleared.
• The interrupt service routine should clear individual channel bits when their interrupts are serviced;
failure to do so will cause continuous interrupts.
• The SDMA is responsible for setting the DI[i] bit corresponding to the current channel when the
corresponding done instruction is executed.
7.2.8.3 Channel Stop/Channel Status (SDMABPx_STOP_STAT)
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DE
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMABPx_STOP_STAT field descriptions
Field Description
DE This 32-bit register gives access to the BP (DSP) Enable bits, DE. There is one bit for every channel.
• This register is a "write-ones" register to the BP.
• When the BP writes 1 in bit i of this register, it clears the DE[i] and DSTART[i] bits.
• Reading this register yields the current state of the DE[i] bits.
7.2.8.4 Channel Start (SDMABPx_DSTART)
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R DSTART_DE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMABPx_DSTART field descriptions
Field Description
DSTART_DE The DSTART_DE registers are 32 bits wide with one bit for every channel.
• When a bit is written to 1, it enables the corresponding channel.
• Two physical registers are accessed with that address (DSTART and DE), which enables the BP to
trigger a channel a second time before the first trigger was processed.
• This register is a "write-ones" register to the BP. Neither DSTART[i] bit can be set while the
corresponding DE[i] bit is cleared.
• When the BP tries to set the DSTART[i] bit by writing a one (if the corresponding DE[i] bit is clear),
the bit in the DSTART[i] register will remain cleared and the DE[i] bit will be set. If the corresponding
DE[i] bit was already set, the DSTART[i] bit will be set.
• The next time the SDMA channel i attempts to clear the DE[i] bit by means of a done instruction, the
bit in the DSTART[i] register will be cleared and the DE[i] bit will take the old value of the DSTART[i]
bit.
• Reading this register yields the current state of the DSTART[i] bits. This mechanism enables the BP
to pipeline two DSTART commands per channel.
7.2.8.5 DMA Request Error Register (SDMABPx_EVTERR)
Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHNERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMABPx_EVTERR field descriptions
Field Description
CHNERR This register is used by the SDMA to warn the BP when an incoming DMA request was detected; it then
triggers a channel that is already pending or being serviced, which may mean there is an overflow of data
for that channel. An interrupt is sent to the BP if the corresponding channel bit is set in the INTRMASK
register.
• This is a "write-ones" register for the scheduler. It is only able to set the flags. The flags are cleared
when the register is read by the BP or during an SDMA reset.
• The CHNERR[i] bit is set when a DMA request that triggers channel i is received through the
corresponding input pins and the EP[i] bit is already set. The EVTERR[i] bit is unaffected if the BP
tries to set the EP[i] bit when that EP[i] bit is already set.
7.2.8.6 Channel DSP Interrupt Mask (SDMABPx_INTRMASK)
Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
DIMASK
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMABPx_INTRMASK field descriptions
Field Description
DIMASK The Interrupt Mask Register contains 32 interrupt generation mask bits. If bit DIMASK[i] is set, the DI[i] bit
is set and an interrupt is sent to the BP when a DMA request error is detected on channel i (for example,
EVTERR[i] is set).
7.2.8.7 DMA Request Error Register (SDMABPx_EVTERRDBG)
Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CHNERR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMABPx_EVTERRDBG field descriptions
Field Description
CHNERR This register is the same as EVTERR except reading it does not clear its contents. This address is meant
to be used in debug mode. The BP OnCE may check this register value without modifying it.
7.2.9 SDMA Internal (Core) Memory Map and Internal Register
Definitions
The actual SDMA memory mapped registers are summarized in the following sections;
for peripherals' memory maps, refer to the respective chapters.
The following definitions serve as a key for the SDMA internal register summary.
SDMACORE memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30BD_0000 Arm platform Channel 0 Pointer (SDMACORE1_MC0PTR) 32 R 0000_0000h 7.2.9.1/1249
30BD_0008 Current Channel Pointer (SDMACORE1_CCPTR) 32 R 0000_0000h 7.2.9.2/1249
30BD_000C Current Channel Register (SDMACORE1_CCR) 32 R 0000_0000h 7.2.9.3/1250
30BD_0010 Highest Pending Channel Register (SDMACORE1_NCR) 32 R 0000_0000h 7.2.9.4/1250
30BD_0014 External DMA Requests Mirror (SDMACORE1_EVENTS) 32 R 0000_0000h 7.2.9.5/1251
30BD_0018 Current Channel Priority (SDMACORE1_CCPRI) 32 R 0000_0000h 7.2.9.6/1252
30BD_001C Next Channel Priority (SDMACORE1_NCPRI) 32 R 0000_0000h 7.2.9.7/1252
Table continues on the next page...
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SDMACORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
30BD_0020 OnCE Event Cell Counter (SDMACORE1_ECOUNT) 32 R/W 0000_0000h 7.2.9.8/1253
30BD_0024 OnCE Event Cell Control Register (SDMACORE1_ECTL) 32 R/W 0000_0000h 7.2.9.9/1253
7.2.9.10/
30BD_0028 OnCE Event Address Register A (SDMACORE1_EAA) 32 R/W 0000_0000h
1255
7.2.9.11/
30BD_002C OnCE Event Cell Address Register B (SDMACORE1_EAB) 32 R/W 0000_0000h
1255
7.2.9.12/
30BD_0030 OnCE Event Cell Address Mask (SDMACORE1_EAM) 32 R/W 0000_0000h
1255
7.2.9.13/
30BD_0034 OnCE Event Cell Data Register (SDMACORE1_ED) 32 R/W 0000_0000h
1256
7.2.9.14/
30BD_0038 OnCE Event Cell Data Mask (SDMACORE1_EDM) 32 R/W 0000_0000h
1256
7.2.9.15/
30BD_003C OnCE Real-Time Buffer (SDMACORE1_RTB) 32 R/W 0000_0000h
1257
7.2.9.16/
30BD_0040 OnCE Trace Buffer (SDMACORE1_TB) 32 R 0000_0000h
1257
7.2.9.17/
30BD_0044 OnCE Status (SDMACORE1_OSTAT) 32 R 0000_0000h
1258
7.2.9.18/
30BD_0048 Channel 0 Boot Address (SDMACORE1_MCHN0ADDR) 32 R 0000_0000h
1260
7.2.9.19/
30BD_004C ENDIAN Status Register (SDMACORE1_ENDIANNESS) 32 R 0000_0001h
1261
7.2.9.20/
30BD_0054 Lock Status Register (SDMACORE1_SDMA_LOCK) 32 R 0000_0000h
1262
External DMA Requests Mirror #2 7.2.9.21/
30BD_0058 32 R 0000_0000h
(SDMACORE1_EVENTS2) 1262
30E0_0000 Arm platform Channel 0 Pointer (SDMACORE3_MC0PTR) 32 R 0000_0000h 7.2.9.1/1249
30E0_0008 Current Channel Pointer (SDMACORE3_CCPTR) 32 R 0000_0000h 7.2.9.2/1249
30E0_000C Current Channel Register (SDMACORE3_CCR) 32 R 0000_0000h 7.2.9.3/1250
30E0_0010 Highest Pending Channel Register (SDMACORE3_NCR) 32 R 0000_0000h 7.2.9.4/1250
30E0_0014 External DMA Requests Mirror (SDMACORE3_EVENTS) 32 R 0000_0000h 7.2.9.5/1251
30E0_0018 Current Channel Priority (SDMACORE3_CCPRI) 32 R 0000_0000h 7.2.9.6/1252
30E0_001C Next Channel Priority (SDMACORE3_NCPRI) 32 R 0000_0000h 7.2.9.7/1252
30E0_0020 OnCE Event Cell Counter (SDMACORE3_ECOUNT) 32 R/W 0000_0000h 7.2.9.8/1253
30E0_0024 OnCE Event Cell Control Register (SDMACORE3_ECTL) 32 R/W 0000_0000h 7.2.9.9/1253
7.2.9.10/
30E0_0028 OnCE Event Address Register A (SDMACORE3_EAA) 32 R/W 0000_0000h
1255
7.2.9.11/
30E0_002C OnCE Event Cell Address Register B (SDMACORE3_EAB) 32 R/W 0000_0000h
1255
7.2.9.12/
30E0_0030 OnCE Event Cell Address Mask (SDMACORE3_EAM) 32 R/W 0000_0000h
1255
7.2.9.13/
30E0_0034 OnCE Event Cell Data Register (SDMACORE3_ED) 32 R/W 0000_0000h
1256
Table continues on the next page...
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SDMACORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.9.14/
30E0_0038 OnCE Event Cell Data Mask (SDMACORE3_EDM) 32 R/W 0000_0000h
1256
7.2.9.15/
30E0_003C OnCE Real-Time Buffer (SDMACORE3_RTB) 32 R/W 0000_0000h
1257
7.2.9.16/
30E0_0040 OnCE Trace Buffer (SDMACORE3_TB) 32 R 0000_0000h
1257
7.2.9.17/
30E0_0044 OnCE Status (SDMACORE3_OSTAT) 32 R 0000_0000h
1258
7.2.9.18/
30E0_0048 Channel 0 Boot Address (SDMACORE3_MCHN0ADDR) 32 R 0000_0000h
1260
7.2.9.19/
30E0_004C ENDIAN Status Register (SDMACORE3_ENDIANNESS) 32 R 0000_0001h
1261
7.2.9.20/
30E0_0054 Lock Status Register (SDMACORE3_SDMA_LOCK) 32 R 0000_0000h
1262
External DMA Requests Mirror #2 7.2.9.21/
30E0_0058 32 R 0000_0000h
(SDMACORE3_EVENTS2) 1262
30E1_0000 Arm platform Channel 0 Pointer (SDMACORE2_MC0PTR) 32 R 0000_0000h 7.2.9.1/1249
30E1_0008 Current Channel Pointer (SDMACORE2_CCPTR) 32 R 0000_0000h 7.2.9.2/1249
30E1_000C Current Channel Register (SDMACORE2_CCR) 32 R 0000_0000h 7.2.9.3/1250
30E1_0010 Highest Pending Channel Register (SDMACORE2_NCR) 32 R 0000_0000h 7.2.9.4/1250
30E1_0014 External DMA Requests Mirror (SDMACORE2_EVENTS) 32 R 0000_0000h 7.2.9.5/1251
30E1_0018 Current Channel Priority (SDMACORE2_CCPRI) 32 R 0000_0000h 7.2.9.6/1252
30E1_001C Next Channel Priority (SDMACORE2_NCPRI) 32 R 0000_0000h 7.2.9.7/1252
30E1_0020 OnCE Event Cell Counter (SDMACORE2_ECOUNT) 32 R/W 0000_0000h 7.2.9.8/1253
30E1_0024 OnCE Event Cell Control Register (SDMACORE2_ECTL) 32 R/W 0000_0000h 7.2.9.9/1253
7.2.9.10/
30E1_0028 OnCE Event Address Register A (SDMACORE2_EAA) 32 R/W 0000_0000h
1255
7.2.9.11/
30E1_002C OnCE Event Cell Address Register B (SDMACORE2_EAB) 32 R/W 0000_0000h
1255
7.2.9.12/
30E1_0030 OnCE Event Cell Address Mask (SDMACORE2_EAM) 32 R/W 0000_0000h
1255
7.2.9.13/
30E1_0034 OnCE Event Cell Data Register (SDMACORE2_ED) 32 R/W 0000_0000h
1256
7.2.9.14/
30E1_0038 OnCE Event Cell Data Mask (SDMACORE2_EDM) 32 R/W 0000_0000h
1256
7.2.9.15/
30E1_003C OnCE Real-Time Buffer (SDMACORE2_RTB) 32 R/W 0000_0000h
1257
7.2.9.16/
30E1_0040 OnCE Trace Buffer (SDMACORE2_TB) 32 R 0000_0000h
1257
7.2.9.17/
30E1_0044 OnCE Status (SDMACORE2_OSTAT) 32 R 0000_0000h
1258
7.2.9.18/
30E1_0048 Channel 0 Boot Address (SDMACORE2_MCHN0ADDR) 32 R 0000_0000h
1260
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SDMACORE memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
7.2.9.19/
30E1_004C ENDIAN Status Register (SDMACORE2_ENDIANNESS) 32 R 0000_0001h
1261
7.2.9.20/
30E1_0054 Lock Status Register (SDMACORE2_SDMA_LOCK) 32 R 0000_0000h
1262
External DMA Requests Mirror #2 7.2.9.21/
30E1_0058 32 R 0000_0000h
(SDMACORE2_EVENTS2) 1262
7.2.9.1 Arm platform Channel 0 Pointer (SDMACOREx_MC0PTR)
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R MC0PTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_MC0PTR field descriptions
Field Description
MC0PTR Contains the address-in the Arm platform memory space-of the initial SDMA context and scripts that are
loaded by the SDMA boot script running on channel 0.
7.2.9.2 Current Channel Pointer (SDMACOREx_CCPTR)
Address: Base address + 8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CCPTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_CCPTR field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
CCPTR Contains the start address of the context data for the current channel: Its value is CONTEXT_BASE + 24*
CCR or CONTEXT_BASE + 32* CCR where CONTEXT_BASE = 0x0800. The value 24 or 32 is selected
according to the programmed channel scratch RAM size in the register shown in Channel 0 Boot Address
(SDMAARM_CHN0ADDR) .
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7.2.9.3 Current Channel Register (SDMACOREx_CCR)
Address: Base address + Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_CCR field descriptions
Field Description
31–5 This read-only field is reserved and always has the value 0.
Reserved
CCR Contains the number of the current running channel whose context is installed. In the case that the SDMA
has finished running the channel and has entered sleep state, CCR will indicate the previous running
channel. The PST bits in the OSTAT register indicate when the SDMA is in sleep state.
7.2.9.4 Highest Pending Channel Register (SDMACOREx_NCR)
Address: Base address + 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NCR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_NCR field descriptions
Field Description
31–5 This read-only field is reserved and always has the value 0.
Reserved
NCR Contains the number of the pending channel that the scheduler has selected to run next.
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7.2.9.5 External DMA Requests Mirror (SDMACOREx_EVENTS)
NOTE
This register is very useful in the case of DMA requests that are
active when a peripheral FIFO level is above the programmed
watermark. The activation of the DMA request (rising edge) is
detected by the SDMA logic and it can enable one or several
channels. One of the channels accesses the peripheral and reads
or writes a number of data that matches the watermark level
(for example, if the watermark is four words, the channel reads
or writes four words).
If the channel is effectively executed long after the DMA
request was received, reading or writing the watermark number
of data may not be sufficient to reset the DMA request (for
example, if the FIFO watermark is four and at the channel
execution it already contains nine pieces of data). This means
no new rising edge may be detected by the SDMA, although
there still remains transfers to perform. Therefore, if the
channel were terminated at that time, it would not be restarted,
causing potential overrun or underrun of the peripheral.
The proposed mechanism is for the channel to check this
register after it has performed the "watermark" number of
accesses to the peripheral. If the bit for the DMA request that
triggers this channel is set, it means there is still another
watermark number of data to transfer. This goes on until the bit
is cleared. The same script can be used for multiple channels
that require this behavior. The script can determine its channel
number from the CCR register and infer the corresponding
DMA request bit to check. It needs a reference table that is
coherent with the request-channel matrix that the Arm platform
programmed.
Address: Base address + 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R EVENTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMACOREx_EVENTS field descriptions
Field Description
EVENTS Reflects the status of the SDMA's external DMA requests. It is meant to allow any channel to monitor the
states of these SDMA inputs.
This register displays EVENTS 0-31. The EVENTS2 register displays events 32-47.
7.2.9.6 Current Channel Priority (SDMACOREx_CCPRI)
Address: Base address + 18h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 CCPRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_CCPRI field descriptions
Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
CCPRI Contains the 3-bit priority of the channel whose context is installed. It is 0 when no channel is running.
NOTE: 1-7 current channel priority
0 no running channel
7.2.9.7 Next Channel Priority (SDMACOREx_NCPRI)
Address: Base address + 1Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 NCPRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_NCPRI field descriptions
Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
NCPRI Contains the 3-bit priority of the channel the scheduler has selected to run next. It is 0 when no other
channel is pending.
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7.2.9.8 OnCE Event Cell Counter (SDMACOREx_ECOUNT)
Address: Base address + 20h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ECOUNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_ECOUNT field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
ECOUNT The event cell counter contains the number of times minus one that an event detection must occur before
generating a debug request.
• This register should be written before any attempt to use the event detection counter during an
event detection process.
• The counter is cleared on a JTAG reset.
7.2.9.9 OnCE Event Cell Control Register (SDMACOREx_ECTL)
Address: Base address + 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EN CNT ECTC[1:0] DTC[1:0] ATC[1:0] ABTC[1:0] AATC[1:0] ATS[1:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_ECTL field descriptions
Field Description
31–14 This read-only field is reserved and always has the value 0.
Reserved
13 Event Cell Enable. If the EN bit is set, the event cell is allowed to generate debug requests (the cell is
EN awakened). If it is cleared, the event detection unit is disabled and no hardware breakpoint is generated,
but matching conditions are still reflected on the emulation pin.
0 Cell is disabled.
1 Cell is enabled.
12 Event Counter Enable. The event counter enable bit determines if the cell counter is used during the event
CNT detection. In order to use the event counter during an event detection process, the event cell counter
register should be loaded with a value equal to the number of times minus one that an event occurs before
a debug request is sent. After every event detection, the counter is decreased. When the counter reaches
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SDMACOREx_ECTL field descriptions (continued)
Field Description
the value 0, the event detection cell sends a debug request to the core. The event counter register should
be written and the EN bit should be set before each new event detection process uses the event counter.
0 Counter is disabled.
1 Counter is enabled.
11–10 The event cell trigger condition bits select the combination of address and data matching conditions that
ECTC[1:0] generate the final address/data condition. During program execution, if this event cell trigger condition
goes to 1, a debug request is sent to the SDMA. The EN bit must be set to enable the debug request
generation.
00 address ONLY
01 data ONLY
10 address AND data
11 address OR data
9–8 The data trigger condition bits define when data is considered matching after comparison with the data
DTC[1:0] register of the event detection unit. The operations are performed on unsigned values.
00 equal
01 not equal
10 greater than
11 less than
7–6 The address trigger condition bits select how the two address conditions (addressA and addressB) are
ATC[1:0] combined to define the global address matching condition. The supported combinations are described, as
follows.
00 addressA ONLY
01 addrA AND addrB
10 addrA OR addrB
11 reserved
5–4 The Address B Trigger Condition (ABTC) controls the operations performed by address comparator B. All
ABTC[1:0] operations are performed on unsigned values. This comparator B outputs the addressB condition.
00 equal
01 not equal
10 greater than
11 less than
3–2 The Address A Trigger Condition (AATC) controls the operations performed by address comparator A. All
AATC[1:0] operations are performed on unsigned values. This comparator A outputs the addressA condition.
00 equal
01 not equal
10 greater than
11 less than
ATS[1:0] The access type select bits define the memory access type required on the SDMA memory bus.
00 read ONLY
01 write ONLY
10 read or write
11 -
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7.2.9.10 OnCE Event Address Register A (SDMACOREx_EAA)
Address: Base address + 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_EAA field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EAA Event Cell Address Register A computes an address A condition. It is cleared on a JTAG reset.
7.2.9.11 OnCE Event Cell Address Register B (SDMACOREx_EAB)
Address: Base address + 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_EAB field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EAB Event Cell Address Register B computes an address B condition. It is cleared on a JTAG reset.
7.2.9.12 OnCE Event Cell Address Mask (SDMACOREx_EAM)
Address: Base address + 30h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EAM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_EAM field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
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SDMACOREx_EAM field descriptions (continued)
Field Description
EAM The Event Cell Address Mask contains a user-defined address mask value. This mask is applied to the
address value latched from the memory address bus before performing the address comparison.
NOTE: There is a common address mask value for both address comparators. If bit i of this register is
set, then bit i of the address value latched from the memory bus does not influence the result of
the address comparison. The register is cleared on a JTAG reset.
7.2.9.13 OnCE Event Cell Data Register (SDMACOREx_ED)
Address: Base address + 34h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
ED
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_ED field descriptions
Field Description
ED The event cell data register contains a user defined data value. This data value is an input for the data
comparator which generates the data condition. It is cleared on a JTAG reset.
7.2.9.14 OnCE Event Cell Data Mask (SDMACOREx_EDM)
Address: Base address + 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
EDM
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_EDM field descriptions
Field Description
EDM The event cell data mask register contains the user-defined data mask value.
• This mask is applied to the data value latched from the memory bus before performing the data
comparison.
• Setting bit i of the event cell data mask register means that bit i of the data value latched from the
address bus does not influence the result of the data comparison.
• The data mask is cleared on a JTAG reset.
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7.2.9.15 OnCE Real-Time Buffer (SDMACOREx_RTB)
Address: Base address + 3Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
RTB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_RTB field descriptions
Field Description
RTB The Real Time Buffer register stores and retrieves run time information without putting the SDMA in debug
mode. Writing to that register triggers a pulse on a specific real-time debug pin whose connection depends
on the chip implementation.
The RTB value can be accessed by the OnCE under Arm platform or JTAG control using the rbuffer
command.
7.2.9.16 OnCE Trace Buffer (SDMACOREx_TB)
Address: Base address + 40h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 TBF TADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TADDR CHFADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_TB field descriptions
Field Description
31–29 This read-only field is reserved and always has the value 0.
Reserved
28 The Trace Buffer Flag is set when the buffer contains the addresses of a valid change of flow. The
TBF contents of the buffer should be ignored otherwise.
0 Invalid information
1 Valid information
27–14 The target address is the address taken after the execution of the change of flow instruction.
TADDR
CHFADDR The change of flow address is the address where the change of flow is taken when executing a change of
flow instruction.
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7.2.9.17 OnCE Status (SDMACOREx_OSTAT)
Address: Base address + 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PST[3:0] RCV EDR ODR SWB MST 0 ECDR[2:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_OSTAT field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
15–12 The Processor Status bits reflect the state of the SDMA RISC engine.
PST[3:0] • The "Program" state is the usual instruction execution cycle.
• The "Data" state is inserted when there are wait-states during a load or a store on the data bus (ld or
st).
• The "Change of Flow" state is the second cycle of any instruction that breaks the sequence of
instructions (jumps and channel-switching instructions).
• The "Change of Flow in Loop" state is used when an error causes a hardware loop exit.
• The "Debug" state means the SDMA is in debug mode.
• The "Functional Unit" state is inserted when there are wait-states during a load or a store on the
functional units bus (ldf or stf).
• In "Sleep" modes, no script is running (this is the RISC engine idle state). The "after Reset" is
slightly different because no context restoring phase will happen when a channel is triggered: The
script located at address 0 will be executed (boot operation).
• The "in Sleep" states are the same as above except they do not have any corresponding channel.
They are used when entering debug mode after reset; the reason is that it is necessary to return to
the "Sleep after Reset" state when leaving debug mode.
0 Program
1 Data
2 Change of Flow
3 Change of Flow in Loop
4 Debug
5 Functional Unit
6 Sleep
7 Save
8 Program in Sleep
9 Data in Sleep
10 Change of Flow in Sleep
11 Change Flow Loop Sleep
12 Debug in Sleep
13 Functional Unit in Sleep
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SDMACOREx_OSTAT field descriptions (continued)
Field Description
14 Sleep after Reset
15 Restore
11 After each write access to the real time buffer (RTB), the RCV bit is set. This bit is cleared after execution
RCV of an rbuffer command and on a JTAG reset.
10 This flag is raised when the SDMA has entered debug mode after an external debug request.
EDR
9 This flag is raised when the SDMA has entered debug mode after a OnCE debug request.
ODR
8 This flag is raised when the SDMA has entered debug mode after a software breakpoint.
SWB
7 This flag is raised when the OnCE is controlled from the Arm platform peripheral interface.
MST
0 JTAG interface controls the OnCE.
1 Arm platform peripheral interface controls the OnCE.
6–3 This read-only field is reserved and always has the value 0.
Reserved
ECDR[2:0] Event Cell Debug Request. If the debug request comes from the event cell, the reason for entering debug
mode is given by the EDR bits. The encoding of the EDR bits is useful to find out more precisely why the
debug request was generated. A debug request from an event cell is generated for a specific combination
of the addressA, addressB, and data conditions; the value of those fields is given by the EDR bits. If all
three bits of the EDR are reset, then it did not generate any debug request. If the cell did generate a
debug request, then at least one EDR bit is set; the meaning of the encoding is as follows:
0 1 matched addressA condition
1 1 matched addressB condition
2 1 matched data condition
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7.2.9.18 Channel 0 Boot Address (SDMACOREx_MCHN0ADDR)
Address: Base address + 48h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMSZ
R 0 CHN0ADDR[13:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_MCHN0ADDR field descriptions
Field Description
31–15 This read-only field is reserved and always has the value 0.
Reserved
14 The bit 14 (Scratch Memory Size) determines if scratch memory must be available after every channel
SMSZ context. After reset, it is equal to 0, which defines a RAM space of 24 words for each channel. All of
this area stores the channel context. By setting this bit, 32 words are reserved for every channel
context, which gives eight additional words that can be used by the channel script to store any type of
data. Those words are never erased by the context switching mechanism.
0 24 words per context
1 32 words per context
CHN0ADDR[13:0] Contains the address of the channel 0 routine programmed by the Arm platform; it is loaded into a
general register at the very start of the boot and the SDMA jumps to the address it contains. By
default, it points to the standard boot routine in ROM.
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7.2.9.19 ENDIAN Status Register (SDMACOREx_ENDIANNESS)
Address: Base address + 4Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APEND
R 0 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SDMACOREx_ENDIANNESS field descriptions
Field Description
31–3 This read-only field is reserved and always has the value 0.
Reserved
2–1 This read-only field is reserved and always has the value 0.
Reserved
0 APEND indicates the endian mode of the Peripheral and Burst DMA interfaces. This bit is tied to logic '1'
APEND indicating little-endian mode.
0 - Arm platform is in big-endian mode
1 - Arm platform is in little-endian mode
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7.2.9.20 Lock Status Register (SDMACOREx_SDMA_LOCK)
Address: Base address + 54h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCK
R 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDMACOREx_SDMA_LOCK field descriptions
Field Description
31–1 This read-only field is reserved and always has the value 0.
Reserved
0 The LOCK bit reports the value of the LOCK bit in the SDMA_LOCK status register. SDMA software may
LOCK use this value to determine if certain operations such as loading of new scripts is allowed.
0 - LOCK bit clear
1 - LOCK bit set
7.2.9.21 External DMA Requests Mirror #2 (SDMACOREx_EVENTS2)
Address: Base address + 58h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 EVENTS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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SDMACOREx_EVENTS2 field descriptions
Field Description
31–16 This read-only field is reserved and always has the value 0.
Reserved
EVENTS Reflects the status of the SDMA's external DMA requests. It is meant to allow any channel to monitor the
states of these SDMA inputs.
This register displays EVENTS 32-47. The separate EVENTS register displays events 0-31.
7.2.10 SDMA Peripheral Registers
Refer to the respective peripherals' chapters for more information.
7.3 Enhanced Direct Memory Access (eDMA)
7.3.1 Introduction
The enhanced direct memory access (eDMA) controller is capable of performing
complex data transfers with minimal intervention from a host processor. The hardware
microarchitecture includes:
• A DMA engine that performs:
• Source address and destination address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 32 channels
7.3.1.1 eDMA system block diagram
Figure 7-23 illustrates the components of the eDMA system, including the eDMA
module (engine).
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eDMA system
Write Address
Write Data
0
1
2
Internal Peripheral Bus
To/from interconnect fabric
Transfer Control
Descriptor (TCD)
n-1
64
eDMA Engine Read Data
Program Model/
Channel Arbitration
Read Data
Address Path
Control
Data Path
Write Data
Address
eDMA eDMA
Peripheral Done
Request
Figure 7-23. eDMA system block diagram
7.3.1.2 Block parts
The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Table 7-58. eDMA engine submodules
Submodule Function
Address path This block:
• Implements a primary channel and secondary (preempt) channel
• Manages all master bus-address calculations
All the channels provide the same functionality. This structure allows data transfers associated
with one channel to be preempted after the completion of a read/write sequence if a higher priority
channel activation is asserted while the primary channel is active.
After a channel is activated, it runs until the minor loop is completed, unless preempted by a
higher priority channel. This provides a mechanism (enabled by CHn_PRI[ECP]) where a large
data transfer can be preempted to minimize the time another channel is blocked from execution.
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Table 7-58. eDMA engine submodules (continued)
Submodule Function
When any channel is selected to execute, the contents of its TCD are read from local memory and
loaded into the address path channel x registers for a normal start and into channel y registers for
a preemption start. After the minor loop completes execution, the address path hardware writes
the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major
iteration count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn_CITER field, and a possible fetch of a new TCDn from memory as
part of a scatter/gather operation. See Dynamic scatter/gather for more details.
Data path This block implements the bus master read/write data path. It includes a data buffer and the
necessary multiplex logic to support any required data alignment. The internal read data bus is the
primary input, and the internal write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined internal bus. The
address path module represents the first stage of the bus pipeline (address phase), and the data
path module implements the second stage of the pipeline (data phase).
Program model/channel This block implements the first section of the eDMA programming model as well as the channel
arbitration arbitration logic. The programming model registers are connected to the internal peripheral bus.
The eDMA peripheral request inputs and interrupt request outputs are also connected to this block
(via control logic).
Control This block provides all the control functions for the eDMA engine. For data transfers where the
source and destination sizes are equal, the eDMA engine performs a series of source read/
destination write operations until the number of bytes specified in the minor loop byte count has
been moved from the source to the destination.
For descriptors where the sizes are not equal, multiple accesses of the smaller size data are
required for each reference of the larger size. As an example, if the source size references 16-bit
data and the destination is 32-bit data, the eDMA performs two reads, then one 32-bit write.
The transfer control descriptor local memory is further partitioned into:
Table 7-59. Transfer control descriptor memory
Submodule Description
Memory controller This logic implements the required dual-ported controller, and manages accesses from the eDMA
engine as well as references from the internal peripheral bus. As noted earlier, in simultaneous
accesses, the eDMA engine is given priority and the peripheral transaction is stalled.
Memory array TCD storage for each channel's transfer profile.
7.3.1.3 Features
The eDMA is a highly programmable data-transfer engine optimized to minimize any
required intervention from the host processor. It is intended for use in applications where
the data size to be transferred is statically known and not defined within the transferred
data itself. The eDMA module features:
• All data movement via dual-address transfers: read from source, write to destination
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• Programmable source and destination addresses and transfer size
• Support for complex address calculations
• 32-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage for all transfers
• Connections to the crossbar switch for bus mastering the data movement
• TCD organized to support two-deep, nested transfer operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• One interrupt per channel, which can be asserted at completion of major iteration
count
• Programmable error terminations per channel that are logically summed together
to form one error interrupt to the interrupt controller
• Programmable support for scatter/gather DMA processing
• Support for complex data structures
In the discussion of this module, n is used to reference the channel number.
7.3.2 Modes of operation
The eDMA operates in the following modes:
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Table 7-60. Modes of operation
Mode Description
Normal In Normal mode, eDMA transfers data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with eDMA.
A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the
TCD. The minor loop is the sequence of read-write operations that transfers these NBYTES per
service request. Each service request executes one iteration of the major loop, which transfers
NBYTES of data.
Debug eDMA operation is configurable in Debug mode via the control register:
• If CSR[EDBG] is cleared to 0, eDMA continues to operate.
• If CSR[EDBG] is set to 1, eDMA stops transferring data. If Debug mode is entered when a
channel is active, eDMA continues operation until the channel retires.
7.3.3 Functional description
The operation of eDMA is described in the following subsections.
7.3.3.1 eDMA basic data flow
The basic flow of a data transfer can be partitioned into three segments.
As shown in the following diagram, the first segment involves the channel activation:
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eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer control
descriptor (TCD)
n-1
64
eDMA engine Read data
Program model/
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 7-24. eDMA operation, part 1
This example uses the assertion of the eDMA peripheral request signal to request service
for channel n. Channel activation via software and the TCDn_CSR[START] field follows
the same basic flow as peripheral requests. The eDMA request input signal is registered
internally and then routed through the eDMA engine: first through the control module,
then into the program model and channel arbitration.
In the next cycle, the channel arbitration begins using fixed-priority plus the optional
round-robin algorithm. After arbitration is complete, the activated channel number is sent
through the address path and converted into the required address to access the local
memory for TCDn. Next, the TCD memory is accessed and the required descriptor is
read from the local memory and then loaded into the eDMA engine address path's
primary or secondary channel execution registers. The TCD memory is 64 bits wide to
minimize the time needed to fetch the activated channel descriptor and load it into the
address path registers.
The following diagram illustrates the second part of the basic data flow:
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eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer control
descriptor (TCD)
n-1
64
eDMA engine Read data
Program model/
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 7-25. eDMA operation, part 2
The modules associated with the data transfer (address path, data path, and control) go
through the required sequence of source reads and destination writes to perform the
actual data movement. The source reads are initiated, and the fetched data is temporarily
stored in the data path block until it is gated onto the internal bus during the destination
write. This source read/destination write processing continues until the byte count,
NBYTES, has been transferred.
After NBYTES of data has been moved, the final phase of the basic data flow is
performed. In this segment, the address path logic performs the required updates to
certain fields in the appropriate TCD (for example, SADDR, DADDR, CITER). If the
major iteration count is exhausted, additional operations are performed. These include the
final address adjustments and reloading of the BITER field into the CITER field.
Assertion of an optional interrupt request also occurs at this time, as does a possible fetch
of a new TCD from memory using the scatter/gather address pointer included in the
descriptor (if scatter/gather is enabled). The updates to the TCD memory and the
assertion of an interrupt request are shown in the following diagram.
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eDMA
Write address
Write data
0
1
2
Internal peripheral bus
To/from crossbar switch
Transfer control
descriptor (TCD)
n-1
64
eDMA engine Read data
Program model/
channel arbitration
Read data
Address path
Control
Data path
Write data
Address
eDMA eDMA
peripheral done
request
Figure 7-26. eDMA operation, part 3
7.3.3.2 Fault reporting and handling
Channel errors are reported in the Error Status register (CHn_CSR and TCDn_CSR) and
can be caused by any of the following:
• A configuration error, which is an illegal setting in the transfer control descriptor
• An active channel canceled via a "cancel transfer with error" hardware or software
request
• An error termination to a bus master read or write cycle
A configuration error is reported when an inconsistent state is represented by one of these
factors:
• Starting source or destination address
• Source or destination offsets
• Minor loop byte count
• Transfer size
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Each of these possible causes is detailed below:
• The addresses and offsets must be aligned on zero-modulo-transfer-sized boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
• All source reads and destination writes must be configured to the natural boundary of
the programmed transfer size.
Note
To aid in debugging, set the Halt After Error field in the
DMA’s Control Status register, CSR[HAE]. Upon any
error condition, the DMA is halted after the error is
recorded. The DMA remains halted and does not process
any channel service requests. After the error is fixed, the
DMA may be enabled again by clearing the Halt field,
CSR[HALT].
• If a scatter/gather operation is enabled upon channel completion, a configuration
error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32-
byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration
error is reported when the link is attempted if the TCDn_CITER[ELINK] field does
not equal the TCDn_BITER[ELINK] field.
If enabled, all configuration error conditions, except the scatter/gather and minor-loop
link errors, are reported as the channel activates and asserts an error interrupt request. A
scatter/gather configuration error is reported when the scatter/gather operation begins at
major loop completion if properly enabled. A minor loop channel link configuration error
is reported when the link operation is serviced at minor loop completion.
The occurrence of any error causes the eDMA engine to stop normal processing of the
active channel immediately (it goes to its error processing states and the transaction to the
system bus still has pipeline effect), and the appropriate channel field in the eDMA error
register is set to 1. At the same time, the details of the error condition are loaded into the
Error Status register (CHn_CSR and TCDn_CSR). The major loop complete indicators,
setting the transfer control descriptor DONE flag, and the possible assertion of an
interrupt request are not affected when an error is detected.
After the error status has been updated, the eDMA engine continues operating by
servicing the next appropriate channel. A channel that experiences an error condition is
not automatically disabled. If a channel is terminated by an error and then issues another
service request before the error is fixed, that channel executes and terminates with the
same error condition.
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The error status fields are read-only. These error indicators are sticky and cannot be
cleared. They show the last recorded error until the DMA is reset. The valid field (VLD)
is used to determine if a new error condition exists. This field is the logical OR of each
channel's error interrupt field (ERR).
After the software has resolved any errors and cleared all of the error interrupt fields, the
valid field is cleared to 0 but the cause of the last error is still indicated.
7.3.3.3 Channel preemption
Channel preemption is enabled on a per-channel basis by setting the CHn_PRI[ECP]
field. Channel preemption allows the executing channel’s data transfers to temporarily
suspend in favor of starting a higher-priority channel. After the preempting channel has
completed all of its minor loop data transfers, the preempted channel is restored and
resumes execution.
After the restored channel completes one read/write sequence, it is again eligible for
preemption. If any higher priority channel is requesting service, the restored channel is
suspended, and the higher-priority channel is serviced. Nested preemption, that is,
attempting to preempt a preempting channel, is not supported. After a preempting
channel begins execution, it cannot be preempted.
A channel’s ability to preempt another channel can be disabled by setting
CHn_PRI[DPA] to 1. When a channel’s preempt ability is disabled, that channel cannot
suspend a lower-priority channel’s data transfer, regardless of the lower-priority
channel’s ECP setting. This allows for a pool of low-priority, large-data-moving channels
to be defined.
You can configure these low-priority channels to not preempt each other, thus preventing
a low-priority channel from consuming the preempt slot normally available to a true
high-priority channel. When you enable round-robin channel arbitration mode
(CSR[ERCA] is set to 1), any channel with a priority level equal to 0 (CHn_PRI[APL] =
0) has preemption disabled and cannot preempt another channel.
7.3.4 Initialization/application information
The following sections discuss initialization of the eDMA and programming
considerations.
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7.3.4.1 eDMA initialization
To initialize the eDMA:
1. Write to the MP_CSR if a configuration other than the default is wanted.
2. Write the channel priority levels to the CHn_PRI registers and group priority levels
to the CHn_GRPRI registers if a configuration other than the default is wanted.
3. Enable error interrupts in the CHn_CSR[EEI] registers if they are wanted.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the CHn_CSR[ERQ] registers.
6. Request channel service via either:
• Software: setting TCDn_CSR[START]
• Hardware: slave device asserting its eDMA peripheral request signal
After any channel requests service, a channel is selected for execution based on the
arbitration and priority levels written into the programmer's model. The eDMA engine
reads the entire TCD, including the TCD control and status fields, as shown in Table
7-61, for the selected channel into its internal address path module.
As the TCD is read, the first transfer is initiated on the internal bus, unless a
configuration error is detected. Transfers from the source, defined by TCDn_SADDR, to
the destination, defined by TCD_DADDR, continue until the number of bytes specified
by TCDn_NBYTES are transferred.
When the transfer is complete, the eDMA engine's local TCDn_SADDR,
TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted, then
eDMA executes further post-processing, such as interrupts, major loop channel linking,
and scatter/gather operations, if enabled.
Table 7-61. TCD control and status (TCDn_CSR) fields
TCDn_CSR field
Description
name
START Control field to start the channel explicitly when using a software-initiated DMA service
(automatically cleared by hardware)
EEOP Control field to enable end-of-packet processing
ESDA Control field to enable storing of the destination address to system memory after the major loop
completes
DREQ Control field to disable hardware-initiated DMA service requests after major loop completion
BWC Control field for throttling the bandwidth control of a channel
ESG Control field to enable the scatter-gather feature
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Table 7-61. TCD control and status (TCDn_CSR) fields (continued)
TCDn_CSR field
Description
name
INTHALF Control field to enable interrupt when major loop is half-complete
INTMAJOR Control field to enable interrupt when major loop completes
Table 7-62. Channel control and status (CHn_CSR) fields
CHn_CSR field name Description
ACTIVE Status field indicating the channel is currently in execution
DONE Status field indicating major loop completion (cleared by software when a channel begins execution)
EEI Control field to enable error interrupts
EARQ Control field to enable external, asynchronous wakeup event in conjunction with the ERQ field
ERQ Control field to enable hardware service requests
The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
Current major
loop iteration
Source or destination memory count (CITER)
DMA request
• Minor loop 3
•
•
DMA request
• Minor loop Major loop 2
•
•
DMA request
• Minor loop 1
•
•
Figure 7-27. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings are related.
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xADDR: (starting address) xSIZE: (size of one
data transfer) Minor loop
(NBYTES in
• minor loop, Offset (xOFF): number of bytes added to
• often the same current address after each transfer
• value as xSIZE) (often the same value as xSIZE)
Each DMA source (S) and
destination (D) has its own:
• •
• •
Address (xADDR)
• • Size (xSIZE)
Minor loop Offset (xOFF)
• •
• • Modulo (xMOD)
• • Last Address Adjustment (xLAST)
where x = S or D
Peripheral queues typically
have size and offset equal
•
• Last minor loop to NBYTES
•
xLAST: Number of bytes added to
current address after major loop
(typically used to loop back)
Figure 7-28. Memory array terms
7.3.4.2 eDMA arbitration
The eDMA uses a layered arbitration scheme composed of multiple priority levels. The
eDMA uses a fixed-priority arbitration scheme with optional round-robin arbitration
under specific conditions. The priorities are evaluated in the following order:
Table 7-63. eDMA arbitration priorities
Priority Scheme Description
1 (Highest) Arbitration group priority Each channel is assigned an arbitration
group via the CHn_GRPRI registers.
Priority is given to the highest value (31
being the highest possible value) down
to the lowest value (zero, the default).
2 Channel priority Each channel is assigned a channel
priority level via the CHn_PRI registers.
The channel priority is a relative priority
level within an arbitration group. Priority
is given to the highest value (seven
being the highest possible value) down
to the lowest value (zero, the default).
Channel priorities within each arbitration
group need not be unique. If multiple
channels have the same channel priority
level, the channel number will be used to
determine priority as defined in row
three.
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Table 7-63. eDMA arbitration priorities (continued)
Priority Scheme Description
3 Channel number When two or more channels have the
same arbitration group priority and
channel priority, the channel number
(CHn_NUM) is used to determine the
highest priority. Priority is giver to the
highest channel number. Lowest priority
is channel 0. The channel numbers are
static and cannot be changed in the
programmer's model.
4 (Lowest) Round-robin When round-robin is enabled, any
channel configured for round-robin
operation has lowest priority within an
arbitration group. Round-robin is
enabled by setting the MP_CSR[ERCA]
field to 1. After being enabled, channels
with a channel priority of zero
(CHn_PRI=0) will use round-robin
arbitration. Round-robin arbitration will
rotate the channel selection among the
channels requesting service with
CHn_PRI=0 within the arbitration group.
Any non-zero channel within the
arbitration group will continue to use
fixed-priority arbitration, and if requesting
service will be selected over any round-
robin channels.
For fixed arbitration, the overall priority can be considered a number composed of three
concatenated priority levels: CHn_GRPRI :CHn_PRI:CH_NUM. The largest number has
the highest priority and the lowest number has the lowest priority.
For round-robin arbitration, the priority number is CHn_GRPRI :0:X. The module rotates
through the CHn_PRI=0 channels requesting service without regard to priority among
these channels. Any channel within the arbitration group for which CHn_PRI is greater
than 0 will be serviced before the round-robin channels.
7.3.4.3 Programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency
in the descriptor data.
The channel number causing the error is recorded in the Error Status register (CHn_CSR
and TCDn_CSR). If the error source is not removed before the next activation of the
problematic channel, the error is detected and recorded again. Setting the halt after error
field, CSR[HAE], will halt the DMA and prevent reoccurrence of the error.
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7.3.4.4 Arbitration mode considerations
This section discusses arbitration considerations for eDMA.
7.3.4.4.1 Fixed group arbitration, fixed channel arbitration
In this mode, eDMA selects for execution the channel service request from the highest-
priority channel in the highest-priority group. If eDMA is programmed so that the
channels within a high-priority group have a high number of requests or large data
transfers, that group may consume all the bandwidth of the eDMA controller. That is, no
lower-priority groups are serviced if there is always at least one DMA request pending on
a channel in the highest-priority group when the controller arbitrates the next DMA
request. The advantage of this scenario is that latency can be small for channels that need
to be serviced quickly.
7.3.4.4.2 Fixed group arbitration, round-robin channel arbitration
The highest-priority group with a request is serviced. Lower-priority groups are serviced
if no pending requests exist in the higher-priority groups.
Within each group, channels are serviced starting with the highest non-zero channel
priority. For all channels with a channel priority programmed to 0, selection begins with
the highest channel number requesting service and then rotates through to the lowest
channel number requesting service. The round-robin channel arbitration can provide a
fairness mechanism to lower-priority channels.
This scenario could cause the same bandwidth consumption problem as indicated in
Fixed group arbitration, fixed channel arbitration, but all the channels in the highest-
priority group will be serviced. Service latency is short on the highest-priority group, but
could potentially be very much longer as the group priority decreases.
7.3.4.5 Performing DMA transfers
This section presents examples on how to perform DMA transfers with the eDMA.
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7.3.4.5.1 Single request
To perform a simple transfer of n bytes of data with one activation, set the major loop to
one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel
service request is acknowledged and the channel is selected to execute. After the transfer
is complete, the CHn_CSR[DONE] field is set to 1 and an interrupt is generated if
properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The
eDMA is programmed for one iteration of the major loop transferring 16 bytes per
iteration. The source memory has a byte-wide memory port located at 0x1000. The
destination memory has a 32-bit port located at 0x2000. The address offsets are
programmed in increments to match the transfer size: one byte for the source, and four
bytes for the destination. The final source and destination addresses are adjusted to return
to their beginning values.
TCDn_CITER = TCDn_BITER = 1
TCDn_NBYTES = 16
TCDn_SADDR = 0x1000
TCDn_SOFF = 1
TCDn_ATTR[SSIZE] = 0
TCDn_SLAST = -16
TCDn_DADDR = 0x2000
TCDn_DOFF = 4
TCDn_ATTR[DSIZE] = 2
TCDn_DLAST_SGA= –16
TCDn_CSR[INTMAJ] = 1
TCDn_CSR[START] = 1 (should be written last after all other fields have been initialized)
All other TCDn fields = 0
This generates the following event sequence:
1. User write to the TCDn_CSR[START] field requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes:
• CHn_CSR[DONE] = 0
• TCDn_CSR[START] = 0
• CHn_CSR[ACTIVE] = 1
4. eDMA engine reads: channel TCD data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32 bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
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d. Write 32 bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32 bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32 bits to location 0x200C → last iteration of the minor loop → major loop
complete.
6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 1 (TCDn_BITER).
7. The eDMA engine writes: CHn_CSR[ACTIVE] = 0, CHn_CSR[DONE] = 1,
CHn_INT[INT] = 1.
8. The channel retires and the eDMA goes idle or services the next channel.
7.3.4.5.2 Multiple requests
The following example transfers 32 bytes via two hardware requests, but is otherwise the
same as the previous example. The only fields that change are the major loop iteration
count and the final address offsets. The eDMA is programmed for two iterations of the
major loop, transferring 16 bytes per iteration. After the channel's hardware requests are
enabled via the CHn_CSR[ERQ] register field, the slave device initiates channel service
requests.
TCDn_CITER = TCDn_BITER = 2
TCDn_SLAST = –32
TCDn_DLAST_SGA = –32
This would generate the following sequence of events:
1. First hardware (eDMA peripheral) requests channel service.
2. The channel is selected by arbitration for servicing.
3. eDMA engine writes: CHn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
CHn_CSR[ACTIVE] = 1.
4. eDMA engine reads: channel TCDn data from local memory to internal register file.
5. The source-to-destination transfers are executed as follows:
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a. Read byte from location 0x1000, read byte from location 0x1001, read byte from
0x1002, read byte from 0x1003.
b. Write 32 bits to location 0x2000 → first iteration of the minor loop.
c. Read byte from location 0x1004, read byte from location 0x1005, read byte from
0x1006, read byte from 0x1007.
d. Write 32 bits to location 0x2004 → second iteration of the minor loop.
e. Read byte from location 0x1008, read byte from location 0x1009, read byte from
0x100A, read byte from 0x100B.
f. Write 32 bits to location 0x2008 → third iteration of the minor loop.
g. Read byte from location 0x100C, read byte from location 0x100D, read byte
from 0x100E, read byte from 0x100F.
h. Write 32 bits to location 0x200C → last iteration of the minor loop.
6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010,
TCDn_CITER = 1.
7. eDMA engine writes: CHn_CSR[ACTIVE] = 0.
8. The channel retires, which concludes one iteration of the major loop. The eDMA
goes idle or services the next channel.
9. Second hardware (eDMA peripheral) requests channel service.
10. The channel is selected by arbitration for servicing.
11. eDMA engine writes: CHn_CSR[DONE] = 0, TCDn_CSR[START] = 0,
CHn_CSR[ACTIVE] = 1.
12. eDMA engine reads: Channel TCD data from local memory to internal register file.
13. The source-to-destination transfers are executed as follows:
a. Read byte from location 0x1010, read byte from location 0x1011, read byte from
0x1012, read byte from 0x1013.
b. Write 32 bits to location 0x2010 → first iteration of the minor loop.
c. Read byte from location 0x1014, read byte from location 0x1015, read byte from
0x1016, read byte from 0x1017.
d. Write 32 bits to location 0x2014 → second iteration of the minor loop.
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e. Read byte from location 0x1018, read byte from location 0x1019, read byte from
0x101A, read byte from 0x101B.
f. Write 32 bits to location 0x2018 → third iteration of the minor loop.
g. Read byte from location 0x101C, read byte from location 0x101D, read byte
from 0x101E, read byte from 0x101F.
h. Write 32 bits to location 0x201C → last iteration of the minor loop → major loop
complete.
14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000,
TCDn_CITER = 2 (TCDn_BITER).
15. eDMA engine writes: CHn_CSR[ACTIVE] = 0, CHn_CSR[DONE] = 1,
CHn_INT[INT] = 1.
16. The channel retires, which concludes with the major loop complete. The eDMA goes
idle or services the next channel.
7.3.4.5.3 Using the modulo feature
The modulo feature of the eDMA allows implementation of a circular data queue in
which the size of the queue is a power of 2. xMOD is a 5-bit field for the source and
destination in the TCD, and it specifies which lower address bits increment from their
original value after the address+offset calculation. All upper address bits remain the same
as in the original value. A setting of 0 for this field disables the modulo feature. Modulo
addressing applies to cases where the minor loop offset is enabled; that is, the upper
address bits remain the same after the minor loop offset is added to the source or
destination address.
The following table shows how the transfer addresses are specified based on the setting
of the MOD field. Here a circular buffer is created where the address wraps to the
original value but the 28 upper address bits (0x1234567x) retain their original value. In
this example, the source address is set to 0x12345670, the offset is set to four bytes, and
the MOD field is set to four, which allows for a 24 byte (16 byte) queue size.
Table 7-64. Modulo example
Transfer number Address
1 0x12345670
2 0x12345674
3 0x12345678
4 0x1234567C
5 0x12345670
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Table 7-64. Modulo example (continued)
Transfer number Address
6 0x12345674
7.3.4.6 Monitoring transfer descriptor status
This section discusses how to monitor eDMA status.
7.3.4.6.1 Testing for minor loop completion
There are two methods to test for minor loop completion when using software-initiated
service requests.
1. The first method is to read the TCDn_CITER field and test for a change.
2. The second method, extracted from the sequence shown below, is to test the
TCDn_CSR[START] field and the CHn_CSR[ACTIVE] field. The minor-loop-
complete condition is indicated by both fields reading 0 after TCDn_CSR[START] is
set to 1. Polling the CHn_CSR[ACTIVE] field only may be inconclusive because the
active status may be missed if the channel execution is short in duration.
The CHn_CSR and TCDn_CSR status fields execute the following sequence for a
software-activated channel:
TCDn_CSR
CHn_CSR fields
Stage field State
START ACTIVE DONE
1 1 0 0 Initiate channel service request via software.
2 0 1 0 Channel is executing.
3a 0 0 0 Channel has completed the minor loop and is idle.
3b 0 0 1 Channel has completed the major loop and is idle.
The best method to test for minor-loop completion when using hardware-initiated (that is,
peripheral-initiated) service requests is to read the TCDn_CITER field and test for a
change. The hardware request and acknowledge handshake signals are not visible in the
programmer's model.
The TCD status fields execute the following sequence for a hardware-activated channel:
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TCDn_CSR
CHn_CSR fields
Stage field State
START ACTIVE DONE
Initiate channel service request via hardware
1 0 0 0
(peripheral request asserted).
2 0 1 0 Channel is executing.
3a 0 0 0 Channel has completed the minor loop and is idle.
3b 0 0 1 Channel has completed the major loop and is idle.
For both activation types, the major-loop-complete status is explicitly indicated via the
CHn_CSR[DONE] field.
The TCDn_CSR[START] field is cleared to 0 automatically when the channel begins
execution, regardless of how the channel activates.
7.3.4.6.2 Reading the transfer descriptors of active channels
The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES
values if they are read when a channel executes. The true values of SADDR, DADDR,
and NBYTES are the values the eDMA engine currently uses in its internal register file,
and not the values in the TCD local memory for that channel. The addresses, SADDR
and DADDR, and NBYTES (which decrements to zero as the transfer progresses), can
give an indication of the progress of the transfer. All other values are read back from the
TCD local memory.
7.3.4.6.3 Checking channel preemption status
A preemptive situation is one in which a preempt-enabled channel is executing and a
higher-priority request becomes active. When round-robin channel arbitration mode is
enabled, all channels with their channel priority set to 0 lose their preempt ability.
Channel priorities of 0 are treated as equal, that is, they are constantly rotating, when
round-robin arbitration mode is enabled.
The CHn_CSR[ACTIVE] field for the preempted channel remains asserted throughout
the preemption. The preempted channel is temporarily suspended when the preempting
channel executes one major loop iteration. If two CHn_CSR[ACTIVE] fields are set
simultaneously in the global TCD map, a higher-priority channel is actively preempting a
lower-priority channel.
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7.3.4.7 Channel linking
Channel linking (or chaining) is a mechanism in which one channel sets the
TCDn_CSR[START] field of another channel (or itself), thus initiating a service request
for that channel. When properly enabled, the eDMA engine automatically performs this
operation at the major or minor loop completion.
The minor loop channel linking occurs at the completion of the minor loop (or one
iteration of the major loop). The TCDn_CITER[ELINK] field determines whether a
minor loop link is requested. When enabled, the channel link is made after each iteration
of the major loop except for the last. When the major loop is exhausted, only the major
loop channel link fields are used to determine if a channel link should be made. For
example, using an initial field setting of:
TCDn_CITER[ELINK] = 1
TCDn_CITER[LINKCH] = 0xC
TCDn_CITER[CITER] value = 0x4
TCDn_CSR[MAJORELINK] = 1
TCDn_CSR[MAJORLINKCH] = 0x7
executes as:
1. Minor loop done → set TCD12_CSR[START] field
2. Minor loop done → set TCD12_CSR[START] field
3. Minor loop done → set TCD12_CSR[START] field
4. Minor loop done, major loop done→ set TCD7_CSR[START] field
When minor loop linking is enabled (TCDn_CITER[ELINK] = 1), the
TCDn_CITER[CITER] field uses a nine-bit vector to form the current iteration count.
When minor loop linking is disabled (TCDn_CITER[ELINK] = 0), the
TCDn_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The
bits associated with the TCDn_CITER[LINKCH] field are concatenated onto the CITER
value to increase the range of the CITER.
Note
The TCDn_CITER[ELINK] field and the
TCDn_BITER[ELINK] field must be equal — if they are not, a
configuration error is reported. The CITER and BITER vector
widths must be equal to calculate the major loop halfway done
interrupt point.
The following table summarizes how a DMA channel can link to another DMA channel,
that is, use another channel's TCD, at the end of a loop.
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Table 7-65. Channel linking parameters
Wanted link
TCD control field name Description
behavior
Link at end of TCDn_CITER[ELINK] Enable channel-to-channel linking on minor loop completion (current
minor loop iteration)
TCDn_CITER[LINKCH] Link channel number when linking at end of minor loop (current iteration)
Link at end of TCDn_CSR[MAJORELINK] Enable channel-to-channel linking on major loop completion
major loop TCDn_CSR[MAJORLINKCH] Link channel number when linking at end of major loop
7.3.4.8 Dynamic programming
This section provides recommended methods to change the programming model during
channel execution.
7.3.4.8.1 Dynamically changing the channel priority
To change group or channel priority levels:
1. Halt the DMA by writing 1 to the CSR[HALT] field.
2. Change the group or channel priorities as wanted.
3. Enable normal DMA operations by writing 0 to the CSR[HALT] field.
7.3.4.8.2 Dynamic channel linking
Dynamic channel linking is the process of setting the TCDn_CSR[MAJORELINK] field
during channel execution (see the diagram in TCD structure). This field is read from the
TCD local memory at the end of channel execution, thus allowing you to enable the
feature during channel execution.
Because you are allowed to change the configuration during execution, you need a
coherency model. Consider the scenario where you attempt to execute a dynamic channel
link by enabling the TCDn_CSR[MAJORELINK] field at the same time the eDMA
engine is retiring the channel. TCDn_CSR[MAJORELINK] would be set in the
programmer’s model, but it would be unclear whether the actual link was made before
the channel retired.
We recommend that you use the following coherency model when executing a dynamic
channel link request.
1. Write 1 to the TCDn_CSR[MAJORELINK] field.
2. Read back the TCDn_CSR[MAJORELINK] field.
3. Test the TCDn_CSR[MAJORELINK] request status:
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• If TCDn_CSR[MAJORELINK] = 1, the dynamic link attempt was successful.
• If TCDn_CSR[MAJORELINK] = 0, the attempted dynamic link did not succeed
(the channel was already retiring).
For this request, the TCD local memory controller forces the
TCDn_CSR[MAJORELINK] field to 0 on any writes to a channel’s TCDn_CSR[7:0]
after that channel’s CHn_CSR[DONE] field is set to 1, indicating the major loop is
complete.
NOTE
You must clear the CHn_CSR[DONE] field to 0 before writing
to the TCDn_CSR[MAJORELINK] field. The
CHn_CSR[DONE] field is cleared to 0 automatically by the
eDMA engine after a channel begins execution.
7.3.4.8.3 Dynamic scatter/gather
Scatter/gather is the process of automatically loading a new TCD into a channel. It allows
a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA
data to multiple destinations or gather it from multiple sources. When scatter/gather is
enabled and the channel has finished its major loop, a new TCD is fetched from system
memory and loaded into that channel’s descriptor location in the eDMA programmer’s
model, thus replacing the current descriptor.
Because you are allowed to change the configuration during execution, you need a
coherency model. Consider the scenario where you attempt to execute a dynamic scatter/
gather operation by enabling the TCDn_CSR[ESG] field at the same time the eDMA
engine is retiring the channel. The TCDn_CSR[ESG] field would be set in the
programmer’s model, but it would be unclear whether the actual scatter/gather request
was honored before the channel retired.
Two methods are recommended for executing a dynamic scatter/gather request.
Whenever the TCDn_CSR is written, the TCD local memory controller forces the
TCDn_CSR[ESG] field to 0 on any writes to a channel’s TCDn_CSR [7:0] after that
channel’s CHn_CSR[DONE] field has been set to 1, indicating the major loop is
complete. If attempting to set the ESG, ensure the DONE field is cleared to 0.
NOTE
You must clear the CHn_CSR[DONE] field to 0 before writing
the TCDn_CSR[MAJORELINK] or TCDn_CSR[ESG] fields.
The CHn_CSR[DONE] field is cleared to 0 automatically by
the eDMA engine after a channel begins execution and is set to
1 upon major loop completion.
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7.3.4.8.3.1 Method 1 (channel not using major loop channel linking)
For a channel not using major loop channel linking, the coherency model described here
may be used for a dynamic scatter/gather request.
When the TCDn_CSR[MAJORELINK] field is 0, the TCDn_CSR[MAJORLINKCH]
field is not used by the eDMA. In this case, the TCDn_CSR[MAJORLINKCH] bits may
be used for other purposes. This method uses the TCDn_CSR[MAJORLINKCH] field as
a TCDn_CSR identification (ID).
When the descriptors are built, write a unique TCDn_CSR ID in the
TCDn_CSR[MAJORLINKCH] field for each TCDn_CSR associated with a channel
using dynamic scatter/gather.
1. Write a 1 to the TCDn_CSR[DREQ] field. Should a dynamic scatter/gather attempt
fail, setting the TCDn_CSR[DREQ] field to 1 will prevent future hardware activation
of this channel. This stops the channel from executing with a destination address
(daddr) that was calculated using a scatter/gather address (written in the next step)
instead of a DLAST final offset value.
2. Write the TCDn_DLAST_SGA field with the scatter/gather address.
3. Write a 1 to the TCDn_CSR[ESG] field.
4. Read back the 16-bit TCDn_CSR control/status field.
5. Test the TCDn_CSR[ESG] request status and TCDn_CSR[MAJORLINKCH] value:
• If ESG = 1, the dynamic scatter/gather attempt was successful.
• If ESG = 0 and the MAJORLINKCH (ID) did not change, the dynamic scatter/
gather attempt was not successful (the channel was already retiring).
• If ESG = 0 and the MAJORLINKCH (ID) changed, the dynamic scatter/gather
attempt was successful (the new TCDn_CSR’s ESG value cleared the ESG field
to 0).
7.3.4.8.3.2 Method 2 (channel using major loop channel linking)
For a channel using major loop channel linking, the coherency model described here may
be used for a dynamic scatter/gather request. This method uses the TCDn_DLAST_SGA
field as a TCD identification (ID).
1. Write a 1 to the TCDn_CSR[DREQ] field. Should a dynamic scatter/gather attempt
fail, setting the DREQ field to 1 will prevent a future hardware activation of this
channel. This stops the channel from executing with a destination address (DADDR)
that was calculated using a scatter/gather address (written in the next step) instead of
a DLAST final offset value.
2. Write the TCDn_DLAST_SGA field with the scatter/gather address.
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3. Write a 1 to the TCDn_CSR[ESG] field.
4. Read back the TCDn_CSR[ESG] field.
5. Test the TCDn_CSR[ESG] request status:
• If ESG = 1, the dynamic scatter/gather attempt was successful.
• If ESG = 0, read the 32-bit TCDn_DLAST_SGA field.
• If ESG = 0 and the TCDn_DLAST_SGA did not change, the dynamic scatter/
gather attempt was not successful (the channel was already retiring).
• If ESG = 0 and the TCDn_DLAST_SGA changed, the dynamic scatter/gather
attempt was successful (the new TCDn_CSR’s ESG value cleared the ESG field
to 0).
7.3.4.9 Suspend/resume a DMA channel with active hardware service
requests
The DMA allows you to move data from memory or peripheral registers to another
location in memory or to peripheral registers without CPU interaction. After the DMA
and peripherals are configured and active, it is rare but supported to suspend a
peripheral's service request dynamically. In this scenario, there are certain restrictions to
disabling a DMA hardware service request. For coherency, you must follow a specific
procedure. This section provides guidance on how to coherently suspend and resume a
Direct Memory Access (DMA) channel when the DMA is triggered by a slave module
such as the Serial Peripheral Interface (SPI), Sigma Delta Analog to Digital Convertor
(SDADC), or other module.
7.3.4.9.1 Suspend an active DMA channel
To suspend an active DMA channel:
1. Stop the DMA service request at the peripheral first. Confirm it has been disabled by
reading back the appropriate register in the peripheral.
2. Check the DMA's Hardware Request Status (MP_HRS) to ensure there is no service
request to the DMA channel being suspended. Then disable the hardware service
request by clearing the ERQ field to 0 on the appropriate DMA channel.
For example, assume the SPI is set as a master for transmitting data via a DMA service
request when the TXFIFO has an empty slot. The DMA will transfer the next command
and data to the TXFIFO upon the request. If you need to suspend the DMA/SPI transfer
loop, perform the following steps:
1. Disable the DMA service request at the source by writing 0 to
DSPI_RSER[TFFF_RE]. Confirm that DSPI_RSER[TFFF_RE] is 0.
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2. Ensure there is no DMA service request from the SPI by verifying that
MP_HRS[HRS] is 0 for the appropriate channel. If no service request is present,
disable the DMA channel by clearing the channel's ERQ field to 0. If a service
request is present, wait until the request has been processed and the HRS field reads
0.
7.3.4.9.2 Resume a DMA channel
To resume a DMA channel:
1. Enable the DMA service request on the appropriate channel by setting its ERQ field
to 1.
2. Enable the DMA service request at the peripheral.
7.3.5 Memory map/register definition
The eDMA programming model is partitioned into three parts:
1. The first part defines a number of registers providing overall control functions and is
known as the management page.
2. The second part corresponds to the channel (CH) control, status, and configuration.
3. The third part corresponds to the local TCD memory.
7.3.5.1 TCD memory
Each channel requires a 32-byte transfer control descriptor for defining the data
movement operation. Each TCDn definition is presented as 11 registers of 16 or 32 bits.
7.3.5.2 TCD initialization
Prior to activating a channel, you must initialize its TCD with the appropriate transfer
profile.
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7.3.5.3 TCD structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0020h SADDR
{
0024h SMOD SSIZE DMOD DSIZE SOFF
NBYTES { DMA_CR[EMLM] disabled
0028h
{
DMLOE
SMLOE
MLOFF or NBYTES NBYTES DMA_CR[EMLM] enabled
002Ch SLAST
0030h DADDR
CITER.ELINK
Reserved
CITER or
0034h CITER DOFF
CITER.LINKCH
0038h DLAST_SGA
MAJOR.ELINK
BITER.ELINK
INTMAJOR
INTHALF
Reserved
Reserved
START
DREQ
EEOP
BITER or
ESDA
ESG
003Ch BITER BWC MAJOR.LINKCH
BITER.LINKCH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Figure 7-29. TCD structure
7.3.5.4 Accesses to reserved memory and fields
• Reading reserved fields in a register returns the value of zero.
• Writes to reserved fields in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
7.3.5.5 DMA MP register descriptions
7.3.5.5.1 MP memory map
MP base address: 30E3_0000h
Offset Register Width Access Reset value
(In bits)
0h Management Page Control (MP_CSR) 32 RW 0030_0000h
4h Management Page Error Status (MP_ES) 32 RO 0000_0000h
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Offset Register Width Access Reset value
(In bits)
8h Management Page Interrupt Request Status (MP_INT) 32 RO 0000_0000h
Ch Management Page Hardware Request Status (MP_HRS) 32 RO 0000_0000h
100h - 17Ch Channel Arbitration Group (CH0_GRPRI - CH31_GRPRI) 32 RW 0000_0000h
7.3.5.5.2 Management Page Control (MP_CSR)
7.3.5.5.2.1 Offset
Register Offset
MP_CSR 0h
7.3.5.5.2.2 Function
The Management Page Control register defines the basic operating configuration of the
DMA.
Arbitration uses a two-tier priority system; group and channel priority. The eDMA
assigns each channel to a priority group. Group arbitration is fixed-priority and cannot be
changed. Channel arbitration uses fixed priority and may be configured to use a selective
round-robin scheme for specified channels within each priority group. For fixed-priority
arbitration, eDMA selects for execution the highest priority channel requesting service in
the highest priority arbitration group.
The channel priority registers assign the relative priorities within each arbitration group;
see CHn_PRI. All channels with a non-zero CHn_PRI value use fixed-priority
arbitration.
When you enable round-robin arbitration, all channels with channel priority set to zero do
not have a priority and, of those channels requesting service, are cycled through (from
high to low channel number) without regard to priority relative to each other within the
same priority group. Any channel with a non-zero CHn_PRI value automatically has a
higher priority over the round-robin channels. A channel's priority group is assigned in
Channel Arbitration Group (CH0_GRPRI - CH31_GRPRI).
NOTE
For correct operation, changes to the CSR[ERCA, GCLC,
GMRC] fields must be performed when the DMA channels are
inactive; that is, when the CSR[ACTIVE] field is 0.
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7.3.5.5.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE_ID
Reserved
Reserved
ACTIVE
W
Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Reserved
0 Reserved
0 Reserved
R
GMRC
ERCA
EDBG
GCLC
HALT
ECX
HAE
CX
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.5.2.4 Fields
Field Function
31 DMA Active Status
0b - eDMA is idle
ACTIVE
1b - eDMA is executing a channel
30-29 Reserved
—
28-24 Active Channel ID
ACTIVE_ID This field identifies the channel number that is executing when the ACTIVE bit is 1.
23-16 Reserved
—
15-10 Reserved
—
9 Cancel Transfer
CX When set to 1, this field cancels the remaining data transfer, stops the executing channel, and forces the
minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. CX
clears itself to 0 after the cancel has been honored. This cancel retires the channel normally as if the
minor loop had been completed.
0b - Normal operation
1b - Cancel the remaining data transfer
8 Cancel Transfer With Error
ECX Cancellation of the remaining data transfer is similar to that of the CX field. Execution of the the channel
is stopped and the minor loop is forced to finish. The cancellation takes effect after the last write of the
current read/write sequence. The ECX field clears itself to 0 after the cancel is honored. In addition to
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Field Function
cancelling the transfer, ECX treats the cancel as an error condition, thus updating Management Page
Error Status (MP_ES) and generating an optional error interrupt.
0b - Normal operation
1b - Cancel the remaining data transfer
7 Global Master ID Replication Control
GMRC NOTE: If master ID replication is disabled, the privileged protection level (Supervisor mode) for DMA
transfers is used.
0b - Master ID replication disabled for all channels
1b - Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting
6 Global Channel Linking Control
0b - Channel linking disabled for all channels
GCLC
1b - Channel linking available and controlled by each channel's link settings
5 Halt DMA Operations
HALT This field stalls the start of any new channels. Executing channels are allowed to complete. Channel
execution resumes when this field is cleared to 0.
0b - Normal operation
1b - Stall the start of any new channels
4 Halt After Error
HAE When this field is set to 1, any error causes the HALT field to be set to 1. Then all service requests are
ignored until the HALT field is cleared to 0.
0b - Normal operation
1b - Any error causes the HALT field to be set to 1
3 Reserved
—
2 Enable Round Robin Channel Arbitration
0b - Round-robin channel arbitration disabled. Fixed priority arbitration used for channel selection
ERCA
within each group
1b - Round-robin channel arbitration enabled. Round-robin arbitration used for channel selection
within each group
1 Enable Debug
EDBG When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to
complete. DMA resumes channel execution when the system exits debug mode or clears the EDBG field
to 0.
0b - Debug mode disabled. When in debug mode, the DMA continues to operate
1b - Debug mode is enabled. When in debug mode, the DMA stalls the start of a new channel
0 Reserved
—
7.3.5.5.3 Management Page Error Status (MP_ES)
7.3.5.5.3.1 Offset
Register Offset
MP_ES 4h
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7.3.5.5.3.2 Function
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• An illegal setting in the transfer control descriptor
• An error termination to a bus master read or write cycle
• An uncorrectable error that occurred when the device was accessing the TCD SRAM
• A "cancel transfer with error" request was made via the corresponding cancel transfer
field or input signal
Upon any error condition, the software must initialize the TCD of the channel that
contains the error, as it is in an incomplete state after an error. See Fault reporting and
handling for more details.
7.3.5.5.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ERRCHN
Reserved
VLD
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 ECX SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.5.3.4 Fields
Field Function
31 Valid
VLD Logical OR of all ERR status fields.
0b - No ERR fields are set to 1
1b - At least one ERR field is set to 1, indicating a valid error exists that software has not cleared
30-29 Reserved
—
28-24 Error Channel Number or Canceled Channel Number
ERRCHN The channel number of the last recorded error or last recorded error-canceled transfer.
23-9 Reserved
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Field Function
—
8 Transfer Canceled
ECX The ECX operation is a management page function. When employed, the targeted channel's CHn_ES
register reports an unspecified error; that is, only the ERR field is set to 1. The management page has full
view of the error condition.
0b - No canceled transfers
1b - Last recorded entry was a canceled transfer by the error cancel transfer input
7 Source Address Error
SAE When this field is 1, it indicates that TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
0b - No source address configuration error
1b - Last recorded error was a configuration error detected in the TCDn_SADDR field
6 Source Offset Error
SOE When this field is 1, it indicates that TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
0b - No source offset configuration error
1b - Last recorded error was a configuration error detected in the TCDn_SOFF field
5 Destination Address Error
DAE When this field is 1, it indicates that TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
0b - No destination address configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DADDR field
4 Destination Offset Error
DOE When this field is 1, it indicates that TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
0b - No destination offset configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DOFF field
3 NBYTES/CITER Configuration Error
NCE This error indicates that one of the following has occurred:
• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE]
• TCDn_CITER[CITER] is equal to zero
• TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
0b - No NBYTES/CITER configuration error
1b - The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error. Last
recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields
2 Scatter/Gather Configuration Error
SGE When this field is 1, it indicates that TCDn_DLAST_SGA is not on a 32-byte boundary. This field is
checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
enabled.
0b - No scatter/gather configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
1 Source Bus Error
0b - No source bus error
SBE
1b - Last recorded error was a bus error on a source read
0 Destination Bus Error
0b - No destination bus error
DBE
1b - Last recorded error was a bus error on a destination write
7.3.5.5.4 Management Page Interrupt Request Status (MP_INT)
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7.3.5.5.4.1 Offset
Register Offset
MP_INT 8h
7.3.5.5.4.2 Function
This register shows the current state of the interrupt service requests for all eDMA
channels.
7.3.5.5.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R INT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.5.4.4 Fields
Field Function
31-0 Interrupt Request Status
INT The INT register presents the interrupt request status for each eDMA channel. Depending on the
appropriate field setting in the transfer control descriptors, the eDMA engine generates an interrupt on
data transfer completion. The eDMA routes channel interrupt requests to the interrupt controller. During
the interrupt service routine associated with any given channel, it is the software's responsibility to clear
the appropriate field in the channel’s interrupt request register, CHn_INT, thus negating the interrupt
request.
0b - Interrupt request for corresponding channel not present
1b - Interrupt request for corresponding channel present
7.3.5.5.5 Management Page Hardware Request Status (MP_HRS)
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7.3.5.5.5.1 Offset
Register Offset
MP_HRS Ch
7.3.5.5.5.2 Function
The hardware request status register (HRS) shows the current state of the hardware
service request signaling as seen by eDMA's arbitration logic.
7.3.5.5.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R HRS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R HRS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.5.5.4 Fields
Field Function
31-0 Hardware Request Status
HRS The HRS bit for its respective channel remains asserted for the period when a hardware request is
present on the channel. After the request is completed and the channel is free, the hardware
automatically clears the corresponding HRS bit to 0.
0b - Hardware service request for corresponding channel is not present
1b - Hardware service request for corresponding channel is present
7.3.5.5.6 Channel Arbitration Group (CH0_GRPRI - CH31_GRPRI)
7.3.5.5.6.1 Offset
For n = 0 to 31:
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Register Offset
CHn_GRPRI 100h + (n × 4h)
7.3.5.5.6.2 Function
The contents of this register define the arbitration group associated with each channel.
Using a fixed-priority group arbitration scheme, eDMA evaluates the arbitration group
priorities by numeric value from highest group number to lowest; for example, 0 is the
lowest priority, 1 is the next higher priority, then 2, 3, and so on. The range of the group
priority values is limited to the values of 0 through 31. Within each arbitration group, the
channel priority assignment CHn_PRI determines the highest-priority channel.
7.3.5.5.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
GRPRI
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.5.6.4 Fields
Field Function
31-5 Reserved
—
4-0 Arbitration Group For Channel n
GRPRI Fixed-priority arbitration group number.
7.3.5.6 DMA TCD register descriptions
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7.3.5.6.1 TCD memory map
TCD base address: 1_0000h
Offset Register Width Access Reset value
(In bits)
0h - 1_F000h Channel Control and Status (CH0_CSR - CH31_CSR) 32 RW 0000_0000h
4h - 1_F004h Channel Error Status (CH0_ES - CH31_ES) 32 W1C 0000_0000h
8h - 1_F008h Channel Interrupt Status (CH0_INT - CH31_INT) 32 W1C 0000_0000h
Ch - 1_F00Ch Channel System Bus (CH0_SBR - CH31_SBR) 32 RW 0000_8002h
10h - 1_F010h Channel Priority (CH0_PRI - CH31_PRI) 32 RW 0000_0000h
20h - 1_F020h TCD Source Address (TCD0_SADDR - TCD31_SADDR) 32 RW Table 7-629
24h - 1_F024h TCD Signed Source Address Offset (TCD0_SOFF - TCD31_SOFF) 16 RW Table 7-629
26h - 1_F026h TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR) 16 RW Table 7-629
28h - 1_F028h TCD Transfer Size Without Minor Loop Offsets 32 RW Table 7-629
(TCD0_NBYTES_MLOFFNO - TCD31_NBYTES_MLOFFNO)
28h - 1_F028h TCD Transfer Size with Minor Loop Offsets 32 RW Table 7-629
(TCD0_NBYTES_MLOFFYES - TCD31_NBYTES_MLOFFYES)
2Ch - TCD Last Source Address Adjustment / Store DADDR Address 32 RW Table 7-629
1_F02Ch (TCD0_SLAST_SDA - TCD31_SLAST_SDA)
30h - 1_F030h TCD Destination Address (TCD0_DADDR - TCD31_DADDR) 32 RW Table 7-629
34h - 1_F034h TCD Signed Destination Address Offset (TCD0_DOFF - 16 RW Table 7-629
TCD31_DOFF)
36h - 1_F036h TCD Current Major Loop Count (Minor Loop Channel Linking 16 RW Table 7-629
Disabled) (TCD0_CITER_ELINKNO - TCD31_CITER_ELINKNO)
36h - 1_F036h TCD Current Major Loop Count (Minor Loop Channel Linking 16 RW Table 7-629
Enabled) (TCD0_CITER_ELINKYES - TCD31_CITER_ELINKYES)
38h - 1_F038h TCD Last Destination Address Adjustment / Scatter Gather Address 32 RW Table 7-629
(TCD0_DLAST_SGA - TCD31_DLAST_SGA)
3Ch - TCD Control and Status (TCD0_CSR - TCD31_CSR) 16 RW Table 7-629
1_F03Ch
3Eh - TCD Beginning Major Loop Count (Minor Loop Channel Linking 16 RW Table 7-629
1_F03Eh Disabled) (TCD0_BITER_ELINKNO - TCD31_BITER_ELINKNO)
3Eh - TCD Beginning Major Loop Count (Minor Loop Channel Linking 16 RW Table 7-629
1_F03Eh Enabled) (TCD0_BITER_ELINKYES - TCD31_BITER_ELINKYES)
7.3.5.6.2 Channel Control and Status (CH0_CSR - CH31_CSR)
7.3.5.6.2.1 Offset
For n = 0 to 31:
Register Offset
CHn_CSR 0h + (n × 1000h)
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7.3.5.6.2.2 Function
This register contains several fields related to hardware and interrupt requests,
configuration, and status for the given channel.
7.3.5.6.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ACTIVE
DONE
R
W1C
W
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EARQ
EBW
ERQ
EEI
W
0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.6.2.4 Fields
Field Function
31 Channel Active
ACTIVE The ACTIVE field indicates the channel was selected by arbitration and is executing the prescribed
transfers. The eDMA sets it to 1 when channel service begins, and clears it to 0 as the minor loop
completes or when any error condition is detected. Except for dynamic scatter/gather or dynamic channel
linking, you must not modify the transfer control descriptor when a channel is active.
30 Channel Done
DONE The DONE field indicates the eDMA has completed the major loop. The eDMA engine sets this field as
the CITER count reaches zero. If enabled, the eDMA generates an interrupt request corresponding to this
completed channel. The software clears it, or the hardware clears it when the channel is activated.
NOTE: This field must be cleared to 0 before writing the MAJORELINK or ESG fields.
29-4 Reserved
—
3 Enable Buffered Writes
EBW When buffered writes are enabled, all writes except for the last write sequence of the minor loop are
signaled by the eDMA as bufferable.
0b - Buffered writes on system bus disabled. Buffered writes on system bus disabled
1b - Buffered writes on system bus enabled. Bufferable write signal asserted on all system bus
writes except during last write sequence
2 Enable Error Interrupt
EEI
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Field Function
The EEI field enables the error interrupt signal for the channel. The DMA error indicator and the error
interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to
the interrupt controller.
0b - Error signal for corresponding channel does not generate error interrupt
1b - Assertion of error signal for corresponding channel generates error interrupt request
1 Enable Asynchronous DMA Request In Stop Mode For Channel
EARQ The enable asynchronous DMA request field (EARQ) does not affect DMA operations. When set to 1, this
field allows the hardware service request enable field (ERQ) to propagate out of the DMA to the power
controller. When cleared to 0, this field masks the hardware service request enable field to the power
controller.
0b - Disable asynchronous DMA request for the channel
1b - Enable asynchronous DMA request for the channel
0 Enable DMA Request
ERQ Disable a channel's hardware service request at the source before clearing the channel's ERQ field. The
DMA hardware request input signal and the enable request field (ERQ) must be asserted before a
channel's hardware service request is accepted. The state of the eDMA enable request field does not
affect a channel service request made explicitly through software or channel linking. The state of the ERQ
field does not affect the channel's START field.
0b - DMA hardware request signal for corresponding channel disabled
1b - DMA hardware request signal for corresponding channel enabled
7.3.5.6.3 Channel Error Status (CH0_ES - CH31_ES)
7.3.5.6.3.1 Offset
For n = 0 to 31:
Register Offset
CHn_ES 4h + (n × 1000h)
7.3.5.6.3.2 Function
The ES provides information concerning the last recorded channel error. Channel errors
can be caused by:
• An illegal setting in the transfer control descriptor
• An error termination to a bus master read or write cycle
The ERR field signals the presence of an error for the channel. The eDMA engine signals
the occurrence of an error condition by setting the appropriate field in this register. The
outputs of this register are enabled by the contents of the CHn_CSR[EEI] field, then
logically summed across all channels to form an error interrupt request, which may be
routed to the interrupt controller.
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During the execution of the interrupt service routine associated with any DMA errors, it
is software's responsibility to clear the appropriate bit, negating the error-interrupt
request. The normal DMA channel completion indicators (setting the transfer control
descriptor DONE flag and the possible assertion of an interrupt request) are not affected
when eDMA detects an error. The contents of this ERR register field can also be polled
because a non-zero value indicates the presence of a channel error, regardless of the state
of the EEI mask.
The state of any given channel's error indicators is affected by writes to this register.
Writing a 1 to the ERR field clears the channel's error status, and writing a 0 has no
effect.
An unspecified error, where only the ERR field is set to 1, indicates that either a transfer
was cancelled with an error. The Management Page Error Status register has full view of
the error condition.
See Fault reporting and handling for more details.
7.3.5.6.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R ERR Reserved
W W1C 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved SAE SOE DAE DOE NCE SGE SBE DBE
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.6.3.4 Fields
Field Function
31 Error In Channel
0b - An error in this channel has not occurred
ERR
1b - An error in this channel has occurred
30-8 Reserved
—
7 Source Address Error
SAE TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
0b - No source address configuration error
1b - Last recorded error was a configuration error detected in the TCDn_SADDR field
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Field Function
6 Source Offset Error
SOE TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
0b - No source offset configuration error
1b - Last recorded error was a configuration error detected in the TCDn_SOFF field
5 Destination Address Error
DAE TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
0b - No destination address configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DADDR field
4 Destination Offset Error
DOE TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
0b - No destination offset configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DOFF field
3 NBYTES/CITER Configuration Error
NCE This error indicates that one of the following has occurred:
• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE]
• TCDn_CITER[CITER] is equal to zero
• TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
0b - No NBYTES/CITER configuration error
1b - Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
fields
2 Scatter/Gather Configuration Error
SGE When this field is 1, it indicates that TCDn_DLAST_SGA is not on a 32-byte boundary. This field is
checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
enabled.
0b - No scatter/gather configuration error
1b - Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field
1 Source Bus Error
0b - No source bus error
SBE
1b - Last recorded error was bus error on source read
0 Destination Bus Error
0b - No destination bus error
DBE
1b - Last recorded error was bus error on destination write
7.3.5.6.4 Channel Interrupt Status (CH0_INT - CH31_INT)
7.3.5.6.4.1 Offset
For n = 0 to 31:
Register Offset
CHn_INT 8h + (n × 1000h)
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7.3.5.6.4.2 Function
The INT field signals the presence of an interrupt request for the channel. Depending on
the appropriate bit setting in the transfe control descriptors, the eDMA engine generates
an interrupt on data transfer completion.
The outputs of this register are directly routed to the interrupt controller. During the
interrupt service routine associated with any given channel, it is the software's
responsibility to clear the appropriate bit, negating the interrupt request. On writes to
INT, a 1 clears the channel's interrupt request. A zero has no effect on the channel's
current interrupt status.
7.3.5.6.4.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 INT
W W1C
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.6.4.4 Fields
Field Function
31-1 Reserved
—
0 Interrupt Request
0b - Interrupt request for corresponding channel cleared
INT
1b - Interrupt request for corresponding channel active
7.3.5.6.5 Channel System Bus (CH0_SBR - CH31_SBR)
7.3.5.6.5.1 Offset
For n = 0 to 31:
Register Offset
CHn_SBR Ch + (n × 1000h)
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7.3.5.6.5.2 Function
The Channel System Bus register places identification and attribute information on the
system bus interface for the eDMA.
The ATTR register outputs the register values onto the system bus interface for further
decoding by the security system.
7.3.5.6.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Reserved
0 Reserved
R
ATTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PAL 0 MID
W
Reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
7.3.5.6.5.4 Fields
Field Function
31-23 Reserved
—
22-17 Attribute Output
ATTR DMA's system bus attribute output value.
16 Reserved
—
15 Privileged Access Level
PAL This field controls DMA's protection level on the system bus when the channel is active.
NOTE: When you enable master ID replication, the value captured in this register is the privilege level of
the core or other master writing the channel's transfer control descriptor, which is the lower byte
of TCDn_CSR.
0b - User protection level for DMA transfers
1b - Privileged protection level for DMA transfers
14-5 Reserved
—
4-0 Master ID
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Field Function
MID This field controls the DMA's master ID on the system bus when the channel is active.
NOTE: The ID captured in this register reflects the master ID of the core or other master writing the
channel's control attributes, which are in the lower byte of TCDn_CSR.
7.3.5.6.6 Channel Priority (CH0_PRI - CH31_PRI)
7.3.5.6.6.1 Offset
For n = 0 to 31:
Register Offset
CHn_PRI 10h + (n × 1000h)
7.3.5.6.6.2 Function
The contents of these registers define unique priorities associated with each channel
within the same channel group. Channel grouping is programmed via Channel Arbitration
Group (CH0_GRPRI - CH31_GRPRI).
The channel priorities within a group are evaluated by numeric value; for example, 0 is
the lowest priority, 1 is the next higher priority, then 2, 3, and so on. Software must
program the channel priorities with unique values; otherwise, channel numbers with the
same, non-zero value, will be selected based on channel number with the higher channel
number having higher priority.
If more than one channel in a group has an arbitration priority level value of zero, then
the arbitration mode field MP_CSR[ERCA] is used to determine the arbitration scheme
for all channels with APL=0 within a group.
When you enable round-robin channel arbitration (MP_CSR[ERCA] = 1), all channels
with APL=0 within a group will use a round-robin arbitration scheme, which rotates
among these channels requesting service without regard to priority. Round-robin provides
a fairness mechanism within an arbitration group.
When you enable fixed-priority channel arbitration (MP_CSR[ERCA] = 0), eDMA
selects channels with APL=0 based on channel number, with the higher channel number
having higher priority.
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7.3.5.6.6.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Reserved
ECP DPA
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
APL
W 0
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.3.5.6.6.4 Fields
Field Function
31 Enable Channel Preemption
0b - Channel cannot be suspended by a higher-priority channel's service request
ECP
1b - Channel can be temporarily suspended by a higher-priority channel's service request
30 Disable Preempt Ability
0b - Channel can suspend a lower-priority channel
DPA
1b - Channel cannot suspend any other channel, regardless of channel priority
29-3 Reserved
—
2-0 Arbitration Priority Level
APL Channel priority level for arbitration within the assigned arbitration group.
7.3.5.6.7 TCD Source Address (TCD0_SADDR - TCD31_SADDR)
7.3.5.6.7.1 Offset
For n = 0 to 31:
Register Offset
TCDn_SADDR 20h + (n × 1000h)
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7.3.5.6.7.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SADDR
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SADDR
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.7.3 Fields
Field Function
31-0 Source Address
SADDR Memory address pointing to the source data.
7.3.5.6.8 TCD Signed Source Address Offset (TCD0_SOFF - TCD31_SOFF)
7.3.5.6.8.1 Offset
For n = 0 to 31:
Register Offset
TCDn_SOFF 24h + (n × 1000h)
7.3.5.6.8.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SOFF
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.8.3 Fields
Field Function
15-0 Source Address Signed Offset
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Field Function
SOFF Sign-extended offset applied to the current source address to form the next-state value as each source
read is completed.
7.3.5.6.9 TCD Transfer Attributes (TCD0_ATTR - TCD31_ATTR)
7.3.5.6.9.1 Offset
For n = 0 to 31:
Register Offset
TCDn_ATTR 26h + (n × 1000h)
7.3.5.6.9.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SMOD SSIZE DMOD DSIZE
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.9.3 Fields
Field Function
15-11 Source Address Modulo
SMOD This field defines a specific address range, which is the value after the SADDR + SOFF calculation is
performed on the original register value. Setting this field makes it easy to implement a circular data
queue.
For data queues requiring power-of-2-sized bytes, the queue must start at a 0-modulo-size address and
the SMOD field must be set to the appropriate value for the queue, freezing the required number of upper
address bits.
The value programmed into this field specifies the number of lower address bits that are allowed to
change. For a circular queue application, you typically set TCDn_SOFF[SOFF] to the transfer size to
implement post-increment addressing, with the SMOD function constraining the addresses to a 0-modulo-
size range.
00000b - Source address modulo feature disabled
00001b - Source address modulo feature enabled for any non-zero value [1-31]
10-8 Source Data Transfer Size
000b - 8-bit
SSIZE
001b - 16-bit
010b - 32-bit
011b - 64-bit
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Field Function
100b - 16-byte
101b - 32-byte
110b - 64-byte
111b - Reserved
7-3 Destination Address Modulo
DMOD See the SMOD definition.
2-0 Destination Data Transfer Size
DSIZE See the SSIZE definition.
7.3.5.6.10 TCD Transfer Size Without Minor Loop Offsets
(TCD0_NBYTES_MLOFFNO - TCD31_NBYTES_MLOFFNO)
7.3.5.6.10.1 Offset
For n = 0 to 31:
Register Offset
TCDn_NBYTES_MLOFF 28h + (n × 1000h)
NO
7.3.5.6.10.2 Function
The TCDn_NBYTES field defines the number of bytes to transfer per service request.
Minor loop offsets are address offset values added to the final source address
(TCDn_SADDR), or destination address (TCDn_DADDR), upon minor loop completion.
Minor loop completion is when the channel has finished the service request and has
transferred NBYTES. When minor loop offsets are enabled, the minor loop offset value
(TCDn_NBYTES_MLOFFYES[MLOFF]) is added to the final source address
(TCDn_SADDR), to the final destination address (TCDn_DADDR), or to both, prior to
the addresses being written back to the TCD. If the major loop is complete, the minor
loop offset is ignored and the major loop address offsets (TCDn_SLAST_SDA and
TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR
values.
When minor loop mapping is enabled (SMLOE or DMLOE is 1),
TCDn_NBYTES_MLOFFNO /TCDn_NBYTES_MLOFFYES is redefined. A portion of
TCDn_NBYTES_MLOFFNO/TCDn_NBYTES_MLOFFYES is used to specify multiple
fields:
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• A source enable bit (SMLOE) to specify the minor loop offset must be applied to the
source address (TCDn_SADDR) upon minor loop completion
• A destination enable bit (DMLOE) to specify the minor loop offset must be applied
to the destination address (TCDn_DADDR) upon minor loop completion
• The sign extended minor loop offset value (MLOFF)
The same offset value (MLOFF) is used for both source and destination minor loop
offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
NBYTES field is reduced to 10 bits. If both minor loop offsets are disabled (SMLOE
cleared and DMLOE cleared), the NBYTES field is a 30-bit vector.
One of two register profiles (this register or TCDn_NBYTES_MLOFFYES), defines the
number of bytes to transfer per request. Which register to use depends on whether source
or destination minor loop mapping is enabled.
TCDn_NBYTES_MLOFFNO/TCDn_NBYTES_MLOFFYES is defined as follows:
• If SMLOE = 0 and DMLOE = 0, then see the TCDn_NBYTES_MLOFFNO register
description.
• If either SMLOE or DMLOE is 1, then see the TCDn_NBYTES_MLOFFYES
register description.
7.3.5.6.10.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
NBYTES
SMLOE
DMLOE
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NBYTES
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.10.4 Fields
Field Function
31 Source Minor Loop Offset Enable
SMLOE Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0b - Minor loop offset not applied to SADDR
1b - Minor loop offset applied to SADDR
30 Destination Minor Loop Offset Enable
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Field Function
DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0b - Minor loop offset not applied to DADDR
1b - Minor loop offset applied to DADDR
29-0 Number of Bytes To Transfer Per Service Request
NBYTES Number of bytes to be transferred for each service request of the channel.
When a channel activates, the module loads the appropriate TCD contents into the eDMA engine and
performs the appropriate reads and writes until the byte transfer count has been reached. This process is
normally an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth
control field, or via preemption.
After the byte count is exhausted, the SADDR and DADDR values are written back into the TCD memory,
and the major loop iteration count (CITER) is decremented by one and written back to the TCD memory.
If the major iteration count is complete, additional processing is performed.
7.3.5.6.11 TCD Transfer Size with Minor Loop Offsets
(TCD0_NBYTES_MLOFFYES - TCD31_NBYTES_MLOFFYES)
7.3.5.6.11.1 Offset
For n = 0 to 31:
Register Offset
TCDn_NBYTES_MLOFF 28h + (n × 1000h)
YES
7.3.5.6.11.2 Function
The TCDn_NBYTES field defines the number of bytes to transfer per service request.
Minor loop offset is an address offset value added to the final source address
(TCDn_SADDR) or destination address (TCDn_DADDR) upon minor loop completion.
Minor loop completion occurs when the channel has finished the service request and has
transferred NBYTES. Minor loop offsets are enabled by setting either the source enable
bit (SMLOE) or the destination enable bit (DMLOE).
The source enable bit (SMLOE) specifies the minor loop offset value (MLOFF) that is to
be applied to the source address (TCDn_SADDR) upon minor loop completion. The
destination enable bit (DMLOE) specifies the minor loop offset (MLOFF) that is to be
applied to the destination address (TCDn_DADDR) upon minor loop completion.
If the major loop is complete, the minor loop offsets are ignored and the major loop
address offsets (TCDn_SLAST_SDA and TCDn_DLAST_SGA) are used to compute the
next TCDn_SADDR and TCDn_DADDR values.
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When you enable the minor loop offset overlay (either SMLOE or DMLOE is 1), eDMA
redefines TCDn_NBYTES_MLOFFNO /TCDn_NBYTES_MLOFFYES. A portion of
TCDn_NBYTES_MLOFFNO/TCDn_NBYTES_MLOFFYES specifies the sign-
extended minor loop offset value (MLOFF). The same offset value (MLOFF) applies to
both source and destination minor loop offsets. When the minor loop offset is enabled,
you must align it to the transfer size of the source or destination it is associated with.
When either minor loop offset is enabled (SMLOE set or DMLOE set), the NBYTES
field is reduced to 10 bits. If both minor loop offsets are disabled (SMLOE cleared and
DMLOE cleared), the NBYTES field is a 30-bit vector.
One of two register profiles (this register or TCDn_NBYTES_MLOFFNO) defines the
number of bytes to transfer per request. Which register to use depends on whether source
or destination minor loop mapping is enabled.
TCDn_NBYTES_MLOFFYES is defined as follows:
• If either minor loop offset is enabled (SMLOE or DMLOE = 1), then see the
TCDn_NBYTES_MLOFFYES register description.
• If SMLOE and DMLOE are both 0, then see the TCDn_NBYTES_MLOFFNO
register description.
7.3.5.6.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
MLOFF
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MLOFF NBYTES
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.11.4 Fields
Field Function
31 Source Minor Loop Offset Enable
SMLOE Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0b - Minor loop offset not applied to SADDR
1b - Minor loop offset applied to SADDR
30 Destination Minor Loop Offset Enable
DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
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Field Function
0b - Minor loop offset not applied to DADDR
1b - Minor loop offset applied to DADDR
29-10 Minor Loop Offset
MLOFF If SMLOE or DMLOE is 1, this field represents a sign-extended offset applied to the source or destination
address to form the next-state value after the minor loop completes.
9-0 Number of Bytes To Transfer Per Service Request
NBYTES The number of bytes to be transferred in each service request of the channel.
As a channel activates, the module loads the appropriate TCD contents into the eDMA engine and
performs the appropriate reads and writes until the minor byte transfer count has been reached. This is
an indivisible operation and cannot be halted. It can, however, be stalled by using the bandwidth control
field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, and the major iteration count is decremented and restored to the TCD memory. If the major
iteration count is complete, additional processing is performed.
7.3.5.6.12 TCD Last Source Address Adjustment / Store DADDR Address
(TCD0_SLAST_SDA - TCD31_SLAST_SDA)
7.3.5.6.12.1 Offset
For n = 0 to 31:
Register Offset
TCDn_SLAST_SDA 2Ch + (n × 1000h)
7.3.5.6.12.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SLAST_SDA
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SLAST_SDA
W
Reset u u u u u u u u u u u u u u u u
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7.3.5.6.12.3 Fields
Field Function
31-0 Last Source Address Adjustment / Store DADDR Address
SLAST_SDA Source last address adjustment or the system memory address for destination address (DADDR)
storage.
If (TCDn_CSR[ESDA] = 0), then:
• Adjustment value is added to the source address at the completion of the major iteration count.
This value can be used to restore the source address to the initial value or adjust the address to
reference the next data structure.
• This field uses two's complement notation for the final source address adjustment.
Otherwise:
• This address points to the 32-bit-aligned memory location where the destination address (DADDR)
is to be stored in system memory. By saving the final destination address in system memory via the
ESDA feature, you are able to compute the size of a variable destination data buffer by simply
subtracting the beginning DADDR from the final, saved DADDR. This feature is used together with
the scatter/gather operation to prevent the loss of the final DADDR, which is overwritten during the
scatter/gather operation.
The "Store Destination Address" (SDA) value must be a 32-bit-aligned location because the eDMA
forces the lower two address bits of the SLAST_SDA field to zero when ESDA is enabled. The
module performs this write operation when the major loop is done; that is, when the major iteration
count (CITER) decrements to zero.
7.3.5.6.13 TCD Destination Address (TCD0_DADDR - TCD31_DADDR)
7.3.5.6.13.1 Offset
For n = 0 to 31:
Register Offset
TCDn_DADDR 30h + (n × 1000h)
7.3.5.6.13.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DADDR
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DADDR
W
Reset u u u u u u u u u u u u u u u u
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7.3.5.6.13.3 Fields
Field Function
31-0 Destination Address
DADDR Memory address pointing to the destination data.
7.3.5.6.14 TCD Signed Destination Address Offset (TCD0_DOFF -
TCD31_DOFF)
7.3.5.6.14.1 Offset
For n = 0 to 31:
Register Offset
TCDn_DOFF 34h + (n × 1000h)
7.3.5.6.14.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DOFF
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.14.3 Fields
Field Function
15-0 Destination Address Signed Offset
DOFF Sign-extended offset that is applied to the current destination address to form the next-state value as
each destination write is completed.
7.3.5.6.15 TCD Current Major Loop Count (Minor Loop Channel Linking
Disabled) (TCD0_CITER_ELINKNO - TCD31_CITER_ELINKNO)
7.3.5.6.15.1 Offset
For n = 0 to 31:
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Register Offset
TCDn_CITER_ELINKNO 36h + (n × 1000h)
7.3.5.6.15.2 Function
If TCDn_CITER[ELINK] is 0, the TCDn_CITER register is defined as follows.
7.3.5.6.15.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
CITER
ELINK
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.15.4 Fields
Field Function
15 Enable Link
ELINK As the channel completes the minor loop, this flag enables linking to another channel as defined by the
relevant LINKCH field. The link target channel initiates a channel service request via an internal
mechanism that sets the TCDn_CSR[START] bit of the specified channel to 1.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of MAJORELINK channel linking.
NOTE: This field must be equal to the BITER[ELINK] field; otherwise, a configuration error is reported.
0b - Channel-to-channel linking disabled
1b - Channel-to-channel linking enabled
14-0 Current Major Iteration Count
CITER This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the
channel. It is decremented each time the channel finishes a service request and is written back to TCD
memory. After the major iteration count is exhausted, the channel performs a number of operations — for
example, final source and destination address calculations — and optionally generates an interrupt to
signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER)
field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
7.3.5.6.16 TCD Current Major Loop Count (Minor Loop Channel Linking
Enabled) (TCD0_CITER_ELINKYES - TCD31_CITER_ELINKYES)
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7.3.5.6.16.1 Offset
For n = 0 to 31:
Register Offset
TCDn_CITER_ELINKYE 36h + (n × 1000h)
S
7.3.5.6.16.2 Function
If TCDn_CITER[ELINK] is 1, the TCDn_CITER register is defined as follows.
7.3.5.6.16.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Reserved
R
LINKCH
CITER
ELINK
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.16.4 Fields
Field Function
15 Enable Link
ELINK As the channel completes the minor loop, this flag enables linking to another channel as defined by the
relevant LINKCH field. When enabled, an internal mechanism sets the TCDn_CSR[START] field of the
specified channel (LINKCH) upon minor loop completion.
If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If
the major loop is exhausted, this link mechanism is suppressed in favor of MAJORELINK channel linking.
NOTE: This field must be equal to the BITER[ELINK] field; otherwise, a configuration error is reported.
0b - Channel-to-channel linking disabled
1b - Channel-to-channel linking enabled
14 Reserved
—
13-9 Minor Loop Link Channel Number
LINKCH If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted the eDMA
engine initiates a channel service request to the channel defined by this field by writing that channel’s
TCDn_CSR[START] field to 1.
8-0 Current Major Iteration Count
CITER
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Field Function
This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the
channel. It is decremented each time the channel finishes a service request and is written back to the
TCD memory. After the major iteration count is exhausted, the channel performs a number of operations
— for example, final source and destination address calculations — and optionally generates an interrupt
to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER)
field.
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that
contained in the BITER field.
NOTE: If the channel is configured to execute a single service request, the initial values of BITER and
CITER should be 0x0001.
7.3.5.6.17 TCD Last Destination Address Adjustment / Scatter Gather
Address (TCD0_DLAST_SGA - TCD31_DLAST_SGA)
7.3.5.6.17.1 Offset
For n = 0 to 31:
Register Offset
TCDn_DLAST_SGA 38h + (n × 1000h)
7.3.5.6.17.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
DLAST_SGA
W
Reset u u u u u u u u u u u u u u u u
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DLAST_SGA
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.17.3 Fields
Field Function
31-0 Last Destination Address Adjustment / Scatter Gather Address
DLAST_SGA Adjustment of the last destination address or the memory address for the next transfer control descriptor
to be loaded into this channel (scatter/gather).
If (TCDn_CSR[ESG] = 0) then:
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Field Function
• Adjustment value is added to the destination address at the completion of the major iteration count.
This value can apply to restore the destination address to the initial value or adjust the address to
reference the next data structure.
• This field uses two's complement notation for the final destination address adjustment.
Otherwise:
• This address points to the beginning of a 0-modulo 32-byte region containing the next transfer
control descriptor to be loaded into this channel. This channel reload is performed as the major
iteration count completes. The scatter/gather address must be 0-modulo 32-byte, or else a
configuration error is reported.
7.3.5.6.18 TCD Control and Status (TCD0_CSR - TCD31_CSR)
7.3.5.6.18.1 Offset
For n = 0 to 31:
Register Offset
TCDn_CSR 3Ch + (n × 1000h)
7.3.5.6.18.2 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MAJORLINKCH
MAJORELINK
INTMAJOR
INTHALF
START
DREQ
EEOP
ESDA
BWC
ESG
W
0
Reset u u u u u u u u u u u u u u u 0
7.3.5.6.18.3 Fields
Field Function
15-14 Bandwidth Control
BWC Throttles the amount of bus bandwidth consumed by the eDMA. Generally, as the eDMA processes the
minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field
forces eDMA to stall after the completion of each read/write access, to control the bus request bandwidth
seen by the system bus interconnect.
NOTE: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing
start-up latency.
Table continues on the next page...
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Field Function
00b - No eDMA engine stalls
01b - Reserved
10b - eDMA engine stalls for 4 cycles after each R/W
11b - eDMA engine stalls for 8 cycles after each R/W
13 Reserved
—
12-8 Major Loop Link Channel Number
MAJORLINKCH If (MAJORELINK = 0) then:
• No channel-to-channel linking, or chaining, is performed after the major loop counter is exhausted.
Otherwise:
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
the channel defined by this field by setting that channel’s TCDn_CSR[START] field to 1.
7 Enable Store Destination Address
ESDA As the channel completes the major loop by either the current iteration counter (CITER) decrementing to
0, or by receiving an enabled end-of-packet signal, this field enables writing the destination address
(DADDR) to the address stored in the SLAST_SDA field. The value written to system memory is the last
DADDR value prior to the DLAST_SGA offset being applied, or overwritten by an enabled scatter/gather
operation. When the SDA bit is 1, SLAST_SDA contains the write pointer instead of the final source
address offset. Because this is a pointer and not a final offset, a last source address offset of zero is
applied to SADDR instead of the SLAST_SGA value.
0b - Ability to store destination address to system memory disabled
1b - Ability to store destination address to system memory enabled
6 Enable End-Of-Packet Processing
EEOP When enabled by the EEOP field, an end-of-packet hardware input signal directs eDMA to discontinue
executing the active channel, and to treat the shutdown as the major-loop-completed event. If the EEOP
field is 1, the end-of-packet signal from supported peripherals is accepted. If the EEOP field is 0, the end-
of-packet input is ignored. With an end-of-packet retirement, the current TCD destination address (or
ESDA-saved destination address), minus the software-saved initial address (DADDR), reflects the total
amount of data transferred.
0b - End-of-packet operation disabled
1b - End-of-packet hardware input signal enabled
5 Enable Link When Major Loop Complete
MAJORELINK As the channel completes the major loop, this flag enables linking to another channel defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] field of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to 0 if written when
TCDn_CSR[DONE] is 1.
0b - Channel-to-channel linking disabled
1b - Channel-to-channel linking enabled
4 Enable Scatter/Gather Processing
ESG As the channel completes the major loop, this flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses TCDn_DLAST_SGA as a memory pointer to a 0-modulo 32-
bit address containing a 32-byte data structure, which is loaded as the transfer control descriptor into
local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to 0 if written when
TCDn_CSR[DONE] is 1.
0b - Current channel’s TCD is normal format
1b - Current channel’s TCD specifies scatter/gather format.
Table continues on the next page...
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Field Function
3 Disable Request
DREQ If this flag is 1, the eDMA hardware automatically clears the corresponding ERQ bit when the current
major iteration count reaches 0.
0b - No operation. Channel’s ERQ field not affected
1b - Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service
requests. Channel’s ERQ field cleared to 0 when major loop complete
2 Enable Interrupt If Major Counter Half-complete
INTHALF If this flag is 1, the channel generates an interrupt request by setting the appropriate field in the INT
register to 1 when the current major iteration count reaches the halfway point. Specifically, the
comparison performed by the eDMA engine is (CITER = (BITER/2)). This halfway point interrupt request
is provided to support double-buffered, also known as ping-pong, schemes, or other types of data
movement where the processor needs an early indication of the transfer’s progress.
NOTE: If BITER = 1, do not use INTHALF; use INTMAJOR instead.
0b - Halfway point interrupt disabled
1b - Halfway point interrupt enabled
1 Enable Interrupt If Major count complete
INTMAJOR If this flag is 1, the channel generates an interrupt request by setting the appropriate field in the INT
register to 1 when the current major iteration count (CITER) reaches 0.
0b - End-of-major loop interrupt disabled
1b - End-of-major loop interrupt enabled
0 Channel Start
START If this flag is 1, the channel is requesting service. The eDMA hardware automatically clears this flag to 0
after the channel begins execution.
0b - Channel not explicitly started
1b - Channel explicitly started via a software-initiated service request
7.3.5.6.19 TCD Beginning Major Loop Count (Minor Loop Channel Linking
Disabled) (TCD0_BITER_ELINKNO - TCD31_BITER_ELINKNO)
7.3.5.6.19.1 Offset
For n = 0 to 31:
Register Offset
TCDn_BITER_ELINKNO 3Eh + (n × 1000h)
7.3.5.6.19.2 Function
If the TCDn_BITER[ELINK] field is 0, the TCDn_BITER register is defined as follows.
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7.3.5.6.19.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITER
ELINK
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.19.4 Fields
Field Function
15 Enables Link
ELINK As the channel completes the minor loop, this flag enables linking to another channel as defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] field of the specified channel. If channel linking is disabled, the BITER
value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link
mechanism is suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, eDMA
reloads the contents of this field into the CITER field.
0b - Channel-to-channel linking disabled
1b - Channel-to-channel linking enabled
14-0 Starting Major Iteration Count
BITER As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be set equal to the value in the CITER field. As the major iteration count is exhausted, eDMA
reloads the contents of this field into the CITER field. If the channel is configured to execute a single
service request, the initial values of BITER and CITER must be 0x0001.
7.3.5.6.20 TCD Beginning Major Loop Count (Minor Loop Channel Linking
Enabled) (TCD0_BITER_ELINKYES - TCD31_BITER_ELINKYES)
7.3.5.6.20.1 Offset
For n = 0 to 31:
Register Offset
TCDn_BITER_ELINKYE 3Eh + (n × 1000h)
S
7.3.5.6.20.2 Function
If the TCDn_BITER[ELINK] field is set, the TCDn_BITER register is defined as
follows.
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7.3.5.6.20.3 Diagram
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Reserved
R
LINKCH
BITER
ELINK
W
Reset u u u u u u u u u u u u u u u u
7.3.5.6.20.4 Fields
Field Function
15 Enable Link
ELINK As the channel completes the minor loop, this flag enables linking to another channel as defined by
BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] field of the specified channel. If channel linking disables, the BITER
value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link
mechanism is suppressed in favor of the MAJORELINK channel linking.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, eDMA
reloads the contents of this field into the CITER field.
0b - Channel-to-channel linking disabled
1b - Channel-to-channel linking enabled
14 Reserved
—
13-9 Link Channel Number
LINKCH If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA
engine initiates a channel service request at the channel defined by this field by setting that channel’s
TCDn_CSR[START] field.
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field;
otherwise, a configuration error is reported. As the major iteration count is exhausted, eDMA
reloads the contents of this field into the CITER field.
8-0 Starting Major Iteration Count
BITER As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0)
field must be set equal to the value in the CITER field. As the major iteration count is exhausted, eDMA
reloads the contents of this field into the CITER field. If the channel is configured to execute a single
service request, the initial values of BITER and CITER must be 0x0001.
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Interrupt Request Steering (IRQ_STEER)
7.4 Interrupt Request Steering (IRQ_STEER)
7.4.1 Overview
The Interrupt Request Steering (IRQ_STEER) module redirects/steers the incoming
interrupts to output interrupts of a selected/designated channel as specified by a set of
configuration registers.
7.4.1.1 Block diagram
A high-level block diagram of the IRQ_STEER module is provided below.
Output
Interrupt
Channel 0
Wakeup
Output
Interrupt
Channel 1
Wakeup
Input
Interrupts
Output
Interrupt
Wakeup
Output
Interrupt
Channel n
Wakeup
Figure 7-30. IRQ_STEER block diagram
The following figure shows the high-level operation of one channel of the IRQ_STEER
module.
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MASK STATUS MINTDIS
Output
Interrupt
Group
Input
Interrupts OR by 64
OR Wakeup
SET MSTRSTAT
Figure 7-31. IRQ_STEER channel block diagram
7.4.1.2 Features
The IRQ_STEER module supports:
• 3 IRQ channels
• 160 interrupts per channel
7.4.2 Functional description
The IRQ_STEER module allows the user to steer 160 interrupts into one of 3 channels.
Each channel in the IRQ_STEER module supports up to 160 interrupts, and has its own
set of registers consisting of:
• 5 CHn_MASK registers
• 5 CHn_SET registers
• 5 CHn_STATUS registers
• One CHn_MINTDIS register
• One CHn_MSTRSTAT register
Since this module supports 3 channels, there are 3 sets of these registers. Each set of
registers will have its own base offset, which must be added to the relative offset shown
in the IRQ_STEER memory map.
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Interrupt Request Steering (IRQ_STEER)
7.4.2.1 Interrupt Mapping
The following table shows the correlation between an interrupt and its register and bit
offset for the CHn_MASK, CHn_SET, and CHn_STATUS registers of each channel.
For example:
• For a = 0, the row represents the mapping of an interrupt to the bit offset for the
CHn_MASK0, CHn_SET0, and CHn_STATUS0 registers.
• For a = 1, the row represents the mapping of an interrupt to the bit offset for the
CHn_MASK1, CHn_SET1, and CHn_STATUS1 registers.
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Table 7-66. Interrupt Mapping (incomplete)
a Bit offset
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128
1 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96
NXP Semiconductors
2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
3 63 62 61 60 59 58 57 56 55 54 53 52 52 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Interrupt Request Steering (IRQ_STEER)
7.4.2.2 Clocks
The following table describes the clock sources for the IRQ_STEER module. Please see
Clock Controller Module (CCM) for clock setting, configuration and gating information.
Table 7-67. IRQ_STEER Clocks
Clock name Description
ipg_clk Peripheral clock
7.4.3 External Signals
There are no external signals pinned out for this module.
7.4.4 Memory Map / Register Definition
This section includes the IRQ_STEER module memory map and detailed descriptions of
all registers.
7.4.4.1 IRQ_STEER register descriptions
7.4.4.1.1 IRQ_STEER memory map
irq_steer_audio_processor base address: 30A8_0000h
irq_steer_hdmi_tx base address: 32FC_2000h
Offset Register Width Access Reset value
(In bits)
4h - 14h Channel n Interrupt Mask Register (CHn_MASK0 - CHn_MASK4) 32 RW 0000_0000h
18h - 28h Channel n Interrupt Set Register (CHn_SET0 - CHn_SET4) 32 RW 0000_0000h
2Ch - 3Ch Channel n Interrupt Status Register (CHn_STATUS0 - 32 RO 0000_0000h
CHn_STATUS4)
40h Channel n Master Interrupt Disable Register (CHn_MINTDIS) 32 RW 0000_0000h
44h Channel n Master Status Register (CHn_MSTRSTAT) 32 RO 0000_0000h
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7.4.4.1.2 Channel n Interrupt Mask Register (CHn_MASK0 - CHn_MASK4)
7.4.4.1.2.1 Offset
Register Offset
CHn_MASK0 4h
CHn_MASK1 8h
CHn_MASK2 Ch
CHn_MASK3 10h
CHn_MASK4 14h
7.4.4.1.2.2 Function
The MASK registers are used to mask any of the 160 individual interrupts.
7.4.4.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MASKFLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MASKFLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.4.4.1.2.4 Fields
Field Function
31-0 Mask bits
MASKFLD See Table 7-66 for the correlation between an interrupt and its register and bit offset.
00000000000000000000000000000000b - Mask interrupt
00000000000000000000000000000001b - Do not mask interrupt
7.4.4.1.3 Channel n Interrupt Set Register (CHn_SET0 - CHn_SET4)
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7.4.4.1.3.1 Offset
Register Offset
CHn_SET0 18h
CHn_SET1 1Ch
CHn_SET2 20h
CHn_SET3 24h
CHn_SET4 28h
7.4.4.1.3.2 Function
This register is used to force an interrupt.
7.4.4.1.3.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
FORCEFLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FORCEFLD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.4.4.1.3.4 Fields
Field Function
31-0 Force interrupt.
FORCEFLD See Table 7-66 for the correlation between an interrupt and its register and bit offset.
00000000000000000000000000000000b - Normal operation
00000000000000000000000000000001b - Force interrupt
7.4.4.1.4 Channel n Interrupt Status Register (CHn_STATUS0 -
CHn_STATUS4)
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7.4.4.1.4.1 Offset
Register Offset
CHn_STATUS0 2Ch
CHn_STATUS1 30h
CHn_STATUS2 34h
CHn_STATUS3 38h
CHn_STATUS4 3Ch
7.4.4.1.4.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R STATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.4.4.1.4.3 Fields
Field Function
31-0 Status of an interrupt
STATUS See Table 7-66 for the correlation between an interrupt and its register and bit offset.
00000000000000000000000000000000b - Interrupt is not set.
00000000000000000000000000000001b - Interrupt is set.
7.4.4.1.5 Channel n Master Interrupt Disable Register (CHn_MINTDIS)
7.4.4.1.5.1 Offset
Register Offset
CHn_MINTDIS 40h
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7.4.4.1.5.2 Function
Table 7-68. Interrupt disable mapping
STATUS bit Interrupts disabled
2 191 - 128
1 127 - 64
0 63 - 0
7.4.4.1.5.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0
DISABLE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.4.4.1.5.4 Fields
Field Function
31-3 Reserved
—
2-0 Each bit of this field disables the corresponding interrupts in table above.
000b - Enable interrupts
DISABLE
001b - Disable interrupts
7.4.4.1.6 Channel n Master Status Register (CHn_MSTRSTAT)
7.4.4.1.6.1 Offset
Register Offset
CHn_MSTRSTAT 44h
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7.4.4.1.6.2 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STATUS
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7.4.4.1.6.3 Fields
Field Function
31-1 Reserved
—
0 Status of all interrupts
0b - No interrupts are asserted.
STATUS
1b - At least one interrupt is asserted.
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Chapter 8
Chip IO and Pinmux
8.1 External Signals and Pin Multiplexing
8.1.1 Overview
The chip contains a limited number of pins, most of which have multiple signal options.
These signal-to-pin and pin-to-signal options are selected by the input-output multiplexer
called IOMUX. The IOMUX is also used to configure other pin characteristics, such as
voltage level, drive strength, and hysteresis.
The muxing options table lists the external signals grouped by the module instance, the
muxing options for each signal, and the registers used to route the signal to the chosen
pad.
8.1.1.1 Muxing Options
Instance Port Pad Mode
CCM CCM_CLKO1 ECSPI2_MISO ALT4
GPIO1_IO14 ALT6
CCM_CLKO2 ECSPI2_SS0 ALT4
GPIO1_IO15 ALT6
CCM_ENET_PHY_REF_CLK GPIO1_IO00 ALT1
_ROOT
CCM_EXT_CLK1 GPIO1_IO00 ALT6
CCM_EXT_CLK2 GPIO1_IO01 ALT6
CCM_EXT_CLK3 GPIO1_IO06 ALT6
CCM_EXT_CLK4 GPIO1_IO07 ALT6
CCM_PMIC_READY GPIO1_IO05 ALT5
GPIO1_IO11 ALT5
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1285
External Signals and Pin Multiplexing
Instance Port Pad Mode
CCM_PMIC_STBY_REQ PMIC_STBY_REQ ALT0
REF_CLK_24M GPIO1_IO01 ALT5
REF_CLK_32K GPIO1_IO00 ALT5
CORESIGHT CORESIGHT_EVENTI SD2_WP ALT6
CORESIGHT_EVENTO NAND_WP_B ALT6
CORESIGHT_TRACE00 NAND_CE1_B ALT6
CORESIGHT_TRACE01 NAND_CE2_B ALT6
CORESIGHT_TRACE02 NAND_CE3_B ALT6
CORESIGHT_TRACE03 NAND_CLE ALT6
CORESIGHT_TRACE04 NAND_DATA00 ALT6
CORESIGHT_TRACE05 NAND_DATA01 ALT6
CORESIGHT_TRACE06 NAND_DATA02 ALT6
CORESIGHT_TRACE07 NAND_DATA03 ALT6
CORESIGHT_TRACE08 NAND_DATA04 ALT6
CORESIGHT_TRACE09 NAND_DATA05 ALT6
CORESIGHT_TRACE10 NAND_DATA06 ALT6
CORESIGHT_TRACE11 NAND_DATA07 ALT6
CORESIGHT_TRACE12 NAND_DQS ALT6
CORESIGHT_TRACE13 NAND_RE_B ALT6
CORESIGHT_TRACE14 NAND_READY_B ALT6
CORESIGHT_TRACE15 NAND_WE_B ALT6
CORESIGHT_TRACE_CLK NAND_ALE ALT6
CORESIGHT_TRACE_CTL NAND_CE0_B ALT6
DRAM DRAM_AC00 DRAM_AC00 No Muxing
DRAM_AC01 DRAM_AC01 No Muxing
DRAM_AC02 DRAM_AC02 No Muxing
DRAM_AC03 DRAM_AC03 No Muxing
DRAM_AC04 DRAM_AC04 No Muxing
DRAM_AC05 DRAM_AC05 No Muxing
DRAM_AC06 DRAM_AC06 No Muxing
DRAM_AC07 DRAM_AC07 No Muxing
DRAM_AC08 DRAM_AC08 No Muxing
DRAM_AC09 DRAM_AC09 No Muxing
DRAM_AC10 DRAM_AC10 No Muxing
DRAM_AC11 DRAM_AC11 No Muxing
DRAM_AC12 DRAM_AC12 No Muxing
DRAM_AC13 DRAM_AC13 No Muxing
DRAM_AC14 DRAM_AC14 No Muxing
DRAM_AC15 DRAM_AC15 No Muxing
DRAM_AC16 DRAM_AC16 No Muxing
DRAM_AC17 DRAM_AC17 No Muxing
Table continues on the next page...
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1286 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
DRAM_AC19 DRAM_AC19 No Muxing
DRAM_AC20 DRAM_AC20 No Muxing
DRAM_AC21 DRAM_AC21 No Muxing
DRAM_AC22 DRAM_AC22 No Muxing
DRAM_AC23 DRAM_AC23 No Muxing
DRAM_AC24 DRAM_AC24 No Muxing
DRAM_AC25 DRAM_AC25 No Muxing
DRAM_AC26 DRAM_AC26 No Muxing
DRAM_AC27 DRAM_AC27 No Muxing
DRAM_AC28 DRAM_AC28 No Muxing
DRAM_AC29 DRAM_AC29 No Muxing
DRAM_AC30 DRAM_AC30 No Muxing
DRAM_AC31 DRAM_AC31 No Muxing
DRAM_AC32 DRAM_AC32 No Muxing
DRAM_AC33 DRAM_AC33 No Muxing
DRAM_AC34 DRAM_AC34 No Muxing
DRAM_AC35 DRAM_AC35 No Muxing
DRAM_AC36 DRAM_AC36 No Muxing
DRAM_AC37 DRAM_AC37 No Muxing
DRAM_AC38 DRAM_AC38 No Muxing
DRAM_ALERT_N DRAM_ALERT_N No Muxing
DRAM_DM0 DRAM_DM0 No Muxing
DRAM_DM1 DRAM_DM1 No Muxing
DRAM_DM2 DRAM_DM2 No Muxing
DRAM_DM3 DRAM_DM3 No Muxing
DRAM_DQ00 DRAM_DQ00 No Muxing
DRAM_DQ01 DRAM_DQ01 No Muxing
DRAM_DQ02 DRAM_DQ02 No Muxing
DRAM_DQ03 DRAM_DQ03 No Muxing
DRAM_DQ04 DRAM_DQ04 No Muxing
DRAM_DQ05 DRAM_DQ05 No Muxing
DRAM_DQ06 DRAM_DQ06 No Muxing
DRAM_DQ07 DRAM_DQ07 No Muxing
DRAM_DQ08 DRAM_DQ08 No Muxing
DRAM_DQ09 DRAM_DQ09 No Muxing
DRAM_DQ10 DRAM_DQ10 No Muxing
DRAM_DQ11 DRAM_DQ11 No Muxing
DRAM_DQ12 DRAM_DQ12 No Muxing
DRAM_DQ13 DRAM_DQ13 No Muxing
DRAM_DQ14 DRAM_DQ14 No Muxing
DRAM_DQ15 DRAM_DQ15 No Muxing
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1287
External Signals and Pin Multiplexing
Instance Port Pad Mode
DRAM_DQ16 DRAM_DQ16 No Muxing
DRAM_DQ17 DRAM_DQ17 No Muxing
DRAM_DQ18 DRAM_DQ18 No Muxing
DRAM_DQ19 DRAM_DQ19 No Muxing
DRAM_DQ20 DRAM_DQ20 No Muxing
DRAM_DQ21 DRAM_DQ21 No Muxing
DRAM_DQ22 DRAM_DQ22 No Muxing
DRAM_DQ23 DRAM_DQ23 No Muxing
DRAM_DQ24 DRAM_DQ24 No Muxing
DRAM_DQ25 DRAM_DQ25 No Muxing
DRAM_DQ26 DRAM_DQ26 No Muxing
DRAM_DQ27 DRAM_DQ27 No Muxing
DRAM_DQ28 DRAM_DQ28 No Muxing
DRAM_DQ29 DRAM_DQ29 No Muxing
DRAM_DQ30 DRAM_DQ30 No Muxing
DRAM_DQ31 DRAM_DQ31 No Muxing
DRAM_DQS0_N DRAM_DQS0_N No Muxing
DRAM_DQS0_P DRAM_DQS0_P No Muxing
DRAM_DQS1_N DRAM_DQS1_N No Muxing
DRAM_DQS1_P DRAM_DQS1_P No Muxing
DRAM_DQS2_N DRAM_DQS2_N No Muxing
DRAM_DQS2_P DRAM_DQS2_P No Muxing
DRAM_DQS3_N DRAM_DQS3_N No Muxing
DRAM_DQS3_P DRAM_DQS3_P No Muxing
DRAM_RESET_N DRAM_RESET_N No Muxing
DRAM_VREF DRAM_VREF No Muxing
DRAM_ZN DRAM_ZN No Muxing
EARC EARC_AUX EARC_AUX No Muxing
EARC_P_UTIL EARC_P_UTIL No Muxing
EARC_N_HPD EARC_N_HPD No Muxing
ECSPI1 ECSPI1_MISO ECSPI1_MISO ALT0
I2C2_SCL ALT3
ECSPI1_MOSI ECSPI1_MOSI ALT0
I2C1_SDA ALT3
ECSPI1_SCLK ECSPI1_SCLK ALT0
I2C1_SCL ALT3
ECSPI1_SS0 ECSPI1_SS0 ALT0
I2C2_SDA ALT3
ECSPI2 ECSPI2_MISO ECSPI2_MISO ALT0
SD2_DATA3 ALT2
I2C4_SCL ALT3
Table continues on the next page...
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1288 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
ECSPI2_MOSI ECSPI2_MOSI ALT0
SD2_CMD ALT2
I2C3_SDA ALT3
ECSPI2_SCLK ECSPI2_SCLK ALT0
SD2_CLK ALT2
I2C3_SCL ALT3
ECSPI2_SS0 ECSPI2_SS0 ALT0
SD2_DATA2 ALT2
I2C4_SDA ALT3
ECSPI3 ECSPI3_MISO UART2_RXD ALT1
ECSPI3_MOSI UART1_TXD ALT1
ECSPI3_SCLK UART1_RXD ALT1
ECSPI3_SS0 UART2_TXD ALT1
ENET_QOS ENET_QOS_1588_EVENT0_ GPIO1_IO08 ALT4
AUX_IN
ENET_QOS_1588_EVENT0_ GPIO1_IO08 ALT1
IN
ENET_QOS_1588_EVENT0_ GPIO1_IO09 ALT1
OUT
ENET_QOS_1588_EVENT1_ I2C2_SCL ALT4
AUX_IN
ENET_QOS_1588_EVENT1_ I2C2_SCL ALT1
IN
ENET_QOS_1588_EVENT1_ I2C2_SDA ALT1
OUT
ENET_QOS_1588_EVENT2_ SAI2_TXD0 ALT4
AUX_IN
ENET_QOS_1588_EVENT2_ SAI2_TXD0 ALT2
IN
ENET_QOS_1588_EVENT2_ SAI2_RXD0 ALT2
OUT
ENET_QOS_1588_EVENT3_ SAI2_MCLK ALT4
AUX_IN
ENET_QOS_1588_EVENT3_ SAI2_MCLK ALT2
IN
ENET_QOS_1588_EVENT3_ SAI2_TXFS ALT2
OUT
ENET_QOS_INPUT=ENET_ ENET_TD2 ALT1
QOS_TX_CLK,
OUTPUT=CCM_ENET_QOS
_REF_CLK_ROOT
ENET_QOS_MDC ENET_MDC ALT0
GPIO1_IO06 ALT1
I2C1_SCL ALT1
ENET_QOS_MDIO ENET_MDIO ALT0
Table continues on the next page...
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NXP Semiconductors 1289
External Signals and Pin Multiplexing
Instance Port Pad Mode
GPIO1_IO07 ALT1
I2C1_SDA ALT1
ENET_QOS_RGMII_RD0 ENET_RD0 ALT0
ENET_QOS_RGMII_RD1 ENET_RD1 ALT0
ENET_QOS_RGMII_RD2 ENET_RD2 ALT0
ENET_QOS_RGMII_RD3 ENET_RD3 ALT0
ENET_QOS_RGMII_RX_CTL ENET_RX_CTL ALT0
ENET_QOS_RGMII_RXC ENET_RXC ALT0
ENET_QOS_RGMII_TD0 ENET_TD0 ALT0
ENET_QOS_RGMII_TD1 ENET_TD1 ALT0
ENET_QOS_RGMII_TD2 ENET_TD2 ALT0
ENET_QOS_RGMII_TD3 ENET_TD3 ALT0
ENET_QOS_RGMII_TX_CTL ENET_TX_CTL ALT0
ENET_QOS_RGMII_TXC ENET_TXC ALT0
ENET_QOS_RX_ER ENET_RXC ALT1
ENET_QOS_TX_ER ENET_TXC ALT1
ENET1 ENET1_1588_EVENT0_IN SAI1_RXFS ALT4
ENET1_1588_EVENT0_OUT SAI1_RXC ALT4
ENET1_1588_EVENT1_IN SAI1_RXD0 ALT4
ENET1_1588_EVENT1_OUT SAI1_RXD1 ALT4
ENET1_INPUT=ENET1_TX_ SD1_RESET_B ALT1
CLK,
OUTPUT=CCM_ENET_REF_
CLK_ROOT
ENET1_INPUT=ENET1_TX_ SAI1_MCLK ALT4
CLK,
OUTPUT=CCM_ENET_REF_
CLK_ROOT
ENET1_MDC SD1_CLK ALT1
SAI1_RXD2 ALT4
ENET1_MDIO SD1_CMD ALT1
SAI1_RXD3 ALT4
ENET1_RGMII_RD0 SD1_DATA2 ALT1
SAI1_RXD4 ALT4
ENET1_RGMII_RD1 SD1_DATA3 ALT1
SAI1_RXD5 ALT4
ENET1_RGMII_RD2 SAI1_RXD6 ALT4
ENET1_RGMII_RD3 SAI1_RXD7 ALT4
ENET1_RGMII_RX_CTL SD1_DATA6 ALT1
SAI1_TXFS ALT4
ENET1_RGMII_RXC SAI1_TXC ALT4
ENET1_RGMII_TD0 SD1_DATA1 ALT1
Table continues on the next page...
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1290 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
SAI1_TXD0 ALT4
ENET1_RGMII_TD1 SD1_DATA0 ALT1
SAI1_TXD1 ALT4
ENET1_RGMII_TD2 SAI1_TXD2 ALT4
ENET1_RGMII_TD3 SAI1_TXD3 ALT4
ENET1_RGMII_TX_CTL SD1_DATA4 ALT1
SAI1_TXD4 ALT4
ENET1_RGMII_TXC SAI1_TXD5 ALT4
ENET1_RX_ER SD1_DATA7 ALT1
SAI1_TXD6 ALT4
ENET1_TX_ER SD1_DATA5 ALT1
SAI1_TXD7 ALT4
FLEXCAN1 FLEXCAN1_RX SAI2_TXC ALT3
SPDIF_RX ALT4
HDMI_DDC_SDA ALT4
SAI5_RXD2 ALT6
FLEXCAN1_TX SAI2_RXC ALT3
SPDIF_TX ALT4
HDMI_DDC_SCL ALT4
SAI5_RXD1 ALT6
FLEXCAN2 FLEXCAN2_RX SAI2_MCLK ALT3
UART3_TXD ALT4
HDMI_HPD ALT4
SAI5_MCLK ALT6
FLEXCAN2_TX SAI2_TXD0 ALT3
UART3_RXD ALT4
HDMI_CEC ALT4
SAI5_RXD3 ALT6
GPIO1 GPIO1_IO00 GPIO1_IO00 ALT0
GPIO1_IO01 GPIO1_IO01 ALT0
GPIO1_IO02 GPIO1_IO02 ALT0
GPIO1_IO03 GPIO1_IO03 ALT0
GPIO1_IO04 GPIO1_IO04 ALT0
GPIO1_IO05 GPIO1_IO05 ALT0
GPIO1_IO06 GPIO1_IO06 ALT0
GPIO1_IO07 GPIO1_IO07 ALT0
GPIO1_IO08 GPIO1_IO08 ALT0
GPIO1_IO09 GPIO1_IO09 ALT0
GPIO1_IO10 GPIO1_IO10 ALT0
GPIO1_IO11 GPIO1_IO11 ALT0
GPIO1_IO12 GPIO1_IO12 ALT0
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1291
External Signals and Pin Multiplexing
Instance Port Pad Mode
GPIO1_IO13 GPIO1_IO13 ALT0
GPIO1_IO14 GPIO1_IO14 ALT0
GPIO1_IO15 GPIO1_IO15 ALT0
GPIO1_IO16 ENET_MDC ALT5
GPIO1_IO17 ENET_MDIO ALT5
GPIO1_IO18 ENET_TD3 ALT5
GPIO1_IO19 ENET_TD2 ALT5
GPIO1_IO20 ENET_TD1 ALT5
GPIO1_IO21 ENET_TD0 ALT5
GPIO1_IO22 ENET_TX_CTL ALT5
GPIO1_IO23 ENET_TXC ALT5
GPIO1_IO24 ENET_RX_CTL ALT5
GPIO1_IO25 ENET_RXC ALT5
GPIO1_IO26 ENET_RD0 ALT5
GPIO1_IO27 ENET_RD1 ALT5
GPIO1_IO28 ENET_RD2 ALT5
GPIO1_IO29 ENET_RD3 ALT5
GPIO2 GPIO2_IO00 SD1_CLK ALT5
GPIO2_IO01 SD1_CMD ALT5
GPIO2_IO02 SD1_DATA0 ALT5
GPIO2_IO03 SD1_DATA1 ALT5
GPIO2_IO04 SD1_DATA2 ALT5
GPIO2_IO05 SD1_DATA3 ALT5
GPIO2_IO06 SD1_DATA4 ALT5
GPIO2_IO07 SD1_DATA5 ALT5
GPIO2_IO08 SD1_DATA6 ALT5
GPIO2_IO09 SD1_DATA7 ALT5
GPIO2_IO10 SD1_RESET_B ALT5
GPIO2_IO11 SD1_STROBE ALT5
GPIO2_IO12 SD2_CD_B ALT5
GPIO2_IO13 SD2_CLK ALT5
GPIO2_IO14 SD2_CMD ALT5
GPIO2_IO15 SD2_DATA0 ALT5
GPIO2_IO16 SD2_DATA1 ALT5
GPIO2_IO17 SD2_DATA2 ALT5
GPIO2_IO18 SD2_DATA3 ALT5
GPIO2_IO19 SD2_RESET_B ALT5
GPIO2_IO20 SD2_WP ALT5
GPIO3 GPIO3_IO00 NAND_ALE ALT5
GPIO3_IO01 NAND_CE0_B ALT5
GPIO3_IO02 NAND_CE1_B ALT5
Table continues on the next page...
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1292 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
GPIO3_IO03 NAND_CE2_B ALT5
GPIO3_IO04 NAND_CE3_B ALT5
GPIO3_IO05 NAND_CLE ALT5
GPIO3_IO06 NAND_DATA00 ALT5
GPIO3_IO07 NAND_DATA01 ALT5
GPIO3_IO08 NAND_DATA02 ALT5
GPIO3_IO09 NAND_DATA03 ALT5
GPIO3_IO10 NAND_DATA04 ALT5
GPIO3_IO11 NAND_DATA05 ALT5
GPIO3_IO12 NAND_DATA06 ALT5
GPIO3_IO13 NAND_DATA07 ALT5
GPIO3_IO14 NAND_DQS ALT5
GPIO3_IO15 NAND_RE_B ALT5
GPIO3_IO16 NAND_READY_B ALT5
GPIO3_IO17 NAND_WE_B ALT5
GPIO3_IO18 NAND_WP_B ALT5
GPIO3_IO19 SAI5_RXFS ALT5
GPIO3_IO20 SAI5_RXC ALT5
GPIO3_IO21 SAI5_RXD0 ALT5
GPIO3_IO22 SAI5_RXD1 ALT5
GPIO3_IO23 SAI5_RXD2 ALT5
GPIO3_IO24 SAI5_RXD3 ALT5
GPIO3_IO25 SAI5_MCLK ALT5
GPIO3_IO26 HDMI_DDC_SCL ALT5
GPIO3_IO27 HDMI_DDC_SDA ALT5
GPIO3_IO28 HDMI_CEC ALT5
GPIO3_IO29 HDMI_HPD ALT5
GPIO4 GPIO4_IO00 SAI1_RXFS ALT5
GPIO4_IO01 SAI1_RXC ALT5
GPIO4_IO02 SAI1_RXD0 ALT5
GPIO4_IO03 SAI1_RXD1 ALT5
GPIO4_IO04 SAI1_RXD2 ALT5
GPIO4_IO05 SAI1_RXD3 ALT5
GPIO4_IO06 SAI1_RXD4 ALT5
GPIO4_IO07 SAI1_RXD5 ALT5
GPIO4_IO08 SAI1_RXD6 ALT5
GPIO4_IO09 SAI1_RXD7 ALT5
GPIO4_IO10 SAI1_TXFS ALT5
GPIO4_IO11 SAI1_TXC ALT5
GPIO4_IO12 SAI1_TXD0 ALT5
GPIO4_IO13 SAI1_TXD1 ALT5
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1293
External Signals and Pin Multiplexing
Instance Port Pad Mode
GPIO4_IO14 SAI1_TXD2 ALT5
GPIO4_IO15 SAI1_TXD3 ALT5
GPIO4_IO16 SAI1_TXD4 ALT5
GPIO4_IO17 SAI1_TXD5 ALT5
GPIO4_IO18 SAI1_TXD6 ALT5
GPIO4_IO19 SAI1_TXD7 ALT5
GPIO4_IO20 SAI1_MCLK ALT5
GPIO4_IO21 SAI2_RXFS ALT5
GPIO4_IO22 SAI2_RXC ALT5
GPIO4_IO23 SAI2_RXD0 ALT5
GPIO4_IO24 SAI2_TXFS ALT5
GPIO4_IO25 SAI2_TXC ALT5
GPIO4_IO26 SAI2_TXD0 ALT5
GPIO4_IO27 SAI2_MCLK ALT5
GPIO4_IO28 SAI3_RXFS ALT5
GPIO4_IO29 SAI3_RXC ALT5
GPIO4_IO30 SAI3_RXD ALT5
GPIO4_IO31 SAI3_TXFS ALT5
GPIO5 GPIO5_IO00 SAI3_TXC ALT5
GPIO5_IO01 SAI3_TXD ALT5
GPIO5_IO02 SAI3_MCLK ALT5
GPIO5_IO03 SPDIF_TX ALT5
GPIO5_IO04 SPDIF_RX ALT5
GPIO5_IO05 SPDIF_EXT_CLK ALT5
GPIO5_IO06 ECSPI1_SCLK ALT5
GPIO5_IO07 ECSPI1_MOSI ALT5
GPIO5_IO08 ECSPI1_MISO ALT5
GPIO5_IO09 ECSPI1_SS0 ALT5
GPIO5_IO10 ECSPI2_SCLK ALT5
GPIO5_IO11 ECSPI2_MOSI ALT5
GPIO5_IO12 ECSPI2_MISO ALT5
GPIO5_IO13 ECSPI2_SS0 ALT5
GPIO5_IO14 I2C1_SCL ALT5
GPIO5_IO15 I2C1_SDA ALT5
GPIO5_IO16 I2C2_SCL ALT5
GPIO5_IO17 I2C2_SDA ALT5
GPIO5_IO18 I2C3_SCL ALT5
GPIO5_IO19 I2C3_SDA ALT5
GPIO5_IO20 I2C4_SCL ALT5
GPIO5_IO21 I2C4_SDA ALT5
GPIO5_IO22 UART1_RXD ALT5
Table continues on the next page...
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1294 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
GPIO5_IO23 UART1_TXD ALT5
GPIO5_IO24 UART2_RXD ALT5
GPIO5_IO25 UART2_TXD ALT5
GPIO5_IO26 UART3_RXD ALT5
GPIO5_IO27 UART3_TXD ALT5
GPIO5_IO28 UART4_RXD ALT5
GPIO5_IO29 UART4_TXD ALT5
GPT1 GPT1_CAPTURE1 SAI3_TXC ALT3
UART4_TXD ALT3
GPT1_CAPTURE2 SAI3_TXD ALT3
UART3_RXD ALT3
GPT1_CLK SAI3_RXC ALT3
UART3_TXD ALT3
GPT1_COMPARE1 SPDIF_TX ALT3
UART4_RXD ALT3
GPT1_COMPARE2 SPDIF_RX ALT3
UART2_TXD ALT3
GPT1_COMPARE3 SPDIF_EXT_CLK ALT3
UART2_RXD ALT3
GPT2 GPT2_CLK I2C3_SCL ALT2
GPT3 GPT3_CLK I2C3_SDA ALT2
HDMI HDMI_CEC HDMI_CEC ALT0
HDMI_HPD HDMI_HPD ALT0
HDMI_HPD_O HDMI_HPD ALT1
HDMI_SCL HDMI_DDC_SCL ALT0
HDMI_SDA HDMI_DDC_SDA ALT0
HDMI_TX0N HDMI_TX0_N No Muxing
HDMI_TX0P HDMI_TX0_P No Muxing
HDMI_TX1N HDMI_TX1_N No Muxing
HDMI_TX1P HDMI_TX1_P No Muxing
HDMI_TX2N HDMI_TX2_N No Muxing
HDMI_TX2P HDMI_TX2_P No Muxing
HDMI_TXCN HDMI_TXC_N No Muxing
HDMI_TXCP HDMI_TXC_P No Muxing
HDMI_REXT HDMI_REXT No Muxing
I2C1 I2C1_SCL I2C1_SCL ALT0
ECSPI1_SCLK ALT2
SD1_DATA4 ALT3
I2C1_SDA I2C1_SDA ALT0
ECSPI1_MOSI ALT2
SD1_DATA5 ALT3
Table continues on the next page...
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External Signals and Pin Multiplexing
Instance Port Pad Mode
I2C2 I2C2_SCL I2C2_SCL ALT0
ECSPI1_MISO ALT2
SD1_DATA6 ALT3
I2C2_SDA I2C2_SDA ALT0
ECSPI1_SS0 ALT2
SD1_DATA7 ALT3
I2C3 I2C3_SCL I2C3_SCL ALT0
ECSPI2_SCLK ALT2
SD1_RESET_B ALT3
NAND_DQS ALT4
NAND_READY_B ALT4
I2C3_SDA I2C3_SDA ALT0
ECSPI2_MOSI ALT2
SD1_STROBE ALT3
NAND_CE3_B ALT4
NAND_WE_B ALT4
I2C4 I2C4_SCL I2C4_SCL ALT0
SD2_DATA1 ALT2
ECSPI2_MISO ALT2
SD1_DATA2 ALT3
NAND_CE1_B ALT4
NAND_WP_B ALT4
I2C4_SDA I2C4_SDA ALT0
SD2_DATA0 ALT2
ECSPI2_SS0 ALT2
SD1_DATA3 ALT3
NAND_CE2_B ALT4
NAND_DATA02 ALT4
I2C5 I2C5_SCL SPDIF_TX ALT2
SD1_CLK ALT3
SAI5_RXD0 ALT3
HDMI_DDC_SCL ALT3
I2C5_SDA SPDIF_RX ALT2
SD1_CMD ALT3
SAI5_MCLK ALT3
HDMI_DDC_SDA ALT3
I2C6 I2C6_SCL SD1_DATA0 ALT3
SAI5_RXFS ALT3
HDMI_CEC ALT3
UART4_RXD ALT4
I2C6_SDA SD1_DATA1 ALT3
Table continues on the next page...
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1296 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
SAI5_RXC ALT3
HDMI_HPD ALT3
UART4_TXD ALT4
ISP ISP_FL_TRIG_0 GPIO1_IO00 ALT3
NAND_ALE ALT3
ISP_FL_TRIG_1 GPIO1_IO05 ALT3
NAND_DATA03 ALT4
ISP_FLASH_TRIG_0 GPIO1_IO02 ALT3
NAND_DATA00 ALT3
ISP_FLASH_TRIG_1 GPIO1_IO07 ALT3
NAND_DATA05 ALT4
ISP_PRELIGHT_TRIG_0 GPIO1_IO03 ALT3
NAND_DATA01 ALT3
ISP_PRELIGHT_TRIG_1 GPIO1_IO08 ALT3
NAND_DATA06 ALT4
ISP_SHUTTER_OPEN_0 GPIO1_IO04 ALT3
NAND_DQS ALT3
ISP_SHUTTER_OPEN_1 GPIO1_IO09 ALT3
NAND_DATA07 ALT4
ISP_SHUTTER_TRIG_0 GPIO1_IO01 ALT3
NAND_CE0_B ALT3
ISP_SHUTTER_TRIG_1 GPIO1_IO06 ALT3
NAND_DATA04 ALT4
JTAG JTAG_MODE JTAG_MOD ALT0
JTAG_TCK JTAG_TCK ALT0
JTAG_TDI JTAG_TDI ALT0
JTAG_TDO JTAG_TDO ALT0
JTAG_TMS JTAG_TMS ALT0
LVDS0 LVDS0_CLKN LVDS0_CLK_N No Muxing
LVDS0_CLKP LVDS0_CLK_P No Muxing
LVDS0_D0N LVDS0_D0_N No Muxing
LVDS0_D0P LVDS0_D0_P No Muxing
LVDS0_D1N LVDS0_D1_N No Muxing
LVDS0_D1P LVDS0_D1_P No Muxing
LVDS0_D2N LVDS0_D2_N No Muxing
LVDS0_D2P LVDS0_D2_P No Muxing
LVDS0_D3N LVDS0_D3_N No Muxing
LVDS0_D3P LVDS0_D3_P No Muxing
LVDS1_CLKN LVDS1_CLK_N No Muxing
LVDS1_CLKP LVDS1_CLK_P No Muxing
LVDS1_D0N LVDS1_D0_N No Muxing
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i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
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External Signals and Pin Multiplexing
Instance Port Pad Mode
LVDS1_D0P LVDS1_D0_P No Muxing
LVDS1_D1N LVDS1_D1_N No Muxing
LVDS1_D1P LVDS1_D1_P No Muxing
LVDS1_D2N LVDS1_D2_N No Muxing
LVDS1_D2P LVDS1_D2_P No Muxing
LVDS1_D3N LVDS1_D3_N No Muxing
LVDS1_D3P LVDS1_D3_P No Muxing
M7 M7_NMI GPIO1_IO05 ALT1
MIPI CSI1 MIPI_CSI1_CLK_N MIPI_CSI1_CLK_N No Muxing
MIPI_CSI1_CLK_P MIPI_CSI1_CLK_P No Muxing
MIPI_CSI1_D0_N MIPI_CSI1_D0_N No Muxing
MIPI_CSI1_D0_P MIPI_CSI1_D0_P No Muxing
MIPI_CSI1_D1_N MIPI_CSI1_D1_N No Muxing
MIPI_CSI1_D1_P MIPI_CSI1_D1_P No Muxing
MIPI_CSI1_D2_N MIPI_CSI1_D2_N No Muxing
MIPI_CSI1_D2_P MIPI_CSI1_D2_P No Muxing
MIPI_CSI1_D3_N MIPI_CSI1_D3_N No Muxing
MIPI_CSI1_D3_P MIPI_CSI1_D3_P No Muxing
MIPI1_VREG MIPI_VREG1_CAP No Muxing
MIPI CSI2 MIPI_CSI2_CLK_N MIPI_CSI2_CLK_N No Muxing
MIPI_CSI2_CLK_P MIPI_CSI2_CLK_P No Muxing
MIPI_CSI2_D0_N MIPI_CSI2_D0_N No Muxing
MIPI_CSI2_D0_P MIPI_CSI2_D0_P No Muxing
MIPI_CSI2_D1_N MIPI_CSI2_D1_N No Muxing
MIPI_CSI2_D1_P MIPI_CSI2_D1_P No Muxing
MIPI_CSI2_D2_N MIPI_CSI2_D2_N No Muxing
MIPI_CSI2_D2_P MIPI_CSI2_D2_P No Muxing
MIPI_CSI2_D3_N MIPI_CSI2_D3_N No Muxing
MIPI_CSI2_D3_P MIPI_CSI2_D3_P No Muxing
MIPI2_VREG MIPI_VREG2_CAP No Muxing
MIPI DSI1 MIPI_DSI1_CLK_N MIPI_DSI1_CLK_N No Muxing
MIPI_DSI1_CLK_P MIPI_DSI1_CLK_P No Muxing
MIPI_DSI1_D0_N MIPI_DSI1_D0_N No Muxing
MIPI_DSI1_D0_P MIPI_DSI1_D0_P No Muxing
MIPI_DSI1_D1_N MIPI_DSI1_D1_N No Muxing
MIPI_DSI1_D1_P MIPI_DSI1_D1_P No Muxing
MIPI_DSI1_D2_N MIPI_DSI1_D2_N No Muxing
MIPI_DSI1_D2_P MIPI_DSI1_D2_P No Muxing
MIPI_DSI1_D3_N MIPI_DSI1_D3_N No Muxing
MIPI_DSI1_D3_P MIPI_DSI1_D3_P No Muxing
NAND NAND_ALE NAND_ALE ALT0
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Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
NAND_CE0_B NAND_CE0_B ALT0
NAND_CE1_B NAND_CE1_B ALT0
NAND_CE2_B NAND_CE2_B ALT0
NAND_CE3_B NAND_CE3_B ALT0
NAND_CLE NAND_CLE ALT0
NAND_DATA00 NAND_DATA00 ALT0
NAND_DATA01 NAND_DATA01 ALT0
NAND_DATA02 NAND_DATA02 ALT0
NAND_DATA03 NAND_DATA03 ALT0
NAND_DATA04 NAND_DATA04 ALT0
NAND_DATA05 NAND_DATA05 ALT0
NAND_DATA06 NAND_DATA06 ALT0
NAND_DATA07 NAND_DATA07 ALT0
NAND_DQS NAND_DQS ALT0
NAND_RE_B NAND_RE_B ALT0
NAND_READY_B NAND_READY_B ALT0
NAND_WE_B NAND_WE_B ALT0
NAND_WP_B NAND_WP_B ALT0
PCIE1 PCIE1_CLKREQ_B I2C4_SCL ALT2
UART4_RXD ALT2
PCIE_REF_PAD_CLK_N PCIE_REF_PAD_CLK_N No Muxing
PCIE_REF_PAD_CLK_P PCIE_REF_PAD_CLK_P No Muxing
PCIE_RESREF PCIE_RESREF No Muxing
PCIE_RXN_N PCIE_RXN_N No Muxing
PCIE_RXN_P PCIE_RXN_P No Muxing
PCIE_TXN_N PCIE_TXN_N No Muxing
PCIE_TXN_P PCIE_TXN_P No Muxing
PDM PDM_BIT_STREAM0 ENET_TD1 ALT3
ENET_RD1 ALT3
SAI1_RXD0 ALT3
SD2_DATA0 ALT4
SAI5_RXD0 ALT4
SAI3_RXFS ALT6
PDM_BIT_STREAM1 ENET_TD2 ALT3
ENET_RD0 ALT3
SAI1_RXD1 ALT3
SD2_DATA1 ALT4
SAI5_RXD1 ALT4
SAI2_RXC ALT6
SAI2_TXC ALT6
SAI3_RXD ALT6
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External Signals and Pin Multiplexing
Instance Port Pad Mode
PDM_BIT_STREAM2 ENET_TD3 ALT3
ENET_RXC ALT3
SAI1_RXD2 ALT3
SD2_DATA2 ALT4
SAI5_RXD2 ALT4
SAI2_RXFS ALT6
SAI2_TXFS ALT6
SAI3_TXC ALT6
PDM_BIT_STREAM3 ENET_MDIO ALT3
ENET_RX_CTL ALT3
SAI1_RXD3 ALT3
SD2_DATA3 ALT4
SAI5_RXD3 ALT4
SAI2_RXD0 ALT6
SAI3_TXFS ALT6
PDM_CLK ENET_TD0 ALT3
ENET_RD2 ALT3
SAI1_RXC ALT3
SAI1_TXD7 ALT3
SD2_CMD ALT4
SAI5_RXC ALT4
SAI3_RXC ALT6
PWM1 PWM1_OUT GPIO1_IO01 ALT1
SPDIF_EXT_CLK ALT1
I2C4_SDA ALT1
GPIO1_IO08 ALT2
SAI5_MCLK ALT2
PWM2 PWM2_OUT SPDIF_RX ALT1
I2C4_SCL ALT1
GPIO1_IO09 ALT2
GPIO1_IO11 ALT2
SAI5_RXD0 ALT2
GPIO1_IO13 ALT5
PWM3 PWM3_OUT SPDIF_TX ALT1
I2C3_SDA ALT1
GPIO1_IO10 ALT2
SAI5_RXC ALT2
GPIO1_IO14 ALT5
PWM4 PWM4_OUT SAI3_MCLK ALT1
I2C3_SCL ALT1
SAI5_RXFS ALT2
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Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
GPIO1_IO15 ALT5
QSPI QSPI_A_DATA0 NAND_DATA00 ALT1
QSPI_A_DATA1 NAND_DATA01 ALT1
QSPI_A_DATA2 NAND_DATA02 ALT1
QSPI_A_DATA3 NAND_DATA03 ALT1
QSPI_A_DATA4 NAND_DATA04 ALT3
QSPI_A_DATA5 NAND_DATA05 ALT3
QSPI_A_DATA6 NAND_DATA06 ALT3
QSPI_A_DATA7 NAND_DATA07 ALT3
QSPI_A_DQS NAND_DQS ALT1
QSPI_A_SCLK NAND_ALE ALT1
QSPI_A_SS0_B NAND_CE0_B ALT1
QSPI_A_SS1_B NAND_CE1_B ALT1
QSPI_B_DATA0 NAND_DATA04 ALT1
QSPI_B_DATA1 NAND_DATA05 ALT1
QSPI_B_DATA2 NAND_DATA06 ALT1
QSPI_B_DATA3 NAND_DATA07 ALT1
QSPI_B_DQS NAND_RE_B ALT1
QSPI_B_SCLK NAND_CLE ALT1
QSPI_B_SS0_B NAND_CE2_B ALT1
QSPI_B_SS1_B NAND_CE3_B ALT1
SAI1 SAI1_MCLK SAI1_MCLK ALT0
SAI1_RX_BCLK SAI1_RXC ALT0
SAI1_RX_DATA0 SAI1_RXD0 ALT0
SAI1_RX_DATA1 SAI1_RXD1 ALT0
SAI1_RX_DATA2 SAI1_RXD2 ALT0
SAI1_RX_DATA3 SAI1_RXD3 ALT0
SAI1_RX_DATA4 SAI1_RXD4 ALT0
SAI1_RX_DATA5 SAI1_RXD5 ALT0
SAI1_RX_DATA6 SAI1_RXD6 ALT0
SAI1_RX_DATA7 SAI1_RXD7 ALT0
SAI1_RX_SYNC SAI1_RXFS ALT0
SAI1_RXD5 ALT3
SAI1_TX_BCLK SAI1_TXC ALT0
SAI5_MCLK ALT1
SAI1_MCLK ALT2
SAI1_TX_DATA0 SAI1_TXD0 ALT0
SAI5_RXFS ALT1
SAI1_TX_DATA1 SAI1_TXD1 ALT0
SAI5_RXC ALT1
SAI1_RXD0 ALT2
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External Signals and Pin Multiplexing
Instance Port Pad Mode
SAI1_TX_DATA2 SAI1_TXD2 ALT0
SAI5_RXD0 ALT1
SAI1_TX_DATA3 SAI1_TXD3 ALT0
SAI5_RXD1 ALT1
SAI1_TX_DATA4 SAI1_TXD4 ALT0
SAI5_RXD2 ALT1
SAI1_RXD7 ALT3
SAI1_TX_DATA5 SAI1_TXD5 ALT0
SAI5_RXD3 ALT1
SAI1_TX_DATA6 SAI1_TXD6 ALT0
SAI1_TX_DATA7 SAI1_TXD7 ALT0
SAI1_TX_SYNC SAI1_TXFS ALT0
SAI5_RXD1 ALT2
SAI5_RXD2 ALT2
SAI5_RXD3 ALT2
SAI1_RXD7 ALT2
SAI2 SAI2_MCLK SAI2_MCLK ALT0
SAI2_RX_BCLK SAI2_RXC ALT0
SAI2_RX_DATA0 SAI2_RXD0 ALT0
SAI2_RX_DATA1 SAI3_RXFS ALT1
SAI2_RXFS ALT3
SAI2_RX_DATA2 SAI3_RXC ALT1
SAI2_RX_DATA3 SAI3_RXD ALT1
SAI2_RX_SYNC SAI2_RXFS ALT0
SAI2_TX_BCLK SAI2_TXC ALT0
SAI2_TX_DATA0 SAI2_TXD0 ALT0
SAI2_TX_DATA1 SAI3_TXFS ALT1
SAI2_RXD0 ALT3
SAI2_TXFS ALT3
SAI2_TX_DATA2 SAI3_TXC ALT1
SAI2_TX_DATA3 SAI3_TXD ALT1
SAI2_TX_SYNC SAI2_TXFS ALT0
SAI3 SAI3_MCLK SAI3_MCLK ALT0
NAND_DQS ALT2
SAI2_MCLK ALT6
SAI3_RX_BCLK SAI3_RXC ALT0
SAI3_RX_DATA0 SAI3_RXD ALT0
NAND_DATA00 ALT2
SAI3_RX_DATA1 SAI3_RXFS ALT3
SAI3_RX_SYNC SAI3_RXFS ALT0
SAI3_TX_BCLK SAI3_TXC ALT0
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Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
NAND_ALE ALT2
SAI3_TX_DATA0 SAI3_TXD ALT0
NAND_CE0_B ALT2
SAI3_TX_DATA1 SAI3_TXFS ALT3
SAI3_TX_SYNC SAI3_TXFS ALT0
NAND_DATA01 ALT2
SAI5 SAI5_MCLK SAI5_MCLK ALT0
SAI2_MCLK ALT1
SAI3_MCLK ALT2
SAI5_RX_BCLK SAI5_RXC ALT0
SAI3_RXC ALT2
SAI5_RX_DATA0 SAI5_RXD0 ALT0
SAI3_RXD ALT2
SAI5_RX_DATA1 SAI5_RXD1 ALT0
SAI3_TXFS ALT2
SAI5_RX_DATA2 SAI5_RXD2 ALT0
SAI3_TXC ALT2
SAI5_RX_DATA3 SAI5_RXD3 ALT0
SAI3_TXD ALT2
SAI5_RX_SYNC SAI5_RXFS ALT0
SAI3_RXFS ALT2
SAI5_TX_BCLK SAI2_RXC ALT1
SAI5_RXD2 ALT3
SAI5_TX_DATA0 SAI2_RXD0 ALT1
SAI5_RXD3 ALT3
SAI5_TX_DATA1 SAI2_TXFS ALT1
SAI2_RXFS ALT2
SAI5_TX_DATA2 SAI2_TXC ALT1
SAI5_TX_DATA3 SAI2_TXD0 ALT1
SAI5_TX_SYNC SAI2_RXFS ALT1
SAI5_RXD1 ALT3
SAI6 SAI6_MCLK SAI1_RXD7 ALT1
SAI1_TXD7 ALT1
ENET_TX_CTL ALT2
SAI6_RX_BCLK SAI1_TXD4 ALT1
ENET_TD0 ALT2
SAI1_RXD4 ALT2
SAI6_RX_DATA0 SAI1_TXD5 ALT1
ENET_TD2 ALT2
SAI1_RXD5 ALT2
SAI6_RX_SYNC SAI1_TXD6 ALT1
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External Signals and Pin Multiplexing
Instance Port Pad Mode
ENET_TD1 ALT2
SAI1_RXD6 ALT2
SAI6_TX_BCLK SAI1_RXD4 ALT1
ENET_TD3 ALT2
SAI1_TXD4 ALT2
SAI6_TX_DATA0 SAI1_RXD5 ALT1
ENET_MDC ALT2
SAI1_TXD5 ALT2
SAI6_TX_SYNC SAI1_RXD6 ALT1
ENET_MDIO ALT2
SAI1_TXD6 ALT2
SAI7 SAI7_MCLK ENET_RD3 ALT2
ECSPI2_MISO ALT3
SAI7_RX_BCLK ENET_RD2 ALT2
ECSPI1_MOSI ALT3
SAI7_RX_DATA0 ENET_RD0 ALT2
ECSPI1_MISO ALT3
SAI7_RX_SYNC ENET_RD1 ALT2
ECSPI1_SCLK ALT3
SAI7_TX_BCLK ENET_RXC ALT2
ECSPI2_SCLK ALT3
SAI7_TX_DATA0 ENET_TXC ALT2
ECSPI2_MOSI ALT3
SAI7_TX_SYNC ENET_RX_CTL ALT2
ECSPI1_SS0 ALT3
SDMA1 SDMA1_EXT_EVENT0 GPIO1_IO03 ALT5
SDMA1_EXT_EVENT1 GPIO1_IO04 ALT5
SDMA2 SDMA2_EXT_EVENT0 GPIO1_IO09 ALT5
SDMA2_EXT_EVENT1 GPIO1_IO12 ALT5
SJC SJC_DE_B GPIO1_IO02 ALT7
SNVS SNVS_ONOFF ONOFF ALT0
SNVS_PMIC_ON_REQ PMIC_ON_REQ ALT0
SNVS_POR_B POR_B ALT0
SNVS_RTC RTC_XTALI ALT0
SPDIF1 SPDIF1_EXT_CLK SPDIF_EXT_CLK ALT0
SAI3_TXD ALT4
SPDIF1_IN SPDIF_RX ALT0
ENET_RD3 ALT3
SD2_DATA3 ALT3
SAI3_RXFS ALT4
SAI3_MCLK ALT6
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Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
SPDIF1_OUT SPDIF_TX ALT0
ENET_TX_CTL ALT3
SD2_DATA2 ALT3
SAI3_MCLK ALT4
SRC SRC_BOOT_MODE0 BOOT_MODE0 ALT0
SRC_BOOT_MODE1 BOOT_MODE1 ALT0
SRC_BOOT_MODE2 BOOT_MODE2 ALT0
SRC_BOOT_MODE3 BOOT_MODE3 ALT0
UART1 UART1_CTS_B UART3_RXD ALT1
SD1_DATA1 ALT4
SAI2_TXFS ALT4
UART1_RTS_B UART3_TXD ALT1
SD1_DATA0 ALT4
SAI2_RXD0 ALT4
UART1_RX UART1_RXD ALT0
SD1_CMD ALT4
SAI2_RXC ALT4
UART1_TX UART1_TXD ALT0
SD1_CLK ALT4
SAI2_RXFS ALT4
UART2 UART2_CTS_B UART4_RXD ALT1
SD1_DATA5 ALT4
SAI3_RXC ALT4
UART2_RTS_B UART4_TXD ALT1
SD1_DATA4 ALT4
SAI3_RXD ALT4
UART2_RX UART2_RXD ALT0
SD2_DATA0 ALT3
SD1_DATA3 ALT4
SAI3_TXFS ALT4
UART2_TX UART2_TXD ALT0
SD2_DATA1 ALT3
SD1_DATA2 ALT4
SAI3_TXC ALT4
UART3 UART3_CTS_B ECSPI1_MISO ALT1
SD1_STROBE ALT4
UART3_RTS_B ECSPI1_SS0 ALT1
SD1_RESET_B ALT4
UART3_RX UART3_RXD ALT0
ECSPI1_SCLK ALT1
SD1_DATA7 ALT4
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External Signals and Pin Multiplexing
Instance Port Pad Mode
NAND_ALE ALT4
UART3_TX UART3_TXD ALT0
ECSPI1_MOSI ALT1
SD1_DATA6 ALT4
NAND_CE0_B ALT4
UART4 UART4_CTS_B ECSPI2_MISO ALT1
NAND_DATA02 ALT3
UART4_RTS_B ECSPI2_SS0 ALT1
NAND_DATA03 ALT3
UART4_RX UART4_RXD ALT0
ECSPI2_SCLK ALT1
SD2_CLK ALT3
NAND_CLE ALT4
NAND_DATA00 ALT4
UART4_TX UART4_TXD ALT0
ECSPI2_MOSI ALT1
SD2_CMD ALT3
NAND_DATA01 ALT4
NAND_RE_B ALT4
USB1 USB1_OC GPIO1_IO13 ALT1
USB1_PWR GPIO1_IO12 ALT1
USB1_DN USB1_D_N No muxing
USB1_DP USB1_D_P No muxing
USB1_RESREF USB1_TXRTUNE No muxing
USB1_RX_N USB1_RX_N No muxing
USB1_RX_P USB1_RX_P No muxing
USB1_TX_N USB1_TX_N No muxing
USB1_TX_P USB1_TX_P No muxing
USB1_VBUS USB1_VBUS No muxing
USB2 USB2_OC GPIO1_IO15 ALT1
USB2_PWR GPIO1_IO14 ALT1
USB2_DN USB2_D_N No muxing
USB2_DP USB2_D_P No muxing
USB2_RESREF USB2_TXRTUNE No muxing
USB2_RX_N USB2_RX_N No muxing
USB2_RX_P USB2_RX_P No muxing
USB2_TX_N USB2_TX_N No muxing
USB2_TX_P USB2_TX_P No muxing
USB2_VBUS USB2_VBUS No muxing
USDHC1 USDHC1_CD_B GPIO1_IO06 ALT5
USDHC1_CLK SD1_CLK ALT0
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Chapter 8 Chip IO and Pinmux
Instance Port Pad Mode
USDHC1_CMD SD1_CMD ALT0
USDHC1_DATA0 SD1_DATA0 ALT0
USDHC1_DATA1 SD1_DATA1 ALT0
USDHC1_DATA2 SD1_DATA2 ALT0
USDHC1_DATA3 SD1_DATA3 ALT0
USDHC1_DATA4 SD1_DATA4 ALT0
USDHC1_DATA5 SD1_DATA5 ALT0
USDHC1_DATA6 SD1_DATA6 ALT0
USDHC1_DATA7 SD1_DATA7 ALT0
USDHC1_RESET_B SD1_RESET_B ALT0
USDHC1_STROBE SD1_STROBE ALT0
USDHC1_VSELECT GPIO1_IO03 ALT1
USDHC1_WP GPIO1_IO07 ALT5
USDHC2 USDHC2_CD_B SD2_CD_B ALT0
USDHC2_CLK SD2_CLK ALT0
USDHC2_CMD SD2_CMD ALT0
USDHC2_DATA0 SD2_DATA0 ALT0
USDHC2_DATA1 SD2_DATA1 ALT0
USDHC2_DATA2 SD2_DATA2 ALT0
USDHC2_DATA3 SD2_DATA3 ALT0
USDHC2_RESET_B SD2_RESET_B ALT0
GPIO1_IO08 ALT5
USDHC2_VSELECT GPIO1_IO04 ALT1
USDHC2_WP SD2_WP ALT0
USDHC3 USDHC3_CD_B NAND_DATA02 ALT2
I2C2_SCL ALT2
GPIO1_IO14 ALT4
ENET_TD1 ALT6
USDHC3_CLK NAND_WE_B ALT2
ENET_RD2 ALT6
USDHC3_CMD NAND_WP_B ALT2
ENET_RD3 ALT6
USDHC3_DATA0 NAND_DATA04 ALT2
ENET_TX_CTL ALT6
USDHC3_DATA1 NAND_DATA05 ALT2
ENET_TXC ALT6
USDHC3_DATA2 NAND_DATA06 ALT2
ENET_RX_CTL ALT6
USDHC3_DATA3 NAND_DATA07 ALT2
ENET_RXC ALT6
USDHC3_DATA4 NAND_RE_B ALT2
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IOMUX Controller (IOMUXC)
Instance Port Pad Mode
ENET_RD0 ALT6
USDHC3_DATA5 NAND_CE2_B ALT2
ENET_MDIO ALT6
USDHC3_DATA6 NAND_CE3_B ALT2
ENET_TD3 ALT6
USDHC3_DATA7 NAND_CLE ALT2
ENET_TD2 ALT6
USDHC3_RESET_B NAND_READY_B ALT2
UART3_RXD ALT2
GPIO1_IO09 ALT4
ENET_RD1 ALT6
USDHC3_STROBE NAND_CE1_B ALT2
ENET_MDC ALT6
USDHC3_VSELECT UART3_TXD ALT2
GPIO1_IO11 ALT4
USDHC3_WP NAND_DATA03 ALT2
I2C2_SDA ALT2
GPIO1_IO15 ALT4
ENET_TD0 ALT6
WDOG1 WDOG1_WDOG_ANY GPIO1_IO02 ALT5
WDOG1_WDOG_B GPIO1_IO02 ALT1
XTALOSC XTALI_24M XTALI_24M No Muxing
XTALO_24M XTALO_24M No Muxing
8.2 IOMUX Controller (IOMUXC)
8.2.1 Overview
The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC to share
one pad to several functional blocks. This sharing is done by multiplexing the pad's input
and output signals.
Every module requires a specific pad setting (such as pull up or keeper), and for each
pad, there are up to 8 muxing options (called ALT modes). The pad settings parameters
are controlled by the IOMUXC.
The IOMUX consists only of combinatorial logic combined from several basic IOMUX
cells. Each basic IOMUX cell handles only one pad signal's muxing.
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Chapter 8 Chip IO and Pinmux
Figure 8-1 illustrates the IOMUX/IOMUXC connectivity in the system.
PAD Settings
PAD Settings
Registers
MUX Control
Registers
IOMUXC
. .
IOMUX IO Pad
Cells
. Cells
.
. .
IPMUX
HW
signal
moduleY
CFG
AIPS Reg
moduleX IOMUX IORING
Arm PLATFORM + AHBMAX module module module
#1 #2 #N
Figure 8-1. IOMUX SoC Level Block Diagram
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IOMUX Controller (IOMUXC)
8.2.1.1 Block Diagram
The high level illustration of the IO cells is shown in Figure 8-3
8.2.1.2 Features
The IOMUXC features include:
• 32-bit software mux control registers (IOMUXC_SW_MUX_CTL_PAD_<PAD
NAME> or IOMUXC_SW_MUX_CTL_GRP_<GROUP NAME>) to configure 1 of
8 alternate (ALT) MUX_MODE fields of each pad or a predefined group of pads and
to enable the forcing of an input path of the pad(s) (SION bit).
• 32-bit software pad control registers
(IOMUXC_SW_PAD_CTL_PAD_<PAD_NAME> or
IOMUXC_SW_PAD_CTL_GRP_<GROUP NAME>) to configure specific pad
settings of each pad, or a predefined group of pads.
• 32-bit general purpose registers - several (GPR0 to GPRn) 32-bit registers according
to SoC requirements for any usage.
• 32-bit input select control registers to control the input path to a module when more
than one pad drives this module input.
Each SW MUX/PAD CTL IOMUXC register handles only one pad or one pad's group.
Only the minimum number of registers required by software are implemented by
hardware. For example, if only ALT0 and ALT1 modes are used on Pad x then only one
bit register will be generated as the MUX_MODE control field in the software mux
control register of Pad x.
The software mux control registers may allow the forcing of pads to become input (input
path enabled) regardless of the functional direction driven. This may be useful for
loopback and GPIO data capture.
8.2.2 Functional description
This section provides a complete functional description of the block.
The IOMUXC consists of two sub-blocks:
• IOMUXC_REGISTERS includes all of the IOMUXC registers (see Features).
• IOMUXC_LOGIC includes all of the IOMUXC combinatorial logic (IP interface
controls, address decoder, observability muxes).
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Chapter 8 Chip IO and Pinmux
The IOMUX consists of a number (about the number of pads in the SoC) of basic
iomux_cell units. If only one functional mode is required for a specific pad, there is no
need for IOMUX and the signals can be connected directly from the module to the I/O.
The IOMUX cell is required whenever two or more functional modes are required for a
specific pad or when one functional mode and the one test mode are required.
The basic iomux_cell design, which allows two levels of HW signal control (in ALT6
and ALT7 modes - ALT7 gets highest priority) is shown in Figure 8-2.
IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
: PAD0
ALTn
ALT0
ALT1
<SOURCE>_SELECT_INPUT :
ALTn
Peripheral1 DATA_IN IOMUXC_SW_MUX_CTRL_<PAD>[MUX_MODE]
SW_PAD_CTL
ALT0
ALT1
:
PAD1
ALTn
ALT0
ALT1
:
ALTn
Figure 8-2. IOMUX Cell Block Diagram
8.2.2.1 GPIO pad features
The GPIO pad includes the following features:
• Wide-range voltage interface
• 1.8V ~ 3.3V I/O interface
• CMOS input / Schmitt trigger Input
• 3-state and open-drain output
• Two slew rate control levels
• Programmable feature support
• Controllable input enable
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IOMUX Controller (IOMUXC)
• Controllable CMOS/Schmitt trigger input
• Controllable pull-up/pull-down resistor
• Controllable output drive strength (x1 / x2 / x4 / x6)
• Controllable slew rate control (slow slew / fast slew)
8.2.2.1.1 Pull up/Pull down control
Pull up/Pull down function is controlled by the PE and PS pin.
Table 8-1. Pull up / Pull down control truth table
Mode State
PE PS
Disable 0 X
Pull-down enable 1 0
Pull-up enable 1 1
8.2.2.1.2 Input control
The IS pin selects CMOS and Schmitt trigger.
Table 8-2. Input control truth table
Mode State
IE IS
Disable 0 X
CMOS input 1 0
Schmitt trigger input 1 1
8.2.2.1.3 Output driver control
Output drive strength is controlled by the DS0, DS1 pin.
Table 8-3. Drive strength control truth table
State Driver Strength
DS1 DS0
0 0 X1
1 0 X2
0 1 X4
1 1 X6
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The SR pin controls slew-rate of output driver.
Table 8-4. Slew-rate of output driver
State Driver Slew
SR
0 Fast Slew
1 Slow Slew
8.2.2.2 ALT6 and ALT7 extended muxing modes
The ALT7 and ALT6 extended muxing modes allow any signal in the system (such as
fuse, pad input, JTAG, or software register) to override any software configuration and to
force the ALT6/ALT7 muxing mode.
It also allows an IOMUX software register to control a group of pads.
8.2.2.3 SW Loopback through SION bit
A limited option exists to override the default pad functionality and force the input path
to be active (ipp_ibe==1'b1) regardless of the value driven by the corresponding module.
This can be done by setting the SION (Software Input On) bit in the
IOMUXC_SW_MUX_CTL register (when available) to "1".
Uses include:
• LoopBack - Module x drives the pad and also receives pad value as an input.
• GPIO Capture - Module x drives the pad and the value is captured by GPIO.
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IOMUX Controller (IOMUXC)
8.2.2.4 Daisy chain - multi pads driving same module input pin
In some cases, more than one pad may drive a single module input pin. Such cases
require the addition of one more level of IOMUXing; all of these input signals are
muxed, and a dedicated software controlled register controls the mux in order to select
the required input path.
A module port involved in "daisy chain" requires two software configuration commands,
one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers).
This means that a module port involved in "daisy chain" requires two software
configuration commands, one for selecting the mode for this pad (programable via the
IOMUXC_SW_MUX_CTL_<PAD> registers) and one for defining it as the input path
(via the daisy chain registers). The daisy chain is illustrated in the figure below.
IOMUX IORING
IOMUX Cells
To module D
To module F
A
To module X
ALT x select
To module G
To module X
Module X B
To module H
ALT x select
Daisy Chain
To module X
select
To module M
C
To module N
ALT x select
Figure 8-3. Daisy chain illustration
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Chapter 8 Chip IO and Pinmux
8.2.2.5 Clocks
The table found here describes the clock sources for IOMUXC.
Please see Clock Controller Module (CCM) for clock setting, configuration and gating
information.
Table 8-5. IOMUXC Clocks
Clock name Clock Root Description
ipg_clk_s ipg_clk_root Peripheral access clock
8.2.3 IOMUXC GPR Memory Map/Register Definition
IOMUXC_GPR memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
3034_0000 General Purpose Register 0 (IOMUXC_GPR_GPR0) 32 R/W 0000_0000h 8.2.3.1/1366
3034_0004 General Purpose Register 1 (IOMUXC_GPR_GPR1) 32 R/W 0001_0000h 8.2.3.2/1367
3034_0008 General Purpose Register 2 (IOMUXC_GPR_GPR2) 32 R/W 0000_0000h 8.2.3.3/1369
3034_000C General Purpose Register 3 (IOMUXC_GPR_GPR3) 32 R/W 0000_0000h 8.2.3.4/1369
3034_0010 General Purpose Register 4 (IOMUXC_GPR_GPR4) 32 R/W 0000_0000h 8.2.3.5/1370
3034_0014 General Purpose Register 5 (IOMUXC_GPR_GPR5) 32 R/W 0000_0000h 8.2.3.6/1373
3034_0018 General Purpose Register 6 (IOMUXC_GPR_GPR6) 32 R/W 0000_0000h 8.2.3.7/1374
3034_001C General Purpose Register 7 (IOMUXC_GPR_GPR7) 32 R/W 0000_0000h 8.2.3.8/1374
3034_0020 General Purpose Register 8 (IOMUXC_GPR_GPR8) 32 R/W 0000_0000h 8.2.3.9/1375
8.2.3.10/
3034_0024 General Purpose Register 9 (IOMUXC_GPR_GPR9) 32 R/W 0000_0000h
1375
8.2.3.11/
3034_0028 General Purpose Register 10 (IOMUXC_GPR_GPR10) 32 R/W 0000_0008h
1376
8.2.3.12/
3034_002C General Purpose Register 11 (IOMUXC_GPR_GPR11) 32 R/W 0000_0200h
1377
8.2.3.13/
3034_0030 General Purpose Register 12 (IOMUXC_GPR_GPR12) 32 R/W 0000_4000h
1379
8.2.3.14/
3034_0034 General Purpose Register 13 (IOMUXC_GPR_GPR13) 32 R/W 0000_0000h
1380
8.2.3.15/
3034_0038 General Purpose Register 14 (IOMUXC_GPR_GPR14) 32 R/W 0349_4000h
1382
8.2.3.16/
3034_003C General Purpose Register 15 (IOMUXC_GPR_GPR15) 32 R/W 0000_0000h
1383
8.2.3.17/
3034_0040 General Purpose Register 16 (IOMUXC_GPR_GPR16) 32 R/W 0000_0000h
1384
Table continues on the next page...
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IOMUXC_GPR memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
8.2.3.18/
3034_0044 General Purpose Register 17 (IOMUXC_GPR_GPR17) 32 R/W 0000_0000h
1385
8.2.3.19/
3034_0048 General Purpose Register 18 (IOMUXC_GPR_GPR18) 32 R/W 0000_0000h
1385
8.2.3.20/
3034_004C General Purpose Register 19 (IOMUXC_GPR_GPR19) 32 R See section
1385
8.2.3.21/
3034_0050 General Purpose Register 20 (IOMUXC_GPR_GPR20) 32 R/W 0000_0000h
1386
8.2.3.22/
3034_0054 General Purpose Register 21 (IOMUXC_GPR_GPR21) 32 R/W See section
1389
8.2.3.23/
3034_0058 General Purpose Register 22 (IOMUXC_GPR_GPR22) 32 R/W 0000_0001h
1391
8.2.3.24/
3034_005C General Purpose Register 23 (IOMUXC_GPR_GPR23) 32 R/W 0000_0000h
1393
8.2.3.25/
3034_0060 General Purpose Register 24 (IOMUXC_GPR_GPR24) 32 R See section
1393
8.2.3.1 General Purpose Register 0 (IOMUXC_GPR_GPR0)
Address: 3034_0000h base + 0h offset = 3034_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR0 field descriptions
Field Description
- This field is reserved.
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8.2.3.2 General Purpose Register 1 (IOMUXC_GPR_GPR1)
Address: 3034_0000h base + 4h offset = 3034_0004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_DBG_ACK_M7_MASK
GPR_TZASC1_SECURE_
QOS_CLK_TX_CLK_SEL
GPR_ENET_QOS_CLK_
IOMUXC_GPR_ENET1_
IOMUXC_GPR_ENET_
IOMUXC_GPR_ENET_
R
QOS_RGMII_EN
BOOT_LOCK
RGMII_EN
GEN_EN
GPR_DBG_ACK_A53_ GPR_ENET_QOS_
Reserved
MASK INTF_SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOMUXC_GPR_ENET1_TX_
GPR_ANAMIX_IPT_MODE
GPR_GPT1_CAPIN2_SEL
GPR_GPT1_CAPIN1_SEL
GPR_ENET1_EVENT0IN_
GPR_ENET_QOS_DIS_
GPR_ENET_QOS_
R
EVENT0IN_SEL
CRC_CHK
GPR_IRQ
CLK_SEL
SEL
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR1 field descriptions
Field Description
31–28 Mask debug ack from each CA53 core
GPR_DBG_
ACK_A53_MASK 0 unmasked
1 mask to 0
27 Mask debug ack from each CM7
GPR_DBG_
ACK_M7_MASK 0 unmasked
1 mask to 0
26–24 This field is reserved.
-
23 secure_boot_lock for TZASC
GPR_TZASC1_
SECURE_
BOOT_LOCK
22 ENET1 TX clock direction select for RGMII or MII
IOMUXC_GPR_
ENET1_RGMII_ 0 MII (input)
EN 1 RGMII (output)
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IOMUXC_GPR_GPR1 field descriptions (continued)
Field Description
21 ENET QOS TX clock direction select for RGMII or MII
IOMUXC_GPR_
ENET_QOS_ 0 MII(input)
RGMII_EN 1 RGMII(output)
20 SOI bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should also be set.
IOMUXC_GPR_
ENET_QOS_ 1 ENET QOS RMII clock comes from ccm->pad->loopback
CLK_TX_CLK_ 0 ENET QOS RMII clock comes from external PHY or OSC
SEL
19 Enable clk generate module for ENET QoS
GPR_ENET_
QOS_CLK_ 0 disable
GEN_EN 1 enable
18–16 Select ENET QOS working mode
GPR_ENET_
QOS_INTF_SEL 0 MII
1 RGMII
4 RMII
15 Mask ANAMIX ipt_mode
GPR_ANAMIX_
IPT_MODE 0 masked to 0
1 unmasked
14 Disable CRC check feature
GPR_ENET_
QOS_DIS_CRC_ 0 do not disable
CHK 1 disable
13 SOI bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should also be set
IOMUXC_GPR_
ENET1_TX_ 1 ENET1 RMII clock comes from ccm->pad->loopback
CLK_SEL 0 ENET1 RMII clock comes from external PHY or OSC
12 Generate IRQ on IRQ0
GPR_IRQ
11–8 This field is reserved.
-
7–4 This field is reserved.
-
3 Selector for GPT1 Capture in Channel 2
GPR_GPT1_
CAPIN2_SEL 0 IOMUX
1 ENET QOS TIMIER1 EVENT
2 Selector for GPT1 Capture in Channel 1
GPR_GPT1_
CAPIN1_SEL 0 IOMUX
1 ENET1 TIMIER1 EVENT
1 Selector for ENET QoS EVENT0 IN
GPR_ENET_
QOS_ 0 IOMUX;
EVENT0IN_SEL 1 GPT1 CMPOUT2
Table continues on the next page...
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IOMUXC_GPR_GPR1 field descriptions (continued)
Field Description
0 Selector for ENET1 EVENT0 IN
GPR_ENET1_
EVENT0IN_SEL 0 IOMUX
1 GPT1 CMPOUT2
8.2.3.3 General Purpose Register 2 (IOMUXC_GPR_GPR2)
Address: 3034_0000h base + 8h offset = 3034_0008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_
R CORE
SIGH
Reserved T_
GPR_
W CTM_
SEL
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR2 field descriptions
Field Description
31–2 This field is reserved.
-
GPR_ Select for Coresight master
CORESIGHT_
GPR_CTM_SEL
8.2.3.4 General Purpose Register 3 (IOMUXC_GPR_GPR3)
Address: 3034_0000h base + Ch offset = 3034_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR3 field descriptions
Field Description
- This field is reserved.
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8.2.3.5 General Purpose Register 4 (IOMUXC_GPR_GPR4)
Address: 3034_0000h base + 10h offset = 3034_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_FLEXSPI_O_IPG_STOP_ACK
GPR_SDAM1_IPG_STOP_ACK
GPR_ENET1_IPG_STOP_ACK
GPR_CAN2_IPG_STOP_ACK
GPR_CAN1_IPG_STOP_ACK
R CPU_STANDBYWFE CPU_STANDBYWFI
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_FLEXSPI_I_IPG_STOP
GPR_SDMA1_IPG_STOP
GPR_ENET1_IPG_STOP
GPR_CAN2_IPG_STOP
GPR_CAN1_IPG_STOP
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR4 field descriptions
Field Description
31–28 From CA53. Status of CPU STANDBYWFE low power states.
CPU_
MSB: status of core 3 STANDBYWFE low power state
STANDBYWFE
LSB: status of core 0 STANDBYWFE low power state
1 WFE
27–24 From CA53. Status of CPU STANDBYWFI low power states.
CPU_
MSB: status of core 3 STANDBYWFI low power state
STANDBYWFI
LSB: status of core 0 STANDBYWFI low power state
1 WFI
23–22 This field is reserved.
-
21 CAN2 stop acknowledge
GPR_CAN2_
IPG_STOP_ACK 0 stop acknowledge is not asserted
1 stop acknowledge is asserted, peripheral is in STOP mode
20 CAN1 stop acknowledge
GPR_CAN1_
IPG_STOP_ACK 0 stop acknowledge is not asserted
1 stop acknowledge is asserted, peripheral is in STOP mode
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IOMUXC_GPR_GPR4 field descriptions (continued)
Field Description
19 ENET1 stop acknowledge
GPR_ENET1_
IPG_STOP_ACK 0 stop acknowledge is not asserted
1 stop acknowledge is asserted, peripheral is in STOP mode
18 This field is reserved.
-
17 FLEXSPI stop acknowledge
GPR_FLEXSPI_
O_IPG_STOP_ 0 stop acknowledge is not asserted
ACK 1 stop acknowledge is asserted, peripheral is in STOP mode
16 SDMA1 stop acknowledge
GPR_SDAM1_
IPG_STOP_ACK 0 stop acknowledge is not asserted
1 stop acknowledge is asserted, peripheral is in STOP mode
15–6 This field is reserved.
-
5 CAN2 stop request
GPR_CAN2_
IPG_STOP 0 stop request off
1 stop request on
4 CAN1 stop request
GPR_CAN1_
IPG_STOP 0 stop request off
1 stop request on
3 ENET1 stop request
GPR_ENET1_
IPG_STOP 0 stop request off
1 stop request on
2 This field is reserved.
-
1 FLEXSPI stop request
GPR_FLEXSPI_
I_IPG_STOP 0 stop request off
1 stop request on
0 SDMA1 stop request
GPR_SDMA1_
IPG_STOP 0 stop request off
1 stop request on
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8.2.3.6 General Purpose Register 5 (IOMUXC_GPR_GPR5)
Address: 3034_0000h base + 14h offset = 3034_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_WDOG3_MASK
R
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_RMW_S_WAIT_
GPR_WDOG2_MASK
GPR_WDOG1_MASK
GPR_RMW_WAIT_
GPR_ENABLE_
R
BVALID_CPL
BVALID_CPL
UPSIZER
Reserved Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR5 field descriptions
Field Description
31–21 This field is reserved.
-
20 This bit is only used to mask the internal WDOG3 int signal for output of GPIO1_IO02.ALT5_OUT, which
GPR_WDOG3_ is combined with WDOG1/2/3.
MASK
0 WDOG3 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG3 low will NOT impact the GPIO1_IO02.ALT5_OUT
19–8 This field is reserved.
-
7 This bit is only used to mask the internal WDOG2 int signal for output of GPIO1_IO02.ALT5_OUT, which
GPR_WDOG2_ is combined with WDOG1/2/3.
MASK
0 WDOG2 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG2 low will NOT impact the GPIO1_IO02.ALT5_OUT
6 Normally, WDOG1 output is in GPIO1_IO02.ALT1_OUT. This bit is only used to mask the internal
GPR_WDOG1_ WDOG1 int signal for output of GPIO1_IO02.ALT5_OUT, which is combined with WDOG1/2/3.
MASK
0 WDOG1 low will make the GPIO1_IO02.ALT5_OUT low
1 WDOG1 low will NOT impact the GPIO1_IO02.ALT5_OUT
5–3 This field is reserved.
-
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IOMUXC_GPR_GPR5 field descriptions (continued)
Field Description
2 Enable to upsize 32=bit SDMA1 burst transaction to 64-bit
GPR_ENABLE_
UPSIZER
1 If this bit set to 1, RMW will write back the next data after bvalid_s is 1
GPR_RMW_S_
WAIT_BVALID_
CPL
0 If this bit set to 1, RMW will write back the next data after bvalid_s is 1
GPR_RMW_
WAIT_BVALID_
CPL
8.2.3.7 General Purpose Register 6 (IOMUXC_GPR_GPR6)
Address: 3034_0000h base + 18h offset = 3034_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GPR_M7_INITVTOR Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR6 field descriptions
Field Description
31–7 Decides where CM7 boots up out of reset
GPR_M7_
INITVTOR
- This field is reserved.
8.2.3.8 General Purpose Register 7 (IOMUXC_GPR_GPR7)
Address: 3034_0000h base + 1Ch offset = 3034_001Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR7 field descriptions
Field Description
- This field is reserved.
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8.2.3.9 General Purpose Register 8 (IOMUXC_GPR_GPR8)
Address: 3034_0000h base + 20h offset = 3034_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR8 field descriptions
Field Description
- This field is reserved.
8.2.3.10 General Purpose Register 9 (IOMUXC_GPR_GPR9)
Address: 3034_0000h base + 24h offset = 3034_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR9 field descriptions
Field Description
- This field is reserved.
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8.2.3.11 General Purpose Register 10 (IOMUXC_GPR_GPR10)
Address: 3034_0000h base + 28h offset = 3034_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK_GPR_TZASC_ID_
LOCK_GPR_EXC_ERR_
LOCK_GPR_SEC_ERR_
LOCK_GPR_TZASC_EN
R
SWAP_BYPASS
RESP_EN
RESP_EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_TZASC_ID_SWAP_
GPR_OCRAM_A_TZ_EN
GPR_EXC_ERR_RESP_
GPR_SEC_ERR_RESP_
GPR_TZASC_EN
R
BYPASS
EN
EN
Reserved GPR_OCRAM_A_TZ_START_ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
IOMUXC_GPR_GPR10 field descriptions
Field Description
31–20 This field is reserved.
-
19 Lock bit for GPR_EXC_ERR_RESP_EN
LOCK_GPR_
EXC_ERR_
RESP_EN
18 Lock bit for GPR_SEC_ERR_RESP_EN
LOCK_GPR_
SEC_ERR_
RESP_EN
17 Lock bit for GPR_TZASC_ID_SWAP_BYPASS
LOCK_GPR_
TZASC_ID_
SWAP_BYPASS
16 Lock bit for GPR_TZASC_EN
LOCK_GPR_
TZASC_EN
15–11 This field is reserved.
-
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IOMUXC_GPR_GPR10 field descriptions (continued)
Field Description
10–5 OCRAM Audio Trustzone start address
GPR_OCRAM_
A_TZ_START_
ADDR
4 OCRAM Audio Trustzone Enable
GPR_OCRAM_
A_TZ_EN
3 mem security gasket exclusive error response enable
GPR_EXC_
ERR_RESP_EN
2 mem security gasket security error response enable
GPR_SEC_
ERR_RESP_EN
1 Connect to id_swap_bypass input on tzasc_id_wrap.
GPR_TZASC_
ID_SWAP_
BYPASS
0 Connect to tzasc_en input on tzasc_id_wrap.
GPR_TZASC_
EN
8.2.3.12 General Purpose Register 11 (IOMUXC_GPR_GPR11)
Address: 3034_0000h base + 2Ch offset = 3034_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LOCK_GPR_OCRAM_S_
CAAM_IPS_MANAGER
LOCK_GPR_OCRAM_
LOCK_GPR_CAAM_
LOCK_GPR_
TZ_EN
TZ_EN
Reserved OCRAM_S_TZ_ LOCK_GPR_OCRAM_TZ_START_ADDR
START_ADDR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_CAAM_CAAM_IPS_
GPR_OCRAM_S_TZ_EN
GPR_OCRAM_TZ_EN
R
MANAGER
Reserved
GPR_OCRAM_S_TZ_
GPR_OCRAM_TZ_START_ADDR
START_ADDR
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
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IOMUX Controller (IOMUXC)
IOMUXC_GPR_GPR11 field descriptions
Field Description
31–30 This field is reserved.
-
29–27 Lock bit for GPR_OCRAM_S_TZ_START_ADDR[15:12]
LOCK_GPR_
OCRAM_S_TZ_
START_ADDR
26 Lock bit for GPR_OCRAM_S_TZ_EN
LOCK_GPR_
OCRAM_S_TZ_
EN
25 Lock bit for GPR_CAAM_CAAM_IPS_MANAGER[4]
LOCK_GPR_
CAAM_CAAM_
IPS_MANAGER
24–17 Lock bit for GPR_OCRAM_TZ_START_ADDR[19:12]
LOCK_GPR_
OCRAM_TZ_
START_ADDR
16 Lock bit for GPR_OCRAM_TZ_EN
LOCK_GPR_
OCRAM_TZ_EN
15 This field is reserved.
-
14–11 OCRAM_S Trustzone start address
GPR_OCRAM_
S_TZ_START_
ADDR
10 OCRAM_S Trustzone Enable
GPR_OCRAM_
S_TZ_EN
9 Used to control whether CAAM manager page and Job ring registers are controlled by CSU/RDC slot
GPR_CAAM_
CAAM_IPS_ 0 not controlled by CSU/RDC slot
MANAGER 1 controlled by CSU/RDC slot
8–1 OCRAM Trustzone start address
GPR_OCRAM_
TZ_START_
ADDR
0 OCRAM Trustzone Enable
GPR_OCRAM_
TZ_EN
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Chapter 8 Chip IO and Pinmux
8.2.3.13 General Purpose Register 12 (IOMUXC_GPR_GPR12)
Address: 3034_0000h base + 30h offset = 3034_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_PCIE_DIAG_BUS_
GPR_PCIE1_CTRL_
DIAG_CTRL_BUS
R
Reserved
GPR_PCIE1_CTRL_DIAG_
SEL
Reserved
STATUS_BUS_SELECT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_PCIE1_CTRL_
Reserved
DEVICE_TYPE
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR12 field descriptions
Field Description
31 To PCIe CTRL
GPR_PCIE_
DIAG_BUS_SEL
30–23 This field is reserved.
-
22–21 To PCIe CTRL
GPR_PCIE1_
CTRL_DIAG_
CTRL_BUS
20–17 To PCIe CTRL
GPR_PCIE1_
CTRL_DIAG_
STATUS_BUS_
SELECT
16 This field is reserved.
-
15–12 To PCIe CTRL
GPR_PCIE1_
CTRL_DEVICE_
TYPE
- This field is reserved.
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IOMUX Controller (IOMUXC)
8.2.3.14 General Purpose Register 13 (IOMUXC_GPR_GPR13)
Address: 3034_0000h base + 34h offset = 3034_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_AWCACHE_USDHC
GPR_ARCACHE_USDHC
GPR_AWCACHE_PCIE_
GPR_ARCACHE_PCIE_
GPR_AWCACHE_USB2
GPR_AWCACHE_USB1
GPR_ARCACHE_USB2
GPR_ARCACHE_USB1
GPR_AWCACHE_PCIE
GPR_ARCACHE_PCIE
R
Reserved
Reserved
Reserved
Reserved
EN
EN
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR13 field descriptions
Field Description
31–16 This field is reserved.
-
15 This field is reserved.
-
14 Control the awcache[1] of usb master transaction
GPR_
AWCACHE_
USB2
13 Control the arcache[1] of usb master transaction
GPR_
ARCACHE_
USB2
12 This field is reserved.
-
11 Enable the GPR control of AWCACHE[1] of PCIE1 master transaction
GPR_
AWCACHE_
PCIE_EN
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_GPR_GPR13 field descriptions (continued)
Field Description
10 Enable the GPR control of ARCACHE[1] of PCIE1 master transaction
GPR_
ARCACHE_
PCIE_EN
9 This field is reserved.
-
8 Control the awcache[1] of usb master transaction
GPR_
AWCACHE_
USB1
7 Control the arcache[1] of usb master transaction
GPR_
ARCACHE_
USB1
6 This field is reserved.
-
5 Control the awcache[1] of pcie master transaction
GPR_
AWCACHE_
PCIE
4 Control the arcache[1] of pcie master transaction
GPR_
ARCACHE_PCIE
3–2 This field is reserved.
-
1 sim_m.awcache_m_d_6/7/8[1]
GPR_
AWCACHE_
USDHC
0 sim_m.arcache_m_d_6/7/8[1]
GPR_
ARCACHE_
USDHC
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IOMUX Controller (IOMUXC)
8.2.3.15 General Purpose Register 14 (IOMUXC_GPR_GPR14)
Address: 3034_0000h base + 38h offset = 3034_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_PCIE_PHY_PLL_
R
REF_CLK_SEL
GPR_PCIE_PHY_CTRL_
Reserved Reserved
BUS
Reset 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_PCIE_CLKREQ_B_
GPR_PCIE_CLKREQ_B_
GPR_PCIE_REF_USE_
GPR_PCIE_APP_CLK_
R
OVERRIDE_EN
OVERRIDE
PM_EN
PAD
Reserved Reserved
Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR14 field descriptions
Field Description
31–26 This field is reserved.
-
25–24 PCIE PHY reference clock select
GPR_PCIE_
PHY_PLL_REF_ 00 N/A
CLK_SEL 01 Selects reference clock from XO (pll_refclk_from_xo)
10 Selects reference clock from IO (ext_ref_clkp/n)
11 Selects reference clock from SOC PLL (pll_refclk_from_syspll)
23–20 This field is reserved.
-
19–16 To PCIe CTRL
GPR_PCIE_
PHY_CTRL_BUS
15–12 This field is reserved.
-
11 Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
GPR_PCIE_
CLKREQ_B_
OVERRIDE
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_GPR_GPR14 field descriptions (continued)
Field Description
10 Control the PCIE_CLKREQ_B to the pad together with CLKREQ_B from controller
GPR_PCIE_
CLKREQ_B_
OVERRIDE_EN
9 To PCIe CTRL
GPR_PCIE_
REF_USE_PAD
8 To PCIe CTRL
GPR_PCIE_
APP_CLK_PM_
EN
- This field is reserved.
8.2.3.16 General Purpose Register 15 (IOMUXC_GPR_GPR15)
Address: 3034_0000h base + 3Ch offset = 3034_003Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU2D GPR_GPUMIX_GPR_AXI_LIMIT_BEAT_LIMIT_GPU3D
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR15 field descriptions
Field Description
31–16 GPU2D AXI OTR limit beat limit
GPR_GPUMIX_
GPR_AXI_
LIMIT_BEAT_
LIMIT_GPU2D
GPR_GPUMIX_ GPU3D AXI OTR limit beat limit
GPR_AXI_
LIMIT_BEAT_
LIMIT_GPU3D
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IOMUX Controller (IOMUXC)
8.2.3.17 General Purpose Register 16 (IOMUXC_GPR_GPR16)
Address: 3034_0000h base + 40h offset = 3034_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_GPUMIX_GPR_AXI_
GPR_GPUMIX_GPR_AXI_
LIMIT_ENABLE_GPU2D
LIMIT_ENABLE_GPU3D
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR16 field descriptions
Field Description
31–2 This field is reserved.
-
1 GPU2D AXI OTR limit gasket eanble
GPR_GPUMIX_
GPR_AXI_
LIMIT_ENABLE_
GPU2D
0 GPU3D AXI OTR limit gasket eanble
GPR_GPUMIX_
GPR_AXI_
LIMIT_ENABLE_
GPU3D
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Chapter 8 Chip IO and Pinmux
8.2.3.18 General Purpose Register 17 (IOMUXC_GPR_GPR17)
Address: 3034_0000h base + 44h offset = 3034_0044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR17 field descriptions
Field Description
- This field is reserved.
8.2.3.19 General Purpose Register 18 (IOMUXC_GPR_GPR18)
Address: 3034_0000h base + 48h offset = 3034_0048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR18 field descriptions
Field Description
- This field is reserved.
8.2.3.20 General Purpose Register 19 (IOMUXC_GPR_GPR19)
Address: 3034_0000h base + 4Ch offset = 3034_004Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PCIE_DIAG_STATUS
W
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
• For reset: [31:0] - N/A
IOMUXC_GPR_GPR19 field descriptions
Field Description
PCIE_DIAG_ From PCIE
STATUS
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1336
W
R
W
R
Reset
Bit
Reset
Bit
28
29
30
31
GPR_RAWNAND_M_D_ GPR_APBHDMA_M_D_
0
0
15
31
Field
GPR_
GPR_
GPR_
GPR_
5_ARADDR32 4_HADDR32
APBHDMA_M_
APBHDMA_M_
AXI master.
D_4_HADDR33
D_4_HADDR32
A_0_ARADDR33
A_0_ARADDR32
GPR_RAWNAND_M_D_ GPR_APBHDMA_M_D_
CORESIGHT_M_
CORESIGHT_M_
0
0
14
30
5_ARADDR33 4_HADDR33
GPR_RAWNAND_M_D_ GPR_CORESIGHT_M_A_
0
0
13
29
5_AWADDR32 0_ARADDR32
IOMUX Controller (IOMUXC)
GPR_RAWNAND_M_D_ GPR_CORESIGHT_M_A_
0
0
12
28
5_AWADDR33 0_ARADDR33
GPR_USDHC1_M_D_6_ GPR_CORESIGHT_M_A_
0
0
11
27
ARADDR32 0_AWADDR32
HADDR bit 33 of apbhdma
HADDR bit 32 of apbhdma
GPR_USDHC1_M_D_6_ GPR_CORESIGHT_M_A_
ARADDR bit 33 of CoreSight
ARADDR bit 32 of CoreSight
0
0
10
26
ARADDR33 0_AWADDR33
Address: 3034_0000h base + 50h offset = 3034_0050h
GPR_USDHC1_M_D_6_ GPR_DAP_M_D_0_
0
0
25
AWADDR32 HADDR32
GPR_USDHC1_M_D_6_ GPR_DAP_M_D_0_
0
0
24
AWADDR33 HADDR33
GPR_USDHC2_M_D_7_ GPR_ENET1_M_E_0_
7
0
0
23
ARADDR32 ARADDR32
GPR_USDHC2_M_D_7_ GPR_ENET1_M_E_0_
6
0
0
22
Description
ARADDR33 ARADDR33
Table continues on the next page...
GPR_USDHC2_M_D_7_ GPR_ENET1_M_E_0_
5
0
0
21
AWADDR32 AWADDR32
IOMUXC_GPR_GPR20 field descriptions
GPR_USDHC2_M_D_7_ GPR_ENET1_M_E_0_
4
0
0
20
AWADDR33 AWADDR33
GPR_USDHC3_M_D_8_ GPR_ENET1_M_E_1_
3
0
0
19
ARADDR32 ARADDR32
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
GPR_USDHC3_M_D_8_ GPR_ENET1_M_E_1_
2
0
0
18
ARADDR33 ARADDR33
8.2.3.21 General Purpose Register 20 (IOMUXC_GPR_GPR20)
GPR_USDHC3_M_D_8_ GPR_ENET1_M_E_1_
1
0
0
17
AWADDR32 AWADDR32
This chip supports 34-bit addresses. This register contains address bits [33:32] for each
GPR_USDHC3_M_D_8_ GPR_ENET1_M_E_1_
0
0
0
16
AWADDR33 AWADDR33
NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_GPR_GPR20 field descriptions (continued)
Field Description
27 AWADDR bit 32 of CoreSight
GPR_
CORESIGHT_M_
A_0_AWADDR32
26 AWADDR bit 33 of CoreSight
GPR_
CORESIGHT_M_
A_0_AWADDR33
25 AHB address bit 32 of DAP
GPR_DAP_M_
D_0_HADDR32
24 AHB address bit 33 of DAP
GPR_DAP_M_
D_0_HADDR33
23 AXI read in fabric m_e_0 address bit 32 of ENET1
GPR_ENET1_M_
E_0_ARADDR32
22 AXI read in fabric m_e_0 address bit 33 of ENET1
GPR_ENET1_M_
E_0_ARADDR33
21 AXI write in fabric m_e_0 address bit 32 of ENET1
GPR_ENET1_M_
E_0_AWADDR32
20 AXI write in fabric m_e_0 address bit 33 of ENET1
GPR_ENET1_M_
E_0_AWADDR33
19 AXI read in fabric m_e_1 address bit 32 of ENET1
GPR_ENET1_M_
E_1_ARADDR32
18 AXI read in fabric m_e_1 address bit 33 of ENET1
GPR_ENET1_M_
E_1_ARADDR33
17 AXI write in fabric m_e_1 address bit 32 of ENET1
GPR_ENET1_M_
E_1_AWADDR32
16 AXI write in fabric m_e_1 address bit 33 of ENET1
GPR_ENET1_M_
E_1_AWADDR33
15 AXI read address bit 32 of RAWNAND
GPR_
RAWNAND_M_
D_5_ARADDR32
14 AXI read address bit 33 of RAWNAND
GPR_
RAWNAND_M_
D_5_ARADDR33
13 AXI write address bit 32 of RAWNAND
GPR_
RAWNAND_M_
Table continues on the next page...
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IOMUX Controller (IOMUXC)
IOMUXC_GPR_GPR20 field descriptions (continued)
Field Description
D_5_
AWADDR32
12 AXI write address bit 33 of RAWNAND
GPR_
RAWNAND_M_
D_5_
AWADDR33
11 AXI read address bit 32 of USDHC1
GPR_USDHC1_
M_D_6_
ARADDR32
10 AXI read address bit 33 of USDHC1
GPR_USDHC1_
M_D_6_
ARADDR33
9 AXI write address bit 32 of USDHC1
GPR_USDHC1_
M_D_6_
AWADDR32
8 AXI write address bit 33 of USDHC1
GPR_USDHC1_
M_D_6_
AWADDR33
7 AXI read address bit 32 of USDHC2
GPR_USDHC2_
M_D_7_
ARADDR32
6 AXI read address bit 33 of USDHC2
GPR_USDHC2_
M_D_7_
ARADDR33
5 AXI write address bit 32 of USDHC2
GPR_USDHC2_
M_D_7_
AWADDR32
4 AXI write address bit 33 of USDHC2
GPR_USDHC2_
M_D_7_
AWADDR33
3 AXI read address bit 32 of USDHC3
GPR_USDHC3_
M_D_8_
ARADDR32
2 AXI read address bit 33 of USDHC3
GPR_USDHC3_
M_D_8_
ARADDR33
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_GPR_GPR20 field descriptions (continued)
Field Description
1 AXI write address bit 32 of USDHC3
GPR_USDHC3_
M_D_8_
AWADDR32
0 AXI write address bit 33 of USDHC3
GPR_USDHC3_
M_D_8_
AWADDR33
8.2.3.22 General Purpose Register 21 (IOMUXC_GPR_GPR21)
Address: 3034_0000h base + 54h offset = 3034_0054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
GPR_SDMA1_M_D_2_
GPR_SDMA1_M_D_2_
GPR_SDMA1_M_D_3_
GPR_SDMA1_M_D_3_
GPR_SDMA1_M_D_3_
GPR_SDMA1_M_D_3_
R
AWADDR32
AWADDR33
ARADDR32
ARADDR33
HADDR32
HADDR33
Reserved
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
• For reset: -
[31:26] - 0x0
-
[25:0] - N/A
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IOMUX Controller (IOMUXC)
IOMUXC_GPR_GPR21 field descriptions
Field Description
31 AHB address bit 32 of SDMA1
GPR_SDMA1_
M_D_2_
HADDR32
30 AHB address bit 33 of SDMA1
GPR_SDMA1_
M_D_2_
HADDR33
29 AXI read address bit 32 of SDMA1
GPR_SDMA1_
M_D_3_
ARADDR32
28 AXI read address bit 33 of SDMA1
GPR_SDMA1_
M_D_3_
ARADDR33
27 AXI write address bit 32 of SDMA1
GPR_SDMA1_
M_D_3_
AWADDR32
26 AXI write address bit 33 of SDMA1
GPR_SDMA1_
M_D_3_
AWADDR33
- This field is reserved.
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Chapter 8 Chip IO and Pinmux
8.2.3.23 General Purpose Register 22 (IOMUXC_GPR_GPR22)
Address: 3034_0000h base + 58h offset = 3034_0058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SJC_CHALLENGE_RESPONSE_AUTHENTICATION_FAIL
R
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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IOMUX Controller (IOMUXC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPR_M7_HCLK_AUTO_GATE_EN
R
GPR_M7_HCLK_GATE_EN
GPR_M7_CPUWAIT
Reserved
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
IOMUXC_GPR_GPR22 field descriptions
Field Description
31–17 This field is reserved.
-
16 SJC challenge response authentication fail
SJC_CHALLENGE_
RESPONSE_
AUTHENTICATION_
FAIL
15–4 This field is reserved.
-
3 Gate off CM7 hclk
GPR_M7_HCLK_
GATE_EN 0 gate on
1 gate off
2 Gate CM7 hclk automatically
GPR_M7_HCLK_
AUTO_GATE_EN 0 depends on the value of GPR_M7_HCLK_GATE_EN
1 ignore the value of GPR_M7_HCLK_GATE_EN
1 This field is reserved.
-
0 CM7 in wait mode
GPR_M7_CPUWAIT
0 do not let CM7 enter wait mode
1 let CM7 enter wait mode
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Chapter 8 Chip IO and Pinmux
8.2.3.24 General Purpose Register 23 (IOMUXC_GPR_GPR23)
Address: 3034_0000h base + 5Ch offset = 3034_005Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IOMUXC_GPR_GPR23 field descriptions
Field Description
- This field is reserved.
8.2.3.25 General Purpose Register 24 (IOMUXC_GPR_GPR24)
Address: 3034_0000h base + 60h offset = 3034_0060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reserved
Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
• For reset: -
[31:24] - N/A
-
[23:0] - 0x0
IOMUXC_GPR_GPR24 field descriptions
Field Description
- This field is reserved.
8.2.4 IOMUXC Memory Map/Register Definition
IOMUXC memory map
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control
3033_0014 32 R/W 0000_0000h 8.2.4.1/1413
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00)
SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control
3033_0018 32 R/W 0000_0000h 8.2.4.2/1414
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01)
Table continues on the next page...
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IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control
3033_001C 32 R/W 0000_0000h 8.2.4.3/1415
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02)
SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control
3033_0020 32 R/W 0000_0000h 8.2.4.4/1417
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03)
SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control
3033_0024 32 R/W 0000_0000h 8.2.4.5/1418
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04)
SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control
3033_0028 32 R/W 0000_0000h 8.2.4.6/1419
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05)
SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control
3033_002C 32 R/W 0000_0000h 8.2.4.7/1421
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06)
SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control
3033_0030 32 R/W 0000_0000h 8.2.4.8/1422
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07)
SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control
3033_0034 32 R/W 0000_0000h 8.2.4.9/1423
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08)
SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control 8.2.4.10/
3033_0038 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09) 1425
SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control 8.2.4.11/
3033_003C 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10) 1426
SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control 8.2.4.12/
3033_0040 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11) 1427
SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control 8.2.4.13/
3033_0044 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12) 1428
SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control 8.2.4.14/
3033_0048 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13) 1429
SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control 8.2.4.15/
3033_004C 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14) 1430
SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control 8.2.4.16/
3033_0050 32 R/W 0000_0000h
Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15) 1432
SW_MUX_CTL_PAD_ENET_MDC SW MUX Control 8.2.4.17/
3033_0054 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDC) 1433
SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control 8.2.4.18/
3033_0058 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO) 1434
SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control 8.2.4.19/
3033_005C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TD3) 1436
SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control 8.2.4.20/
3033_0060 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TD2) 1437
SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control 8.2.4.21/
3033_0064 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TD1) 1438
SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control 8.2.4.22/
3033_0068 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TD0) 1440
SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control 8.2.4.23/
3033_006C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL) 1441
SW_MUX_CTL_PAD_ENET_TXC SW MUX Control 8.2.4.24/
3033_0070 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TXC) 1442
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1344 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control 8.2.4.25/
3033_0074 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL) 1444
SW_MUX_CTL_PAD_ENET_RXC SW MUX Control 8.2.4.26/
3033_0078 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RXC) 1445
SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control 8.2.4.27/
3033_007C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RD0) 1446
SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control 8.2.4.28/
3033_0080 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RD1) 1448
SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control 8.2.4.29/
3033_0084 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RD2) 1449
SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control 8.2.4.30/
3033_0088 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RD3) 1450
SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register 8.2.4.31/
3033_008C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK) 1452
SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register 8.2.4.32/
3033_0090 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD) 1453
SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control 8.2.4.33/
3033_0094 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0) 1454
SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control 8.2.4.34/
3033_0098 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1) 1456
SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control 8.2.4.35/
3033_009C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2) 1457
SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control 8.2.4.36/
3033_00A0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3) 1458
SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control 8.2.4.37/
3033_00A4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4) 1460
SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control 8.2.4.38/
3033_00A8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5) 1461
SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control 8.2.4.39/
3033_00AC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6) 1462
SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control 8.2.4.40/
3033_00B0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7) 1464
SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control 8.2.4.41/
3033_00B4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B) 1465
SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control 8.2.4.42/
3033_00B8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE) 1466
SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control 8.2.4.43/
3033_00BC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B) 1468
SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register 8.2.4.44/
3033_00C0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK) 1469
SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register 8.2.4.45/
3033_00C4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD) 1470
SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control 8.2.4.46/
3033_00C8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0) 1471
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1345
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control 8.2.4.47/
3033_00CC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1) 1472
SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control 8.2.4.48/
3033_00D0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2) 1474
SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control 8.2.4.49/
3033_00D4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3) 1475
SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control 8.2.4.50/
3033_00D8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B) 1476
SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register 8.2.4.51/
3033_00DC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SD2_WP) 1477
SW_MUX_CTL_PAD_NAND_ALE SW MUX Control 8.2.4.52/
3033_00E0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_ALE) 1478
SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control 8.2.4.53/
3033_00E4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B) 1480
SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control 8.2.4.54/
3033_00E8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B) 1481
SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control 8.2.4.55/
3033_00EC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B) 1483
SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control 8.2.4.56/
3033_00F0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B) 1484
SW_MUX_CTL_PAD_NAND_CLE SW MUX Control 8.2.4.57/
3033_00F4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE) 1485
SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control 8.2.4.58/
3033_00F8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00) 1487
SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control 8.2.4.59/
3033_00FC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01) 1488
SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control 8.2.4.60/
3033_0100 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02) 1490
SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control 8.2.4.61/
3033_0104 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03) 1491
SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control 8.2.4.62/
3033_0108 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04) 1492
SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control 8.2.4.63/
3033_010C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05) 1494
SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control 8.2.4.64/
3033_0110 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06) 1495
SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control 8.2.4.65/
3033_0114 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07) 1497
SW_MUX_CTL_PAD_NAND_DQS SW MUX Control 8.2.4.66/
3033_0118 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DQS) 1498
SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control 8.2.4.67/
3033_011C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B) 1500
SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control
8.2.4.68/
3033_0120 Register 32 R/W 0000_0005h
1501
(IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1346 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control 8.2.4.69/
3033_0124 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B) 1502
SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control 8.2.4.70/
3033_0128 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B) 1504
SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control 8.2.4.71/
3033_012C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS) 1505
SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register 8.2.4.72/
3033_0130 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC) 1506
SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control 8.2.4.73/
3033_0134 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0) 1508
SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control 8.2.4.74/
3033_0138 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1) 1509
SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control 8.2.4.75/
3033_013C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2) 1511
SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control 8.2.4.76/
3033_0140 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3) 1512
SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control 8.2.4.77/
3033_0144 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK) 1514
SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control 8.2.4.78/
3033_0148 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS) 1515
SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register 8.2.4.79/
3033_014C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC) 1516
SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control 8.2.4.80/
3033_0150 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0) 1518
SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control 8.2.4.81/
3033_0154 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1) 1519
SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control 8.2.4.82/
3033_0158 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2) 1520
SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control 8.2.4.83/
3033_015C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3) 1522
SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control 8.2.4.84/
3033_0160 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4) 1523
SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control 8.2.4.85/
3033_0164 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5) 1524
SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control 8.2.4.86/
3033_0168 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6) 1526
SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control 8.2.4.87/
3033_016C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7) 1527
SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control 8.2.4.88/
3033_0170 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS) 1528
SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register 8.2.4.89/
3033_0174 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC) 1530
SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control 8.2.4.90/
3033_0178 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0) 1531
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1347
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control 8.2.4.91/
3033_017C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1) 1532
SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control 8.2.4.92/
3033_0180 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2) 1533
SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control 8.2.4.93/
3033_0184 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3) 1535
SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control 8.2.4.94/
3033_0188 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4) 1536
SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control 8.2.4.95/
3033_018C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5) 1537
SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control 8.2.4.96/
3033_0190 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6) 1539
SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control 8.2.4.97/
3033_0194 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7) 1540
SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control 8.2.4.98/
3033_0198 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK) 1541
SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control 8.2.4.99/
3033_019C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS) 1543
SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register 8.2.4.100/
3033_01A0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC) 1544
SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control 8.2.4.101/
3033_01A4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0) 1546
SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control 8.2.4.102/
3033_01A8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS) 1547
SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register 8.2.4.103/
3033_01AC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC) 1549
SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control 8.2.4.104/
3033_01B0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0) 1550
SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control 8.2.4.105/
3033_01B4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK) 1551
SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control 8.2.4.106/
3033_01B8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS) 1553
SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register 8.2.4.107/
3033_01BC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC) 1554
SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register 8.2.4.108/
3033_01C0 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD) 1556
SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control 8.2.4.109/
3033_01C4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS) 1557
SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register 8.2.4.110/
3033_01C8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC) 1559
SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register 8.2.4.111/
3033_01CC 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD) 1560
SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control 8.2.4.112/
3033_01D0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK) 1562
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1348 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register 8.2.4.113/
3033_01D4 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX) 1563
SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register 8.2.4.114/
3033_01D8 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX) 1564
SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control
8.2.4.115/
3033_01DC Register 32 R/W 0000_0005h
1566
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK)
SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control 8.2.4.116/
3033_01E0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK) 1567
SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control 8.2.4.117/
3033_01E4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI) 1568
SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control 8.2.4.118/
3033_01E8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO) 1570
SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control 8.2.4.119/
3033_01EC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0) 1571
SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control 8.2.4.120/
3033_01F0 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK) 1572
SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control 8.2.4.121/
3033_01F4 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI) 1574
SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control 8.2.4.122/
3033_01F8 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO) 1575
SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control 8.2.4.123/
3033_01FC 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0) 1576
SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register 8.2.4.124/
3033_0200 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL) 1578
SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register 8.2.4.125/
3033_0204 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA) 1579
SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register 8.2.4.126/
3033_0208 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL) 1580
SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register 8.2.4.127/
3033_020C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA) 1581
SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register 8.2.4.128/
3033_0210 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL) 1583
SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register 8.2.4.129/
3033_0214 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA) 1584
SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register 8.2.4.130/
3033_0218 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL) 1585
SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register 8.2.4.131/
3033_021C 32 R/W 0000_0005h
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA) 1586
SW_MUX_CTL_PAD_UART1_RXD SW MUX Control 8.2.4.132/
3033_0220 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART1_RXD) 1587
SW_MUX_CTL_PAD_UART1_TXD SW MUX Control 8.2.4.133/
3033_0224 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART1_TXD) 1588
SW_MUX_CTL_PAD_UART2_RXD SW MUX Control 8.2.4.134/
3033_0228 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART2_RXD) 1589
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1349
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_MUX_CTL_PAD_UART2_TXD SW MUX Control 8.2.4.135/
3033_022C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART2_TXD) 1591
SW_MUX_CTL_PAD_UART3_RXD SW MUX Control 8.2.4.136/
3033_0230 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART3_RXD) 1592
SW_MUX_CTL_PAD_UART3_TXD SW MUX Control 8.2.4.137/
3033_0234 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART3_TXD) 1593
SW_MUX_CTL_PAD_UART4_RXD SW MUX Control 8.2.4.138/
3033_0238 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART4_RXD) 1595
SW_MUX_CTL_PAD_UART4_TXD SW MUX Control 8.2.4.139/
3033_023C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_UART4_TXD) 1596
SW_MUX_CTL_PAD_HDMI_DDC_SCL SW MUX Control
8.2.4.140/
3033_0240 Register 32 R/W 0000_0005h
1597
(IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SCL)
SW_MUX_CTL_PAD_HDMI_DDC_SDA SW MUX Control
8.2.4.141/
3033_0244 Register 32 R/W 0000_0005h
1599
(IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA)
SW_MUX_CTL_PAD_HDMI_CEC SW MUX Control 8.2.4.142/
3033_0248 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_HDMI_CEC) 1600
SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control 8.2.4.143/
3033_024C 32 R/W 0000_0005h
Register (IOMUXC_SW_MUX_CTL_PAD_HDMI_HPD) 1601
SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control 8.2.4.144/
3033_0250 32 R/W 0000_0194h
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0) 1602
SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control 8.2.4.145/
3033_0254 32 R/W 0000_0194h
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1) 1604
SW_PAD_CTL_PAD_BOOT_MODE2 SW PAD Control 8.2.4.146/
3033_0258 32 R/W 0000_0194h
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2) 1606
SW_PAD_CTL_PAD_BOOT_MODE3 SW PAD Control 8.2.4.147/
3033_025C 32 R/W 0000_0194h
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3) 1608
SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control 8.2.4.148/
3033_0260 32 R/W 0000_0114h
Register (IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD) 1610
SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register 8.2.4.149/
3033_0264 32 R/W 0000_0154h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI) 1612
SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register 8.2.4.150/
3033_0268 32 R/W 0000_0154h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS) 1614
SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register 8.2.4.151/
3033_026C 32 R/W 0000_0154h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK) 1616
SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register 8.2.4.152/
3033_0270 32 R/W 0000_0154h
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO) 1618
SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control 8.2.4.153/
3033_0274 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00) 1620
SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control 8.2.4.154/
3033_0278 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01) 1622
SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control 8.2.4.155/
3033_027C 32 R/W 0000_0146h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02) 1624
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1350 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control 8.2.4.156/
3033_0280 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03) 1626
SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control 8.2.4.157/
3033_0284 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04) 1628
SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control 8.2.4.158/
3033_0288 32 R/W 0000_0146h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05) 1630
SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control 8.2.4.159/
3033_028C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06) 1632
SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control 8.2.4.160/
3033_0290 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07) 1634
SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control 8.2.4.161/
3033_0294 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08) 1636
SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control 8.2.4.162/
3033_0298 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09) 1638
SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control 8.2.4.163/
3033_029C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10) 1640
SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control 8.2.4.164/
3033_02A0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11) 1642
SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control 8.2.4.165/
3033_02A4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12) 1644
SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control 8.2.4.166/
3033_02A8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13) 1646
SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control 8.2.4.167/
3033_02AC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14) 1648
SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control 8.2.4.168/
3033_02B0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15) 1650
SW_PAD_CTL_PAD_ENET_MDC SW PAD Control 8.2.4.169/
3033_02B4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDC) 1652
SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control 8.2.4.170/
3033_02B8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO) 1654
SW_PAD_CTL_PAD_ENET_TD3 SW PAD Control Register 8.2.4.171/
3033_02BC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD3) 1656
SW_PAD_CTL_PAD_ENET_TD2 SW PAD Control Register 8.2.4.172/
3033_02C0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD2) 1658
SW_PAD_CTL_PAD_ENET_TD1 SW PAD Control Register 8.2.4.173/
3033_02C4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD1) 1660
SW_PAD_CTL_PAD_ENET_TD0 SW PAD Control Register 8.2.4.174/
3033_02C8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD0) 1662
SW_PAD_CTL_PAD_ENET_TX_CTL SW PAD Control 8.2.4.175/
3033_02CC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL) 1664
SW_PAD_CTL_PAD_ENET_TXC SW PAD Control Register 8.2.4.176/
3033_02D0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_TXC) 1666
SW_PAD_CTL_PAD_ENET_RX_CTL SW PAD Control 8.2.4.177/
3033_02D4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL) 1668
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1351
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_ENET_RXC SW PAD Control Register 8.2.4.178/
3033_02D8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RXC) 1670
SW_PAD_CTL_PAD_ENET_RD0 SW PAD Control Register 8.2.4.179/
3033_02DC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD0) 1672
SW_PAD_CTL_PAD_ENET_RD1 SW PAD Control Register 8.2.4.180/
3033_02E0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD1) 1674
SW_PAD_CTL_PAD_ENET_RD2 SW PAD Control Register 8.2.4.181/
3033_02E4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD2) 1676
SW_PAD_CTL_PAD_ENET_RD3 SW PAD Control Register 8.2.4.182/
3033_02E8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD3) 1678
SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register 8.2.4.183/
3033_02EC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD1_CLK) 1680
SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register 8.2.4.184/
3033_02F0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD1_CMD) 1682
SW_PAD_CTL_PAD_SD1_DATA0 SW PAD Control 8.2.4.185/
3033_02F4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) 1684
SW_PAD_CTL_PAD_SD1_DATA1 SW PAD Control 8.2.4.186/
3033_02F8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1) 1686
SW_PAD_CTL_PAD_SD1_DATA2 SW PAD Control 8.2.4.187/
3033_02FC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2) 1688
SW_PAD_CTL_PAD_SD1_DATA3 SW PAD Control 8.2.4.188/
3033_0300 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3) 1690
SW_PAD_CTL_PAD_SD1_DATA4 SW PAD Control 8.2.4.189/
3033_0304 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA4) 1692
SW_PAD_CTL_PAD_SD1_DATA5 SW PAD Control 8.2.4.190/
3033_0308 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA5) 1694
SW_PAD_CTL_PAD_SD1_DATA6 SW PAD Control 8.2.4.191/
3033_030C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA6) 1696
SW_PAD_CTL_PAD_SD1_DATA7 SW PAD Control 8.2.4.192/
3033_0310 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA7) 1698
SW_PAD_CTL_PAD_SD1_RESET_B SW PAD Control 8.2.4.193/
3033_0314 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B) 1700
SW_PAD_CTL_PAD_SD1_STROBE SW PAD Control 8.2.4.194/
3033_0318 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD1_STROBE) 1702
SW_PAD_CTL_PAD_SD2_CD_B SW PAD Control Register 8.2.4.195/
3033_031C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B) 1704
SW_PAD_CTL_PAD_SD2_CLK SW PAD Control Register 8.2.4.196/
3033_0320 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CLK) 1706
SW_PAD_CTL_PAD_SD2_CMD SW PAD Control Register 8.2.4.197/
3033_0324 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD2_CMD) 1708
SW_PAD_CTL_PAD_SD2_DATA0 SW PAD Control 8.2.4.198/
3033_0328 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0) 1710
SW_PAD_CTL_PAD_SD2_DATA1 SW PAD Control 8.2.4.199/
3033_032C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1) 1712
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1352 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_SD2_DATA2 SW PAD Control 8.2.4.200/
3033_0330 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2) 1714
SW_PAD_CTL_PAD_SD2_DATA3 SW PAD Control 8.2.4.201/
3033_0334 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3) 1716
SW_PAD_CTL_PAD_SD2_RESET_B SW PAD Control 8.2.4.202/
3033_0338 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B) 1718
SW_PAD_CTL_PAD_SD2_WP SW PAD Control Register 8.2.4.203/
3033_033C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SD2_WP) 1720
SW_PAD_CTL_PAD_NAND_ALE SW PAD Control Register 8.2.4.204/
3033_0340 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_NAND_ALE) 1722
SW_PAD_CTL_PAD_NAND_CE0_B SW PAD Control 8.2.4.205/
3033_0344 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B) 1724
SW_PAD_CTL_PAD_NAND_CE1_B SW PAD Control 8.2.4.206/
3033_0348 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B) 1726
SW_PAD_CTL_PAD_NAND_CE2_B SW PAD Control 8.2.4.207/
3033_034C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B) 1728
SW_PAD_CTL_PAD_NAND_CE3_B SW PAD Control 8.2.4.208/
3033_0350 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B) 1730
SW_PAD_CTL_PAD_NAND_CLE SW PAD Control Register 8.2.4.209/
3033_0354 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE) 1732
SW_PAD_CTL_PAD_NAND_DATA00 SW PAD Control 8.2.4.210/
3033_0358 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00) 1734
SW_PAD_CTL_PAD_NAND_DATA01 SW PAD Control 8.2.4.211/
3033_035C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01) 1736
SW_PAD_CTL_PAD_NAND_DATA02 SW PAD Control 8.2.4.212/
3033_0360 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02) 1738
SW_PAD_CTL_PAD_NAND_DATA03 SW PAD Control 8.2.4.213/
3033_0364 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03) 1740
SW_PAD_CTL_PAD_NAND_DATA04 SW PAD Control 8.2.4.214/
3033_0368 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04) 1742
SW_PAD_CTL_PAD_NAND_DATA05 SW PAD Control 8.2.4.215/
3033_036C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05) 1744
SW_PAD_CTL_PAD_NAND_DATA06 SW PAD Control 8.2.4.216/
3033_0370 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06) 1746
SW_PAD_CTL_PAD_NAND_DATA07 SW PAD Control 8.2.4.217/
3033_0374 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07) 1748
SW_PAD_CTL_PAD_NAND_DQS SW PAD Control 8.2.4.218/
3033_0378 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DQS) 1750
SW_PAD_CTL_PAD_NAND_RE_B SW PAD Control 8.2.4.219/
3033_037C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B) 1752
SW_PAD_CTL_PAD_NAND_READY_B SW PAD Control
8.2.4.220/
3033_0380 Register 32 R/W 0000_0106h
1754
(IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B)
SW_PAD_CTL_PAD_NAND_WE_B SW PAD Control 8.2.4.221/
3033_0384 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B) 1756
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1353
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_NAND_WP_B SW PAD Control 8.2.4.222/
3033_0388 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B) 1758
SW_PAD_CTL_PAD_SAI5_RXFS SW PAD Control 8.2.4.223/
3033_038C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS) 1760
SW_PAD_CTL_PAD_SAI5_RXC SW PAD Control Register 8.2.4.224/
3033_0390 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI5_RXC) 1762
SW_PAD_CTL_PAD_SAI5_RXD0 SW PAD Control 8.2.4.225/
3033_0394 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0) 1764
SW_PAD_CTL_PAD_SAI5_RXD1 SW PAD Control 8.2.4.226/
3033_0398 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1) 1766
SW_PAD_CTL_PAD_SAI5_RXD2 SW PAD Control 8.2.4.227/
3033_039C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2) 1768
SW_PAD_CTL_PAD_SAI5_RXD3 SW PAD Control 8.2.4.228/
3033_03A0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3) 1770
SW_PAD_CTL_PAD_SAI5_MCLK SW PAD Control 8.2.4.229/
3033_03A4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK) 1772
SW_PAD_CTL_PAD_SAI1_RXFS SW PAD Control 8.2.4.230/
3033_03A8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS) 1774
SW_PAD_CTL_PAD_SAI1_RXC SW PAD Control Register 8.2.4.231/
3033_03AC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_RXC) 1776
SW_PAD_CTL_PAD_SAI1_RXD0 SW PAD Control 8.2.4.232/
3033_03B0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0) 1778
SW_PAD_CTL_PAD_SAI1_RXD1 SW PAD Control 8.2.4.233/
3033_03B4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1) 1780
SW_PAD_CTL_PAD_SAI1_RXD2 SW PAD Control 8.2.4.234/
3033_03B8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2) 1782
SW_PAD_CTL_PAD_SAI1_RXD3 SW PAD Control 8.2.4.235/
3033_03BC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3) 1784
SW_PAD_CTL_PAD_SAI1_RXD4 SW PAD Control 8.2.4.236/
3033_03C0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4) 1786
SW_PAD_CTL_PAD_SAI1_RXD5 SW PAD Control 8.2.4.237/
3033_03C4 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5) 1788
SW_PAD_CTL_PAD_SAI1_RXD6 SW PAD Control 8.2.4.238/
3033_03C8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6) 1790
SW_PAD_CTL_PAD_SAI1_RXD7 SW PAD Control 8.2.4.239/
3033_03CC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7) 1792
SW_PAD_CTL_PAD_SAI1_TXFS SW PAD Control Register 8.2.4.240/
3033_03D0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS) 1794
SW_PAD_CTL_PAD_SAI1_TXC SW PAD Control Register 8.2.4.241/
3033_03D4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXC) 1796
SW_PAD_CTL_PAD_SAI1_TXD0 SW PAD Control Register 8.2.4.242/
3033_03D8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0) 1798
SW_PAD_CTL_PAD_SAI1_TXD1 SW PAD Control Register 8.2.4.243/
3033_03DC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1) 1800
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1354 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_SAI1_TXD2 SW PAD Control Register 8.2.4.244/
3033_03E0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2) 1802
SW_PAD_CTL_PAD_SAI1_TXD3 SW PAD Control Register 8.2.4.245/
3033_03E4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3) 1804
SW_PAD_CTL_PAD_SAI1_TXD4 SW PAD Control Register 8.2.4.246/
3033_03E8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4) 1806
SW_PAD_CTL_PAD_SAI1_TXD5 SW PAD Control Register 8.2.4.247/
3033_03EC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5) 1808
SW_PAD_CTL_PAD_SAI1_TXD6 SW PAD Control Register 8.2.4.248/
3033_03F0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6) 1810
SW_PAD_CTL_PAD_SAI1_TXD7 SW PAD Control Register 8.2.4.249/
3033_03F4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7) 1812
SW_PAD_CTL_PAD_SAI1_MCLK SW PAD Control 8.2.4.250/
3033_03F8 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK) 1814
SW_PAD_CTL_PAD_SAI2_RXFS SW PAD Control 8.2.4.251/
3033_03FC 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS) 1816
SW_PAD_CTL_PAD_SAI2_RXC SW PAD Control Register 8.2.4.252/
3033_0400 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_RXC) 1818
SW_PAD_CTL_PAD_SAI2_RXD0 SW PAD Control 8.2.4.253/
3033_0404 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0) 1820
SW_PAD_CTL_PAD_SAI2_TXFS SW PAD Control Register 8.2.4.254/
3033_0408 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS) 1822
SW_PAD_CTL_PAD_SAI2_TXC SW PAD Control Register 8.2.4.255/
3033_040C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXC) 1824
SW_PAD_CTL_PAD_SAI2_TXD0 SW PAD Control Register 8.2.4.256/
3033_0410 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0) 1826
SW_PAD_CTL_PAD_SAI2_MCLK SW PAD Control 8.2.4.257/
3033_0414 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK) 1828
SW_PAD_CTL_PAD_SAI3_RXFS SW PAD Control 8.2.4.258/
3033_0418 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS) 1830
SW_PAD_CTL_PAD_SAI3_RXC SW PAD Control Register 8.2.4.259/
3033_041C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_RXC) 1832
SW_PAD_CTL_PAD_SAI3_RXD SW PAD Control Register 8.2.4.260/
3033_0420 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_RXD) 1834
SW_PAD_CTL_PAD_SAI3_TXFS SW PAD Control Register 8.2.4.261/
3033_0424 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS) 1836
SW_PAD_CTL_PAD_SAI3_TXC SW PAD Control Register 8.2.4.262/
3033_0428 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXC) 1838
SW_PAD_CTL_PAD_SAI3_TXD SW PAD Control Register 8.2.4.263/
3033_042C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SAI3_TXD) 1840
SW_PAD_CTL_PAD_SAI3_MCLK SW PAD Control 8.2.4.264/
3033_0430 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK) 1842
SW_PAD_CTL_PAD_SPDIF_TX SW PAD Control Register 8.2.4.265/
3033_0434 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_TX) 1844
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1355
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_SPDIF_RX SW PAD Control Register 8.2.4.266/
3033_0438 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_RX) 1846
SW_PAD_CTL_PAD_SPDIF_EXT_CLK SW PAD Control
8.2.4.267/
3033_043C Register 32 R/W 0000_0106h
1848
(IOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK)
SW_PAD_CTL_PAD_ECSPI1_SCLK SW PAD Control 8.2.4.268/
3033_0440 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK) 1850
SW_PAD_CTL_PAD_ECSPI1_MOSI SW PAD Control 8.2.4.269/
3033_0444 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI) 1852
SW_PAD_CTL_PAD_ECSPI1_MISO SW PAD Control 8.2.4.270/
3033_0448 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO) 1854
SW_PAD_CTL_PAD_ECSPI1_SS0 SW PAD Control 8.2.4.271/
3033_044C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0) 1856
SW_PAD_CTL_PAD_ECSPI2_SCLK SW PAD Control 8.2.4.272/
3033_0450 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK) 1858
SW_PAD_CTL_PAD_ECSPI2_MOSI SW PAD Control 8.2.4.273/
3033_0454 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI) 1860
SW_PAD_CTL_PAD_ECSPI2_MISO SW PAD Control 8.2.4.274/
3033_0458 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO) 1862
SW_PAD_CTL_PAD_ECSPI2_SS0 SW PAD Control 8.2.4.275/
3033_045C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0) 1864
SW_PAD_CTL_PAD_I2C1_SCL SW PAD Control Register 8.2.4.276/
3033_0460 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL) 1866
SW_PAD_CTL_PAD_I2C1_SDA SW PAD Control Register 8.2.4.277/
3033_0464 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA) 1868
SW_PAD_CTL_PAD_I2C2_SCL SW PAD Control Register 8.2.4.278/
3033_0468 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL) 1870
SW_PAD_CTL_PAD_I2C2_SDA SW PAD Control Register 8.2.4.279/
3033_046C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA) 1872
SW_PAD_CTL_PAD_I2C3_SCL SW PAD Control Register 8.2.4.280/
3033_0470 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL) 1874
SW_PAD_CTL_PAD_I2C3_SDA SW PAD Control Register 8.2.4.281/
3033_0474 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA) 1876
SW_PAD_CTL_PAD_I2C4_SCL SW PAD Control Register 8.2.4.282/
3033_0478 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL) 1878
SW_PAD_CTL_PAD_I2C4_SDA SW PAD Control Register 8.2.4.283/
3033_047C 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA) 1880
SW_PAD_CTL_PAD_UART1_RXD SW PAD Control 8.2.4.284/
3033_0480 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART1_RXD) 1882
SW_PAD_CTL_PAD_UART1_TXD SW PAD Control 8.2.4.285/
3033_0484 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART1_TXD) 1884
SW_PAD_CTL_PAD_UART2_RXD SW PAD Control 8.2.4.286/
3033_0488 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART2_RXD) 1886
SW_PAD_CTL_PAD_UART2_TXD SW PAD Control 8.2.4.287/
3033_048C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART2_TXD) 1888
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1356 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
SW_PAD_CTL_PAD_UART3_RXD SW PAD Control 8.2.4.288/
3033_0490 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART3_RXD) 1890
SW_PAD_CTL_PAD_UART3_TXD SW PAD Control 8.2.4.289/
3033_0494 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART3_TXD) 1892
SW_PAD_CTL_PAD_UART4_RXD SW PAD Control 8.2.4.290/
3033_0498 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART4_RXD) 1894
SW_PAD_CTL_PAD_UART4_TXD SW PAD Control 8.2.4.291/
3033_049C 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_UART4_TXD) 1896
SW_PAD_CTL_PAD_HDMI_DDC_SCL SW PAD Control 8.2.4.292/
3033_04A0 32 R/W 0000_0106h
Register (IOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SCL) 1898
SW_PAD_CTL_PAD_HDMI_DDC_SDA SW PAD Control
8.2.4.293/
3033_04A4 Register 32 R/W 0000_0106h
1900
(IOMUXC_SW_PAD_CTL_PAD_HDMI_DDC_SDA)
SW_PAD_CTL_PAD_HDMI_CEC SW PAD Control Register 8.2.4.294/
3033_04A8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_HDMI_CEC) 1902
SW_PAD_CTL_PAD_HDMI_HPD SW PAD Control Register 8.2.4.295/
3033_04AC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_HDMI_HPD) 1904
SW_PAD_CTL_PAD_CLKIN1 SW PAD Control Register 8.2.4.296/
3033_04B0 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_CLKIN1) 1906
SW_PAD_CTL_PAD_CLKIN2 SW PAD Control Register 8.2.4.297/
3033_04B4 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_CLKIN2) 1908
SW_PAD_CTL_PAD_CLKOUT1 SW PAD Control Register 8.2.4.298/
3033_04B8 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_CLKOUT1) 1910
SW_PAD_CTL_PAD_CLKOUT2 SW PAD Control Register 8.2.4.299/
3033_04BC 32 R/W 0000_0106h
(IOMUXC_SW_PAD_CTL_PAD_CLKOUT2) 1912
AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPU
T_0 DAISY Register 8.2.4.300/
3033_04C0 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SEL 1913
ECT_INPUT_0)
AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPU
T_1 DAISY Register 8.2.4.301/
3033_04C4 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SEL 1914
ECT_INPUT_1)
AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPU
T_2 DAISY Register 8.2.4.302/
3033_04C8 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SEL 1915
ECT_INPUT_2)
AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SELECT_INPU
T_3 DAISY Register 8.2.4.303/
3033_04CC 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_PDM_MIC_PDM_BITSTREAM_SEL 1915
ECT_INPUT_3)
AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT DAISY
8.2.4.304/
3033_04D0 Register 32 R/W 0000_0000h
1916
(IOMUXC_AUDIOMIX_SAI1_RXSYNC_SELECT_INPUT)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1357
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT DAISY
8.2.4.305/
3033_04D4 Register 32 R/W 0000_0000h
1917
(IOMUXC_AUDIOMIX_SAI1_TXBCLK_SELECT_INPUT)
AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT DAISY
8.2.4.306/
3033_04D8 Register 32 R/W 0000_0000h
1917
(IOMUXC_AUDIOMIX_SAI1_TXSYNC_SELECT_INPUT)
AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1 DAISY
8.2.4.307/
3033_04DC Register 32 R/W 0000_0000h
1918
(IOMUXC_AUDIOMIX_SAI2_RXDATA_SELECT_INPUT_1)
AUDIOMIX_SAI3_MCLK_SELECT_INPUT DAISY Register 8.2.4.308/
3033_04E0 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_SAI3_MCLK_SELECT_INPUT) 1919
AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0 DAISY
8.2.4.309/
3033_04E4 Register 32 R/W 0000_0000h
1920
(IOMUXC_AUDIOMIX_SAI3_RXDATA_SELECT_INPUT_0)
AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT DAISY
8.2.4.310/
3033_04E8 Register 32 R/W 0000_0000h
1921
(IOMUXC_AUDIOMIX_SAI3_TXBCLK_SELECT_INPUT)
AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT DAISY
8.2.4.311/
3033_04EC Register 32 R/W 0000_0000h
1922
(IOMUXC_AUDIOMIX_SAI3_TXSYNC_SELECT_INPUT)
AUDIOMIX_SAI5_MCLK_SELECT_INPUT DAISY Register 8.2.4.312/
3033_04F0 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_SAI5_MCLK_SELECT_INPUT) 1922
AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT DAISY
8.2.4.313/
3033_04F4 Register 32 R/W 0000_0000h
1923
(IOMUXC_AUDIOMIX_SAI5_RXBCLK_SELECT_INPUT)
AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0 DAISY
8.2.4.314/
3033_04F8 Register 32 R/W 0000_0000h
1924
(IOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_0)
AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1 DAISY
8.2.4.315/
3033_04FC Register 32 R/W 0000_0000h
1924
(IOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_1)
AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2 DAISY
8.2.4.316/
3033_0500 Register 32 R/W 0000_0000h
1925
(IOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_2)
AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3 DAISY
8.2.4.317/
3033_0504 Register 32 R/W 0000_0000h
1926
(IOMUXC_AUDIOMIX_SAI5_RXDATA_SELECT_INPUT_3)
AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT DAISY
8.2.4.318/
3033_0508 Register 32 R/W 0000_0000h
1926
(IOMUXC_AUDIOMIX_SAI5_RXSYNC_SELECT_INPUT)
AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT DAISY
8.2.4.319/
3033_050C Register 32 R/W 0000_0000h
1927
(IOMUXC_AUDIOMIX_SAI5_TXBCLK_SELECT_INPUT)
AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT DAISY
8.2.4.320/
3033_0510 Register 32 R/W 0000_0000h
1928
(IOMUXC_AUDIOMIX_SAI5_TXSYNC_SELECT_INPUT)
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1358 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
AUDIOMIX_SAI6_MCLK_SELECT_INPUT DAISY Register 8.2.4.321/
3033_0514 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_SAI6_MCLK_SELECT_INPUT) 1928
AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT DAISY
8.2.4.322/
3033_0518 Register 32 R/W 0000_0000h
1929
(IOMUXC_AUDIOMIX_SAI6_RXBCLK_SELECT_INPUT)
AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0 DAISY
8.2.4.323/
3033_051C Register 32 R/W 0000_0000h
1930
(IOMUXC_AUDIOMIX_SAI6_RXDATA_SELECT_INPUT_0)
AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT DAISY
8.2.4.324/
3033_0520 Register 32 R/W 0000_0000h
1930
(IOMUXC_AUDIOMIX_SAI6_RXSYNC_SELECT_INPUT)
AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT DAISY
8.2.4.325/
3033_0524 Register 32 R/W 0000_0000h
1931
(IOMUXC_AUDIOMIX_SAI6_TXBCLK_SELECT_INPUT)
AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT DAISY
8.2.4.326/
3033_0528 Register 32 R/W 0000_0000h
1932
(IOMUXC_AUDIOMIX_SAI6_TXSYNC_SELECT_INPUT)
AUDIOMIX_SAI7_MCLK_SELECT_INPUT DAISY Register 8.2.4.327/
3033_052C 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_SAI7_MCLK_SELECT_INPUT) 1933
AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT DAISY
8.2.4.328/
3033_0530 Register 32 R/W 0000_0000h
1934
(IOMUXC_AUDIOMIX_SAI7_RXBCLK_SELECT_INPUT)
AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0 DAISY
8.2.4.329/
3033_0534 Register 32 R/W 0000_0000h
1935
(IOMUXC_AUDIOMIX_SAI7_RXDATA_SELECT_INPUT_0)
AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT DAISY
8.2.4.330/
3033_0538 Register 32 R/W 0000_0000h
1936
(IOMUXC_AUDIOMIX_SAI7_RXSYNC_SELECT_INPUT)
AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT DAISY
8.2.4.331/
3033_053C Register 32 R/W 0000_0000h
1937
(IOMUXC_AUDIOMIX_SAI7_TXBCLK_SELECT_INPUT)
AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT DAISY
8.2.4.332/
3033_0540 Register 32 R/W 0000_0000h
1938
(IOMUXC_AUDIOMIX_SAI7_TXSYNC_SELECT_INPUT)
AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_INPUT
DAISY Register 8.2.4.333/
3033_0544 32 R/W 0000_0000h
(IOMUXC_AUDIOMIX_EARC_PHY_SPDIF_IN_SELECT_IN 1938
PUT)
AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT DAISY
8.2.4.334/
3033_0548 Register 32 R/W 0000_0000h
1939
(IOMUXC_AUDIOMIX_SPDIF_EXTCLK_SELECT_INPUT)
CAN1_CANRX_SELECT_INPUT DAISY Register 8.2.4.335/
3033_054C 32 R/W 0000_0000h
(IOMUXC_CAN1_CANRX_SELECT_INPUT) 1940
CAN2_CANRX_SELECT_INPUT DAISY Register 8.2.4.336/
3033_0550 32 R/W 0000_0000h
(IOMUXC_CAN2_CANRX_SELECT_INPUT) 1940
CCM_GPC_PMIC_VFUNCTIONAL_READY_SELECT_INP 8.2.4.337/
3033_0554 32 R/W 0000_0000h
UT DAISY Register 1941
Table continues on the next page...
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NXP Semiconductors 1359
IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
(IOMUXC_CCM_GPC_PMIC_VFUNCTIONAL_READY_SE
LECT_INPUT)
ECSPI1_CSPI_CLK_IN_SELECT_INPUT DAISY Register 8.2.4.338/
3033_0558 32 R/W 0000_0000h
(IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT) 1942
ECSPI1_MISO_SELECT_INPUT DAISY Register 8.2.4.339/
3033_055C 32 R/W 0000_0000h
(IOMUXC_ECSPI1_MISO_SELECT_INPUT) 1943
ECSPI1_MOSI_SELECT_INPUT DAISY Register 8.2.4.340/
3033_0560 32 R/W 0000_0000h
(IOMUXC_ECSPI1_MOSI_SELECT_INPUT) 1944
ECSPI1_SS_B_SELECT_INPUT_0 DAISY Register 8.2.4.341/
3033_0564 32 R/W 0000_0000h
(IOMUXC_ECSPI1_SS_B_SELECT_INPUT_0) 1945
ECSPI2_CSPI_CLK_IN_SELECT_INPUT DAISY Register 8.2.4.342/
3033_0568 32 R/W 0000_0000h
(IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT) 1945
ECSPI2_MISO_SELECT_INPUT DAISY Register 8.2.4.343/
3033_056C 32 R/W 0000_0000h
(IOMUXC_ECSPI2_MISO_SELECT_INPUT) 1946
ECSPI2_MOSI_SELECT_INPUT DAISY Register 8.2.4.344/
3033_0570 32 R/W 0000_0000h
(IOMUXC_ECSPI2_MOSI_SELECT_INPUT) 1947
ECSPI2_SS_B_SELECT_INPUT_0 DAISY Register 8.2.4.345/
3033_0574 32 R/W 0000_0000h
(IOMUXC_ECSPI2_SS_B_SELECT_INPUT_0) 1947
ENET1_IPG_CLK_RMII_SELECT_INPUT DAISY Register 8.2.4.346/
3033_0578 32 R/W 0000_0000h
(IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT) 1948
ENET1_MDIO_SELECT_INPUT DAISY Register 8.2.4.347/
3033_057C 32 R/W 0000_0000h
(IOMUXC_ENET1_MDIO_SELECT_INPUT) 1949
ENET1_RXDATA_0_SELECT_INPUT DAISY Register 8.2.4.348/
3033_0580 32 R/W 0000_0000h
(IOMUXC_ENET1_RXDATA_0_SELECT_INPUT) 1950
ENET1_RXDATA_1_SELECT_INPUT DAISY Register 8.2.4.349/
3033_0584 32 R/W 0000_0000h
(IOMUXC_ENET1_RXDATA_1_SELECT_INPUT) 1951
ENET1_RXEN_SELECT_INPUT DAISY Register 8.2.4.350/
3033_0588 32 R/W 0000_0000h
(IOMUXC_ENET1_RXEN_SELECT_INPUT) 1952
ENET1_RXERR_SELECT_INPUT DAISY Register 8.2.4.351/
3033_058C 32 R/W 0000_0000h
(IOMUXC_ENET1_RXERR_SELECT_INPUT) 1953
ENET_QOS_GMII_MDI_I_SELECT_INPUT DAISY Register 8.2.4.352/
3033_0590 32 R/W 0000_0000h
(IOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT) 1953
GPT1_CAPIN1_SELECT_INPUT DAISY Register 8.2.4.353/
3033_0594 32 R/W 0000_0000h
(IOMUXC_GPT1_CAPIN1_SELECT_INPUT) 1954
GPT1_CAPIN2_SELECT_INPUT DAISY Register 8.2.4.354/
3033_0598 32 R/W 0000_0000h
(IOMUXC_GPT1_CAPIN2_SELECT_INPUT) 1955
GPT1_CLKIN_SELECT_INPUT DAISY Register 8.2.4.355/
3033_059C 32 R/W 0000_0000h
(IOMUXC_GPT1_CLKIN_SELECT_INPUT) 1956
PCIE_CLKREQ_B_SELECT_INPUT DAISY Register 8.2.4.356/
3033_05A0 32 R/W 0000_0000h
(IOMUXC_PCIE_CLKREQ_B_SELECT_INPUT) 1957
I2C1_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.357/
3033_05A4 32 R/W 0000_0000h
(IOMUXC_I2C1_SCL_IN_SELECT_INPUT) 1957
I2C1_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.358/
3033_05A8 32 R/W 0000_0000h
(IOMUXC_I2C1_SDA_IN_SELECT_INPUT) 1958
Table continues on the next page...
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1360 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
I2C2_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.359/
3033_05AC 32 R/W 0000_0000h
(IOMUXC_I2C2_SCL_IN_SELECT_INPUT) 1959
I2C2_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.360/
3033_05B0 32 R/W 0000_0000h
(IOMUXC_I2C2_SDA_IN_SELECT_INPUT) 1959
I2C3_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.361/
3033_05B4 32 R/W 0000_0000h
(IOMUXC_I2C3_SCL_IN_SELECT_INPUT) 1960
I2C3_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.362/
3033_05B8 32 R/W 0000_0000h
(IOMUXC_I2C3_SDA_IN_SELECT_INPUT) 1961
I2C4_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.363/
3033_05BC 32 R/W 0000_0000h
(IOMUXC_I2C4_SCL_IN_SELECT_INPUT) 1961
I2C4_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.364/
3033_05C0 32 R/W 0000_0000h
(IOMUXC_I2C4_SDA_IN_SELECT_INPUT) 1962
I2C5_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.365/
3033_05C4 32 R/W 0000_0000h
(IOMUXC_I2C5_SCL_IN_SELECT_INPUT) 1963
I2C5_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.366/
3033_05C8 32 R/W 0000_0000h
(IOMUXC_I2C5_SDA_IN_SELECT_INPUT) 1963
I2C6_SCL_IN_SELECT_INPUT DAISY Register 8.2.4.367/
3033_05CC 32 R/W 0000_0000h
(IOMUXC_I2C6_SCL_IN_SELECT_INPUT) 1964
I2C6_SDA_IN_SELECT_INPUT DAISY Register 8.2.4.368/
3033_05D0 32 R/W 0000_0000h
(IOMUXC_I2C6_SDA_IN_SELECT_INPUT) 1965
ISP_FL_TRIG_0_SELECT_INPUT DAISY Register 8.2.4.369/
3033_05D4 32 R/W 0000_0000h
(IOMUXC_ISP_FL_TRIG_0_SELECT_INPUT) 1966
ISP_FL_TRIG_1_SELECT_INPUT DAISY Register 8.2.4.370/
3033_05D8 32 R/W 0000_0000h
(IOMUXC_ISP_FL_TRIG_1_SELECT_INPUT) 1967
ISP_SHUTTER_TRIG_0_SELECT_INPUT DAISY Register 8.2.4.371/
3033_05DC 32 R/W 0000_0000h
(IOMUXC_ISP_SHUTTER_TRIG_0_SELECT_INPUT) 1968
ISP_SHUTTER_TRIG_1_SELECT_INPUT DAISY Register 8.2.4.372/
3033_05E0 32 R/W 0000_0000h
(IOMUXC_ISP_SHUTTER_TRIG_1_SELECT_INPUT) 1969
UART1_UART_RTS_B_SELECT_INPUT DAISY Register 8.2.4.373/
3033_05E4 32 R/W 0000_0000h
(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT) 1969
UART1_UART_RXD_MUX_SELECT_INPUT DAISY
8.2.4.374/
3033_05E8 Register 32 R/W 0000_0000h
1970
(IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT)
UART2_UART_RTS_B_SELECT_INPUT DAISY Register 8.2.4.375/
3033_05EC 32 R/W 0000_0000h
(IOMUXC_UART2_UART_RTS_B_SELECT_INPUT) 1971
UART2_UART_RXD_MUX_SELECT_INPUT DAISY
8.2.4.376/
3033_05F0 Register 32 R/W 0000_0000h
1971
(IOMUXC_UART2_UART_RXD_MUX_SELECT_INPUT)
UART3_UART_RTS_B_SELECT_INPUT DAISY Register 8.2.4.377/
3033_05F4 32 R/W 0000_0000h
(IOMUXC_UART3_UART_RTS_B_SELECT_INPUT) 1972
UART3_UART_RXD_MUX_SELECT_INPUT DAISY
8.2.4.378/
3033_05F8 Register 32 R/W 0000_0000h
1973
(IOMUXC_UART3_UART_RXD_MUX_SELECT_INPUT)
UART4_UART_RTS_B_SELECT_INPUT DAISY Register 8.2.4.379/
3033_05FC 32 R/W 0000_0000h
(IOMUXC_UART4_UART_RTS_B_SELECT_INPUT) 1973
Table continues on the next page...
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IOMUX Controller (IOMUXC)
IOMUXC memory map (continued)
Absolute
Width Section/
address Register name Access Reset value
(in bits) page
(hex)
UART4_UART_RXD_MUX_SELECT_INPUT DAISY
8.2.4.380/
3033_0600 Register 32 R/W 0000_0000h
1974
(IOMUXC_UART4_UART_RXD_MUX_SELECT_INPUT)
USDHC3_CARD_CLK_IN_SELECT_INPUT DAISY Register 8.2.4.381/
3033_0604 32 R/W 0000_0000h
(IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT) 1975
USDHC3_CARD_DET_SELECT_INPUT DAISY Register 8.2.4.382/
3033_0608 32 R/W 0000_0000h
(IOMUXC_USDHC3_CARD_DET_SELECT_INPUT) 1975
USDHC3_CMD_IN_SELECT_INPUT DAISY Register 8.2.4.383/
3033_060C 32 R/W 0000_0000h
(IOMUXC_USDHC3_CMD_IN_SELECT_INPUT) 1976
USDHC3_DAT0_IN_SELECT_INPUT DAISY Register 8.2.4.384/
3033_0610 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT0_IN_SELECT_INPUT) 1977
USDHC3_DAT1_IN_SELECT_INPUT DAISY Register 8.2.4.385/
3033_0614 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT1_IN_SELECT_INPUT) 1978
USDHC3_DAT2_IN_SELECT_INPUT DAISY Register 8.2.4.386/
3033_0618 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT2_IN_SELECT_INPUT) 1979
USDHC3_DAT3_IN_SELECT_INPUT DAISY Register 8.2.4.387/
3033_061C 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT3_IN_SELECT_INPUT) 1980
USDHC3_DAT4_IN_SELECT_INPUT DAISY Register 8.2.4.388/
3033_0620 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT4_IN_SELECT_INPUT) 1981
USDHC3_DAT5_IN_SELECT_INPUT DAISY Register 8.2.4.389/
3033_0624 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT5_IN_SELECT_INPUT) 1982
USDHC3_DAT6_IN_SELECT_INPUT DAISY Register 8.2.4.390/
3033_0628 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT6_IN_SELECT_INPUT) 1983
USDHC3_DAT7_IN_SELECT_INPUT DAISY Register 8.2.4.391/
3033_062C 32 R/W 0000_0000h
(IOMUXC_USDHC3_DAT7_IN_SELECT_INPUT) 1984
USDHC3_STROBE_SELECT_INPUT DAISY Register 8.2.4.392/
3033_0630 32 R/W 0000_0000h
(IOMUXC_USDHC3_STROBE_SELECT_INPUT) 1985
USDHC3_WP_ON_SELECT_INPUT DAISY Register 8.2.4.393/
3033_0634 32 R/W 0000_0000h
(IOMUXC_USDHC3_WP_ON_SELECT_INPUT) 1985
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Chapter 8 Chip IO and Pinmux
8.2.4.1 SW_MUX_CTL_PAD_GPIO1_IO00 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00)
SW_MUX_CTL Register
Address: 3033_0000h base + 14h offset = 3033_0014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO00
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO00.
000 ALT0_GPIO1_IO[0] — Select mux mode: ALT0 mux port: GPIO1_IO00 of instance: gpio1
001 ALT1_CCM_ENET_PHY_REF_CLK_ROOT — Select mux mode: ALT1 mux port:
CCM_ENET_PHY_REF_CLK_ROOT of instance: ccm
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 field descriptions (continued)
Field Description
011 ALT3_ISP_FL_TRIG_0 — Select mux mode: ALT3 mux port: ISP_FL_TRIG_0 of instance: isp
101 ALT5_REF_CLK_32K — Select mux mode: ALT5 mux port: REF_CLK_32K of instance: anamix
110 ALT6_CCM_EXT_CLK1 — Select mux mode: ALT6 mux port: CCM_EXT_CLK1 of instance: ccm
8.2.4.2 SW_MUX_CTL_PAD_GPIO1_IO01 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01)
SW_MUX_CTL Register
Address: 3033_0000h base + 18h offset = 3033_0018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO01
0 DISABLED — Input Path is determined by functionality
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO01.
000 ALT0_GPIO1_IO[1] — Select mux mode: ALT0 mux port: GPIO1_IO01 of instance: gpio1
001 ALT1_PWM1_OUT — Select mux mode: ALT1 mux port: PWM1_OUT of instance: pwm1
011 ALT3_ISP_SHUTTER_TRIG_0 — Select mux mode: ALT3 mux port: ISP_SHUTTER_TRIG_0 of
instance: isp
101 ALT5_REF_CLK_24M — Select mux mode: ALT5 mux port: REF_CLK_24M of instance: anamix
110 ALT6_CCM_EXT_CLK2 — Select mux mode: ALT6 mux port: CCM_EXT_CLK2 of instance: ccm
8.2.4.3 SW_MUX_CTL_PAD_GPIO1_IO02 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02)
SW_MUX_CTL Register
Address: 3033_0000h base + 1Ch offset = 3033_001Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO02
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO02.
000 ALT0_GPIO1_IO[2] — Select mux mode: ALT0 mux port: GPIO1_IO02 of instance: gpio1
001 ALT1_WDOG1_WDOG_B — Select mux mode: ALT1 mux port: WDOG1_WDOG_B of instance:
wdog1
011 ALT3_ISP_FLASH_TRIG_0 — Select mux mode: ALT3 mux port: ISP_FLASH_TRIG_0 of
instance: isp
101 ALT5_WDOG1_WDOG_ANY — Select mux mode: ALT5 mux port: WDOG1_WDOG_ANY of
instance: wdog1
111 ALT7_SJC_DE_B — Select mux mode: ALT7 mux port: SJC_DE_B of instance: sjc
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Chapter 8 Chip IO and Pinmux
8.2.4.4 SW_MUX_CTL_PAD_GPIO1_IO03 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03)
SW_MUX_CTL Register
Address: 3033_0000h base + 20h offset = 3033_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO03
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO03.
000 ALT0_GPIO1_IO[3] — Select mux mode: ALT0 mux port: GPIO1_IO03 of instance: gpio1
001 ALT1_USDHC1_VSELECT — Select mux mode: ALT1 mux port: USDHC1_VSELECT of instance:
usdhc1
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 field descriptions (continued)
Field Description
011 ALT3_ISP_PRELIGHT_TRIG_0 — Select mux mode: ALT3 mux port: ISP_PRELIGHT_TRIG_0 of
instance: isp
101 ALT5_SDMA1_EXT_EVENT[0] — Select mux mode: ALT5 mux port: SDMA1_EXT_EVENT00 of
instance: sdma1
8.2.4.5 SW_MUX_CTL_PAD_GPIO1_IO04 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04)
SW_MUX_CTL Register
Address: 3033_0000h base + 24h offset = 3033_0024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO04
0 DISABLED — Input Path is determined by functionality
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO04.
000 ALT0_GPIO1_IO[4] — Select mux mode: ALT0 mux port: GPIO1_IO04 of instance: gpio1
001 ALT1_USDHC2_VSELECT — Select mux mode: ALT1 mux port: USDHC2_VSELECT of instance:
usdhc2
011 ALT3_ISP_SHUTTER_OPEN_0 — Select mux mode: ALT3 mux port: ISP_SHUTTER_OPEN_0 of
instance: isp
101 ALT5_SDMA1_EXT_EVENT[1] — Select mux mode: ALT5 mux port: SDMA1_EXT_EVENT01 of
instance: sdma1
8.2.4.6 SW_MUX_CTL_PAD_GPIO1_IO05 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05)
SW_MUX_CTL Register
Address: 3033_0000h base + 28h offset = 3033_0028h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO05
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO05.
000 ALT0_GPIO1_IO[5] — Select mux mode: ALT0 mux port: GPIO1_IO05 of instance: gpio1
001 ALT1_M7_NMI — Select mux mode: ALT1 mux port: M7_NMI of instance: m7
011 ALT3_ISP_FL_TRIG_1 — Select mux mode: ALT3 mux port: ISP_FL_TRIG_1 of instance: isp
101 ALT5_CCM_PMIC_READY — Select mux mode: ALT5 mux port: CCM_PMIC_READY of instance:
ccm
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Chapter 8 Chip IO and Pinmux
8.2.4.7 SW_MUX_CTL_PAD_GPIO1_IO06 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06)
SW_MUX_CTL Register
Address: 3033_0000h base + 2Ch offset = 3033_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO06
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO06.
000 ALT0_GPIO1_IO[6] — Select mux mode: ALT0 mux port: GPIO1_IO06 of instance: gpio1
001 ALT1_ENET_QOS_MDC — Select mux mode: ALT1 mux port: ENET_QOS_MDC of instance:
enet_qos
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 field descriptions (continued)
Field Description
011 ALT3_ISP_SHUTTER_TRIG_1 — Select mux mode: ALT3 mux port: ISP_SHUTTER_TRIG_1 of
instance: isp
101 ALT5_USDHC1_CD_B — Select mux mode: ALT5 mux port: USDHC1_CD_B of instance: usdhc1
110 ALT6_CCM_EXT_CLK3 — Select mux mode: ALT6 mux port: CCM_EXT_CLK3 of instance: ccm
8.2.4.8 SW_MUX_CTL_PAD_GPIO1_IO07 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07)
SW_MUX_CTL Register
Address: 3033_0000h base + 30h offset = 3033_0030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO07
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO07.
000 ALT0_GPIO1_IO[7] — Select mux mode: ALT0 mux port: GPIO1_IO07 of instance: gpio1
001 ALT1_ENET_QOS_MDIO — Select mux mode: ALT1 mux port: ENET_QOS_MDIO of instance:
enet_qos
011 ALT3_ISP_FLASH_TRIG_1 — Select mux mode: ALT3 mux port: ISP_FLASH_TRIG_1 of
instance: isp
101 ALT5_USDHC1_WP — Select mux mode: ALT5 mux port: USDHC1_WP of instance: usdhc1
110 ALT6_CCM_EXT_CLK4 — Select mux mode: ALT6 mux port: CCM_EXT_CLK4 of instance: ccm
8.2.4.9 SW_MUX_CTL_PAD_GPIO1_IO08 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08)
SW_MUX_CTL Register
Address: 3033_0000h base + 34h offset = 3033_0034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO08
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: GPIO1_IO08.
000 ALT0_GPIO1_IO[8] — Select mux mode: ALT0 mux port: GPIO1_IO08 of instance: gpio1
001 ALT1_ENET_QOS_1588_EVENT0_IN — Select mux mode: ALT1 mux port:
ENET_QOS_1588_EVENT0_IN of instance: enet_qos
010 ALT2_PWM1_OUT — Select mux mode: ALT2 mux port: PWM1_OUT of instance: pwm1
011 ALT3_ISP_PRELIGHT_TRIG_1 — Select mux mode: ALT3 mux port: ISP_PRELIGHT_TRIG_1 of
instance: isp
100 ALT4_ENET_QOS_1588_EVENT0_AUX_IN — Select mux mode: ALT4 mux port:
ENET_QOS_1588_EVENT0_AUX_IN of instance: enet_qos
101 ALT5_USDHC2_RESET_B — Select mux mode: ALT5 mux port: USDHC2_RESET_B of instance:
usdhc2
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8.2.4.10 SW_MUX_CTL_PAD_GPIO1_IO09 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09)
SW_MUX_CTL Register
Address: 3033_0000h base + 38h offset = 3033_0038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO09
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: GPIO1_IO09.
000 ALT0_GPIO1_IO[9] — Select mux mode: ALT0 mux port: GPIO1_IO09 of instance: gpio1
001 ALT1_ENET_QOS_1588_EVENT0_OUT — Select mux mode: ALT1 mux port:
ENET_QOS_1588_EVENT0_OUT of instance: enet_qos
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 field descriptions (continued)
Field Description
010 ALT2_PWM2_OUT — Select mux mode: ALT2 mux port: PWM2_OUT of instance: pwm2
011 ALT3_ISP_SHUTTER_OPEN_1 — Select mux mode: ALT3 mux port: ISP_SHUTTER_OPEN_1 of
instance: isp
100 ALT4_USDHC3_RESET_B — Select mux mode: ALT4 mux port: USDHC3_RESET_B of instance:
usdhc3
101 ALT5_SDMA2_EXT_EVENT[0] — Select mux mode: ALT5 mux port: SDMA2_EXT_EVENT00 of
instance: SDMA2
8.2.4.11 SW_MUX_CTL_PAD_GPIO1_IO10 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10)
SW_MUX_CTL Register
Address: 3033_0000h base + 3Ch offset = 3033_003Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad GPIO1_IO10
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: GPIO1_IO10.
000 ALT0_GPIO1_IO[10] — Select mux mode: ALT0 mux port: GPIO1_IO10 of instance: gpio1
010 ALT2_PWM3_OUT — Select mux mode: ALT2 mux port: PWM3_OUT of instance: pwm3
8.2.4.12 SW_MUX_CTL_PAD_GPIO1_IO11 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11)
SW_MUX_CTL Register
Address: 3033_0000h base + 40h offset = 3033_0040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO11
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: GPIO1_IO11.
000 ALT0_GPIO1_IO[11] — Select mux mode: ALT0 mux port: GPIO1_IO11 of instance: gpio1
010 ALT2_PWM2_OUT — Select mux mode: ALT2 mux port: PWM2_OUT of instance: pwm2
100 ALT4_USDHC3_VSELECT — Select mux mode: ALT4 mux port: USDHC3_VSELECT of instance:
usdhc3
101 ALT5_CCM_PMIC_READY — Select mux mode: ALT5 mux port: CCM_PMIC_READY of instance:
ccm
8.2.4.13 SW_MUX_CTL_PAD_GPIO1_IO12 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12)
SW_MUX_CTL Register
Address: 3033_0000h base + 44h offset = 3033_0044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO12
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO12.
000 ALT0_GPIO1_IO[12] — Select mux mode: ALT0 mux port: GPIO1_IO12 of instance: gpio1
001 ALT1_USB1_PWR — Select mux mode: ALT1 mux port: usb1_PWR of instance: usb1
101 ALT5_SDMA2_EXT_EVENT[1] — Select mux mode: ALT5 mux port: SDMA2_EXT_EVENT01 of
instance: SDMA2
8.2.4.14 SW_MUX_CTL_PAD_GPIO1_IO13 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13)
SW_MUX_CTL Register
Address: 3033_0000h base + 48h offset = 3033_0048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO13
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: GPIO1_IO13.
000 ALT0_GPIO1_IO[13] — Select mux mode: ALT0 mux port: GPIO1_IO13 of instance: gpio1
001 ALT1_USB1_OC — Select mux mode: ALT1 mux port: usb1_OC of instance: usb1
101 ALT5_PWM2_OUT — Select mux mode: ALT5 mux port: PWM2_OUT of instance: pwm2
8.2.4.15 SW_MUX_CTL_PAD_GPIO1_IO14 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14)
SW_MUX_CTL Register
Address: 3033_0000h base + 4Ch offset = 3033_004Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO14
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO14.
000 ALT0_GPIO1_IO[14] — Select mux mode: ALT0 mux port: GPIO1_IO14 of instance: gpio1
001 ALT1_USB2_PWR — Select mux mode: ALT1 mux port: usb2_PWR of instance: usb2
100 ALT4_USDHC3_CD_B — Select mux mode: ALT4 mux port: USDHC3_CD_B of instance: usdhc3
101 ALT5_PWM3_OUT — Select mux mode: ALT5 mux port: PWM3_OUT of instance: pwm3
110 ALT6_CCM_CLKO1 — Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm
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8.2.4.16 SW_MUX_CTL_PAD_GPIO1_IO15 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15)
SW_MUX_CTL Register
Address: 3033_0000h base + 50h offset = 3033_0050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad GPIO1_IO15
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: GPIO1_IO15.
000 ALT0_GPIO1_IO[15] — Select mux mode: ALT0 mux port: GPIO1_IO15 of instance: gpio1
001 ALT1_USB2_OC — Select mux mode: ALT1 mux port: usb2_OC of instance: usb2
100 ALT4_USDHC3_WP — Select mux mode: ALT4 mux port: USDHC3_WP of instance: usdhc3
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IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 field descriptions (continued)
Field Description
101 ALT5_PWM4_OUT — Select mux mode: ALT5 mux port: PWM4_OUT of instance: pwm4
110 ALT6_CCM_CLKO2 — Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm
8.2.4.17 SW_MUX_CTL_PAD_ENET_MDC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDC)
SW_MUX_CTL Register
Address: 3033_0000h base + 54h offset = 3033_0054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_MDC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_MDC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_ENET_MDC field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: ENET_MDC.
000 ALT0_ENET_QOS_MDC — Select mux mode: ALT0 mux port: ENET_QOS_MDC of instance:
enet_qos
010 ALT2_AUDIOMIX_SAI6_TX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_DATA00 of instance: sai6
101 ALT5_GPIO1_IO[16] — Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1
110 ALT6_USDHC3_STROBE — Select mux mode: ALT6 mux port: USDHC3_STROBE of instance:
usdhc3
8.2.4.18 SW_MUX_CTL_PAD_ENET_MDIO SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO)
SW_MUX_CTL Register
Address: 3033_0000h base + 58h offset = 3033_0058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_MDIO
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_MDIO.
000 ALT0_ENET_QOS_MDIO — Select mux mode: ALT0 mux port: ENET_QOS_MDIO of instance:
enet_qos
010 ALT2_AUDIOMIX_SAI6_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_SYNC of instance: sai6
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
101 ALT5_GPIO1_IO[17] — Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1
110 ALT6_USDHC3_DATA5 — Select mux mode: ALT6 mux port: USDHC3_DATA5 of instance:
usdhc3
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8.2.4.19 SW_MUX_CTL_PAD_ENET_TD3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD3)
SW_MUX_CTL Register
Address: 3033_0000h base + 5Ch offset = 3033_005Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_TD3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TD3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_TD3.
000 ALT0_ENET_QOS_RGMII_TD3 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_TD3 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI6_TX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_BCLK of instance: sai6
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IOMUXC_SW_MUX_CTL_PAD_ENET_TD3 field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
101 ALT5_GPIO1_IO[18] — Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1
110 ALT6_USDHC3_DATA6 — Select mux mode: ALT6 mux port: USDHC3_DATA6 of instance:
usdhc3
8.2.4.20 SW_MUX_CTL_PAD_ENET_TD2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD2)
SW_MUX_CTL Register
Address: 3033_0000h base + 60h offset = 3033_0060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_TD2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TD2
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_ENET_TD2 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: ENET_TD2.
000 ALT0_ENET_QOS_RGMII_TD2 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_TD2 of
instance: enet_qos
001 ALT1_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK — Select mux mode: ALT1 mux port:
CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK of instance: ccm_enet_qos_clock_generate
010 ALT2_AUDIOMIX_SAI6_RX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_DATA00 of instance: sai6
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
101 ALT5_GPIO1_IO[19] — Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1
110 ALT6_USDHC3_DATA7 — Select mux mode: ALT6 mux port: USDHC3_DATA7 of instance:
usdhc3
8.2.4.21 SW_MUX_CTL_PAD_ENET_TD1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD1)
SW_MUX_CTL Register
Address: 3033_0000h base + 64h offset = 3033_0064h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ENET_TD1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TD1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_TD1.
000 ALT0_ENET_QOS_RGMII_TD1 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_TD1 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI6_RX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_SYNC of instance: sai6
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
101 ALT5_GPIO1_IO[20] — Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1
110 ALT6_USDHC3_CD_B — Select mux mode: ALT6 mux port: USDHC3_CD_B of instance: usdhc3
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8.2.4.22 SW_MUX_CTL_PAD_ENET_TD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_TD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 68h offset = 3033_0068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_TD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TD0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_TD0.
000 ALT0_ENET_QOS_RGMII_TD0 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_TD0 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI6_RX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_BCLK of instance: sai6
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IOMUXC_SW_MUX_CTL_PAD_ENET_TD0 field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_PDM_CLK — Select mux mode: ALT3 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
101 ALT5_GPIO1_IO[21] — Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1
110 ALT6_USDHC3_WP — Select mux mode: ALT6 mux port: USDHC3_WP of instance: usdhc3
8.2.4.23 SW_MUX_CTL_PAD_ENET_TX_CTL SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL)
SW_MUX_CTL Register
Address: 3033_0000h base + 6Ch offset = 3033_006Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TX_CTL
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_TX_CTL.
000 ALT0_ENET_QOS_RGMII_TX_CTL — Select mux mode: ALT0 mux port:
ENET_QOS_RGMII_TX_CTL of instance: enet_qos
010 ALT2_AUDIOMIX_SAI6_MCLK — Select mux mode: ALT2 mux port: AUDIOMIX_SAI6_MCLK of
instance: sai6
011 ALT3_AUDIOMIX_SPDIF1_OUT — Select mux mode: ALT3 mux port: AUDIOMIX_SPDIF1_OUT
of instance: spdif
101 ALT5_GPIO1_IO[22] — Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1
110 ALT6_USDHC3_DATA0 — Select mux mode: ALT6 mux port: USDHC3_DATA0 of instance:
usdhc3
8.2.4.24 SW_MUX_CTL_PAD_ENET_TXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_TXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 70h offset = 3033_0070h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ENET_TXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_TXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_TXC.
000 ALT0_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK — Select mux mode: ALT0 mux port:
CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK of instance: ccm_enet_qos_clock_generate
001 ALT1_ENET_QOS_TX_ER — Select mux mode: ALT1 mux port: ENET_QOS_TX_ER of instance:
enet_qos
010 ALT2_AUDIOMIX_SAI7_TX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_TX_DATA00 of instance: sai7
101 ALT5_GPIO1_IO[23] — Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1
110 ALT6_USDHC3_DATA1 — Select mux mode: ALT6 mux port: USDHC3_DATA1 of instance:
usdhc3
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8.2.4.25 SW_MUX_CTL_PAD_ENET_RX_CTL SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL)
SW_MUX_CTL Register
Address: 3033_0000h base + 74h offset = 3033_0074h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RX_CTL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_RX_CTL.
000 ALT0_ENET_QOS_RGMII_RX_CTL — Select mux mode: ALT0 mux port:
ENET_QOS_RGMII_RX_CTL of instance: enet_qos
010 ALT2_AUDIOMIX_SAI7_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_TX_SYNC of instance: sai7
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IOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
101 ALT5_GPIO1_IO[24] — Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1
110 ALT6_USDHC3_DATA2 — Select mux mode: ALT6 mux port: USDHC3_DATA2 of instance:
usdhc3
8.2.4.26 SW_MUX_CTL_PAD_ENET_RXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_RXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 78h offset = 3033_0078h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_RXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RXC
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_ENET_RXC field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: ENET_RXC.
000 ALT0_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK — Select mux mode: ALT0 mux port:
CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK of instance: ccm_enet_qos_clock_generate
001 ALT1_ENET_QOS_RX_ER — Select mux mode: ALT1 mux port: ENET_QOS_RX_ER of instance:
enet_qos
010 ALT2_AUDIOMIX_SAI7_TX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_TX_BCLK of instance: sai7
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
101 ALT5_GPIO1_IO[25] — Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1
110 ALT6_USDHC3_DATA3 — Select mux mode: ALT6 mux port: USDHC3_DATA3 of instance:
usdhc3
8.2.4.27 SW_MUX_CTL_PAD_ENET_RD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 7Ch offset = 3033_007Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ENET_RD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RD0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_RD0.
000 ALT0_ENET_QOS_RGMII_RD0 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_RD0 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI7_RX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_RX_DATA00 of instance: sai7
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
101 ALT5_GPIO1_IO[26] — Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1
110 ALT6_USDHC3_DATA4 — Select mux mode: ALT6 mux port: USDHC3_DATA4 of instance:
usdhc3
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8.2.4.28 SW_MUX_CTL_PAD_ENET_RD1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD1)
SW_MUX_CTL Register
Address: 3033_0000h base + 80h offset = 3033_0080h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_RD1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RD1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_RD1.
000 ALT0_ENET_QOS_RGMII_RD1 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_RD1 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI7_RX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_RX_SYNC of instance: sai7
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IOMUXC_SW_MUX_CTL_PAD_ENET_RD1 field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
101 ALT5_GPIO1_IO[27] — Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1
110 ALT6_USDHC3_RESET_B — Select mux mode: ALT6 mux port: USDHC3_RESET_B of instance:
usdhc3
8.2.4.29 SW_MUX_CTL_PAD_ENET_RD2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD2)
SW_MUX_CTL Register
Address: 3033_0000h base + 84h offset = 3033_0084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ENET_RD2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RD2
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_ENET_RD2 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_RD2.
000 ALT0_ENET_QOS_RGMII_RD2 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_RD2 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI7_RX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI7_RX_BCLK of instance: sai7
011 ALT3_AUDIOMIX_PDM_CLK — Select mux mode: ALT3 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
101 ALT5_GPIO1_IO[28] — Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1
110 ALT6_USDHC3_CLK — Select mux mode: ALT6 mux port: USDHC3_CLK of instance: usdhc3
8.2.4.30 SW_MUX_CTL_PAD_ENET_RD3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_ENET_RD3)
SW_MUX_CTL Register
Address: 3033_0000h base + 88h offset = 3033_0088h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ENET_RD3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ENET_RD3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ENET_RD3.
000 ALT0_ENET_QOS_RGMII_RD3 — Select mux mode: ALT0 mux port: ENET_QOS_RGMII_RD3 of
instance: enet_qos
010 ALT2_AUDIOMIX_SAI7_MCLK — Select mux mode: ALT2 mux port: AUDIOMIX_SAI7_MCLK of
instance: sai7
011 ALT3_AUDIOMIX_SPDIF1_IN — Select mux mode: ALT3 mux port: AUDIOMIX_SPDIF1_IN of
instance: spdif
101 ALT5_GPIO1_IO[29] — Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1
110 ALT6_USDHC3_CMD — Select mux mode: ALT6 mux port: USDHC3_CMD of instance: usdhc3
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8.2.4.31 SW_MUX_CTL_PAD_SD1_CLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 8Ch offset = 3033_008Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_CLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_CLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_CLK.
000 ALT0_USDHC1_CLK — Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1
001 ALT1_ENET1_MDC — Select mux mode: ALT1 mux port: ENET1_MDC of instance: enet1
011 ALT3_I2C5_SCL — Select mux mode: ALT3 mux port: I2C5_SCL of instance: i2c5
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IOMUXC_SW_MUX_CTL_PAD_SD1_CLK field descriptions (continued)
Field Description
100 ALT4_UART1_TX — Select mux mode: ALT4 mux port: UART1_TX of instance: uart1
101 ALT5_GPIO2_IO[0] — Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2
8.2.4.32 SW_MUX_CTL_PAD_SD1_CMD SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
SW_MUX_CTL Register
Address: 3033_0000h base + 90h offset = 3033_0090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_CMD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_CMD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SD1_CMD field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_CMD.
000 ALT0_USDHC1_CMD — Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1
001 ALT1_ENET1_MDIO — Select mux mode: ALT1 mux port: ENET1_MDIO of instance: enet1
011 ALT3_I2C5_SDA — Select mux mode: ALT3 mux port: I2C5_SDA of instance: i2c5
100 ALT4_UART1_RX — Select mux mode: ALT4 mux port: UART1_RX of instance: uart1
101 ALT5_GPIO2_IO[1] — Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2
8.2.4.33 SW_MUX_CTL_PAD_SD1_DATA0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0)
SW_MUX_CTL Register
Address: 3033_0000h base + 94h offset = 3033_0094h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA0.
000 ALT0_USDHC1_DATA0 — Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance:
usdhc1
001 ALT1_ENET1_RGMII_TD1 — Select mux mode: ALT1 mux port: ENET1_RGMII_TD1 of instance:
enet1
011 ALT3_I2C6_SCL — Select mux mode: ALT3 mux port: I2C6_SCL of instance: i2c6
100 ALT4_UART1_RTS_B — Select mux mode: ALT4 mux port: UART1_RTS_B of instance: uart1
101 ALT5_GPIO2_IO[2] — Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2
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8.2.4.34 SW_MUX_CTL_PAD_SD1_DATA1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1)
SW_MUX_CTL Register
Address: 3033_0000h base + 98h offset = 3033_0098h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA1.
000 ALT0_USDHC1_DATA1 — Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance:
usdhc1
001 ALT1_ENET1_RGMII_TD0 — Select mux mode: ALT1 mux port: ENET1_RGMII_TD0 of instance:
enet1
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IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 field descriptions (continued)
Field Description
011 ALT3_I2C6_SDA — Select mux mode: ALT3 mux port: I2C6_SDA of instance: i2c6
100 ALT4_UART1_CTS_B — Select mux mode: ALT4 mux port: UART1_CTS_B of instance: uart1
101 ALT5_GPIO2_IO[3] — Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2
8.2.4.35 SW_MUX_CTL_PAD_SD1_DATA2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2)
SW_MUX_CTL Register
Address: 3033_0000h base + 9Ch offset = 3033_009Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA2
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA2.
000 ALT0_USDHC1_DATA2 — Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance:
usdhc1
001 ALT1_ENET1_RGMII_RD0 — Select mux mode: ALT1 mux port: ENET1_RGMII_RD0 of instance:
enet1
011 ALT3_I2C4_SCL — Select mux mode: ALT3 mux port: I2C4_SCL of instance: i2c4
100 ALT4_UART2_TX — Select mux mode: ALT4 mux port: UART2_TX of instance: uart2
101 ALT5_GPIO2_IO[4] — Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2
8.2.4.36 SW_MUX_CTL_PAD_SD1_DATA3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3)
SW_MUX_CTL Register
Address: 3033_0000h base + A0h offset = 3033_00A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SD1_DATA3.
000 ALT0_USDHC1_DATA3 — Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance:
usdhc1
001 ALT1_ENET1_RGMII_RD1 — Select mux mode: ALT1 mux port: ENET1_RGMII_RD1 of instance:
enet1
011 ALT3_I2C4_SDA — Select mux mode: ALT3 mux port: I2C4_SDA of instance: i2c4
100 ALT4_UART2_RX — Select mux mode: ALT4 mux port: UART2_RX of instance: uart2
101 ALT5_GPIO2_IO[5] — Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2
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IOMUX Controller (IOMUXC)
8.2.4.37 SW_MUX_CTL_PAD_SD1_DATA4 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4)
SW_MUX_CTL Register
Address: 3033_0000h base + A4h offset = 3033_00A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA4
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA4.
000 ALT0_USDHC1_DATA4 — Select mux mode: ALT0 mux port: USDHC1_DATA4 of instance:
usdhc1
001 ALT1_ENET1_RGMII_TX_CTL — Select mux mode: ALT1 mux port: ENET1_RGMII_TX_CTL of
instance: enet1
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 field descriptions (continued)
Field Description
011 ALT3_I2C1_SCL — Select mux mode: ALT3 mux port: I2C1_SCL of instance: i2c1
100 ALT4_UART2_RTS_B — Select mux mode: ALT4 mux port: UART2_RTS_B of instance: uart2
101 ALT5_GPIO2_IO[6] — Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2
8.2.4.38 SW_MUX_CTL_PAD_SD1_DATA5 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5)
SW_MUX_CTL Register
Address: 3033_0000h base + A8h offset = 3033_00A8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA5
0 DISABLED — Input Path is determined by functionality
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA5.
000 ALT0_USDHC1_DATA5 — Select mux mode: ALT0 mux port: USDHC1_DATA5 of instance:
usdhc1
001 ALT1_ENET1_TX_ER — Select mux mode: ALT1 mux port: ENET1_TX_ER of instance: enet1
011 ALT3_I2C1_SDA — Select mux mode: ALT3 mux port: I2C1_SDA of instance: i2c1
100 ALT4_UART2_CTS_B — Select mux mode: ALT4 mux port: UART2_CTS_B of instance: uart2
101 ALT5_GPIO2_IO[7] — Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2
8.2.4.39 SW_MUX_CTL_PAD_SD1_DATA6 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6)
SW_MUX_CTL Register
Address: 3033_0000h base + ACh offset = 3033_00ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA6
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA6.
000 ALT0_USDHC1_DATA6 — Select mux mode: ALT0 mux port: USDHC1_DATA6 of instance:
usdhc1
001 ALT1_ENET1_RGMII_RX_CTL — Select mux mode: ALT1 mux port: ENET1_RGMII_RX_CTL of
instance: enet1
011 ALT3_I2C2_SCL — Select mux mode: ALT3 mux port: I2C2_SCL of instance: i2c2
100 ALT4_UART3_TX — Select mux mode: ALT4 mux port: UART3_TX of instance: uart3
101 ALT5_GPIO2_IO[8] — Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2
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IOMUX Controller (IOMUXC)
8.2.4.40 SW_MUX_CTL_PAD_SD1_DATA7 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7)
SW_MUX_CTL Register
Address: 3033_0000h base + B0h offset = 3033_00B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_DATA7
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_DATA7.
000 ALT0_USDHC1_DATA7 — Select mux mode: ALT0 mux port: USDHC1_DATA7 of instance:
usdhc1
001 ALT1_ENET1_RX_ER — Select mux mode: ALT1 mux port: ENET1_RX_ER of instance: enet1
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 field descriptions (continued)
Field Description
011 ALT3_I2C2_SDA — Select mux mode: ALT3 mux port: I2C2_SDA of instance: i2c2
100 ALT4_UART3_RX — Select mux mode: ALT4 mux port: UART3_RX of instance: uart3
101 ALT5_GPIO2_IO[9] — Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2
8.2.4.41 SW_MUX_CTL_PAD_SD1_RESET_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B)
SW_MUX_CTL Register
Address: 3033_0000h base + B4h offset = 3033_00B4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_RESET_B
0 DISABLED — Input Path is determined by functionality
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD1_RESET_B.
000 ALT0_USDHC1_RESET_B — Select mux mode: ALT0 mux port: USDHC1_RESET_B of instance:
usdhc1
001 ALT1_ENET1_TX_CLK — Select mux mode: ALT1 mux port: ENET1_TX_CLK of instance: enet1
011 ALT3_I2C3_SCL — Select mux mode: ALT3 mux port: I2C3_SCL of instance: i2c3
100 ALT4_UART3_RTS_B — Select mux mode: ALT4 mux port: UART3_RTS_B of instance: uart3
101 ALT5_GPIO2_IO[10] — Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2
8.2.4.42 SW_MUX_CTL_PAD_SD1_STROBE SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE)
SW_MUX_CTL Register
Address: 3033_0000h base + B8h offset = 3033_00B8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD1_STROBE
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SD1_STROBE.
000 ALT0_USDHC1_STROBE — Select mux mode: ALT0 mux port: USDHC1_STROBE of instance:
usdhc1
011 ALT3_I2C3_SDA — Select mux mode: ALT3 mux port: I2C3_SDA of instance: i2c3
100 ALT4_UART3_CTS_B — Select mux mode: ALT4 mux port: UART3_CTS_B of instance: uart3
101 ALT5_GPIO2_IO[11] — Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2
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8.2.4.43 SW_MUX_CTL_PAD_SD2_CD_B SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B)
SW_MUX_CTL Register
Address: 3033_0000h base + BCh offset = 3033_00BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_CD_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SD2_CD_B.
000 ALT0_USDHC2_CD_B — Select mux mode: ALT0 mux port: USDHC2_CD_B of instance: usdhc2
101 ALT5_GPIO2_IO[12] — Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2
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8.2.4.44 SW_MUX_CTL_PAD_SD2_CLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK)
SW_MUX_CTL Register
Address: 3033_0000h base + C0h offset = 3033_00C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_CLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_CLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SD2_CLK.
000 ALT0_USDHC2_CLK — Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2
010 ALT2_ECSPI2_SCLK — Select mux mode: ALT2 mux port: ECSPI2_SCLK of instance: ecspi2
011 ALT3_UART4_RX — Select mux mode: ALT3 mux port: UART4_RX of instance: uart4
101 ALT5_GPIO2_IO[13] — Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2
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IOMUX Controller (IOMUXC)
8.2.4.45 SW_MUX_CTL_PAD_SD2_CMD SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD)
SW_MUX_CTL Register
Address: 3033_0000h base + C4h offset = 3033_00C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_CMD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_CMD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SD2_CMD.
000 ALT0_USDHC2_CMD — Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2
010 ALT2_ECSPI2_MOSI — Select mux mode: ALT2 mux port: ECSPI2_MOSI of instance: ecspi2
011 ALT3_UART4_TX — Select mux mode: ALT3 mux port: UART4_TX of instance: uart4
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SD2_CMD field descriptions (continued)
Field Description
100 ALT4_AUDIOMIX_PDM_CLK — Select mux mode: ALT4 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
101 ALT5_GPIO2_IO[14] — Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2
8.2.4.46 SW_MUX_CTL_PAD_SD2_DATA0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0)
SW_MUX_CTL Register
Address: 3033_0000h base + C8h offset = 3033_00C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_DATA0
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SD2_DATA0.
000 ALT0_USDHC2_DATA0 — Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance:
usdhc2
010 ALT2_I2C4_SDA — Select mux mode: ALT2 mux port: I2C4_SDA of instance: i2c4
011 ALT3_UART2_RX — Select mux mode: ALT3 mux port: UART2_RX of instance: uart2
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
101 ALT5_GPIO2_IO[15] — Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2
8.2.4.47 SW_MUX_CTL_PAD_SD2_DATA1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1)
SW_MUX_CTL Register
Address: 3033_0000h base + CCh offset = 3033_00CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_DATA1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SD2_DATA1.
000 ALT0_USDHC2_DATA1 — Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance:
usdhc2
010 ALT2_I2C4_SCL — Select mux mode: ALT2 mux port: I2C4_SCL of instance: i2c4
011 ALT3_UART2_TX — Select mux mode: ALT3 mux port: UART2_TX of instance: uart2
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
101 ALT5_GPIO2_IO[16] — Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2
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8.2.4.48 SW_MUX_CTL_PAD_SD2_DATA2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2)
SW_MUX_CTL Register
Address: 3033_0000h base + D0h offset = 3033_00D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_DATA2
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SD2_DATA2.
000 ALT0_USDHC2_DATA2 — Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance:
usdhc2
010 ALT2_ECSPI2_SS0 — Select mux mode: ALT2 mux port: ECSPI2_SS0 of instance: ecspi2
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IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_SPDIF1_OUT — Select mux mode: ALT3 mux port: AUDIOMIX_SPDIF1_OUT
of instance: spdif
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
101 ALT5_GPIO2_IO[17] — Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2
8.2.4.49 SW_MUX_CTL_PAD_SD2_DATA3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3)
SW_MUX_CTL Register
Address: 3033_0000h base + D4h offset = 3033_00D4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_DATA3
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SD2_DATA3.
000 ALT0_USDHC2_DATA3 — Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance:
usdhc2
010 ALT2_ECSPI2_MISO — Select mux mode: ALT2 mux port: ECSPI2_MISO of instance: ecspi2
011 ALT3_AUDIOMIX_SPDIF1_IN — Select mux mode: ALT3 mux port: AUDIOMIX_SPDIF1_IN of
instance: spdif
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
101 ALT5_GPIO2_IO[18] — Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2
8.2.4.50 SW_MUX_CTL_PAD_SD2_RESET_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B)
SW_MUX_CTL Register
Address: 3033_0000h base + D8h offset = 3033_00D8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_RESET_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 2 iomux modes to be used for pad: SD2_RESET_B.
000 ALT0_USDHC2_RESET_B — Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance:
usdhc2
101 ALT5_GPIO2_IO[19] — Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2
8.2.4.51 SW_MUX_CTL_PAD_SD2_WP SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SD2_WP)
SW_MUX_CTL Register
Address: 3033_0000h base + DCh offset = 3033_00DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_SD2_WP field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SD2_WP
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SD2_WP.
000 ALT0_USDHC2_WP — Select mux mode: ALT0 mux port: USDHC2_WP of instance: usdhc2
101 ALT5_GPIO2_IO[20] — Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2
110 ALT6_CORESIGHT_EVENTI — Select mux mode: ALT6 mux port: CORESIGHT_EVENTI of
instance: coresight
8.2.4.52 SW_MUX_CTL_PAD_NAND_ALE SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
SW_MUX_CTL Register
Address: 3033_0000h base + E0h offset = 3033_00E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_NAND_ALE field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_ALE
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_ALE.
000 ALT0_NAND_ALE — Select mux mode: ALT0 mux port: NAND_ALE of instance: nand
001 ALT1_FLEXSPI_A_SCLK — Select mux mode: ALT1 mux port: FLEXSPI_A_SCLK of instance:
flexspi
010 ALT2_AUDIOMIX_SAI3_TX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI3_TX_BCLK of instance: sai3
011 ALT3_ISP_FL_TRIG_0 — Select mux mode: ALT3 mux port: ISP_FL_TRIG_0 of instance: isp
100 ALT4_UART3_RX — Select mux mode: ALT4 mux port: UART3_RX of instance: uart3
101 ALT5_GPIO3_IO[0] — Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3
110 ALT6_CORESIGHT_TRACE_CLK — Select mux mode: ALT6 mux port:
CORESIGHT_TRACE_CLK of instance: coresight
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IOMUX Controller (IOMUXC)
8.2.4.53 SW_MUX_CTL_PAD_NAND_CE0_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B)
SW_MUX_CTL Register
Address: 3033_0000h base + E4h offset = 3033_00E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_CE0_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_CE0_B.
000 ALT0_NAND_CE0_B — Select mux mode: ALT0 mux port: NAND_CE0_B of instance: nand
001 ALT1_FLEXSPI_A_SS0_B — Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance:
flexspi
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI3_TX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI3_TX_DATA00 of instance: sai3
011 ALT3_ISP_SHUTTER_TRIG_0 — Select mux mode: ALT3 mux port: ISP_SHUTTER_TRIG_0 of
instance: isp
100 ALT4_UART3_TX — Select mux mode: ALT4 mux port: UART3_TX of instance: uart3
101 ALT5_GPIO3_IO[1] — Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3
110 ALT6_CORESIGHT_TRACE_CTL — Select mux mode: ALT6 mux port:
CORESIGHT_TRACE_CTL of instance: coresight
8.2.4.54 SW_MUX_CTL_PAD_NAND_CE1_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B)
SW_MUX_CTL Register
Address: 3033_0000h base + E8h offset = 3033_00E8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_CE1_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: NAND_CE1_B.
000 ALT0_NAND_CE1_B — Select mux mode: ALT0 mux port: NAND_CE1_B of instance: nand
001 ALT1_FLEXSPI_A_SS1_B — Select mux mode: ALT1 mux port: FLEXSPI_A_SS1_B of instance:
flexspi
010 ALT2_USDHC3_STROBE — Select mux mode: ALT2 mux port: USDHC3_STROBE of instance:
usdhc3
100 ALT4_I2C4_SCL — Select mux mode: ALT4 mux port: I2C4_SCL of instance: i2c4
101 ALT5_GPIO3_IO[2] — Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[0] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE00 of
instance: coresight
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Chapter 8 Chip IO and Pinmux
8.2.4.55 SW_MUX_CTL_PAD_NAND_CE2_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B)
SW_MUX_CTL Register
Address: 3033_0000h base + ECh offset = 3033_00ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_CE2_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: NAND_CE2_B.
000 ALT0_NAND_CE2_B — Select mux mode: ALT0 mux port: NAND_CE2_B of instance: nand
001 ALT1_FLEXSPI_B_SS0_B — Select mux mode: ALT1 mux port: FLEXSPI_B_SS0_B of instance:
flexspi
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B field descriptions (continued)
Field Description
010 ALT2_USDHC3_DATA5 — Select mux mode: ALT2 mux port: USDHC3_DATA5 of instance:
usdhc3
100 ALT4_I2C4_SDA — Select mux mode: ALT4 mux port: I2C4_SDA of instance: i2c4
101 ALT5_GPIO3_IO[3] — Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[1] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE01 of
instance: coresight
8.2.4.56 SW_MUX_CTL_PAD_NAND_CE3_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B)
SW_MUX_CTL Register
Address: 3033_0000h base + F0h offset = 3033_00F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad NAND_CE3_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: NAND_CE3_B.
000 ALT0_NAND_CE3_B — Select mux mode: ALT0 mux port: NAND_CE3_B of instance: nand
001 ALT1_FLEXSPI_B_SS1_B — Select mux mode: ALT1 mux port: FLEXSPI_B_SS1_B of instance:
flexspi
010 ALT2_USDHC3_DATA6 — Select mux mode: ALT2 mux port: USDHC3_DATA6 of instance:
usdhc3
100 ALT4_I2C3_SDA — Select mux mode: ALT4 mux port: I2C3_SDA of instance: i2c3
101 ALT5_GPIO3_IO[4] — Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[2] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE02 of
instance: coresight
8.2.4.57 SW_MUX_CTL_PAD_NAND_CLE SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
SW_MUX_CTL Register
Address: 3033_0000h base + F4h offset = 3033_00F4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_NAND_CLE field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_CLE
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: NAND_CLE.
000 ALT0_NAND_CLE — Select mux mode: ALT0 mux port: NAND_CLE of instance: nand
001 ALT1_FLEXSPI_B_SCLK — Select mux mode: ALT1 mux port: FLEXSPI_B_SCLK of instance:
flexspi
010 ALT2_USDHC3_DATA7 — Select mux mode: ALT2 mux port: USDHC3_DATA7 of instance:
usdhc3
100 ALT4_UART4_RX — Select mux mode: ALT4 mux port: UART4_RX of instance: uart4
101 ALT5_GPIO3_IO[5] — Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[3] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE03 of
instance: coresight
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8.2.4.58 SW_MUX_CTL_PAD_NAND_DATA00 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
SW_MUX_CTL Register
Address: 3033_0000h base + F8h offset = 3033_00F8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA00
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA00.
000 ALT0_NAND_DATA00 — Select mux mode: ALT0 mux port: NAND_DATA00 of instance: nand
001 ALT1_FLEXSPI_A_DATA[0] — Select mux mode: ALT1 mux port: FLEXSPI_A_DATA00 of
instance: flexspi
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI3_RX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI3_RX_DATA00 of instance: sai3
011 ALT3_ISP_FLASH_TRIG_0 — Select mux mode: ALT3 mux port: ISP_FLASH_TRIG_0 of
instance: isp
100 ALT4_UART4_RX — Select mux mode: ALT4 mux port: UART4_RX of instance: uart4
101 ALT5_GPIO3_IO[6] — Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[4] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE04 of
instance: coresight
8.2.4.59 SW_MUX_CTL_PAD_NAND_DATA01 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
SW_MUX_CTL Register
Address: 3033_0000h base + FCh offset = 3033_00FCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA01
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA01.
000 ALT0_NAND_DATA01 — Select mux mode: ALT0 mux port: NAND_DATA01 of instance: nand
001 ALT1_FLEXSPI_A_DATA[1] — Select mux mode: ALT1 mux port: FLEXSPI_A_DATA01 of
instance: flexspi
010 ALT2_AUDIOMIX_SAI3_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI3_TX_SYNC of instance: sai3
011 ALT3_ISP_PRELIGHT_TRIG_0 — Select mux mode: ALT3 mux port: ISP_PRELIGHT_TRIG_0 of
instance: isp
100 ALT4_UART4_TX — Select mux mode: ALT4 mux port: UART4_TX of instance: uart4
101 ALT5_GPIO3_IO[7] — Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[5] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE05 of
instance: coresight
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8.2.4.60 SW_MUX_CTL_PAD_NAND_DATA02 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
SW_MUX_CTL Register
Address: 3033_0000h base + 100h offset = 3033_0100h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA02
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA02.
000 ALT0_NAND_DATA02 — Select mux mode: ALT0 mux port: NAND_DATA02 of instance: nand
001 ALT1_FLEXSPI_A_DATA[2] — Select mux mode: ALT1 mux port: FLEXSPI_A_DATA02 of
instance: flexspi
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 field descriptions (continued)
Field Description
010 ALT2_USDHC3_CD_B — Select mux mode: ALT2 mux port: USDHC3_CD_B of instance: usdhc3
011 ALT3_UART4_CTS_B — Select mux mode: ALT3 mux port: UART4_CTS_B of instance: uart4
100 ALT4_I2C4_SDA — Select mux mode: ALT4 mux port: I2C4_SDA of instance: i2c4
101 ALT5_GPIO3_IO[8] — Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[6] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE06 of
instance: coresight
8.2.4.61 SW_MUX_CTL_PAD_NAND_DATA03 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
SW_MUX_CTL Register
Address: 3033_0000h base + 104h offset = 3033_0104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad NAND_DATA03
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA03.
000 ALT0_NAND_DATA03 — Select mux mode: ALT0 mux port: NAND_DATA03 of instance: nand
001 ALT1_FLEXSPI_A_DATA[3] — Select mux mode: ALT1 mux port: FLEXSPI_A_DATA03 of
instance: flexspi
010 ALT2_USDHC3_WP — Select mux mode: ALT2 mux port: USDHC3_WP of instance: usdhc3
011 ALT3_UART4_RTS_B — Select mux mode: ALT3 mux port: UART4_RTS_B of instance: uart4
100 ALT4_ISP_FL_TRIG_1 — Select mux mode: ALT4 mux port: ISP_FL_TRIG_1 of instance: isp
101 ALT5_GPIO3_IO[9] — Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[7] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE07 of
instance: coresight
8.2.4.62 SW_MUX_CTL_PAD_NAND_DATA04 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04)
SW_MUX_CTL Register
Address: 3033_0000h base + 108h offset = 3033_0108h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA04
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA04.
000 ALT0_NAND_DATA04 — Select mux mode: ALT0 mux port: NAND_DATA04 of instance: nand
001 ALT1_FLEXSPI_B_DATA[0] — Select mux mode: ALT1 mux port: FLEXSPI_B_DATA00 of
instance: flexspi
010 ALT2_USDHC3_DATA0 — Select mux mode: ALT2 mux port: USDHC3_DATA0 of instance:
usdhc3
011 ALT3_FLEXSPI_A_DATA[4] — Select mux mode: ALT3 mux port: FLEXSPI_A_DATA04 of
instance: flexspi
100 ALT4_ISP_SHUTTER_TRIG_1 — Select mux mode: ALT4 mux port: ISP_SHUTTER_TRIG_1 of
instance: isp
101 ALT5_GPIO3_IO[10] — Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[8] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE08 of
instance: coresight
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8.2.4.63 SW_MUX_CTL_PAD_NAND_DATA05 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05)
SW_MUX_CTL Register
Address: 3033_0000h base + 10Ch offset = 3033_010Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA05
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA05.
000 ALT0_NAND_DATA05 — Select mux mode: ALT0 mux port: NAND_DATA05 of instance: nand
001 ALT1_FLEXSPI_B_DATA[1] — Select mux mode: ALT1 mux port: FLEXSPI_B_DATA01 of
instance: flexspi
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 field descriptions (continued)
Field Description
010 ALT2_USDHC3_DATA1 — Select mux mode: ALT2 mux port: USDHC3_DATA1 of instance:
usdhc3
011 ALT3_FLEXSPI_A_DATA[5] — Select mux mode: ALT3 mux port: FLEXSPI_A_DATA05 of
instance: flexspi
100 ALT4_ISP_FLASH_TRIG_1 — Select mux mode: ALT4 mux port: ISP_FLASH_TRIG_1 of
instance: isp
101 ALT5_GPIO3_IO[11] — Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[9] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE09 of
instance: coresight
8.2.4.64 SW_MUX_CTL_PAD_NAND_DATA06 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06)
SW_MUX_CTL Register
Address: 3033_0000h base + 110h offset = 3033_0110h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA06
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA06.
000 ALT0_NAND_DATA06 — Select mux mode: ALT0 mux port: NAND_DATA06 of instance: nand
001 ALT1_FLEXSPI_B_DATA[2] — Select mux mode: ALT1 mux port: FLEXSPI_B_DATA02 of
instance: flexspi
010 ALT2_USDHC3_DATA2 — Select mux mode: ALT2 mux port: USDHC3_DATA2 of instance:
usdhc3
011 ALT3_FLEXSPI_A_DATA[6] — Select mux mode: ALT3 mux port: FLEXSPI_A_DATA06 of
instance: flexspi
100 ALT4_ISP_PRELIGHT_TRIG_1 — Select mux mode: ALT4 mux port: ISP_PRELIGHT_TRIG_1 of
instance: isp
101 ALT5_GPIO3_IO[12] — Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[10] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE10 of
instance: coresight
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8.2.4.65 SW_MUX_CTL_PAD_NAND_DATA07 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07)
SW_MUX_CTL Register
Address: 3033_0000h base + 114h offset = 3033_0114h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DATA07
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DATA07.
000 ALT0_NAND_DATA07 — Select mux mode: ALT0 mux port: NAND_DATA07 of instance: nand
001 ALT1_FLEXSPI_B_DATA[3] — Select mux mode: ALT1 mux port: FLEXSPI_B_DATA03 of
instance: flexspi
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IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 field descriptions (continued)
Field Description
010 ALT2_USDHC3_DATA3 — Select mux mode: ALT2 mux port: USDHC3_DATA3 of instance:
usdhc3
011 ALT3_FLEXSPI_A_DATA[7] — Select mux mode: ALT3 mux port: FLEXSPI_A_DATA07 of
instance: flexspi
100 ALT4_ISP_SHUTTER_OPEN_1 — Select mux mode: ALT4 mux port: ISP_SHUTTER_OPEN_1 of
instance: isp
101 ALT5_GPIO3_IO[13] — Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[11] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE11 of
instance: coresight
8.2.4.66 SW_MUX_CTL_PAD_NAND_DQS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_DQS)
SW_MUX_CTL Register
Address: 3033_0000h base + 118h offset = 3033_0118h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_DQS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_NAND_DQS field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_DQS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: NAND_DQS.
000 ALT0_NAND_DQS — Select mux mode: ALT0 mux port: NAND_DQS of instance: nand
001 ALT1_FLEXSPI_A_DQS — Select mux mode: ALT1 mux port: FLEXSPI_A_DQS of instance:
flexspi
010 ALT2_AUDIOMIX_SAI3_MCLK — Select mux mode: ALT2 mux port: AUDIOMIX_SAI3_MCLK of
instance: sai3
011 ALT3_ISP_SHUTTER_OPEN_0 — Select mux mode: ALT3 mux port: ISP_SHUTTER_OPEN_0 of
instance: isp
100 ALT4_I2C3_SCL — Select mux mode: ALT4 mux port: I2C3_SCL of instance: i2c3
101 ALT5_GPIO3_IO[14] — Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[12] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE12 of
instance: coresight
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8.2.4.67 SW_MUX_CTL_PAD_NAND_RE_B SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B)
SW_MUX_CTL Register
Address: 3033_0000h base + 11Ch offset = 3033_011Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_RE_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: NAND_RE_B.
000 ALT0_NAND_RE_B — Select mux mode: ALT0 mux port: NAND_RE_B of instance: nand
001 ALT1_FLEXSPI_B_DQS — Select mux mode: ALT1 mux port: FLEXSPI_B_DQS of instance:
flexspi
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IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B field descriptions (continued)
Field Description
010 ALT2_USDHC3_DATA4 — Select mux mode: ALT2 mux port: USDHC3_DATA4 of instance:
usdhc3
100 ALT4_UART4_TX — Select mux mode: ALT4 mux port: UART4_TX of instance: uart4
101 ALT5_GPIO3_IO[15] — Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[13] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE13 of
instance: coresight
8.2.4.68 SW_MUX_CTL_PAD_NAND_READY_B SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
SW_MUX_CTL Register
Address: 3033_0000h base + 120h offset = 3033_0120h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad NAND_READY_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: NAND_READY_B.
000 ALT0_NAND_READY_B — Select mux mode: ALT0 mux port: NAND_READY_B of instance: nand
010 ALT2_USDHC3_RESET_B — Select mux mode: ALT2 mux port: USDHC3_RESET_B of instance:
usdhc3
100 ALT4_I2C3_SCL — Select mux mode: ALT4 mux port: I2C3_SCL of instance: i2c3
101 ALT5_GPIO3_IO[16] — Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[14] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE14 of
instance: coresight
8.2.4.69 SW_MUX_CTL_PAD_NAND_WE_B SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B)
SW_MUX_CTL Register
Address: 3033_0000h base + 124h offset = 3033_0124h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_WE_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: NAND_WE_B.
000 ALT0_NAND_WE_B — Select mux mode: ALT0 mux port: NAND_WE_B of instance: nand
010 ALT2_USDHC3_CLK — Select mux mode: ALT2 mux port: USDHC3_CLK of instance: usdhc3
100 ALT4_I2C3_SDA — Select mux mode: ALT4 mux port: I2C3_SDA of instance: i2c3
101 ALT5_GPIO3_IO[17] — Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3
110 ALT6_CORESIGHT_TRACE[15] — Select mux mode: ALT6 mux port: CORESIGHT_TRACE15 of
instance: coresight
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8.2.4.70 SW_MUX_CTL_PAD_NAND_WP_B SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
SW_MUX_CTL Register
Address: 3033_0000h base + 128h offset = 3033_0128h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad NAND_WP_B
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: NAND_WP_B.
000 ALT0_NAND_WP_B — Select mux mode: ALT0 mux port: NAND_WP_B of instance: nand
010 ALT2_USDHC3_CMD — Select mux mode: ALT2 mux port: USDHC3_CMD of instance: usdhc3
100 ALT4_I2C4_SCL — Select mux mode: ALT4 mux port: I2C4_SCL of instance: i2c4
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IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B field descriptions (continued)
Field Description
101 ALT5_GPIO3_IO[18] — Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3
110 ALT6_CORESIGHT_EVENTO — Select mux mode: ALT6 mux port: CORESIGHT_EVENTO of
instance: coresight
8.2.4.71 SW_MUX_CTL_PAD_SAI5_RXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 12Ch offset = 3033_012Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_RXFS
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI5_RXFS.
000 ALT0_AUDIOMIX_SAI5_RX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_SYNC of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[0] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA00 of instance: sai1
010 ALT2_PWM4_OUT — Select mux mode: ALT2 mux port: PWM4_OUT of instance: pwm4
011 ALT3_I2C6_SCL — Select mux mode: ALT3 mux port: I2C6_SCL of instance: i2c6
101 ALT5_GPIO3_IO[19] — Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3
8.2.4.72 SW_MUX_CTL_PAD_SAI5_RXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 130h offset = 3033_0130h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_RXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_RXC.
000 ALT0_AUDIOMIX_SAI5_RX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_BCLK of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[1] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA01 of instance: sai1
010 ALT2_PWM3_OUT — Select mux mode: ALT2 mux port: PWM3_OUT of instance: pwm3
011 ALT3_I2C6_SDA — Select mux mode: ALT3 mux port: I2C6_SDA of instance: i2c6
100 ALT4_AUDIOMIX_PDM_CLK — Select mux mode: ALT4 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
101 ALT5_GPIO3_IO[20] — Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3
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8.2.4.73 SW_MUX_CTL_PAD_SAI5_RXD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 134h offset = 3033_0134h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_RXD0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_RXD0.
000 ALT0_AUDIOMIX_SAI5_RX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_DATA00 of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[2] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA02 of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 field descriptions (continued)
Field Description
010 ALT2_PWM2_OUT — Select mux mode: ALT2 mux port: PWM2_OUT of instance: pwm2
011 ALT3_I2C5_SCL — Select mux mode: ALT3 mux port: I2C5_SCL of instance: i2c5
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
101 ALT5_GPIO3_IO[21] — Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3
8.2.4.74 SW_MUX_CTL_PAD_SAI5_RXD1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1)
SW_MUX_CTL Register
Address: 3033_0000h base + 138h offset = 3033_0138h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad SAI5_RXD1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI5_RXD1.
000 ALT0_AUDIOMIX_SAI5_RX_DATA[1] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_DATA01 of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[3] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA03 of instance: sai1
010 ALT2_AUDIOMIX_SAI1_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_SYNC of instance: sai1
011 ALT3_AUDIOMIX_SAI5_TX_SYNC — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI5_TX_SYNC of instance: sai5
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
101 ALT5_GPIO3_IO[22] — Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3
110 ALT6_CAN1_TX — Select mux mode: ALT6 mux port: CAN1_TX of instance: can1
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8.2.4.75 SW_MUX_CTL_PAD_SAI5_RXD2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2)
SW_MUX_CTL Register
Address: 3033_0000h base + 13Ch offset = 3033_013Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_RXD2
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI5_RXD2.
000 ALT0_AUDIOMIX_SAI5_RX_DATA[2] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_DATA02 of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[4] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA04 of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI1_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_SYNC of instance: sai1
011 ALT3_AUDIOMIX_SAI5_TX_BCLK — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI5_TX_BCLK of instance: sai5
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
101 ALT5_GPIO3_IO[23] — Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3
110 ALT6_CAN1_RX — Select mux mode: ALT6 mux port: CAN1_RX of instance: can1
8.2.4.76 SW_MUX_CTL_PAD_SAI5_RXD3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3)
SW_MUX_CTL Register
Address: 3033_0000h base + 140h offset = 3033_0140h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_RXD3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI5_RXD3.
000 ALT0_AUDIOMIX_SAI5_RX_DATA[3] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI5_RX_DATA03 of instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_DATA[5] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_DATA05 of instance: sai1
010 ALT2_AUDIOMIX_SAI1_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_SYNC of instance: sai1
011 ALT3_AUDIOMIX_SAI5_TX_DATA[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI5_TX_DATA00 of instance: sai5
100 ALT4_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT4 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
101 ALT5_GPIO3_IO[24] — Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3
110 ALT6_CAN2_TX — Select mux mode: ALT6 mux port: CAN2_TX of instance: can2
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8.2.4.77 SW_MUX_CTL_PAD_SAI5_MCLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 144h offset = 3033_0144h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI5_MCLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI5_MCLK.
000 ALT0_AUDIOMIX_SAI5_MCLK — Select mux mode: ALT0 mux port: AUDIOMIX_SAI5_MCLK of
instance: sai5
001 ALT1_AUDIOMIX_SAI1_TX_BCLK — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI1_TX_BCLK of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK field descriptions (continued)
Field Description
010 ALT2_PWM1_OUT — Select mux mode: ALT2 mux port: PWM1_OUT of instance: pwm1
011 ALT3_I2C5_SDA — Select mux mode: ALT3 mux port: I2C5_SDA of instance: i2c5
101 ALT5_GPIO3_IO[25] — Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3
110 ALT6_CAN2_RX — Select mux mode: ALT6 mux port: CAN2_RX of instance: can2
8.2.4.78 SW_MUX_CTL_PAD_SAI1_RXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 148h offset = 3033_0148h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXFS
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_RXFS.
000 ALT0_AUDIOMIX_SAI1_RX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_SYNC of instance: sai1
100 ALT4_ENET1_1588_EVENT0_IN — Select mux mode: ALT4 mux port: ENET1_1588_EVENT0_IN
of instance: enet1
101 ALT5_GPIO4_IO[0] — Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4
8.2.4.79 SW_MUX_CTL_PAD_SAI1_RXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 14Ch offset = 3033_014Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXC field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXC.
000 ALT0_AUDIOMIX_SAI1_RX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_BCLK of instance: sai1
011 ALT3_AUDIOMIX_PDM_CLK — Select mux mode: ALT3 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
100 ALT4_ENET1_1588_EVENT0_OUT — Select mux mode: ALT4 mux port:
ENET1_1588_EVENT0_OUT of instance: enet1
101 ALT5_GPIO4_IO[1] — Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4
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8.2.4.80 SW_MUX_CTL_PAD_SAI1_RXD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 150h offset = 3033_0150h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_RXD0.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA00 of instance: sai1
010 ALT2_AUDIOMIX_SAI1_TX_DATA[1] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_DATA01 of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
100 ALT4_ENET1_1588_EVENT1_IN — Select mux mode: ALT4 mux port: ENET1_1588_EVENT1_IN
of instance: enet1
101 ALT5_GPIO4_IO[2] — Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4
8.2.4.81 SW_MUX_CTL_PAD_SAI1_RXD1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1)
SW_MUX_CTL Register
Address: 3033_0000h base + 154h offset = 3033_0154h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD1
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXD1.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[1] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA01 of instance: sai1
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
100 ALT4_ENET1_1588_EVENT1_OUT — Select mux mode: ALT4 mux port:
ENET1_1588_EVENT1_OUT of instance: enet1
101 ALT5_GPIO4_IO[3] — Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4
8.2.4.82 SW_MUX_CTL_PAD_SAI1_RXD2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2)
SW_MUX_CTL Register
Address: 3033_0000h base + 158h offset = 3033_0158h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD2
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXD2.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[2] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA02 of instance: sai1
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
100 ALT4_ENET1_MDC — Select mux mode: ALT4 mux port: ENET1_MDC of instance: enet1
101 ALT5_GPIO4_IO[4] — Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4
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8.2.4.83 SW_MUX_CTL_PAD_SAI1_RXD3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3)
SW_MUX_CTL Register
Address: 3033_0000h base + 15Ch offset = 3033_015Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_RXD3.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[3] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA03 of instance: sai1
011 ALT3_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT3 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 field descriptions (continued)
Field Description
100 ALT4_ENET1_MDIO — Select mux mode: ALT4 mux port: ENET1_MDIO of instance: enet1
101 ALT5_GPIO4_IO[5] — Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4
8.2.4.84 SW_MUX_CTL_PAD_SAI1_RXD4 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4)
SW_MUX_CTL Register
Address: 3033_0000h base + 160h offset = 3033_0160h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD4
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_RXD4.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[4] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA04 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_TX_BCLK — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_TX_BCLK of instance: sai6
010 ALT2_AUDIOMIX_SAI6_RX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_BCLK of instance: sai6
100 ALT4_ENET1_RGMII_RD0 — Select mux mode: ALT4 mux port: ENET1_RGMII_RD0 of instance:
enet1
101 ALT5_GPIO4_IO[6] — Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4
8.2.4.85 SW_MUX_CTL_PAD_SAI1_RXD5 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5)
SW_MUX_CTL Register
Address: 3033_0000h base + 164h offset = 3033_0164h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD5
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD5.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[5] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA05 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_TX_DATA[0] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_TX_DATA00 of instance: sai6
010 ALT2_AUDIOMIX_SAI6_RX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_DATA00 of instance: sai6
011 ALT3_AUDIOMIX_SAI1_RX_SYNC — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI1_RX_SYNC of instance: sai1
100 ALT4_ENET1_RGMII_RD1 — Select mux mode: ALT4 mux port: ENET1_RGMII_RD1 of instance:
enet1
101 ALT5_GPIO4_IO[7] — Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4
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8.2.4.86 SW_MUX_CTL_PAD_SAI1_RXD6 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6)
SW_MUX_CTL Register
Address: 3033_0000h base + 168h offset = 3033_0168h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD6
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_RXD6.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[6] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA06 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_TX_SYNC — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_TX_SYNC of instance: sai6
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI6_RX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_RX_SYNC of instance: sai6
100 ALT4_ENET1_RGMII_RD2 — Select mux mode: ALT4 mux port: ENET1_RGMII_RD2 of instance:
enet1
101 ALT5_GPIO4_IO[8] — Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4
8.2.4.87 SW_MUX_CTL_PAD_SAI1_RXD7 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7)
SW_MUX_CTL Register
Address: 3033_0000h base + 16Ch offset = 3033_016Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_RXD7
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI1_RXD7.
000 ALT0_AUDIOMIX_SAI1_RX_DATA[7] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_RX_DATA07 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_MCLK — Select mux mode: ALT1 mux port: AUDIOMIX_SAI6_MCLK of
instance: sai6
010 ALT2_AUDIOMIX_SAI1_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_SYNC of instance: sai1
011 ALT3_AUDIOMIX_SAI1_TX_DATA[4] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI1_TX_DATA04 of instance: sai1
100 ALT4_ENET1_RGMII_RD3 — Select mux mode: ALT4 mux port: ENET1_RGMII_RD3 of instance:
enet1
101 ALT5_GPIO4_IO[9] — Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4
8.2.4.88 SW_MUX_CTL_PAD_SAI1_TXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 170h offset = 3033_0170h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXFS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXFS.
000 ALT0_AUDIOMIX_SAI1_TX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_SYNC of instance: sai1
100 ALT4_ENET1_RGMII_RX_CTL — Select mux mode: ALT4 mux port: ENET1_RGMII_RX_CTL of
instance: enet1
101 ALT5_GPIO4_IO[10] — Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4
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8.2.4.89 SW_MUX_CTL_PAD_SAI1_TXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 174h offset = 3033_0174h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXC.
000 ALT0_AUDIOMIX_SAI1_TX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_BCLK of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXC field descriptions (continued)
Field Description
100 ALT4_ENET1_RGMII_RXC — Select mux mode: ALT4 mux port: ENET1_RGMII_RXC of instance:
enet1
101 ALT5_GPIO4_IO[11] — Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4
8.2.4.90 SW_MUX_CTL_PAD_SAI1_TXD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 178h offset = 3033_0178h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD0
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXD0.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA00 of instance: sai1
100 ALT4_ENET1_RGMII_TD0 — Select mux mode: ALT4 mux port: ENET1_RGMII_TD0 of instance:
enet1
101 ALT5_GPIO4_IO[12] — Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4
8.2.4.91 SW_MUX_CTL_PAD_SAI1_TXD1 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1)
SW_MUX_CTL Register
Address: 3033_0000h base + 17Ch offset = 3033_017Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD1
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXD1.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[1] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA01 of instance: sai1
100 ALT4_ENET1_RGMII_TD1 — Select mux mode: ALT4 mux port: ENET1_RGMII_TD1 of instance:
enet1
101 ALT5_GPIO4_IO[13] — Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4
8.2.4.92 SW_MUX_CTL_PAD_SAI1_TXD2 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2)
SW_MUX_CTL Register
Address: 3033_0000h base + 180h offset = 3033_0180h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD2
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXD2.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[2] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA02 of instance: sai1
100 ALT4_ENET1_RGMII_TD2 — Select mux mode: ALT4 mux port: ENET1_RGMII_TD2 of instance:
enet1
101 ALT5_GPIO4_IO[14] — Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4
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8.2.4.93 SW_MUX_CTL_PAD_SAI1_TXD3 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3)
SW_MUX_CTL Register
Address: 3033_0000h base + 184h offset = 3033_0184h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD3
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 3 iomux modes to be used for pad: SAI1_TXD3.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[3] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA03 of instance: sai1
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 field descriptions (continued)
Field Description
100 ALT4_ENET1_RGMII_TD3 — Select mux mode: ALT4 mux port: ENET1_RGMII_TD3 of instance:
enet1
101 ALT5_GPIO4_IO[15] — Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4
8.2.4.94 SW_MUX_CTL_PAD_SAI1_TXD4 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4)
SW_MUX_CTL Register
Address: 3033_0000h base + 188h offset = 3033_0188h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD4
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD4.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[4] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA04 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_RX_BCLK — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_RX_BCLK of instance: sai6
010 ALT2_AUDIOMIX_SAI6_TX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_BCLK of instance: sai6
100 ALT4_ENET1_RGMII_TX_CTL — Select mux mode: ALT4 mux port: ENET1_RGMII_TX_CTL of
instance: enet1
101 ALT5_GPIO4_IO[16] — Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4
8.2.4.95 SW_MUX_CTL_PAD_SAI1_TXD5 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5)
SW_MUX_CTL Register
Address: 3033_0000h base + 18Ch offset = 3033_018Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD5
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD5.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[5] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA05 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_RX_DATA[0] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_RX_DATA00 of instance: sai6
010 ALT2_AUDIOMIX_SAI6_TX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_DATA00 of instance: sai6
100 ALT4_ENET1_RGMII_TXC — Select mux mode: ALT4 mux port: ENET1_RGMII_TXC of instance:
enet1
101 ALT5_GPIO4_IO[17] — Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4
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8.2.4.96 SW_MUX_CTL_PAD_SAI1_TXD6 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6)
SW_MUX_CTL Register
Address: 3033_0000h base + 190h offset = 3033_0190h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD6
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD6.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[6] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA06 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_RX_SYNC — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI6_RX_SYNC of instance: sai6
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI6_TX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI6_TX_SYNC of instance: sai6
100 ALT4_ENET1_RX_ER — Select mux mode: ALT4 mux port: ENET1_RX_ER of instance: enet1
101 ALT5_GPIO4_IO[18] — Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4
8.2.4.97 SW_MUX_CTL_PAD_SAI1_TXD7 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7)
SW_MUX_CTL Register
Address: 3033_0000h base + 194h offset = 3033_0194h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_TXD7
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: SAI1_TXD7.
000 ALT0_AUDIOMIX_SAI1_TX_DATA[7] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI1_TX_DATA07 of instance: sai1
001 ALT1_AUDIOMIX_SAI6_MCLK — Select mux mode: ALT1 mux port: AUDIOMIX_SAI6_MCLK of
instance: sai6
011 ALT3_AUDIOMIX_PDM_CLK — Select mux mode: ALT3 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
100 ALT4_ENET1_TX_ER — Select mux mode: ALT4 mux port: ENET1_TX_ER of instance: enet1
101 ALT5_GPIO4_IO[19] — Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4
8.2.4.98 SW_MUX_CTL_PAD_SAI1_MCLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 198h offset = 3033_0198h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI1_MCLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SAI1_MCLK.
000 ALT0_AUDIOMIX_SAI1_MCLK — Select mux mode: ALT0 mux port: AUDIOMIX_SAI1_MCLK of
instance: sai1
010 ALT2_AUDIOMIX_SAI1_TX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI1_TX_BCLK of instance: sai1
100 ALT4_ENET1_TX_CLK — Select mux mode: ALT4 mux port: ENET1_TX_CLK of instance: enet1
101 ALT5_GPIO4_IO[20] — Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4
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8.2.4.99 SW_MUX_CTL_PAD_SAI2_RXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 19Ch offset = 3033_019Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_RXFS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI2_RXFS.
000 ALT0_AUDIOMIX_SAI2_RX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_RX_SYNC of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_SYNC — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_SYNC of instance: sai5
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IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI5_TX_DATA[1] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_TX_DATA01 of instance: sai5
011 ALT3_AUDIOMIX_SAI2_RX_DATA[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI2_RX_DATA01 of instance: sai2
100 ALT4_UART1_TX — Select mux mode: ALT4 mux port: UART1_TX of instance: uart1
101 ALT5_GPIO4_IO[21] — Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
8.2.4.100 SW_MUX_CTL_PAD_SAI2_RXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 1A0h offset = 3033_01A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_RXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI2_RXC.
000 ALT0_AUDIOMIX_SAI2_RX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_RX_BCLK of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_BCLK — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_BCLK of instance: sai5
011 ALT3_CAN1_TX — Select mux mode: ALT3 mux port: CAN1_TX of instance: can1
100 ALT4_UART1_RX — Select mux mode: ALT4 mux port: UART1_RX of instance: uart1
101 ALT5_GPIO4_IO[22] — Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
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8.2.4.101 SW_MUX_CTL_PAD_SAI2_RXD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 1A4h offset = 3033_01A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_RXD0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI2_RXD0.
000 ALT0_AUDIOMIX_SAI2_RX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_RX_DATA00 of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_DATA[0] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_DATA00 of instance: sai5
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IOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 field descriptions (continued)
Field Description
010 ALT2_ENET_QOS_1588_EVENT2_OUT — Select mux mode: ALT2 mux port:
ENET_QOS_1588_EVENT2_OUT of instance: enet_qos
011 ALT3_AUDIOMIX_SAI2_TX_DATA[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI2_TX_DATA01 of instance: sai2
100 ALT4_UART1_RTS_B — Select mux mode: ALT4 mux port: UART1_RTS_B of instance: uart1
101 ALT5_GPIO4_IO[23] — Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
8.2.4.102 SW_MUX_CTL_PAD_SAI2_TXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 1A8h offset = 3033_01A8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_TXFS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI2_TXFS.
000 ALT0_AUDIOMIX_SAI2_TX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_TX_SYNC of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_DATA[1] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_DATA01 of instance: sai5
010 ALT2_ENET_QOS_1588_EVENT3_OUT — Select mux mode: ALT2 mux port:
ENET_QOS_1588_EVENT3_OUT of instance: enet_qos
011 ALT3_AUDIOMIX_SAI2_TX_DATA[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI2_TX_DATA01 of instance: sai2
100 ALT4_UART1_CTS_B — Select mux mode: ALT4 mux port: UART1_CTS_B of instance: uart1
101 ALT5_GPIO4_IO[24] — Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
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Chapter 8 Chip IO and Pinmux
8.2.4.103 SW_MUX_CTL_PAD_SAI2_TXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 1ACh offset = 3033_01ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_TXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI2_TXC.
000 ALT0_AUDIOMIX_SAI2_TX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_TX_BCLK of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_DATA[2] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_DATA02 of instance: sai5
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_SAI2_TXC field descriptions (continued)
Field Description
011 ALT3_CAN1_RX — Select mux mode: ALT3 mux port: CAN1_RX of instance: can1
101 ALT5_GPIO4_IO[25] — Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
8.2.4.104 SW_MUX_CTL_PAD_SAI2_TXD0 SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0)
SW_MUX_CTL Register
Address: 3033_0000h base + 1B0h offset = 3033_01B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_TXD0
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI2_TXD0.
000 ALT0_AUDIOMIX_SAI2_TX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI2_TX_DATA00 of instance: sai2
001 ALT1_AUDIOMIX_SAI5_TX_DATA[3] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI5_TX_DATA03 of instance: sai5
010 ALT2_ENET_QOS_1588_EVENT2_IN — Select mux mode: ALT2 mux port:
ENET_QOS_1588_EVENT2_IN of instance: enet_qos
011 ALT3_CAN2_TX — Select mux mode: ALT3 mux port: CAN2_TX of instance: can2
100 ALT4_ENET_QOS_1588_EVENT2_AUX_IN — Select mux mode: ALT4 mux port:
ENET_QOS_1588_EVENT2_AUX_IN of instance: enet_qos
101 ALT5_GPIO4_IO[26] — Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4
8.2.4.105 SW_MUX_CTL_PAD_SAI2_MCLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 1B4h offset = 3033_01B4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI2_MCLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI2_MCLK.
000 ALT0_AUDIOMIX_SAI2_MCLK — Select mux mode: ALT0 mux port: AUDIOMIX_SAI2_MCLK of
instance: sai2
001 ALT1_AUDIOMIX_SAI5_MCLK — Select mux mode: ALT1 mux port: AUDIOMIX_SAI5_MCLK of
instance: sai5
010 ALT2_ENET_QOS_1588_EVENT3_IN — Select mux mode: ALT2 mux port:
ENET_QOS_1588_EVENT3_IN of instance: enet_qos
011 ALT3_CAN2_RX — Select mux mode: ALT3 mux port: CAN2_RX of instance: can2
100 ALT4_ENET_QOS_1588_EVENT3_AUX_IN — Select mux mode: ALT4 mux port:
ENET_QOS_1588_EVENT3_AUX_IN of instance: enet_qos
101 ALT5_GPIO4_IO[27] — Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4
110 ALT6_AUDIOMIX_SAI3_MCLK — Select mux mode: ALT6 mux port: AUDIOMIX_SAI3_MCLK of
instance: sai3
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8.2.4.106 SW_MUX_CTL_PAD_SAI3_RXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 1B8h offset = 3033_01B8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_RXFS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI3_RXFS.
000 ALT0_AUDIOMIX_SAI3_RX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_RX_SYNC of instance: sai3
001 ALT1_AUDIOMIX_SAI2_RX_DATA[1] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_RX_DATA01 of instance: sai2
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IOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI5_RX_SYNC — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_SYNC of instance: sai5
011 ALT3_AUDIOMIX_SAI3_RX_DATA[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI3_RX_DATA01 of instance: sai3
100 ALT4_AUDIOMIX_SPDIF1_IN — Select mux mode: ALT4 mux port: AUDIOMIX_SPDIF1_IN of
instance: spdif
101 ALT5_GPIO4_IO[28] — Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[0] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM00 of instance: pdm
8.2.4.107 SW_MUX_CTL_PAD_SAI3_RXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 1BCh offset = 3033_01BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_SAI3_RXC field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_RXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI3_RXC.
000 ALT0_AUDIOMIX_SAI3_RX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_RX_BCLK of instance: sai3
001 ALT1_AUDIOMIX_SAI2_RX_DATA[2] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_RX_DATA02 of instance: sai2
010 ALT2_AUDIOMIX_SAI5_RX_BCLK — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_BCLK of instance: sai5
011 ALT3_GPT1_CLK — Select mux mode: ALT3 mux port: GPT1_CLK of instance: gpt1
100 ALT4_UART2_CTS_B — Select mux mode: ALT4 mux port: UART2_CTS_B of instance: uart2
101 ALT5_GPIO4_IO[29] — Select mux mode: ALT5 mux port: GPIO4_IO29 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_CLK — Select mux mode: ALT6 mux port: AUDIOMIX_PDM_CLK of
instance: pdm
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8.2.4.108 SW_MUX_CTL_PAD_SAI3_RXD SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 1C0h offset = 3033_01C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_RXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI3_RXD.
000 ALT0_AUDIOMIX_SAI3_RX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_RX_DATA00 of instance: sai3
001 ALT1_AUDIOMIX_SAI2_RX_DATA[3] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_RX_DATA03 of instance: sai2
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IOMUXC_SW_MUX_CTL_PAD_SAI3_RXD field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI5_RX_DATA[0] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_DATA00 of instance: sai5
100 ALT4_UART2_RTS_B — Select mux mode: ALT4 mux port: UART2_RTS_B of instance: uart2
101 ALT5_GPIO4_IO[30] — Select mux mode: ALT5 mux port: GPIO4_IO30 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[1] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM01 of instance: pdm
8.2.4.109 SW_MUX_CTL_PAD_SAI3_TXFS SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS)
SW_MUX_CTL Register
Address: 3033_0000h base + 1C4h offset = 3033_01C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad SAI3_TXFS
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI3_TXFS.
000 ALT0_AUDIOMIX_SAI3_TX_SYNC — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_TX_SYNC of instance: sai3
001 ALT1_AUDIOMIX_SAI2_TX_DATA[1] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_TX_DATA01 of instance: sai2
010 ALT2_AUDIOMIX_SAI5_RX_DATA[1] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_DATA01 of instance: sai5
011 ALT3_AUDIOMIX_SAI3_TX_DATA[1] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI3_TX_DATA01 of instance: sai3
100 ALT4_UART2_RX — Select mux mode: ALT4 mux port: UART2_RX of instance: uart2
101 ALT5_GPIO4_IO[31] — Select mux mode: ALT5 mux port: GPIO4_IO31 of instance: gpio4
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[3] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM03 of instance: pdm
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8.2.4.110 SW_MUX_CTL_PAD_SAI3_TXC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC)
SW_MUX_CTL Register
Address: 3033_0000h base + 1C8h offset = 3033_01C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_TXC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 8 iomux modes to be used for pad: SAI3_TXC.
000 ALT0_AUDIOMIX_SAI3_TX_BCLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_TX_BCLK of instance: sai3
001 ALT1_AUDIOMIX_SAI2_TX_DATA[2] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_TX_DATA02 of instance: sai2
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IOMUXC_SW_MUX_CTL_PAD_SAI3_TXC field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI5_RX_DATA[2] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_DATA02 of instance: sai5
011 ALT3_GPT1_CAPTURE1 — Select mux mode: ALT3 mux port: GPT1_CAPTURE1 of instance:
gpt1
100 ALT4_UART2_TX — Select mux mode: ALT4 mux port: UART2_TX of instance: uart2
101 ALT5_GPIO5_IO[0] — Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5
110 ALT6_AUDIOMIX_PDM_BIT_STREAM[2] — Select mux mode: ALT6 mux port:
AUDIOMIX_PDM_BIT_STREAM02 of instance: pdm
8.2.4.111 SW_MUX_CTL_PAD_SAI3_TXD SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 1CCh offset = 3033_01CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_SAI3_TXD field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_TXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SAI3_TXD.
000 ALT0_AUDIOMIX_SAI3_TX_DATA[0] — Select mux mode: ALT0 mux port:
AUDIOMIX_SAI3_TX_DATA00 of instance: sai3
001 ALT1_AUDIOMIX_SAI2_TX_DATA[3] — Select mux mode: ALT1 mux port:
AUDIOMIX_SAI2_TX_DATA03 of instance: sai2
010 ALT2_AUDIOMIX_SAI5_RX_DATA[3] — Select mux mode: ALT2 mux port:
AUDIOMIX_SAI5_RX_DATA03 of instance: sai5
011 ALT3_GPT1_CAPTURE2 — Select mux mode: ALT3 mux port: GPT1_CAPTURE2 of instance:
gpt1
100 ALT4_AUDIOMIX_SPDIF1_EXT_CLK — Select mux mode: ALT4 mux port:
AUDIOMIX_SPDIF1_EXT_CLK of instance: spdif
101 ALT5_GPIO5_IO[1] — Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5
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8.2.4.112 SW_MUX_CTL_PAD_SAI3_MCLK SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 1D0h offset = 3033_01D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SAI3_MCLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: SAI3_MCLK.
000 ALT0_AUDIOMIX_SAI3_MCLK — Select mux mode: ALT0 mux port: AUDIOMIX_SAI3_MCLK of
instance: sai3
001 ALT1_PWM4_OUT — Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4
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IOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK field descriptions (continued)
Field Description
010 ALT2_AUDIOMIX_SAI5_MCLK — Select mux mode: ALT2 mux port: AUDIOMIX_SAI5_MCLK of
instance: sai5
100 ALT4_AUDIOMIX_SPDIF1_OUT — Select mux mode: ALT4 mux port: AUDIOMIX_SPDIF1_OUT
of instance: spdif
101 ALT5_GPIO5_IO[2] — Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5
110 ALT6_AUDIOMIX_SPDIF1_IN — Select mux mode: ALT6 mux port: AUDIOMIX_SPDIF1_IN of
instance: spdif
8.2.4.113 SW_MUX_CTL_PAD_SPDIF_TX SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX)
SW_MUX_CTL Register
Address: 3033_0000h base + 1D4h offset = 3033_01D4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
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IOMUXC_SW_MUX_CTL_PAD_SPDIF_TX field descriptions (continued)
Field Description
1 ENABLED — Force input path of pad SPDIF_TX
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SPDIF_TX.
000 ALT0_AUDIOMIX_SPDIF1_OUT — Select mux mode: ALT0 mux port: AUDIOMIX_SPDIF1_OUT
of instance: spdif
001 ALT1_PWM3_OUT — Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3
010 ALT2_I2C5_SCL — Select mux mode: ALT2 mux port: I2C5_SCL of instance: i2c5
011 ALT3_GPT1_COMPARE1 — Select mux mode: ALT3 mux port: GPT1_COMPARE1 of instance:
gpt1
100 ALT4_CAN1_TX — Select mux mode: ALT4 mux port: CAN1_TX of instance: can1
101 ALT5_GPIO5_IO[3] — Select mux mode: ALT5 mux port: GPIO5_IO03 of instance: gpio5
8.2.4.114 SW_MUX_CTL_PAD_SPDIF_RX SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX)
SW_MUX_CTL Register
Address: 3033_0000h base + 1D8h offset = 3033_01D8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_SPDIF_RX field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SPDIF_RX
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: SPDIF_RX.
000 ALT0_AUDIOMIX_SPDIF1_IN — Select mux mode: ALT0 mux port: AUDIOMIX_SPDIF1_IN of
instance: spdif
001 ALT1_PWM2_OUT — Select mux mode: ALT1 mux port: PWM2_OUT of instance: pwm2
010 ALT2_I2C5_SDA — Select mux mode: ALT2 mux port: I2C5_SDA of instance: i2c5
011 ALT3_GPT1_COMPARE2 — Select mux mode: ALT3 mux port: GPT1_COMPARE2 of instance:
gpt1
100 ALT4_CAN1_RX — Select mux mode: ALT4 mux port: CAN1_RX of instance: can1
101 ALT5_GPIO5_IO[4] — Select mux mode: ALT5 mux port: GPIO5_IO04 of instance: gpio5
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IOMUX Controller (IOMUXC)
8.2.4.115 SW_MUX_CTL_PAD_SPDIF_EXT_CLK SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 1DCh offset = 3033_01DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad SPDIF_EXT_CLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: SPDIF_EXT_CLK.
011 ALT3_GPT1_COMPARE3 — Select mux mode: ALT3 mux port: GPT1_COMPARE3 of instance:
gpt1
101 ALT5_GPIO5_IO[5] — Select mux mode: ALT5 mux port: GPIO5_IO05 of instance: gpio5
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK field descriptions (continued)
Field Description
000 ALT0_AUDIOMIX_SPDIF1_EXT_CLK — Select mux mode: ALT0 mux port:
AUDIOMIX_SPDIF1_EXT_CLK of instance: spdif
001 ALT1_PWM1_OUT — Select mux mode: ALT1 mux port: PWM1_OUT of instance: pwm1
8.2.4.116 SW_MUX_CTL_PAD_ECSPI1_SCLK SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 1E0h offset = 3033_01E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI1_SCLK
0 DISABLED — Input Path is determined by functionality
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI1_SCLK.
000 ALT0_ECSPI1_SCLK — Select mux mode: ALT0 mux port: ECSPI1_SCLK of instance: ecspi1
001 ALT1_UART3_RX — Select mux mode: ALT1 mux port: UART3_RX of instance: uart3
010 ALT2_I2C1_SCL — Select mux mode: ALT2 mux port: I2C1_SCL of instance: i2c1
011 ALT3_AUDIOMIX_SAI7_RX_SYNC — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_RX_SYNC of instance: sai7
101 ALT5_GPIO5_IO[6] — Select mux mode: ALT5 mux port: GPIO5_IO06 of instance: gpio5
8.2.4.117 SW_MUX_CTL_PAD_ECSPI1_MOSI SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI)
SW_MUX_CTL Register
Address: 3033_0000h base + 1E4h offset = 3033_01E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI1_MOSI
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI1_MOSI.
000 ALT0_ECSPI1_MOSI — Select mux mode: ALT0 mux port: ECSPI1_MOSI of instance: ecspi1
001 ALT1_UART3_TX — Select mux mode: ALT1 mux port: UART3_TX of instance: uart3
010 ALT2_I2C1_SDA — Select mux mode: ALT2 mux port: I2C1_SDA of instance: i2c1
011 ALT3_AUDIOMIX_SAI7_RX_BCLK — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_RX_BCLK of instance: sai7
101 ALT5_GPIO5_IO[7] — Select mux mode: ALT5 mux port: GPIO5_IO07 of instance: gpio5
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IOMUX Controller (IOMUXC)
8.2.4.118 SW_MUX_CTL_PAD_ECSPI1_MISO SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO)
SW_MUX_CTL Register
Address: 3033_0000h base + 1E8h offset = 3033_01E8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI1_MISO
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI1_MISO.
000 ALT0_ECSPI1_MISO — Select mux mode: ALT0 mux port: ECSPI1_MISO of instance: ecspi1
001 ALT1_UART3_CTS_B — Select mux mode: ALT1 mux port: UART3_CTS_B of instance: uart3
010 ALT2_I2C2_SCL — Select mux mode: ALT2 mux port: I2C2_SCL of instance: i2c2
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_SAI7_RX_DATA[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_RX_DATA00 of instance: sai7
101 ALT5_GPIO5_IO[8] — Select mux mode: ALT5 mux port: GPIO5_IO08 of instance: gpio5
8.2.4.119 SW_MUX_CTL_PAD_ECSPI1_SS0 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0)
SW_MUX_CTL Register
Address: 3033_0000h base + 1ECh offset = 3033_01ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI1_SS0
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI1_SS0.
000 ALT0_ECSPI1_SS0 — Select mux mode: ALT0 mux port: ECSPI1_SS0 of instance: ecspi1
001 ALT1_UART3_RTS_B — Select mux mode: ALT1 mux port: UART3_RTS_B of instance: uart3
010 ALT2_I2C2_SDA — Select mux mode: ALT2 mux port: I2C2_SDA of instance: i2c2
011 ALT3_AUDIOMIX_SAI7_TX_SYNC — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_TX_SYNC of instance: sai7
101 ALT5_GPIO5_IO[9] — Select mux mode: ALT5 mux port: GPIO5_IO09 of instance: gpio5
8.2.4.120 SW_MUX_CTL_PAD_ECSPI2_SCLK SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK)
SW_MUX_CTL Register
Address: 3033_0000h base + 1F0h offset = 3033_01F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI2_SCLK
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI2_SCLK.
000 ALT0_ECSPI2_SCLK — Select mux mode: ALT0 mux port: ECSPI2_SCLK of instance: ecspi2
001 ALT1_UART4_RX — Select mux mode: ALT1 mux port: UART4_RX of instance: uart4
010 ALT2_I2C3_SCL — Select mux mode: ALT2 mux port: I2C3_SCL of instance: i2c3
011 ALT3_AUDIOMIX_SAI7_TX_BCLK — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_TX_BCLK of instance: sai7
101 ALT5_GPIO5_IO[10] — Select mux mode: ALT5 mux port: GPIO5_IO10 of instance: gpio5
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8.2.4.121 SW_MUX_CTL_PAD_ECSPI2_MOSI SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI)
SW_MUX_CTL Register
Address: 3033_0000h base + 1F4h offset = 3033_01F4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI2_MOSI
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI2_MOSI.
000 ALT0_ECSPI2_MOSI — Select mux mode: ALT0 mux port: ECSPI2_MOSI of instance: ecspi2
001 ALT1_UART4_TX — Select mux mode: ALT1 mux port: UART4_TX of instance: uart4
010 ALT2_I2C3_SDA — Select mux mode: ALT2 mux port: I2C3_SDA of instance: i2c3
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI field descriptions (continued)
Field Description
011 ALT3_AUDIOMIX_SAI7_TX_DATA[0] — Select mux mode: ALT3 mux port:
AUDIOMIX_SAI7_TX_DATA00 of instance: sai7
101 ALT5_GPIO5_IO[11] — Select mux mode: ALT5 mux port: GPIO5_IO11 of instance: gpio5
8.2.4.122 SW_MUX_CTL_PAD_ECSPI2_MISO SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO)
SW_MUX_CTL Register
Address: 3033_0000h base + 1F8h offset = 3033_01F8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI2_MISO
0 DISABLED — Input Path is determined by functionality
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: ECSPI2_MISO.
101 ALT5_GPIO5_IO[12] — Select mux mode: ALT5 mux port: GPIO5_IO12 of instance: gpio5
000 ALT0_ECSPI2_MISO — Select mux mode: ALT0 mux port: ECSPI2_MISO of instance: ecspi2
001 ALT1_UART4_CTS_B — Select mux mode: ALT1 mux port: UART4_CTS_B of instance: uart4
010 ALT2_I2C4_SCL — Select mux mode: ALT2 mux port: I2C4_SCL of instance: i2c4
011 ALT3_AUDIOMIX_SAI7_MCLK — Select mux mode: ALT3 mux port: AUDIOMIX_SAI7_MCLK of
instance: sai7
100 ALT4_CCM_CLKO1 — Select mux mode: ALT4 mux port: CCM_CLKO1 of instance: ccm
8.2.4.123 SW_MUX_CTL_PAD_ECSPI2_SS0 SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0)
SW_MUX_CTL Register
Address: 3033_0000h base + 1FCh offset = 3033_01FCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad ECSPI2_SS0
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: ECSPI2_SS0.
000 ALT0_ECSPI2_SS0 — Select mux mode: ALT0 mux port: ECSPI2_SS0 of instance: ecspi2
001 ALT1_UART4_RTS_B — Select mux mode: ALT1 mux port: UART4_RTS_B of instance: uart4
010 ALT2_I2C4_SDA — Select mux mode: ALT2 mux port: I2C4_SDA of instance: i2c4
100 ALT4_CCM_CLKO2 — Select mux mode: ALT4 mux port: CCM_CLKO2 of instance: ccm
101 ALT5_GPIO5_IO[13] — Select mux mode: ALT5 mux port: GPIO5_IO13 of instance: gpio5
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8.2.4.124 SW_MUX_CTL_PAD_I2C1_SCL SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL)
SW_MUX_CTL Register
Address: 3033_0000h base + 200h offset = 3033_0200h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C1_SCL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: I2C1_SCL.
000 ALT0_I2C1_SCL — Select mux mode: ALT0 mux port: I2C1_SCL of instance: i2c1
001 ALT1_ENET_QOS_MDC — Select mux mode: ALT1 mux port: ENET_QOS_MDC of instance:
enet_qos
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IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL field descriptions (continued)
Field Description
011 ALT3_ECSPI1_SCLK — Select mux mode: ALT3 mux port: ECSPI1_SCLK of instance: ecspi1
101 ALT5_GPIO5_IO[14] — Select mux mode: ALT5 mux port: GPIO5_IO14 of instance: gpio5
8.2.4.125 SW_MUX_CTL_PAD_I2C1_SDA SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA)
SW_MUX_CTL Register
Address: 3033_0000h base + 204h offset = 3033_0204h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C1_SDA
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: I2C1_SDA.
000 ALT0_I2C1_SDA — Select mux mode: ALT0 mux port: I2C1_SDA of instance: i2c1
001 ALT1_ENET_QOS_MDIO — Select mux mode: ALT1 mux port: ENET_QOS_MDIO of instance:
enet_qos
011 ALT3_ECSPI1_MOSI — Select mux mode: ALT3 mux port: ECSPI1_MOSI of instance: ecspi1
101 ALT5_GPIO5_IO[15] — Select mux mode: ALT5 mux port: GPIO5_IO15 of instance: gpio5
8.2.4.126 SW_MUX_CTL_PAD_I2C2_SCL SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL)
SW_MUX_CTL Register
Address: 3033_0000h base + 208h offset = 3033_0208h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C2_SCL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: I2C2_SCL.
000 ALT0_I2C2_SCL — Select mux mode: ALT0 mux port: I2C2_SCL of instance: i2c2
001 ALT1_ENET_QOS_1588_EVENT1_IN — Select mux mode: ALT1 mux port:
ENET_QOS_1588_EVENT1_IN of instance: enet_qos
010 ALT2_USDHC3_CD_B — Select mux mode: ALT2 mux port: USDHC3_CD_B of instance: usdhc3
011 ALT3_ECSPI1_MISO — Select mux mode: ALT3 mux port: ECSPI1_MISO of instance: ecspi1
100 ALT4_ENET_QOS_1588_EVENT1_AUX_IN — Select mux mode: ALT4 mux port:
ENET_QOS_1588_EVENT1_AUX_IN of instance: enet_qos
101 ALT5_GPIO5_IO[16] — Select mux mode: ALT5 mux port: GPIO5_IO16 of instance: gpio5
8.2.4.127 SW_MUX_CTL_PAD_I2C2_SDA SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA)
SW_MUX_CTL Register
Address: 3033_0000h base + 20Ch offset = 3033_020Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C2_SDA
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: I2C2_SDA.
000 ALT0_I2C2_SDA — Select mux mode: ALT0 mux port: I2C2_SDA of instance: i2c2
001 ALT1_ENET_QOS_1588_EVENT1_OUT — Select mux mode: ALT1 mux port:
ENET_QOS_1588_EVENT1_OUT of instance: enet_qos
010 ALT2_USDHC3_WP — Select mux mode: ALT2 mux port: USDHC3_WP of instance: usdhc3
011 ALT3_ECSPI1_SS0 — Select mux mode: ALT3 mux port: ECSPI1_SS0 of instance: ecspi1
101 ALT5_GPIO5_IO[17] — Select mux mode: ALT5 mux port: GPIO5_IO17 of instance: gpio5
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8.2.4.128 SW_MUX_CTL_PAD_I2C3_SCL SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL)
SW_MUX_CTL Register
Address: 3033_0000h base + 210h offset = 3033_0210h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C3_SCL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: I2C3_SCL.
000 ALT0_I2C3_SCL — Select mux mode: ALT0 mux port: I2C3_SCL of instance: i2c3
001 ALT1_PWM4_OUT — Select mux mode: ALT1 mux port: PWM4_OUT of instance: pwm4
010 ALT2_GPT2_CLK — Select mux mode: ALT2 mux port: GPT2_CLK of instance: gpt2
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IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL field descriptions (continued)
Field Description
011 ALT3_ECSPI2_SCLK — Select mux mode: ALT3 mux port: ECSPI2_SCLK of instance: ecspi2
101 ALT5_GPIO5_IO[18] — Select mux mode: ALT5 mux port: GPIO5_IO18 of instance: gpio5
8.2.4.129 SW_MUX_CTL_PAD_I2C3_SDA SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA)
SW_MUX_CTL Register
Address: 3033_0000h base + 214h offset = 3033_0214h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C3_SDA
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: I2C3_SDA.
000 ALT0_I2C3_SDA — Select mux mode: ALT0 mux port: I2C3_SDA of instance: i2c3
001 ALT1_PWM3_OUT — Select mux mode: ALT1 mux port: PWM3_OUT of instance: pwm3
010 ALT2_GPT3_CLK — Select mux mode: ALT2 mux port: GPT3_CLK of instance: gpt3
011 ALT3_ECSPI2_MOSI — Select mux mode: ALT3 mux port: ECSPI2_MOSI of instance: ecspi2
101 ALT5_GPIO5_IO[19] — Select mux mode: ALT5 mux port: GPIO5_IO19 of instance: gpio5
8.2.4.130 SW_MUX_CTL_PAD_I2C4_SCL SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL)
SW_MUX_CTL Register
Address: 3033_0000h base + 218h offset = 3033_0218h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL field descriptions (continued)
Field Description
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C4_SCL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: I2C4_SCL.
000 ALT0_I2C4_SCL — Select mux mode: ALT0 mux port: I2C4_SCL of instance: i2c4
001 ALT1_PWM2_OUT — Select mux mode: ALT1 mux port: PWM2_OUT of instance: pwm2
010 ALT2_PCIE_CLKREQ_B — Select mux mode: ALT2 mux port: PCIE_CLKREQ_B of instance: pcie
011 ALT3_ECSPI2_MISO — Select mux mode: ALT3 mux port: ECSPI2_MISO of instance: ecspi2
101 ALT5_GPIO5_IO[20] — Select mux mode: ALT5 mux port: GPIO5_IO20 of instance: gpio5
8.2.4.131 SW_MUX_CTL_PAD_I2C4_SDA SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA)
SW_MUX_CTL Register
Address: 3033_0000h base + 21Ch offset = 3033_021Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad I2C4_SDA
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: I2C4_SDA.
000 ALT0_I2C4_SDA — Select mux mode: ALT0 mux port: I2C4_SDA of instance: i2c4
001 ALT1_PWM1_OUT — Select mux mode: ALT1 mux port: PWM1_OUT of instance: pwm1
011 ALT3_ECSPI2_SS0 — Select mux mode: ALT3 mux port: ECSPI2_SS0 of instance: ecspi2
101 ALT5_GPIO5_IO[21] — Select mux mode: ALT5 mux port: GPIO5_IO21 of instance: gpio5
8.2.4.132 SW_MUX_CTL_PAD_UART1_RXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART1_RXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 220h offset = 3033_0220h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_UART1_RXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART1_RXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: UART1_RXD.
000 ALT0_UART1_RX — Select mux mode: ALT0 mux port: UART1_RX of instance: uart1
001 ALT1_ECSPI3_SCLK — Select mux mode: ALT1 mux port: ECSPI3_SCLK of instance: ecspi3
101 ALT5_GPIO5_IO[22] — Select mux mode: ALT5 mux port: GPIO5_IO22 of instance: gpio5
8.2.4.133 SW_MUX_CTL_PAD_UART1_TXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART1_TXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 224h offset = 3033_0224h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_UART1_TXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART1_TXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: UART1_TXD.
000 ALT0_UART1_TX — Select mux mode: ALT0 mux port: UART1_TX of instance: uart1
001 ALT1_ECSPI3_MOSI — Select mux mode: ALT1 mux port: ECSPI3_MOSI of instance: ecspi3
101 ALT5_GPIO5_IO[23] — Select mux mode: ALT5 mux port: GPIO5_IO23 of instance: gpio5
8.2.4.134 SW_MUX_CTL_PAD_UART2_RXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART2_RXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 228h offset = 3033_0228h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_UART2_RXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART2_RXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: UART2_RXD.
000 ALT0_UART2_RX — Select mux mode: ALT0 mux port: UART2_RX of instance: uart2
001 ALT1_ECSPI3_MISO — Select mux mode: ALT1 mux port: ECSPI3_MISO of instance: ecspi3
011 ALT3_GPT1_COMPARE3 — Select mux mode: ALT3 mux port: GPT1_COMPARE3 of instance:
gpt1
101 ALT5_GPIO5_IO[24] — Select mux mode: ALT5 mux port: GPIO5_IO24 of instance: gpio5
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8.2.4.135 SW_MUX_CTL_PAD_UART2_TXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART2_TXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 22Ch offset = 3033_022Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_UART2_TXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART2_TXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: UART2_TXD.
000 ALT0_UART2_TX — Select mux mode: ALT0 mux port: UART2_TX of instance: uart2
001 ALT1_ECSPI3_SS0 — Select mux mode: ALT1 mux port: ECSPI3_SS0 of instance: ecspi3
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_UART2_TXD field descriptions (continued)
Field Description
011 ALT3_GPT1_COMPARE2 — Select mux mode: ALT3 mux port: GPT1_COMPARE2 of instance:
gpt1
101 ALT5_GPIO5_IO[25] — Select mux mode: ALT5 mux port: GPIO5_IO25 of instance: gpio5
8.2.4.136 SW_MUX_CTL_PAD_UART3_RXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART3_RXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 230h offset = 3033_0230h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_UART3_RXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART3_RXD
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_UART3_RXD field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: UART3_RXD.
000 ALT0_UART3_RX — Select mux mode: ALT0 mux port: UART3_RX of instance: uart3
001 ALT1_UART1_CTS_B — Select mux mode: ALT1 mux port: UART1_CTS_B of instance: uart1
010 ALT2_USDHC3_RESET_B — Select mux mode: ALT2 mux port: USDHC3_RESET_B of instance:
usdhc3
011 ALT3_GPT1_CAPTURE2 — Select mux mode: ALT3 mux port: GPT1_CAPTURE2 of instance:
gpt1
100 ALT4_CAN2_TX — Select mux mode: ALT4 mux port: CAN2_TX of instance: can2
101 ALT5_GPIO5_IO[26] — Select mux mode: ALT5 mux port: GPIO5_IO26 of instance: gpio5
8.2.4.137 SW_MUX_CTL_PAD_UART3_TXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART3_TXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 234h offset = 3033_0234h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_UART3_TXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART3_TXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: UART3_TXD.
000 ALT0_UART3_TX — Select mux mode: ALT0 mux port: UART3_TX of instance: uart3
001 ALT1_UART1_RTS_B — Select mux mode: ALT1 mux port: UART1_RTS_B of instance: uart1
010 ALT2_USDHC3_VSELECT — Select mux mode: ALT2 mux port: USDHC3_VSELECT of instance:
usdhc3
011 ALT3_GPT1_CLK — Select mux mode: ALT3 mux port: GPT1_CLK of instance: gpt1
100 ALT4_CAN2_RX — Select mux mode: ALT4 mux port: CAN2_RX of instance: can2
101 ALT5_GPIO5_IO[27] — Select mux mode: ALT5 mux port: GPIO5_IO27 of instance: gpio5
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8.2.4.138 SW_MUX_CTL_PAD_UART4_RXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART4_RXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 238h offset = 3033_0238h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_UART4_RXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART4_RXD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 7 iomux modes to be used for pad: UART4_RXD.
000 ALT0_UART4_RX — Select mux mode: ALT0 mux port: UART4_RX of instance: uart4
001 ALT1_UART2_CTS_B — Select mux mode: ALT1 mux port: UART2_CTS_B of instance: uart2
010 ALT2_PCIE_CLKREQ_B — Select mux mode: ALT2 mux port: PCIE_CLKREQ_B of instance: pcie
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_UART4_RXD field descriptions (continued)
Field Description
011 ALT3_GPT1_COMPARE1 — Select mux mode: ALT3 mux port: GPT1_COMPARE1 of instance:
gpt1
100 ALT4_I2C6_SCL — Select mux mode: ALT4 mux port: I2C6_SCL of instance: i2c6
101 ALT5_GPIO5_IO[28] — Select mux mode: ALT5 mux port: GPIO5_IO28 of instance: gpio5
8.2.4.139 SW_MUX_CTL_PAD_UART4_TXD SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_UART4_TXD)
SW_MUX_CTL Register
Address: 3033_0000h base + 23Ch offset = 3033_023Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_UART4_TXD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad UART4_TXD
0 DISABLED — Input Path is determined by functionality
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IOMUXC_SW_MUX_CTL_PAD_UART4_TXD field descriptions (continued)
Field Description
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 6 iomux modes to be used for pad: UART4_TXD.
000 ALT0_UART4_TX — Select mux mode: ALT0 mux port: UART4_TX of instance: uart4
001 ALT1_UART2_RTS_B — Select mux mode: ALT1 mux port: UART2_RTS_B of instance: uart2
011 ALT3_GPT1_CAPTURE1 — Select mux mode: ALT3 mux port: GPT1_CAPTURE1 of instance:
gpt1
100 ALT4_I2C6_SDA — Select mux mode: ALT4 mux port: I2C6_SDA of instance: i2c6
101 ALT5_GPIO5_IO[29] — Select mux mode: ALT5 mux port: GPIO5_IO29 of instance: gpio5
8.2.4.140 SW_MUX_CTL_PAD_HDMI_DDC_SCL SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SCL)
SW_MUX_CTL Register
Address: 3033_0000h base + 240h offset = 3033_0240h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
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IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SCL field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad HDMI_DDC_SCL
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: HDMI_DDC_SCL.
000 ALT0_HDMIMIX_HDMI_SCL — Select mux mode: ALT0 mux port: HDMIMIX_HDMI_SCL of
instance: hdmi
011 ALT3_I2C5_SCL — Select mux mode: ALT3 mux port: I2C5_SCL of instance: i2c5
100 ALT4_CAN1_TX — Select mux mode: ALT4 mux port: CAN1_TX of instance: can1
101 ALT5_GPIO3_IO[26] — Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3
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8.2.4.141 SW_MUX_CTL_PAD_HDMI_DDC_SDA SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA)
SW_MUX_CTL Register
Address: 3033_0000h base + 244h offset = 3033_0244h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad HDMI_DDC_SDA
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: HDMI_DDC_SDA.
000 ALT0_HDMIMIX_HDMI_SDA — Select mux mode: ALT0 mux port: HDMIMIX_HDMI_SDA of
instance: hdmi
011 ALT3_I2C5_SDA — Select mux mode: ALT3 mux port: I2C5_SDA of instance: i2c5
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IOMUX Controller (IOMUXC)
IOMUXC_SW_MUX_CTL_PAD_HDMI_DDC_SDA field descriptions (continued)
Field Description
100 ALT4_CAN1_RX — Select mux mode: ALT4 mux port: CAN1_RX of instance: can1
101 ALT5_GPIO3_IO[27] — Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3
8.2.4.142 SW_MUX_CTL_PAD_HDMI_CEC SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_HDMI_CEC)
SW_MUX_CTL Register
Address: 3033_0000h base + 248h offset = 3033_0248h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_HDMI_CEC field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad HDMI_CEC
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
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IOMUXC_SW_MUX_CTL_PAD_HDMI_CEC field descriptions (continued)
Field Description
MUX_MODE MUX Mode Select Field.
Select 1 of 4 iomux modes to be used for pad: HDMI_CEC.
000 ALT0_HDMIMIX_HDMI_CEC — Select mux mode: ALT0 mux port: HDMIMIX_HDMI_CEC of
instance: hdmi
011 ALT3_I2C6_SCL — Select mux mode: ALT3 mux port: I2C6_SCL of instance: i2c6
100 ALT4_CAN2_TX — Select mux mode: ALT4 mux port: CAN2_TX of instance: can2
101 ALT5_GPIO3_IO[28] — Select mux mode: ALT5 mux port: GPIO3_IO28 of instance: gpio3
8.2.4.143 SW_MUX_CTL_PAD_HDMI_HPD SW MUX Control Register
(IOMUXC_SW_MUX_CTL_PAD_HDMI_HPD)
SW_MUX_CTL Register
Address: 3033_0000h base + 24Ch offset = 3033_024Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved SION MUX_MODE
Reset
IOMUXC_SW_MUX_CTL_PAD_HDMI_HPD field descriptions
Field Description
31–5 This field is reserved.
- Reserved
4 Software Input On Field.
SION
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IOMUXC_SW_MUX_CTL_PAD_HDMI_HPD field descriptions (continued)
Field Description
Force the selected mux mode Input path no matter of MUX_MODE functionality.
1 ENABLED — Force input path of pad HDMI_HPD
0 DISABLED — Input Path is determined by functionality
3 This field is reserved.
- Reserved
MUX_MODE MUX Mode Select Field.
Select 1 of 5 iomux modes to be used for pad: HDMI_HPD.
000 ALT0_HDMIMIX_HDMI_HPD — Select mux mode: ALT0 mux port: HDMIMIX_HDMI_HPD of
instance: hdmi
001 ALT1_AUDIOMIX_HDMI_HPD_O — Select mux mode: ALT1 mux port: AUDIOMIX_HDMI_HPD_O
of instance: hdmi
011 ALT3_I2C6_SDA — Select mux mode: ALT3 mux port: I2C6_SDA of instance: i2c6
100 ALT4_CAN2_RX — Select mux mode: ALT4 mux port: CAN2_RX of instance: can2
101 ALT5_GPIO3_IO[29] — Select mux mode: ALT5 mux port: GPIO3_IO29 of instance: gpio3
8.2.4.144 SW_PAD_CTL_PAD_BOOT_MODE0 SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0)
SW_PAD_CTL Register
Address: 3033_0000h base + 250h offset = 3033_0250h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: BOOT_MODE0
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: BOOT_MODE0
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: BOOT_MODE0
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: BOOT_MODE0
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: BOOT_MODE0
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: BOOT_MODE0
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.145 SW_PAD_CTL_PAD_BOOT_MODE1 SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1)
SW_PAD_CTL Register
Address: 3033_0000h base + 254h offset = 3033_0254h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: BOOT_MODE1
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: BOOT_MODE1
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: BOOT_MODE1
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: BOOT_MODE1
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: BOOT_MODE1
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: BOOT_MODE1
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.146 SW_PAD_CTL_PAD_BOOT_MODE2 SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2)
SW_PAD_CTL Register
Address: 3033_0000h base + 258h offset = 3033_0258h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: BOOT_MODE2
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: BOOT_MODE2
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: BOOT_MODE2
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: BOOT_MODE2
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: BOOT_MODE2
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: BOOT_MODE2
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.147 SW_PAD_CTL_PAD_BOOT_MODE3 SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3)
SW_PAD_CTL Register
Address: 3033_0000h base + 25Ch offset = 3033_025Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: BOOT_MODE3
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: BOOT_MODE3
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: BOOT_MODE3
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: BOOT_MODE3
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: BOOT_MODE3
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: BOOT_MODE3
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.148 SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD)
SW_PAD_CTL Register
Address: 3033_0000h base + 260h offset = 3033_0260h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: JTAG_MOD
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: JTAG_MOD
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: JTAG_MOD
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: JTAG_MOD
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: JTAG_MOD
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: JTAG_MOD
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.149 SW_PAD_CTL_PAD_JTAG_TDI SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI)
SW_PAD_CTL Register
Address: 3033_0000h base + 264h offset = 3033_0264h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: JTAG_TDI
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: JTAG_TDI
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: JTAG_TDI
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: JTAG_TDI
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: JTAG_TDI
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: JTAG_TDI
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.150 SW_PAD_CTL_PAD_JTAG_TMS SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS)
SW_PAD_CTL Register
Address: 3033_0000h base + 268h offset = 3033_0268h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: JTAG_TMS
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: JTAG_TMS
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: JTAG_TMS
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: JTAG_TMS
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: JTAG_TMS
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: JTAG_TMS
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.151 SW_PAD_CTL_PAD_JTAG_TCK SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK)
SW_PAD_CTL Register
Address: 3033_0000h base + 26Ch offset = 3033_026Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: JTAG_TCK
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: JTAG_TCK
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: JTAG_TCK
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: JTAG_TCK
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: JTAG_TCK
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: JTAG_TCK
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.152 SW_PAD_CTL_PAD_JTAG_TDO SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO)
SW_PAD_CTL Register
Address: 3033_0000h base + 270h offset = 3033_0270h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: JTAG_TDO
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: JTAG_TDO
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: JTAG_TDO
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: JTAG_TDO
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: JTAG_TDO
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: JTAG_TDO
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.153 SW_PAD_CTL_PAD_GPIO1_IO00 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00)
SW_PAD_CTL Register
Address: 3033_0000h base + 274h offset = 3033_0274h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO00
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO00
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO00
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO00
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO00
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO00
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.154 SW_PAD_CTL_PAD_GPIO1_IO01 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01)
SW_PAD_CTL Register
Address: 3033_0000h base + 278h offset = 3033_0278h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO01
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO01
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO01
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO01
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO01
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO01
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.155 SW_PAD_CTL_PAD_GPIO1_IO02 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02)
SW_PAD_CTL Register
Address: 3033_0000h base + 27Ch offset = 3033_027Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO02
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO02
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO02
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO02
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO02
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO02
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.156 SW_PAD_CTL_PAD_GPIO1_IO03 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03)
SW_PAD_CTL Register
Address: 3033_0000h base + 280h offset = 3033_0280h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO03
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO03
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO03
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO03
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO03
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO03
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.157 SW_PAD_CTL_PAD_GPIO1_IO04 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04)
SW_PAD_CTL Register
Address: 3033_0000h base + 284h offset = 3033_0284h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO04
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO04
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO04
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO04
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO04
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO04
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.158 SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05)
SW_PAD_CTL Register
Address: 3033_0000h base + 288h offset = 3033_0288h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO05
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO05
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO05
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO05
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO05
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO05
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.159 SW_PAD_CTL_PAD_GPIO1_IO06 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06)
SW_PAD_CTL Register
Address: 3033_0000h base + 28Ch offset = 3033_028Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO06
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO06
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO06
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO06
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO06
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO06
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.160 SW_PAD_CTL_PAD_GPIO1_IO07 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07)
SW_PAD_CTL Register
Address: 3033_0000h base + 290h offset = 3033_0290h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO07
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO07
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO07
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO07
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO07
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO07
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.161 SW_PAD_CTL_PAD_GPIO1_IO08 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08)
SW_PAD_CTL Register
Address: 3033_0000h base + 294h offset = 3033_0294h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO08
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO08
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO08
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO08
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO08
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO08
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.162 SW_PAD_CTL_PAD_GPIO1_IO09 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09)
SW_PAD_CTL Register
Address: 3033_0000h base + 298h offset = 3033_0298h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO09
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO09
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO09
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO09
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO09
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO09
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.163 SW_PAD_CTL_PAD_GPIO1_IO10 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10)
SW_PAD_CTL Register
Address: 3033_0000h base + 29Ch offset = 3033_029Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO10
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO10
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO10
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO10
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO10
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO10
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.164 SW_PAD_CTL_PAD_GPIO1_IO11 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11)
SW_PAD_CTL Register
Address: 3033_0000h base + 2A0h offset = 3033_02A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO11
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO11
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO11
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO11
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO11
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO11
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.165 SW_PAD_CTL_PAD_GPIO1_IO12 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12)
SW_PAD_CTL Register
Address: 3033_0000h base + 2A4h offset = 3033_02A4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO12
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO12
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO12
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO12
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO12
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO12
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.166 SW_PAD_CTL_PAD_GPIO1_IO13 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13)
SW_PAD_CTL Register
Address: 3033_0000h base + 2A8h offset = 3033_02A8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO13
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO13
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO13
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO13
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO13
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO13
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.167 SW_PAD_CTL_PAD_GPIO1_IO14 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14)
SW_PAD_CTL Register
Address: 3033_0000h base + 2ACh offset = 3033_02ACh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO14
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO14
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO14
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO14
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO14
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO14
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.168 SW_PAD_CTL_PAD_GPIO1_IO15 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15)
SW_PAD_CTL Register
Address: 3033_0000h base + 2B0h offset = 3033_02B0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: GPIO1_IO15
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: GPIO1_IO15
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: GPIO1_IO15
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: GPIO1_IO15
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: GPIO1_IO15
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: GPIO1_IO15
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.169 SW_PAD_CTL_PAD_ENET_MDC SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDC)
SW_PAD_CTL Register
Address: 3033_0000h base + 2B4h offset = 3033_02B4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_MDC field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_MDC
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_MDC
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_MDC
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_MDC field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_MDC
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_MDC
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_MDC
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.170 SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO)
SW_PAD_CTL Register
Address: 3033_0000h base + 2B8h offset = 3033_02B8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_MDIO
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_MDIO
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_MDIO
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_MDIO
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_MDIO
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_MDIO
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.171 SW_PAD_CTL_PAD_ENET_TD3 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD3)
SW_PAD_CTL Register
Address: 3033_0000h base + 2BCh offset = 3033_02BCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TD3 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TD3
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TD3
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TD3
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TD3 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TD3
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TD3
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TD3
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.172 SW_PAD_CTL_PAD_ENET_TD2 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD2)
SW_PAD_CTL Register
Address: 3033_0000h base + 2C0h offset = 3033_02C0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TD2 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TD2
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TD2
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TD2
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TD2 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TD2
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TD2
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TD2
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.173 SW_PAD_CTL_PAD_ENET_TD1 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD1)
SW_PAD_CTL Register
Address: 3033_0000h base + 2C4h offset = 3033_02C4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TD1 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TD1
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TD1
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TD1
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TD1 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TD1
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TD1
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TD1
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.174 SW_PAD_CTL_PAD_ENET_TD0 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_TD0)
SW_PAD_CTL Register
Address: 3033_0000h base + 2C8h offset = 3033_02C8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TD0 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TD0
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TD0
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TD0
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TD0 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TD0
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TD0
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TD0
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.175 SW_PAD_CTL_PAD_ENET_TX_CTL SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL)
SW_PAD_CTL Register
Address: 3033_0000h base + 2CCh offset = 3033_02CCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TX_CTL
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TX_CTL
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TX_CTL
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TX_CTL
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TX_CTL
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TX_CTL
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.176 SW_PAD_CTL_PAD_ENET_TXC SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_TXC)
SW_PAD_CTL Register
Address: 3033_0000h base + 2D0h offset = 3033_02D0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_TXC field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_TXC
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_TXC
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_TXC
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_TXC field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_TXC
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_TXC
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_TXC
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
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IOMUX Controller (IOMUXC)
8.2.4.177 SW_PAD_CTL_PAD_ENET_RX_CTL SW PAD Control
Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL)
SW_PAD_CTL Register
Address: 3033_0000h base + 2D4h offset = 3033_02D4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RX_CTL
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RX_CTL
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RX_CTL
Table continues on the next page...
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Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RX_CTL
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RX_CTL
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RX_CTL
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1619
IOMUX Controller (IOMUXC)
8.2.4.178 SW_PAD_CTL_PAD_ENET_RXC SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_RXC)
SW_PAD_CTL Register
Address: 3033_0000h base + 2D8h offset = 3033_02D8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RXC field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RXC
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RXC
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RXC
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1620 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RXC field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RXC
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RXC
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RXC
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1621
IOMUX Controller (IOMUXC)
8.2.4.179 SW_PAD_CTL_PAD_ENET_RD0 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD0)
SW_PAD_CTL Register
Address: 3033_0000h base + 2DCh offset = 3033_02DCh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RD0 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RD0
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RD0
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RD0
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1622 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RD0 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RD0
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RD0
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RD0
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1623
IOMUX Controller (IOMUXC)
8.2.4.180 SW_PAD_CTL_PAD_ENET_RD1 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD1)
SW_PAD_CTL Register
Address: 3033_0000h base + 2E0h offset = 3033_02E0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RD1 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RD1
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RD1
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RD1
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1624 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RD1 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RD1
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RD1
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RD1
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1625
IOMUX Controller (IOMUXC)
8.2.4.181 SW_PAD_CTL_PAD_ENET_RD2 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD2)
SW_PAD_CTL Register
Address: 3033_0000h base + 2E4h offset = 3033_02E4h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RD2 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RD2
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RD2
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RD2
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1626 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RD2 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RD2
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RD2
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RD2
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1627
IOMUX Controller (IOMUXC)
8.2.4.182 SW_PAD_CTL_PAD_ENET_RD3 SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_ENET_RD3)
SW_PAD_CTL Register
Address: 3033_0000h base + 2E8h offset = 3033_02E8h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_ENET_RD3 field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: ENET_RD3
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: ENET_RD3
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: ENET_RD3
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1628 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_ENET_RD3 field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: ENET_RD3
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: ENET_RD3
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: ENET_RD3
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1629
IOMUX Controller (IOMUXC)
8.2.4.183 SW_PAD_CTL_PAD_SD1_CLK SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
SW_PAD_CTL Register
Address: 3033_0000h base + 2ECh offset = 3033_02ECh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
Reset
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reserved PE HYS PUE ODE FSEL DSE
Reset
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK field descriptions
Field Description
31–9 This field is reserved.
- Reserved
8 Pull Select Field
PE
Select one out of next values for pad: SD1_CLK
0 PE_0_PULL_DISABLE — Pull Disable
1 PE_1_PULL_ENABLE — Pull Enable
7 Input Select Field
HYS
Select one out of next values for pad: SD1_CLK
0 HYS_0_CMOS — CMOS
1 HYS_1_SCHMITT — Schmitt
6 Pull Up / Down Config. Field
PUE
Select one out of next values for pad: SD1_CLK
Table continues on the next page...
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
1630 NXP Semiconductors
Chapter 8 Chip IO and Pinmux
IOMUXC_SW_PAD_CTL_PAD_SD1_CLK field descriptions (continued)
Field Description
0 PUE_0_WEAK_PULL_DOWN — Weak pull down
1 PUE_1_WEAK_PULL_UP — Weak pull up
5 Open Drain Field
ODE
Select one out of next values for pad: SD1_CLK
0 ODE_0_OPEN_DRAIN_DISABLE — Open Drain Disable
1 ODE_1_OPEN_DRAIN_ENABLE — Open Drain Enable
4 Slew Rate Field
FSEL
Select one out of next values for pad: SD1_CLK
0 FSEL_0_SLOW_SLEW_RATE — Slow Slew Rate (SR=1)
1 FSEL_1_FAST_SLEW_RATE — Fast Slew Rate (SR=0)
3 This field is reserved.
- Reserved
2–1 Drive Strength Field
DSE
Select one out of next values for pad: SD1_CLK
00 DSE_X1 — X1
10 DSE_X2 — X2
01 DSE_X4 — X4
11 DSE_X6 — X6
0 This field is reserved.
- Reserved
i.MX 8M Plus Applications Processor Reference Manual, Rev. 2, 02/2024
NXP Semiconductors 1631
IOMUX Controller (IOMUXC)
8.2.4.184 SW_PAD_CTL_PAD_SD1_CMD SW PAD Control Register
(IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
SW_PAD_CTL Register
Address: 3033_0000h base + 2F0h offset = 3033_02F0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
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