SIMP with Answers

MODULE-5
1. Write and explain the control sequence for execution of the instruction ADD
(R3), R1 on a single bus processor
OR
Write and explain the control sequence for execution of an unconditional
branch instruction
• Here the processor contain only a single bus for the movement of data,
address and instructions.
• ALU and all the registers are interconnected via a Single Common Bus
• Data & address lines of the external memory-bus is connected to the
internalprocessor-bus via MDR & MAR respectively.
EXECUTION OF A COMPLETE INSTRUCTION :
• Consider the instruction Add (R3),R1 which adds the contents of a memory-
locationpointed by R3 to register R1.
• Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand.
3) Perform the addition
4) Load the result into R1. THE fig gives the sequence of control steps required
to perform these operations for the single -bus architecture .
➢ Step1--> The instruction-fetch operation is initiated by loading contents of PC
into MAR & sending a Read request to memory. The Select signal is set to
Select4, which causes the Mux to select constant 4. This value is added to
operand at input B (PC‟s content), and the result is stored in Z.
➢ Step2--> Updated value in Z is moved to PC. This completes the PC increment
operation and PC will now point to next instruction.
➢ Step3--> Fetched instruction is moved into MDR and then to IR. The step 1
through 3constitutes the Fetch Phase. ➢ At the beginning of step 4, the
instruction decoder interprets the contents of the IR. This enables the control
circuitry to activate the control-signals for steps 4 through 7. The step 4 through
7 constitutes the Execution Phase.
➢ Step4--> Contents of R3 are loaded into MAR & a memory read signal is
issued
➢ Step5--> Contents of R1 are transferred to Y to prepare for addition.
➢Step6--> When Read operation is completed, memory-operand is available in
MDR,
➢ Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a
new instruction fetch cycle to begin by returning to step1.
3. With a neat diagram explaining single bus processor data path wrt
organization of computer and fundamental concepts
SINGLE BUS ORGANIZATION:

• Here the processor contain only a single bus for the movement of data,
address and instructions.
• ALU and all the registers are interconnected via a Single Common Bus
• Data & address lines of the external memory-bus is connected to the
internalprocessor-bus via MDR & MAR respectively. (MDR -> Memory Data
Register, MAR -> Memory Address Register).
• MDR has 2 inputs and 2 outputs.
Data may be loaded → into MDR either from memory-bus (external) or → from
processor-bus (internal).
• MAR‟s input is connected to internal-bus; MAR‟s output is connected to
external- bus. (address sent from processor to memory only)
• Instruction Decoder & Control Unit is responsible for → Decoding the
instruction and issuing the control-signals to all the units inside the processor.
→ implementing the actions specified by the instruction (loaded in the IR).
• Processor Registers - Register R0 through R(n-1) are also called as
GeneralPurpose Register. The programmer can access these registers for
general-purpose use.
• Temporary Registers – There are 3 temporary registers in the processor.
Registers - Y, Z & Temp are used for temporary storage during program
execution. The programmer cannot access these 3 registers.
• In ALU,
1) “A‟ input gets the operand from the output of the multiplexer (MUX).
2) “B‟ input gets the operand directly from the processor-bus.
• There are 2 options provided for “A‟ input of the ALU.
• MUX is used to select one of the 2 inputs.
• MUX selects either → output of Y or → constant-value 4( which is used to
increment PC content).
• An instruction is executed by performing one or more of the following
operations:
1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.
• Disadvantage: Only one data-word can be transferred over the bus in a clock
cycle. Solution: Provide multiple internal-paths. Multiple paths allow several
data- transfers to take place in parallel.

5. Write a note on register transfer and ALU operation

REGISTER TRANSFERS
• Instruction execution involves a sequence of steps in which data are
transferredfrom one register to another.
• For each register, two control-signals are used: Riin & Riout. These are called
Gating Signals
• Riin=1,the data on the bus are loaded into Ri,
• Riout=1,the contents of register are placed on the bus,
• Riout=0,the bus can be used for transferring data from other registers.
Suppose we wish to transfer the contents of register R1 to register R2.This can
be accomplished as follows: 1. Enable the output of registers R1 by setting
R1out to 1 . This places the contents of R1 on processor-bus. 2. Enable the input
of register R4 by setting R4in to 1.This loads data from processor-bus into
register R4.
• All operations and data transfers within the processor take place within time-
periods defined by the processor-clock.
• The control-signals that govern a particular transfer are asserted at the start of
the clock cycle.

PERFORMING AN ARITHMETIC OR LOGIC OPERATION (refer fig:7.2)

• The ALU is a combinational circuit that has no internal storage.
• The ALU performs arithmetic and logic operations on the 2 operands applied
to its A and B inputs.
• ALU gets the two operands, one is from MUX and another from bus. The result
is temporarily stored in register Z.
• Therefore, a sequence of operations [R3]=[R1]+[R2]. 1) R1out, Yin 2) R2out,
Select Y, Add, Zin 3) Zout, R3in Instruction execution proceeds as follows:
Step 1 --> Contents from register R1 are loaded into register Y.
Step2 --> Contents from Y and from register R2 are applied to the A and B
inputs of ALU; Addition is performed & Result is stored in the Z register.
Step 3 --> The contents of Z register is stored in the R3 register.
• The signals are activated for the duration of the clock cycle corresponding to
that step. All other signals are inactive.

6. Briefly explain fetching a word from memory and storing a word in memory
FETCHING A WORD FROM MEMORY
• To fetch instruction/data from memory, the processor has to specify the
address of the memory location where this information is stored and request a
Read operation.
• processor transfers required address to MAR .At the same time, processor
issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR.
From MDR, they are transferred to other registers in the processor.
Storing a Word in Memory
• Consider the instruction Move R2,(R1). This requires the following sequence:
1) R1out, MARin ; desired address is loaded into MAR.
2) R2out,MDRin ,Write ;data to be written are loaded into MDR & Write
command is issued.
3) MDRoutE, WMFC ;load data into memory-location pointed by R1 from MDR

7. Explain in detail (i) Hazards and its types with examples (ii) pipeline
performance (iii)role of cache in pipelining (iv)process of fetching a word from
memory with diagram
HAZARDS:
Any condition that causes the pipeline to stall is called a hazard.

1) A data hazard is any condition in which either the source or the destination operands of an instruction are not
available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.

2) control hazards or instruction hazards: The pipeline may also be stalled because of a delay in the availability of
an instruction. For example, this may be a result of a miss in the cache .

3) A third type of hazard known as a structural hazard: This is the situation when two instructions require the use
of a given hardware resource at the same time.

DATA HAZARD EX:

INSTRUCTION HAZARD EX:

STRUCTURAL HAZARD EX:

(II) PIPELINE PERFORMANCE:
➢ The potential increase in performance resulting from pipelining is
proportional to the number of pipeline stages. ➢ However, this increase would
be achieved only if pipelined operation as depicted in Figure a could be
sustained without interruption throughout program execution.
➢ Unfortunately, this is not the True.
➢ Floating point may involve many clock cycle.
➢ For a variety of reasons, one of the pipeline stages may not be able to
complete its processing task for a given instruction in the time allotted. For
example, stage E in the four stage pipeline of Figure b is responsible for
arithmetic and logic operations, and one clock cycle is assigned for this task.
Although this may be sufficient for most operations, some operations, such as
divide, may require more time to complete. Figure shows an example in which
the operation specified in instruction I2 requires three cycles to complete, from
cycle 4 through cycle 6. Thus, in cycles 5 and 6, the Write stage must be told to
do nothing, because it has no data to work with. Meanwhile, the information in
buffer B2 must remain intact until the Execute stage has completed its
operation. This means that stage 2 and, in turn, stage 1 are blocked from
accepting new instructions because the information in B1 cannot be
overwritten. Thus, steps D4 and F5 must be postponed as shown.
Pipelined operation in Figure 8.3 is said to have been stalled for two clock
cycles. Normal pipelined operation resumes in cycle 7

 The effect of a cache miss on pipelined operation is illustrated in Figure.

  Instruction I1 is fetched from the cache in cycle 1, and its execution
proceeds normally. However, the fetch operation for instruction I2, which
is started in cycle 2, results in a cache miss.
 The instruction fetch unit must now suspend any further fetch requests
and wait for I2 to arrive. We assume that instruction I2 is received and
loaded into buffer B1 at the end of cycle 5. The pipeline resumes its
normal operation at that point.

If instructions and data reside in the same cache unit, only one instruction can
proceed and the other instruction is delayed. Many processors use separate
instruction and data caches to avoid this delay.
It is important to understand that pipelining does not result in individual
instructions being executed faster; rather, it is the throughput that increases,
where throughput is measured by the rate at which instruction execution is
completed. The pipeline stalls, causes degradation in pipeline performance. We
need to identify all hazards that may cause the pipeline to stall and to find ways
to minimize their impact.

(III)ROLE OF CACHE IN PIPELINING

1. Each stage in a pipeline is expected to complete its operation in one clock
cycle.
2. Hence, the clock period should be sufficiently long to complete the task
being performed in any stage. If different units require different amounts
of time, the clock period must allow the longest task to be completed.

3. A unit that completes its task early is idle for the remainder of the clock
period.
 4. Hence, pipelining is most effective in improving performance if the tasks
being performed in different stages require about the same amount of
time. This consideration is particularly important for the instruction fetch
step, which is assigned one clock period.

5. The clock cycle has to be equal to or greater than the time needed to
complete a fetch operation. However, the access time of the main
memory may be as much as ten times greater than the time needed to
perform basic pipeline stage operations inside the processor, such as
adding two numbers.

6. Thus, if each instruction fetch required access to the main memory,

pipelining would be of little value. The use of cache memories solves the
memory access problem. In particular, when a cache is included on the
same chip as the processor, access time to the cache is usually the same as
the time needed to perform other basic operations inside the processor.

7. This makes it possible to divide instruction fetching and processing into

steps that are more or less equal in duration. Each of these steps is
performed by a different pipeline stage, and the clock period is chosen to
correspond to the longest one.

IV)PROCESS OF FETCHING A WORD FROM MEMORY WITH DIAGRAM

FETCHING A WORD FROM MEMORY •

To fetch instruction/data from memory, the processor has to specify the

address of the memory location where this information is stored and request a
Read operation.
• processor transfers required address to MAR.At the same time, processor
issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR.
FromMDR, they are transferred to other registers in the processor. The
Connections for register MDR has shown in fig 7.4
 8. What is a stall or bubble in the pipeline? Explain in detail with example

 The effect of a cache miss on pipelined operation is illustrated in Figure.

 Instruction I1 is fetched from the cache in cycle 1, and its execution
proceeds normally. However, the fetch operation for instruction I2, which
is started in cycle 2, results in a cache miss.
 The instruction fetch unit must now suspend any further fetch requests
and wait for I2 to arrive. We assume that instruction I2 is received and
loaded into buffer B1 at the end of cycle 5. The pipeline resumes its
normal operation at that point.
 An alternative representation of the operation of a pipeline in the case of
a cache miss is shown in Figure b. This figure gives the function performed
by each pipeline stage in each clock cycle.

 Note that the Decode unit is idle in cycles 3 through 5, the Execute unit is
idle in cycles 4 through 6, and the Write unit is idle in cycles 5 through 7.
Such idle periods are called stalls. They are also often referred to as
bubbles in the pipeline.
 Eg: If instructions and data reside in the same cache unit, only one
instruction can proceed and the other instruction is delayed. Many
processors use separate instruction and data caches to avoid this delay
 MODULE-4
1. How the input and output are performed by the processor? Write a program
that reads the line or characters and displays
There are a number of input/output (I/O) devices, that can be connected to a
computer.
The input maybe from a keyboard, a sensor, switch, mouse etc. Similarly output
may be a speaker, monitor, printer, a digital display etc. These variety of I/O
devices exchange information in varied format, having different word length,
transfer speed is different, but are connected to the same system and exchange
information with the same computer. Computer must be capable of handling
these wide variety of devices.
ACCESSING I/O-DEVICES A single bus-structure can be used for connecting I/O-
devices to a computer. The simple arrangement of connecting set of I/O devices
to memory and processor by means of system bus is as shown in the figure.
Such an arrangement is called as Single Bus Organization.
• The system bus enables all the devices connected to it to involve in the data
transfer operation.
• The system bus establishes data communication between I/O device and
processor.
• Each I/O device is assigned a unique set of address.
• When processor places an address on address-lines, the intended device
responds to the command.
• The processor requests either a read or write-operation.
• The requested data are transferred over the data-lines

2. Differentiate memory mapped I/O and I/O mapped I/O

3. With neat sketches explain various methods for handling multiple
interrupts raised by multiple devices. (or explain how I/O devices are
organized in priority structure)

HANDLING MULTIPLE DEVICES While handling multiple devices, the issues

concerned are:
VECTORED INTERRUPT
• A device requesting an interrupt identifies itself by sending a special-code to
processor over bus.
• Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR.
• The special-code length ranges from 4 to 8 bits.
• The location pointed to by the interrupting-device is used to store the staring
address to ISR.
• The staring address to ISR is called the interrupt vector.
• Processor → loads interrupt-vector into PC & → executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA
line.
• Then, I/O-device responds by sending its interrupt-vector code & turning off
the INTR signal.
• The interrupt vector also includes a new value for the Processor Status
Register
INTERRUPT NESTING
• A multiple-priority scheme is implemented by using separate INTR & INTA
lines for each device
• Each INTR line is assigned a different priority-level as shown in Figure.
• Each device has a separate interrupt-request and interrupt-acknowledge line.
• Each interrupt-request line is assigned a different priority level.
• Interrupt requests received over these lines are sent to a priority arbitration
circuit in the processor.
• If the interrupt request has a higher priority level than the priority of the
processor, then the request is accepted.
• Priority-level of processor is the priority of program that is currently being
executed.
• Processor accepts interrupts only from devices that have higher-priority than
its own.
• At the time of execution of ISR for some device, priority of processor is raised
to that of the device.
• Thus, interrupts from devices at the same level of priority or lower are
disabled.

SIMULTANEOUS REQUESTS
DAISY CHAIN
• The daisy chain with multiple priority levels is as shown in the figure.
• The interrupt request line INTR is common to all devices as shown in the fig.
• The interrupt acknowledge line is connected in a daisy fashion as shown in the
figure.
• This signal propagates serially from one device to another device.
• The several devices raise an interrupt by activating INTR signal. In response to
the signal, processor transfers its device by activating INTA signal.
• This signal is received by device 1. The device-1 blocks the propagation of
INTA signal to device-2,when it needs processor service.
• The device-1 transfers the INTA signal to next device when it does not require
the processor service.
• In daisy chain arrangement device-1 has the highest priority.
Advantage: It requires fewer wires than the individual connection
ARRANGEMENT OF PRIORITY GROUPS
• In this technique, devices are organizes in a group and each group is
connected to the processor at a different priority level.
• With in a group devices are connected in a daisy chain fashion as shown in the
figure.

4. Define Interrupt and interrupt hardware. how enabling and disabling of

interrupts are performed.
Interrupt
• It is an event which suspends the execution of one program and begins the
execution of another program.
INTERRUPT HARDWARE
• The external device (I/O device) sends interrupt request to the processor by
activating a bus line and called as interrupt request line.
• All I/O device uses the same single interrupt-request line.
• One end of this interrupt request line is connected to input power supply by
means of a register.
• The another end of interrupt request line is connected to INTR (Interrupt
request) signal of processor as shown in the fig.
• The I/O device is connected to interrupt request line by means of switch,
which is grounded as shown in the fig.
• When all the switches are open the voltage drop on interrupt request line is
equal to the VDD and INTR value at process is 0.
• This state is called as in-active state of the interrupt request line.
• The I/O device interrupts the processor by closing its switch.
• When switch is closed the voltage drop on the interrupt request line is found
to be zero, as the switch is grounded, hence INTR=0 and INTR=1.
• The signal on the interrupt request line is logical OR of requests from the
several I/O devices. Therefore, INTR=INTR1 + INTR2 + + INTR n
ENABLING AND DISABLING THE INTERRUPTS
The arrival of interrupt request from external devices or from within a process,
causes the suspension of on-going execution and start the execution of another
program.
• Interrupt arrives at any time and it alters the sequence of execution. Hence
the interrupt to be executed must be selected carefully.
• All computers can enable and disable interruptions as desired.
• When an interrupt is under execution, other interrupts should not be invoked.
This is performed in a system in different ways. • The problem of infinite loop
occurs due to successive interruptions of active INTR signals.

6. Explain operation of DMA controller with neat block diagram

Direct Memory Access (DMA)
• It is the process of transferring the block of data at high speed in between
main memory and external device (I/O devices) without continuous intervention
of CPU is called as DMA.
• The DMA operation is performed by one control circuit and is part of the I/O
interface
• This control circuit is called DMA controller. Hence DMA transfer operation is
performed by DMAcontroller.
• To initiate Directed data transfer between main memory and external devices
DMA controller needsparameters from the CPU.
• These 3 Parameters are:
1)Starting address of the memory block.
2)No of words to be transferred.
3)Type of operation (Read or Write).
The computer with DMA controller is as shown in the fig.:
• The DMA controller connects two external devices namely disk 1 and disk 2 to
system bus as shown in the above fig
• The DMA controller also interconnects high speed network devices to system
bus as shown in the above fig.
• Let us consider direct data transfer operation by means of DMA controller
without the involvement of CPU in between main memory and disk 1 as
indicated by dotted lines (in the fig.).
• To establish direct data transfer operation between main memory and disk
1. DMA controller request the processor to obtain 3 parameters namely:
1) Starting address of the memory block.
2) No of words to be transferred.
3) Type of operation (Read or Write).
• After receiving these 3 parameters from processor, DMA controller directly
transfers block of data main memory and external devices (disk 1).
• This information is informed to CPU by setting respective bits in the status and
controller register of DMA controller. These are 2 types of request with respect
to system bus1). CPU request. 2). DMA request. Highest priority will be given to
DMA request.
• Actually the CPU generates memory cycles to perform read and write
operations. The DMA controller steals memory cycles from the CPU to perform
read and write operations. This approach is called as “Cycle stealing”.
• An exclusive option will be given for DMA controller to transfer block of data
from external devices to main memory and from main memory to external
devices. This technique is called as “Burst mode of operation”.

7. Define DMA bus arbitration. Explain centralized and distributed bus

arbitration
BUS ARBITRATION
• Any device which initiates data transfer operation on bus at any instant of
time is called as Bus-Master.
• When the bus mastership is transferred from one device to another device,
the next device is ready to obtain the bus mastership.
• The bus-mastership is transferred from one device to another device based
on the principle of priority system. There are two types of bus-arbitration
technique:
a) Centralized bus arbitration:
In this technique CPU acts as a bus-master or any control unit connected to bus
can be acts as a bus master. The schematic diagram of centralized bus
arbitration is as shown in the fig.:

The following steps are necessary to transfer the bus mastership from CPU to
one of the DMA controller:
• The DMA controller request the processor to obtain the bus mastership by
activating BR (Bus request) signal
• In response to this signal the CPU transfers the bus mastership to requested
devices DMAcontroller1 in the form of BG (Bus grant).
• When the bus mastership is obtained from CPU the DMA controller1 blocks
the propagation of bus grant signal from one device to another device.
• The BG signal is connected to DMA controller2 from DMA controller1 in as
daisy fashion style is as shown in the figure.
• When the DMA controller1 has not sent BR request, it transfers the bus
mastership to DMAcontroller2 by unblocking bus grant signal.
• When the DMA controller1 receives the bus grant signal, it blocks the signal
from passing to DMA controller2 and enables BBSY signal. When BBSY signal is
set to 1 the set of devices connected to system bus doesn’t have any rights to
obtain the bus mastership from the CPU.

B )Distributed bus arbitration:

• In this technique 2 or more devices trying to access system bus at the same
time may participate in bus arbitration process
. • The schematic diagram of distributed bus arbitration is as shown in the figure
:

• The external device requests the processor to obtain bus mastership by

enabling start arbitration signal.
• In this technique 4 bit code is assigned to each device to request the CPU in
order to obtain bus mastership.
• Two or more devices request the bus by placing 4 bit code over the system
bus.
• The signals on the bus interpret the 4 bit code and produces winner as a result
from the CPU.
• When the input to the one driver = 1, and input to the another driver = 0, on
the same bus line,this state is called as “Low level voltage state of bus”.
• Consider 2 devices namely A & B trying to access bus mastership at the same
time. Let assigned code for devices A & B are 5 (0101) & 6 (0110) respectively.
• The device A sends the pattern (0101) and device B sends its pattern (0110)
to master. The signals on the system bus interpret the 4 bit code for devices A &
B produces device B as a winner.
• The device B can obtain the bus mastership to initiate direct data transfer
between external devices and main memory.

8. Draw a neat diagram of memory hierarchy in a computer system. Discuss

the variation of size, speed and cost per bit in the hierarchy
The Memory System Speed, Size and Cost
The block diagram of memory hierarchy is as shown in the figure:
• Registers: The fastest access is to data held in registers. Hence
registers are part of the memory hierarchy. More speed, small size and
cost per bit is also more.
• At the next level of hierarchy, small amount of memory can be
directly implemented on the processor chip.
• This memory is called as processor cache. It holds the copy of
recently accessed data and instructions. There are 2 levels of caches viz
level-1 and level-2. Level-1 cache is part of the processor and level-2
cache is placed in between level-1 cache and main memory.
• The level-2 cache is implemented using SRAM chips
• The next level in the memory hierarchy is called as main memory. It
is implemented using dynamic memory components (DRAM). The main
memory is larger but slower than cache memory. The access time for
main memory is ten times longer than the cache memory
• The level next in the memory hierarchy is called as secondary
memory. It holds huge amount of data.

• The main-memory is built with DRAM

• SRAMs are used in cache memory, where speed is essential.
• The Cache-memory is of 2 types: 1) Primary/Processor Cache (Level1
or L1 cache)
 ➢ It is always located on the processor-chip. 2) Secondary Cache
(Level2 or L2 cache)
➢ It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM,
DIMM). The access time for main-memory is about 10 times longer
than the access time for L1cache.

9. What is cache memory? Explain different mapping functions with diagrams.

Cache Memory
It is the fast access memory located in between processor and main memory as
shown in the fig.

It is designed to reduce the access time.

The cache memory holds the copy of recently accessed data and instructions.
• The processor needs less access time to read the data and instructions from
the cache memory as compared to main memory .
• Hence by incorporating cache memory, in between processor and main
memory, itis possible to enhance the performance of the system.
• The effectiveness of cache mechanism is based on the property of “Locality of
Reference”.
Mapping functions
There are 3 techniques to map main memory blocks into cache memory –
1. Direct mapped cache
2. Associative Mapping
3. Set-Associative Mapping
DIRECT MAPPING
• The simplest way to determine cache locations in which to store memory
blocks is the direct mapping technique as shown in the figure.

• If there are 128 blocks in a cache, the block-j of the main-memory maps onto
block-jmodulo-128 of the cache . When the memory-blocks 0, 128, & 256 are
loaded into cache, the block is stored in cache-block 0. Similarly, memoryblocks
1, 129, 257 are stored in cache-block 1.(eg:1mod 128=1, 129 mod 128=1)
• The contention may arise 1) Even when the cache is full. 2) But more than one
memory-block is mapped onto a given cache-block position.
• The contention is resolved by allowing the new blocks to overwrite the
currently resident-block. Memory-address determines placement of block in the
cache.
• Cache block number= (block-j of main memory)%128;
• The main memory block is loaded into cache block by means of memory
address. The main memory address consists of 3 fields as shown in the figure.
• Each block consists of 16 words. Hence least significant 4 bits are used to
select one of the 16 words.
• If there is no match, then the block containing the required word must first be
read from the main memory main memory block has to be placed in particular
cache block number by using below formula Cache block number=main memory
block number % number of blocks present in cache memory.
2. Associative Mapping:
• It is also called as associative mapped cache. It is much more flexible.
• In this technique main memory block can be placed into any cache block
position.
• In this case , 12 tag bits are required to identify a memory block when it is
resident of the cache memory.
• The Associative Mapping technique is illustrated as shown in the fig.
• In this technique 12 bits of address generated by the processor are compared
with the tag bits of each block of the cache to see if the desired block is present.
This is called as associative mapping technique.
3. Set Associative Mapping:
• It is the combination of direct and associative mapping techniques.
• The blocks of cache are divided into several groups. Such a groups are called
as sets.
• Each set consists of number of cache blocks. A memory block is loaded into
one of the cache sets.
• The main memory address consists of three fields, as shown in the figure.
• The lower 4 bits of memory address are used to select a word from a 16
words.
• A cache consists of 64 sets as shown in the figure. Hence 6 bit set field is used
to select a cache set from 64 sets.
• As there are 64 sets, the memory is divided into groups containing 64 blocks,
where each group is given a tag number
• The following figure clearly describes the working principle of Set Associative
Mapping technique.
• If the main-memory-block is updated by a source & if the block in the source
is already exists in the cache, then the valid-bit will be cleared to “0‟. • If
Processor & DMA uses the same copies of data then it is called as Cache
Coherence Problem.

MODULE-3
1. With a neat diagram explain the basic operational concepts of computer ,
explain the registers of processor and explain the sequence of steps
 A computer consists of five functionally independent main parts:
input, memory, arithmetic and logic, output, and control units, as shown in
Figure 1.1.
  The input unit accepts coded information from human operators using
devices such as keyboards, or from other computers over digital communication
lines.
 The information received is stored in the computer‟s memory, either for
later use or to be processed immediately by the arithmetic and logic unit.
 The processing steps are specified by a program that is also stored in the
memory.
 Finally, the results are sent back to the outside world through the output unit.
 All of these actions are coordinated by the control unit.
 An interconnection network provides the means for the functional units to
exchange information and coordinate their actions.

2. Analyze Big-Endian and little-Endian methods of byte addressing with

example.
Two ways in which byte addresses can be assigned in a word

 BIG ENDIAN
 LITTLE ENDIAN ASSIGNMENT.

BIG ENDIAN ASSIGNMENT

In this technique lower byte of data is assigned to higher address of the memory and higher byte of data is
assigned to lower address of the memory.
The structure of memory to represent 32 bit number for big endian assignment is as shown in the above
figure.

LITTLE ENDIAN ASSIGNMENT

 In this technique lower byte of data is assigned to lower address of the memory and higher byte of data is
assigned to higher address of the memory.
  The structure of memory to represent 32 bit number for little endian assignment is as shown in the fig.

 Eg – store a word “JOHNSENA” in memory starting from word 1000, using Big Endian and Little endian.

4. Define instruction sequencing and branching. Explain conditional flags and

the concept of branching with an example program
INSTRUCTION EXECUTION
There are 4 steps for instruction execution
1 Fetch the instruction from memory into the Instruction Register (IR) whose
address is stored in PC. IR ← [ [PC] ]
2 Decode the instruction.
3 Perform the operation according to the opcode of an instruction
4 Load the result into the destination.
5 During this process, Increment the contents of PC to point to next instruction
( In 32 bit machine increment by 4 address) PC ← [PC] + 4.
6 The next instruction is fetched, from the address pointed by PC.
BRANCHING
Suppose a list of „N‟ numbers have to be added. Instead of adding one after the
other, the add statement can be put in a loop. The loop is a straight-line of
instructions executed as many times as needed.

The „N‟ value is copied to R1 and R1 is decremented by 1 each time in loop. In

the loop find the value of next elemet and add it with Ro. In conditional branch
instruction, the loop continues by coming out of sequence only if the condition
is true.
Here the PC value is set to „LLOP‟ if the condition is true. Branch > 0 LOOP // if
>0 go to LOOP The PC value is set to LOOP, if the previous statement value is >0
ie. after decrementing R1 value is greater than 0.
If R1 value is not greater than 0, the PC value is incremented in a normal
sequential way and the next instruction is executed.
5. What is performance measurement? Explain the overall SPEC rating.

 The performance of a Computer System is based on hardware design of the

processor and the instruction set of the processors.
 To obtain high performance of computer system it is necessary to reduce the
execution time of the processor.
 Execution time: It is defined as total time required executing one complete
program.
 The processing time of a program includes time taken to read inputs, display
outputs, system services, execution time etc.
 The performance of the processor is inversely proportional to execution time
of the processor.
More performance = Less Execution time. Less Performance = More Execution
time.
BASIC PERFORMANCE EQUATION Let „T „be total time required to execute the
program.
Let „N „be the number of instructions contained in the program.
Let „S „be the average number of steps required to one instruction.
Let „R‟ be number of clock cycles per second generated by the processor to
execute one program.
Processor Execution Time is given by T = N * S / R
This equation is called as Basic Performance Equation. For the programmer the
value of T is important.
To obtain high performance it is necessary to reduce the values of N & S and
increase the value of R Performance of a computer can also be measured by
using benchmark programs.
SPEC (System Performance Evaluation Corporation) is an non-profitable
organization, that measures performance of computer using SPEC rating.
The organization publishes the application programs and also time taken to
execute these programs in standard systems.
𝑆𝑃𝐸𝐶 = 𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑓 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 𝐶𝑜𝑚𝑝𝑢𝑡𝑒𝑟
𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑓 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 𝑢𝑛𝑑𝑒𝑟 𝑡𝑒𝑠t
6. Explain processor clock, clock rate, basic performance equation and
performance measurement
PROCESSOR CLOCK:
The processor circuits are controlled by timing signals called as Clock. It defines
constant time intervals and are called as Clock Cycles. To execute one
instruction there are 3 basic steps namely
1. Fetch
2. Decode
3. Execute.
The processor uses one clock cycle to perform one operation as shown in the
figure Clock Cycle → T1 T2 T3 Instruction →
Fetch Decode Execute The performance of the processor depends on the length
of the clock cycle. To obtain high performance reduce the length of the clock
cycle.
Let „ P ‟ be the number of clock cycles generated by the Processor and „ R „ be
the Clock rate .
The Clock rate is inversely proportional to the number of clock cycles. i.e R =
1/P. Cycles/second is measured in Hertz (Hz). Eg: 500MHz, 1.25GHz. Two ways
to increase the clock rate –  Improve the IC technology by making the logical
circuit work faster, so that the time taken for the basic steps reduces.  Reduce
the clock period, P.

BASIC PERFORMANCE EQUATION

Let „T „be total time required to execute the program. Let „N „be the number
of instructions contained in the program.
Let „S „be the average number of steps required to one instruction. Let „R‟ be
number of clock cycles per second generated by the processor to execute one
program.
Processor Execution Time is given by T = N * S / R This equation is called as Basic
Performance Equation.
7. Explain all the addressing modes with examples
The various formats of representing operand in an instruction or location of an
operand is called as “Addressing Mode”. The different types of Addressing
Modes are
a) Register Addressing
b) Direct Addressing
c) Immediate Addressing
d) Indirect Addressing
e) Index Addressing
f) Relative Addressing
g) Auto Increment Addressing
h) Auto Decrement Addressing
a. REGISTER ADDRESSING: In this mode operands are stored in the registers of
CPU. The name of the register is directly specified in the instruction. Ex: MOVE
R1,R2 Where R1 and R2 are the Source and Destination registers respectively.
This instruction transfers 32 bits of data from R1 register into R2 register. This
instruction does not refer memory for operands. The operands are directly
available in the registers.

b. DIRECT ADDRESSING It is also called as Absolute Addressing Mode. In this

addressing mode operands are stored in the memory locations. The name of the
memory location is directly specified in the instruction. Ex: MOVE LOCA, R1 :
Where LOCA is the memory location and R1 is the Register. This instruction
transfers 32 bits of data from memory location X into the General Purpose
Register R1.
 c. IMMEDIATE ADDRESSING In this Addressing Mode operands are directly
specified in the instruction. The source field is used to represent the operands.
The operands are represented by # (hash) sign. Ex: MOVE #23, R0

d. INDIRECT ADDRESSING In this Addressing Mode effective address of an

operand is stored in the memory location or General Purpose Register. The
memory locations or GPRs are used as the memory pointers. Memory pointer: It
stores the address of the memory location. There are two types Indirect
Addressing
i) Indirect through GPRs
ii) Indirect through memory location
i) Indirect Addressing Mode through GPRs In this Addressing Mode the effective
address of an operand is stored in the one of the General Purpose Register of
the CPU.
Ex: ADD (R1), R0 ; Where R1 and R0 are GPRs This instruction adds the data
from the memory location whose address is stored in R1 with the contents of R0
Register and the result is stored in R0 register as shown in the fig.
The diagrammatic representation of this addressing mode is as shown in the fig.
ii) Indirect Addressing Mode through Memory Location. In this Addressing
Mode, effective address of an operand is stored in the memory location.
Ex: ADD (X), R0 This instruction adds the data from the memory location whose
address is stored in „X‟ memory location with the contents of R0 and result is
stored in R0 register.
The diagrammatic representation of this addressing mode is as shown in the fig.

MODULE-2
1. Design a combinational circuit to convert BCD to Excess-3 or can ask any
design.
Code Conversion (Convert BCD to Excess-3 Code)
• A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code.
• Since each code uses four bits to represent a decimal digit, there must be four
input variables and four output variables. We designate the four input binary
variables by the symbols A, B, C, and D, and the four output variables by w, x, y ,
and z .
• ADD 3 to BCD to get Excess -3 Code
3. Explain carry look ahead adder circuit with block diagram
There are several techniques for reducing the carry propagation time in a
parallel adder. The most widely used technique employs the principle of carry
look ahead logic .
Carry Propagation
• Carry Propagation The addition of two binary numbers in parallel implies that
all the bits of the augend and addend are available for computation at the same
time.
• Consider the circuit of the full adder shown in Fig. 4.10 .
If we define two new binary variables.
• Gi is called a carry generate , and it produces a carry of 1 when both Ai and Bi
are 1, regardless of the input carry Ci
. • Pi is called a carry propagate , because it determines whether a carry into
stage i will propagate into stage i + 1
3b.What is a binary subtractor, explain
The addition and subtraction operations can be combined into one circuit with
one common binary adder by including an exclusive-OR gate with each full
adder.
A four-bit adder–subtractor circuit is shown in Fig. 4.13 . The mode input M
controls the operation. When M = 0, the circuit is an adder, and when M = 1, the
circuit becomes a subtractor.
Each exclusive-OR gate receives input M and one of the inputs of B. When M =
0, we have B ⊕0 = B. The full adders receive the value of B , the input carry is 0,
and the circuit performs A plus B . When M = 1, we have B ⊕ 1 = B’ and C0 = 1.
The B inputs are all complemented and a 1 is added through the input carry.
The circuit performs the operation A plus the 2’s complement of B . (The
exclusive-OR with output V is for detecting an overflow.)
Explain the full adder with the help of TT and Logic diagram
Full Adder
• A full adder is a combinational circuit that forms the arithmetic sum of three
bits. It consists of three inputs and two outputs.
• Two of the input variables, denoted by x and y , represent the two significant
bits to be added. The third input, z , represents the carry from the previous
lower significant position.
The two outputs are designated by the symbols S for sum and C for carry.

5. What is a decoder? Construct a two four line decoder with enable input
along with TT and Explain
DECODERS
• A Decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2𝑛 unique output lines.
• The decoders presented here are called n -to- m -line decoders, where m …
2𝑛 . Their purpose is to generate the 2𝑛 (or fewer) min terms of n input
variables.
• Each combination of inputs will assert a unique output. The name decoder is
also used in conjunction with other code converters, such as a BCD-to-seven-
segment decoder.
6. Define Multiplexer? Explain 8:1 mux with the help of Logic diagram and
logic expression, Also implement function F (A, B, C, D) = ϵm (1,2,5,6,9,12)
using 8:1 Mux
Multiplexer
• A multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line
• The selection of a particular input line is controlled by a set of selection lines
• normally, there are 2𝑛 input lines and n selection lines whose bit
combinations determine which input is selected.
8. Explain the operation of JK, SR T and D flip flop and Positive edge triggered
D Flip flop with Characteristic table and truth table
CHARACTERISTIC TABLES:
9.Explain the working of SR Latch using NOR gates, show how SR Latch can be
used for switch debouncing

10. Write the verilog HDL code for (i)Two to one line MUX (ii)Two to four line
decoder (iii)Full adder using half adder module