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6 Combinational Logic Gates Static Dynamic-2

Ratioed logic aims to reduce transistor count by replacing pull-up networks with single load devices, resulting in pseudo-NMOS gates with reduced robustness and higher power. Differential Cascode Voltage Switch Logic (DCVSL) improves ratioed logic by eliminating static current and providing rail-to-rail swing using differential logic and regenerative feedback. Pass transistor logic further reduces transistor count by using transistors to drive gate/source/drain terminals but introduces high impedance states.

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9 views

6 Combinational Logic Gates Static Dynamic-2

Ratioed logic aims to reduce transistor count by replacing pull-up networks with single load devices, resulting in pseudo-NMOS gates with reduced robustness and higher power. Differential Cascode Voltage Switch Logic (DCVSL) improves ratioed logic by eliminating static current and providing rail-to-rail swing using differential logic and regenerative feedback. Pass transistor logic further reduces transistor count by using transistors to drive gate/source/drain terminals but introduces high impedance states.

Uploaded by

d23134
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Book

Content
Ratioed logic
● Ratioed logic is an attempt to reduce the number of transistors
required to implement a given logic function,
– at the cost of reduced robustness and extra power dissipation.
●
The purpose of the PUN in complementary CMOS is to provide a
conditional path between VDD and the output when the PDN is
turned off.
● In ratioed logic, the entire PUN is replaced with a single
unconditional load device that pulls up the output for a high output.
●
Instead of a combination of active pull-down and pull-up networks,
such a gate consists of an NMOS pull-down network that realizes the
logic function, and a simple load device.
● Referred to as a pseudo-NMOS gate.
An example of ratioed logic
Features of the logic
● Reduced number of logic,
● Nominal output voltage is as logic 0, not 0V,
● Fight between PDU and PDN,
● Load device needs attention in terms of sizing
to achieve:
– NMH, NHL, VM, ...
● Voltage swing depends on the ratio of PDN and PUN
devices.
Governing equations
Governing equations
Governing equations
VTC
Performance matrix
NOR Logic
NAND Logic
How to build a better load?
● It is required to have a Ratioed logic which
eliminates static current and provides rail-to-rail
swing.
● Combination of two concepts:
– Differential logic
– Regenerative positive feedback

● Differential Cascode Voltage Switch Logic


(DCVSL)
DCVSL logic gate: basic principle
XOR -- XNOR
AND -- NAND
Single ended vs differential
Pass transistor: concept
● Popular and widely used alternative to the
CMOS technology,
● Reduced number of transistors,
● Driving of gate/source/drain terminals of MOS.
Example: AND logic gate
Example: AND logic gate

Eliminating High impedance state


Example: AND logic gate
Require 4 transistors in total!

Eliminating High impedance state


Silver bullet
Voltage swing of pass transistor
Golden bullet
VTC of AND gate
Complementary pass transistor
Complementary pass logic (CPL)
Complementary pass logic (CPL)
Complementary pass logic (CPL)
Solution-1: Level restoring technique
Swing restored technique
Solution-2: Usage of multiple threshold
Solution-3: Transmission gate
Rail-to-rail swing
Transmission gate based MUX
Transmission gate based XOR gate
Transmission gate resistance
Chain of transmission gates
Chain of transmission gates
Dynamic CMOS gates
Concept

● Precharge
●
Evaluation
Example

● Precharge
●
Evaluation
Properties of dynamic gates
Properties of dynamic gates
Properties of dynamic gates
Properties of dynamic gates
Properties of dynamic gates
4 input NAND gate
Static vs dynamic NOR
Issues in dynamic gates
Issues in dynamic gates
Issues in dynamic gates
Issues in dynamic gates
Issues in dynamic gates
Defining the floating nodes by strong arm
Issues in dynamic gates
Cascading dynamic gates
Issue with cascading of stages
Domino Logic
Domino logic
Dealing with non-inverting property
Differntial domino logic
Multiple domino logic
np-CMOS logic style

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