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Introduction Using gem5 gem5 devel gem5 devel Extra topics
• Getting started • General using • First SimObject, • Classic caches • Contributing to
with gem5: • gem5 models: params, events, • Ruby and SLICC gem5
using, develop, caches, CPUs, memory ops • OCN and Garnet
and simulation memory

Using gem5
• gem5 standard • Full system sim • Instruction • gem5’s GPGPU • Using other
library • Accelerating execution simulators w/
simulation • Adding an gem5
instruction
• Whatever you
want!
Running Things on gem5

A presentation by
Maryam Babaie
OOO Action Item ☺
Launch codespace and run the following commands:

cd gem5

scons build/X86/gem5.debug –j14

Table of Contents
1. Intro. to Syscall Emulation Mode

2. The m5 Utility
i. Examples on m5 Utility

ii. SE mode uses hosts for most things

3. Cross-compiling

4. Traffic Generator
Intro. to Syscall Emulation Mode
 Previously on gem5: how to build & use
Building with Scons:
scons build/{ISA}/gem5.{variant} -j {cpus}
Once compiled, gem5 can then be run using:
build/{ISA}/gem5.{variant} [gem5 options] {simulation script} [script options]

Example:
build/X86/gem5.fast --outdir=simple_out configs/learning_gem5/part1/simple.py --l1i_size=32kB

Syscall
No interaction
Emulation
with OS
Mode
 What is Syscall Emulation?

Syscall Emulation (SE) mode does not model all the devices in a system.

It focuses on simulating the CPU and memory system.

SE mode is much easier to configure.

However, SE only emulates Linux system calls, and only models user-mode code.
 When to use/avoid Syscall Emulation?

If you do not need to model the OS, and you want extra performance,
then you should use SE mode.

However, if you need high fidelity modeling of the system, or if OS interactions like
page table walks are important, then you should use FS mode.
The m5 Utility
 The m5 Utility API

“m5ops” are the special opcodes that can be used in m5 to issue special instructions.

➢ Usage: checkpointing, exiting simulation, etc.

The m5 utility is the API providing these functionalities/options.

Options include:
• exit (delay): Stop the simulation in delay nanoseconds.
• resetstats (delay, period): Reset simulation statistics in delay nanoseconds; repeat this every period nanoseconds.
• dumpstats (delay , period): Save simulation statistics to a file in delay nanoseconds; repeat this every period nanoseconds.
• dumpresetstats (delay ,period): same as dumpstats; resetstats;

• Full list of options can be found here.

 How to use the m5 utility?

It is best to insert the option(s) directly in the source code of the application.

m5ops.h header file has prototypes for all the functionalities/options must be included.

The application should be linked with the appropriate m5 & libm5.a files.

The command line utility C library for the utility.

 Building m5 and libm5

The m5 utility is in “gem5/util/m5/” directory.

To build m5 and libm5.a, run the following command in the gem5/util/m5/ directory.
scons build/{TARGET_ISA}/out/m5

Target ISA must be in lower case:

• x86
• arm
• thumb
• sparc
• arm64
• Riscv

This will generate libm5.a and m5 binaries in the util/m5/build/{TARGET_ISA}/out/ directory.

 Building m5 and libm5

Note: if you are using a x86 system for other ISAs, you need to have the cross-compiler

Cross-compiler for each target ISA:

• arm : arm-linux-gnueabihf-gcc
• thumb : arm-linux-gnueabihf-gcc
• sparc : sparc64-linux-gnu-gcc
• arm64 : aarch64-linux-gnu-gcc
• riscv : riscv64-linux-gnu-gcc

See util/m5/README.md for more details.

 Linking m5 to C/C++ code

After building the m5 and libm5.a as described, link them to your code:

1. Include gem5/m5ops.h in your source file(s).

2. Add gem5/include to your compiler’s include search path.

3. Add gem5/util/m5/build/{TARGET_ISA}/out to the linker search path.

4. Link against libm5.a.

 Example 1: print in std out
Example1 code:
materials/using-gem5/03-running/example1/se_example.cpp

Config file:
materials/using-gem5/03-running/simple.py

Commands
Compile the code: gcc materials/using-gem5/03-running/example1/se_example.cpp -o exampleBin

Run workload: ./exampleBin

Run gem5: gem5-x86 materials/using-gem5/03-running/simple.py

 Example 1

Include gem5/m5ops.h

Adding m5 util option

Adding m5 util option

Example 1: building x86 m5 utility

cd gem5/util/m5

scons build/x86/out/m5
 Example 1
Add gem5/include to your compiler’s include search path.

gcc materials/using-gem5/03-running/example1/se_example.cpp -o exampleBin

-I gem5/include/
-lm5 Link against libm5.a.
-Lgem5/util/m5/build/x86/out

Add gem5/util/m5/build/{TARGET_ISA}/out to the linker search path.

Note: if you try to locally run the output binary in your host, it will generate error:
 SE mode uses the host for many things.

SE mode treats a system call as one instruction for the guest.

Run gem5:
gem5/build/X86/gem5.debug --debug-flags=ExecAll materials/using-gem5/03-running/simple.py > debugOut.txt
 Example 2: checking a directory
Example2 code:
materials/using-gem5/03-running/example2/dir_example.cpp

Config file:
materials/using-gem5/03-running/simple.py

Commands
Compile the code: g++ materials/using-gem5/03-running/example2/dir_example.cpp -o exampleBin

Run gem5: gem5-x86 materials/using-gem5/03-running/simple.py

 SE mode uses the host for many things.
For things like creating/reading a file, it will create/read files on the host.
 SE mode deos NOT implement many things!

• Filesystem
• Most of systemcalls
• I/O devices
• Interrupts
• TLB misses → Page table walks
• Context switches
• multiple threads
You may have a multithreaded execution, but there's no context switches & no spin locks
Cross-compiling
Cross-compiling from one ISA to another.
 Example: Cross-compiling
Host = X86 → Target: ARM64
(1) Build m5 utility for arm64
cd gem5/util/m5

scons arm64.CROSS_COMPILE=aarch64-linux- build/arm64/out/m5

(2) Cross-compile the program with m5 utility

aarch64-linux-g++ materials/using-gem5/03-running/example1/se_example.cpp -o exampleBin
-I gem5/include/ -lm5 -Lgem5/util/m5/build/arm64/out -static

(3) Run gem5

gem5-arm materials/using-gem5/03-running/simple.py
 Example: Cross-compiling (Dynamic)

(1) Build m5 utility for ARM, as shown before.

(2) Cross-compile the program with m5 utility

aarch64-linux-g++ materials/using-gem5/03-running/example1/se_example.cpp -o exampleBin

-I gem5/include/ -lm5 -Lgem5/util/m5/build/arm64/out

Also, you need to let gem5 know where the libraries associated with the guest ISA are located, using “redirect”.
 Example: Cross-compiling (Dynamic)
You should modify the config file (simple.py) as follows:

(3) Run gem5

gem5-arm materials/using-gem5/03-running/simple.py
Traffic Generator in gem5
 Traffic Generator
A traffic generator module generates stimuli for the memory system.

Used for creating test cases for caches, interconnects, and memory controllers, etc.

Load/ P
CPU o Memory
Traffic Store
generator r System
LLC Data
t

Requestor Interconnect Responder

 gem5’s Traffic Gen: PyTrafficGen
PyTrafficGen is a traffic generator module (SimObject) located in:
"gem5/src/cpu/testers/traffic_gen"
Used as a black box replacement for any generator of read/write requestor.

Rd/Wr P
Req o Memory
PyTrafficGen r System
t Data

Requestor Interconnect Responder

 PyTrafficGen: Params

PyTrafficGen’s parameters allow you to control the characteristics of the generated traffic.

Parameter Definition
pattern The pattern of generated addresses: linear/ random
duration The duration of generating requests in ticks (quantum of time in gem5).
start address The lower bound for addresses that the synthetic traffic will access.
end address The upper bound for addresses that the synthetic traffic will access.
minimum period The minimum timing difference between two consecutive requests in ticks.
maximum period The maximum timing difference between two consecutive requests in ticks.
request size The number of bytes that are read/written by each request.
read percentage The percentage of reads among all the requests, the rest of requests are write requests.
 Example3: PyTrafficGen
Code: “src/mem”
Linear/Random
Memory System
Types:
Duration Rd/Wr MemCtrl, HetMemCtrl, etc
P
Rd/Wr % Req Memory Ctrlr
o Scheduling Policy
PyTrafficGen r FCFS, FRFCFS
Address Range
Data
t Memory Interface Device Type
DDRs, NVM, HBM, etc

Device Size

Command to run tests for this examples: ./materials/using-gem5/03-running/example3/traffGen_run.sh

 Summary
• SE mode is easy to configure and fast for development purposes, if OS is not involved.

• m5 utility API is a useful tool for simulation behavior and performance analysis.

• Cross compilers should be used if the host and guest ISAs are different.

• Traffic generator can abstract away the details of a data requestor such as CPU for
generating test cases for memory systems.