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Lab 2

The document describes a lab experiment to implement a half adder, full adder, and arithmetic logic unit. Code is provided to perform logical and mathematical operations on 8-bit inputs using different opcodes. Sequential code is also implemented to pass data through registers on each clock cycle. Gate-level, data flow, and behavioral models are created for a full adder.

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AbdurRehman
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7 views

Lab 2

The document describes a lab experiment to implement a half adder, full adder, and arithmetic logic unit. Code is provided to perform logical and mathematical operations on 8-bit inputs using different opcodes. Sequential code is also implemented to pass data through registers on each clock cycle. Gate-level, data flow, and behavioral models are created for a full adder.

Uploaded by

AbdurRehman
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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AIR UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

EXPERIMENT NO 2

Lab Title: Implementation of Half Adder and Full Adder and ALU

Student Name: Abdur Rehman Reg. No: 210312

Objective: To Implement Half, Full Adder and ALU

LAB ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory


Attributes (5) (4) (3) (2) (1)
Ability to Conduct
Experiment
Ability to assimilate the
results
Effective use of lab
equipment and follows
the lab safety rules

Total Marks: ________________________ Obtained Marks: _______________________

LAB REPORT ASSESSMENT:

Excellent Good Average Satisfactory Unsatisfactory


Attributes
(5) (4) (3) (2) (1)

Data presentation

Experimental results

Conclusion

Total Marks: ________________________ Obtained Marks: _______________________

Date: ______________________________ark Signature: _______________________


Arithmetic Logic Unit: Able to perform logical and mathematical operations. There are total three
inputs and one output signals. Two inputs a and b are input signals on which operation is going to
be performed according to opcode input. a and b are 8 bit wide. Opcode is 4 bit wide, so we can do
sixteen different operations.

CODE:
module ALU(
input [7:0]A,
input [7:0]B,
input [2:0]op,
output [7:0]R);
reg [7:0]R;
always @(*)
begin
case(op)
3'b000: R = (A+B);
3'b001: R = (A-B);
3'b010: R = (A & B);
3'b011: R = ~(A|B);
3'b100: R = (A|B);
3'b101: R = ~(A&B);
3'b110: R = (A^B);
3'b111: R = ~(A);
endcase
end
endmodule

TB:
module ALUtb;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg [2:0] op;
// Outputs
wire [7:0] R;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.A(A),
.B(B),
.op(op),
.R(R)
);
initial begin
// Initialize Inputs
A = 8'b11001110;
B = 8'b01100101;
op = 000;
// Wait 100 ns for global reset to finish
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 001;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 010;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 011;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 100;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 101;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 110;
#100;
A = 8'b11001110;
B = 8'b01100101;
op = 111;
// Add stimulus here
end
endmodule
Figure 1:: 3 Bits ALU
Sequential Block Code:

module task2(in1, in2, in3, in4, clk, out1, out2);


input [7:0] in1, in2, in3, in4;
input clk;
output [7:0] out1, out2;
reg [7:0] reg1, reg2, reg3, reg4;

always @(posedge clk)


begin
reg1 <= in1;
reg2 <= in2;
reg3 <= in3;
reg4 <= in4;

end

assign out1 = reg1+reg2+reg3+reg4;


assign out2 = reg1*reg2*reg3*reg4;
endmodule
Full adder
GateLevel:
Code:
module fagatelevel(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,s2,c1;
xor(s1,a,b);
and(c1,a,b);
xor(sum,s1,cin);
and(s2,s1,cin);
xor(cout,s2,c1);

endmodule
Data Flow:
Code:
module fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign {cout,sum} = a + b + cin;

endmodule
Behavioural:
Code:
module fabehaviour(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always@(*)
begin
{cout,sum} = a+b+cin;
end

endmodule
GateLevel:
RTL:
Data Flow:
RTL:
Behavioural:
RTL:
Conclusion:

In this lab we have learnt how to use XILINX and implemented code of a 3-bits ALU, made a half
and full adder, also implemented sequential block code using (+ve edge clock, -ve edge reset) and
Structural Modeling. This foundational knowledge will be crucial for future exploration in
digital system design and integrated circuit development.

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