Digital Circuits

ECE 212

Lecture 9
Sequential Circuits
Mohamed Dessouky
Integrated Circuits Laboratory
Ain Shams University
Cairo, Egypt
[email protected]

Digital Circuits – ECE212 – S24

Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

CLK

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

M. Dessouky Digital Circuits – ECE212 – S24

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 Synchronous Systems
• Digital systems = Datapath + Controller + Memory
• Datapath: Moving data through computation functional units
• Controller: Control the dataflow
• Most digital systems are synchronous systems: Use a clock
– to retime the data/control signals typically once a cycle.
– to define time reference for data movement within synchronous
systems.

M. Dessouky Digital Circuits – ECE212 – S24

Sequential Examples

• Dataflow/Datapath
– Moving data through computation functional units
– Functional units are the optimized combinational logic (CL) blocks
– Registers to demark re-synchronization.
• Controller/Finite-State Machine
– Control the dataflow
– States are stored in the registers.
– CL computes the next state as well as outputs.
• But, Why do we need clocks in digital systems??

clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

M. Dessouky Digital Circuits – ECE212 – S24

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 Timing Diagrams

D1

D2 Output Stable

• Horizontal axis indicates the time. D3 Output Stable

• Vertical axis indicates logic level.
• A single line indicates that a signal is high or low.
• A pair of lines indicate that a signal is stable but that we don’t
care about its value.
• Criss-crossed lines indicate that the signal might change at that
time.
• A pair of lines with cross-hatching indicates that the signal may
change once or more over an interval of time.

M. Dessouky Digital Circuits – ECE212 – S24

Combinational Logic (CL)

Desired
S Output
D=1
S
C=1 Y
Y
B=1 X
X
A=0 A Gate delay

time
• Combinational logic is a signal unidirectional system
• Signals (events) propagate from the inputs to the outputs
• There should be no feedback in combinational logic
• In order to obtain the desired output, all inputs must remain
stable till the output is generated.
• In general, multiple CL blocks are placed in series to perform
different operations on the input data.
M. Dessouky Digital Circuits – ECE212 – S24

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 Variable Combinational Logic Delay
Case 1: Only Q3 changes:
Q0 – Minimum Delay (Shortest Path)
D
Q1
Q3
Q2
D Output Stable
Q3
Min.
Delay

Case 2: Only Q1 changes: Case 3: All Qi changes:

– Maximum Delay (Longest/Critical Path) – Output changes between min and
max delays (Glitches)
Q1
Qi
D Output Stable
Max. Delay D Output Stable
Min.
• The delay of a combination block Delay

depends on the input data pattern. Max. Delay

M. Dessouky Digital Circuits – ECE212 – S24

CL Delay Definitions

• ‘A’ represents all inputs. Y is the output.

• Propagation delay tpd: maximum time from the input crossing
50% to the output crossing 50% of the amplitude.
• Contamination delay tcd: minimum time from the input crossing
50% to the output crossing 50% of the amplitude.
• Delay Spread tpd = tpd − tcd.

M. Dessouky Digital Circuits – ECE212 – S24

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 Propagation Delay

• If the propagation delay of the CL is constant (regardless of data

input pattern), we don’t really need clocks.
– The inherent cycle time of a state-machine will be the delay.
– It can actually be even faster for data flow.
– No synchronization overhead
• In reality, a Problem exists: Fast data ‘waves’ can catch slow
ones corrupting data

Wave arrives at t0

Data waves

M. Dessouky Digital Circuits – ECE212 – S24

Constant Delay – Clocking?

• Make the delay constant for all CL: Q0
Input signals coming from other CL
D1 D2
change at the same time that the Q1
output is generated.
Q2
• Use a register before and after CL.
Q3
• First register:
– Inputs (Qi) are applied together at the
clock edge, even if they are ready
CK
beforehand.
– Inputs (Qi) are stable during the entire
CK
clock cycle.
• Second register:
– Output (D1) needs only to be stable Qi
before the clock rising edge.
– Output (D2) appears at the clock edge D1
– D2 is the input of another CL. CL: tpd

M. Dessouky Digital Circuits – ECE212 – S24

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 Sequential Design – Data Sequencing

Data-in

Data-out

OutA is sampled by F2
InA is sampled by F1 OutA appears at Data-out, 1-cycle delayed
InB is sampled by F1

InA is processed by LOGIC to produce OutA

InB appears in Data-in

M. Dessouky Digital Circuits – ECE212 – S24

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Price to pay for Synchronization

• Cycle time is determined by the delay through the CL.

– Output must be stable before the latching edge
– If too late, it waits until the next cycle leading to a synchronization
problem.
• tcycle> tpd+ toverhead
– tpd: worst-case combinational logic delay (longest path)
– toverhead: delay overhead due to memory elements (price to pay)
• It determines the maximum clock frequency of the chip, i.e.
system speed

M. Dessouky Digital Circuits – ECE212 – S24

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 Latches versus Registers (FF)

• Latch is level sensitive • Register is edge-sensitive

• Latch is transparent when • Register (i.e flip-flop) stores
clock is: data when clock:
o high (+ve latch) o rises (+ve edge-trigger)
o low (-ve latch) o falls (-ve edge-trigger)

+ve latch

+ve edge-triggered

M. Dessouky Digital Circuits – ECE212 – S24

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Latch Realization: Mux-Based

• Positive latch
(transparent when CLK=1)
– When CLK=1, the Mux
selects the D input.
– When CLK=0, the Mux
selects the other input which
is a feedback from the output Positive latch
Q. It holds the previous
value.
• Negative latch
(transparent when CLK=0)
– Similar to the above

• Robust but large area Negative latch

M. Dessouky Digital Circuits – ECE212 – S24

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 Master-Slave (+ve Edge-Triggered) Register

• The output Q makes only one transition per cycle.

• The value of Q is the value of D right before the
rising edge of the clock, achieving the positive
edge-triggered effect

M. Dessouky Digital Circuits – ECE212 – S24

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Register Timing Diagrams

• Setup time, tsetup: time before clock edge where data must be stable.
• Hold time, thold: time after clock edge where data must remain stable.
• The hold time can be negative, i.e. the data can change even before
the clock edge.
• Clock to output propagation delay, tpcq (hold phase).
• Clock to output contamination delay, tccq (hold phase).

M. Dessouky Digital Circuits – ECE212 – S24

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 Sequencing Timing

• Ideally, the clock arrives at all FFs at the same time.

• The clock cycle time (Tc) must allow for all CL computations to
complete.
• The longest delay in the CL comes from the longest path, called
the critical path.
• If CL delay is too short, can violate the hold time of F2.

M. Dessouky Digital Circuits – ECE212 – S24

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Sequencing Timing: Design Problem

Given:
• Pre-defined Flip-Flops
• Clock speed (Tc)
• Clock non-idealities: next lecture
Design variables are:
• CL delay: tpd and tcd

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 Design Variable: tpd vs. FF Setup Time
clk clk

Q1 D2

F1

F2
Combinational Logic

Tc

tsetup
clk
tpcq

Q1 tpd

D2

CL: tpd
CL is changing

• Operation: data produced by F1 must be processed by the CL

and be ready at F2 input before the next clk edge

Tc  t pcq + t pd + t setup t pd  Tc − (t setup + t pcq )

toverhead
M. Dessouky Digital Circuits – ECE212 – S24

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Design Variable: tcd vs. FF Hold Time

clk
• If CL delay is too short,
Q1
data from Q1 can reach
F1

CL
F2 at the same clk
edge (race through). clk
• At F2, the fast data D2
F2

violates the hold time of

the previous state and
distorts stored data clk
• In order to prevent hold
tcd
time violation: Q1 tccq

thold  tccq + tcd D2 thold

or
Previous state Next state
tcd  thold − tccq
CL: tpd

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 References

• Rabaey sections 7.1, 7.2

• W&H section 7.3

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