Scribd
Upload
23 views4 pages

Ec8095 SP Talks

Uploaded by

It Me
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
23 views4 pages

Ec8095 SP Talks

Uploaded by

It Me
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

EC 8095 – VLSI DESIGN

UNIT 1
Part - A
❖ Propagation delay of a CMOS Inverter
❖ What is meant channel length modulation in NMOS transistors
❖ What is velocity saturation effect
❖ List the scaling Principles
❖ By what factor, gate capacitance must be scaled if constant electric field scaling is
employed
❖ Why nMOS transistor is selected as pull down transistor
❖ What is the need of demarcation line
❖ Why nMOS device conducts strong zero and weak one
❖ Draw the stick diagram of static CMOS 2 input NAND Gate
❖ Define Threshold voltage of MOSFET
❖ Draw the stick diagram of NMOS NOR Gate
❖ How does transmission gate produce fully restored logic output
❖ Define Low noise margin and high noise margin of a CMOS inverter

Part -B , C

❖ NAND & NOR Gate Layout Diagram


❖ Explain the DC and transfer characteristics of a CMOS Inverter
❖ Need of scaling, scaling principles and fundamental units of CMOS Inverter
❖ Equivalent RC circuit for an Inverter
❖ Dynamic behaviour of MOSFET transistor
❖ Electrical Properties of CMOS and Discuss the scaling principles and Limits
❖ State the minimum width and minimum spacing lamba based design rules to draw the
layout

UNIT 2
Part - A
❖ Elmore Constant
❖ Advantages of Transmission Gates
❖ Types of power dissipation
❖ Draw a 2 input XOR using nMOS pass transistor logic
❖ List out the sources of static and dynamic power consumption
❖ Realize X=B+C and Y=(A(B+C) using multiple output domino stages
❖ Compare Static and Dynamic power Dissipation
❖ Use of Transmission Gates
❖ List out the sources of power dissipation in CMOS Circuits

Part – B, C

❖ DCVSL Logic with suitable example


❖ Basic principle of transmission gate in CMOS Design and explain its use
❖ Draw the CMOS logic circuit for the Boolean expression Z=[A(B+C)+DE]’ &
Y=(A+BC)D+E. explain
❖ Sketch a combinational function Y=(A(B+C+D)+E.F.G)’ using Pseudo nMOS
logic, Domino logic and cascode voltage switch logic
❖ Limitations of pass transistor logic. Explain any two techniques used to overcome the
drawback of pass transistor logic design.
❖ Static CMOS XOR Gate
❖ Static & Dynamic power dissipation in CMOS circuits with necessary diagrams
and expressions
❖ Signal integrity issues in dynamic design
❖ Domino logic and low power design principles in detail
❖ Explain the pass transistor logic
❖ How dynamic voltage scaling can reduce dynamic power dissipation

UNIT 3
Part - A
❖ What is meant by pipelining?
❖ Compare and contrast synchronous design and asynchronous design
❖ Define clock skew
❖ Compare registers and latches
❖ Draw 1 transistor Dynamic RAM cell
❖ Define clock jitter
❖ What is NORA CMOS
❖ Advantages and Limitations of 3 T DRAM & 1 T DRAM
❖ List out the advantage of C2MOS logic based register over pass-transistor logic based
master slave register
❖ Compare Latch & Flip-flop
❖ Define set-up and hold time
❖ What is meant by bistability
❖ List the timing classification of Digital system
Part – B , C

❖ Operation of true single phase clocked register


❖ Explain the operation of conventional, pulsed and resettable latches
❖ CMOS register concept and design master slave triggered register, explain its
operation with overlapping periods
❖ Design a D-latch using Transmission gate, using which realize a two phase non-
overlapping master-slave negative edge triggered D Flip flop
❖ Design of sequential dynamic circuits and its pipelining concept
❖

❖ Concept of timing issues and pipelining


❖ Memory Architecture and its control circuits in detail
❖ Low power SRAM circuit
❖ Explain the timing basics and clock distribution techniques in synchronous design in
detail
❖ Analyse the impact of spatial variations of clock signal on edge triggered sequential
logic circuits
❖ Discuss the timing parameters that characterize the timing of sequential circuit

UNIT 4
Part - A
❖ List out the components of data path
❖ Give the application of high speed adder
❖ Write the full adder output interms of propagate and generate
❖ Draw the structure of 4x4 barrel shifter
❖ Define kill term, propagate and generate term in a carry look ahead adder
❖ State radix-2 booth encoding table
❖ Why is barrel shifter very useful in the designing of arithmetic circuits
❖ Write the principle of any one fast multiplier
❖ How to design a high speed adder
❖ What is latency
❖ Draw a 4 bit ripple carry adder and find its critical path delay
❖ Merits of barrel shifter
❖ Mention the different hardware architectures used for multiplier
❖ Draw the dot diagram for wallaace tree multiplier
❖ List out the categories of memory arrays
❖ Draw the circuit diagram of 1 bit binary shifter using MOS transistor
❖ Need of sense amplifier in a memory cell

Part – B , C

❖ Concept of Carry look ahead adder


❖ Discuss about speed and area trade off
❖ Concept of modified Booth multiplier
❖ Structure of ripple carry adder
❖ Design an 8 bit Brent-Kung Adder
❖ Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the
number of adders. Discuss it over Wallace multiplier.
❖ Design a 4 bit unsigned array multiplier and analyze its hardware complexity
❖ Rotate right and rotate left operations using barrel shifters
❖ List the several commonly used shifters
❖ Construct 4 x 4 array type multiplier and find its critical path delay
❖ Design 4 input and 4 output barrel shift adder using NMOS logic
❖ Building blocks of Memory architectures and memory peripheral circutary adapted to
operate for non-volatile memory
❖ Draw the NOR and NAND implementation of 4 word, 4 bit ROM

UNIT 5
Part - A
❖ What is meant by CBIC
❖ Name the elements in a configuration logic block
❖ What is the role of cell libraries in ASIC design
❖ Explain routing and its types
❖ Diff full custom and semi custom design
❖ State the three important blocks in FPGA architecture
❖ What is an antifuse, state its merits and demerits
❖ What is ULSI
❖ Compare between Xilinx CLB interconnect and Alter a LAB interconnect
❖ Common techniques of ad hoc testing
❖ Limitations of IDDQ testing
❖ Significance of field programmable gate arrays
❖ Identify the ways to optimize the manufacturability, to increase yield
❖ Diff Hard Macro & Soft Macro
❖ Flow chart of digital circuit design techniques
Part – B , C

❖ Different types of ASIC


❖ Different types of programming technology used in FFGA Design
❖ Explain CLB of Xilinx 4000 Architecture
❖ Built in self test procedure
❖ Building Block Architecture of FPGA
❖ Short notes on routing procedures involved in FPGA interconnect
❖ Main approached commonly used for design for testability(DFT)

You might also like