EC6601– VLSI Design

Unit-II: Combinational Logic

Circuits
Presented By
Dr. B. S. Sreeja,
Associate Professor, ECE Dept.
[email protected]
FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Presentation Outline
• Combinational Logic Design
– Static Logic Design
• Complementary CMOS
– Design Techniques
• Ratioed Logic
• Pass Transistor Logic
– Dynamic Logic Design
• Dynamic CMOS
– Speed and Power Analysis
– Issues – Charge Leakage, Charge Sharing,
Capacitive Coupling, Clock Feed-through
– Cascade of Dynamic CMOS – Domino Logic, np-
CMOS

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 Combinational vs. Sequential
Logic
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Output=f(in) Output=f(in, previous output)

non-regenerative circuits
circuits that have the regenerative circuits
property that at any point in the output is not only a
time, the output of the circuit function of the current input
is related to its current input data, but also of previous
signals by some Boolean values of the input signals
expression
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 Static Logic Design
• extension of the static CMOS inverter to
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

multiple inputs.
• the primary advantage of the CMOS
structure is robustness (i.e, low sensitivity
to noise), good performance, and low
power consumption with no static power
dissipation
• the design of various static circuit flavors
including complementary CMOS, ratioed
logic (pseudo-NMOS and DCVSL), and pass
transistor logic
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FDP on VLSI Design, SSNCE, Jan 4-8, 2016

– Static Logic Design

• Complementary
CMOS
– Design Techniques
• Ratioed Logic
• Pass Transistor Logic
• Transmission Gate
Logic

5
FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Static Logic Design-Complementary CMOS

static CMOS gate is a combination of two

networks, called the pull-up network (PUN)
and the pull-down network (PDN)

once the transients

have settled,
PMOS only
a path always exists
between VDD and the
output F, realizing a
high output (“one”),
or, alternatively,
NMOS only between VSS and F for
a low output (“zero”).

always a low-impedance node in

steady state 6
 Static Logic Design-Complementary CMOS

• A transistor can be thought of as a switch

FDP on VLSI Design, SSNCE, Jan 4-8, 2016

controlled by its gate signal

• “strong zeros,”-NMOS-PDN
• “strong ones,”-PMOS-PUN

Threshold drops

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 Static Logic Design-Complementary CMOS
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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 Static Logic Design-Complementary CMOS
PMOS Transistors in Series/Parallel Connection
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PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0 9

 Static Logic Design-Complementary CMOS
Complementary CMOS Logic Style
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 Static Logic Design-Complementary CMOS
Example Gate: NAND
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FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Static Logic Design-Complementary CMOS

Example Gate: NOR

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 Static Logic Design-Complementary CMOS
Complex CMOS Gate
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B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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 Static Logic Design-Complementary CMOS
Constructing a Complex Gate
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VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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 Static Logic Design-Complementary CMOS
Cell Design
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• Standard Cells
– General purpose logic
– Can be synthesized
– Same height, varying width
• Datapath Cells
– For regular, structured designs
(arithmetic)
– Includes some wiring in the cell
– Fixed height and width

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 Static Logic Design-Complementary CMOS
Standard Cell Layout
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Methodology – 1980s
Routing
channel
VDD

signals

GND

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 Static Logic Design-Complementary CMOS
Standard Cell Layout
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Methodology – 1990s
Mirrored Cell

No Routing VDD
channels
VDD

M2

M3
GND

Mirrored Cell GND

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 Static Logic Design-Complementary CMOS
Standard Cells
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N Well
VDD Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch =
repetitive distance between objects

Cell height is “12 pitch”

Out
In
2

Rails ~10
GND
Cell boundary

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 Static Logic Design-Complementary CMOS
Standard Cells
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With minimal VDD With silicided VDD

diffusion diffusion
routing

VDD

M2
Out In Out
In
In Out

M1

GND GND

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 Static Logic Design-Complementary CMOS
Standard Cells
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD 2-input NAND gate

VDD

B
A B

Out
A

GND

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 Static Logic Design-Complementary CMOS
Stick Diagrams
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Contains no dimensions
Represents relative positions of transistors

VDD VDD

Inverter
NAND2

Out Out

In A B
GND GND

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 Static Logic Design-Complementary CMOS
Stick Diagrams
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A
j C Logic Graph X PUN
B
C

C X i VDD
X = C • (A + B)
i
A
A B B B j A
C
PDN
Systematic approach to derive order of input signal GND
wires so gate can be laid out to minimize area

Note PUN and PDN are duals (parallel <-> series)

Vertices are nodes (signals) of circuit, VDD, X, GND
and edges are transitions 22
 Static Logic Design-Complementary CMOS

Two Versions of C • (A + B)
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A C B A B C

VDD VDD

X X

GND GND

Line of diffusion layout – abutting source-drain

connections

Note crossover eliminated by A B C ordering 23

FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Static Logic Design-Complementary CMOS

Consistent Euler Path

A path through all nodes in the graph
such that each edge is visited once and X
only once.
The sequence of signals on the path is C
the signal ordering for the inputs.
PUN and PDN Euler paths are (must i VDD
be) consistent (same sequence) X
If you can define a Euler path then you
can generate a layout with no diffusion B j A
breaks
ABC
CAB GND A B C
B C A  no PDN
BAC
A C B -> no PDN
CBA 24
 Static Logic Design-Complementary CMOS
OAI22 Logic Graph
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X PUN
A C

B D D C

X VDD
X = (A+B)•(C+D)

C D
B A

A B PDN
A GND
B
C
D

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 Static Logic Design-Complementary CMOS
Example: x = ab+cd
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x x

b c b c

x VDD x VD D

a d a d

GND GND

(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}

VD D

GND
a b c d
(c) stick diagram for ordering {a b c d}

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 Static Logic Design-Complementary CMOS
Multi-Fingered Transistors
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One finger Two fingers (folded)

Less diffusion capacitance

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 Static Logic Design-Complementary CMOS
Properties of Complementary
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CMOS Gates Snapshot

High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)

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 Static Logic Design-Complementary CMOS
CMOS Properties
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• Full rail-to-rail swing; high noise margins

• Logic levels not dependent upon the
relative device sizes; ratioless
• Always a path to Vdd or Gnd in steady
state; low output impedance
• Extremely high input resistance; nearly
zero steady-state input current
• No direct path steady state between
power and ground; no static power
dissipation
• Propagation delay function of load
capacitance and resistance of transistors
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 Static Logic Design-Complementary CMOS
Switch Delay Model
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capacitance on
A Req the internal
A node – due to
the source grain
Rp of the two fets in
Rp Rp series and the
B overlap gate
A B Rp
capacitances of
A Rp Cint the two fets in
Rn CL A series
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

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 Static Logic Design-Complementary CMOS
Input Pattern Effects on Delay
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• Delay is dependent
Rp Rp on the pattern of
A B inputs
• Low to high transition
Rn CL – both inputs go low
B • delay is 0.69 Rp/2 CL
– one input goes low
Rn
Cint • delay is 0.69 Rp CL
A
• High to low transition
– both inputs go high
• delay is 0.69 2Rn CL
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 Static Logic Design-Complementary CMOS
Delay Dependence on Input
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

3
Patterns
Input Data Delay
2.5 A=B=10
Pattern (psec)
2 A=B=01 67
A=1 0, B=1
A=1, B=01 64
Voltage [V]

1.5

1
A=1, B=10 A= 01, B=1 61

0.5 A=B=10 45

0 A=1, B=10 80
0 100 200 300 400 A= 10, B=1 81
-0.5
time [ps] NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
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 Static Logic Design-Complementary CMOS
Transistor Sizing
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Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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 Static Logic Design-Complementary CMOS
Transistor Sizing a Complex
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CMOS Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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 Static Logic Design-Complementary CMOS
Fan-In Considerations
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A B C D

A CL Distributed RC model
(Elmore delay)
B C3
C tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C2
D C1 Propagation delay deteriorates rapidly as
a function of fan-in – quadratically in the
worst case.

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 Static Logic Design-Complementary CMOS
tp as a Function of Fan-In
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1250
quadratic
1000
Gates with a
750 fan-in greater
tp (psec)

tpH than 4 should

tp
500 be avoided.
L

250 tpL
H linear
0
2 4 6 8 10 12 14 16
fan-in

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 Static Logic Design-Complementary CMOS
tp as a Function of Fan-Out
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

All gates have

tpNOR2 tpNAND2 the same drive
current.

tpINV
tp (psec)

Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out

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 Static Logic Design-Complementary CMOS
tp as a Function of Fan-In and
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Fan-Out
• Fan-in: quadratic due to increasing
resistance and capacitance
• Fan-out: each additional fan-out gate
adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

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 Static Logic Design-Complementary CMOS
Fast Complex Gates:
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Design Technique 1
• Transistor sizing
– as long as fan-out capacitance
dominates
• Progressive sizingDistributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
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 Static Logic Design-Complementary CMOS
Fast Complex Gates:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Design Technique 2
• Transistor ordering

critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

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 Static Logic Design-Complementary CMOS
Fast Complex Gates:
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Design Technique 3
• Alternative logic structures
F = ABCDEFGH

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 Static Logic Design-Complementary CMOS
Fast Complex Gates:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Design Technique 4
• Isolating fan-in from fan-out using
buffer insertion

CL CL

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 Static Logic Design-Complementary CMOS
Fast Complex Gates:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Design Technique 5
• Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

– linear reduction in delay

– also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on
the receiving end to restore the signal
level (memory design)
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 Static Logic Design-Complementary CMOS
Sizing Logic Paths for Speed
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• Frequently, input capacitance of a logic

path is constrained
• Logic also has to drive some capacitance
• Example: ALU load in an Intel’s
microprocessor is 0.5pF
• How do we size the ALU datapath to
achieve maximum speed?
• We have already solved this for the
inverter chain – can we generalize it for
any type of logic?

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 Static Logic Design-Complementary CMOS
Buffer Example
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In Out

1 2 N CL

N
Delay    pi  g i  f i  (in units of inv)
i 1

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?

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 Static Logic Design-Complementary CMOS
Logical Effort
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 CL 
Delay  k  Runit Cunit 1  
 Cin 
 p  g  f 
p – intrinsic delay (3kRunitCunit) - gate parameter  f(W)
g – logical effort (kRunitCunit) – gate parameter  f(W)
f – effective fanout

Normalize everything to an inverter:

ginv =1, pinv = 1

Divide everything by inv

(everything is measured in unit delays inv)
Assume = 1.

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 Static Logic Design-Complementary CMOS
Delay in a Logic Gate
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Gate delay:

d=h+p

effort delay intrinsic delay

Effort delay:

h=gf

logical effort effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizing

Effective fanout (electrical effort) is a function of load/gate size
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 Static Logic Design-Complementary CMOS
Logical Effort
• Inverter has the smallest logical effort and
intrinsic delay of all static CMOS gates
• Logical effort of a gate presents the ratio
of its input capacitance to the inverter
capacitance when sized to deliver the
same current
• Logical effort increases with the gate
complexity

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 Static Logic Design-Complementary CMOS
Logical Effort
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Logical effort is the ratio of input capacitance of a gate to the input

capacitance of an inverter with the same output current
VDD VDD VDD

A 2 A 2 B 2 B 4

F
F
A 4
A 2
A 1 F

A 1 B 1
B 2

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

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 Static Logic Design-Complementary CMOS
Logical Effort of Gates
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Normalized delay (d)

t pNAND
g= t pINV
p=
d=
g=
p=
d=

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

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 Static Logic Design-Complementary CMOS
Logical Effort of Gates
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Normalized delay (d)

t pNAND
g = 4/3 t pINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1

F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)

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 Static Logic Design-Complementary CMOS
Logical Effort of Gates
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

2
=
p
3;
4/
5 1

=
p=

g
Normalized Delay

D:
1;

AN
4 =
: g
N ter
ut
e r
p

3 v
in

In Effort
2-

Delay
2

1
Intrinsic
Delay

1 2 3 4 5
Fanout f
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 Static Logic Design-Complementary CMOS
Add Branching Effort
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Branching effort:

Con  path  Coff  path

b
Con  path

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 Static Logic Design-Complementary CMOS
Multistage Networks
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N
Delay    pi  g i  f i 
i 1

Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB

Path delay D = di = pi + hi

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 Static Logic Design-Complementary CMOS
Optimum Effort per Stage
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When each stage bears the same effort:

hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN

Effective fanout of each stage: fi  h gi

Minimum path delay

Dˆ    g i f i  pi   NH 1/ N  P

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 Static Logic Design-Complementary CMOS
Optimal Number of Stages
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For a given load,

and given input capacitance of the first gate
Find optimal number of stages and optimal sizing

D  NH 1/ N  Npinv
D
N
 
  H 1/ N ln H 1/ N  H 1/ N  pinv  0

Substitute ‘best stage effort’ hH 1 / Nˆ

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 Static Logic Design-Complementary CMOS
Logical Effort
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

From Sutherland, Sproull

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 Static Logic Design-Complementary CMOS
Example: Optimize Path
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1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F =
G=
H=
h=
a=
b=

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 Static Logic Design-Complementary CMOS
Example: Optimize Path
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59

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 Static Logic Design-Complementary CMOS
Example: Optimize Path
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

1 b c
a 5

g1 = 1 g2 = 5/3 g3 = 5/3 g4 = 1

Effective fanout, H = 5
G = 25/9
F = 125/9 = 13.9
f = 1.93
a = 1.93
b = fa/g2 = 2.23
c = fb/g3 = 5g4/f = 2.59

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 Static Logic Design-Complementary CMOS
Example – 8-input AND
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 Static Logic Design-Complementary CMOS
Method of Logical Effort
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• Compute the path effort: F = GBH

• Find the best number of stages N ~ log4F
• Compute the stage effort f = F1/N
• Sketch the path with this number of
stages
• Work either from either end, find sizes:
Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann

1999.

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 Static Logic Design-Complementary CMOS
Summary
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Sutherland,
Sproull
Harris

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FDP on VLSI Design, SSNCE, Jan 4-8, 2016

– Static Logic Design

• Complementary
CMOS
– Design Techniques
• Ratioed Logic
• Pass Transistor Logic
• Transmission Gate
Logic

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FDP on VLSI Design, SSNCE, Jan 4-8, 2016
Static Logic Design-Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

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 Static Logic Design-Ratioed Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD

• N transistors + Load
Resistive
Load • VOH = V DD
RL

• VOL = RPN
F RPN + RL

In1 • Assymetrical response

In2 PDN
In3 • Static power consumption

• tpL= 0.69 RLCL

VSS

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 Static Logic Design-Ratioed Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD
Active Loads VDD

Depletion PMOS
Load VT < 0 Load
VSS
F F
In1 In1
In2 PDN In2 PDN
In3 In3

VSS VSS

depletion load NMOS pseudo-NMOS

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FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Static Logic Design-Ratioed Logic

Pseudo-NMOS
VDD

F
CL
A B C D

VOH = VDD (similar to complementary CMOS)

2
 V OL  kp 2
k  V – V V – -------------  = ------  V – V 
n DD Tn OL DD Tp
 2  2

kp
V OL =  VDD – V T  1 – 1 – ------ (assuming that V T = V Tn = VTp )
k
n

SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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FDP on VLSI Design, SSNCE, Jan 4-8, 2016 Static Logic Design-Ratioed Logic
Pseudo-NMOS VTC
3.0

2.5

2.0 W/Lp = 4

1.5
Vou t [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

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 Static Logic Design-Ratioed Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Improved Loads
VDD

M1 M1 >> M2
Enable M2

CL
A B C D

Adaptive Load
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 Static Logic Design-Ratioed Logic
Improved Loads (2)
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD VDD

M1 M2

Out Out

A
A PDN1 PDN2
B
B

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

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FDP on VLSI Design, SSNCE, Jan 4-8, 2016
Static Logic Design-Ratioed Logic
DCVSL Example

Out

Out

B B B B

A A

XOR-NXOR gate

72
 Static Logic Design-Ratioed Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

DCVSL Transient Response

2.5

AB
V ol ta ge [V]

1.5
AB
A, B
0.5 A,B

-0.5 0 0.2 0.4 0.6 0.8 1.0

Time [ns]

73
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

– Static Logic Design

• Complementary
CMOS
– Design Techniques
• Ratioed Logic
• Pass Transistor Logic
• Transmission Gate
Logic

74
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Switch Out A
Out
Inputs

Network B
B

• N transistors
• No static consumption

75
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Example: AND Gate

B

A
B
F = AB

76
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

NMOS-Only Logic
3.0
In
In
1.5 m/0.25 m Out
2.0

Voltage [V]
VD D x x
Out
0.5  m/0.25 m
0.5 m/0.25 m 1.0

0.0
0 0.5 1 1.5 2
Time [ns]

77
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

NMOS-only Switch
C = 2.5V C = 2.5 V
M2
A = 2.5 V A = 2.5 V B
Mn
B
CL M1

VB does not pull up to 2.5V, but 2.5V - VTN

Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
78
 Static Logic Design-Pass-Transistor
Logic
NMOS Only Logic:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Level Restoring
V
Transistor
DD
VDD
Level Restorer
Mr
B
M2
X
A Mn Out
M1

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
79
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Restorer Sizing
3.0
•Upper limit on restorer size
•Pass-transistor pull-down
2.0 can have several transistors in
V olta ge [V]

W /Lr =1.75/0.25
stack
W /L r =1.50/0.25

1.0

W/ Lr =1.0/0.25 W /L r =1.25/0.25

0.0
0 100 200 300 400 500
Time [ps]

80
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Solution 2: Single Transistor Pass

Gate
V DD
with VT=0
VDD
0V 2.5V

VDD 0V Out

2.5V

WATCH OUT FOR LEAKAGE CURRENTS

81
 Static Logic Design-Pass-Transistor
Logic
Complementary Pass Transistor
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Logic
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network

B B B B B B

A A A

B F=AB B F=A+B A F=AÝ

A A A
(b)

B F=AB B F=A+B A F=AÝ

EXOR/NEXOR
AND/NAND OR/NOR 82
 Static Logic Design-Pass-Transistor
Logic
Solution 3: Transmission Gate
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

C
C

A B A B

C
C

C = 2.5 V
A = 2.5 V
B
CL
C=0V

83
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Resistance of Transmission Gate

30

2.5 V
Rn Rn
Resistance, ohms

20 Rp
2.5 V Vou t

Rp
0V
10
R n || R p

0
0.0 1.0 2.0
Vou t , V

84
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Pass-Transistor Based Multiplexer

S S
VDD

V DD
S

A
M2

S F

M1
B

GND
In1 S S In2

85
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Transmission Gate XOR

B

B
M2

A
A
F
M1 M3/M4
B

86
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Delay in Transmission Gate Networks

2.5 2.5 2.5 2.5
V1 Vi-1 Vi Vi+1 Vn-1 Vn
In

C C C C C
0 0 0 0

(a)

Req Req Req Req

V1 Vi Vi+1 Vn-1 Vn
In

C C C C C

(b)
m

Req Req Req Req Req Req

In
C CC C C CC C

(c)

87
 Static Logic Design-Pass-Transistor
Logic
Delay Optimization
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

88
 Static Logic Design-Pass-Transistor
Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Transmission Gate Full Adder

P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci

A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P

Similar delays for sum and carry

89
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Dynamic Logic Design

Dynamic CMOS
Speed and Power
Analysis
Issues – Charge Leakage,
Charge Sharing,
Capacitive Coupling,
Clock Feed-through
Cascade of Dynamic
CMOS – Domino Logic,
np-CMOS

90
 Dynamic Logic Design
Dynamic CMOS
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

• In static circuits at every point in time

(except when switching) the output is
connected to either GND or VDD via a low
resistance path.
– fan-in of n requires 2n (n N-type + n P-type)
devices

• Dynamic circuits rely on the temporary

storage of signal values on the
capacitance of high impedance nodes.
– requires on n + 2 (n+1 N-type + 1 P-type)
transistors
91
 Dynamic Logic Design
Dynamic Gate
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk Mp Clk Mp
Out Out
In1 CL
A
In2 PDN
C
In3
B
Clk Me
Clk Me

Two phase operation

Precharge (CLK = 0)
Evaluate (CLK = 1)

92
 Dynamic Logic Design
Dynamic Gate
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

93
 Dynamic Logic Design
Conditions on Output
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

• Once the output of a dynamic gate is

discharged, it cannot be charged again
until the next precharge operation.
• Inputs to the gate can make at most one
transition during evaluation.

• Output can be in the high impedance state

during and after evaluation (PDN off),
state is stored on CL

94
 Dynamic Logic Design
Properties of Dynamic Gates
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

• Logic function is implemented by the PDN only

– number of transistors is N + 2 (versus 2N for static
complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not
affect the logic levels
• Faster switching speeds
– reduced load capacitance due to lower input capacitance (Cin)
– reduced load capacitance due to smaller output loading
(Cout)
– no Isc, so all the current provided by PDN goes into
discharging CL

95
 Dynamic Logic Design
FDP on VLSI Design, SSNCE, Jan 4-8, 2016
Properties of Dynamic Gates
• Overall power dissipation usually higher
than static CMOS
– no static current path ever exists between VDD
and GND (including Psc)
– no glitching
– higher transition probabilities
– extra load on Clk
• PDN starts to work as soon as the input
signals exceed VTn, so VM, VIH and VIL equal
to VTn
– low noise margin (NML)
• Needs a precharge/evaluate clock
96
 Dynamic Logic Design
FDP on VLSI Design, SSNCE, Jan 4-8, 2016
Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

97
 Dynamic Logic Design
Solution to Charge Leakage
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

98
 Dynamic Logic Design
Issues in Dynamic Design 2:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Charge Sharing
Charge stored originally on CL is
Clk redistributed (shared) over CL and
Mp
Out CA leading to reduced robustness
A CL

B=0 CA

Clk Me CB

99
 Dynamic Logic Design
Charge Sharing Example
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk
Out
A A CL=50fF

Ca=15fF B B B !B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

100
 Dynamic Logic Design
Charge Sharing
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD
case 1) if V out < VTn

Clk Mp
Out C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
or
CL
A Ma Ca
 V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
X CL

Ca
B0 Mb case 2) if V out > VTn
C
 ---------------------
a -
Vout = –V DD 
Ca + CL 
Cb
Clk Me  

101
 Dynamic Logic Design
Solution to Charge
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Redistribution
Clk Mp Mkp Clk
Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor (at the

cost of increased area and power)

102
 Dynamic Logic Design
Issues in Dynamic Design 3:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Backgate Coupling

Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

103
 Dynamic Logic Design
Backgate Coupling Effect
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

2
Out1
1
Clk

0
In Out2

-1
0 2 Time, ns 4 6

104
 Dynamic Logic Design
Issues in Dynamic Design 4:
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clock Feedthrough
Coupling between Out and Clk
Clk input of the precharge device due
Mp
Out to the gate to drain capacitance.
So voltage of Out can rise above
A CL VDD. The fast rising (and falling
edges) of the clock couple to Out.
B

Clk Me

105
 Dynamic Logic Design
Clock Feedthrough
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clock feedthrough
Clk
Out 2.5
In1
In2 1.5

In3 In &
0.5 Clk
In4 Out
Clk -0.5
0 0.5 Time, ns 1

Clock feedthrough

106
 Dynamic Logic Design
Other Effects
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

107
 Dynamic Logic Design
Cascading Dynamic Gates
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0  1 transitions allowed at inputs!

108
 Dynamic Logic Design
Domino Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

109
 Dynamic Logic Design
Why Domino?
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

110
 Dynamic Logic Design
Properties of Domino Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

• Only non-inverting logic can be

implemented
• Very high speed
– static inverter can be skewed, only L-H
transition
– Input capacitance reduced – smaller logical
effort

111
 Dynamic Logic Design
Designing with Domino Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD VDD
VDD

Clk Mp Clk Mp Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!

Clk Me Clk Me

Inputs = 0
during precharge

112
 Dynamic Logic Design
Footless Domino
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

VDD VDD VDD

Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0 1 0 1 0

The first gate in the chain needs a foot switch

Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage

113
 Dynamic Logic Design
Differential (Dual Rail) Domino
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B

Clk Me

Solves the problem of non-inverting logic

114
 Dynamic Logic Design
np-CMOS
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

Only 0  1 transitions allowed at inputs of PDN Only 1

 0 transitions allowed at inputs of PUN

115
 Dynamic Logic Design
NORA Logic
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDN’s PUN’s

WARNING: Very sensitive to noise!

116
FDP on VLSI Design, SSNCE, Jan 4-8, 2016

Thank You